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Fix target register false dependency of lzcnt, tzcnt, and popcnt #19772
This raises an important question about optimizing for one class of targets while potentially penalizing another class.
I think it's important to minimize, to the extent possible, the matrix of supported targets. We are already down a relatively costly path of supporting a large number of target ISA's, and I think we must be extremely careful before broadening it further.
In a case like this, where we can avoid a significant penalty on one class of targets by adding a very small penalty on another class, I think that's the right tradeoff. There may be cases where the cost of the mitigation is higher, and at that point we may want to consider whether it's worth broadening the target matrix to address it, but for this case it seems pretty low cost.
@dotnet/jit-contrib - Any other opinions?
IMHO @CarolEidt is right that this particular issue is most probably not worth expanding codegen target matrix, however, it may be inevitable in future once we expand optimizations in tier1 or perhaps add even higher optimization tiers. The areas where this may have large performance impact which could depend on targeted processor type are optimizations exploiting instruction level parallelism which heavily relies on given processor type i.e. Arm53 and Arm72 will have different instruction latencies and throughputs despite implementing the same ISA.