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Arm64: Add S.P.CoreLib instrinsics ZipLow and ZipHigh #27730

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merged 1 commit into from Nov 8, 2019

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@TamarChristinaArm
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TamarChristinaArm commented Nov 7, 2019

This implements the ZipLow and ZipHigh intrinsics for Arm64.

These are general permutation intrinsics operating on pairs of vectors.

See dotnet/corefx#42176 and is split of #26769
CoreFX reference assembly update at dotnet/corefx#42440

/CC @tannergooding @CarolEidt @echesakovMSFT

Thanks,
Tamar

/// uint8x8_t vzip2_u8(uint8x8_t a, uint8x8_t b)
/// A64: ZIP2 Vd.8B, Vn.8B, Vm.8B
/// </summary>
public static Vector64<byte> ZipHigh(Vector64<byte> left, Vector64<byte> right) { throw new PlatformNotSupportedException(); }

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tannergooding Nov 7, 2019

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It looks like ARM32 has VZIP, how does it differ from ZIP1/ZIP2 exposed on ARM64?

Reading, it looks like ZIP1 gets the lower interleaved elements and ZIP2 gets the upper interleaved elements.

It looks like VZIP does the same, but in a single instruction and reuses the two input registers, is that correct?

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TamarChristinaArm Nov 7, 2019

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Yeah that's correct, on VZIP both registers are destructive, so to get the same behaviour one of the arguments has to to be duplicated before the call to preserve the original value.

I wasn't quite sure how to handle this so in the design proposal I had separated them out and had them treated them as we did in the C compiler as different intrinsics.

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echesakovMSFT commented Nov 8, 2019

/azp run coreclr-ci

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@echesakovMSFT echesakovMSFT merged commit 6912d5f into dotnet:master Nov 8, 2019
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Dotnet-GitSync-Bot pushed a commit to Dotnet-GitSync-Bot/corefx that referenced this pull request Nov 8, 2019
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@TamarChristinaArm TamarChristinaArm deleted the TamarChristinaArm:implement-arm64-zip branch Nov 11, 2019
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