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[RISC-V] Replace rsGetRsvdReg with ordinary temp registers (#95317)
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* [RISC-V] Replace rsGetRsvdReg calls in emitInsTernary with ordinary temps

* [RISC-V] Give emitInsTernary a haircut

* [RISC-V] Add missing newline when printf is exceeds MAX_LEN

* [RISC-V] Replace rsGetRsvdReg with a normal constant in genLcLHeap. Plus a small optimization, fuse addi+and into andi to avoid using a temp reg.

* [RISC-V] Replace rsGetRsvdReg with ordinary temp regs in GT_(MOD|DIV|MULHI)

* [RISC-V] Replace rsGetRsvdReg with ordinary temp reg in switch tables

* [RISC-V] Replace rsGetRsvdReg with ordinary temps in genCodeForCompare

* [RISC-V] Replace rsGetRsvdReg with ordinary temps in genCodeForShift

* [RISC-V] Replace rsGetRsvdReg with ordinary temp reg in genCodeForIndexAddr and genLeaInstruction

* [RISC-V] Replace rsGetRsvdReg with ordinary temp reg in genIntCastOverflowCheck

* [RISC-V] Code review: remove an always true if and don't enter divisor checking when we know we need a temp

* [RISC-V] Small refactorings after review
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tomeksowi committed Dec 4, 2023
1 parent 88b5e3d commit b69f79c
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Showing 4 changed files with 314 additions and 182 deletions.
8 changes: 7 additions & 1 deletion src/coreclr/jit/codegen.h
Expand Up @@ -800,7 +800,11 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
void genSetRegToCond(regNumber dstReg, GenTree* tree);

#if defined(TARGET_ARMARCH) || defined(TARGET_LOONGARCH64) || defined(TARGET_RISCV64)
void genScaledAdd(emitAttr attr, regNumber targetReg, regNumber baseReg, regNumber indexReg, int scale);
void genScaledAdd(emitAttr attr,
regNumber targetReg,
regNumber baseReg,
regNumber indexReg,
int scale RISCV64_ARG(regNumber scaleTempReg));
#endif // TARGET_ARMARCH || TARGET_LOONGARCH64 || TARGET_RISCV64

#if defined(TARGET_ARMARCH)
Expand All @@ -817,6 +821,7 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
// Generate the instruction to move a value between register files
void genBitCast(var_types targetType, regNumber targetReg, var_types srcType, regNumber srcReg);

public:
struct GenIntCastDesc
{
enum CheckKind
Expand Down Expand Up @@ -894,6 +899,7 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
}
};

protected:
void genIntCastOverflowCheck(GenTreeCast* cast, const GenIntCastDesc& desc, regNumber reg);
void genIntToIntCast(GenTreeCast* cast);
void genFloatToFloatCast(GenTree* treeNode);
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