BEGIN EXECUTION
 "D:\Sergey\git\runtime\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\corerun.exe" GitHub_24159.dll 
7
****** START compiling GitHub_24159.Test:Test2():int (MethodHash=5a8a154a)
Generating code for Windows x64
OPTIONS: compCodeOpt = BLENDED_CODE
OPTIONS: compDbgCode = false
OPTIONS: compDbgInfo = true
OPTIONS: compDbgEnC  = false
OPTIONS: compProcedureSplitting   = false
OPTIONS: compProcedureSplittingEH = false
IL to import:
IL_0000  16                ldc.i4.0    
IL_0001  80 0b 00 00 04    stsfld       0x400000B
IL_0006  12 00             ldloca.s     0x0
IL_0008  fe 15 02 00 00 02 initobj      0x2000002
IL_000e  7e 0b 00 00 04    ldsfld       0x400000B
IL_0013  2c 0a             brfalse.s    10 (IL_001f)
IL_0015  12 00             ldloca.s     0x0
IL_0017  fe 15 02 00 00 02 initobj      0x2000002
IL_001d  2b 08             br.s         8 (IL_0027)
IL_001f  12 00             ldloca.s     0x0
IL_0021  1d                ldc.i4.7    
IL_0022  7d 02 00 00 04    stfld        0x4000002
IL_0027  06                ldloc.0     
IL_0028  28 02 00 00 06    call         0x6000002
IL_002d  0b                stloc.1     
IL_002e  07                ldloc.1     
IL_002f  0c                stloc.2     
IL_0030  08                ldloc.2     
IL_0031  7b 07 00 00 04    ldfld        0x4000007
IL_0036  0d                stloc.3     
IL_0037  09                ldloc.3     
IL_0038  28 05 00 00 0a    call         0xA000005
IL_003d  09                ldloc.3     
IL_003e  1f 5d             ldc.i4.s     0x5D
IL_0040  58                add         
IL_0041  2a                ret         

lvaGrabTemp returning 4 (V04 tmp0) (a long lifetime temp) called for OutgoingArgSpace.
; Initial local variable assignments
;
;  V00 loc0           struct <GitHub_24159.Str1, 20>
;  V01 loc1           struct <GitHub_24159.Str2, 20>
;  V02 loc2           struct <GitHub_24159.Str2, 20>
;  V03 loc3              int 
;  V04 OutArgs        lclBlk <na>  "OutgoingArgSpace"
*************** In compInitDebuggingInfo() for GitHub_24159.Test:Test2():int
getVars() returned cVars = 0, extendOthers = true
info.compVarScopesCount = 4
    	VarNum 	LVNum 	      Name 	Beg 	End
 0: 	00h 	00h 	  V00 loc0 	000h   	042h
 1: 	01h 	01h 	  V01 loc1 	000h   	042h
 2: 	02h 	02h 	  V02 loc2 	000h   	042h
 3: 	03h 	03h 	  V03 loc3 	000h   	042h
info.compStmtOffsetsCount    = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for GitHub_24159.Test:Test2():int
Marked V01 as a single def local
Marked V02 as a single def local
Marked V03 as a single def local
Jump targets:
  IL_001f
  IL_0027
New Basic Block BB01 [0000] created.
BB01 [000..015)
New Basic Block BB02 [0001] created.
BB02 [015..01F)
New Basic Block BB03 [0002] created.
BB03 [01F..027)
New Basic Block BB04 [0003] created.
BB04 [027..042)
IL Code Size,Instr   66,  26, Basic Block count   4, Local Variable Num,Ref count   5, 11 for method GitHub_24159.Test:Test2():int
OPTIONS: opts.MinOpts() == false
Basic block list for 'GitHub_24159.Test:Test2():int'

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd                 weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1        [000..015)-> BB03 ( cond )                     
BB02 [0001]  1                             1        [015..01F)-> BB04 (always)                     
BB03 [0002]  1                             1        [01F..027)                                     
BB04 [0003]  2                             1        [027..042)        (return)                     
-----------------------------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Pre-import

*************** Finishing PHASE Pre-import

*************** Starting PHASE Importation
*************** In impImport() for GitHub_24159.Test:Test2():int

impImportBlockPending for BB01

Importing BB01 (PC=000) of 'GitHub_24159.Test:Test2():int'
    [ 0]   0 (0x000) ldc.i4.0 0
    [ 1]   1 (0x001) stsfld 0400000B

STMT00000 (IL 0x000...  ???)
               [000002] -A--G-------              *  ASG       int   
               [000001] ----G--N----              +--*  FIELD     int    i
               [000000] ------------              \--*  CNS_INT   int    0

    [ 0]   6 (0x006) ldloca.s 0
    [ 1]   8 (0x008) initobj 02000002

STMT00001 (IL 0x006...  ???)
               [000006] IA----------              *  ASG       struct (init)
               [000003] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
               [000005] ------------              \--*  CNS_INT   int    0

    [ 0]  14 (0x00e) ldsfld 0400000B
    [ 1]  19 (0x013) brfalse.s

STMT00002 (IL 0x00E...  ???)
               [000010] ----G-------              *  JTRUE     void  
               [000009] ----G-------              \--*  EQ        int   
               [000007] ----G-------                 +--*  FIELD     int    i
               [000008] ------------                 \--*  CNS_INT   int    0

impImportBlockPending for BB02

impImportBlockPending for BB03

Importing BB03 (PC=031) of 'GitHub_24159.Test:Test2():int'
    [ 0]  31 (0x01f) ldloca.s 0
    [ 1]  33 (0x021) ldc.i4.7 7
    [ 2]  34 (0x022) stfld 04000002

STMT00003 (IL 0x01F...  ???)
               [000015] -A----------              *  ASG       int   
               [000014] -------N----              +--*  FIELD     int    i2
               [000012] ------------              |  \--*  ADDR      byref 
               [000011] -------N----              |     \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
               [000013] ------------              \--*  CNS_INT   int    7

impImportBlockPending for BB04

Importing BB04 (PC=039) of 'GitHub_24159.Test:Test2():int'
    [ 0]  39 (0x027) ldloc.0
    [ 1]  40 (0x028) call 06000002
In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 20
Calling impNormStructVal on:
               [000016] ------------              *  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
resulting tree:
               [000019] n-----------              *  OBJ       struct<GitHub_24159.Str1, 20>
               [000018] ------------              \--*  ADDR      byref 
               [000016] -------N----                 \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         


STMT00004 (IL 0x027...  ???)
               [000017] I-C-G-------              *  CALL      struct GitHub_24159.Test.Cast (exactContextHnd=0x00007FFD8EEF68B1)
               [000019] n----------- arg0         \--*  OBJ       struct<GitHub_24159.Str1, 20>
               [000018] ------------                 \--*  ADDR      byref 
               [000016] -------N----                    \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         

    [ 1]  45 (0x02d) stloc.1

STMT00005 (IL   ???...  ???)
               [000020] --C---------              *  RET_EXPR  void  (inl return from call [000017])

    [ 0]  46 (0x02e) ldloc.1
    [ 1]  47 (0x02f) stloc.2

STMT00006 (IL 0x02E...  ???)
               [000026] -A----------              *  ASG       struct (copy)
               [000024] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V02 loc2         
               [000023] ------------              \--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V01 loc1         

    [ 0]  48 (0x030) ldloc.2
    [ 1]  49 (0x031) ldfld 04000007
    [ 1]  54 (0x036) stloc.3

STMT00007 (IL 0x030...  ???)
               [000031] -A----------              *  ASG       int   
               [000030] D------N----              +--*  LCL_VAR   int    V03 loc3         
               [000029] ------------              \--*  FIELD     int    j2
               [000028] ------------                 \--*  ADDR      byref 
               [000027] -------N----                    \--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V02 loc2         

    [ 0]  55 (0x037) ldloc.3
    [ 1]  56 (0x038) call 0A000005
In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0
INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'GitHub_24159.Test:Test2():int' calling 'System.Console:WriteLine(int)'
INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result'


STMT00008 (IL 0x037...  ???)
               [000033] --C-G-------              *  CALL      void   System.Console.WriteLine
               [000032] ------------ arg0         \--*  LCL_VAR   int    V03 loc3         

    [ 0]  61 (0x03d) ldloc.3
    [ 1]  62 (0x03e) ldc.i4.s 93
    [ 2]  64 (0x040) add
    [ 1]  65 (0x041) ret

STMT00009 (IL 0x03D...  ???)
               [000037] ------------              *  RETURN    int   
               [000036] ------------              \--*  ADD       int   
               [000034] ------------                 +--*  LCL_VAR   int    V03 loc3         
               [000035] ------------                 \--*  CNS_INT   int    93

Importing BB02 (PC=021) of 'GitHub_24159.Test:Test2():int'
    [ 0]  21 (0x015) ldloca.s 0
    [ 1]  23 (0x017) initobj 02000002

STMT00010 (IL 0x015...  ???)
               [000041] IA----------              *  ASG       struct (init)
               [000038] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
               [000040] ------------              \--*  CNS_INT   int    0

    [ 0]  29 (0x01d) br.s
impImportBlockPending for BB04

*************** Finishing PHASE Importation
Trees after Importation

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd                 weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1        [000..015)-> BB03 ( cond )                     i 
BB02 [0001]  1                             1        [015..01F)-> BB04 (always)                     i 
BB03 [0002]  1                             1        [01F..027)                                     i 
BB04 [0003]  2                             1        [027..042)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..015) -> BB03 (cond), preds={} succs={BB02,BB03}

***** BB01
STMT00000 (IL 0x000...0x001)
               [000002] -A--G-------              *  ASG       int   
               [000001] ----G--N----              +--*  FIELD     int    i
               [000000] ------------              \--*  CNS_INT   int    0

***** BB01
STMT00001 (IL 0x006...0x009)
               [000006] IA----------              *  ASG       struct (init)
               [000003] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
               [000005] ------------              \--*  CNS_INT   int    0

***** BB01
STMT00002 (IL 0x00E...0x013)
               [000010] ----G-------              *  JTRUE     void  
               [000009] ----G-------              \--*  EQ        int   
               [000007] ----G-------                 +--*  FIELD     int    i
               [000008] ------------                 \--*  CNS_INT   int    0

------------ BB02 [015..01F) -> BB04 (always), preds={} succs={BB04}

***** BB02
STMT00010 (IL 0x015...0x018)
               [000041] IA----------              *  ASG       struct (init)
               [000038] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
               [000040] ------------              \--*  CNS_INT   int    0

------------ BB03 [01F..027), preds={} succs={BB04}

***** BB03
STMT00003 (IL 0x01F...0x022)
               [000015] -A----------              *  ASG       int   
               [000014] -------N----              +--*  FIELD     int    i2
               [000012] ------------              |  \--*  ADDR      byref 
               [000011] -------N----              |     \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
               [000013] ------------              \--*  CNS_INT   int    7

------------ BB04 [027..042) (return), preds={} succs={}

***** BB04
STMT00004 (IL 0x027...0x02D)
               [000017] I-C-G-------              *  CALL      void   GitHub_24159.Test.Cast (exactContextHnd=0x00007FFD8EEF68B1)
               [000022] ------------ arg0         +--*  ADDR      byref 
               [000021] -------N----              |  \--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V01 loc1         
               [000019] n----------- arg1         \--*  OBJ       struct<GitHub_24159.Str1, 20>
               [000018] ------------                 \--*  ADDR      byref 
               [000016] -------N----                    \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         

***** BB04
STMT00005 (IL   ???...  ???)
               [000020] --C---------              *  RET_EXPR  void  (inl return from call [000017])

***** BB04
STMT00006 (IL 0x02E...0x02F)
               [000026] -A----------              *  ASG       struct (copy)
               [000024] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V02 loc2         
               [000023] ------------              \--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V01 loc1         

***** BB04
STMT00007 (IL 0x030...0x036)
               [000031] -A----------              *  ASG       int   
               [000030] D------N----              +--*  LCL_VAR   int    V03 loc3         
               [000029] ------------              \--*  FIELD     int    j2
               [000028] ------------                 \--*  ADDR      byref 
               [000027] -------N----                    \--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V02 loc2         

***** BB04
STMT00008 (IL 0x037...0x041)
               [000033] --C-G-------              *  CALL      void   System.Console.WriteLine
               [000032] ------------ arg0         \--*  LCL_VAR   int    V03 loc3         

***** BB04
STMT00009 (IL 0x03D...  ???)
               [000037] ------------              *  RETURN    int   
               [000036] ------------              \--*  ADD       int   
               [000034] ------------                 +--*  LCL_VAR   int    V03 loc3         
               [000035] ------------                 \--*  CNS_INT   int    93

-------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Indirect call transform

 -- no candidates to transform

*************** Finishing PHASE Indirect call transform [no changes]

*************** Starting PHASE Expand patchpoints

 -- no patchpoints to transform

*************** Finishing PHASE Expand patchpoints [no changes]

*************** Starting PHASE Post-import

*************** Finishing PHASE Post-import

*************** Starting PHASE Morph - Init

New BlockSet epoch 1, # of blocks (including unused BB00): 5, bitset array size: 1 (short)

*************** In fgRemoveEmptyBlocks

*************** Finishing PHASE Morph - Init
*************** In fgDebugCheckBBlist

*************** Starting PHASE Morph - Inlining
Expanding INLINE_CANDIDATE in statement STMT00004 in BB04:
STMT00004 (IL 0x027...0x02D)
               [000017] I-C-G-------              *  CALL      void   GitHub_24159.Test.Cast (exactContextHnd=0x00007FFD8EEF68B1)
               [000022] ------------ arg0         +--*  ADDR      byref 
               [000021] -------N----              |  \--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V01 loc1         
               [000019] n----------- arg1         \--*  OBJ       struct<GitHub_24159.Str1, 20>
               [000018] ------------                 \--*  ADDR      byref 
               [000016] -------N----                    \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         

Argument #0: has caller local ref
               [000019] n-----------              *  OBJ       struct<GitHub_24159.Str1, 20>
               [000018] ------------              \--*  ADDR      byref 
               [000016] -------N----                 \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         

INLINER: inlineInfo.tokenLookupContextHandle for GitHub_24159.Test:Cast(GitHub_24159.Str1):GitHub_24159.Str2 set to 0x00007FFD8EEF68B1:

Invoking compiler for the inlinee method GitHub_24159.Test:Cast(GitHub_24159.Str1):GitHub_24159.Str2 :
IL to import:
IL_0000  0f 00             ldarga.s     0x0
IL_0002  28 01 00 00 2b    call         0x2B000001
IL_0007  71 03 00 00 02    ldobj        0x2000003
IL_000c  2a                ret         

INLINER impTokenLookupContextHandle for GitHub_24159.Test:Cast(GitHub_24159.Str1):GitHub_24159.Str2 is 0x00007FFD8EEF68B1.
Notify VM instruction set (AVX) must be supported.
*************** In fgFindBasicBlocks() for GitHub_24159.Test:Cast(GitHub_24159.Str1):GitHub_24159.Str2
Jump targets:
  none
Computing inlinee profile scale:
   ... call site not profiled
New Basic Block BB05 [0004] created.
BB05 [000..00D)
Basic block list for 'GitHub_24159.Test:Cast(GitHub_24159.Str1):GitHub_24159.Str2'

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd                 weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB05 [0004]  1                             1        [000..00D)        (return)                     
-----------------------------------------------------------------------------------------------------------------------------------------

*************** Inline @[000017] Starting PHASE Pre-import

*************** Inline @[000017] Finishing PHASE Pre-import

*************** Inline @[000017] Starting PHASE Importation
*************** In impImport() for GitHub_24159.Test:Cast(GitHub_24159.Str1):GitHub_24159.Str2

impImportBlockPending for BB05

Importing BB05 (PC=000) of 'GitHub_24159.Test:Cast(GitHub_24159.Str1):GitHub_24159.Str2'
    [ 0]   0 (0x000) ldarga.s 0
lvaGrabTemp returning 5 (V05 tmp1) called for Inlining Arg.

    [ 1]   2 (0x002) call 2B000001
In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0


               [000044] I-C-G-------              *  CALL      byref  System.Runtime.CompilerServices.Unsafe.As (exactContextHnd=0x00007FFD8F02D860)
               [000043] ------------ arg0         \--*  ADDR      byref 
               [000042] -------N----                 \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V05 tmp1         

    [ 1]   7 (0x007) ldobj 02000003
    [ 1]  12 (0x00c) ret

    Inlinee Return expression (before normalization)  =>
               [000046] --CXG-------              *  OBJ       struct<GitHub_24159.Str2, 20>
               [000045] --C---------              \--*  RET_EXPR  byref (inl return from call [000044])

*************** Inline @[000017] Finishing PHASE Importation
Trees after Importation

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd                 weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB05 [0004]  1                             1        [000..00D)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB05 [000..00D) (return), preds={} succs={}

***** BB05
               [000044] I-C-G-------              *  CALL      byref  System.Runtime.CompilerServices.Unsafe.As (exactContextHnd=0x00007FFD8F02D860)
               [000043] ------------ arg0         \--*  ADDR      byref 
               [000042] -------N----                 \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V05 tmp1         

-------------------------------------------------------------------------------------------------------------------

*************** Inline @[000017] Starting PHASE Indirect call transform

 -- no candidates to transform

*************** Inline @[000017] Finishing PHASE Indirect call transform [no changes]

*************** Inline @[000017] Starting PHASE Expand patchpoints

 -- no patchpoints to transform

*************** Inline @[000017] Finishing PHASE Expand patchpoints [no changes]

*************** Inline @[000017] Starting PHASE Post-import

*************** In fgRemoveEmptyBlocks

*************** Inline @[000017] Finishing PHASE Post-import


----------- Statements (and blocks) added due to the inlining of call [000017] -----------

Arguments setup:
STMT00012 (IL 0x027...  ???)
               [000052] -A----------              *  ASG       struct (copy)
               [000050] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V05 tmp1         
               [000019] n-----------              \--*  OBJ       struct<GitHub_24159.Str1, 20>
               [000018] ------------                 \--*  ADDR      byref 
               [000016] -------N----                    \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         

Inlinee method body:
STMT00011 (IL 0x027...  ???)
               [000044] I-C-G-------              *  CALL      byref  System.Runtime.CompilerServices.Unsafe.As (exactContextHnd=0x00007FFD8F02D860)
               [000043] ------------ arg0         \--*  ADDR      byref 
               [000042] -------N----                 \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V05 tmp1         

fgInlineAppendStatements: no gc ref inline locals.

Return expression for call at [000017] is
               [000049] -ACXG-------              *  ASG       struct (copy)
               [000048] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V01 loc1         
               [000046] --CXG-------              \--*  OBJ       struct<GitHub_24159.Str2, 20>
               [000045] --C---------                 \--*  RET_EXPR  byref (inl return from call [000044])
Successfully inlined GitHub_24159.Test:Cast(GitHub_24159.Str1):GitHub_24159.Str2 (13 IL bytes) (depth 1) [below ALWAYS_INLINE size]
--------------------------------------------------------------------------------------------

INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'GitHub_24159.Test:Test2():int' calling 'GitHub_24159.Test:Cast(GitHub_24159.Str1):GitHub_24159.Str2'
INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size'
Expanding INLINE_CANDIDATE in statement STMT00011 in BB04:
STMT00011 (IL 0x027...  ???)
               [000044] I-C-G-------              *  CALL      byref  System.Runtime.CompilerServices.Unsafe.As (exactContextHnd=0x00007FFD8F02D860)
               [000043] ------------ arg0         \--*  ADDR      byref 
               [000042] -------N----                 \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V05 tmp1         

Argument #0: is a constant is byref to a struct local
               [000043] ------------              *  ADDR      byref 
               [000042] -------N----              \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V05 tmp1         

INLINER: inlineInfo.tokenLookupContextHandle for System.Runtime.CompilerServices.Unsafe:As(byref):byref set to 0x00007FFD8F02D860:

Invoking compiler for the inlinee method System.Runtime.CompilerServices.Unsafe:As(byref):byref :
IL to import:
IL_0000  02                ldarg.0     
IL_0001  2a                ret         

INLINER impTokenLookupContextHandle for System.Runtime.CompilerServices.Unsafe:As(byref):byref is 0x00007FFD8F02D860.
*************** In fgFindBasicBlocks() for System.Runtime.CompilerServices.Unsafe:As(byref):byref
Jump targets:
  none
Computing inlinee profile scale:
   ... call site not profiled
New Basic Block BB06 [0005] created.
BB06 [000..002)
Basic block list for 'System.Runtime.CompilerServices.Unsafe:As(byref):byref'

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd                 weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB06 [0005]  1                             1        [000..002)        (return)                     
-----------------------------------------------------------------------------------------------------------------------------------------

*************** Inline @[000044] Starting PHASE Pre-import

*************** Inline @[000044] Finishing PHASE Pre-import

*************** Inline @[000044] Starting PHASE Importation
*************** In impImport() for System.Runtime.CompilerServices.Unsafe:As(byref):byref

impImportBlockPending for BB06

Importing BB06 (PC=000) of 'System.Runtime.CompilerServices.Unsafe:As(byref):byref'
    [ 0]   0 (0x000) ldarg.0
    [ 1]   1 (0x001) ret

    Inlinee Return expression (before normalization)  =>
               [000054] ------------              *  ADDR      byref 
               [000055] -------N----              \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V05 tmp1         

Setting lvOverlappingFields to true on V05 because of struct reinterpretation


    Inlinee Return expression (after normalization) =>
               [000054] ------------              *  ADDR      byref 
               [000055] -------N----              \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V05 tmp1         

** Note: inlinee IL was partially imported -- imported 0 of 2 bytes of method IL

*************** Inline @[000044] Finishing PHASE Importation
Trees after Importation

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd                 weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB06 [0005]  1                             1        [000..002)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB06 [000..002) (return), preds={} succs={}

-------------------------------------------------------------------------------------------------------------------

*************** Inline @[000044] Starting PHASE Indirect call transform

 -- no candidates to transform

*************** Inline @[000044] Finishing PHASE Indirect call transform [no changes]

*************** Inline @[000044] Starting PHASE Expand patchpoints

 -- no patchpoints to transform

*************** Inline @[000044] Finishing PHASE Expand patchpoints [no changes]

*************** Inline @[000044] Starting PHASE Post-import

*************** In fgRemoveEmptyBlocks

*************** Inline @[000044] Finishing PHASE Post-import


----------- Statements (and blocks) added due to the inlining of call [000044] -----------

Arguments setup:

Inlinee method body:fgInlineAppendStatements: no gc ref inline locals.

Return expression for call at [000044] is
               [000054] ------------              *  ADDR      byref 
               [000055] -------N----              \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V05 tmp1         
Successfully inlined System.Runtime.CompilerServices.Unsafe:As(byref):byref (2 IL bytes) (depth 2) [aggressive inline attribute]
--------------------------------------------------------------------------------------------

INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'GitHub_24159.Test:Test2():int' calling 'System.Runtime.CompilerServices.Unsafe:As(byref):byref'
INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute'

Replacing the return expression placeholder [000020] with [000049]
               [000020] --C---------              *  RET_EXPR  void  (inl return from call [000049])

Inserting the inline return expression
               [000049] -ACXG-------              *  ASG       struct (copy)
               [000048] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V01 loc1         
               [000046] --CXG-------              \--*  OBJ       struct<GitHub_24159.Str2, 20>
               [000045] --C---------                 \--*  RET_EXPR  byref (inl return from call [000054])


Replacing the return expression placeholder [000045] with [000054]
               [000045] --C---------              *  RET_EXPR  byref (inl return from call [000054])

Inserting the inline return expression
               [000054] ------------              *  ADDR      byref 
               [000055] -------N----              \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V05 tmp1         

**************** Inline Tree
Inlines into 06000003 GitHub_24159.Test:Test2():int
  [1 IL=0040 TR=000017 06000002] [below ALWAYS_INLINE size] GitHub_24159.Test:Cast(GitHub_24159.Str1):GitHub_24159.Str2
    [2 IL=0002 TR=000044 06000017] [aggressive inline attribute] System.Runtime.CompilerServices.Unsafe:As(byref):byref
  [0 IL=0056 TR=000033 0600007E] [FAILED: noinline per IL/cached result] System.Console:WriteLine(int)
Budget: initialTime=258, finalTime=256, initialBudget=2580, currentBudget=2580
Budget: discretionary inline caused a force inline
Budget: initialSize=1636, finalSize=1636

*************** Finishing PHASE Morph - Inlining
Trees after Morph - Inlining

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd                 weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1        [000..015)-> BB03 ( cond )                     i 
BB02 [0001]  1                             1        [015..01F)-> BB04 (always)                     i 
BB03 [0002]  1                             1        [01F..027)                                     i 
BB04 [0003]  2                             1        [027..042)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..015) -> BB03 (cond), preds={} succs={BB02,BB03}

***** BB01
STMT00000 (IL 0x000...0x001)
               [000002] -A--G-------              *  ASG       int   
               [000001] ----G--N----              +--*  FIELD     int    i
               [000000] ------------              \--*  CNS_INT   int    0

***** BB01
STMT00001 (IL 0x006...0x009)
               [000006] IA----------              *  ASG       struct (init)
               [000003] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
               [000005] ------------              \--*  CNS_INT   int    0

***** BB01
STMT00002 (IL 0x00E...0x013)
               [000010] ----G-------              *  JTRUE     void  
               [000009] ----G-------              \--*  EQ        int   
               [000007] ----G-------                 +--*  FIELD     int    i
               [000008] ------------                 \--*  CNS_INT   int    0

------------ BB02 [015..01F) -> BB04 (always), preds={} succs={BB04}

***** BB02
STMT00010 (IL 0x015...0x018)
               [000041] IA----------              *  ASG       struct (init)
               [000038] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
               [000040] ------------              \--*  CNS_INT   int    0

------------ BB03 [01F..027), preds={} succs={BB04}

***** BB03
STMT00003 (IL 0x01F...0x022)
               [000015] -A----------              *  ASG       int   
               [000014] -------N----              +--*  FIELD     int    i2
               [000012] ------------              |  \--*  ADDR      byref 
               [000011] -------N----              |     \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
               [000013] ------------              \--*  CNS_INT   int    7

------------ BB04 [027..042) (return), preds={} succs={}

***** BB04
STMT00012 (IL 0x027...  ???)
               [000052] -A----------              *  ASG       struct (copy)
               [000050] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V05 tmp1         
               [000019] n-----------              \--*  OBJ       struct<GitHub_24159.Str1, 20>
               [000018] ------------                 \--*  ADDR      byref 
               [000016] -------N----                    \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         

***** BB04
STMT00005 (IL   ???...  ???)
               [000049] -ACXG-------              *  ASG       struct (copy)
               [000048] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V01 loc1         
               [000046] --CXG-------              \--*  OBJ       struct<GitHub_24159.Str2, 20>
               [000054] ------------                 \--*  ADDR      byref 
               [000055] -------N----                    \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V05 tmp1         

***** BB04
STMT00006 (IL 0x02E...0x02F)
               [000026] -A----------              *  ASG       struct (copy)
               [000024] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V02 loc2         
               [000023] ------------              \--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V01 loc1         

***** BB04
STMT00007 (IL 0x030...0x036)
               [000031] -A----------              *  ASG       int   
               [000030] D------N----              +--*  LCL_VAR   int    V03 loc3         
               [000029] ------------              \--*  FIELD     int    j2
               [000028] ------------                 \--*  ADDR      byref 
               [000027] -------N----                    \--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V02 loc2         

***** BB04
STMT00008 (IL 0x037...0x041)
               [000033] --C-G-------              *  CALL      void   System.Console.WriteLine
               [000032] ------------ arg0         \--*  LCL_VAR   int    V03 loc3         

***** BB04
STMT00009 (IL 0x03D...  ???)
               [000037] ------------              *  RETURN    int   
               [000036] ------------              \--*  ADD       int   
               [000034] ------------                 +--*  LCL_VAR   int    V03 loc3         
               [000035] ------------                 \--*  CNS_INT   int    93

-------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Allocate Objects
no newobjs in this method; punting

*************** Finishing PHASE Allocate Objects [no changes]

*************** Starting PHASE Morph - Add internal blocks

*************** After fgAddInternal()

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd                 weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1        [000..015)-> BB03 ( cond )                     i 
BB02 [0001]  1                             1        [015..01F)-> BB04 (always)                     i 
BB03 [0002]  1                             1        [01F..027)                                     i 
BB04 [0003]  2                             1        [027..042)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty

*************** Finishing PHASE Morph - Add internal blocks

*************** Starting PHASE Remove empty try

*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.

*************** Finishing PHASE Remove empty try [no changes]

*************** Starting PHASE Remove empty finally
No EH in this method, nothing to remove.

*************** Finishing PHASE Remove empty finally [no changes]

*************** Starting PHASE Merge callfinally chains
No EH in this method, nothing to merge.

*************** Finishing PHASE Merge callfinally chains [no changes]

*************** Starting PHASE Clone finally
No EH in this method, no cloning.

*************** Finishing PHASE Clone finally [no changes]

*************** Starting PHASE Compute preds

Renumbering the basic blocks for fgComputePred

*************** Before renumbering the basic blocks

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd                 weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1        [000..015)-> BB03 ( cond )                     i 
BB02 [0001]  1                             1        [015..01F)-> BB04 (always)                     i 
BB03 [0002]  1                             1        [01F..027)                                     i 
BB04 [0003]  2                             1        [027..042)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty

*************** After renumbering the basic blocks
=============== No blocks renumbered!

New BlockSet epoch 2, # of blocks (including unused BB00): 5, bitset array size: 1 (short)

*************** In fgComputePreds()

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd                 weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1        [000..015)-> BB03 ( cond )                     i 
BB02 [0001]  1                             1        [015..01F)-> BB04 (always)                     i 
BB03 [0002]  1                             1        [01F..027)                                     i 
BB04 [0003]  2                             1        [027..042)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------


*************** After fgComputePreds()

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1        [000..015)-> BB03 ( cond )                     i label target 
BB02 [0001]  1       BB01                  1        [015..01F)-> BB04 (always)                     i 
BB03 [0002]  1       BB01                  1        [01F..027)                                     i label target 
BB04 [0003]  2       BB02,BB03             1        [027..042)        (return)                     i label target 
-----------------------------------------------------------------------------------------------------------------------------------------


*************** Finishing PHASE Compute preds

*************** Starting PHASE Merge throw blocks

*************** In fgTailMergeThrows
Method does not have multiple noreturn calls.

*************** Finishing PHASE Merge throw blocks [no changes]

*************** Starting PHASE Update flow graph early pass

*************** In fgUpdateFlowGraph()
Before updating the flow graph:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1        [000..015)-> BB03 ( cond )                     i label target 
BB02 [0001]  1       BB01                  1        [015..01F)-> BB04 (always)                     i 
BB03 [0002]  1       BB01                  1        [01F..027)                                     i label target 
BB04 [0003]  2       BB02,BB03             1        [027..042)        (return)                     i label target 
-----------------------------------------------------------------------------------------------------------------------------------------

*************** In fgDebugCheckBBlist

*************** Finishing PHASE Update flow graph early pass

*************** Starting PHASE Morph - Promote Structs

*************** In fgResetImplicitByRefRefCount()
*************** In fgPromoteStructs()

lvaTable before fgPromoteStructs
; Initial local variable assignments
;
;  V00 loc0           struct <GitHub_24159.Str1, 20> ld-addr-op
;  V01 loc1           struct <GitHub_24159.Str2, 20>
;  V02 loc2           struct <GitHub_24159.Str2, 20>
;  V03 loc3              int 
;  V04 OutArgs        lclBlk <na>  "OutgoingArgSpace"
;  V05 tmp1           struct <GitHub_24159.Str1, 20> ld-addr-op overlapping-fields "Inlining Arg"

lvaTable after fgPromoteStructs
; Initial local variable assignments
;
;  V00 loc0           struct <GitHub_24159.Str1, 20> ld-addr-op
;  V01 loc1           struct <GitHub_24159.Str2, 20>
;  V02 loc2           struct <GitHub_24159.Str2, 20>
;  V03 loc3              int 
;  V04 OutArgs        lclBlk <na>  "OutgoingArgSpace"
;  V05 tmp1           struct <GitHub_24159.Str1, 20> ld-addr-op overlapping-fields "Inlining Arg"

*************** Finishing PHASE Morph - Promote Structs

*************** Starting PHASE Morph - Structs/AddrExp

*************** In fgMarkAddressExposedLocals()
LocalAddressVisitor visiting statement:
STMT00000 (IL 0x000...0x001)
               [000002] -A--G-------              *  ASG       int   
               [000001] ----G--N----              +--*  FIELD     int    i
               [000000] ------------              \--*  CNS_INT   int    0

LocalAddressVisitor visiting statement:
STMT00001 (IL 0x006...0x009)
               [000006] IA----------              *  ASG       struct (init)
               [000003] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
               [000005] ------------              \--*  CNS_INT   int    0

LocalAddressVisitor visiting statement:
STMT00002 (IL 0x00E...0x013)
               [000010] ----G-------              *  JTRUE     void  
               [000009] ----G-------              \--*  EQ        int   
               [000007] ----G-------                 +--*  FIELD     int    i
               [000008] ------------                 \--*  CNS_INT   int    0

LocalAddressVisitor visiting statement:
STMT00010 (IL 0x015...0x018)
               [000041] IA----------              *  ASG       struct (init)
               [000038] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
               [000040] ------------              \--*  CNS_INT   int    0

LocalAddressVisitor visiting statement:
STMT00003 (IL 0x01F...0x022)
               [000015] -A----------              *  ASG       int   
               [000014] -------N----              +--*  FIELD     int    i2
               [000012] ------------              |  \--*  ADDR      byref 
               [000011] -------N----              |     \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
               [000013] ------------              \--*  CNS_INT   int    7

Local V00 should not be enregistered because: was accessed as a local field
LocalAddressVisitor modified statement:
STMT00003 (IL 0x01F...0x022)
               [000015] -A----------              *  ASG       int   
               [000014] U------N----              +--*  LCL_FLD   int    V00 loc0         [+4] Fseq[i2]
               [000013] ------------              \--*  CNS_INT   int    7

LocalAddressVisitor visiting statement:
STMT00012 (IL 0x027...  ???)
               [000052] -A----------              *  ASG       struct (copy)
               [000050] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V05 tmp1         
               [000019] n-----------              \--*  OBJ       struct<GitHub_24159.Str1, 20>
               [000018] ------------                 \--*  ADDR      byref 
               [000016] -------N----                    \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
LocalAddressVisitor modified statement:
STMT00012 (IL 0x027...  ???)
               [000052] -A----------              *  ASG       struct (copy)
               [000050] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V05 tmp1         
               [000019] ------------              \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         

LocalAddressVisitor visiting statement:
STMT00005 (IL   ???...  ???)
               [000049] -ACXG-------              *  ASG       struct (copy)
               [000048] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V01 loc1         
               [000046] --CXG-------              \--*  OBJ       struct<GitHub_24159.Str2, 20>
               [000054] ------------                 \--*  ADDR      byref 
               [000055] -------N----                    \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V05 tmp1         
LocalAddressVisitor modified statement:
STMT00005 (IL   ???...  ???)
               [000049] -ACXG-------              *  ASG       struct (copy)
               [000048] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V01 loc1         
               [000046] ------------              \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V05 tmp1         

LocalAddressVisitor visiting statement:
STMT00006 (IL 0x02E...0x02F)
               [000026] -A----------              *  ASG       struct (copy)
               [000024] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V02 loc2         
               [000023] ------------              \--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V01 loc1         

LocalAddressVisitor visiting statement:
STMT00007 (IL 0x030...0x036)
               [000031] -A----------              *  ASG       int   
               [000030] D------N----              +--*  LCL_VAR   int    V03 loc3         
               [000029] ------------              \--*  FIELD     int    j2
               [000028] ------------                 \--*  ADDR      byref 
               [000027] -------N----                    \--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V02 loc2         

Local V02 should not be enregistered because: was accessed as a local field
LocalAddressVisitor modified statement:
STMT00007 (IL 0x030...0x036)
               [000031] -A----------              *  ASG       int   
               [000030] D------N----              +--*  LCL_VAR   int    V03 loc3         
               [000029] ------------              \--*  LCL_FLD   int    V02 loc2         [+4] Fseq[j2]

LocalAddressVisitor visiting statement:
STMT00008 (IL 0x037...0x041)
               [000033] --C-G-------              *  CALL      void   System.Console.WriteLine
               [000032] ------------ arg0         \--*  LCL_VAR   int    V03 loc3         

LocalAddressVisitor visiting statement:
STMT00009 (IL 0x03D...  ???)
               [000037] ------------              *  RETURN    int   
               [000036] ------------              \--*  ADD       int   
               [000034] ------------                 +--*  LCL_VAR   int    V03 loc3         
               [000035] ------------                 \--*  CNS_INT   int    93


*************** Finishing PHASE Morph - Structs/AddrExp

*************** Starting PHASE Morph - ByRefs

*************** In fgRetypeImplicitByRefArgs()

*************** Finishing PHASE Morph - ByRefs

*************** Starting PHASE Morph - Global

*************** In fgMorphBlocks()

Morphing BB01 of 'GitHub_24159.Test:Test2():int'

fgMorphTree BB01, STMT00000 (before)
               [000002] -A--G-------              *  ASG       int   
               [000001] ----G--N----              +--*  FIELD     int    i
               [000000] ------------              \--*  CNS_INT   int    0

fgMorphTree BB01, STMT00000 (after)
               [000002] -A--G+------              *  ASG       int   
               [000001] n---G+-N----              +--*  IND       int   
               [000057] H----+------              |  \--*  CNS_INT(h) long   0x7ffd8eef4abc static Fseq[i]
               [000000] -----+------              \--*  CNS_INT   int    0

fgMorphTree BB01, STMT00001 (before)
               [000006] IA----------              *  ASG       struct (init)
               [000003] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
               [000005] ------------              \--*  CNS_INT   int    0
fgMorphBlkNode for dst tree, before:
               [000003] D----+-N----              *  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
fgMorphBlkNode after:
               [000003] D----+-N----              *  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         

fgMorphInitBlock:
Local V00 should not be enregistered because: written in a block op
GenTreeNode creates assertion:
               [000006] IA----------              *  ASG       struct (init)
In BB01 New Local Constant Assertion: V00 == 0 index=#01, mask=0000000000000001

fgMorphTree BB01, STMT00002 (before)
               [000010] ----G-------              *  JTRUE     void  
               [000009] ----G-------              \--*  EQ        int   
               [000007] ----G-------                 +--*  FIELD     int    i
               [000008] ------------                 \--*  CNS_INT   int    0

fgMorphTree BB01, STMT00002 (after)
               [000010] ----G+------              *  JTRUE     void  
               [000009] J---G+-N----              \--*  EQ        int   
               [000007] n---G+------                 +--*  IND       int   
               [000058] H----+------                 |  \--*  CNS_INT(h) long   0x7ffd8eef4abc static Fseq[i]
               [000008] -----+------                 \--*  CNS_INT   int    0

Morphing BB02 of 'GitHub_24159.Test:Test2():int'

fgMorphTree BB02, STMT00010 (before)
               [000041] IA----------              *  ASG       struct (init)
               [000038] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
               [000040] ------------              \--*  CNS_INT   int    0
fgMorphBlkNode for dst tree, before:
               [000038] D----+-N----              *  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
fgMorphBlkNode after:
               [000038] D----+-N----              *  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         

fgMorphInitBlock:
Local V00 should not be enregistered because: written in a block op
GenTreeNode creates assertion:
               [000041] IA----------              *  ASG       struct (init)
In BB02 New Local Constant Assertion: V00 == 0 index=#01, mask=0000000000000001

Morphing BB03 of 'GitHub_24159.Test:Test2():int'

fgMorphTree BB03, STMT00003 (before)
               [000015] -A----------              *  ASG       int   
               [000014] U------N----              +--*  LCL_FLD   int    V00 loc0         [+4] Fseq[i2]
               [000013] ------------              \--*  CNS_INT   int    7

Morphing BB04 of 'GitHub_24159.Test:Test2():int'

fgMorphTree BB04, STMT00012 (before)
               [000052] -A----------              *  ASG       struct (copy)
               [000050] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V05 tmp1         
               [000019] ------------              \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
fgMorphCopyBlock:
fgMorphBlkNode for dst tree, before:
               [000050] D----+-N----              *  LCL_VAR   struct<GitHub_24159.Str1, 20> V05 tmp1         
fgMorphBlkNode after:
               [000050] D----+-N----              *  LCL_VAR   struct<GitHub_24159.Str1, 20> V05 tmp1         
fgMorphBlkNode for src tree, before:
               [000019] -----+------              *  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
fgMorphBlkNode after:
               [000019] -----+------              *  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
block assignment to morph:
               [000052] -A----------              *  ASG       struct (copy)
               [000050] D----+-N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V05 tmp1         
               [000019] -----+------              \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
 with no promoted structs this requires a CopyBlock.

Local V05 should not be enregistered because: written in a block op

Local V00 should not be enregistered because: written in a block op

fgMorphCopyBlock (after):
               [000052] -A----------              *  ASG       struct (copy)
               [000050] D----+-N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V05 tmp1         
               [000019] -----+------              \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
GenTreeNode creates assertion:
               [000052] -A----------              *  ASG       struct (copy)
In BB04 New Local Copy     Assertion: V05 == V00 index=#01, mask=0000000000000001

fgMorphTree BB04, STMT00005 (before)
               [000049] -ACXG-------              *  ASG       struct (copy)
               [000048] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V01 loc1         
               [000046] ------------              \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V05 tmp1         

Assertion prop in BB04:
Copy     Assertion: V05 == V00 index=#01, mask=0000000000000001
               [000046] ------------              *  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
fgMorphCopyBlock:
fgMorphBlkNode for dst tree, before:
               [000048] D----+-N----              *  LCL_VAR   struct<GitHub_24159.Str2, 20> V01 loc1         
fgMorphBlkNode after:
               [000048] D----+-N----              *  LCL_VAR   struct<GitHub_24159.Str2, 20> V01 loc1         
fgMorphBlkNode for src tree, before:
               [000046] -----+------              *  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
fgMorphBlkNode after:
               [000046] -----+------              *  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
block assignment to morph:
               [000049] -A--G-------              *  ASG       struct (copy)
               [000048] D----+-N----              +--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V01 loc1         
               [000046] -----+------              \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
 with no promoted structs this requires a CopyBlock.

Local V01 should not be enregistered because: written in a block op

Local V00 should not be enregistered because: written in a block op

fgMorphCopyBlock (after):
               [000049] -A--G-------              *  ASG       struct (copy)
               [000048] D----+-N----              +--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V01 loc1         
               [000046] -----+------              \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
GenTreeNode creates assertion:
               [000049] -A--G-------              *  ASG       struct (copy)
In BB04 New Local Copy     Assertion: V01 == V00 index=#02, mask=0000000000000002

fgMorphTree BB04, STMT00005 (after)
               [000049] -A--G+------              *  ASG       struct (copy)
               [000048] D----+-N----              +--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V01 loc1         
               [000046] -----+------              \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         

fgMorphTree BB04, STMT00006 (before)
               [000026] -A----------              *  ASG       struct (copy)
               [000024] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V02 loc2         
               [000023] ------------              \--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V01 loc1         

Assertion prop in BB04:
Copy     Assertion: V01 == V00 index=#02, mask=0000000000000002
               [000023] ------------              *  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
fgMorphCopyBlock:
fgMorphBlkNode for dst tree, before:
               [000024] D----+-N----              *  LCL_VAR   struct<GitHub_24159.Str2, 20> V02 loc2         
fgMorphBlkNode after:
               [000024] D----+-N----              *  LCL_VAR   struct<GitHub_24159.Str2, 20> V02 loc2         
fgMorphBlkNode for src tree, before:
               [000023] -----+------              *  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
fgMorphBlkNode after:
               [000023] -----+------              *  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
block assignment to morph:
               [000026] -A----------              *  ASG       struct (copy)
               [000024] D----+-N----              +--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V02 loc2         
               [000023] -----+------              \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
 with no promoted structs this requires a CopyBlock.

Local V02 should not be enregistered because: written in a block op

Local V00 should not be enregistered because: written in a block op

fgMorphCopyBlock (after):
               [000026] -A----------              *  ASG       struct (copy)
               [000024] D----+-N----              +--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V02 loc2         
               [000023] -----+------              \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
GenTreeNode creates assertion:
               [000026] -A----------              *  ASG       struct (copy)
In BB04 New Local Copy     Assertion: V02 == V00 index=#03, mask=0000000000000004

fgMorphTree BB04, STMT00006 (after)
               [000026] -A---+------              *  ASG       struct (copy)
               [000024] D----+-N----              +--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V02 loc2         
               [000023] -----+------              \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         

fgMorphTree BB04, STMT00007 (before)
               [000031] -A----------              *  ASG       int   
               [000030] D------N----              +--*  LCL_VAR   int    V03 loc3         
               [000029] ------------              \--*  LCL_FLD   int    V02 loc2         [+4] Fseq[j2]
GenTreeNode creates assertion:
               [000031] -A----------              *  ASG       int   
In BB04 New Local Subrange Assertion: V03 in [-2147483648..2147483647] index=#04, mask=0000000000000008

fgMorphTree BB04, STMT00008 (before)
               [000033] --C-G-------              *  CALL      void   System.Console.WriteLine
               [000032] ------------ arg0         \--*  LCL_VAR   int    V03 loc3         
Initializing arg info for 33.CALL:
ArgTable for 33.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 32.LCL_VAR int (By ref), 1 reg: rcx, align=1]

Morphing args for 33.CALL:
argSlots=1, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32

Sorting the arguments:
Deferred argument ('rcx'):
               [000032] -----+------              *  LCL_VAR   int    V03 loc3         
Replaced with placeholder node:
               [000059] ----------L-              *  ARGPLACE  int   

Shuffled argument table:    rcx 
ArgTable for 33.CALL after fgMorphArgs:
fgArgTabEntry[arg 0 32.LCL_VAR int (By ref), 1 reg: rcx, align=1, lateArgInx=0, processed]


fgMorphTree BB04, STMT00008 (after)
               [000033] --CXG+------              *  CALL      void   System.Console.WriteLine
               [000032] -----+------ arg0 in rcx  \--*  LCL_VAR   int    V03 loc3         

fgMorphTree BB04, STMT00009 (before)
               [000037] ------------              *  RETURN    int   
               [000036] ------------              \--*  ADD       int   
               [000034] ------------                 +--*  LCL_VAR   int    V03 loc3         
               [000035] ------------                 \--*  CNS_INT   int    93

*************** Finishing PHASE Morph - Global
Trees after Morph - Global

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1        [000..015)-> BB03 ( cond )                     i label target 
BB02 [0001]  1       BB01                  1        [015..01F)-> BB04 (always)                     i 
BB03 [0002]  1       BB01                  1        [01F..027)                                     i label target 
BB04 [0003]  2       BB02,BB03             1        [027..042)        (return)                     i label target hascall gcsafe 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..015) -> BB03 (cond), preds={} succs={BB02,BB03}

***** BB01
STMT00000 (IL 0x000...0x001)
               [000002] -A--G+------              *  ASG       int   
               [000001] n---G+-N----              +--*  IND       int   
               [000057] H----+------              |  \--*  CNS_INT(h) long   0x7ffd8eef4abc static Fseq[i]
               [000000] -----+------              \--*  CNS_INT   int    0

***** BB01
STMT00001 (IL 0x006...0x009)
               [000006] IA---+------              *  ASG       struct (init)
               [000003] D----+-N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
               [000005] -----+------              \--*  CNS_INT   int    0

***** BB01
STMT00002 (IL 0x00E...0x013)
               [000010] ----G+------              *  JTRUE     void  
               [000009] J---G+-N----              \--*  EQ        int   
               [000007] n---G+------                 +--*  IND       int   
               [000058] H----+------                 |  \--*  CNS_INT(h) long   0x7ffd8eef4abc static Fseq[i]
               [000008] -----+------                 \--*  CNS_INT   int    0

------------ BB02 [015..01F) -> BB04 (always), preds={BB01} succs={BB04}

***** BB02
STMT00010 (IL 0x015...0x018)
               [000041] IA---+------              *  ASG       struct (init)
               [000038] D----+-N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
               [000040] -----+------              \--*  CNS_INT   int    0

------------ BB03 [01F..027), preds={BB01} succs={BB04}

***** BB03
STMT00003 (IL 0x01F...0x022)
               [000015] -A---+------              *  ASG       int   
               [000014] U----+-N----              +--*  LCL_FLD   int    V00 loc0         [+4] Fseq[i2]
               [000013] -----+------              \--*  CNS_INT   int    7

------------ BB04 [027..042) (return), preds={BB02,BB03} succs={}

***** BB04
STMT00012 (IL 0x027...  ???)
               [000052] -A---+------              *  ASG       struct (copy)
               [000050] D----+-N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V05 tmp1         
               [000019] -----+------              \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         

***** BB04
STMT00005 (IL   ???...  ???)
               [000049] -A--G+------              *  ASG       struct (copy)
               [000048] D----+-N----              +--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V01 loc1         
               [000046] -----+------              \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         

***** BB04
STMT00006 (IL 0x02E...0x02F)
               [000026] -A---+------              *  ASG       struct (copy)
               [000024] D----+-N----              +--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V02 loc2         
               [000023] -----+------              \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         

***** BB04
STMT00007 (IL 0x030...0x036)
               [000031] -A---+------              *  ASG       int   
               [000030] D----+-N----              +--*  LCL_VAR   int    V03 loc3         
               [000029] -----+------              \--*  LCL_FLD   int    V02 loc2         [+4] Fseq[j2]

***** BB04
STMT00008 (IL 0x037...0x041)
               [000033] --CXG+------              *  CALL      void   System.Console.WriteLine
               [000032] -----+------ arg0 in rcx  \--*  LCL_VAR   int    V03 loc3         

***** BB04
STMT00009 (IL 0x03D...  ???)
               [000037] -----+------              *  RETURN    int   
               [000036] -----+------              \--*  ADD       int   
               [000034] -----+------                 +--*  LCL_VAR   int    V03 loc3         
               [000035] -----+------                 \--*  CNS_INT   int    93

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist

*************** Starting PHASE GS Cookie
No GS security needed

*************** Finishing PHASE GS Cookie

*************** Starting PHASE Mark GC poll blocks

*************** Before renumbering the basic blocks

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1        [000..015)-> BB03 ( cond )                     i label target 
BB02 [0001]  1       BB01                  1        [015..01F)-> BB04 (always)                     i 
BB03 [0002]  1       BB01                  1        [01F..027)                                     i label target 
BB04 [0003]  2       BB02,BB03             1        [027..042)        (return)                     i label target hascall gcsafe 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty

*************** After renumbering the basic blocks
=============== No blocks renumbered!

*************** Finishing PHASE Mark GC poll blocks

*************** Starting PHASE Compute edge weights (1, false)
*************** In fgComputeBlockAndEdgeWeights()

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1        [000..015)-> BB03 ( cond )                     i label target 
BB02 [0001]  1       BB01                  1        [015..01F)-> BB04 (always)                     i 
BB03 [0002]  1       BB01                  1        [01F..027)                                     i label target 
BB04 [0003]  2       BB02,BB03             1        [027..042)        (return)                     i label target hascall gcsafe 
-----------------------------------------------------------------------------------------------------------------------------------------

 -- no profile data, so using default called count
fgComputeEdgeWeights() found inconsistent profile data, not using the edge weights

*************** Finishing PHASE Compute edge weights (1, false)

*************** Starting PHASE Create EH funclets
*************** In fgCreateFunclets()

After fgCreateFunclets()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1        [000..015)-> BB03 ( cond )                     i label target 
BB02 [0001]  1       BB01                  1        [015..01F)-> BB04 (always)                     i 
BB03 [0002]  1       BB01                  1        [01F..027)                                     i label target 
BB04 [0003]  2       BB02,BB03             1        [027..042)        (return)                     i label target hascall gcsafe 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty
*************** In fgDebugCheckBBlist

*************** Finishing PHASE Create EH funclets

*************** Starting PHASE Optimize layout
*************** In optOptimizeLayout()

***************  Exception Handling table is empty
*************** In fgDebugCheckBBlist

*************** In fgUpdateFlowGraph()
Before updating the flow graph:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1        [000..015)-> BB03 ( cond )                     i label target 
BB02 [0001]  1       BB01                  1        [015..01F)-> BB04 (always)                     i 
BB03 [0002]  1       BB01                  1        [01F..027)                                     i label target 
BB04 [0003]  2       BB02,BB03             1        [027..042)        (return)                     i label target hascall gcsafe 
-----------------------------------------------------------------------------------------------------------------------------------------

*************** In fgDebugCheckBBlist

*************** In fgExpandRarelyRunBlocks()
*************** In fgReorderBlocks()

Initial BasicBlocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1        [000..015)-> BB03 ( cond )                     i label target 
BB02 [0001]  1       BB01                  1        [015..01F)-> BB04 (always)                     i 
BB03 [0002]  1       BB01                  1        [01F..027)                                     i label target 
BB04 [0003]  2       BB02,BB03             1        [027..042)        (return)                     i label target hascall gcsafe 
-----------------------------------------------------------------------------------------------------------------------------------------


*************** In fgUpdateFlowGraph()
Before updating the flow graph:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1        [000..015)-> BB03 ( cond )                     i label target 
BB02 [0001]  1       BB01                  1        [015..01F)-> BB04 (always)                     i 
BB03 [0002]  1       BB01                  1        [01F..027)                                     i label target 
BB04 [0003]  2       BB02,BB03             1        [027..042)        (return)                     i label target hascall gcsafe 
-----------------------------------------------------------------------------------------------------------------------------------------

*************** In fgDebugCheckBBlist

*************** Finishing PHASE Optimize layout

*************** Starting PHASE Compute blocks reachability
*************** In fgComputeReachability
*************** In fgDebugCheckBBlist

Renumbering the basic blocks for fgComputeReachability pass #1

*************** Before renumbering the basic blocks

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1        [000..015)-> BB03 ( cond )                     i label target 
BB02 [0001]  1       BB01                  1        [015..01F)-> BB04 (always)                     i 
BB03 [0002]  1       BB01                  1        [01F..027)                                     i label target 
BB04 [0003]  2       BB02,BB03             1        [027..042)        (return)                     i label target hascall gcsafe 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty

*************** After renumbering the basic blocks
=============== No blocks renumbered!
Enter blocks: BB01 

After computing reachability sets:
------------------------------------------------
BBnum  Reachable by 
------------------------------------------------
BB01 : BB01 
BB02 : BB01 BB02 
BB03 : BB01 BB03 
BB04 : BB01 BB02 BB03 BB04 

After computing reachability:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1        [000..015)-> BB03 ( cond )                     i label target 
BB02 [0001]  1       BB01                  1        [015..01F)-> BB04 (always)                     i 
BB03 [0002]  1       BB01                  1        [01F..027)                                     i label target 
BB04 [0003]  2       BB02,BB03             1        [027..042)        (return)                     i label target hascall gcsafe 
-----------------------------------------------------------------------------------------------------------------------------------------

*************** In fgDebugCheckBBlist
*************** In fgComputeDoms
*************** In fgDebugCheckBBlist

Dominator computation start blocks (those blocks with no incoming edges):
BB01 
------------------------------------------------
BBnum  Dominated by
------------------------------------------------
BB01:  BB01 
BB02:  BB02 BB01 
BB03:  BB03 BB01 
BB04:  BB04 BB01 

Inside fgBuildDomTree

After computing the Dominance Tree:
BB01 : BB04 BB03 BB02 


After numbering the dominator tree:
BB01: pre=01, post=04
BB02: pre=04, post=03
BB03: pre=03, post=02
BB04: pre=02, post=01

*************** Finishing PHASE Compute blocks reachability

*************** Starting PHASE Optimize loops
*************** In optOptimizeLoops()

After optSetBlockWeights:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1        [000..015)-> BB03 ( cond )                     i label target 
BB02 [0001]  1       BB01                  0.50     [015..01F)-> BB04 (always)                     i 
BB03 [0002]  1       BB01                  0.50     [01F..027)                                     i label target 
BB04 [0003]  2       BB02,BB03             1        [027..042)        (return)                     i label target hascall gcsafe 
-----------------------------------------------------------------------------------------------------------------------------------------

*************** In fgDebugCheckBBlist

*************** Finishing PHASE Optimize loops

*************** Starting PHASE Clone loops

*************** In optCloneLoops()

*************** Finishing PHASE Clone loops

*************** Starting PHASE Unroll loops

*************** Finishing PHASE Unroll loops

*************** Starting PHASE Mark local vars

*************** In lvaMarkLocalVars()
*** lvaComputeRefCounts ***

*** lvaComputeRefCounts -- explicit counts ***

*** marking local variables in block BB01 (weight=1   )
STMT00000 (IL 0x000...0x001)
               [000002] -A--G+------              *  ASG       int   
               [000001] n---G+-N----              +--*  IND       int   
               [000057] H----+------              |  \--*  CNS_INT(h) long   0x7ffd8eef4abc static Fseq[i]
               [000000] -----+------              \--*  CNS_INT   int    0
STMT00001 (IL 0x006...0x009)
               [000006] IA---+------              *  ASG       struct (init)
               [000003] D----+-N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
               [000005] -----+------              \--*  CNS_INT   int    0
New refCnts for V00: refCnt =  1, refCntWtd = 1   
STMT00002 (IL 0x00E...0x013)
               [000010] ----G+------              *  JTRUE     void  
               [000009] J---G+-N----              \--*  EQ        int   
               [000007] n---G+------                 +--*  IND       int   
               [000058] H----+------                 |  \--*  CNS_INT(h) long   0x7ffd8eef4abc static Fseq[i]
               [000008] -----+------                 \--*  CNS_INT   int    0

*** marking local variables in block BB02 (weight=0.50)
STMT00010 (IL 0x015...0x018)
               [000041] IA---+------              *  ASG       struct (init)
               [000038] D----+-N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
               [000040] -----+------              \--*  CNS_INT   int    0
New refCnts for V00: refCnt =  2, refCntWtd = 1.50

*** marking local variables in block BB03 (weight=0.50)
STMT00003 (IL 0x01F...0x022)
               [000015] -A---+------              *  ASG       int   
               [000014] U----+-N----              +--*  LCL_FLD   int    V00 loc0         [+4] Fseq[i2]
               [000013] -----+------              \--*  CNS_INT   int    7
New refCnts for V00: refCnt =  3, refCntWtd = 2   

*** marking local variables in block BB04 (weight=1   )
STMT00012 (IL 0x027...  ???)
               [000052] -A---+------              *  ASG       struct (copy)
               [000050] D----+-N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V05 tmp1         
               [000019] -----+------              \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
New refCnts for V05: refCnt =  1, refCntWtd = 2   
New refCnts for V00: refCnt =  4, refCntWtd = 3   
STMT00005 (IL   ???...  ???)
               [000049] -A--G+------              *  ASG       struct (copy)
               [000048] D----+-N----              +--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V01 loc1         
               [000046] -----+------              \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
New refCnts for V01: refCnt =  1, refCntWtd = 1   
New refCnts for V00: refCnt =  5, refCntWtd = 4   
STMT00006 (IL 0x02E...0x02F)
               [000026] -A---+------              *  ASG       struct (copy)
               [000024] D----+-N----              +--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V02 loc2         
               [000023] -----+------              \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
New refCnts for V02: refCnt =  1, refCntWtd = 1   
New refCnts for V00: refCnt =  6, refCntWtd = 5   
STMT00007 (IL 0x030...0x036)
               [000031] -A---+------              *  ASG       int   
               [000030] D----+-N----              +--*  LCL_VAR   int    V03 loc3         
               [000029] -----+------              \--*  LCL_FLD   int    V02 loc2         [+4] Fseq[j2]
New refCnts for V03: refCnt =  1, refCntWtd = 1   
New refCnts for V02: refCnt =  2, refCntWtd = 2   
STMT00008 (IL 0x037...0x041)
               [000033] --CXG+------              *  CALL      void   System.Console.WriteLine
               [000032] -----+------ arg0 in rcx  \--*  LCL_VAR   int    V03 loc3         
New refCnts for V03: refCnt =  2, refCntWtd = 2   
STMT00009 (IL 0x03D...  ???)
               [000037] -----+------              *  RETURN    int   
               [000036] -----+------              \--*  ADD       int   
               [000034] -----+------                 +--*  LCL_VAR   int    V03 loc3         
               [000035] -----+------                 \--*  CNS_INT   int    93
New refCnts for V03: refCnt =  3, refCntWtd = 3   

*** lvaComputeRefCounts -- implicit counts ***

*************** In optAddCopies()


*************** Finishing PHASE Mark local vars

*************** Starting PHASE Optimize bools
*************** In optOptimizeBools()
*************** In fgDebugCheckBBlist

*************** Finishing PHASE Optimize bools

*************** Starting PHASE Find oper order
*************** In fgFindOperOrder()

*************** Finishing PHASE Find oper order

*************** Starting PHASE Set block order
*************** In fgSetBlockOrder()
The biggest BB has    5 tree nodes

*************** Finishing PHASE Set block order
Trees before Build SSA representation

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1        [000..015)-> BB03 ( cond )                     i label target 
BB02 [0001]  1       BB01                  0.50     [015..01F)-> BB04 (always)                     i 
BB03 [0002]  1       BB01                  0.50     [01F..027)                                     i label target 
BB04 [0003]  2       BB02,BB03             1        [027..042)        (return)                     i label target hascall gcsafe 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..015) -> BB03 (cond), preds={} succs={BB02,BB03}

***** BB01
STMT00000 (IL 0x000...0x001)
N004 (  6, 14) [000002] -A--G-------              *  ASG       int   
N002 (  4, 12) [000001] n---G--N----              +--*  IND       int   
N001 (  2, 10) [000057] H-----------              |  \--*  CNS_INT(h) long   0x7ffd8eef4abc static Fseq[i]
N003 (  1,  1) [000000] ------------              \--*  CNS_INT   int    0

***** BB01
STMT00001 (IL 0x006...0x009)
N003 (  5,  4) [000006] IA------R---              *  ASG       struct (init)
N002 (  3,  2) [000003] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
N001 (  1,  1) [000005] ------------              \--*  CNS_INT   int    0

***** BB01
STMT00002 (IL 0x00E...0x013)
N005 (  8, 16) [000010] ----G-------              *  JTRUE     void  
N004 (  6, 14) [000009] J---G--N----              \--*  EQ        int   
N002 (  4, 12) [000007] n---G-------                 +--*  IND       int   
N001 (  2, 10) [000058] H-----------                 |  \--*  CNS_INT(h) long   0x7ffd8eef4abc static Fseq[i]
N003 (  1,  1) [000008] ------------                 \--*  CNS_INT   int    0

------------ BB02 [015..01F) -> BB04 (always), preds={BB01} succs={BB04}

***** BB02
STMT00010 (IL 0x015...0x018)
N003 (  5,  4) [000041] IA------R---              *  ASG       struct (init)
N002 (  3,  2) [000038] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
N001 (  1,  1) [000040] ------------              \--*  CNS_INT   int    0

------------ BB03 [01F..027), preds={BB01} succs={BB04}

***** BB03
STMT00003 (IL 0x01F...0x022)
N003 (  5,  6) [000015] -A------R---              *  ASG       int   
N002 (  3,  4) [000014] U------N----              +--*  LCL_FLD   int    V00 loc0         [+4] Fseq[i2]
N001 (  1,  1) [000013] ------------              \--*  CNS_INT   int    7

------------ BB04 [027..042) (return), preds={BB02,BB03} succs={}

***** BB04
STMT00012 (IL 0x027...  ???)
N003 (  7,  5) [000052] -A------R---              *  ASG       struct (copy)
N002 (  3,  2) [000050] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V05 tmp1         
N001 (  3,  2) [000019] ------------              \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         

***** BB04
STMT00005 (IL   ???...  ???)
N003 (  7,  5) [000049] -A--G---R---              *  ASG       struct (copy)
N002 (  3,  2) [000048] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V01 loc1         
N001 (  3,  2) [000046] ------------              \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         

***** BB04
STMT00006 (IL 0x02E...0x02F)
N003 (  7,  5) [000026] -A------R---              *  ASG       struct (copy)
N002 (  3,  2) [000024] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V02 loc2         
N001 (  3,  2) [000023] ------------              \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         

***** BB04
STMT00007 (IL 0x030...0x036)
N003 (  3,  4) [000031] -A------R---              *  ASG       int   
N002 (  1,  1) [000030] D------N----              +--*  LCL_VAR   int    V03 loc3         
N001 (  3,  4) [000029] ------------              \--*  LCL_FLD   int    V02 loc2         [+4] Fseq[j2]

***** BB04
STMT00008 (IL 0x037...0x041)
N003 ( 15,  7) [000033] --CXG-------              *  CALL      void   System.Console.WriteLine
N002 (  1,  1) [000032] ------------ arg0 in rcx  \--*  LCL_VAR   int    V03 loc3         

***** BB04
STMT00009 (IL 0x03D...  ???)
N004 (  4,  4) [000037] ------------              *  RETURN    int   
N003 (  3,  3) [000036] ------------              \--*  ADD       int   
N001 (  1,  1) [000034] ------------                 +--*  LCL_VAR   int    V03 loc3         
N002 (  1,  1) [000035] ------------                 \--*  CNS_INT   int    93

-------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Build SSA representation
*************** In SsaBuilder::Build()
[SsaBuilder] Max block count is 5.

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1        [000..015)-> BB03 ( cond )                     i label target 
BB02 [0001]  1       BB01                  0.50     [015..01F)-> BB04 (always)                     i 
BB03 [0002]  1       BB01                  0.50     [01F..027)                                     i label target 
BB04 [0003]  2       BB02,BB03             1        [027..042)        (return)                     i label target hascall gcsafe 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty
[SsaBuilder] Topologically sorted the graph.
[SsaBuilder::ComputeImmediateDom]

Inside fgBuildDomTree

After computing the Dominance Tree:
BB01 : BB04 BB03 BB02 

*************** In fgLocalVarLiveness()
In fgLocalVarLivenessInit

Local V00 should not be enregistered because: it is a struct

Local V01 should not be enregistered because: it is a struct

Local V02 should not be enregistered because: it is a struct

Local V05 should not be enregistered because: it is a struct
Tracked variable (5 out of 6) table:
V00 loc0          [struct]: refCnt =    6, refCntWtd =   5   
V03 loc3          [   int]: refCnt =    3, refCntWtd =   3   
V02 loc2          [struct]: refCnt =    2, refCntWtd =   2   
V05 tmp1          [struct]: refCnt =    1, refCntWtd =   2   
V01 loc1          [struct]: refCnt =    1, refCntWtd =   1   

*************** In fgPerBlockLocalVarLiveness()
BB01 USE(0)={   } + ByrefExposed + GcHeap
     DEF(1)={V00} + ByrefExposed + GcHeap

BB02 USE(0)={   }
     DEF(1)={V00}

BB03 USE(1)={V00}
     DEF(1)={V00}

BB04 USE(1)={V00                } + ByrefExposed + GcHeap
     DEF(4)={    V03 V02 V05 V01} + ByrefExposed* + GcHeap*

** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()

BB liveness after fgLiveVarAnalysis():

BB01 IN (0)={   } + ByrefExposed + GcHeap
     OUT(1)={V00} + ByrefExposed + GcHeap

BB02 IN (0)={   } + ByrefExposed + GcHeap
     OUT(1)={V00} + ByrefExposed + GcHeap

BB03 IN (1)={V00} + ByrefExposed + GcHeap
     OUT(1)={V00} + ByrefExposed + GcHeap

BB04 IN (1)={V00} + ByrefExposed + GcHeap
     OUT(0)={   }

top level assign
removing stmt with no side effects

Removing statement STMT00005 (IL   ???...  ???)
N003 (  7,  5) [000049] -A--G---R---              *  ASG       struct (copy)
N002 (  3,  2) [000048] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V01 loc1         
N001 (  3,  2) [000046] ------------              \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
 in BB04 as useless:

top level assign
removing stmt with no side effects

Removing statement STMT00012 (IL 0x027...  ???)
N003 (  7,  5) [000052] -A------R---              *  ASG       struct (copy)
N002 (  3,  2) [000050] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V05 tmp1         
N001 (  3,  2) [000019] ------------              \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         
 in BB04 as useless:

*************** In optRemoveRedundantZeroInits()
*************** In SsaBuilder::InsertPhiFunctions()
Inserting phi functions:
Added PHI definition for V00 at start of BB04.
*************** In SsaBuilder::RenameVariables()

After fgSsaBuild:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1        [000..015)-> BB03 ( cond )                     i label target 
BB02 [0001]  1       BB01                  0.50     [015..01F)-> BB04 (always)                     i 
BB03 [0002]  1       BB01                  0.50     [01F..027)                                     i label target 
BB04 [0003]  2       BB02,BB03             1        [027..042)        (return)                     i label target hascall gcsafe 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..015) -> BB03 (cond), preds={} succs={BB02,BB03}

***** BB01
STMT00000 (IL 0x000...0x001)
N004 (  6, 14) [000002] -A--G-------              *  ASG       int   
N002 (  4, 12) [000001] n---G--N----              +--*  IND       int   
N001 (  2, 10) [000057] H-----------              |  \--*  CNS_INT(h) long   0x7ffd8eef4abc static Fseq[i]
N003 (  1,  1) [000000] ------------              \--*  CNS_INT   int    0

***** BB01
STMT00001 (IL 0x006...0x009)
N003 (  5,  4) [000006] IA------R---              *  ASG       struct (init)
N002 (  3,  2) [000003] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         d:2
N001 (  1,  1) [000005] ------------              \--*  CNS_INT   int    0

***** BB01
STMT00002 (IL 0x00E...0x013)
N005 (  8, 16) [000010] ----G-------              *  JTRUE     void  
N004 (  6, 14) [000009] J---G--N----              \--*  EQ        int   
N002 (  4, 12) [000007] n---G-------                 +--*  IND       int   
N001 (  2, 10) [000058] H-----------                 |  \--*  CNS_INT(h) long   0x7ffd8eef4abc static Fseq[i]
N003 (  1,  1) [000008] ------------                 \--*  CNS_INT   int    0

------------ BB02 [015..01F) -> BB04 (always), preds={BB01} succs={BB04}

***** BB02
STMT00010 (IL 0x015...0x018)
N003 (  5,  4) [000041] IA------R---              *  ASG       struct (init)
N002 (  3,  2) [000038] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         d:5
N001 (  1,  1) [000040] ------------              \--*  CNS_INT   int    0

------------ BB03 [01F..027), preds={BB01} succs={BB04}

***** BB03
STMT00003 (IL 0x01F...0x022)
N003 (  5,  6) [000015] -A------R---              *  ASG       int   
N002 (  3,  4) [000014] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:2->4[+4] Fseq[i2]
N001 (  1,  1) [000013] ------------              \--*  CNS_INT   int    7

------------ BB04 [027..042) (return), preds={BB02,BB03} succs={}

***** BB04
STMT00013 (IL   ???...  ???)
N005 (  0,  0) [000062] -A------R---              *  ASG       struct (copy)
N004 (  0,  0) [000060] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         d:3
N003 (  0,  0) [000061] ------------              \--*  PHI       struct
N001 (  0,  0) [000064] ------------ pred BB02       +--*  PHI_ARG   struct V00 loc0         u:5
N002 (  0,  0) [000063] ------------ pred BB03       \--*  PHI_ARG   struct V00 loc0         u:4

***** BB04
STMT00006 (IL 0x02E...0x02F)
N003 (  7,  5) [000026] -A------R---              *  ASG       struct (copy)
N002 (  3,  2) [000024] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V02 loc2         d:2
N001 (  3,  2) [000023] ------------              \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         u:3 (last use)

***** BB04
STMT00007 (IL 0x030...0x036)
N003 (  3,  4) [000031] -A------R---              *  ASG       int   
N002 (  1,  1) [000030] D------N----              +--*  LCL_VAR   int    V03 loc3         d:2
N001 (  3,  4) [000029] ------------              \--*  LCL_FLD   int    V02 loc2         u:2[+4] Fseq[j2] (last use)

***** BB04
STMT00008 (IL 0x037...0x041)
N003 ( 15,  7) [000033] --CXG-------              *  CALL      void   System.Console.WriteLine
N002 (  1,  1) [000032] ------------ arg0 in rcx  \--*  LCL_VAR   int    V03 loc3         u:2

***** BB04
STMT00009 (IL 0x03D...  ???)
N004 (  4,  4) [000037] ------------              *  RETURN    int   
N003 (  3,  3) [000036] ------------              \--*  ADD       int   
N001 (  1,  1) [000034] ------------                 +--*  LCL_VAR   int    V03 loc3         u:2 (last use)
N002 (  1,  1) [000035] ------------                 \--*  CNS_INT   int    93

-------------------------------------------------------------------------------------------------------------------

*************** Finishing PHASE Build SSA representation
Trees after Build SSA representation

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1        [000..015)-> BB03 ( cond )                     i label target 
BB02 [0001]  1       BB01                  0.50     [015..01F)-> BB04 (always)                     i 
BB03 [0002]  1       BB01                  0.50     [01F..027)                                     i label target 
BB04 [0003]  2       BB02,BB03             1        [027..042)        (return)                     i label target hascall gcsafe 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..015) -> BB03 (cond), preds={} succs={BB02,BB03}

***** BB01
STMT00000 (IL 0x000...0x001)
N004 (  6, 14) [000002] -A--G-------              *  ASG       int   
N002 (  4, 12) [000001] n---G--N----              +--*  IND       int   
N001 (  2, 10) [000057] H-----------              |  \--*  CNS_INT(h) long   0x7ffd8eef4abc static Fseq[i]
N003 (  1,  1) [000000] ------------              \--*  CNS_INT   int    0

***** BB01
STMT00001 (IL 0x006...0x009)
N003 (  5,  4) [000006] IA------R---              *  ASG       struct (init)
N002 (  3,  2) [000003] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         d:2
N001 (  1,  1) [000005] ------------              \--*  CNS_INT   int    0

***** BB01
STMT00002 (IL 0x00E...0x013)
N005 (  8, 16) [000010] ----G-------              *  JTRUE     void  
N004 (  6, 14) [000009] J---G--N----              \--*  EQ        int   
N002 (  4, 12) [000007] n---G-------                 +--*  IND       int   
N001 (  2, 10) [000058] H-----------                 |  \--*  CNS_INT(h) long   0x7ffd8eef4abc static Fseq[i]
N003 (  1,  1) [000008] ------------                 \--*  CNS_INT   int    0

------------ BB02 [015..01F) -> BB04 (always), preds={BB01} succs={BB04}

***** BB02
STMT00010 (IL 0x015...0x018)
N003 (  5,  4) [000041] IA------R---              *  ASG       struct (init)
N002 (  3,  2) [000038] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         d:5
N001 (  1,  1) [000040] ------------              \--*  CNS_INT   int    0

------------ BB03 [01F..027), preds={BB01} succs={BB04}

***** BB03
STMT00003 (IL 0x01F...0x022)
N003 (  5,  6) [000015] -A------R---              *  ASG       int   
N002 (  3,  4) [000014] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:2->4[+4] Fseq[i2]
N001 (  1,  1) [000013] ------------              \--*  CNS_INT   int    7

------------ BB04 [027..042) (return), preds={BB02,BB03} succs={}

***** BB04
STMT00013 (IL   ???...  ???)
N005 (  0,  0) [000062] -A------R---              *  ASG       struct (copy)
N004 (  0,  0) [000060] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         d:3
N003 (  0,  0) [000061] ------------              \--*  PHI       struct
N001 (  0,  0) [000064] ------------ pred BB02       +--*  PHI_ARG   struct V00 loc0         u:5
N002 (  0,  0) [000063] ------------ pred BB03       \--*  PHI_ARG   struct V00 loc0         u:4

***** BB04
STMT00006 (IL 0x02E...0x02F)
N003 (  7,  5) [000026] -A------R---              *  ASG       struct (copy)
N002 (  3,  2) [000024] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V02 loc2         d:2
N001 (  3,  2) [000023] ------------              \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         u:3 (last use)

***** BB04
STMT00007 (IL 0x030...0x036)
N003 (  3,  4) [000031] -A------R---              *  ASG       int   
N002 (  1,  1) [000030] D------N----              +--*  LCL_VAR   int    V03 loc3         d:2
N001 (  3,  4) [000029] ------------              \--*  LCL_FLD   int    V02 loc2         u:2[+4] Fseq[j2] (last use)

***** BB04
STMT00008 (IL 0x037...0x041)
N003 ( 15,  7) [000033] --CXG-------              *  CALL      void   System.Console.WriteLine
N002 (  1,  1) [000032] ------------ arg0 in rcx  \--*  LCL_VAR   int    V03 loc3         u:2

***** BB04
STMT00009 (IL 0x03D...  ???)
N004 (  4,  4) [000037] ------------              *  RETURN    int   
N003 (  3,  3) [000036] ------------              \--*  ADD       int   
N001 (  1,  1) [000034] ------------                 +--*  LCL_VAR   int    V03 loc3         u:2 (last use)
N002 (  1,  1) [000035] ------------                 \--*  CNS_INT   int    93

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist

*************** Starting PHASE Early Value Propagation
*************** In optEarlyProp()

After optEarlyProp:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1        [000..015)-> BB03 ( cond )                     i label target 
BB02 [0001]  1       BB01                  0.50     [015..01F)-> BB04 (always)                     i 
BB03 [0002]  1       BB01                  0.50     [01F..027)                                     i label target 
BB04 [0003]  2       BB02,BB03             1        [027..042)        (return)                     i label target hascall gcsafe 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..015) -> BB03 (cond), preds={} succs={BB02,BB03}

***** BB01
STMT00000 (IL 0x000...0x001)
N004 (  6, 14) [000002] -A--G-------              *  ASG       int   
N002 (  4, 12) [000001] n---G--N----              +--*  IND       int   
N001 (  2, 10) [000057] H-----------              |  \--*  CNS_INT(h) long   0x7ffd8eef4abc static Fseq[i]
N003 (  1,  1) [000000] ------------              \--*  CNS_INT   int    0

***** BB01
STMT00001 (IL 0x006...0x009)
N003 (  5,  4) [000006] IA------R---              *  ASG       struct (init)
N002 (  3,  2) [000003] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         d:2
N001 (  1,  1) [000005] ------------              \--*  CNS_INT   int    0

***** BB01
STMT00002 (IL 0x00E...0x013)
N005 (  8, 16) [000010] ----G-------              *  JTRUE     void  
N004 (  6, 14) [000009] J---G--N----              \--*  EQ        int   
N002 (  4, 12) [000007] n---G-------                 +--*  IND       int   
N001 (  2, 10) [000058] H-----------                 |  \--*  CNS_INT(h) long   0x7ffd8eef4abc static Fseq[i]
N003 (  1,  1) [000008] ------------                 \--*  CNS_INT   int    0

------------ BB02 [015..01F) -> BB04 (always), preds={BB01} succs={BB04}

***** BB02
STMT00010 (IL 0x015...0x018)
N003 (  5,  4) [000041] IA------R---              *  ASG       struct (init)
N002 (  3,  2) [000038] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         d:5
N001 (  1,  1) [000040] ------------              \--*  CNS_INT   int    0

------------ BB03 [01F..027), preds={BB01} succs={BB04}

***** BB03
STMT00003 (IL 0x01F...0x022)
N003 (  5,  6) [000015] -A------R---              *  ASG       int   
N002 (  3,  4) [000014] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:2->4[+4] Fseq[i2]
N001 (  1,  1) [000013] ------------              \--*  CNS_INT   int    7

------------ BB04 [027..042) (return), preds={BB02,BB03} succs={}

***** BB04
STMT00013 (IL   ???...  ???)
N005 (  0,  0) [000062] -A------R---              *  ASG       struct (copy)
N004 (  0,  0) [000060] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         d:3
N003 (  0,  0) [000061] ------------              \--*  PHI       struct
N001 (  0,  0) [000064] ------------ pred BB02       +--*  PHI_ARG   struct V00 loc0         u:5
N002 (  0,  0) [000063] ------------ pred BB03       \--*  PHI_ARG   struct V00 loc0         u:4

***** BB04
STMT00006 (IL 0x02E...0x02F)
N003 (  7,  5) [000026] -A------R---              *  ASG       struct (copy)
N002 (  3,  2) [000024] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V02 loc2         d:2
N001 (  3,  2) [000023] ------------              \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         u:3 (last use)

***** BB04
STMT00007 (IL 0x030...0x036)
N003 (  3,  4) [000031] -A------R---              *  ASG       int   
N002 (  1,  1) [000030] D------N----              +--*  LCL_VAR   int    V03 loc3         d:2
N001 (  3,  4) [000029] ------------              \--*  LCL_FLD   int    V02 loc2         u:2[+4] Fseq[j2] (last use)

***** BB04
STMT00008 (IL 0x037...0x041)
N003 ( 15,  7) [000033] --CXG-------              *  CALL      void   System.Console.WriteLine
N002 (  1,  1) [000032] ------------ arg0 in rcx  \--*  LCL_VAR   int    V03 loc3         u:2

***** BB04
STMT00009 (IL 0x03D...  ???)
N004 (  4,  4) [000037] ------------              *  RETURN    int   
N003 (  3,  3) [000036] ------------              \--*  ADD       int   
N001 (  1,  1) [000034] ------------                 +--*  LCL_VAR   int    V03 loc3         u:2 (last use)
N002 (  1,  1) [000035] ------------                 \--*  CNS_INT   int    93

-------------------------------------------------------------------------------------------------------------------

*************** Finishing PHASE Early Value Propagation

*************** Starting PHASE Do value numbering

*************** In fgValueNumber()
Memory Initial Value in BB01 is: $80
The SSA definition for ByrefExposed (#1) at start of BB01 is $80 {InitVal($41)}
The SSA definition for GcHeap (#1) at start of BB01 is $80 {InitVal($41)}

***** BB01, STMT00000(before)
N004 (  6, 14) [000002] -A--G-------              *  ASG       int   
N002 (  4, 12) [000001] n---G--N----              +--*  IND       int   
N001 (  2, 10) [000057] H-----------              |  \--*  CNS_INT(h) long   0x7ffd8eef4abc static Fseq[i]
N003 (  1,  1) [000000] ------------              \--*  CNS_INT   int    0

N001 [000057]   CNS_INT(h) 0x7ffd8eef4abc static Fseq[i] => $c0 {Hnd const: 0x00007FFD8EEF4ABC}
N003 [000000]   CNS_INT   0 => $40 {IntCns 0}
  fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [000002] to VN: $100.
N004 [000002]   ASG       => $VN.Void

***** BB01, STMT00000(after)
N004 (  6, 14) [000002] -A--G-------              *  ASG       int    $VN.Void
N002 (  4, 12) [000001] n---G--N----              +--*  IND       int    $40
N001 (  2, 10) [000057] H-----------              |  \--*  CNS_INT(h) long   0x7ffd8eef4abc static Fseq[i] $c0
N003 (  1,  1) [000000] ------------              \--*  CNS_INT   int    0 $40

---------

***** BB01, STMT00001(before)
N003 (  5,  4) [000006] IA------R---              *  ASG       struct (init)
N002 (  3,  2) [000003] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         d:2
N001 (  1,  1) [000005] ------------              \--*  CNS_INT   int    0

N001 [000005]   CNS_INT   0 => $40 {IntCns 0}
N003 [000006]   ASG       V00/2 => $VN.ZeroMap
N003 [000006]   ASG       => $VN.Void

***** BB01, STMT00001(after)
N003 (  5,  4) [000006] IA------R---              *  ASG       struct (init) $VN.Void
N002 (  3,  2) [000003] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         d:2
N001 (  1,  1) [000005] ------------              \--*  CNS_INT   int    0 $40

---------

***** BB01, STMT00002(before)
N005 (  8, 16) [000010] ----G-------              *  JTRUE     void  
N004 (  6, 14) [000009] J---G--N----              \--*  EQ        int   
N002 (  4, 12) [000007] n---G-------                 +--*  IND       int   
N001 (  2, 10) [000058] H-----------                 |  \--*  CNS_INT(h) long   0x7ffd8eef4abc static Fseq[i]
N003 (  1,  1) [000008] ------------                 \--*  CNS_INT   int    0

N001 [000058]   CNS_INT(h) 0x7ffd8eef4abc static Fseq[i] => $c0 {Hnd const: 0x00007FFD8EEF4ABC}
N002 [000007]   IND       => <l:$180 {ByrefExposedLoad($42, $c0, $100)}, c:$1c0 {1c0}>
N003 [000008]   CNS_INT   0 => $40 {IntCns 0}
N004 [000009]   EQ        => <l:$201 {EQ($180, $40)}, c:$200 {EQ($1c0, $40)}>

***** BB01, STMT00002(after)
N005 (  8, 16) [000010] ----G-------              *  JTRUE     void  
N004 (  6, 14) [000009] J---G--N----              \--*  EQ        int    <l:$201, c:$200>
N002 (  4, 12) [000007] n---G-------                 +--*  IND       int    <l:$180, c:$1c0>
N001 (  2, 10) [000058] H-----------                 |  \--*  CNS_INT(h) long   0x7ffd8eef4abc static Fseq[i] $c0
N003 (  1,  1) [000008] ------------                 \--*  CNS_INT   int    0 $40

finish(BB01).
   Succ(BB02).
     Not yet completed.
     All preds complete, adding to allDone.
   Succ(BB03).
     Not yet completed.
     All preds complete, adding to allDone.
The SSA definition for ByrefExposed (#2) at start of BB03 is $100 {100}
The SSA definition for GcHeap (#2) at start of BB03 is $100 {100}

***** BB03, STMT00003(before)
N003 (  5,  6) [000015] -A------R---              *  ASG       int   
N002 (  3,  4) [000014] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:2->4[+4] Fseq[i2]
N001 (  1,  1) [000013] ------------              \--*  CNS_INT   int    7

N001 [000013]   CNS_INT   7 => $42 {IntCns 7}
  VNApplySelectors:
    VNForHandle(i2) is $c1, fieldType is int
    VNForMapSelect($1, $c1):int returns $40 {IntCns 0}
  VNApplySelectors:
    VNForHandle(i2) is $c1, fieldType is int
    VNForMapSelect($1, $c1):int returns $40 {IntCns 0}
N002 [000014]   LCL_FLD   V00 loc0         ud:2->4[+4] Fseq[i2] => $40 {IntCns 0}
  VNApplySelectorsAssign:
    VNForHandle(i2) is $c1, fieldType is int
    VNForMapStore($1, $c1, $42):int returns $181 {$VN.ZeroMap[$c1 := $42]}
  VNApplySelectorsAssign:
    VNForHandle(i2) is $c1, fieldType is int
    VNForMapStore($1, $c1, $42):int returns $181 {$VN.ZeroMap[$c1 := $42]}
N002 [000014]   LCL_FLD   V00 loc0         ud:2->4[+4] Fseq[i2] => $181 {$VN.ZeroMap[$c1 := $42]}
N003 [000015]   ASG       => $42 {IntCns 7}

***** BB03, STMT00003(after)
N003 (  5,  6) [000015] -A------R---              *  ASG       int    $42
N002 (  3,  4) [000014] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:2->4[+4] Fseq[i2] $181
N001 (  1,  1) [000013] ------------              \--*  CNS_INT   int    7 $42

finish(BB03).
   Succ(BB04).
     Not yet completed.
     Not all preds complete  Adding to notallDone, if necessary...
       Was necessary.
The SSA definition for ByrefExposed (#2) at start of BB02 is $100 {100}
The SSA definition for GcHeap (#2) at start of BB02 is $100 {100}

***** BB02, STMT00010(before)
N003 (  5,  4) [000041] IA------R---              *  ASG       struct (init)
N002 (  3,  2) [000038] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         d:5
N001 (  1,  1) [000040] ------------              \--*  CNS_INT   int    0

N001 [000040]   CNS_INT   0 => $40 {IntCns 0}
N003 [000041]   ASG       V00/5 => $VN.ZeroMap
N003 [000041]   ASG       => $VN.Void

***** BB02, STMT00010(after)
N003 (  5,  4) [000041] IA------R---              *  ASG       struct (init) $VN.Void
N002 (  3,  2) [000038] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         d:5
N001 (  1,  1) [000040] ------------              \--*  CNS_INT   int    0 $40

finish(BB02).
   Succ(BB04).
     Not yet completed.
     All preds complete, adding to allDone.
SSA PHI definition: set VN of local 0/3 to $280 {PhiDef($0, $3, $240)} .
The SSA definition for ByrefExposed (#2) at start of BB04 is $100 {100}
The SSA definition for GcHeap (#2) at start of BB04 is $100 {100}

***** BB04, STMT00006(before)
N003 (  7,  5) [000026] -A------R---              *  ASG       struct (copy)
N002 (  3,  2) [000024] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V02 loc2         d:2
N001 (  3,  2) [000023] ------------              \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         u:3 (last use)

N001 [000023]   LCL_VAR   V00 loc0         u:3 (last use) => $280 {PhiDef($0, $3, $240)}
Tree [000026] assigned VN to local var V02/2: $280 {PhiDef($0, $3, $240)}
N003 [000026]   ASG       => $VN.Void

***** BB04, STMT00006(after)
N003 (  7,  5) [000026] -A------R---              *  ASG       struct (copy) $VN.Void
N002 (  3,  2) [000024] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V02 loc2         d:2
N001 (  3,  2) [000023] ------------              \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         u:3 (last use) $280

---------

***** BB04, STMT00007(before)
N003 (  3,  4) [000031] -A------R---              *  ASG       int   
N002 (  1,  1) [000030] D------N----              +--*  LCL_VAR   int    V03 loc3         d:2
N001 (  3,  4) [000029] ------------              \--*  LCL_FLD   int    V02 loc2         u:2[+4] Fseq[j2] (last use)

  VNApplySelectors:
    VNForHandle(j2) is $c2, fieldType is int
      AX2: $c2 != $c1 ==> select([$181]store($1, $c1, $42), $c2) ==> select($1, $c2).
    VNForMapSelect($280, $c2):int returns $40 {IntCns 0}
  VNApplySelectors:
    VNForHandle(j2) is $c2, fieldType is int
    VNForMapSelect($280, $c2):int returns $40 {IntCns 0}
N001 [000029]   LCL_FLD   V02 loc2         u:2[+4] Fseq[j2] (last use) => $40 {IntCns 0}
N002 [000030]   LCL_VAR   V03 loc3         d:2 => $40 {IntCns 0}
N003 [000031]   ASG       => $40 {IntCns 0}

***** BB04, STMT00007(after)
N003 (  3,  4) [000031] -A------R---              *  ASG       int    $40
N002 (  1,  1) [000030] D------N----              +--*  LCL_VAR   int    V03 loc3         d:2 $40
N001 (  3,  4) [000029] ------------              \--*  LCL_FLD   int    V02 loc2         u:2[+4] Fseq[j2] (last use) $40

---------

***** BB04, STMT00008(before)
N003 ( 15,  7) [000033] --CXG-------              *  CALL      void   System.Console.WriteLine
N002 (  1,  1) [000032] ------------ arg0 in rcx  \--*  LCL_VAR   int    V03 loc3         u:2

N001 [000059]   ARGPLACE  => $1c2 {1c2}
N002 [000032]   LCL_VAR   V03 loc3         u:2 => $40 {IntCns 0}
VN of ARGPLACE tree [000059] updated to $40 {IntCns 0}
  fgCurMemoryVN[GcHeap] assigned for CALL at [000033] to VN: $101.
N003 [000033]   CALL      => $VN.Void

***** BB04, STMT00008(after)
N003 ( 15,  7) [000033] --CXG-------              *  CALL      void   System.Console.WriteLine $VN.Void
N002 (  1,  1) [000032] ------------ arg0 in rcx  \--*  LCL_VAR   int    V03 loc3         u:2 $40

---------

***** BB04, STMT00009(before)
N004 (  4,  4) [000037] ------------              *  RETURN    int   
N003 (  3,  3) [000036] ------------              \--*  ADD       int   
N001 (  1,  1) [000034] ------------                 +--*  LCL_VAR   int    V03 loc3         u:2 (last use)
N002 (  1,  1) [000035] ------------                 \--*  CNS_INT   int    93

N001 [000034]   LCL_VAR   V03 loc3         u:2 (last use) => $40 {IntCns 0}
N002 [000035]   CNS_INT   93 => $45 {IntCns 93}
N003 [000036]   ADD       => $45 {IntCns 93}
N004 [000037]   RETURN    => $1c3 {1c3}

***** BB04, STMT00009(after)
N004 (  4,  4) [000037] ------------              *  RETURN    int    $1c3
N003 (  3,  3) [000036] ------------              \--*  ADD       int    $45
N001 (  1,  1) [000034] ------------                 +--*  LCL_VAR   int    V03 loc3         u:2 (last use) $40
N002 (  1,  1) [000035] ------------                 \--*  CNS_INT   int    93 $45

finish(BB04).

*************** Finishing PHASE Do value numbering

*************** Starting PHASE Hoist loop code

*************** Finishing PHASE Hoist loop code

*************** Starting PHASE VN based copy prop
*************** In optVnCopyProp()
Copy Assertion for BB01
  curSsaName stack: { }

							Live vars: {} => {V00}
Copy Assertion for BB04
  curSsaName stack: { 0-[000003]:V00 }

							Live vars: {V00} => {}
							Live vars: {} => {V02}
							Live vars: {V02} => {}
							Live vars: {} => {V03}
							Live vars: {V03} => {}
Copy Assertion for BB03
  curSsaName stack: { 0-[000003]:V00 }

Copy Assertion for BB02
  curSsaName stack: { 0-[000003]:V00 }

							Live vars: {} => {V00}

*************** Finishing PHASE VN based copy prop

*************** Starting PHASE Optimize Valnum CSEs

*************** In optOptimizeCSEs()
Blocks/Trees at start of optOptimizeCSE phase

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1        [000..015)-> BB03 ( cond )                     i label target 
BB02 [0001]  1       BB01                  0.50     [015..01F)-> BB04 (always)                     i 
BB03 [0002]  1       BB01                  0.50     [01F..027)                                     i label target 
BB04 [0003]  2       BB02,BB03             1        [027..042)        (return)                     i label target hascall gcsafe 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..015) -> BB03 (cond), preds={} succs={BB02,BB03}

***** BB01
STMT00000 (IL 0x000...0x001)
N004 (  6, 14) [000002] -A--G-------              *  ASG       int    $VN.Void
N002 (  4, 12) [000001] n---G--N----              +--*  IND       int    $40
N001 (  2, 10) [000057] H-----------              |  \--*  CNS_INT(h) long   0x7ffd8eef4abc static Fseq[i] $c0
N003 (  1,  1) [000000] ------------              \--*  CNS_INT   int    0 $40

***** BB01
STMT00001 (IL 0x006...0x009)
N003 (  5,  4) [000006] IA------R---              *  ASG       struct (init) $VN.Void
N002 (  3,  2) [000003] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         d:2
N001 (  1,  1) [000005] ------------              \--*  CNS_INT   int    0 $40

***** BB01
STMT00002 (IL 0x00E...0x013)
N005 (  8, 16) [000010] ----G-------              *  JTRUE     void  
N004 (  6, 14) [000009] J---G--N----              \--*  EQ        int    <l:$201, c:$200>
N002 (  4, 12) [000007] n---G-------                 +--*  IND       int    <l:$180, c:$1c0>
N001 (  2, 10) [000058] H-----------                 |  \--*  CNS_INT(h) long   0x7ffd8eef4abc static Fseq[i] $c0
N003 (  1,  1) [000008] ------------                 \--*  CNS_INT   int    0 $40

------------ BB02 [015..01F) -> BB04 (always), preds={BB01} succs={BB04}

***** BB02
STMT00010 (IL 0x015...0x018)
N003 (  5,  4) [000041] IA------R---              *  ASG       struct (init) $VN.Void
N002 (  3,  2) [000038] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         d:5
N001 (  1,  1) [000040] ------------              \--*  CNS_INT   int    0 $40

------------ BB03 [01F..027), preds={BB01} succs={BB04}

***** BB03
STMT00003 (IL 0x01F...0x022)
N003 (  5,  6) [000015] -A------R---              *  ASG       int    $42
N002 (  3,  4) [000014] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:2->4[+4] Fseq[i2] $181
N001 (  1,  1) [000013] ------------              \--*  CNS_INT   int    7 $42

------------ BB04 [027..042) (return), preds={BB02,BB03} succs={}

***** BB04
STMT00013 (IL   ???...  ???)
N005 (  0,  0) [000062] -A------R---              *  ASG       struct (copy)
N004 (  0,  0) [000060] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         d:3
N003 (  0,  0) [000061] ------------              \--*  PHI       struct
N001 (  0,  0) [000064] ------------ pred BB02       +--*  PHI_ARG   struct V00 loc0         u:5 $VN.ZeroMap
N002 (  0,  0) [000063] ------------ pred BB03       \--*  PHI_ARG   struct V00 loc0         u:4 $181

***** BB04
STMT00006 (IL 0x02E...0x02F)
N003 (  7,  5) [000026] -A------R---              *  ASG       struct (copy) $VN.Void
N002 (  3,  2) [000024] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V02 loc2         d:2
N001 (  3,  2) [000023] ------------              \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         u:3 (last use) $280

***** BB04
STMT00007 (IL 0x030...0x036)
N003 (  3,  4) [000031] -A------R---              *  ASG       int    $40
N002 (  1,  1) [000030] D------N----              +--*  LCL_VAR   int    V03 loc3         d:2 $40
N001 (  3,  4) [000029] ------------              \--*  LCL_FLD   int    V02 loc2         u:2[+4] Fseq[j2] (last use) $40

***** BB04
STMT00008 (IL 0x037...0x041)
N003 ( 15,  7) [000033] --CXG-------              *  CALL      void   System.Console.WriteLine $VN.Void
N002 (  1,  1) [000032] ------------ arg0 in rcx  \--*  LCL_VAR   int    V03 loc3         u:2 $40

***** BB04
STMT00009 (IL 0x03D...  ???)
N004 (  4,  4) [000037] ------------              *  RETURN    int    $1c3
N003 (  3,  3) [000036] ------------              \--*  ADD       int    $45
N001 (  1,  1) [000034] ------------                 +--*  LCL_VAR   int    V03 loc3         u:2 (last use) $40
N002 (  1,  1) [000035] ------------                 \--*  CNS_INT   int    93 $45

-------------------------------------------------------------------------------------------------------------------

*************** In optOptimizeValnumCSEs()

*************** Finishing PHASE Optimize Valnum CSEs

*************** Starting PHASE Assertion prop
*************** In optAssertionPropMain()
Blocks/Trees at start of phase

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1        [000..015)-> BB03 ( cond )                     i label target 
BB02 [0001]  1       BB01                  0.50     [015..01F)-> BB04 (always)                     i 
BB03 [0002]  1       BB01                  0.50     [01F..027)                                     i label target 
BB04 [0003]  2       BB02,BB03             1        [027..042)        (return)                     i label target hascall gcsafe 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..015) -> BB03 (cond), preds={} succs={BB02,BB03}

***** BB01
STMT00000 (IL 0x000...0x001)
N004 (  6, 14) [000002] -A--G-------              *  ASG       int    $VN.Void
N002 (  4, 12) [000001] n---G--N----              +--*  IND       int    $40
N001 (  2, 10) [000057] H-----------              |  \--*  CNS_INT(h) long   0x7ffd8eef4abc static Fseq[i] $c0
N003 (  1,  1) [000000] ------------              \--*  CNS_INT   int    0 $40

***** BB01
STMT00001 (IL 0x006...0x009)
N003 (  5,  4) [000006] IA------R---              *  ASG       struct (init) $VN.Void
N002 (  3,  2) [000003] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         d:2
N001 (  1,  1) [000005] ------------              \--*  CNS_INT   int    0 $40

***** BB01
STMT00002 (IL 0x00E...0x013)
N005 (  8, 16) [000010] ----G-------              *  JTRUE     void  
N004 (  6, 14) [000009] J---G--N----              \--*  EQ        int    <l:$201, c:$200>
N002 (  4, 12) [000007] n---G-------                 +--*  IND       int    <l:$180, c:$1c0>
N001 (  2, 10) [000058] H-----------                 |  \--*  CNS_INT(h) long   0x7ffd8eef4abc static Fseq[i] $c0
N003 (  1,  1) [000008] ------------                 \--*  CNS_INT   int    0 $40

------------ BB02 [015..01F) -> BB04 (always), preds={BB01} succs={BB04}

***** BB02
STMT00010 (IL 0x015...0x018)
N003 (  5,  4) [000041] IA------R---              *  ASG       struct (init) $VN.Void
N002 (  3,  2) [000038] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         d:5
N001 (  1,  1) [000040] ------------              \--*  CNS_INT   int    0 $40

------------ BB03 [01F..027), preds={BB01} succs={BB04}

***** BB03
STMT00003 (IL 0x01F...0x022)
N003 (  5,  6) [000015] -A------R---              *  ASG       int    $42
N002 (  3,  4) [000014] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:2->4[+4] Fseq[i2] $181
N001 (  1,  1) [000013] ------------              \--*  CNS_INT   int    7 $42

------------ BB04 [027..042) (return), preds={BB02,BB03} succs={}

***** BB04
STMT00013 (IL   ???...  ???)
N005 (  0,  0) [000062] -A------R---              *  ASG       struct (copy)
N004 (  0,  0) [000060] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         d:3
N003 (  0,  0) [000061] ------------              \--*  PHI       struct
N001 (  0,  0) [000064] ------------ pred BB02       +--*  PHI_ARG   struct V00 loc0         u:5 $VN.ZeroMap
N002 (  0,  0) [000063] ------------ pred BB03       \--*  PHI_ARG   struct V00 loc0         u:4 $181

***** BB04
STMT00006 (IL 0x02E...0x02F)
N003 (  7,  5) [000026] -A------R---              *  ASG       struct (copy) $VN.Void
N002 (  3,  2) [000024] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V02 loc2         d:2
N001 (  3,  2) [000023] ------------              \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         u:3 (last use) $280

***** BB04
STMT00007 (IL 0x030...0x036)
N003 (  3,  4) [000031] -A------R---              *  ASG       int    $40
N002 (  1,  1) [000030] D------N----              +--*  LCL_VAR   int    V03 loc3         d:2 $40
N001 (  3,  4) [000029] ------------              \--*  LCL_FLD   int    V02 loc2         u:2[+4] Fseq[j2] (last use) $40

***** BB04
STMT00008 (IL 0x037...0x041)
N003 ( 15,  7) [000033] --CXG-------              *  CALL      void   System.Console.WriteLine $VN.Void
N002 (  1,  1) [000032] ------------ arg0 in rcx  \--*  LCL_VAR   int    V03 loc3         u:2 $40

***** BB04
STMT00009 (IL 0x03D...  ???)
N004 (  4,  4) [000037] ------------              *  RETURN    int    $1c3
N003 (  3,  3) [000036] ------------              \--*  ADD       int    $45
N001 (  1,  1) [000034] ------------                 +--*  LCL_VAR   int    V03 loc3         u:2 (last use) $40
N002 (  1,  1) [000035] ------------                 \--*  CNS_INT   int    93 $45

-------------------------------------------------------------------------------------------------------------------
After constant propagation on [000032]:
STMT00008 (IL 0x037...0x041)
N003 ( 15,  7) [000033] --CXG-------              *  CALL      void   System.Console.WriteLine $VN.Void
               [000065] ------------ arg0 in rcx  \--*  CNS_INT   int    0 $40
ReMorphing args for 33.CALL:
argSlots=1, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32
ArgTable for 33.CALL after fgMorphArgs:
fgArgTabEntry[arg 0 65.CNS_INT int (By ref), 1 reg: rcx, align=1, lateArgInx=0, processed]

optVNAssertionPropCurStmt morphed tree:
N003 ( 15,  7) [000033] --CXG-------              *  CALL      void   System.Console.WriteLine $VN.Void
N002 (  1,  1) [000065] ------------ arg0 in rcx  \--*  CNS_INT   int    0 $40

After constant propagation on [000036]:
STMT00009 (IL 0x03D...  ???)
N004 (  4,  4) [000037] ------------              *  RETURN    int    $1c3
               [000066] ------------              \--*  CNS_INT   int    93 $45
optVNAssertionPropCurStmt morphed tree:
N002 (  2,  2) [000037] ------------              *  RETURN    int    $1c3
N001 (  1,  1) [000066] ------------              \--*  CNS_INT   int    93 $45


*************** Finishing PHASE Assertion prop

*************** Starting PHASE Optimize index checks
*************** In OptimizeRangeChecks()
Blocks/trees before phase

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1        [000..015)-> BB03 ( cond )                     i label target 
BB02 [0001]  1       BB01                  0.50     [015..01F)-> BB04 (always)                     i 
BB03 [0002]  1       BB01                  0.50     [01F..027)                                     i label target 
BB04 [0003]  2       BB02,BB03             1        [027..042)        (return)                     i label target hascall gcsafe 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..015) -> BB03 (cond), preds={} succs={BB02,BB03}

***** BB01
STMT00000 (IL 0x000...0x001)
N004 (  6, 14) [000002] -A--G-------              *  ASG       int    $VN.Void
N002 (  4, 12) [000001] n---G--N----              +--*  IND       int    $40
N001 (  2, 10) [000057] H-----------              |  \--*  CNS_INT(h) long   0x7ffd8eef4abc static Fseq[i] $c0
N003 (  1,  1) [000000] ------------              \--*  CNS_INT   int    0 $40

***** BB01
STMT00001 (IL 0x006...0x009)
N003 (  5,  4) [000006] IA------R---              *  ASG       struct (init) $VN.Void
N002 (  3,  2) [000003] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         d:2
N001 (  1,  1) [000005] ------------              \--*  CNS_INT   int    0 $40

***** BB01
STMT00002 (IL 0x00E...0x013)
N005 (  8, 16) [000010] ----G-------              *  JTRUE     void  
N004 (  6, 14) [000009] J---G--N----              \--*  EQ        int    <l:$201, c:$200>
N002 (  4, 12) [000007] n---G-------                 +--*  IND       int    <l:$180, c:$1c0>
N001 (  2, 10) [000058] H-----------                 |  \--*  CNS_INT(h) long   0x7ffd8eef4abc static Fseq[i] $c0
N003 (  1,  1) [000008] ------------                 \--*  CNS_INT   int    0 $40

------------ BB02 [015..01F) -> BB04 (always), preds={BB01} succs={BB04}

***** BB02
STMT00010 (IL 0x015...0x018)
N003 (  5,  4) [000041] IA------R---              *  ASG       struct (init) $VN.Void
N002 (  3,  2) [000038] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         d:5
N001 (  1,  1) [000040] ------------              \--*  CNS_INT   int    0 $40

------------ BB03 [01F..027), preds={BB01} succs={BB04}

***** BB03
STMT00003 (IL 0x01F...0x022)
N003 (  5,  6) [000015] -A------R---              *  ASG       int    $42
N002 (  3,  4) [000014] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:2->4[+4] Fseq[i2] $181
N001 (  1,  1) [000013] ------------              \--*  CNS_INT   int    7 $42

------------ BB04 [027..042) (return), preds={BB02,BB03} succs={}

***** BB04
STMT00013 (IL   ???...  ???)
N005 (  0,  0) [000062] -A------R---              *  ASG       struct (copy)
N004 (  0,  0) [000060] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         d:3
N003 (  0,  0) [000061] ------------              \--*  PHI       struct
N001 (  0,  0) [000064] ------------ pred BB02       +--*  PHI_ARG   struct V00 loc0         u:5 $VN.ZeroMap
N002 (  0,  0) [000063] ------------ pred BB03       \--*  PHI_ARG   struct V00 loc0         u:4 $181

***** BB04
STMT00006 (IL 0x02E...0x02F)
N003 (  7,  5) [000026] -A------R---              *  ASG       struct (copy) $VN.Void
N002 (  3,  2) [000024] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V02 loc2         d:2
N001 (  3,  2) [000023] ------------              \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         u:3 (last use) $280

***** BB04
STMT00007 (IL 0x030...0x036)
N003 (  3,  4) [000031] -A------R---              *  ASG       int    $40
N002 (  1,  1) [000030] D------N----              +--*  LCL_VAR   int    V03 loc3         d:2 $40
N001 (  3,  4) [000029] ------------              \--*  LCL_FLD   int    V02 loc2         u:2[+4] Fseq[j2] (last use) $40

***** BB04
STMT00008 (IL 0x037...0x041)
N003 ( 15,  7) [000033] --CXG-------              *  CALL      void   System.Console.WriteLine $VN.Void
N002 (  1,  1) [000065] ------------ arg0 in rcx  \--*  CNS_INT   int    0 $40

***** BB04
STMT00009 (IL 0x03D...  ???)
N002 (  2,  2) [000037] ------------              *  RETURN    int    $1c3
N001 (  1,  1) [000066] ------------              \--*  CNS_INT   int    93 $45

-------------------------------------------------------------------------------------------------------------------

*************** Finishing PHASE Optimize index checks

*************** Starting PHASE Insert GC Polls

*************** Finishing PHASE Insert GC Polls [no changes]

*************** Starting PHASE Determine first cold block

*************** In fgDetermineFirstColdBlock()
No procedure splitting will be done for this method

*************** Finishing PHASE Determine first cold block
Trees before Rationalize IR

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1        [000..015)-> BB03 ( cond )                     i label target 
BB02 [0001]  1       BB01                  0.50     [015..01F)-> BB04 (always)                     i 
BB03 [0002]  1       BB01                  0.50     [01F..027)                                     i label target 
BB04 [0003]  2       BB02,BB03             1        [027..042)        (return)                     i label target hascall gcsafe 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..015) -> BB03 (cond), preds={} succs={BB02,BB03}

***** BB01
STMT00000 (IL 0x000...0x001)
N004 (  6, 14) [000002] -A--G-------              *  ASG       int    $VN.Void
N002 (  4, 12) [000001] n---G--N----              +--*  IND       int    $40
N001 (  2, 10) [000057] H-----------              |  \--*  CNS_INT(h) long   0x7ffd8eef4abc static Fseq[i] $c0
N003 (  1,  1) [000000] ------------              \--*  CNS_INT   int    0 $40

***** BB01
STMT00001 (IL 0x006...0x009)
N003 (  5,  4) [000006] IA------R---              *  ASG       struct (init) $VN.Void
N002 (  3,  2) [000003] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         d:2
N001 (  1,  1) [000005] ------------              \--*  CNS_INT   int    0 $40

***** BB01
STMT00002 (IL 0x00E...0x013)
N005 (  8, 16) [000010] ----G-------              *  JTRUE     void  
N004 (  6, 14) [000009] J---G--N----              \--*  EQ        int    <l:$201, c:$200>
N002 (  4, 12) [000007] n---G-------                 +--*  IND       int    <l:$180, c:$1c0>
N001 (  2, 10) [000058] H-----------                 |  \--*  CNS_INT(h) long   0x7ffd8eef4abc static Fseq[i] $c0
N003 (  1,  1) [000008] ------------                 \--*  CNS_INT   int    0 $40

------------ BB02 [015..01F) -> BB04 (always), preds={BB01} succs={BB04}

***** BB02
STMT00010 (IL 0x015...0x018)
N003 (  5,  4) [000041] IA------R---              *  ASG       struct (init) $VN.Void
N002 (  3,  2) [000038] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         d:5
N001 (  1,  1) [000040] ------------              \--*  CNS_INT   int    0 $40

------------ BB03 [01F..027), preds={BB01} succs={BB04}

***** BB03
STMT00003 (IL 0x01F...0x022)
N003 (  5,  6) [000015] -A------R---              *  ASG       int    $42
N002 (  3,  4) [000014] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:2->4[+4] Fseq[i2] $181
N001 (  1,  1) [000013] ------------              \--*  CNS_INT   int    7 $42

------------ BB04 [027..042) (return), preds={BB02,BB03} succs={}

***** BB04
STMT00013 (IL   ???...  ???)
N005 (  0,  0) [000062] -A------R---              *  ASG       struct (copy)
N004 (  0,  0) [000060] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         d:3
N003 (  0,  0) [000061] ------------              \--*  PHI       struct
N001 (  0,  0) [000064] ------------ pred BB02       +--*  PHI_ARG   struct V00 loc0         u:5 $VN.ZeroMap
N002 (  0,  0) [000063] ------------ pred BB03       \--*  PHI_ARG   struct V00 loc0         u:4 $181

***** BB04
STMT00006 (IL 0x02E...0x02F)
N003 (  7,  5) [000026] -A------R---              *  ASG       struct (copy) $VN.Void
N002 (  3,  2) [000024] D------N----              +--*  LCL_VAR   struct<GitHub_24159.Str2, 20> V02 loc2         d:2
N001 (  3,  2) [000023] ------------              \--*  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         u:3 (last use) $280

***** BB04
STMT00007 (IL 0x030...0x036)
N003 (  3,  4) [000031] -A------R---              *  ASG       int    $40
N002 (  1,  1) [000030] D------N----              +--*  LCL_VAR   int    V03 loc3         d:2 $40
N001 (  3,  4) [000029] ------------              \--*  LCL_FLD   int    V02 loc2         u:2[+4] Fseq[j2] (last use) $40

***** BB04
STMT00008 (IL 0x037...0x041)
N003 ( 15,  7) [000033] --CXG-------              *  CALL      void   System.Console.WriteLine $VN.Void
N002 (  1,  1) [000065] ------------ arg0 in rcx  \--*  CNS_INT   int    0 $40

***** BB04
STMT00009 (IL 0x03D...  ???)
N002 (  2,  2) [000037] ------------              *  RETURN    int    $1c3
N001 (  1,  1) [000066] ------------              \--*  CNS_INT   int    93 $45

-------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Rationalize IR
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 (  5,  4) [000006] DA----------              *  STORE_LCL_VAR struct<GitHub_24159.Str1, 20> V00 loc0         d:2

rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 (  5,  4) [000041] DA----------              *  STORE_LCL_VAR struct<GitHub_24159.Str1, 20> V00 loc0         d:5

rewriting asg(LCL_FLD, X) to STORE_LCL_FLD(X)
N003 (  5,  6) [000015] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:2->0[+4] Fseq[i2]

rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N005 (  0,  0) [000062] DA----------              *  STORE_LCL_VAR struct<GitHub_24159.Str1, 20> V00 loc0         d:3

rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 (  7,  5) [000026] DA----------              *  STORE_LCL_VAR struct<GitHub_24159.Str2, 20> V02 loc2         d:2

rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 (  3,  4) [000031] DA----------              *  STORE_LCL_VAR int    V03 loc3         d:2


*************** Finishing PHASE Rationalize IR
Trees after Rationalize IR

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1        [000..015)-> BB03 ( cond )                     i label target LIR 
BB02 [0001]  1       BB01                  0.50     [015..01F)-> BB04 (always)                     i LIR 
BB03 [0002]  1       BB01                  0.50     [01F..027)                                     i label target LIR 
BB04 [0003]  2       BB02,BB03             1        [027..042)        (return)                     i label target hascall gcsafe LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..015) -> BB03 (cond), preds={} succs={BB02,BB03}
               [000067] ------------                 IL_OFFSET void   IL offset: 0x0
N001 (  2, 10) [000057] H-----------        t57 =    CNS_INT(h) long   0x7ffd8eef4abc static Fseq[i] $c0
N003 (  1,  1) [000000] ------------         t0 =    CNS_INT   int    0 $40
                                                  /--*  t57    long   
                                                  +--*  t0     int    
               [000068] -A--G-------              *  STOREIND  int   
               [000069] ------------                 IL_OFFSET void   IL offset: 0x6
N001 (  1,  1) [000005] ------------         t5 =    CNS_INT   int    0 $40
                                                  /--*  t5     int    
N003 (  5,  4) [000006] DA----------              *  STORE_LCL_VAR struct<GitHub_24159.Str1, 20> V00 loc0         d:2
               [000070] ------------                 IL_OFFSET void   IL offset: 0xe
N001 (  2, 10) [000058] H-----------        t58 =    CNS_INT(h) long   0x7ffd8eef4abc static Fseq[i] $c0
                                                  /--*  t58    long   
N002 (  4, 12) [000007] n---G-------         t7 = *  IND       int    <l:$180, c:$1c0>
N003 (  1,  1) [000008] ------------         t8 =    CNS_INT   int    0 $40
                                                  /--*  t7     int    
                                                  +--*  t8     int    
N004 (  6, 14) [000009] J---G--N----         t9 = *  EQ        int    <l:$201, c:$200>
                                                  /--*  t9     int    
N005 (  8, 16) [000010] ----G-------              *  JTRUE     void  

------------ BB02 [015..01F) -> BB04 (always), preds={BB01} succs={BB04}
               [000071] ------------                 IL_OFFSET void   IL offset: 0x15
N001 (  1,  1) [000040] ------------        t40 =    CNS_INT   int    0 $40
                                                  /--*  t40    int    
N003 (  5,  4) [000041] DA----------              *  STORE_LCL_VAR struct<GitHub_24159.Str1, 20> V00 loc0         d:5

------------ BB03 [01F..027), preds={BB01} succs={BB04}
               [000072] ------------                 IL_OFFSET void   IL offset: 0x1f
N001 (  1,  1) [000013] ------------        t13 =    CNS_INT   int    7 $42
                                                  /--*  t13    int    
N003 (  5,  6) [000015] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:2->0[+4] Fseq[i2]

------------ BB04 [027..042) (return), preds={BB02,BB03} succs={}
N001 (  0,  0) [000064] ------------        t64 =    PHI_ARG   struct V00 loc0         u:5 $VN.ZeroMap
N002 (  0,  0) [000063] ------------        t63 =    PHI_ARG   struct V00 loc0         u:4 $181
                                                  /--*  t64    struct 
                                                  +--*  t63    struct 
N003 (  0,  0) [000061] ------------        t61 = *  PHI       struct
                                                  /--*  t61    struct 
N005 (  0,  0) [000062] DA----------              *  STORE_LCL_VAR struct<GitHub_24159.Str1, 20> V00 loc0         d:3
               [000073] ------------                 IL_OFFSET void   IL offset: 0x2e
N001 (  3,  2) [000023] ------------        t23 =    LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         u:3 (last use) $280
                                                  /--*  t23    struct 
N003 (  7,  5) [000026] DA----------              *  STORE_LCL_VAR struct<GitHub_24159.Str2, 20> V02 loc2         d:2
               [000074] ------------                 IL_OFFSET void   IL offset: 0x30
N001 (  3,  4) [000029] ------------        t29 =    LCL_FLD   int    V02 loc2         u:2[+4] Fseq[j2] (last use) $40
                                                  /--*  t29    int    
N003 (  3,  4) [000031] DA----------              *  STORE_LCL_VAR int    V03 loc3         d:2
               [000075] ------------                 IL_OFFSET void   IL offset: 0x37
N002 (  1,  1) [000065] ------------        t65 =    CNS_INT   int    0 $40
                                                  /--*  t65    int    arg0 in rcx
N003 ( 15,  7) [000033] --CXG-------              *  CALL      void   System.Console.WriteLine $VN.Void
               [000076] ------------                 IL_OFFSET void   IL offset: 0x3d
N001 (  1,  1) [000066] ------------        t66 =    CNS_INT   int    93 $45
                                                  /--*  t66    int    
N002 (  2,  2) [000037] ------------              *  RETURN    int    $1c3

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist

*************** Starting PHASE Do 'simple' lowering
Bumping outgoingArgSpaceSize to 32 for call [000033]

*************** Finishing PHASE Do 'simple' lowering
*************** In fgDebugCheckBBlist
Trees before Lowering nodeinfo

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1        [000..015)-> BB03 ( cond )                     i label target LIR 
BB02 [0001]  1       BB01                  0.50     [015..01F)-> BB04 (always)                     i LIR 
BB03 [0002]  1       BB01                  0.50     [01F..027)                                     i label target LIR 
BB04 [0003]  2       BB02,BB03             1        [027..042)        (return)                     i label target hascall gcsafe LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..015) -> BB03 (cond), preds={} succs={BB02,BB03}
               [000067] ------------                 IL_OFFSET void   IL offset: 0x0
N001 (  2, 10) [000057] H-----------        t57 =    CNS_INT(h) long   0x7ffd8eef4abc static Fseq[i] $c0
N003 (  1,  1) [000000] ------------         t0 =    CNS_INT   int    0 $40
                                                  /--*  t57    long   
                                                  +--*  t0     int    
               [000068] -A--G-------              *  STOREIND  int   
               [000069] ------------                 IL_OFFSET void   IL offset: 0x6
N001 (  1,  1) [000005] ------------         t5 =    CNS_INT   int    0 $40
                                                  /--*  t5     int    
N003 (  5,  4) [000006] DA----------              *  STORE_LCL_VAR struct<GitHub_24159.Str1, 20> V00 loc0         d:2
               [000070] ------------                 IL_OFFSET void   IL offset: 0xe
N001 (  2, 10) [000058] H-----------        t58 =    CNS_INT(h) long   0x7ffd8eef4abc static Fseq[i] $c0
                                                  /--*  t58    long   
N002 (  4, 12) [000007] n---G-------         t7 = *  IND       int    <l:$180, c:$1c0>
N003 (  1,  1) [000008] ------------         t8 =    CNS_INT   int    0 $40
                                                  /--*  t7     int    
                                                  +--*  t8     int    
N004 (  6, 14) [000009] J---G--N----         t9 = *  EQ        int    <l:$201, c:$200>
                                                  /--*  t9     int    
N005 (  8, 16) [000010] ----G-------              *  JTRUE     void  

------------ BB02 [015..01F) -> BB04 (always), preds={BB01} succs={BB04}
               [000071] ------------                 IL_OFFSET void   IL offset: 0x15
N001 (  1,  1) [000040] ------------        t40 =    CNS_INT   int    0 $40
                                                  /--*  t40    int    
N003 (  5,  4) [000041] DA----------              *  STORE_LCL_VAR struct<GitHub_24159.Str1, 20> V00 loc0         d:5

------------ BB03 [01F..027), preds={BB01} succs={BB04}
               [000072] ------------                 IL_OFFSET void   IL offset: 0x1f
N001 (  1,  1) [000013] ------------        t13 =    CNS_INT   int    7 $42
                                                  /--*  t13    int    
N003 (  5,  6) [000015] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:2->0[+4] Fseq[i2]

------------ BB04 [027..042) (return), preds={BB02,BB03} succs={}
N001 (  0,  0) [000064] ------------        t64 =    PHI_ARG   struct V00 loc0         u:5 $VN.ZeroMap
N002 (  0,  0) [000063] ------------        t63 =    PHI_ARG   struct V00 loc0         u:4 $181
                                                  /--*  t64    struct 
                                                  +--*  t63    struct 
N003 (  0,  0) [000061] ------------        t61 = *  PHI       struct
                                                  /--*  t61    struct 
N005 (  0,  0) [000062] DA----------              *  STORE_LCL_VAR struct<GitHub_24159.Str1, 20> V00 loc0         d:3
               [000073] ------------                 IL_OFFSET void   IL offset: 0x2e
N001 (  3,  2) [000023] ------------        t23 =    LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         u:3 (last use) $280
                                                  /--*  t23    struct 
N003 (  7,  5) [000026] DA----------              *  STORE_LCL_VAR struct<GitHub_24159.Str2, 20> V02 loc2         d:2
               [000074] ------------                 IL_OFFSET void   IL offset: 0x30
N001 (  3,  4) [000029] ------------        t29 =    LCL_FLD   int    V02 loc2         u:2[+4] Fseq[j2] (last use) $40
                                                  /--*  t29    int    
N003 (  3,  4) [000031] DA----------              *  STORE_LCL_VAR int    V03 loc3         d:2
               [000075] ------------                 IL_OFFSET void   IL offset: 0x37
N002 (  1,  1) [000065] ------------        t65 =    CNS_INT   int    0 $40
                                                  /--*  t65    int    arg0 in rcx
N003 ( 15,  7) [000033] --CXG-------              *  CALL      void   System.Console.WriteLine $VN.Void
               [000076] ------------                 IL_OFFSET void   IL offset: 0x3d
N001 (  1,  1) [000066] ------------        t66 =    CNS_INT   int    93 $45
                                                  /--*  t66    int    
N002 (  2,  2) [000037] ------------              *  RETURN    int    $1c3

-------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Lowering nodeinfo
Lower of StoreInd didn't mark the node as self contained for reason: 4
N001 (  2, 10) [000057] H-----------        t57 =    CNS_INT(h) long   0x7ffd8eef4abc static Fseq[i] $c0
N003 (  1,  1) [000000] ------------         t0 =    CNS_INT   int    0 $40
                                                  /--*  t57    long   
                                                  +--*  t0     int    
               [000068] -A--G-------              *  STOREIND  int   
lowering store lcl var/field (before):
N001 (  1,  1) [000005] ------------         t5 =    CNS_INT   int    0 $40
                                                  /--*  t5     int    
N003 (  5,  4) [000006] DA----------              *  STORE_LCL_VAR struct<GitHub_24159.Str1, 20> V00 loc0         d:2

lowering store lcl var/field (before):
N001 (  1,  1) [000040] ------------        t40 =    CNS_INT   int    0 $40
                                                  /--*  t40    int    
N003 (  5,  4) [000041] DA----------              *  STORE_LCL_VAR struct<GitHub_24159.Str1, 20> V00 loc0         d:5

lowering store lcl var/field (before):
N001 (  1,  1) [000013] ------------        t13 =    CNS_INT   int    7 $42
                                                  /--*  t13    int    
N003 (  5,  6) [000015] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:2->0[+4] Fseq[i2]

lowering store lcl var/field (after):
N001 (  1,  1) [000013] -c----------        t13 =    CNS_INT   int    7 $42
                                                  /--*  t13    int    
N003 (  5,  6) [000015] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:2->0[+4] Fseq[i2]

lowering store lcl var/field (before):
N001 (  0,  0) [000064] ------------        t64 =    PHI_ARG   struct V00 loc0         u:5 $VN.ZeroMap
N002 (  0,  0) [000063] ------------        t63 =    PHI_ARG   struct V00 loc0         u:4 $181
                                                  /--*  t64    struct 
                                                  +--*  t63    struct 
N003 (  0,  0) [000061] ------------        t61 = *  PHI       struct
                                                  /--*  t61    struct 
N005 (  0,  0) [000062] DA----------              *  STORE_LCL_VAR struct<GitHub_24159.Str1, 20> V00 loc0         d:3

lowering store lcl var/field (after):
N001 (  0,  0) [000064] ------------        t64 =    PHI_ARG   struct V00 loc0         u:5 $VN.ZeroMap
N002 (  0,  0) [000063] ------------        t63 =    PHI_ARG   struct V00 loc0         u:4 $181
                                                  /--*  t64    struct 
                                                  +--*  t63    struct 
N003 (  0,  0) [000061] ------------        t61 = *  PHI       struct
                                                  /--*  t61    struct 
N005 (  0,  0) [000062] DA----------              *  STORE_LCL_VAR struct<GitHub_24159.Str1, 20> V00 loc0         d:3

lowering store lcl var/field (before):
N001 (  3,  2) [000023] ------------        t23 =    LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         u:3 (last use) $280
                                                  /--*  t23    struct 
N003 (  7,  5) [000026] DA----------              *  STORE_LCL_VAR struct<GitHub_24159.Str2, 20> V02 loc2         d:2

lowering store lcl var/field (before):
N001 (  3,  4) [000029] ------------        t29 =    LCL_FLD   int    V02 loc2         u:2[+4] Fseq[j2] (last use) $40
                                                  /--*  t29    int    
N003 (  3,  4) [000031] DA----------              *  STORE_LCL_VAR int    V03 loc3         d:2

lowering store lcl var/field (after):
N001 (  3,  4) [000029] ------------        t29 =    LCL_FLD   int    V02 loc2         u:2[+4] Fseq[j2] (last use) $40
                                                  /--*  t29    int    
N003 (  3,  4) [000031] DA----------              *  STORE_LCL_VAR int    V03 loc3         d:2

lowering call (before):
N002 (  1,  1) [000065] ------------        t65 =    CNS_INT   int    0 $40
                                                  /--*  t65    int    arg0 in rcx
N003 ( 15,  7) [000033] --CXG-------              *  CALL      void   System.Console.WriteLine $VN.Void

objp:
======

args:
======
lowering arg : N001 (  0,  0) [000059] ----------L-              *  ARGPLACE  int    $40

late:
======
lowering arg : N002 (  1,  1) [000065] ------------              *  CNS_INT   int    0 $40
new node is :                [000080] ------------              *  PUTARG_REG int    REG rcx

lowering call (after):
N002 (  1,  1) [000065] ------------        t65 =    CNS_INT   int    0 $40
                                                  /--*  t65    int    
               [000080] ------------        t80 = *  PUTARG_REG int    REG rcx
                                                  /--*  t80    int    arg0 in rcx
N003 ( 15,  7) [000033] --CXG-------              *  CALL      void   System.Console.WriteLine $VN.Void

lowering GT_RETURN
N002 (  2,  2) [000037] ------------              *  RETURN    int    $1c3
============Lower has completed modifying nodes.

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1        [000..015)-> BB03 ( cond )                     i label target LIR 
BB02 [0001]  1       BB01                  0.50     [015..01F)-> BB04 (always)                     i LIR 
BB03 [0002]  1       BB01                  0.50     [01F..027)                                     i label target LIR 
BB04 [0003]  2       BB02,BB03             1        [027..042)        (return)                     i label target hascall gcsafe LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..015) -> BB03 (cond), preds={} succs={BB02,BB03}
               [000067] ------------                 IL_OFFSET void   IL offset: 0x0
N001 (  2, 10) [000057] H-----------        t57 =    CNS_INT(h) long   0x7ffd8eef4abc static Fseq[i] $c0
N003 (  1,  1) [000000] ------------         t0 =    CNS_INT   int    0 $40
                                                  /--*  t57    long   
                                                  +--*  t0     int    
               [000068] -A--G-------              *  STOREIND  int   
               [000069] ------------                 IL_OFFSET void   IL offset: 0x6
N001 (  1,  1) [000005] ------------         t5 =    CNS_INT   int    0 $40
               [000077] Dc-----N----        t77 =    LCL_VAR_ADDR byref  V00 loc0         
                                                  /--*  t77    byref  
                                                  +--*  t5     int    
N003 (  5,  4) [000006] sA----------              *  STORE_BLK struct<GitHub_24159.Str1, 20> (init) (Unroll)
               [000070] ------------                 IL_OFFSET void   IL offset: 0xe
N001 (  2, 10) [000058] H-----------        t58 =    CNS_INT(h) long   0x7ffd8eef4abc static Fseq[i] $c0
                                                  /--*  t58    long   
N002 (  4, 12) [000007] nc--G-------         t7 = *  IND       int    <l:$180, c:$1c0>
N003 (  1,  1) [000008] -c----------         t8 =    CNS_INT   int    0 $40
                                                  /--*  t7     int    
                                                  +--*  t8     int    
N004 (  6, 14) [000009] J---G--N----              *  EQ        void   <l:$201, c:$200>
N005 (  8, 16) [000010] ----G-------              *  JTRUE     void  

------------ BB02 [015..01F) -> BB04 (always), preds={BB01} succs={BB04}
               [000071] ------------                 IL_OFFSET void   IL offset: 0x15
N001 (  1,  1) [000040] ------------        t40 =    CNS_INT   int    0 $40
               [000078] Dc-----N----        t78 =    LCL_VAR_ADDR byref  V00 loc0         
                                                  /--*  t78    byref  
                                                  +--*  t40    int    
N003 (  5,  4) [000041] sA----------              *  STORE_BLK struct<GitHub_24159.Str1, 20> (init) (Unroll)

------------ BB03 [01F..027), preds={BB01} succs={BB04}
               [000072] ------------                 IL_OFFSET void   IL offset: 0x1f
N001 (  1,  1) [000013] -c----------        t13 =    CNS_INT   int    7 $42
                                                  /--*  t13    int    
N003 (  5,  6) [000015] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:2->0[+4] Fseq[i2]

------------ BB04 [027..042) (return), preds={BB02,BB03} succs={}
N001 (  0,  0) [000064] ------------        t64 =    PHI_ARG   struct V00 loc0         u:5 $VN.ZeroMap
N002 (  0,  0) [000063] ------------        t63 =    PHI_ARG   struct V00 loc0         u:4 $181
                                                  /--*  t64    struct 
                                                  +--*  t63    struct 
N003 (  0,  0) [000061] ------------        t61 = *  PHI       struct
                                                  /--*  t61    struct 
N005 (  0,  0) [000062] DA----------              *  STORE_LCL_VAR struct<GitHub_24159.Str1, 20> V00 loc0         d:3
               [000073] ------------                 IL_OFFSET void   IL offset: 0x2e
N001 (  3,  2) [000023] -c----------        t23 =    LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         u:3 (last use) $280
               [000079] Dc-----N----        t79 =    LCL_VAR_ADDR byref  V02 loc2         
                                                  /--*  t79    byref  
                                                  +--*  t23    struct 
N003 (  7,  5) [000026] sA----------              *  STORE_BLK struct<GitHub_24159.Str2, 20> (copy) (Unroll)
               [000074] ------------                 IL_OFFSET void   IL offset: 0x30
N001 (  3,  4) [000029] ------------        t29 =    LCL_FLD   int    V02 loc2         u:2[+4] Fseq[j2] (last use) $40
                                                  /--*  t29    int    
N003 (  3,  4) [000031] DA----------              *  STORE_LCL_VAR int    V03 loc3         d:2
               [000075] ------------                 IL_OFFSET void   IL offset: 0x37
N002 (  1,  1) [000065] ------------        t65 =    CNS_INT   int    0 $40
                                                  /--*  t65    int    
               [000080] ------------        t80 = *  PUTARG_REG int    REG rcx
                                                  /--*  t80    int    arg0 in rcx
N003 ( 15,  7) [000033] --CXG-------              *  CALL      void   System.Console.WriteLine $VN.Void
               [000076] ------------                 IL_OFFSET void   IL offset: 0x3d
N001 (  1,  1) [000066] ------------        t66 =    CNS_INT   int    93 $45
                                                  /--*  t66    int    
N002 (  2,  2) [000037] ------------              *  RETURN    int    $1c3

-------------------------------------------------------------------------------------------------------------------

*** lvaComputeRefCounts ***

*** lvaComputeRefCounts -- explicit counts ***
New refCnts for V00: refCnt =  1, refCntWtd = 1   
New refCnts for V00: refCnt =  2, refCntWtd = 1.50
New refCnts for V00: refCnt =  3, refCntWtd = 2   
New refCnts for V00: refCnt =  4, refCntWtd = 3   
New refCnts for V02: refCnt =  1, refCntWtd = 1   
New refCnts for V02: refCnt =  2, refCntWtd = 2   
New refCnts for V03: refCnt =  1, refCntWtd = 1   

*** lvaComputeRefCounts -- implicit counts ***
*************** In fgLocalVarLiveness()
; Initial local variable assignments
;
;  V00 loc0           struct <GitHub_24159.Str1, 20> do-not-enreg[SFB] ld-addr-op
;  V01 loc1           struct <GitHub_24159.Str2, 20> do-not-enreg[SB]
;  V02 loc2           struct <GitHub_24159.Str2, 20> do-not-enreg[SFB]
;  V03 loc3              int 
;  V04 OutArgs        lclBlk <32>  "OutgoingArgSpace"
;  V05 tmp1           struct <GitHub_24159.Str1, 20> do-not-enreg[SB] ld-addr-op overlapping-fields "Inlining Arg"
In fgLocalVarLivenessInit

Local V00 should not be enregistered because: it is a struct

Local V01 should not be enregistered because: it is a struct

Local V02 should not be enregistered because: it is a struct

Local V05 should not be enregistered because: it is a struct
Tracked variable (3 out of 6) table:
V00 loc0          [struct]: refCnt =    4, refCntWtd =   3   
V02 loc2          [struct]: refCnt =    2, refCntWtd =   2   
V03 loc3          [   int]: refCnt =    1, refCntWtd =   1   

*************** In fgPerBlockLocalVarLiveness()
BB01 USE(0)={   } + ByrefExposed + GcHeap
     DEF(1)={V00}

BB02 USE(0)={   }
     DEF(1)={V00}

BB03 USE(1)={V00}
     DEF(1)={V00}

BB04 USE(1)={V00        } + ByrefExposed + GcHeap
     DEF(2)={    V02 V03} + ByrefExposed* + GcHeap*

** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()

BB liveness after fgLiveVarAnalysis():

BB01 IN (0)={   } + ByrefExposed + GcHeap
     OUT(1)={V00} + ByrefExposed + GcHeap

BB02 IN (0)={   } + ByrefExposed + GcHeap
     OUT(1)={V00} + ByrefExposed + GcHeap

BB03 IN (1)={V00} + ByrefExposed + GcHeap
     OUT(1)={V00} + ByrefExposed + GcHeap

BB04 IN (1)={V00} + ByrefExposed + GcHeap
     OUT(0)={   }

Removing dead store:
N003 (  3,  4) [000031] DA----------              *  STORE_LCL_VAR int    V03 loc3         d:2 (last use)
Removing dead LclVar use:
N001 (  3,  4) [000029] ------------              *  LCL_FLD   int    V02 loc2         u:2[+4] Fseq[j2] (last use) $40
Removing dead indirect store:
N003 (  7,  5) [000026] sA----------              *  STORE_BLK struct<GitHub_24159.Str2, 20> (copy) (Unroll)
Removing dead LclVar use:
N001 (  3,  2) [000023] ------------              *  LCL_VAR   struct<GitHub_24159.Str1, 20> V00 loc0         u:3 (last use) $280
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(0)={   } + ByrefExposed + GcHeap
     DEF(1)={V00}

BB02 USE(0)={   }
     DEF(1)={V00}

BB03 USE(1)={V00}
     DEF(1)={V00}

BB04 USE(0)={} + ByrefExposed + GcHeap
     DEF(0)={} + ByrefExposed* + GcHeap*

** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()

BB liveness after fgLiveVarAnalysis():

BB01 IN (0)={   } + ByrefExposed + GcHeap
     OUT(1)={V00} + ByrefExposed + GcHeap

BB02 IN (0)={} + ByrefExposed + GcHeap
     OUT(0)={} + ByrefExposed + GcHeap

BB03 IN (1)={V00} + ByrefExposed + GcHeap
     OUT(0)={   } + ByrefExposed + GcHeap

BB04 IN (0)={} + ByrefExposed + GcHeap
     OUT(0)={}

Removing dead indirect store:
N003 (  5,  4) [000041] sA----------              *  STORE_BLK struct<GitHub_24159.Str1, 20> (init) (Unroll)
Removing dead node:
N001 (  1,  1) [000040] ------------              *  CNS_INT   int    0 $40
Removing dead store:
N003 (  5,  6) [000015] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:2->0[+4] Fseq[i2] (last use)
Removing dead node:
N001 (  1,  1) [000013] ------------              *  CNS_INT   int    7 $42
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(0)={   } + ByrefExposed + GcHeap
     DEF(1)={V00}

BB02 USE(0)={}
     DEF(0)={}

BB03 USE(0)={}
     DEF(0)={}

BB04 USE(0)={} + ByrefExposed + GcHeap
     DEF(0)={} + ByrefExposed* + GcHeap*

** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()

BB liveness after fgLiveVarAnalysis():

BB01 IN (0)={} + ByrefExposed + GcHeap
     OUT(0)={} + ByrefExposed + GcHeap

BB02 IN (0)={} + ByrefExposed + GcHeap
     OUT(0)={} + ByrefExposed + GcHeap

BB03 IN (0)={} + ByrefExposed + GcHeap
     OUT(0)={} + ByrefExposed + GcHeap

BB04 IN (0)={} + ByrefExposed + GcHeap
     OUT(0)={}

Removing dead indirect store:
N003 (  5,  4) [000006] sA----------              *  STORE_BLK struct<GitHub_24159.Str1, 20> (init) (Unroll)
Removing dead node:
N001 (  1,  1) [000005] ------------              *  CNS_INT   int    0 $40

*************** In fgUpdateFlowGraph()
Before updating the flow graph:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1        [000..015)-> BB03 ( cond )                     i label target LIR 
BB02 [0001]  1       BB01                  0.50     [015..01F)-> BB04 (always)                     i LIR 
BB03 [0002]  1       BB01                  0.50     [01F..027)                                     i label target LIR 
BB04 [0003]  2       BB02,BB03             1        [027..042)        (return)                     i label target hascall gcsafe LIR 
-----------------------------------------------------------------------------------------------------------------------------------------


Reversing a conditional jump around an unconditional jump (BB01 -> BB03 -> BB04)

After reversing the jump:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1        [000..015)-> BB04 ( cond )                     i label target LIR 
BB03 [0002]  1       BB01                  0.50     [01F..027)                                     i label target LIR 
BB04 [0003]  2       BB01,BB03             1        [027..042)        (return)                     i label target hascall gcsafe LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

Compacting blocks BB03 and BB04:
Second block has multiple incoming edges
*************** In fgDebugCheckBBlist

Removing conditional jump to next block (BB01 -> BB03)

Compacting blocks BB01 and BB03:
*************** In fgDebugCheckBBlist

After updating the flow graph:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1        [000..042)        (return)                     i label target gcsafe LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty
*************** In fgDebugCheckBBlist
had to run another liveness pass:
*************** In fgLocalVarLiveness()
; Initial local variable assignments
;
;  V00 loc0           struct <GitHub_24159.Str1, 20> do-not-enreg[SFB] ld-addr-op
;  V01 loc1           struct <GitHub_24159.Str2, 20> do-not-enreg[SB]
;  V02 loc2           struct <GitHub_24159.Str2, 20> do-not-enreg[SFB]
;  V03 loc3              int 
;  V04 OutArgs        lclBlk <32>  "OutgoingArgSpace"
;  V05 tmp1           struct <GitHub_24159.Str1, 20> do-not-enreg[SB] ld-addr-op overlapping-fields "Inlining Arg"
In fgLocalVarLivenessInit

Local V00 should not be enregistered because: it is a struct

Local V01 should not be enregistered because: it is a struct

Local V02 should not be enregistered because: it is a struct

Local V05 should not be enregistered because: it is a struct
Tracked variable (3 out of 6) table:
V00 loc0          [struct]: refCnt =    4, refCntWtd =   3   
V02 loc2          [struct]: refCnt =    2, refCntWtd =   2   
V03 loc3          [   int]: refCnt =    1, refCntWtd =   1   

*************** In fgPerBlockLocalVarLiveness()
BB01 USE(0)={} + ByrefExposed + GcHeap
     DEF(0)={} + ByrefExposed* + GcHeap*

** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()

BB liveness after fgLiveVarAnalysis():

BB01 IN (0)={} + ByrefExposed + GcHeap
     OUT(0)={}


*** lvaComputeRefCounts ***

*** lvaComputeRefCounts -- explicit counts ***

*** lvaComputeRefCounts -- implicit counts ***

*************** Finishing PHASE Lowering nodeinfo
Trees after Lowering nodeinfo

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1        [000..042)        (return)                     i label target gcsafe LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..042) (return), preds={} succs={}
N001 (  0,  0) [000064] ------------        t64 =    PHI_ARG   struct V00 loc0         u:5 $VN.ZeroMap
N002 (  0,  0) [000063] ------------        t63 =    PHI_ARG   struct V00 loc0         u:4 $181
                                                  /--*  t64    struct 
                                                  +--*  t63    struct 
N003 (  0,  0) [000061] ------------        t61 = *  PHI       struct
                                                  /--*  t61    struct 
N005 (  0,  0) [000062] DA----------              *  STORE_LCL_VAR struct<GitHub_24159.Str1, 20> V00 loc0         d:3
               [000067] ------------                 IL_OFFSET void   IL offset: 0x0
N001 (  2, 10) [000057] H-----------        t57 =    CNS_INT(h) long   0x7ffd8eef4abc static Fseq[i] $c0
N003 (  1,  1) [000000] ------------         t0 =    CNS_INT   int    0 $40
                                                  /--*  t57    long   
                                                  +--*  t0     int    
               [000068] -A--G-------              *  STOREIND  int   
               [000069] ------------                 IL_OFFSET void   IL offset: 0x6
               [000070] ------------                 IL_OFFSET void   IL offset: 0xe
               [000072] ------------                 IL_OFFSET void   IL offset: 0x1f
               [000073] ------------                 IL_OFFSET void   IL offset: 0x2e
               [000074] ------------                 IL_OFFSET void   IL offset: 0x30
               [000075] ------------                 IL_OFFSET void   IL offset: 0x37
N002 (  1,  1) [000065] ------------        t65 =    CNS_INT   int    0 $40
                                                  /--*  t65    int    
               [000080] ------------        t80 = *  PUTARG_REG int    REG rcx
                                                  /--*  t80    int    arg0 in rcx
N003 ( 15,  7) [000033] --CXG-------              *  CALL      void   System.Console.WriteLine $VN.Void
               [000076] ------------                 IL_OFFSET void   IL offset: 0x3d
N001 (  1,  1) [000066] ------------        t66 =    CNS_INT   int    93 $45
                                                  /--*  t66    int    
N002 (  2,  2) [000037] ------------              *  RETURN    int    $1c3

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Trees before Calculate stack level slots

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1        [000..042)        (return)                     i label target gcsafe LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..042) (return), preds={} succs={}
N001 (  0,  0) [000064] ------------        t64 =    PHI_ARG   struct V00 loc0         u:5 $VN.ZeroMap
N002 (  0,  0) [000063] ------------        t63 =    PHI_ARG   struct V00 loc0         u:4 $181
                                                  /--*  t64    struct 
                                                  +--*  t63    struct 
N003 (  0,  0) [000061] ------------        t61 = *  PHI       struct
                                                  /--*  t61    struct 
N005 (  0,  0) [000062] DA----------              *  STORE_LCL_VAR struct<GitHub_24159.Str1, 20> V00 loc0         d:3
               [000067] ------------                 IL_OFFSET void   IL offset: 0x0
N001 (  2, 10) [000057] H-----------        t57 =    CNS_INT(h) long   0x7ffd8eef4abc static Fseq[i] $c0
N003 (  1,  1) [000000] ------------         t0 =    CNS_INT   int    0 $40
                                                  /--*  t57    long   
                                                  +--*  t0     int    
               [000068] -A--G-------              *  STOREIND  int   
               [000069] ------------                 IL_OFFSET void   IL offset: 0x6
               [000070] ------------                 IL_OFFSET void   IL offset: 0xe
               [000072] ------------                 IL_OFFSET void   IL offset: 0x1f
               [000073] ------------                 IL_OFFSET void   IL offset: 0x2e
               [000074] ------------                 IL_OFFSET void   IL offset: 0x30
               [000075] ------------                 IL_OFFSET void   IL offset: 0x37
N002 (  1,  1) [000065] ------------        t65 =    CNS_INT   int    0 $40
                                                  /--*  t65    int    
               [000080] ------------        t80 = *  PUTARG_REG int    REG rcx
                                                  /--*  t80    int    arg0 in rcx
N003 ( 15,  7) [000033] --CXG-------              *  CALL      void   System.Console.WriteLine $VN.Void
               [000076] ------------                 IL_OFFSET void   IL offset: 0x3d
N001 (  1,  1) [000066] ------------        t66 =    CNS_INT   int    93 $45
                                                  /--*  t66    int    
N002 (  2,  2) [000037] ------------              *  RETURN    int    $1c3

-------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Calculate stack level slots

*************** Finishing PHASE Calculate stack level slots [no changes]

*************** Starting PHASE Linear scan register alloc
Clearing modified regs.

buildIntervals ========

-----------------
LIVENESS:
-----------------
BB01 use def in out
{}
{}
{}
{}

FP callee save candidate vars: None

floatVarCount = 0; hasLoops = 0, singleExit = 1
TUPLE STYLE DUMP BEFORE LSRA
LSRA Block Sequence: BB01(  1   ) 

BB01 [000..042) (return), preds={} succs={}
=====
  N000.                    IL_OFFSET IL offset: 0x0
  N001. t57             =  CNS_INT(h) 0x7ffd8eef4abc static Fseq[i]
  N003. t0              =  CNS_INT   0
  N000.                    STOREIND ; t57,t0
  N000.                    IL_OFFSET IL offset: 0x6
  N000.                    IL_OFFSET IL offset: 0xe
  N000.                    IL_OFFSET IL offset: 0x1f
  N000.                    IL_OFFSET IL offset: 0x2e
  N000.                    IL_OFFSET IL offset: 0x30
  N000.                    IL_OFFSET IL offset: 0x37
  N002. t65             =  CNS_INT   0
  N000. t80             =  PUTARG_REG; t65
  N003.                    CALL     ; t80
  N000.                    IL_OFFSET IL offset: 0x3d
  N001. t66             =  CNS_INT   93
  N002.                    RETURN   ; t66




buildIntervals second part ========

NEW BLOCK BB01
<RefPosition #0   @1   RefTypeBB  BB01 regmask=[] minReg=1>

DefList: {  }
N003 (???,???) [000067] ------------              *  IL_OFFSET void   IL offset: 0x0 REG NA

DefList: {  }
N005 (  2, 10) [000057] H-----------              *  CNS_INT(h) long   0x7ffd8eef4abc static Fseq[i] REG NA $c0
Interval  0: long RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #1   @6   RefTypeDef <Ivl:0> CNS_INT BB01 regmask=[allInt] minReg=1>

DefList: { N005.t57. CNS_INT }
N007 (  1,  1) [000000] ------------              *  CNS_INT   int    0 REG NA $40
Interval  1: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #2   @8   RefTypeDef <Ivl:1> CNS_INT BB01 regmask=[allInt] minReg=1>

DefList: { N005.t57. CNS_INT; N007.t0. CNS_INT }
N009 (???,???) [000068] -A--G-------              *  STOREIND  int    REG NA
<RefPosition #3   @9   RefTypeUse <Ivl:0>  BB01 regmask=[allInt] minReg=1 last>
<RefPosition #4   @9   RefTypeUse <Ivl:1>  BB01 regmask=[allInt] minReg=1 last>

DefList: {  }
N011 (???,???) [000069] ------------              *  IL_OFFSET void   IL offset: 0x6 REG NA

DefList: {  }
N013 (???,???) [000070] ------------              *  IL_OFFSET void   IL offset: 0xe REG NA

DefList: {  }
N015 (???,???) [000072] ------------              *  IL_OFFSET void   IL offset: 0x1f REG NA

DefList: {  }
N017 (???,???) [000073] ------------              *  IL_OFFSET void   IL offset: 0x2e REG NA

DefList: {  }
N019 (???,???) [000074] ------------              *  IL_OFFSET void   IL offset: 0x30 REG NA

DefList: {  }
N021 (???,???) [000075] ------------              *  IL_OFFSET void   IL offset: 0x37 REG NA

DefList: {  }
N023 (  1,  1) [000065] ------------              *  CNS_INT   int    0 REG NA $40
Interval  2: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #5   @24  RefTypeDef <Ivl:2> CNS_INT BB01 regmask=[allInt] minReg=1>

DefList: { N023.t65. CNS_INT }
N025 (???,???) [000080] ------------              *  PUTARG_REG int    REG rcx
<RefPosition #6   @25  RefTypeFixedReg <Reg:rcx>  BB01 regmask=[rcx] minReg=1>
<RefPosition #7   @25  RefTypeUse <Ivl:2>  BB01 regmask=[rcx] minReg=1 last fixed>
Interval  3: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #8   @26  RefTypeFixedReg <Reg:rcx>  BB01 regmask=[rcx] minReg=1>
<RefPosition #9   @26  RefTypeDef <Ivl:3> PUTARG_REG BB01 regmask=[rcx] minReg=1 fixed>

DefList: { N025.t80. PUTARG_REG }
N027 ( 15,  7) [000033] --CXG-------              *  CALL      void   System.Console.WriteLine REG NA $VN.Void
<RefPosition #10  @27  RefTypeFixedReg <Reg:rcx>  BB01 regmask=[rcx] minReg=1>
<RefPosition #11  @27  RefTypeUse <Ivl:3>  BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #12  @28  RefTypeKill <Reg:rax>  BB01 regmask=[rax] minReg=1>
<RefPosition #13  @28  RefTypeKill <Reg:rcx>  BB01 regmask=[rcx] minReg=1>
<RefPosition #14  @28  RefTypeKill <Reg:rdx>  BB01 regmask=[rdx] minReg=1>
<RefPosition #15  @28  RefTypeKill <Reg:r8 >  BB01 regmask=[r8] minReg=1>
<RefPosition #16  @28  RefTypeKill <Reg:r9 >  BB01 regmask=[r9] minReg=1>
<RefPosition #17  @28  RefTypeKill <Reg:r10>  BB01 regmask=[r10] minReg=1>
<RefPosition #18  @28  RefTypeKill <Reg:r11>  BB01 regmask=[r11] minReg=1>

DefList: {  }
N029 (???,???) [000076] ------------              *  IL_OFFSET void   IL offset: 0x3d REG NA

DefList: {  }
N031 (  1,  1) [000066] ------------              *  CNS_INT   int    93 REG NA $45
Interval  4: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #19  @32  RefTypeDef <Ivl:4> CNS_INT BB01 regmask=[allInt] minReg=1>

DefList: { N031.t66. CNS_INT }
N033 (  2,  2) [000037] ------------              *  RETURN    int    REG NA $1c3
<RefPosition #20  @33  RefTypeFixedReg <Reg:rax>  BB01 regmask=[rax] minReg=1>
<RefPosition #21  @33  RefTypeUse <Ivl:4>  BB01 regmask=[rax] minReg=1 last fixed>



CHECKING LAST USES for BB01, liveout={}
==============================
use: {}
def: {}

Linear scan intervals BEFORE VALIDATING INTERVALS:
Interval  0: long (constant) RefPositions {#1@6 #3@9} physReg:NA Preferences=[allInt]
Interval  1: int (constant) RefPositions {#2@8 #4@9} physReg:NA Preferences=[allInt]
Interval  2: int (constant) RefPositions {#5@24 #7@25} physReg:NA Preferences=[rcx]
Interval  3: int RefPositions {#9@26 #11@27} physReg:NA Preferences=[rcx]
Interval  4: int (constant) RefPositions {#19@32 #21@33} physReg:NA Preferences=[rax]

------------
REFPOSITIONS BEFORE VALIDATING INTERVALS: 
------------
<RefPosition #0   @1   RefTypeBB  BB01 regmask=[] minReg=1>
<RefPosition #1   @6   RefTypeDef <Ivl:0> CNS_INT BB01 regmask=[allInt] minReg=1>
<RefPosition #2   @8   RefTypeDef <Ivl:1> CNS_INT BB01 regmask=[allInt] minReg=1>
<RefPosition #3   @9   RefTypeUse <Ivl:0>  BB01 regmask=[allInt] minReg=1 last>
<RefPosition #4   @9   RefTypeUse <Ivl:1>  BB01 regmask=[allInt] minReg=1 last>
<RefPosition #5   @24  RefTypeDef <Ivl:2> CNS_INT BB01 regmask=[rcx] minReg=1>
<RefPosition #6   @25  RefTypeFixedReg <Reg:rcx>  BB01 regmask=[rcx] minReg=1>
<RefPosition #7   @25  RefTypeUse <Ivl:2>  BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #8   @26  RefTypeFixedReg <Reg:rcx>  BB01 regmask=[rcx] minReg=1>
<RefPosition #9   @26  RefTypeDef <Ivl:3> PUTARG_REG BB01 regmask=[rcx] minReg=1 fixed>
<RefPosition #10  @27  RefTypeFixedReg <Reg:rcx>  BB01 regmask=[rcx] minReg=1>
<RefPosition #11  @27  RefTypeUse <Ivl:3>  BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #12  @28  RefTypeKill <Reg:rax>  BB01 regmask=[rax] minReg=1 last>
<RefPosition #13  @28  RefTypeKill <Reg:rcx>  BB01 regmask=[rcx] minReg=1 last>
<RefPosition #14  @28  RefTypeKill <Reg:rdx>  BB01 regmask=[rdx] minReg=1 last>
<RefPosition #15  @28  RefTypeKill <Reg:r8 >  BB01 regmask=[r8] minReg=1 last>
<RefPosition #16  @28  RefTypeKill <Reg:r9 >  BB01 regmask=[r9] minReg=1 last>
<RefPosition #17  @28  RefTypeKill <Reg:r10>  BB01 regmask=[r10] minReg=1 last>
<RefPosition #18  @28  RefTypeKill <Reg:r11>  BB01 regmask=[r11] minReg=1 last>
<RefPosition #19  @32  RefTypeDef <Ivl:4> CNS_INT BB01 regmask=[rax] minReg=1>
<RefPosition #20  @33  RefTypeFixedReg <Reg:rax>  BB01 regmask=[rax] minReg=1>
<RefPosition #21  @33  RefTypeUse <Ivl:4>  BB01 regmask=[rax] minReg=1 last fixed>
TUPLE STYLE DUMP WITH REF POSITIONS
Incoming Parameters: 
BB01 [000..042) (return), preds={} succs={}
=====
  N003.                    IL_OFFSET IL offset: 0x0
  N005.                    CNS_INT(h) 0x7ffd8eef4abc static Fseq[i]
        Def:<I0>(#1)
  N007.                    CNS_INT   0
        Def:<I1>(#2)
  N009.                    STOREIND 
                               Use:<I0>(#3) *
                               Use:<I1>(#4) *
  N011.                    IL_OFFSET IL offset: 0x6
  N013.                    IL_OFFSET IL offset: 0xe
  N015.                    IL_OFFSET IL offset: 0x1f
  N017.                    IL_OFFSET IL offset: 0x2e
  N019.                    IL_OFFSET IL offset: 0x30
  N021.                    IL_OFFSET IL offset: 0x37
  N023.                    CNS_INT   0
        Def:<I2>(#5)
  N025.                    PUTARG_REG
                               Use:<I2>(#7) Fixed:rcx(#6) *
        Def:<I3>(#9) rcx
  N027.                    CALL     
                               Use:<I3>(#11) Fixed:rcx(#10) *
        Kill: rax rcx rdx r8 r9 r10 r11 
  N029.                    IL_OFFSET IL offset: 0x3d
  N031.                    CNS_INT   93
        Def:<I4>(#19)
  N033.                    RETURN   
                               Use:<I4>(#21) Fixed:rax(#20) *




Linear scan intervals after buildIntervals:
Interval  0: long (constant) RefPositions {#1@6 #3@9} physReg:NA Preferences=[allInt]
Interval  1: int (constant) RefPositions {#2@8 #4@9} physReg:NA Preferences=[allInt]
Interval  2: int (constant) RefPositions {#5@24 #7@25} physReg:NA Preferences=[rcx]
Interval  3: int RefPositions {#9@26 #11@27} physReg:NA Preferences=[rcx]
Interval  4: int (constant) RefPositions {#19@32 #21@33} physReg:NA Preferences=[rax]

*************** In LinearScan::allocateRegisters()

Linear scan intervals before allocateRegisters:
Interval  0: long (constant) RefPositions {#1@6 #3@9} physReg:NA Preferences=[allInt]
Interval  1: int (constant) RefPositions {#2@8 #4@9} physReg:NA Preferences=[allInt]
Interval  2: int (constant) RefPositions {#5@24 #7@25} physReg:NA Preferences=[rcx]
Interval  3: int RefPositions {#9@26 #11@27} physReg:NA Preferences=[rcx]
Interval  4: int (constant) RefPositions {#19@32 #21@33} physReg:NA Preferences=[rax]

------------
REFPOSITIONS BEFORE ALLOCATION: 
------------
<RefPosition #0   @1   RefTypeBB  BB01 regmask=[] minReg=1>
<RefPosition #1   @6   RefTypeDef <Ivl:0> CNS_INT BB01 regmask=[allInt] minReg=1>
<RefPosition #2   @8   RefTypeDef <Ivl:1> CNS_INT BB01 regmask=[allInt] minReg=1>
<RefPosition #3   @9   RefTypeUse <Ivl:0>  BB01 regmask=[allInt] minReg=1 last>
<RefPosition #4   @9   RefTypeUse <Ivl:1>  BB01 regmask=[allInt] minReg=1 last>
<RefPosition #5   @24  RefTypeDef <Ivl:2> CNS_INT BB01 regmask=[rcx] minReg=1>
<RefPosition #6   @25  RefTypeFixedReg <Reg:rcx>  BB01 regmask=[rcx] minReg=1>
<RefPosition #7   @25  RefTypeUse <Ivl:2>  BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #8   @26  RefTypeFixedReg <Reg:rcx>  BB01 regmask=[rcx] minReg=1>
<RefPosition #9   @26  RefTypeDef <Ivl:3> PUTARG_REG BB01 regmask=[rcx] minReg=1 fixed>
<RefPosition #10  @27  RefTypeFixedReg <Reg:rcx>  BB01 regmask=[rcx] minReg=1>
<RefPosition #11  @27  RefTypeUse <Ivl:3>  BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #12  @28  RefTypeKill <Reg:rax>  BB01 regmask=[rax] minReg=1 last>
<RefPosition #13  @28  RefTypeKill <Reg:rcx>  BB01 regmask=[rcx] minReg=1 last>
<RefPosition #14  @28  RefTypeKill <Reg:rdx>  BB01 regmask=[rdx] minReg=1 last>
<RefPosition #15  @28  RefTypeKill <Reg:r8 >  BB01 regmask=[r8] minReg=1 last>
<RefPosition #16  @28  RefTypeKill <Reg:r9 >  BB01 regmask=[r9] minReg=1 last>
<RefPosition #17  @28  RefTypeKill <Reg:r10>  BB01 regmask=[r10] minReg=1 last>
<RefPosition #18  @28  RefTypeKill <Reg:r11>  BB01 regmask=[r11] minReg=1 last>
<RefPosition #19  @32  RefTypeDef <Ivl:4> CNS_INT BB01 regmask=[rax] minReg=1>
<RefPosition #20  @33  RefTypeFixedReg <Reg:rax>  BB01 regmask=[rax] minReg=1>
<RefPosition #21  @33  RefTypeUse <Ivl:4>  BB01 regmask=[rax] minReg=1 last fixed>

VAR REFPOSITIONS BEFORE ALLOCATION
--- V00
--- V01
--- V02
--- V03
--- V04
--- V05



Allocating Registers
--------------------
The following table has one or more rows for each RefPosition that is handled during allocation.
The first column provides the basic information about the RefPosition, with its type (e.g. Def,
Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the
action taken during allocation (e.g. Alloc a new register, or Keep an existing one).
The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is
active, a 'p' if it is a large vector that has been partially spilled, and 'i'if it is inactive.
Columns are only printed up to the last modifed register, which may increase during allocation,
in which case additional columns will appear.  
Registers which are not marked modified have ---- in their column.

------------------------------+----+----+----+----+----+----+----+----+----+
LocRP# Name Type  Action Reg  |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8  |r9  |
------------------------------+----+----+----+----+----+----+----+----+----+
                              |    |    |    |    |    |    |    |    |    |
 1.#0  BB1 PredBB0            |    |    |    |    |    |    |    |    |    |
 6.#1  C0   Def    Alloc rcx  |    |C0 a|    |    |    |    |    |    |    |
 8.#2  C1   Def    Alloc rax  |C1 a|C0 a|    |    |    |    |    |    |    |
 9.#3  C0   Use *  Keep  rcx  |C1 a|C0 a|    |    |    |    |    |    |    |
 9.#4  C1   Use *  Keep  rax  |C1 a|C0 a|    |    |    |    |    |    |    |
24.#5  C2   Def    Alloc rcx  |C1 i|C2 a|    |    |    |    |    |    |    |
25.#6  rcx  Fixd   Keep  rcx  |C1 i|C2 a|    |    |    |    |    |    |    |
25.#7  C2   Use *  Keep  rcx  |C1 i|C2 a|    |    |    |    |    |    |    |
26.#8  rcx  Fixd   Keep  rcx  |C1 i|    |    |    |    |    |    |    |    |
26.#9  I3   Def    Alloc rcx  |C1 i|I3 a|    |    |    |    |    |    |    |
27.#10 rcx  Fixd   Keep  rcx  |C1 i|I3 a|    |    |    |    |    |    |    |
27.#11 I3   Use *  Keep  rcx  |C1 i|I3 a|    |    |    |    |    |    |    |
28.#12 rax  Kill   Keep  rax  |    |    |    |    |    |    |    |    |    |
28.#13 rcx  Kill   Keep  rcx  |    |    |    |    |    |    |    |    |    |
28.#14 rdx  Kill   Keep  rdx  |    |    |    |    |    |    |    |    |    |
28.#15 r8   Kill   Keep  r8   |    |    |    |    |    |    |    |    |    |
28.#16 r9   Kill   Keep  r9   |    |    |    |    |    |    |    |    |    |
28.#17 r10  Kill   Keep  r10  |    |    |    |    |    |    |    |    |    |
28.#18 r11  Kill   Keep  r11  |    |    |    |    |    |    |    |    |    |
32.#19 C4   Def    Alloc rax  |C4 a|    |    |    |    |    |    |    |    |
33.#20 rax  Fixd   Keep  rax  |C4 a|    |    |    |    |    |    |    |    |
33.#21 C4   Use *  Keep  rax  |C4 i|    |    |    |    |    |    |    |    |

------------
REFPOSITIONS AFTER ALLOCATION: 
------------
<RefPosition #0   @1   RefTypeBB  BB01 regmask=[] minReg=1>
<RefPosition #1   @6   RefTypeDef <Ivl:0> CNS_INT BB01 regmask=[rcx] minReg=1>
<RefPosition #2   @8   RefTypeDef <Ivl:1> CNS_INT BB01 regmask=[rax] minReg=1>
<RefPosition #3   @9   RefTypeUse <Ivl:0>  BB01 regmask=[rcx] minReg=1 last>
<RefPosition #4   @9   RefTypeUse <Ivl:1>  BB01 regmask=[rax] minReg=1 last>
<RefPosition #5   @24  RefTypeDef <Ivl:2> CNS_INT BB01 regmask=[rcx] minReg=1>
<RefPosition #6   @25  RefTypeFixedReg <Reg:rcx>  BB01 regmask=[rcx] minReg=1>
<RefPosition #7   @25  RefTypeUse <Ivl:2>  BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #8   @26  RefTypeFixedReg <Reg:rcx>  BB01 regmask=[rcx] minReg=1>
<RefPosition #9   @26  RefTypeDef <Ivl:3> PUTARG_REG BB01 regmask=[rcx] minReg=1 fixed>
<RefPosition #10  @27  RefTypeFixedReg <Reg:rcx>  BB01 regmask=[rcx] minReg=1>
<RefPosition #11  @27  RefTypeUse <Ivl:3>  BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #12  @28  RefTypeKill <Reg:rax>  BB01 regmask=[rax] minReg=1 last>
<RefPosition #13  @28  RefTypeKill <Reg:rcx>  BB01 regmask=[rcx] minReg=1 last>
<RefPosition #14  @28  RefTypeKill <Reg:rdx>  BB01 regmask=[rdx] minReg=1 last>
<RefPosition #15  @28  RefTypeKill <Reg:r8 >  BB01 regmask=[r8] minReg=1 last>
<RefPosition #16  @28  RefTypeKill <Reg:r9 >  BB01 regmask=[r9] minReg=1 last>
<RefPosition #17  @28  RefTypeKill <Reg:r10>  BB01 regmask=[r10] minReg=1 last>
<RefPosition #18  @28  RefTypeKill <Reg:r11>  BB01 regmask=[r11] minReg=1 last>
<RefPosition #19  @32  RefTypeDef <Ivl:4> CNS_INT BB01 regmask=[rax] minReg=1>
<RefPosition #20  @33  RefTypeFixedReg <Reg:rax>  BB01 regmask=[rax] minReg=1>
<RefPosition #21  @33  RefTypeUse <Ivl:4>  BB01 regmask=[rax] minReg=1 last fixed>

VAR REFPOSITIONS AFTER ALLOCATION
--- V00
--- V01
--- V02
--- V03
--- V04
--- V05

Active intervals at end of allocation:

-----------------------
RESOLVING BB BOUNDARIES
-----------------------
Resolution Candidates: {}
Has NoCritical Edges

Prior to Resolution

BB01
use def in out
{}
{}
{}
{}
Var=Reg beg of BB01: none
Var=Reg end of BB01: none


RESOLVING EDGES
Trees after linear scan register allocator (LSRA)

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1        [000..042)        (return)                     i label target gcsafe LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..042) (return), preds={} succs={}
N001 (  0,  0) [000064] ------------        t64 =    PHI_ARG   struct V00 loc0         u:5 $VN.ZeroMap
N002 (  0,  0) [000063] ------------        t63 =    PHI_ARG   struct V00 loc0         u:4 $181
                                                  /--*  t64    struct 
                                                  +--*  t63    struct 
N003 (  0,  0) [000061] ------------        t61 = *  PHI       struct
                                                  /--*  t61    struct 
N005 (  0,  0) [000062] DA----------              *  STORE_LCL_VAR struct<GitHub_24159.Str1, 20> V00 loc0         d:3
N003 (???,???) [000067] ------------                 IL_OFFSET void   IL offset: 0x0 REG NA
N005 (  2, 10) [000057] H-----------        t57 =    CNS_INT(h) long   0x7ffd8eef4abc static Fseq[i] REG rcx $c0
N007 (  1,  1) [000000] ------------         t0 =    CNS_INT   int    0 REG rax $40
                                                  /--*  t57    long   
                                                  +--*  t0     int    
N009 (???,???) [000068] -A--G-------              *  STOREIND  int    REG NA
N011 (???,???) [000069] ------------                 IL_OFFSET void   IL offset: 0x6 REG NA
N013 (???,???) [000070] ------------                 IL_OFFSET void   IL offset: 0xe REG NA
N015 (???,???) [000072] ------------                 IL_OFFSET void   IL offset: 0x1f REG NA
N017 (???,???) [000073] ------------                 IL_OFFSET void   IL offset: 0x2e REG NA
N019 (???,???) [000074] ------------                 IL_OFFSET void   IL offset: 0x30 REG NA
N021 (???,???) [000075] ------------                 IL_OFFSET void   IL offset: 0x37 REG NA
N023 (  1,  1) [000065] ------------        t65 =    CNS_INT   int    0 REG rcx $40
                                                  /--*  t65    int    
N025 (???,???) [000080] ------------        t80 = *  PUTARG_REG int    REG rcx
                                                  /--*  t80    int    arg0 in rcx
N027 ( 15,  7) [000033] --CXG-------              *  CALL      void   System.Console.WriteLine REG NA $VN.Void
N029 (???,???) [000076] ------------                 IL_OFFSET void   IL offset: 0x3d REG NA
N031 (  1,  1) [000066] ------------        t66 =    CNS_INT   int    93 REG rax $45
                                                  /--*  t66    int    
N033 (  2,  2) [000037] ------------              *  RETURN    int    REG NA $1c3

-------------------------------------------------------------------------------------------------------------------

Final allocation
------------------------------+----+----+----+----+----+----+----+----+----+
LocRP# Name Type  Action Reg  |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8  |r9  |
------------------------------+----+----+----+----+----+----+----+----+----+
 1.#0  BB1 PredBB0            |    |    |    |    |    |    |    |    |    |
 6.#1  C0   Def    Alloc rcx  |    |C0 a|    |    |    |    |    |    |    |
 8.#2  C1   Def    Alloc rax  |C1 a|C0 a|    |    |    |    |    |    |    |
 9.#3  C0   Use *  Keep  rcx  |C1 a|C0 i|    |    |    |    |    |    |    |
 9.#4  C1   Use *  Keep  rax  |C1 i|    |    |    |    |    |    |    |    |
24.#5  C2   Def    Alloc rcx  |    |C2 a|    |    |    |    |    |    |    |
25.#6  rcx  Fixd   Keep  rcx  |    |C2 a|    |    |    |    |    |    |    |
25.#7  C2   Use *  Keep  rcx  |    |C2 i|    |    |    |    |    |    |    |
26.#8  rcx  Fixd   Keep  rcx  |    |    |    |    |    |    |    |    |    |
26.#9  I3   Def    Alloc rcx  |    |I3 a|    |    |    |    |    |    |    |
27.#10 rcx  Fixd   Keep  rcx  |    |I3 a|    |    |    |    |    |    |    |
27.#11 I3   Use *  Keep  rcx  |    |I3 i|    |    |    |    |    |    |    |
28.#12 rax  Kill   Keep  rax  |    |    |    |    |    |    |    |    |    |
28.#13 rcx  Kill   Keep  rcx  |    |    |    |    |    |    |    |    |    |
28.#14 rdx  Kill   Keep  rdx  |    |    |    |    |    |    |    |    |    |
28.#15 r8   Kill   Keep  r8   |    |    |    |    |    |    |    |    |    |
28.#16 r9   Kill   Keep  r9   |    |    |    |    |    |    |    |    |    |
28.#17 r10  Kill   Keep  r10  |    |    |    |    |    |    |    |    |    |
28.#18 r11  Kill   Keep  r11  |    |    |    |    |    |    |    |    |    |
32.#19 C4   Def    Alloc rax  |C4 a|    |    |    |    |    |    |    |    |
33.#20 rax  Fixd   Keep  rax  |C4 a|    |    |    |    |    |    |    |    |
33.#21 C4   Use *  Keep  rax  |C4 i|    |    |    |    |    |    |    |    |

Recording the maximum number of concurrent spills:

----------
LSRA Stats
----------
Total Tracked Vars:  3
Total Reg Cand Vars: 0
Total number of Intervals: 4
Total number of RefPositions: 21
Total Spill Count: 0    Weighted: 0
Total CopyReg Count: 0   Weighted: 0
Total ResolutionMov Count: 0    Weighted: 0
Total number of split edges: 0
Total Number of spill temps created: 0

TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
Incoming Parameters: 
BB01 [000..042) (return), preds={} succs={}
=====
  N003.                    IL_OFFSET IL offset: 0x0
  N005. rcx             =  CNS_INT(h) 0x7ffd8eef4abc static Fseq[i]
  N007. rax             =  CNS_INT   0
  N009.                    STOREIND ; rcx,rax
  N011.                    IL_OFFSET IL offset: 0x6
  N013.                    IL_OFFSET IL offset: 0xe
  N015.                    IL_OFFSET IL offset: 0x1f
  N017.                    IL_OFFSET IL offset: 0x2e
  N019.                    IL_OFFSET IL offset: 0x30
  N021.                    IL_OFFSET IL offset: 0x37
  N023. rcx             =  CNS_INT   0
  N025. rcx             =  PUTARG_REG; rcx
  N027.                    CALL     ; rcx
  N029.                    IL_OFFSET IL offset: 0x3d
  N031. rax             =  CNS_INT   93
  N033.                    RETURN   ; rax
Var=Reg end of BB01: none




*************** Finishing PHASE Linear scan register alloc
*************** In genGenerateCode()

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1        [000..042)        (return)                     i label target gcsafe LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Generate code
*************** In fgDebugCheckBBlist
Finalizing stack frame
Recording Var Locations at start of BB01
  <none>

Modified regs: [rax rcx rdx r8-r11]
Callee-saved registers pushed: 0 []
*************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
Assign V04 OutArgs, size=32, stkOffs=-0x28
--- delta bump 8 for RA
--- delta bump 40 for RSP frame
--- virtual stack offset to actual stack offset delta is 48
-- V04 was -40, now 8
; Final local variable assignments
;
;* V00 loc0         [V00,T00] (  0,  0   )  struct (24) zero-ref    do-not-enreg[SFB] ld-addr-op
;* V01 loc1         [V01    ] (  0,  0   )  struct (24) zero-ref    do-not-enreg[SB]
;* V02 loc2         [V02,T01] (  0,  0   )  struct (24) zero-ref    do-not-enreg[SFB]
;* V03 loc3         [V03,T02] (  0,  0   )     int  ->  zero-ref   
;  V04 OutArgs      [V04    ] (  1,  1   )  lclBlk (32) [rsp+0x00]   "OutgoingArgSpace"
;* V05 tmp1         [V05    ] (  0,  0   )  struct (24) zero-ref    do-not-enreg[SB] ld-addr-op overlapping-fields "Inlining Arg"
;
; Lcl frame size = 40
Setting stack level from -572662307 to 0

=============== Generating BB01 [000..042) (return), preds={} succs={} flags=0x00000000.400b0020: i label target gcsafe LIR 
BB01 IN (0)={} + ByrefExposed + GcHeap
     OUT(0)={}

Recording Var Locations at start of BB01
  <none>

Liveness not changing: 0000000000000000 {}
							Live regs: (unchanged) 00000000 {}
							GC regs: (unchanged) 00000000 {}
							Byref regs: (unchanged) 00000000 {}

      L_M60085_BB01:
Label: IG02, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}

Scope info: begin block BB01, IL range [000..042)
Scope info: open scopes =
   <none>
Added IP mapping: 0x0000 STACK_EMPTY (G_M60085_IG02,ins#0,ofs#0) label
Generating: N003 (???,???) [000067] ------------                 IL_OFFSET void   IL offset: 0x0 REG NA
Generating: N005 (  2, 10) [000057] H-----------        t57 =    CNS_INT(h) long   0x7ffd8eef4abc static Fseq[i] REG rcx $c0
IN0001:        mov      rcx, 0x7FFD8EEF4ABC
Generating: N007 (  1,  1) [000000] ------------         t0 =    CNS_INT   int    0 REG rax $40
IN0002:        xor      eax, eax
                                                              /--*  t57    long   
                                                              +--*  t0     int    
Generating: N009 (???,???) [000068] -A--G-------              *  STOREIND  int    REG NA
IN0003:        mov      dword ptr [rcx], eax
Added IP mapping: 0x0006 STACK_EMPTY (G_M60085_IG02,ins#3,ofs#14)
Generating: N011 (???,???) [000069] ------------                 IL_OFFSET void   IL offset: 0x6 REG NA
Added IP mapping: 0x000E STACK_EMPTY (G_M60085_IG02,ins#3,ofs#14)
Generating: N013 (???,???) [000070] ------------                 IL_OFFSET void   IL offset: 0xe REG NA
Added IP mapping: 0x001F STACK_EMPTY (G_M60085_IG02,ins#3,ofs#14)
Generating: N015 (???,???) [000072] ------------                 IL_OFFSET void   IL offset: 0x1f REG NA
Added IP mapping: 0x002E STACK_EMPTY (G_M60085_IG02,ins#3,ofs#14)
Generating: N017 (???,???) [000073] ------------                 IL_OFFSET void   IL offset: 0x2e REG NA
Added IP mapping: 0x0030 STACK_EMPTY (G_M60085_IG02,ins#3,ofs#14)
Generating: N019 (???,???) [000074] ------------                 IL_OFFSET void   IL offset: 0x30 REG NA
Added IP mapping: 0x0037 STACK_EMPTY (G_M60085_IG02,ins#3,ofs#14)
Generating: N021 (???,???) [000075] ------------                 IL_OFFSET void   IL offset: 0x37 REG NA
Generating: N023 (  1,  1) [000065] ------------        t65 =    CNS_INT   int    0 REG rcx $40
IN0004:        xor      ecx, ecx
                                                              /--*  t65    int    
Generating: N025 (???,???) [000080] ------------        t80 = *  PUTARG_REG int    REG rcx
                                                              /--*  t80    int    arg0 in rcx
Generating: N027 ( 15,  7) [000033] --CXG-------              *  CALL      void   System.Console.WriteLine REG NA $VN.Void
							Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
IN0005:        call     System.Console:WriteLine(int)
Added IP mapping: 0x003D STACK_EMPTY (G_M60085_IG02,ins#5,ofs#21)
Generating: N029 (???,???) [000076] ------------                 IL_OFFSET void   IL offset: 0x3d REG NA
Generating: N031 (  1,  1) [000066] ------------        t66 =    CNS_INT   int    93 REG rax $45
IN0006:        mov      eax, 93
                                                              /--*  t66    int    
Generating: N033 (  2,  2) [000037] ------------              *  RETURN    int    REG NA $1c3

Scope info: end block BB01, IL range [000..042)
Scope info: ending scope, LVnum=1 [000..042)
siEndScope: Failed to end scope for V01
Scope info: ending scope, LVnum=2 [000..042)
Scope info: ending scope, LVnum=3 [000..042)
Scope info: ending scope, LVnum=0 [000..042)
Scope info: open scopes =
   <none>
Added IP mapping: EPILOG STACK_EMPTY (G_M60085_IG02,ins#6,ofs#26) label
Reserving epilog IG for block BB01

      G_M60085_IG02:        ; offs=000000H, funclet=00, bbWeight=1   
*************** After placeholder IG creation
G_M60085_IG01:        ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M60085_IG02:        ; offs=000000H, size=001AH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M60085_IG03:        ; epilog placeholder, next placeholder=<END>, BB01 [0000], epilog, extend <-- First placeholder <-- Last placeholder
                      ;   PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
                      ;   InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
Liveness not changing: 0000000000000000 {}

# compCycleEstimate =     56, compSizeEstimate =    62 GitHub_24159.Test:Test2():int
; Final local variable assignments
;
;* V00 loc0         [V00,T00] (  0,  0   )  struct (24) zero-ref    do-not-enreg[SFB] ld-addr-op
;* V01 loc1         [V01    ] (  0,  0   )  struct (24) zero-ref    do-not-enreg[SB]
;* V02 loc2         [V02,T01] (  0,  0   )  struct (24) zero-ref    do-not-enreg[SFB]
;* V03 loc3         [V03,T02] (  0,  0   )     int  ->  zero-ref   
;  V04 OutArgs      [V04    ] (  1,  1   )  lclBlk (32) [rsp+0x00]   "OutgoingArgSpace"
;* V05 tmp1         [V05    ] (  0,  0   )  struct (24) zero-ref    do-not-enreg[SB] ld-addr-op overlapping-fields "Inlining Arg"
;
; Lcl frame size = 40
*************** Before prolog / epilog generation
G_M60085_IG01:        ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M60085_IG02:        ; offs=000000H, size=001AH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M60085_IG03:        ; epilog placeholder, next placeholder=<END>, BB01 [0000], epilog, extend <-- First placeholder <-- Last placeholder
                      ;   PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
                      ;   InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
Recording Var Locations at start of BB01
  <none>

*************** In genFnProlog()
Added IP mapping to front: PROLOG STACK_EMPTY (G_M60085_IG01,ins#0,ofs#0) label

__prolog:
IN0007:        sub      rsp, 40
*************** In genEnregisterIncomingStackArgs()


      G_M60085_IG01:        ; offs=000000H, funclet=00, bbWeight=1   
*************** In genFnEpilog()

__epilog:
gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=00000000 {}, gcRegByrefSetCur=00000000 {}
IN0008:        add      rsp, 40
IN0009:        ret      

      G_M60085_IG03:        ; offs=00001AH, funclet=00, bbWeight=1   
0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs
*************** After prolog / epilog generation
G_M60085_IG01:        ; func=00, offs=000000H, size=0004H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
G_M60085_IG02:        ; offs=000004H, size=001AH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M60085_IG03:        ; offs=00001EH, size=0005H, epilog, nogc, extend
*************** In emitJumpDistBind()

*************** Finishing PHASE Generate code

*************** Starting PHASE Emit code

Hot  code size = 0x23 bytes
Cold code size = 0x0 bytes
reserveUnwindInfo(isFunclet=FALSE, isColdCode=FALSE, unwindSize=0x6)
*************** In emitEndCodeGen()
Converting emitMaxStackDepth from bytes (0) to elements (0)

***************************************************************************
Instructions as they come out of the scheduler


G_M60085_IG01:        ; func=00, offs=000000H, size=0004H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
IN0007: 000000 4883EC28             sub      rsp, 40
						;; bbWeight=1    PerfScore 0.25
G_M60085_IG02:        ; func=00, offs=000004H, size=001AH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
IN0001: 000004 48B9BC4AEF8EFD7F0000 mov      rcx, 0x7FFD8EEF4ABC
IN0002: 00000E 33C0                 xor      eax, eax
IN0003: 000010 8901                 mov      dword ptr [rcx], eax
IN0004: 000012 33C9                 xor      ecx, ecx
[2A2F1E60] ptr arg pop  0
IN0005: 000014 E8A792FFFF           call     System.Console:WriteLine(int)
IN0006: 000019 B85D000000           mov      eax, 93
						;; bbWeight=1    PerfScore 3.00
G_M60085_IG03:        ; func=00, offs=00001EH, size=0005H, epilog, nogc, extend
IN0008: 00001E 4883C428             add      rsp, 40
IN0009: 000022 C3                   ret      
						;; bbWeight=1    PerfScore 1.25Allocated method code size =   35 , actual size =   35

; Total bytes of code 35, prolog size 4, PerfScore 8.00, instruction count 9 (MethodHash=5a8a154a) for method GitHub_24159.Test:Test2():int
; ============================================================

*************** After end code gen, before unwindEmit()
G_M60085_IG01:        ; func=00, offs=000000H, size=0004H, bbWeight=1    PerfScore 0.25, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG

IN0007: 000000 sub      rsp, 40

G_M60085_IG02:        ; offs=000004H, size=001AH, bbWeight=1    PerfScore 3.00, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref

IN0001: 000004 mov      rcx, 0x7FFD8EEF4ABC
IN0002: 00000E xor      eax, eax
IN0003: 000010 mov      dword ptr [rcx], eax
IN0004: 000012 xor      ecx, ecx
IN0005: 000014 call     System.Console:WriteLine(int)
IN0006: 000019 mov      eax, 93

G_M60085_IG03:        ; offs=00001EH, size=0005H, bbWeight=1    PerfScore 1.25, epilog, nogc, extend

IN0008: 00001E add      rsp, 40
IN0009: 000022 ret      


*************** Finishing PHASE Emit code

*************** Starting PHASE Emit GC+EH tables
Unwind Info:
  >> Start offset   : 0x000000 (not in unwind data)
  >>   End offset   : 0x000023 (not in unwind data)
  Version           : 1
  Flags             : 0x00
  SizeOfProlog      : 0x04
  CountOfUnwindCodes: 1
  FrameRegister     : none (0)
  FrameOffset       : N/A (no FrameRegister) (Value=0)
  UnwindCodes       :
    CodeOffset: 0x04 UnwindOp: UWOP_ALLOC_SMALL (2)     OpInfo: 4 * 8 + 8 = 40 = 0x28
allocUnwindInfo(pHotCode=0x00007FFD8ECEFDC0, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x23, unwindSize=0x6, pUnwindBlock=0x000002132A320892, funKind=0 (main function))
*************** In genIPmappingGen()
IP mapping count : 5
IL offs PROLOG : 0x00000000 ( STACK_EMPTY )
IL offs 0x0000 : 0x00000004 ( STACK_EMPTY )
IL offs 0x0037 : 0x00000012 ( STACK_EMPTY )
IL offs 0x003D : 0x00000019 ( STACK_EMPTY )
IL offs EPILOG : 0x0000001E ( STACK_EMPTY )

*************** In genSetScopeInfo()
VarLocInfo count is 0
; Variable debug info: 0 live range(s), 0 var(s) for method GitHub_24159.Test:Test2():int
*************** In gcInfoBlockHdrSave()
Set code length to 35.
Set ReturnKind to Scalar.
Set Outgoing stack arg area size to 32.
Defining 1 call sites:
    Offset 0x14, size 5.

*************** Finishing PHASE Emit GC+EH tables
Method code size: 35

Allocations for GitHub_24159.Test:Test2():int (MethodHash=5a8a154a)
count:        741, size:      69644, max =       3072
allocateMemory:     131072, nraUsed:      74504

Alloc'd bytes by kind:
                  kind |       size |     pct
  ---------------------+------------+--------
         AssertionProp |       6460 |   9.28%
               ASTNode |      10688 |  15.35%
              InstDesc |       2320 |   3.33%
              ImpStack |        384 |   0.55%
            BasicBlock |       2248 |   3.23%
             fgArgInfo |         56 |   0.08%
       fgArgInfoPtrArr |          8 |   0.01%
              FlowList |        160 |   0.23%
     TreeStatementList |          0 |   0.00%
               SiScope |         24 |   0.03%
       DominatorMemory |        240 |   0.34%
                  LSRA |       3000 |   4.31%
         LSRA_Interval |        400 |   0.57%
      LSRA_RefPosition |       1408 |   2.02%
          Reachability |         16 |   0.02%
                   SSA |       1056 |   1.52%
           ValueNumber |       9749 |  14.00%
              LvaTable |       1944 |   2.79%
            UnwindInfo |          0 |   0.00%
                hashBv |        160 |   0.23%
                bitset |        200 |   0.29%
          FixedBitVect |         32 |   0.05%
               Generic |       2048 |   2.94%
   LocalAddressVisitor |          0 |   0.00%
         FieldSeqStore |        272 |   0.39%
    ZeroOffsetFieldMap |        120 |   0.17%
          ArrayInfoMap |         40 |   0.06%
          MemoryPhiArg |          0 |   0.00%
                   CSE |       1248 |   1.79%
                    GC |       1285 |   1.85%
       CorTailCallInfo |          0 |   0.00%
              Inlining |       1720 |   2.47%
            ArrayStack |          0 |   0.00%
             DebugInfo |        480 |   0.69%
             DebugOnly |      19762 |  28.38%
               Codegen |       1176 |   1.69%
               LoopOpt |          0 |   0.00%
             LoopHoist |          0 |   0.00%
               Unknown |        244 |   0.35%
            RangeCheck |          0 |   0.00%
              CopyProp |        408 |   0.59%
           SideEffects |          0 |   0.00%
       ObjectAllocator |          0 |   0.00%
    VariableLiveRanges |          0 |   0.00%
           ClassLayout |        112 |   0.16%
       TailMergeThrows |          0 |   0.00%
             EarlyProp |          0 |   0.00%
              ZeroInit |        176 |   0.25%

****** DONE compiling GitHub_24159.Test:Test2():int
0
Test2 failed
Expected: 100
Actual: 101
END EXECUTION - FAILED
FAILED