BadImageFormatException Microsoft.Cci.PdbWriter::CreateSymWriter32 ****** START compiling Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int (MethodHash=3a6fe5fa) Generating code for Windows x64 OPTIONS: compCodeOpt = BLENDED_CODE OPTIONS: compDbgCode = false OPTIONS: compDbgInfo = true OPTIONS: compDbgEnC = false OPTIONS: compProcedureSplitting = false OPTIONS: compProcedureSplittingEH = false IL to import: IL_0000 02 ldarg.0 IL_0001 7b 38 10 00 04 ldfld 0x4001038 IL_0006 6f 9a 00 00 0a callvirt 0xA00009A IL_000b 2d 0a brtrue.s 10 (IL_0017) IL_000d 04 ldarg.2 IL_000e 03 ldarg.1 IL_000f 6f 63 20 00 06 callvirt 0x6002063 IL_0014 55 stind.i8 IL_0015 17 ldc.i4.1 IL_0016 2a ret IL_0017 03 ldarg.1 IL_0018 6f 5b 20 00 06 callvirt 0x600205B IL_001d 17 ldc.i4.1 IL_001e 58 add IL_001f 0a stloc.0 IL_0020 16 ldc.i4.0 IL_0021 02 ldarg.0 IL_0022 7b 37 10 00 04 ldfld 0x4001037 IL_0027 28 3f 03 00 0a call 0xA00033F IL_002c 25 dup IL_002d 0f 00 ldarga.s 0x0 IL_002f 28 77 20 00 06 call 0x6002077 IL_0034 28 52 03 00 0a call 0xA000352 IL_0039 0b stloc.1 IL_003a 07 ldloc.1 IL_003b 59 sub IL_003c 0c stloc.2 IL_003d 16 ldc.i4.0 IL_003e 0d stloc.3 IL_003f 07 ldloc.1 IL_0040 13 04 stloc.s 0x4 IL_0042 11 04 ldloc.s 0x4 IL_0044 13 05 stloc.s 0x5 IL_0046 0f 00 ldarga.s 0x0 IL_0048 28 77 20 00 06 call 0x6002077 IL_004d 13 06 stloc.s 0x6 IL_004f 11 06 ldloc.s 0x6 IL_0051 11 05 ldloc.s 0x5 IL_0053 59 sub IL_0054 13 07 stloc.s 0x7 IL_0056 02 ldarg.0 IL_0057 09 ldloc.3 IL_0058 11 04 ldloc.s 0x4 IL_005a 28 eb 06 00 06 call 0x60006EB IL_005f 13 08 stloc.s 0x8 IL_0061 08 ldloc.2 IL_0062 16 ldc.i4.0 IL_0063 36 1d ble.un.s 29 (IL_0082) IL_0065 08 ldloc.2 IL_0066 6e conv.u8 IL_0067 03 ldarg.1 IL_0068 6f 5f 20 00 06 callvirt 0x600205F IL_006d 6a conv.i8 IL_006e 31 0a ble.s 10 (IL_007a) IL_0070 04 ldarg.2 IL_0071 03 ldarg.1 IL_0072 6f 64 20 00 06 callvirt 0x6002064 IL_0077 55 stind.i8 IL_0078 19 ldc.i4.3 IL_0079 2a ret IL_007a 12 08 ldloca.s 0x8 IL_007c 08 ldloc.2 IL_007d 28 f3 06 00 06 call 0x60006F3 IL_0082 11 08 ldloc.s 0x8 IL_0084 12 09 ldloca.s 0x9 IL_0086 28 ee 06 00 06 call 0x60006EE IL_008b 13 0a stloc.s 0xA IL_008d 11 0a ldloc.s 0xA IL_008f 06 ldloc.0 IL_0090 34 04 bge.un.s 4 (IL_0096) IL_0092 11 07 ldloc.s 0x7 IL_0094 2d 11 brtrue.s 17 (IL_00a7) IL_0096 11 09 ldloc.s 0x9 IL_0098 11 0a ldloc.s 0xA IL_009a 11 07 ldloc.s 0x7 IL_009c 16 ldc.i4.0 IL_009d fe 03 cgt.un IL_009f 03 ldarg.1 IL_00a0 04 ldarg.2 IL_00a1 28 ea 06 00 06 call 0x60006EA IL_00a6 2a ret IL_00a7 02 ldarg.0 IL_00a8 7b 37 10 00 04 ldfld 0x4001037 IL_00ad 16 ldc.i4.0 IL_00ae 32 04 blt.s 4 (IL_00b4) IL_00b0 11 07 ldloc.s 0x7 IL_00b2 2b 0a br.s 10 (IL_00be) IL_00b4 11 07 ldloc.s 0x7 IL_00b6 02 ldarg.0 IL_00b7 7b 37 10 00 04 ldfld 0x4001037 IL_00bc 65 neg IL_00bd 58 add IL_00be 13 0b stloc.s 0xB IL_00c0 11 0a ldloc.s 0xA IL_00c2 2d 1f brtrue.s 31 (IL_00e3) IL_00c4 11 0b ldloc.s 0xB IL_00c6 6e conv.u8 IL_00c7 0f 00 ldarga.s 0x0 IL_00c9 28 77 20 00 06 call 0x6002077 IL_00ce 6a conv.i8 IL_00cf 59 sub IL_00d0 03 ldarg.1 IL_00d1 6f 5f 20 00 06 callvirt 0x600205F IL_00d6 6a conv.i8 IL_00d7 31 0a ble.s 10 (IL_00e3) IL_00d9 04 ldarg.2 IL_00da 03 ldarg.1 IL_00db 6f 63 20 00 06 callvirt 0x6002063 IL_00e0 55 stind.i8 IL_00e1 18 ldc.i4.2 IL_00e2 2a ret IL_00e3 02 ldarg.0 IL_00e4 11 05 ldloc.s 0x5 IL_00e6 11 06 ldloc.s 0x6 IL_00e8 28 eb 06 00 06 call 0x60006EB IL_00ed 13 0c stloc.s 0xC IL_00ef 7e 9d 02 00 04 ldsfld 0x400029D IL_00f4 13 0d stloc.s 0xD IL_00f6 12 0d ldloca.s 0xD IL_00f8 11 0b ldloc.s 0xB IL_00fa 28 f3 06 00 06 call 0x60006F3 IL_00ff 11 0c ldloc.s 0xC IL_0101 28 ef 06 00 06 call 0x60006EF IL_0106 13 0e stloc.s 0xE IL_0108 11 0d ldloc.s 0xD IL_010a 28 ef 06 00 06 call 0x60006EF IL_010f 13 0f stloc.s 0xF IL_0111 11 0f ldloc.s 0xF IL_0113 11 0e ldloc.s 0xE IL_0115 35 03 bgt.un.s 3 (IL_011a) IL_0117 16 ldc.i4.0 IL_0118 2b 05 br.s 5 (IL_011f) IL_011a 11 0f ldloc.s 0xF IL_011c 11 0e ldloc.s 0xE IL_011e 59 sub IL_011f 13 10 stloc.s 0x10 IL_0121 11 10 ldloc.s 0x10 IL_0123 16 ldc.i4.0 IL_0124 36 09 ble.un.s 9 (IL_012f) IL_0126 12 0c ldloca.s 0xC IL_0128 11 10 ldloc.s 0x10 IL_012a 28 f2 06 00 06 call 0x60006F2 IL_012f 06 ldloc.0 IL_0130 11 0a ldloc.s 0xA IL_0132 59 sub IL_0133 13 11 stloc.s 0x11 IL_0135 11 11 ldloc.s 0x11 IL_0137 13 12 stloc.s 0x12 IL_0139 11 0a ldloc.s 0xA IL_013b 16 ldc.i4.0 IL_013c 36 1e ble.un.s 30 (IL_015c) IL_013e 11 10 ldloc.s 0x10 IL_0140 11 12 ldloc.s 0x12 IL_0142 36 11 ble.un.s 17 (IL_0155) IL_0144 11 09 ldloc.s 0x9 IL_0146 11 0a ldloc.s 0xA IL_0148 11 07 ldloc.s 0x7 IL_014a 16 ldc.i4.0 IL_014b fe 03 cgt.un IL_014d 03 ldarg.1 IL_014e 04 ldarg.2 IL_014f 28 ea 06 00 06 call 0x60006EA IL_0154 2a ret IL_0155 11 12 ldloc.s 0x12 IL_0157 11 10 ldloc.s 0x10 IL_0159 59 sub IL_015a 13 12 stloc.s 0x12 IL_015c 11 0c ldloc.s 0xC IL_015e 11 0d ldloc.s 0xD IL_0160 28 c3 03 00 0a call 0xA0003C3 IL_0165 2d 04 brtrue.s 4 (IL_016b) IL_0167 11 10 ldloc.s 0x10 IL_0169 2b 04 br.s 4 (IL_016f) IL_016b 11 10 ldloc.s 0x10 IL_016d 17 ldc.i4.1 IL_016e 58 add IL_016f 13 13 stloc.s 0x13 IL_0171 12 0c ldloca.s 0xC IL_0173 11 12 ldloc.s 0x12 IL_0175 28 f2 06 00 06 call 0x60006F2 IL_017a 11 0c ldloc.s 0xC IL_017c 11 0d ldloc.s 0xD IL_017e 12 14 ldloca.s 0x14 IL_0180 28 c4 03 00 0a call 0xA0003C4 IL_0185 28 c5 03 00 0a call 0xA0003C5 IL_018a 13 15 stloc.s 0x15 IL_018c 12 14 ldloca.s 0x14 IL_018e 28 c6 03 00 0a call 0xA0003C6 IL_0193 13 16 stloc.s 0x16 IL_0195 11 15 ldloc.s 0x15 IL_0197 28 ec 06 00 06 call 0x60006EC IL_019c 13 17 stloc.s 0x17 IL_019e 11 17 ldloc.s 0x17 IL_01a0 11 11 ldloc.s 0x11 IL_01a2 36 2c ble.un.s 44 (IL_01d0) IL_01a4 11 17 ldloc.s 0x17 IL_01a6 11 11 ldloc.s 0x11 IL_01a8 59 sub IL_01a9 13 1a stloc.s 0x1A IL_01ab 11 16 ldloc.s 0x16 IL_01ad 2c 14 brfalse.s 20 (IL_01c3) IL_01af 11 15 ldloc.s 0x15 IL_01b1 17 ldc.i4.1 IL_01b2 6a conv.i8 IL_01b3 11 1a ldloc.s 0x1A IL_01b5 1f 3f ldc.i4.s 0x3F IL_01b7 5f and IL_01b8 62 shl IL_01b9 17 ldc.i4.1 IL_01ba 6a conv.i8 IL_01bb 59 sub IL_01bc 5f and IL_01bd 16 ldc.i4.0 IL_01be 6a conv.i8 IL_01bf fe 01 ceq IL_01c1 2b 01 br.s 1 (IL_01c4) IL_01c3 16 ldc.i4.0 IL_01c4 13 16 stloc.s 0x16 IL_01c6 11 15 ldloc.s 0x15 IL_01c8 11 1a ldloc.s 0x1A IL_01ca 1f 3f ldc.i4.s 0x3F IL_01cc 5f and IL_01cd 64 shr.un IL_01ce 13 15 stloc.s 0x15 IL_01d0 11 08 ldloc.s 0x8 IL_01d2 28 c5 03 00 0a call 0xA0003C5 IL_01d7 11 11 ldloc.s 0x11 IL_01d9 1f 3f ldc.i4.s 0x3F IL_01db 5f and IL_01dc 62 shl IL_01dd 11 15 ldloc.s 0x15 IL_01df 58 add IL_01e0 13 18 stloc.s 0x18 IL_01e2 11 0a ldloc.s 0xA IL_01e4 16 ldc.i4.0 IL_01e5 35 07 bgt.un.s 7 (IL_01ee) IL_01e7 11 13 ldloc.s 0x13 IL_01e9 65 neg IL_01ea 17 ldc.i4.1 IL_01eb 59 sub IL_01ec 2b 04 br.s 4 (IL_01f2) IL_01ee 11 0a ldloc.s 0xA IL_01f0 18 ldc.i4.2 IL_01f1 59 sub IL_01f2 13 19 stloc.s 0x19 IL_01f4 03 ldarg.1 IL_01f5 11 18 ldloc.s 0x18 IL_01f7 11 19 ldloc.s 0x19 IL_01f9 11 16 ldloc.s 0x16 IL_01fb 04 ldarg.2 IL_01fc 6f 65 20 00 06 callvirt 0x6002065 IL_0201 2a ret Marking V00 as a byref parameter Arg #0 passed in register(s) rcx lvaSetClass: setting class for V01 to (00000000D1FFAB1E) FloatingPointType Arg #1 passed in register(s) rdx Arg #2 passed in register(s) r8 lvaSetClass: setting class for V12 to (00000000D1FFAB1E) System.Byte[] lvaGrabTemp returning 30 (V30 tmp0) (a long lifetime temp) called for OutgoingArgSpace. ; Initial local variable assignments ; ; V00 arg0 struct ; V01 arg1 ref class-hnd ; V02 arg2 byref ; V03 loc0 int ; V04 loc1 int ; V05 loc2 int ; V06 loc3 int ; V07 loc4 int ; V08 loc5 int ; V09 loc6 int ; V10 loc7 int ; V11 loc8 struct ; V12 loc9 ref class-hnd ; V13 loc10 int ; V14 loc11 int ; V15 loc12 struct ; V16 loc13 struct ; V17 loc14 int ; V18 loc15 int ; V19 loc16 int ; V20 loc17 int ; V21 loc18 int ; V22 loc19 int ; V23 loc20 struct ; V24 loc21 long ; V25 loc22 bool ; V26 loc23 int ; V27 loc24 long ; V28 loc25 int ; V29 loc26 int ; V30 OutArgs lclBlk "OutgoingArgSpace" *************** In compInitDebuggingInfo() for Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int getVars() returned cVars = 0, extendOthers = true info.compVarScopesCount = 30 VarNum LVNum Name Beg End 0: 00h 00h V00 arg0 000h 202h 1: 01h 01h V01 arg1 000h 202h 2: 02h 02h V02 arg2 000h 202h 3: 03h 03h V03 loc0 000h 202h 4: 04h 04h V04 loc1 000h 202h 5: 05h 05h V05 loc2 000h 202h 6: 06h 06h V06 loc3 000h 202h 7: 07h 07h V07 loc4 000h 202h 8: 08h 08h V08 loc5 000h 202h 9: 09h 09h V09 loc6 000h 202h 10: 0Ah 0Ah V10 loc7 000h 202h 11: 0Bh 0Bh V11 loc8 000h 202h 12: 0Ch 0Ch V12 loc9 000h 202h 13: 0Dh 0Dh V13 loc10 000h 202h 14: 0Eh 0Eh V14 loc11 000h 202h 15: 0Fh 0Fh V15 loc12 000h 202h 16: 10h 10h V16 loc13 000h 202h 17: 11h 11h V17 loc14 000h 202h 18: 12h 12h V18 loc15 000h 202h 19: 13h 13h V19 loc16 000h 202h 20: 14h 14h V20 loc17 000h 202h 21: 15h 15h V21 loc18 000h 202h 22: 16h 16h V22 loc19 000h 202h 23: 17h 17h V23 loc20 000h 202h 24: 18h 18h V24 loc21 000h 202h 25: 19h 19h V25 loc22 000h 202h 26: 1Ah 1Ah V26 loc23 000h 202h 27: 1Bh 1Bh V27 loc24 000h 202h 28: 1Ch 1Ch V28 loc25 000h 202h 29: 1Dh 1Dh V29 loc26 000h 202h info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE ) *************** In fgFindBasicBlocks() for Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int Marked V03 as a single def local Marked V04 as a single def local Marked V05 as a single def local Marked V06 as a single def local Marked V07 as a single def local Marked V08 as a single def local Marked V09 as a single def local Marked V10 as a single def local Marked V13 as a single def local Marked V14 as a single def local Marked V17 as a single def local Marked V18 as a single def local Marked V19 as a single def local Marked V20 as a single def local Marked V22 as a single def local Marked V26 as a single def local Marked V27 as a single def local Marked V28 as a single def local Marked V29 as a single def local Jump targets: IL_0017 IL_007a IL_0082 IL_0096 IL_00a7 IL_00b4 IL_00be IL_00e3 IL_011a IL_011f IL_012f IL_0155 IL_015c IL_016b IL_016f IL_01c3 IL_01c4 IL_01d0 IL_01ee IL_01f2 New Basic Block BB01 [0000] created. BB01 [000..00D) New Basic Block BB02 [0001] created. BB02 [00D..017) New Basic Block BB03 [0002] created. BB03 [017..065) New Basic Block BB04 [0003] created. BB04 [065..070) New Basic Block BB05 [0004] created. BB05 [070..07A) New Basic Block BB06 [0005] created. BB06 [07A..082) New Basic Block BB07 [0006] created. BB07 [082..092) New Basic Block BB08 [0007] created. BB08 [092..096) New Basic Block BB09 [0008] created. BB09 [096..0A7) New Basic Block BB10 [0009] created. BB10 [0A7..0B0) New Basic Block BB11 [0010] created. BB11 [0B0..0B4) New Basic Block BB12 [0011] created. BB12 [0B4..0BE) New Basic Block BB13 [0012] created. BB13 [0BE..0C4) New Basic Block BB14 [0013] created. BB14 [0C4..0D9) New Basic Block BB15 [0014] created. BB15 [0D9..0E3) New Basic Block BB16 [0015] created. BB16 [0E3..117) New Basic Block BB17 [0016] created. BB17 [117..11A) New Basic Block BB18 [0017] created. BB18 [11A..11F) New Basic Block BB19 [0018] created. BB19 [11F..126) New Basic Block BB20 [0019] created. BB20 [126..12F) New Basic Block BB21 [0020] created. BB21 [12F..13E) New Basic Block BB22 [0021] created. BB22 [13E..144) New Basic Block BB23 [0022] created. BB23 [144..155) New Basic Block BB24 [0023] created. BB24 [155..15C) New Basic Block BB25 [0024] created. BB25 [15C..167) New Basic Block BB26 [0025] created. BB26 [167..16B) New Basic Block BB27 [0026] created. BB27 [16B..16F) New Basic Block BB28 [0027] created. BB28 [16F..1A4) New Basic Block BB29 [0028] created. BB29 [1A4..1AF) New Basic Block BB30 [0029] created. BB30 [1AF..1C3) New Basic Block BB31 [0030] created. BB31 [1C3..1C4) New Basic Block BB32 [0031] created. BB32 [1C4..1D0) New Basic Block BB33 [0032] created. BB33 [1D0..1E7) New Basic Block BB34 [0033] created. BB34 [1E7..1EE) New Basic Block BB35 [0034] created. BB35 [1EE..1F2) New Basic Block BB36 [0035] created. BB36 [1F2..202) IL Code Size,Instr 514, 252, Basic Block count 36, Local Variable Num,Ref count 31,128 for method Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int OPTIONS: opts.MinOpts() == false Basic block list for 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..00D)-> BB03 ( cond ) BB02 [0001] 1 1 [00D..017) (return) BB03 [0002] 1 1 [017..065)-> BB07 ( cond ) BB04 [0003] 1 1 [065..070)-> BB06 ( cond ) BB05 [0004] 1 1 [070..07A) (return) BB06 [0005] 1 1 [07A..082) BB07 [0006] 2 1 [082..092)-> BB09 ( cond ) BB08 [0007] 1 1 [092..096)-> BB10 ( cond ) BB09 [0008] 2 1 [096..0A7) (return) BB10 [0009] 1 1 [0A7..0B0)-> BB12 ( cond ) BB11 [0010] 1 1 [0B0..0B4)-> BB13 (always) BB12 [0011] 1 1 [0B4..0BE) BB13 [0012] 2 1 [0BE..0C4)-> BB16 ( cond ) BB14 [0013] 1 1 [0C4..0D9)-> BB16 ( cond ) BB15 [0014] 1 1 [0D9..0E3) (return) BB16 [0015] 2 1 [0E3..117)-> BB18 ( cond ) BB17 [0016] 1 1 [117..11A)-> BB19 (always) BB18 [0017] 1 1 [11A..11F) BB19 [0018] 2 1 [11F..126)-> BB21 ( cond ) BB20 [0019] 1 1 [126..12F) BB21 [0020] 2 1 [12F..13E)-> BB25 ( cond ) BB22 [0021] 1 1 [13E..144)-> BB24 ( cond ) BB23 [0022] 1 1 [144..155) (return) BB24 [0023] 1 1 [155..15C) BB25 [0024] 2 1 [15C..167)-> BB27 ( cond ) BB26 [0025] 1 1 [167..16B)-> BB28 (always) BB27 [0026] 1 1 [16B..16F) BB28 [0027] 2 1 [16F..1A4)-> BB33 ( cond ) BB29 [0028] 1 1 [1A4..1AF)-> BB31 ( cond ) BB30 [0029] 1 1 [1AF..1C3)-> BB32 (always) BB31 [0030] 1 1 [1C3..1C4) BB32 [0031] 2 1 [1C4..1D0) BB33 [0032] 2 1 [1D0..1E7)-> BB35 ( cond ) BB34 [0033] 1 1 [1E7..1EE)-> BB36 (always) BB35 [0034] 1 1 [1EE..1F2) BB36 [0035] 2 1 [1F2..202) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Pre-import *************** Finishing PHASE Pre-import *************** Starting PHASE Importation *************** In impImport() for Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int impImportBlockPending for BB01 Importing BB01 (PC=000) of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 04001038 [ 1] 6 (0x006) callvirt 0A00009A In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is int, structSize is 0 [ 1] 11 (0x00b) brtrue.s STMT00000 (IL 0x000... ???) [000006] ---XG------- * JTRUE void [000005] ---XG------- \--* NE int [000003] ---XG------- +--* ARR_LENGTH int [000002] ----G------- | \--* FIELD ref Mantissa [000001] ------------ | \--* ADDR byref [000000] -------N---- | \--* LCL_VAR struct V00 arg0 [000004] ------------ \--* CNS_INT int 0 impImportBlockPending for BB02 impImportBlockPending for BB03 Importing BB03 (PC=023) of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' [ 0] 23 (0x017) ldarg.1 [ 1] 24 (0x018) callvirt 0600205B In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is ushort, structSize is 0 STMT00001 (IL 0x017... ???) [000008] I-C-G------- * CALL nullcheck int FloatingPointType.get_NormalMantissaBits (exactContextHnd=0x00000000D1FFAB1E) [000007] ------------ this in rcx \--* LCL_VAR ref V01 arg1 [ 1] 29 (0x01d) ldc.i4.1 1 [ 2] 30 (0x01e) add [ 1] 31 (0x01f) stloc.0 STMT00002 (IL ???... ???) [000013] -AC--------- * ASG int [000012] D------N---- +--* LCL_VAR int V03 loc0 [000011] --C--------- \--* ADD int [000009] --C--------- +--* RET_EXPR int (inl return from call [000008]) [000010] ------------ \--* CNS_INT int 1 [ 0] 32 (0x020) ldc.i4.0 0 [ 1] 33 (0x021) ldarg.0 [ 2] 34 (0x022) ldfld 04001037 [ 2] 39 (0x027) call 0A00033F In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 STMT00003 (IL 0x020... ???) [000018] I-C-G------- * CALL int System.Math.Max (exactContextHnd=0x00000000D1FFAB1E) [000014] ------------ arg0 +--* CNS_INT int 0 [000017] ----G------- arg1 \--* FIELD int Exponent [000016] ------------ \--* ADDR byref [000015] -------N---- \--* LCL_VAR struct V00 arg0 [ 1] 44 (0x02c) dup lvaGrabTemp returning 31 (V31 tmp1) called for dup spill. STMT00004 (IL ???... ???) [000021] -AC--------- * ASG int [000020] D------N---- +--* LCL_VAR int V31 tmp1 [000019] --C--------- \--* RET_EXPR int (inl return from call [000018]) [ 2] 45 (0x02d) ldarga.s 0 [ 3] 47 (0x02f) call 06002077 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 STMT00005 (IL ???... ???) [000026] I-C-G------- * CALL int DecimalFloatingPointString.get_MantissaCount (exactContextHnd=0x00000000D1FFAB1E) [000025] ------------ this in rcx \--* ADDR byref [000024] -------N---- \--* LCL_VAR struct V00 arg0 [ 3] 52 (0x034) call 0A000352 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 STMT00006 (IL ???... ???) [000028] I-C-G------- * CALL int System.Math.Min (exactContextHnd=0x00000000D1FFAB1E) [000023] ------------ arg0 +--* LCL_VAR int V31 tmp1 [000027] --C--------- arg1 \--* RET_EXPR int (inl return from call [000026]) [ 2] 57 (0x039) stloc.1 STMT00007 (IL ???... ???) [000031] -AC--------- * ASG int [000030] D------N---- +--* LCL_VAR int V04 loc1 [000029] --C--------- \--* RET_EXPR int (inl return from call [000028]) [ 1] 58 (0x03a) ldloc.1 [ 2] 59 (0x03b) sub [ 1] 60 (0x03c) stloc.2 STMT00008 (IL ???... ???) [000035] -A---------- * ASG int [000034] D------N---- +--* LCL_VAR int V05 loc2 [000033] ------------ \--* SUB int [000022] ------------ +--* LCL_VAR int V31 tmp1 [000032] ------------ \--* LCL_VAR int V04 loc1 [ 0] 61 (0x03d) ldc.i4.0 0 [ 1] 62 (0x03e) stloc.3 STMT00009 (IL 0x03D... ???) [000038] -A---------- * ASG int [000037] D------N---- +--* LCL_VAR int V06 loc3 [000036] ------------ \--* CNS_INT int 0 [ 0] 63 (0x03f) ldloc.1 [ 1] 64 (0x040) stloc.s 4 STMT00010 (IL 0x03F... ???) [000041] -A---------- * ASG int [000040] D------N---- +--* LCL_VAR int V07 loc4 [000039] ------------ \--* LCL_VAR int V04 loc1 [ 0] 66 (0x042) ldloc.s 4 [ 1] 68 (0x044) stloc.s 5 STMT00011 (IL 0x042... ???) [000044] -A---------- * ASG int [000043] D------N---- +--* LCL_VAR int V08 loc5 [000042] ------------ \--* LCL_VAR int V07 loc4 [ 0] 70 (0x046) ldarga.s 0 [ 1] 72 (0x048) call 06002077 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 STMT00012 (IL 0x046... ???) [000047] I-C-G------- * CALL int DecimalFloatingPointString.get_MantissaCount (exactContextHnd=0x00000000D1FFAB1E) [000046] ------------ this in rcx \--* ADDR byref [000045] -------N---- \--* LCL_VAR struct V00 arg0 [ 1] 77 (0x04d) stloc.s 6 STMT00013 (IL ???... ???) [000050] -AC--------- * ASG int [000049] D------N---- +--* LCL_VAR int V09 loc6 [000048] --C--------- \--* RET_EXPR int (inl return from call [000047]) [ 0] 79 (0x04f) ldloc.s 6 [ 1] 81 (0x051) ldloc.s 5 [ 2] 83 (0x053) sub [ 1] 84 (0x054) stloc.s 7 STMT00014 (IL 0x04F... ???) [000055] -A---------- * ASG int [000054] D------N---- +--* LCL_VAR int V10 loc7 [000053] ------------ \--* SUB int [000051] ------------ +--* LCL_VAR int V09 loc6 [000052] ------------ \--* LCL_VAR int V08 loc5 [ 0] 86 (0x056) ldarg.0 [ 1] 87 (0x057) ldloc.3 [ 2] 88 (0x058) ldloc.s 4 [ 3] 90 (0x05a) call 060006EB In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16 Calling impNormStructVal on: [000056] ------------ * LCL_VAR struct V00 arg0 resulting tree: [000061] n----------- * OBJ struct [000060] ------------ \--* ADDR byref [000056] -------N---- \--* LCL_VAR struct V00 arg0 STMT00015 (IL 0x056... ???) [000059] I-C-G------- * CALL struct Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger (exactContextHnd=0x00000000D1FFAB1E) [000061] n----------- arg0 +--* OBJ struct [000060] ------------ | \--* ADDR byref [000056] -------N---- | \--* LCL_VAR struct V00 arg0 [000057] ------------ arg1 +--* LCL_VAR int V06 loc3 [000058] ------------ arg2 \--* LCL_VAR int V07 loc4 [ 1] 95 (0x05f) stloc.s 8 STMT00016 (IL ???... ???) [000062] --C--------- * RET_EXPR void (inl return from call [000059]) [ 0] 97 (0x061) ldloc.2 [ 1] 98 (0x062) ldc.i4.0 0 [ 2] 99 (0x063) ble.un.s STMT00017 (IL 0x061... ???) [000068] ------------ * JTRUE void [000067] N--------U-- \--* LE int [000065] ------------ +--* LCL_VAR int V05 loc2 [000066] ------------ \--* CNS_INT int 0 impImportBlockPending for BB04 impImportBlockPending for BB07 Importing BB07 (PC=130) of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' [ 0] 130 (0x082) ldloc.s 8 [ 1] 132 (0x084) ldloca.s 9 [ 2] 134 (0x086) call 060006EE In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 Calling impNormStructVal on: [000069] ------------ * LCL_VAR struct V11 loc8 resulting tree: [000074] n----------- * OBJ struct [000073] ------------ \--* ADDR byref [000069] -------N---- \--* LCL_VAR struct V11 loc8 STMT00018 (IL 0x082... ???) [000072] I-C-G------- * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits (exactContextHnd=0x00000000D1FFAB1E) [000074] n----------- arg0 +--* OBJ struct [000073] ------------ | \--* ADDR byref [000069] -------N---- | \--* LCL_VAR struct V11 loc8 [000071] ------------ arg1 \--* ADDR byref [000070] -------N---- \--* LCL_VAR ref V12 loc9 [ 1] 139 (0x08b) stloc.s 10 STMT00019 (IL ???... ???) [000077] -AC--------- * ASG int [000076] D------N---- +--* LCL_VAR int V13 loc10 [000075] --C--------- \--* RET_EXPR int (inl return from call [000072]) [ 0] 141 (0x08d) ldloc.s 10 [ 1] 143 (0x08f) ldloc.0 [ 2] 144 (0x090) bge.un.s STMT00020 (IL 0x08D... ???) [000081] ------------ * JTRUE void [000080] N--------U-- \--* GE int [000078] ------------ +--* LCL_VAR int V13 loc10 [000079] ------------ \--* LCL_VAR int V03 loc0 impImportBlockPending for BB08 impImportBlockPending for BB09 Importing BB09 (PC=150) of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' [ 0] 150 (0x096) ldloc.s 9 [ 1] 152 (0x098) ldloc.s 10 [ 2] 154 (0x09a) ldloc.s 7 [ 3] 156 (0x09c) ldc.i4.0 0 [ 4] 157 (0x09d) cgt.un [ 3] 159 (0x09f) ldarg.1 [ 4] 160 (0x0a0) ldarg.2 [ 5] 161 (0x0a1) call 060006EA (Implicit Tail call: prefixFlags |= PREFIX_TAILCALL_IMPLICIT) In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 GTF_CALL_M_IMPLICIT_TAILCALL set for call [000089] INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' for 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' calling 'Microsoft.CodeAnalysis.RealParser:ConvertBigIntegerToFloatingPointBits(System.Byte[],int,bool,FloatingPointType,byref):int' INLINER: Marking Microsoft.CodeAnalysis.RealParser:ConvertBigIntegerToFloatingPointBits(System.Byte[],int,bool,FloatingPointType,byref):int as NOINLINE because of too many il bytes INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' [ 1] 166 (0x0a6) ret STMT00021 (IL 0x096... ???) [000090] --C-G------- * RETURN int [000089] --C-G------- \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits [000082] ------------ arg0 +--* LCL_VAR ref V12 loc9 [000083] ------------ arg1 +--* LCL_VAR int V13 loc10 [000086] N--------U-- arg2 +--* GT int [000084] ------------ | +--* LCL_VAR int V10 loc7 [000085] ------------ | \--* CNS_INT int 0 [000087] ------------ arg3 +--* LCL_VAR ref V01 arg1 [000088] ------------ arg4 \--* LCL_VAR byref V02 arg2 Importing BB08 (PC=146) of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' [ 0] 146 (0x092) ldloc.s 7 [ 1] 148 (0x094) brtrue.s STMT00022 (IL 0x092... ???) [000094] ------------ * JTRUE void [000093] ------------ \--* NE int [000091] ------------ +--* LCL_VAR int V10 loc7 [000092] ------------ \--* CNS_INT int 0 impImportBlockPending for BB09 impImportBlockPending for BB10 Importing BB10 (PC=167) of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' [ 0] 167 (0x0a7) ldarg.0 [ 1] 168 (0x0a8) ldfld 04001037 [ 1] 173 (0x0ad) ldc.i4.0 0 [ 2] 174 (0x0ae) blt.s STMT00023 (IL 0x0A7... ???) [000100] ----G------- * JTRUE void [000099] ----G------- \--* LT int [000097] ----G------- +--* FIELD int Exponent [000096] ------------ | \--* ADDR byref [000095] -------N---- | \--* LCL_VAR struct V00 arg0 [000098] ------------ \--* CNS_INT int 0 impImportBlockPending for BB11 impImportBlockPending for BB12 Importing BB12 (PC=180) of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' [ 0] 180 (0x0b4) ldloc.s 7 [ 1] 182 (0x0b6) ldarg.0 [ 2] 183 (0x0b7) ldfld 04001037 [ 2] 188 (0x0bc) neg [ 2] 189 (0x0bd) add *************** In impGetSpillTmpBase(BB12) lvaGrabTemps(1) returning 32..32 (long lifetime temps) called for IL Stack Entries *************** In fgComputeCheapPreds() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..00D)-> BB03 ( cond ) i idxlen BB02 [0001] 1 1 [00D..017) (return) BB03 [0002] 1 1 [017..065)-> BB07 ( cond ) i BB04 [0003] 1 1 [065..070)-> BB06 ( cond ) BB05 [0004] 1 1 [070..07A) (return) BB06 [0005] 1 1 [07A..082) BB07 [0006] 2 1 [082..092)-> BB09 ( cond ) i BB08 [0007] 1 1 [092..096)-> BB10 ( cond ) i BB09 [0008] 2 1 [096..0A7) (return) i BB10 [0009] 1 1 [0A7..0B0)-> BB12 ( cond ) i BB11 [0010] 1 1 [0B0..0B4)-> BB13 (always) BB12 [0011] 1 1 [0B4..0BE) BB13 [0012] 2 1 [0BE..0C4)-> BB16 ( cond ) BB14 [0013] 1 1 [0C4..0D9)-> BB16 ( cond ) BB15 [0014] 1 1 [0D9..0E3) (return) BB16 [0015] 2 1 [0E3..117)-> BB18 ( cond ) BB17 [0016] 1 1 [117..11A)-> BB19 (always) BB18 [0017] 1 1 [11A..11F) BB19 [0018] 2 1 [11F..126)-> BB21 ( cond ) BB20 [0019] 1 1 [126..12F) BB21 [0020] 2 1 [12F..13E)-> BB25 ( cond ) BB22 [0021] 1 1 [13E..144)-> BB24 ( cond ) BB23 [0022] 1 1 [144..155) (return) BB24 [0023] 1 1 [155..15C) BB25 [0024] 2 1 [15C..167)-> BB27 ( cond ) BB26 [0025] 1 1 [167..16B)-> BB28 (always) BB27 [0026] 1 1 [16B..16F) BB28 [0027] 2 1 [16F..1A4)-> BB33 ( cond ) BB29 [0028] 1 1 [1A4..1AF)-> BB31 ( cond ) BB30 [0029] 1 1 [1AF..1C3)-> BB32 (always) BB31 [0030] 1 1 [1C3..1C4) BB32 [0031] 2 1 [1C4..1D0) BB33 [0032] 2 1 [1D0..1E7)-> BB35 ( cond ) BB34 [0033] 1 1 [1E7..1EE)-> BB36 (always) BB35 [0034] 1 1 [1EE..1F2) BB36 [0035] 2 1 [1F2..202) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** After fgComputeCheapPreds() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd cheap preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..00D)-> BB03 ( cond ) i idxlen BB02 [0001] 1 BB01 1 [00D..017) (return) BB03 [0002] 1 BB01 1 [017..065)-> BB07 ( cond ) i BB04 [0003] 1 BB03 1 [065..070)-> BB06 ( cond ) BB05 [0004] 1 BB04 1 [070..07A) (return) BB06 [0005] 1 BB04 1 [07A..082) BB07 [0006] 2 BB06,BB03 1 [082..092)-> BB09 ( cond ) i BB08 [0007] 1 BB07 1 [092..096)-> BB10 ( cond ) i BB09 [0008] 2 BB08,BB07 1 [096..0A7) (return) i BB10 [0009] 1 BB08 1 [0A7..0B0)-> BB12 ( cond ) i BB11 [0010] 1 BB10 1 [0B0..0B4)-> BB13 (always) BB12 [0011] 1 BB10 1 [0B4..0BE) BB13 [0012] 2 BB12,BB11 1 [0BE..0C4)-> BB16 ( cond ) BB14 [0013] 1 BB13 1 [0C4..0D9)-> BB16 ( cond ) BB15 [0014] 1 BB14 1 [0D9..0E3) (return) BB16 [0015] 2 BB14,BB13 1 [0E3..117)-> BB18 ( cond ) BB17 [0016] 1 BB16 1 [117..11A)-> BB19 (always) BB18 [0017] 1 BB16 1 [11A..11F) BB19 [0018] 2 BB18,BB17 1 [11F..126)-> BB21 ( cond ) BB20 [0019] 1 BB19 1 [126..12F) BB21 [0020] 2 BB20,BB19 1 [12F..13E)-> BB25 ( cond ) BB22 [0021] 1 BB21 1 [13E..144)-> BB24 ( cond ) BB23 [0022] 1 BB22 1 [144..155) (return) BB24 [0023] 1 BB22 1 [155..15C) BB25 [0024] 2 BB24,BB21 1 [15C..167)-> BB27 ( cond ) BB26 [0025] 1 BB25 1 [167..16B)-> BB28 (always) BB27 [0026] 1 BB25 1 [16B..16F) BB28 [0027] 2 BB27,BB26 1 [16F..1A4)-> BB33 ( cond ) BB29 [0028] 1 BB28 1 [1A4..1AF)-> BB31 ( cond ) BB30 [0029] 1 BB29 1 [1AF..1C3)-> BB32 (always) BB31 [0030] 1 BB29 1 [1C3..1C4) BB32 [0031] 2 BB31,BB30 1 [1C4..1D0) BB33 [0032] 2 BB32,BB28 1 [1D0..1E7)-> BB35 ( cond ) BB34 [0033] 1 BB33 1 [1E7..1EE)-> BB36 (always) BB35 [0034] 1 BB33 1 [1EE..1F2) BB36 [0035] 2 BB35,BB34 1 [1F2..202) (return) ----------------------------------------------------------------------------------------------------------------------------------------- Spilling stack entries into temps STMT00024 (IL 0x0B4... ???) [000108] -A--G------- * ASG int [000107] D------N---- +--* LCL_VAR int V32 tmp2 [000106] ----G------- \--* ADD int [000101] ------------ +--* LCL_VAR int V10 loc7 [000105] ----G------- \--* NEG int [000104] ----G------- \--* FIELD int Exponent [000103] ------------ \--* ADDR byref [000102] -------N---- \--* LCL_VAR struct V00 arg0 impImportBlockPending for BB13 Importing BB13 (PC=190) of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' [ 1] 190 (0x0be) stloc.s 11 STMT00025 (IL ???... ???) [000112] -A---------- * ASG int [000111] D------N---- +--* LCL_VAR int V14 loc11 [000110] ------------ \--* LCL_VAR int V32 tmp2 [ 0] 192 (0x0c0) ldloc.s 10 [ 1] 194 (0x0c2) brtrue.s STMT00026 (IL 0x0C0... ???) [000116] ------------ * JTRUE void [000115] ------------ \--* NE int [000113] ------------ +--* LCL_VAR int V13 loc10 [000114] ------------ \--* CNS_INT int 0 impImportBlockPending for BB14 impImportBlockPending for BB16 Importing BB16 (PC=227) of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' [ 0] 227 (0x0e3) ldarg.0 [ 1] 228 (0x0e4) ldloc.s 5 [ 2] 230 (0x0e6) ldloc.s 6 [ 3] 232 (0x0e8) call 060006EB In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16 Calling impNormStructVal on: [000117] ------------ * LCL_VAR struct V00 arg0 resulting tree: [000122] n----------- * OBJ struct [000121] ------------ \--* ADDR byref [000117] -------N---- \--* LCL_VAR struct V00 arg0 STMT00027 (IL 0x0E3... ???) [000120] I-C-G------- * CALL struct Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger (exactContextHnd=0x00000000D1FFAB1E) [000122] n----------- arg0 +--* OBJ struct [000121] ------------ | \--* ADDR byref [000117] -------N---- | \--* LCL_VAR struct V00 arg0 [000118] ------------ arg1 +--* LCL_VAR int V08 loc5 [000119] ------------ arg2 \--* LCL_VAR int V09 loc6 [ 1] 237 (0x0ed) stloc.s 12 STMT00028 (IL ???... ???) [000123] --C--------- * RET_EXPR void (inl return from call [000120]) [ 0] 239 (0x0ef) ldsfld 0400029D [ 1] 244 (0x0f4) stloc.s 13 STMT00029 (IL 0x0EF... ???) [000133] H-CXG------- * CALL help long HELPER.CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE [000131] ------------ arg0 +--* CNS_INT long 0x7ff815262aa0 [000132] ------------ arg1 \--* CNS_INT int 173 STMT00030 (IL ???... ???) [000137] -A--G------- * ASG struct (copy) [000135] D------N---- +--* LCL_VAR struct V16 loc13 [000129] ----G------- \--* OBJ struct [000128] ----G------- \--* ADD byref [000126] ----G------- +--* FIELD ref BigOne [000127] ------------ \--* CNS_INT long 8 Fseq[#FirstElem] [ 0] 246 (0x0f6) ldloca.s 13 [ 1] 248 (0x0f8) ldloc.s 11 [ 2] 250 (0x0fa) call 060006F3 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 STMT00031 (IL 0x0F6... ???) [000141] I-C-G------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen (exactContextHnd=0x00000000D1FFAB1E) [000139] ------------ arg0 +--* ADDR byref [000138] -------N---- | \--* LCL_VAR struct V16 loc13 [000140] ------------ arg1 \--* LCL_VAR int V14 loc11 [ 0] 255 (0x0ff) ldloc.s 12 [ 1] 257 (0x101) call 060006EF In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 Calling impNormStructVal on: [000142] ------------ * LCL_VAR struct V15 loc12 resulting tree: [000145] n----------- * OBJ struct [000144] ------------ \--* ADDR byref [000142] -------N---- \--* LCL_VAR struct V15 loc12 STMT00032 (IL 0x0FF... ???) [000143] I-C-G------- * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits (exactContextHnd=0x00000000D1FFAB1E) [000145] n----------- arg0 \--* OBJ struct [000144] ------------ \--* ADDR byref [000142] -------N---- \--* LCL_VAR struct V15 loc12 [ 1] 262 (0x106) stloc.s 14 STMT00033 (IL ???... ???) [000148] -AC--------- * ASG int [000147] D------N---- +--* LCL_VAR int V17 loc14 [000146] --C--------- \--* RET_EXPR int (inl return from call [000143]) [ 0] 264 (0x108) ldloc.s 13 [ 1] 266 (0x10a) call 060006EF In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 Calling impNormStructVal on: [000149] ------------ * LCL_VAR struct V16 loc13 resulting tree: [000152] n----------- * OBJ struct [000151] ------------ \--* ADDR byref [000149] -------N---- \--* LCL_VAR struct V16 loc13 STMT00034 (IL 0x108... ???) [000150] I-C-G------- * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits (exactContextHnd=0x00000000D1FFAB1E) [000152] n----------- arg0 \--* OBJ struct [000151] ------------ \--* ADDR byref [000149] -------N---- \--* LCL_VAR struct V16 loc13 [ 1] 271 (0x10f) stloc.s 15 STMT00035 (IL ???... ???) [000155] -AC--------- * ASG int [000154] D------N---- +--* LCL_VAR int V18 loc15 [000153] --C--------- \--* RET_EXPR int (inl return from call [000150]) [ 0] 273 (0x111) ldloc.s 15 [ 1] 275 (0x113) ldloc.s 14 [ 2] 277 (0x115) bgt.un.s STMT00036 (IL 0x111... ???) [000159] ------------ * JTRUE void [000158] N--------U-- \--* GT int [000156] ------------ +--* LCL_VAR int V18 loc15 [000157] ------------ \--* LCL_VAR int V17 loc14 impImportBlockPending for BB17 impImportBlockPending for BB18 Importing BB18 (PC=282) of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' [ 0] 282 (0x11a) ldloc.s 15 [ 1] 284 (0x11c) ldloc.s 14 [ 2] 286 (0x11e) sub *************** In impGetSpillTmpBase(BB18) lvaGrabTemps(1) returning 33..33 (long lifetime temps) called for IL Stack Entries Spilling stack entries into temps STMT00037 (IL 0x11A... ???) [000164] -A---------- * ASG int [000163] D------N---- +--* LCL_VAR int V33 tmp3 [000162] ------------ \--* SUB int [000160] ------------ +--* LCL_VAR int V18 loc15 [000161] ------------ \--* LCL_VAR int V17 loc14 impImportBlockPending for BB19 Importing BB19 (PC=287) of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' [ 1] 287 (0x11f) stloc.s 16 STMT00038 (IL ???... ???) [000168] -A---------- * ASG int [000167] D------N---- +--* LCL_VAR int V19 loc16 [000166] ------------ \--* LCL_VAR int V33 tmp3 [ 0] 289 (0x121) ldloc.s 16 [ 1] 291 (0x123) ldc.i4.0 0 [ 2] 292 (0x124) ble.un.s STMT00039 (IL 0x121... ???) [000172] ------------ * JTRUE void [000171] N--------U-- \--* LE int [000169] ------------ +--* LCL_VAR int V19 loc16 [000170] ------------ \--* CNS_INT int 0 impImportBlockPending for BB20 impImportBlockPending for BB21 Importing BB21 (PC=303) of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' [ 0] 303 (0x12f) ldloc.0 [ 1] 304 (0x130) ldloc.s 10 [ 2] 306 (0x132) sub [ 1] 307 (0x133) stloc.s 17 STMT00040 (IL 0x12F... ???) [000177] -A---------- * ASG int [000176] D------N---- +--* LCL_VAR int V20 loc17 [000175] ------------ \--* SUB int [000173] ------------ +--* LCL_VAR int V03 loc0 [000174] ------------ \--* LCL_VAR int V13 loc10 [ 0] 309 (0x135) ldloc.s 17 [ 1] 311 (0x137) stloc.s 18 STMT00041 (IL 0x135... ???) [000180] -A---------- * ASG int [000179] D------N---- +--* LCL_VAR int V21 loc18 [000178] ------------ \--* LCL_VAR int V20 loc17 [ 0] 313 (0x139) ldloc.s 10 [ 1] 315 (0x13b) ldc.i4.0 0 [ 2] 316 (0x13c) ble.un.s STMT00042 (IL 0x139... ???) [000184] ------------ * JTRUE void [000183] N--------U-- \--* LE int [000181] ------------ +--* LCL_VAR int V13 loc10 [000182] ------------ \--* CNS_INT int 0 impImportBlockPending for BB22 impImportBlockPending for BB25 Importing BB25 (PC=348) of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' [ 0] 348 (0x15c) ldloc.s 12 [ 1] 350 (0x15e) ldloc.s 13 [ 2] 352 (0x160) call 0A0003C3 In Compiler::impImportCall: opcode is call, kind=0, callRetType is bool, structSize is 0 Calling impNormStructVal on: [000186] ------------ * LCL_VAR struct V16 loc13 resulting tree: [000189] n----------- * OBJ struct [000188] ------------ \--* ADDR byref [000186] -------N---- \--* LCL_VAR struct V16 loc13 Calling impNormStructVal on: [000185] ------------ * LCL_VAR struct V15 loc12 resulting tree: [000191] n----------- * OBJ struct [000190] ------------ \--* ADDR byref [000185] -------N---- \--* LCL_VAR struct V15 loc12 STMT00043 (IL 0x15C... ???) [000187] I-C-G------- * CALL int System.Numerics.BigInteger.op_LessThan (exactContextHnd=0x00000000D1FFAB1E) [000191] n----------- arg0 +--* OBJ struct [000190] ------------ | \--* ADDR byref [000185] -------N---- | \--* LCL_VAR struct V15 loc12 [000189] n----------- arg1 \--* OBJ struct [000188] ------------ \--* ADDR byref [000186] -------N---- \--* LCL_VAR struct V16 loc13 [ 1] 357 (0x165) brtrue.s STMT00044 (IL ???... ???) [000195] --C--------- * JTRUE void [000194] --C--------- \--* NE int [000192] --C--------- +--* RET_EXPR int (inl return from call [000187]) [000193] ------------ \--* CNS_INT int 0 impImportBlockPending for BB26 impImportBlockPending for BB27 Importing BB27 (PC=363) of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' [ 0] 363 (0x16b) ldloc.s 16 [ 1] 365 (0x16d) ldc.i4.1 1 [ 2] 366 (0x16e) add *************** In impGetSpillTmpBase(BB27) lvaGrabTemps(1) returning 34..34 (long lifetime temps) called for IL Stack Entries Spilling stack entries into temps STMT00045 (IL 0x16B... ???) [000200] -A---------- * ASG int [000199] D------N---- +--* LCL_VAR int V34 tmp4 [000198] ------------ \--* ADD int [000196] ------------ +--* LCL_VAR int V19 loc16 [000197] ------------ \--* CNS_INT int 1 impImportBlockPending for BB28 Importing BB28 (PC=367) of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' [ 1] 367 (0x16f) stloc.s 19 STMT00046 (IL ???... ???) [000204] -A---------- * ASG int [000203] D------N---- +--* LCL_VAR int V22 loc19 [000202] ------------ \--* LCL_VAR int V34 tmp4 [ 0] 369 (0x171) ldloca.s 12 [ 1] 371 (0x173) ldloc.s 18 [ 2] 373 (0x175) call 060006F2 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 STMT00047 (IL 0x171... ???) [000208] I-C-G------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft (exactContextHnd=0x00000000D1FFAB1E) [000206] ------------ arg0 +--* ADDR byref [000205] -------N---- | \--* LCL_VAR struct V15 loc12 [000207] ------------ arg1 \--* LCL_VAR int V21 loc18 [ 0] 378 (0x17a) ldloc.s 12 [ 1] 380 (0x17c) ldloc.s 13 [ 2] 382 (0x17e) ldloca.s 20 [ 3] 384 (0x180) call 0A0003C4 In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16 Calling impNormStructVal on: [000210] ------------ * LCL_VAR struct V16 loc13 resulting tree: [000215] n----------- * OBJ struct [000214] ------------ \--* ADDR byref [000210] -------N---- \--* LCL_VAR struct V16 loc13 Calling impNormStructVal on: [000209] ------------ * LCL_VAR struct V15 loc12 resulting tree: [000217] n----------- * OBJ struct [000216] ------------ \--* ADDR byref [000209] -------N---- \--* LCL_VAR struct V15 loc12 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' for 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' calling 'System.Numerics.BigInteger:DivRem(System.Numerics.BigInteger,System.Numerics.BigInteger,byref):System.Numerics.BigInteger' INLINER: Marking System.Numerics.BigInteger:DivRem(System.Numerics.BigInteger,System.Numerics.BigInteger,byref):System.Numerics.BigInteger as NOINLINE because of too many il bytes INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' [ 1] 389 (0x185) call 0A0003C5 In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0 Calling impNormStructVal on: [000213] S-C-G------- * CALL struct System.Numerics.BigInteger.DivRem [000217] n----------- arg0 +--* OBJ struct [000216] ------------ | \--* ADDR byref [000209] -------N---- | \--* LCL_VAR struct V15 loc12 [000215] n----------- arg1 +--* OBJ struct [000214] ------------ | \--* ADDR byref [000210] -------N---- | \--* LCL_VAR struct V16 loc13 [000212] ------------ arg2 \--* ADDR byref [000211] -------N---- \--* LCL_VAR struct V23 loc20 lvaGrabTemp returning 35 (V35 tmp5) called for struct address for call/obj. STMT00048 (IL 0x17A... ???) [000213] S-C-G------- * CALL void System.Numerics.BigInteger.DivRem [000220] ------------ arg0 +--* ADDR byref [000219] -------N---- | \--* LCL_VAR struct V35 tmp5 [000217] n----------- arg1 +--* OBJ struct [000216] ------------ | \--* ADDR byref [000209] -------N---- | \--* LCL_VAR struct V15 loc12 [000215] n----------- arg2 +--* OBJ struct [000214] ------------ | \--* ADDR byref [000210] -------N---- | \--* LCL_VAR struct V16 loc13 [000212] ------------ arg3 \--* ADDR byref [000211] -------N---- \--* LCL_VAR struct V23 loc20 resulting tree: [000223] n----------- * OBJ struct [000222] ------------ \--* ADDR byref [000221] -------N---- \--* LCL_VAR struct V35 tmp5 STMT00049 (IL ???... ???) [000218] I-C-G------- * CALL long System.Numerics.BigInteger.op_Explicit (exactContextHnd=0x00000000D1FFAB1E) [000223] n----------- arg0 \--* OBJ struct [000222] ------------ \--* ADDR byref [000221] -------N---- \--* LCL_VAR struct V35 tmp5 [ 1] 394 (0x18a) stloc.s 21 STMT00050 (IL ???... ???) [000226] -AC--------- * ASG long [000225] D------N---- +--* LCL_VAR long V24 loc21 [000224] --C--------- \--* RET_EXPR long (inl return from call [000218]) [ 0] 396 (0x18c) ldloca.s 20 [ 1] 398 (0x18e) call 0A0003C6 In Compiler::impImportCall: opcode is call, kind=0, callRetType is bool, structSize is 0 STMT00051 (IL 0x18C... ???) [000229] I-C-G------- * CALL int System.Numerics.BigInteger.get_IsZero (exactContextHnd=0x00000000D1FFAB1E) [000228] ------------ this in rcx \--* ADDR byref [000227] -------N---- \--* LCL_VAR struct V23 loc20 [ 1] 403 (0x193) stloc.s 22 STMT00052 (IL ???... ???) [000232] -AC--------- * ASG int [000231] D------N---- +--* LCL_VAR int V25 loc22 [000230] --C--------- \--* RET_EXPR int (inl return from call [000229]) [ 0] 405 (0x195) ldloc.s 21 [ 1] 407 (0x197) call 060006EC In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 STMT00053 (IL 0x195... ???) [000234] I-C-G------- * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits (exactContextHnd=0x00000000D1FFAB1E) [000233] ------------ arg0 \--* LCL_VAR long V24 loc21 [ 1] 412 (0x19c) stloc.s 23 STMT00054 (IL ???... ???) [000237] -AC--------- * ASG int [000236] D------N---- +--* LCL_VAR int V26 loc23 [000235] --C--------- \--* RET_EXPR int (inl return from call [000234]) [ 0] 414 (0x19e) ldloc.s 23 [ 1] 416 (0x1a0) ldloc.s 17 [ 2] 418 (0x1a2) ble.un.s STMT00055 (IL 0x19E... ???) [000241] ------------ * JTRUE void [000240] N--------U-- \--* LE int [000238] ------------ +--* LCL_VAR int V26 loc23 [000239] ------------ \--* LCL_VAR int V20 loc17 impImportBlockPending for BB29 impImportBlockPending for BB33 Importing BB33 (PC=464) of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' [ 0] 464 (0x1d0) ldloc.s 8 [ 1] 466 (0x1d2) call 0A0003C5 In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0 Calling impNormStructVal on: [000242] ------------ * LCL_VAR struct V11 loc8 resulting tree: [000245] n----------- * OBJ struct [000244] ------------ \--* ADDR byref [000242] -------N---- \--* LCL_VAR struct V11 loc8 STMT00056 (IL 0x1D0... ???) [000243] I-C-G------- * CALL long System.Numerics.BigInteger.op_Explicit (exactContextHnd=0x00000000D1FFAB1E) [000245] n----------- arg0 \--* OBJ struct [000244] ------------ \--* ADDR byref [000242] -------N---- \--* LCL_VAR struct V11 loc8 [ 1] 471 (0x1d7) ldloc.s 17 [ 2] 473 (0x1d9) ldc.i4.s 63 [ 3] 475 (0x1db) and [ 2] 476 (0x1dc) shl [ 1] 477 (0x1dd) ldloc.s 21 [ 2] 479 (0x1df) add [ 1] 480 (0x1e0) stloc.s 24 STMT00057 (IL ???... ???) [000254] -AC--------- * ASG long [000253] D------N---- +--* LCL_VAR long V27 loc24 [000252] --C--------- \--* ADD long [000250] --C--------- +--* LSH long [000246] --C--------- | +--* RET_EXPR long (inl return from call [000243]) [000249] ------------ | \--* AND int [000247] ------------ | +--* LCL_VAR int V20 loc17 [000248] ------------ | \--* CNS_INT int 63 [000251] ------------ \--* LCL_VAR long V24 loc21 [ 0] 482 (0x1e2) ldloc.s 10 [ 1] 484 (0x1e4) ldc.i4.0 0 [ 2] 485 (0x1e5) bgt.un.s STMT00058 (IL 0x1E2... ???) [000258] ------------ * JTRUE void [000257] N--------U-- \--* GT int [000255] ------------ +--* LCL_VAR int V13 loc10 [000256] ------------ \--* CNS_INT int 0 impImportBlockPending for BB34 impImportBlockPending for BB35 Importing BB35 (PC=494) of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' [ 0] 494 (0x1ee) ldloc.s 10 [ 1] 496 (0x1f0) ldc.i4.2 2 [ 2] 497 (0x1f1) sub *************** In impGetSpillTmpBase(BB35) lvaGrabTemps(1) returning 36..36 (long lifetime temps) called for IL Stack Entries Spilling stack entries into temps STMT00059 (IL 0x1EE... ???) [000263] -A---------- * ASG int [000262] D------N---- +--* LCL_VAR int V36 tmp6 [000261] ------------ \--* SUB int [000259] ------------ +--* LCL_VAR int V13 loc10 [000260] ------------ \--* CNS_INT int 2 impImportBlockPending for BB36 Importing BB36 (PC=498) of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' [ 1] 498 (0x1f2) stloc.s 25 STMT00060 (IL ???... ???) [000267] -A---------- * ASG int [000266] D------N---- +--* LCL_VAR int V28 loc25 [000265] ------------ \--* LCL_VAR int V36 tmp6 [ 0] 500 (0x1f4) ldarg.1 [ 1] 501 (0x1f5) ldloc.s 24 [ 2] 503 (0x1f7) ldloc.s 25 [ 3] 505 (0x1f9) ldloc.s 22 [ 4] 507 (0x1fb) ldarg.2 [ 5] 508 (0x1fc) callvirt 06002065 (Implicit Tail call: prefixFlags |= PREFIX_TAILCALL_IMPLICIT) In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is int, structSize is 0 GTF_CALL_M_IMPLICIT_TAILCALL set for call [000273] INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' for 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' calling 'FloatingPointType:AssembleFloatingPointValue(long,int,bool,byref):int:this' INLINER: Marking FloatingPointType:AssembleFloatingPointValue(long,int,bool,byref):int:this as NOINLINE because of too many il bytes INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' [ 1] 513 (0x201) ret STMT00061 (IL 0x1F4... ???) [000274] --C-G------- * RETURN int [000273] --C-G------- \--* CALL nullcheck int FloatingPointType.AssembleFloatingPointValue [000268] ------------ this in rcx +--* LCL_VAR ref V01 arg1 [000269] ------------ arg1 +--* LCL_VAR long V27 loc24 [000270] ------------ arg2 +--* LCL_VAR int V28 loc25 [000271] ------------ arg3 +--* LCL_VAR int V25 loc22 [000272] ------------ arg4 \--* LCL_VAR byref V02 arg2 Importing BB34 (PC=487) of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' [ 0] 487 (0x1e7) ldloc.s 19 [ 1] 489 (0x1e9) neg [ 1] 490 (0x1ea) ldc.i4.1 1 [ 2] 491 (0x1eb) sub [ 1] 492 (0x1ec) br.s Spilling stack entries into temps STMT00062 (IL 0x1E7... ???) [000280] -A---------- * ASG int [000279] D------N---- +--* LCL_VAR int V36 tmp6 [000278] ------------ \--* SUB int [000276] ------------ +--* NEG int [000275] ------------ | \--* LCL_VAR int V22 loc19 [000277] ------------ \--* CNS_INT int 1 impImportBlockPending for BB36 Importing BB29 (PC=420) of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' [ 0] 420 (0x1a4) ldloc.s 23 [ 1] 422 (0x1a6) ldloc.s 17 [ 2] 424 (0x1a8) sub [ 1] 425 (0x1a9) stloc.s 26 STMT00063 (IL 0x1A4... ???) [000286] -A---------- * ASG int [000285] D------N---- +--* LCL_VAR int V29 loc26 [000284] ------------ \--* SUB int [000282] ------------ +--* LCL_VAR int V26 loc23 [000283] ------------ \--* LCL_VAR int V20 loc17 [ 0] 427 (0x1ab) ldloc.s 22 [ 1] 429 (0x1ad) brfalse.s STMT00064 (IL 0x1AB... ???) [000290] ------------ * JTRUE void [000289] ------------ \--* EQ int [000287] ------------ +--* LCL_VAR int V25 loc22 [000288] ------------ \--* CNS_INT int 0 impImportBlockPending for BB30 impImportBlockPending for BB31 Importing BB31 (PC=451) of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' [ 0] 451 (0x1c3) ldc.i4.0 0 *************** In impGetSpillTmpBase(BB31) lvaGrabTemps(1) returning 37..37 (long lifetime temps) called for IL Stack Entries Spilling stack entries into temps STMT00065 (IL 0x1C3... ???) [000293] -A---------- * ASG int [000292] D------N---- +--* LCL_VAR int V37 tmp7 [000291] ------------ \--* CNS_INT int 0 impImportBlockPending for BB32 Importing BB32 (PC=452) of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' [ 1] 452 (0x1c4) stloc.s 22 STMT00066 (IL ???... ???) [000297] -A---------- * ASG int [000296] D------N---- +--* LCL_VAR int V25 loc22 [000295] ------------ \--* LCL_VAR int V37 tmp7 [ 0] 454 (0x1c6) ldloc.s 21 [ 1] 456 (0x1c8) ldloc.s 26 [ 2] 458 (0x1ca) ldc.i4.s 63 [ 3] 460 (0x1cc) and [ 2] 461 (0x1cd) shr.un [ 1] 462 (0x1ce) stloc.s 21 STMT00067 (IL 0x1C6... ???) [000304] -A---------- * ASG long [000303] D------N---- +--* LCL_VAR long V24 loc21 [000302] ------------ \--* RSZ long [000298] ------------ +--* LCL_VAR long V24 loc21 [000301] ------------ \--* AND int [000299] ------------ +--* LCL_VAR int V29 loc26 [000300] ------------ \--* CNS_INT int 63 impImportBlockPending for BB33 Importing BB30 (PC=431) of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' [ 0] 431 (0x1af) ldloc.s 21 [ 1] 433 (0x1b1) ldc.i4.1 1 [ 2] 434 (0x1b2) conv.i8 [ 2] 435 (0x1b3) ldloc.s 26 [ 3] 437 (0x1b5) ldc.i4.s 63 [ 4] 439 (0x1b7) and [ 3] 440 (0x1b8) shl [ 2] 441 (0x1b9) ldc.i4.1 1 [ 3] 442 (0x1ba) conv.i8 [ 3] 443 (0x1bb) sub [ 2] 444 (0x1bc) and [ 1] 445 (0x1bd) ldc.i4.0 0 [ 2] 446 (0x1be) conv.i8 [ 2] 447 (0x1bf) ceq [ 1] 449 (0x1c1) br.s Spilling stack entries into temps STMT00068 (IL 0x1AF... ???) [000320] -A---------- * ASG int [000319] D------N---- +--* LCL_VAR int V37 tmp7 [000318] ------------ \--* EQ int [000315] ------------ +--* AND long [000305] ------------ | +--* LCL_VAR long V24 loc21 [000314] ------------ | \--* SUB long [000311] ------------ | +--* LSH long [000307] ------------ | | +--* CAST long <- int [000306] ------------ | | | \--* CNS_INT int 1 [000310] ------------ | | \--* AND int [000308] ------------ | | +--* LCL_VAR int V29 loc26 [000309] ------------ | | \--* CNS_INT int 63 [000313] ------------ | \--* CAST long <- int [000312] ------------ | \--* CNS_INT int 1 [000317] ------------ \--* CAST long <- int [000316] ------------ \--* CNS_INT int 0 impImportBlockPending for BB32 Importing BB26 (PC=359) of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' [ 0] 359 (0x167) ldloc.s 16 [ 1] 361 (0x169) br.s Spilling stack entries into temps STMT00069 (IL 0x167... ???) [000324] -A---------- * ASG int [000323] D------N---- +--* LCL_VAR int V34 tmp4 [000322] ------------ \--* LCL_VAR int V19 loc16 impImportBlockPending for BB28 Importing BB22 (PC=318) of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' [ 0] 318 (0x13e) ldloc.s 16 [ 1] 320 (0x140) ldloc.s 18 [ 2] 322 (0x142) ble.un.s STMT00070 (IL 0x13E... ???) [000329] ------------ * JTRUE void [000328] N--------U-- \--* LE int [000326] ------------ +--* LCL_VAR int V19 loc16 [000327] ------------ \--* LCL_VAR int V21 loc18 impImportBlockPending for BB23 impImportBlockPending for BB24 Importing BB24 (PC=341) of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' [ 0] 341 (0x155) ldloc.s 18 [ 1] 343 (0x157) ldloc.s 16 [ 2] 345 (0x159) sub [ 1] 346 (0x15a) stloc.s 18 STMT00071 (IL 0x155... ???) [000334] -A---------- * ASG int [000333] D------N---- +--* LCL_VAR int V21 loc18 [000332] ------------ \--* SUB int [000330] ------------ +--* LCL_VAR int V21 loc18 [000331] ------------ \--* LCL_VAR int V19 loc16 impImportBlockPending for BB25 Importing BB23 (PC=324) of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' [ 0] 324 (0x144) ldloc.s 9 [ 1] 326 (0x146) ldloc.s 10 [ 2] 328 (0x148) ldloc.s 7 [ 3] 330 (0x14a) ldc.i4.0 0 [ 4] 331 (0x14b) cgt.un [ 3] 333 (0x14d) ldarg.1 [ 4] 334 (0x14e) ldarg.2 [ 5] 335 (0x14f) call 060006EA (Implicit Tail call: prefixFlags |= PREFIX_TAILCALL_IMPLICIT) In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 GTF_CALL_M_IMPLICIT_TAILCALL set for call [000342] INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' calling 'Microsoft.CodeAnalysis.RealParser:ConvertBigIntegerToFloatingPointBits(System.Byte[],int,bool,FloatingPointType,byref):int' INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' [ 1] 340 (0x154) ret STMT00072 (IL 0x144... ???) [000343] --C-G------- * RETURN int [000342] --C-G------- \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits [000335] ------------ arg0 +--* LCL_VAR ref V12 loc9 [000336] ------------ arg1 +--* LCL_VAR int V13 loc10 [000339] N--------U-- arg2 +--* GT int [000337] ------------ | +--* LCL_VAR int V10 loc7 [000338] ------------ | \--* CNS_INT int 0 [000340] ------------ arg3 +--* LCL_VAR ref V01 arg1 [000341] ------------ arg4 \--* LCL_VAR byref V02 arg2 Importing BB20 (PC=294) of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' [ 0] 294 (0x126) ldloca.s 12 [ 1] 296 (0x128) ldloc.s 16 [ 2] 298 (0x12a) call 060006F2 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 STMT00073 (IL 0x126... ???) [000347] I-C-G------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft (exactContextHnd=0x00000000D1FFAB1E) [000345] ------------ arg0 +--* ADDR byref [000344] -------N---- | \--* LCL_VAR struct V15 loc12 [000346] ------------ arg1 \--* LCL_VAR int V19 loc16 impImportBlockPending for BB21 Importing BB17 (PC=279) of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' [ 0] 279 (0x117) ldc.i4.0 0 [ 1] 280 (0x118) br.s Spilling stack entries into temps STMT00074 (IL 0x117... ???) [000350] -A---------- * ASG int [000349] D------N---- +--* LCL_VAR int V33 tmp3 [000348] ------------ \--* CNS_INT int 0 impImportBlockPending for BB19 Importing BB14 (PC=196) of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' [ 0] 196 (0x0c4) ldloc.s 11 [ 1] 198 (0x0c6) conv.u8 [ 1] 199 (0x0c7) ldarga.s 0 [ 2] 201 (0x0c9) call 06002077 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 STMT00075 (IL 0x0C4... ???) [000356] I-C-G------- * CALL int DecimalFloatingPointString.get_MantissaCount (exactContextHnd=0x00000000D1FFAB1E) [000355] ------------ this in rcx \--* ADDR byref [000354] -------N---- \--* LCL_VAR struct V00 arg0 [ 2] 206 (0x0ce) conv.i8 [ 2] 207 (0x0cf) sub [ 1] 208 (0x0d0) ldarg.1 [ 2] 209 (0x0d1) callvirt 0600205F In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is int, structSize is 0 lvaGrabTemp returning 38 (V38 tmp8) called for impAppendStmt. STMT00077 (IL ???... ???) [000363] -AC--------- * ASG long [000362] D------N---- +--* LCL_VAR long V38 tmp8 [000359] --C--------- \--* SUB long [000353] ---------U-- +--* CAST long <- ulong <- uint [000352] ------------ | \--* LCL_VAR int V14 loc11 [000358] --C--------- \--* CAST long <- int [000357] --C--------- \--* RET_EXPR int (inl return from call [000356]) STMT00076 (IL ???... ???) [000361] I-C-G------- * CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent (exactContextHnd=0x00000000D1FFAB1E) [000360] ------------ this in rcx \--* LCL_VAR ref V01 arg1 [ 2] 214 (0x0d6) conv.i8 [ 2] 215 (0x0d7) ble.s STMT00078 (IL ???... ???) [000368] --C--------- * JTRUE void [000367] --C--------- \--* LE int [000364] ------------ +--* LCL_VAR long V38 tmp8 [000366] --C--------- \--* CAST long <- int [000365] --C--------- \--* RET_EXPR int (inl return from call [000361]) impImportBlockPending for BB15 impImportBlockPending for BB16 Importing BB15 (PC=217) of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' [ 0] 217 (0x0d9) ldarg.2 [ 1] 218 (0x0da) ldarg.1 [ 2] 219 (0x0db) callvirt 06002063 In Compiler::impImportCall: opcode is callvirt, kind=4, callRetType is long, structSize is 0 impDevirtualizeCall: Trying to devirtualize virtual call: class for 'this' is FloatingPointType (attrib 20000400) base method is FloatingPointType::get_Zero devirt to FloatingPointType::get_Zero -- inexact or not final [000371] --C-G------- * CALLV ind long FloatingPointType.get_Zero [000370] ------------ this in rcx \--* LCL_VAR ref V01 arg1 Class not final or exact, and method not final NOT Marking call [000371] as guarded devirtualization candidate -- disabled by jit config INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' for 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' calling 'FloatingPointType:get_Zero():long:this' INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' [ 2] 224 (0x0e0) stind.i8 STMT00079 (IL 0x0D9... ???) [000373] -ACXG------- * ASG long [000372] *------N---- +--* IND long [000369] ------------ | \--* LCL_VAR byref V02 arg2 [000371] --C-G------- \--* CALLV ind long FloatingPointType.get_Zero [000370] ------------ this in rcx \--* LCL_VAR ref V01 arg1 [ 0] 225 (0x0e1) ldc.i4.2 2 [ 1] 226 (0x0e2) ret STMT00080 (IL 0x0E1... ???) [000375] ------------ * RETURN int [000374] ------------ \--* CNS_INT int 2 Importing BB11 (PC=176) of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' [ 0] 176 (0x0b0) ldloc.s 7 [ 1] 178 (0x0b2) br.s Spilling stack entries into temps STMT00081 (IL 0x0B0... ???) [000378] -A---------- * ASG int [000377] D------N---- +--* LCL_VAR int V32 tmp2 [000376] ------------ \--* LCL_VAR int V10 loc7 impImportBlockPending for BB13 Importing BB04 (PC=101) of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' [ 0] 101 (0x065) ldloc.2 [ 1] 102 (0x066) conv.u8 [ 1] 103 (0x067) ldarg.1 [ 2] 104 (0x068) callvirt 0600205F In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is int, structSize is 0 STMT00082 (IL 0x065... ???) [000383] I-C-G------- * CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent (exactContextHnd=0x00000000D1FFAB1E) [000382] ------------ this in rcx \--* LCL_VAR ref V01 arg1 [ 2] 109 (0x06d) conv.i8 [ 2] 110 (0x06e) ble.s STMT00083 (IL ???... ???) [000387] --C--------- * JTRUE void [000386] --C--------- \--* LE int [000381] ---------U-- +--* CAST long <- ulong <- uint [000380] ------------ | \--* LCL_VAR int V05 loc2 [000385] --C--------- \--* CAST long <- int [000384] --C--------- \--* RET_EXPR int (inl return from call [000383]) impImportBlockPending for BB05 impImportBlockPending for BB06 Importing BB06 (PC=122) of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' [ 0] 122 (0x07a) ldloca.s 8 [ 1] 124 (0x07c) ldloc.2 [ 2] 125 (0x07d) call 060006F3 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 STMT00084 (IL 0x07A... ???) [000391] I-C-G------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen (exactContextHnd=0x00000000D1FFAB1E) [000389] ------------ arg0 +--* ADDR byref [000388] -------N---- | \--* LCL_VAR struct V11 loc8 [000390] ------------ arg1 \--* LCL_VAR int V05 loc2 impImportBlockPending for BB07 Importing BB05 (PC=112) of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' [ 0] 112 (0x070) ldarg.2 [ 1] 113 (0x071) ldarg.1 [ 2] 114 (0x072) callvirt 06002064 In Compiler::impImportCall: opcode is callvirt, kind=4, callRetType is long, structSize is 0 impDevirtualizeCall: Trying to devirtualize virtual call: class for 'this' is FloatingPointType (attrib 20000400) base method is FloatingPointType::get_Infinity devirt to FloatingPointType::get_Infinity -- inexact or not final [000394] --C-G------- * CALLV ind long FloatingPointType.get_Infinity [000393] ------------ this in rcx \--* LCL_VAR ref V01 arg1 Class not final or exact, and method not final NOT Marking call [000394] as guarded devirtualization candidate -- disabled by jit config INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' for 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' calling 'FloatingPointType:get_Infinity():long:this' INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' [ 2] 119 (0x077) stind.i8 STMT00085 (IL 0x070... ???) [000396] -ACXG------- * ASG long [000395] *------N---- +--* IND long [000392] ------------ | \--* LCL_VAR byref V02 arg2 [000394] --C-G------- \--* CALLV ind long FloatingPointType.get_Infinity [000393] ------------ this in rcx \--* LCL_VAR ref V01 arg1 [ 0] 120 (0x078) ldc.i4.3 3 [ 1] 121 (0x079) ret STMT00086 (IL 0x078... ???) [000398] ------------ * RETURN int [000397] ------------ \--* CNS_INT int 3 Importing BB02 (PC=013) of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' [ 0] 13 (0x00d) ldarg.2 [ 1] 14 (0x00e) ldarg.1 [ 2] 15 (0x00f) callvirt 06002063 In Compiler::impImportCall: opcode is callvirt, kind=4, callRetType is long, structSize is 0 impDevirtualizeCall: Trying to devirtualize virtual call: class for 'this' is FloatingPointType (attrib 20000400) base method is FloatingPointType::get_Zero devirt to FloatingPointType::get_Zero -- inexact or not final [000401] --C-G------- * CALLV ind long FloatingPointType.get_Zero [000400] ------------ this in rcx \--* LCL_VAR ref V01 arg1 Class not final or exact, and method not final NOT Marking call [000401] as guarded devirtualization candidate -- disabled by jit config INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' for 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' calling 'FloatingPointType:get_Zero():long:this' INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' [ 2] 20 (0x014) stind.i8 STMT00087 (IL 0x00D... ???) [000403] -ACXG------- * ASG long [000402] *------N---- +--* IND long [000399] ------------ | \--* LCL_VAR byref V02 arg2 [000401] --C-G------- \--* CALLV ind long FloatingPointType.get_Zero [000400] ------------ this in rcx \--* LCL_VAR ref V01 arg1 [ 0] 21 (0x015) ldc.i4.1 1 [ 1] 22 (0x016) ret STMT00088 (IL 0x015... ???) [000405] ------------ * RETURN int [000404] ------------ \--* CNS_INT int 1 *************** Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..00D)-> BB03 ( cond ) i idxlen BB02 [0001] 1 1 [00D..017) (return) i BB03 [0002] 1 1 [017..065)-> BB07 ( cond ) i BB04 [0003] 1 1 [065..070)-> BB06 ( cond ) i BB05 [0004] 1 1 [070..07A) (return) i BB06 [0005] 1 1 [07A..082) i BB07 [0006] 2 1 [082..092)-> BB09 ( cond ) i BB08 [0007] 1 1 [092..096)-> BB10 ( cond ) i BB09 [0008] 2 1 [096..0A7) (return) i BB10 [0009] 1 1 [0A7..0B0)-> BB12 ( cond ) i BB11 [0010] 1 1 [0B0..0B4)-> BB13 (always) i BB12 [0011] 1 1 [0B4..0BE) i BB13 [0012] 2 1 [0BE..0C4)-> BB16 ( cond ) i BB14 [0013] 1 1 [0C4..0D9)-> BB16 ( cond ) i BB15 [0014] 1 1 [0D9..0E3) (return) i BB16 [0015] 2 1 [0E3..117)-> BB18 ( cond ) i BB17 [0016] 1 1 [117..11A)-> BB19 (always) i BB18 [0017] 1 1 [11A..11F) i BB19 [0018] 2 1 [11F..126)-> BB21 ( cond ) i BB20 [0019] 1 1 [126..12F) i BB21 [0020] 2 1 [12F..13E)-> BB25 ( cond ) i BB22 [0021] 1 1 [13E..144)-> BB24 ( cond ) i BB23 [0022] 1 1 [144..155) (return) i BB24 [0023] 1 1 [155..15C) i BB25 [0024] 2 1 [15C..167)-> BB27 ( cond ) i BB26 [0025] 1 1 [167..16B)-> BB28 (always) i BB27 [0026] 1 1 [16B..16F) i BB28 [0027] 2 1 [16F..1A4)-> BB33 ( cond ) i BB29 [0028] 1 1 [1A4..1AF)-> BB31 ( cond ) i BB30 [0029] 1 1 [1AF..1C3)-> BB32 (always) i BB31 [0030] 1 1 [1C3..1C4) i BB32 [0031] 2 1 [1C4..1D0) i BB33 [0032] 2 1 [1D0..1E7)-> BB35 ( cond ) i BB34 [0033] 1 1 [1E7..1EE)-> BB36 (always) i BB35 [0034] 1 1 [1EE..1F2) i BB36 [0035] 2 1 [1F2..202) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..00D) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB01 STMT00000 (IL 0x000...0x00B) [000006] ---XG------- * JTRUE void [000005] ---XG------- \--* NE int [000003] ---XG------- +--* ARR_LENGTH int [000002] ----G------- | \--* FIELD ref Mantissa [000001] ------------ | \--* ADDR byref [000000] -------N---- | \--* LCL_VAR struct V00 arg0 [000004] ------------ \--* CNS_INT int 0 ------------ BB02 [00D..017) (return), preds={} succs={} ***** BB02 STMT00087 (IL 0x00D...0x014) [000403] -ACXG------- * ASG long [000402] *------N---- +--* IND long [000399] ------------ | \--* LCL_VAR byref V02 arg2 [000401] --C-G------- \--* CALLV ind long FloatingPointType.get_Zero [000400] ------------ this in rcx \--* LCL_VAR ref V01 arg1 ***** BB02 STMT00088 (IL 0x015...0x016) [000405] ------------ * RETURN int [000404] ------------ \--* CNS_INT int 1 ------------ BB03 [017..065) -> BB07 (cond), preds={} succs={BB04,BB07} ***** BB03 STMT00001 (IL 0x017...0x01F) [000008] I-C-G------- * CALL nullcheck int FloatingPointType.get_NormalMantissaBits (exactContextHnd=0x00000000D1FFAB1E) [000007] ------------ this in rcx \--* LCL_VAR ref V01 arg1 ***** BB03 STMT00002 (IL ???... ???) [000013] -AC--------- * ASG int [000012] D------N---- +--* LCL_VAR int V03 loc0 [000011] --C--------- \--* ADD int [000009] --C--------- +--* RET_EXPR int (inl return from call [000008]) [000010] ------------ \--* CNS_INT int 1 ***** BB03 STMT00003 (IL 0x020...0x039) [000018] I-C-G------- * CALL int System.Math.Max (exactContextHnd=0x00000000D1FFAB1E) [000014] ------------ arg0 +--* CNS_INT int 0 [000017] ----G------- arg1 \--* FIELD int Exponent [000016] ------------ \--* ADDR byref [000015] -------N---- \--* LCL_VAR struct V00 arg0 ***** BB03 STMT00004 (IL ???... ???) [000021] -AC--------- * ASG int [000020] D------N---- +--* LCL_VAR int V31 tmp1 [000019] --C--------- \--* RET_EXPR int (inl return from call [000018]) ***** BB03 STMT00005 (IL ???... ???) [000026] I-C-G------- * CALL int DecimalFloatingPointString.get_MantissaCount (exactContextHnd=0x00000000D1FFAB1E) [000025] ------------ this in rcx \--* ADDR byref [000024] -------N---- \--* LCL_VAR struct V00 arg0 ***** BB03 STMT00006 (IL ???... ???) [000028] I-C-G------- * CALL int System.Math.Min (exactContextHnd=0x00000000D1FFAB1E) [000023] ------------ arg0 +--* LCL_VAR int V31 tmp1 [000027] --C--------- arg1 \--* RET_EXPR int (inl return from call [000026]) ***** BB03 STMT00007 (IL ???... ???) [000031] -AC--------- * ASG int [000030] D------N---- +--* LCL_VAR int V04 loc1 [000029] --C--------- \--* RET_EXPR int (inl return from call [000028]) ***** BB03 STMT00008 (IL ???...0x03C) [000035] -A---------- * ASG int [000034] D------N---- +--* LCL_VAR int V05 loc2 [000033] ------------ \--* SUB int [000022] ------------ +--* LCL_VAR int V31 tmp1 [000032] ------------ \--* LCL_VAR int V04 loc1 ***** BB03 STMT00009 (IL 0x03D...0x03E) [000038] -A---------- * ASG int [000037] D------N---- +--* LCL_VAR int V06 loc3 [000036] ------------ \--* CNS_INT int 0 ***** BB03 STMT00010 (IL 0x03F...0x040) [000041] -A---------- * ASG int [000040] D------N---- +--* LCL_VAR int V07 loc4 [000039] ------------ \--* LCL_VAR int V04 loc1 ***** BB03 STMT00011 (IL 0x042...0x044) [000044] -A---------- * ASG int [000043] D------N---- +--* LCL_VAR int V08 loc5 [000042] ------------ \--* LCL_VAR int V07 loc4 ***** BB03 STMT00012 (IL 0x046...0x04D) [000047] I-C-G------- * CALL int DecimalFloatingPointString.get_MantissaCount (exactContextHnd=0x00000000D1FFAB1E) [000046] ------------ this in rcx \--* ADDR byref [000045] -------N---- \--* LCL_VAR struct V00 arg0 ***** BB03 STMT00013 (IL ???... ???) [000050] -AC--------- * ASG int [000049] D------N---- +--* LCL_VAR int V09 loc6 [000048] --C--------- \--* RET_EXPR int (inl return from call [000047]) ***** BB03 STMT00014 (IL 0x04F...0x054) [000055] -A---------- * ASG int [000054] D------N---- +--* LCL_VAR int V10 loc7 [000053] ------------ \--* SUB int [000051] ------------ +--* LCL_VAR int V09 loc6 [000052] ------------ \--* LCL_VAR int V08 loc5 ***** BB03 STMT00015 (IL 0x056...0x05F) [000059] I-C-G------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger (exactContextHnd=0x00000000D1FFAB1E) [000064] ------------ arg0 +--* ADDR byref [000063] -------N---- | \--* LCL_VAR struct V11 loc8 [000061] n----------- arg1 +--* OBJ struct [000060] ------------ | \--* ADDR byref [000056] -------N---- | \--* LCL_VAR struct V00 arg0 [000057] ------------ arg2 +--* LCL_VAR int V06 loc3 [000058] ------------ arg3 \--* LCL_VAR int V07 loc4 ***** BB03 STMT00016 (IL ???... ???) [000062] --C--------- * RET_EXPR void (inl return from call [000059]) ***** BB03 STMT00017 (IL 0x061...0x063) [000068] ------------ * JTRUE void [000067] N--------U-- \--* LE int [000065] ------------ +--* LCL_VAR int V05 loc2 [000066] ------------ \--* CNS_INT int 0 ------------ BB04 [065..070) -> BB06 (cond), preds={} succs={BB05,BB06} ***** BB04 STMT00082 (IL 0x065...0x06E) [000383] I-C-G------- * CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent (exactContextHnd=0x00000000D1FFAB1E) [000382] ------------ this in rcx \--* LCL_VAR ref V01 arg1 ***** BB04 STMT00083 (IL ???... ???) [000387] --C--------- * JTRUE void [000386] --C--------- \--* LE int [000381] ---------U-- +--* CAST long <- ulong <- uint [000380] ------------ | \--* LCL_VAR int V05 loc2 [000385] --C--------- \--* CAST long <- int [000384] --C--------- \--* RET_EXPR int (inl return from call [000383]) ------------ BB05 [070..07A) (return), preds={} succs={} ***** BB05 STMT00085 (IL 0x070...0x077) [000396] -ACXG------- * ASG long [000395] *------N---- +--* IND long [000392] ------------ | \--* LCL_VAR byref V02 arg2 [000394] --C-G------- \--* CALLV ind long FloatingPointType.get_Infinity [000393] ------------ this in rcx \--* LCL_VAR ref V01 arg1 ***** BB05 STMT00086 (IL 0x078...0x079) [000398] ------------ * RETURN int [000397] ------------ \--* CNS_INT int 3 ------------ BB06 [07A..082), preds={} succs={BB07} ***** BB06 STMT00084 (IL 0x07A...0x07D) [000391] I-C-G------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen (exactContextHnd=0x00000000D1FFAB1E) [000389] ------------ arg0 +--* ADDR byref [000388] -------N---- | \--* LCL_VAR struct V11 loc8 [000390] ------------ arg1 \--* LCL_VAR int V05 loc2 ------------ BB07 [082..092) -> BB09 (cond), preds={} succs={BB08,BB09} ***** BB07 STMT00018 (IL 0x082...0x08B) [000072] I-C-G------- * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits (exactContextHnd=0x00000000D1FFAB1E) [000074] n----------- arg0 +--* OBJ struct [000073] ------------ | \--* ADDR byref [000069] -------N---- | \--* LCL_VAR struct V11 loc8 [000071] ------------ arg1 \--* ADDR byref [000070] -------N---- \--* LCL_VAR ref V12 loc9 ***** BB07 STMT00019 (IL ???... ???) [000077] -AC--------- * ASG int [000076] D------N---- +--* LCL_VAR int V13 loc10 [000075] --C--------- \--* RET_EXPR int (inl return from call [000072]) ***** BB07 STMT00020 (IL 0x08D...0x090) [000081] ------------ * JTRUE void [000080] N--------U-- \--* GE int [000078] ------------ +--* LCL_VAR int V13 loc10 [000079] ------------ \--* LCL_VAR int V03 loc0 ------------ BB08 [092..096) -> BB10 (cond), preds={} succs={BB09,BB10} ***** BB08 STMT00022 (IL 0x092...0x094) [000094] ------------ * JTRUE void [000093] ------------ \--* NE int [000091] ------------ +--* LCL_VAR int V10 loc7 [000092] ------------ \--* CNS_INT int 0 ------------ BB09 [096..0A7) (return), preds={} succs={} ***** BB09 STMT00021 (IL 0x096...0x0A6) [000090] --C-G------- * RETURN int [000089] --C-G------- \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits [000082] ------------ arg0 +--* LCL_VAR ref V12 loc9 [000083] ------------ arg1 +--* LCL_VAR int V13 loc10 [000086] N--------U-- arg2 +--* GT int [000084] ------------ | +--* LCL_VAR int V10 loc7 [000085] ------------ | \--* CNS_INT int 0 [000087] ------------ arg3 +--* LCL_VAR ref V01 arg1 [000088] ------------ arg4 \--* LCL_VAR byref V02 arg2 ------------ BB10 [0A7..0B0) -> BB12 (cond), preds={} succs={BB11,BB12} ***** BB10 STMT00023 (IL 0x0A7...0x0AE) [000100] ----G------- * JTRUE void [000099] ----G------- \--* LT int [000097] ----G------- +--* FIELD int Exponent [000096] ------------ | \--* ADDR byref [000095] -------N---- | \--* LCL_VAR struct V00 arg0 [000098] ------------ \--* CNS_INT int 0 ------------ BB11 [0B0..0B4) -> BB13 (always), preds={} succs={BB13} ***** BB11 STMT00081 (IL 0x0B0...0x0B2) [000378] -A---------- * ASG int [000377] D------N---- +--* LCL_VAR int V32 tmp2 [000376] ------------ \--* LCL_VAR int V10 loc7 ------------ BB12 [0B4..0BE), preds={} succs={BB13} ***** BB12 STMT00024 (IL 0x0B4...0x0BD) [000108] -A--G------- * ASG int [000107] D------N---- +--* LCL_VAR int V32 tmp2 [000106] ----G------- \--* ADD int [000101] ------------ +--* LCL_VAR int V10 loc7 [000105] ----G------- \--* NEG int [000104] ----G------- \--* FIELD int Exponent [000103] ------------ \--* ADDR byref [000102] -------N---- \--* LCL_VAR struct V00 arg0 ------------ BB13 [0BE..0C4) -> BB16 (cond), preds={} succs={BB14,BB16} ***** BB13 STMT00025 (IL ???...0x0BE) [000112] -A---------- * ASG int [000111] D------N---- +--* LCL_VAR int V14 loc11 [000110] ------------ \--* LCL_VAR int V32 tmp2 ***** BB13 STMT00026 (IL 0x0C0...0x0C2) [000116] ------------ * JTRUE void [000115] ------------ \--* NE int [000113] ------------ +--* LCL_VAR int V13 loc10 [000114] ------------ \--* CNS_INT int 0 ------------ BB14 [0C4..0D9) -> BB16 (cond), preds={} succs={BB15,BB16} ***** BB14 STMT00075 (IL 0x0C4...0x0D7) [000356] I-C-G------- * CALL int DecimalFloatingPointString.get_MantissaCount (exactContextHnd=0x00000000D1FFAB1E) [000355] ------------ this in rcx \--* ADDR byref [000354] -------N---- \--* LCL_VAR struct V00 arg0 ***** BB14 STMT00077 (IL ???... ???) [000363] -AC--------- * ASG long [000362] D------N---- +--* LCL_VAR long V38 tmp8 [000359] --C--------- \--* SUB long [000353] ---------U-- +--* CAST long <- ulong <- uint [000352] ------------ | \--* LCL_VAR int V14 loc11 [000358] --C--------- \--* CAST long <- int [000357] --C--------- \--* RET_EXPR int (inl return from call [000356]) ***** BB14 STMT00076 (IL ???... ???) [000361] I-C-G------- * CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent (exactContextHnd=0x00000000D1FFAB1E) [000360] ------------ this in rcx \--* LCL_VAR ref V01 arg1 ***** BB14 STMT00078 (IL ???... ???) [000368] --C--------- * JTRUE void [000367] --C--------- \--* LE int [000364] ------------ +--* LCL_VAR long V38 tmp8 [000366] --C--------- \--* CAST long <- int [000365] --C--------- \--* RET_EXPR int (inl return from call [000361]) ------------ BB15 [0D9..0E3) (return), preds={} succs={} ***** BB15 STMT00079 (IL 0x0D9...0x0E0) [000373] -ACXG------- * ASG long [000372] *------N---- +--* IND long [000369] ------------ | \--* LCL_VAR byref V02 arg2 [000371] --C-G------- \--* CALLV ind long FloatingPointType.get_Zero [000370] ------------ this in rcx \--* LCL_VAR ref V01 arg1 ***** BB15 STMT00080 (IL 0x0E1...0x0E2) [000375] ------------ * RETURN int [000374] ------------ \--* CNS_INT int 2 ------------ BB16 [0E3..117) -> BB18 (cond), preds={} succs={BB17,BB18} ***** BB16 STMT00027 (IL 0x0E3...0x0ED) [000120] I-C-G------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger (exactContextHnd=0x00000000D1FFAB1E) [000125] ------------ arg0 +--* ADDR byref [000124] -------N---- | \--* LCL_VAR struct V15 loc12 [000122] n----------- arg1 +--* OBJ struct [000121] ------------ | \--* ADDR byref [000117] -------N---- | \--* LCL_VAR struct V00 arg0 [000118] ------------ arg2 +--* LCL_VAR int V08 loc5 [000119] ------------ arg3 \--* LCL_VAR int V09 loc6 ***** BB16 STMT00028 (IL ???... ???) [000123] --C--------- * RET_EXPR void (inl return from call [000120]) ***** BB16 STMT00029 (IL 0x0EF...0x0F4) [000133] H-CXG------- * CALL help long HELPER.CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE [000131] ------------ arg0 +--* CNS_INT long 0x7ff815262aa0 [000132] ------------ arg1 \--* CNS_INT int 173 ***** BB16 STMT00030 (IL ???... ???) [000137] -A--G------- * ASG struct (copy) [000135] D------N---- +--* LCL_VAR struct V16 loc13 [000129] ----G------- \--* OBJ struct [000128] ----G------- \--* ADD byref [000126] ----G------- +--* FIELD ref BigOne [000127] ------------ \--* CNS_INT long 8 Fseq[#FirstElem] ***** BB16 STMT00031 (IL 0x0F6...0x106) [000141] I-C-G------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen (exactContextHnd=0x00000000D1FFAB1E) [000139] ------------ arg0 +--* ADDR byref [000138] -------N---- | \--* LCL_VAR struct V16 loc13 [000140] ------------ arg1 \--* LCL_VAR int V14 loc11 ***** BB16 STMT00032 (IL 0x0FF... ???) [000143] I-C-G------- * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits (exactContextHnd=0x00000000D1FFAB1E) [000145] n----------- arg0 \--* OBJ struct [000144] ------------ \--* ADDR byref [000142] -------N---- \--* LCL_VAR struct V15 loc12 ***** BB16 STMT00033 (IL ???... ???) [000148] -AC--------- * ASG int [000147] D------N---- +--* LCL_VAR int V17 loc14 [000146] --C--------- \--* RET_EXPR int (inl return from call [000143]) ***** BB16 STMT00034 (IL 0x108...0x10F) [000150] I-C-G------- * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits (exactContextHnd=0x00000000D1FFAB1E) [000152] n----------- arg0 \--* OBJ struct [000151] ------------ \--* ADDR byref [000149] -------N---- \--* LCL_VAR struct V16 loc13 ***** BB16 STMT00035 (IL ???... ???) [000155] -AC--------- * ASG int [000154] D------N---- +--* LCL_VAR int V18 loc15 [000153] --C--------- \--* RET_EXPR int (inl return from call [000150]) ***** BB16 STMT00036 (IL 0x111...0x115) [000159] ------------ * JTRUE void [000158] N--------U-- \--* GT int [000156] ------------ +--* LCL_VAR int V18 loc15 [000157] ------------ \--* LCL_VAR int V17 loc14 ------------ BB17 [117..11A) -> BB19 (always), preds={} succs={BB19} ***** BB17 STMT00074 (IL 0x117...0x118) [000350] -A---------- * ASG int [000349] D------N---- +--* LCL_VAR int V33 tmp3 [000348] ------------ \--* CNS_INT int 0 ------------ BB18 [11A..11F), preds={} succs={BB19} ***** BB18 STMT00037 (IL 0x11A...0x11E) [000164] -A---------- * ASG int [000163] D------N---- +--* LCL_VAR int V33 tmp3 [000162] ------------ \--* SUB int [000160] ------------ +--* LCL_VAR int V18 loc15 [000161] ------------ \--* LCL_VAR int V17 loc14 ------------ BB19 [11F..126) -> BB21 (cond), preds={} succs={BB20,BB21} ***** BB19 STMT00038 (IL ???...0x11F) [000168] -A---------- * ASG int [000167] D------N---- +--* LCL_VAR int V19 loc16 [000166] ------------ \--* LCL_VAR int V33 tmp3 ***** BB19 STMT00039 (IL 0x121...0x124) [000172] ------------ * JTRUE void [000171] N--------U-- \--* LE int [000169] ------------ +--* LCL_VAR int V19 loc16 [000170] ------------ \--* CNS_INT int 0 ------------ BB20 [126..12F), preds={} succs={BB21} ***** BB20 STMT00073 (IL 0x126...0x12A) [000347] I-C-G------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft (exactContextHnd=0x00000000D1FFAB1E) [000345] ------------ arg0 +--* ADDR byref [000344] -------N---- | \--* LCL_VAR struct V15 loc12 [000346] ------------ arg1 \--* LCL_VAR int V19 loc16 ------------ BB21 [12F..13E) -> BB25 (cond), preds={} succs={BB22,BB25} ***** BB21 STMT00040 (IL 0x12F...0x133) [000177] -A---------- * ASG int [000176] D------N---- +--* LCL_VAR int V20 loc17 [000175] ------------ \--* SUB int [000173] ------------ +--* LCL_VAR int V03 loc0 [000174] ------------ \--* LCL_VAR int V13 loc10 ***** BB21 STMT00041 (IL 0x135...0x137) [000180] -A---------- * ASG int [000179] D------N---- +--* LCL_VAR int V21 loc18 [000178] ------------ \--* LCL_VAR int V20 loc17 ***** BB21 STMT00042 (IL 0x139...0x13C) [000184] ------------ * JTRUE void [000183] N--------U-- \--* LE int [000181] ------------ +--* LCL_VAR int V13 loc10 [000182] ------------ \--* CNS_INT int 0 ------------ BB22 [13E..144) -> BB24 (cond), preds={} succs={BB23,BB24} ***** BB22 STMT00070 (IL 0x13E...0x142) [000329] ------------ * JTRUE void [000328] N--------U-- \--* LE int [000326] ------------ +--* LCL_VAR int V19 loc16 [000327] ------------ \--* LCL_VAR int V21 loc18 ------------ BB23 [144..155) (return), preds={} succs={} ***** BB23 STMT00072 (IL 0x144...0x154) [000343] --C-G------- * RETURN int [000342] --C-G------- \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits [000335] ------------ arg0 +--* LCL_VAR ref V12 loc9 [000336] ------------ arg1 +--* LCL_VAR int V13 loc10 [000339] N--------U-- arg2 +--* GT int [000337] ------------ | +--* LCL_VAR int V10 loc7 [000338] ------------ | \--* CNS_INT int 0 [000340] ------------ arg3 +--* LCL_VAR ref V01 arg1 [000341] ------------ arg4 \--* LCL_VAR byref V02 arg2 ------------ BB24 [155..15C), preds={} succs={BB25} ***** BB24 STMT00071 (IL 0x155...0x15A) [000334] -A---------- * ASG int [000333] D------N---- +--* LCL_VAR int V21 loc18 [000332] ------------ \--* SUB int [000330] ------------ +--* LCL_VAR int V21 loc18 [000331] ------------ \--* LCL_VAR int V19 loc16 ------------ BB25 [15C..167) -> BB27 (cond), preds={} succs={BB26,BB27} ***** BB25 STMT00043 (IL 0x15C...0x165) [000187] I-C-G------- * CALL int System.Numerics.BigInteger.op_LessThan (exactContextHnd=0x00000000D1FFAB1E) [000191] n----------- arg0 +--* OBJ struct [000190] ------------ | \--* ADDR byref [000185] -------N---- | \--* LCL_VAR struct V15 loc12 [000189] n----------- arg1 \--* OBJ struct [000188] ------------ \--* ADDR byref [000186] -------N---- \--* LCL_VAR struct V16 loc13 ***** BB25 STMT00044 (IL ???... ???) [000195] --C--------- * JTRUE void [000194] --C--------- \--* NE int [000192] --C--------- +--* RET_EXPR int (inl return from call [000187]) [000193] ------------ \--* CNS_INT int 0 ------------ BB26 [167..16B) -> BB28 (always), preds={} succs={BB28} ***** BB26 STMT00069 (IL 0x167...0x169) [000324] -A---------- * ASG int [000323] D------N---- +--* LCL_VAR int V34 tmp4 [000322] ------------ \--* LCL_VAR int V19 loc16 ------------ BB27 [16B..16F), preds={} succs={BB28} ***** BB27 STMT00045 (IL 0x16B...0x16E) [000200] -A---------- * ASG int [000199] D------N---- +--* LCL_VAR int V34 tmp4 [000198] ------------ \--* ADD int [000196] ------------ +--* LCL_VAR int V19 loc16 [000197] ------------ \--* CNS_INT int 1 ------------ BB28 [16F..1A4) -> BB33 (cond), preds={} succs={BB29,BB33} ***** BB28 STMT00046 (IL ???...0x16F) [000204] -A---------- * ASG int [000203] D------N---- +--* LCL_VAR int V22 loc19 [000202] ------------ \--* LCL_VAR int V34 tmp4 ***** BB28 STMT00047 (IL 0x171...0x18A) [000208] I-C-G------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft (exactContextHnd=0x00000000D1FFAB1E) [000206] ------------ arg0 +--* ADDR byref [000205] -------N---- | \--* LCL_VAR struct V15 loc12 [000207] ------------ arg1 \--* LCL_VAR int V21 loc18 ***** BB28 STMT00048 (IL 0x17A... ???) [000213] S-C-G------- * CALL void System.Numerics.BigInteger.DivRem [000220] ------------ arg0 +--* ADDR byref [000219] -------N---- | \--* LCL_VAR struct V35 tmp5 [000217] n----------- arg1 +--* OBJ struct [000216] ------------ | \--* ADDR byref [000209] -------N---- | \--* LCL_VAR struct V15 loc12 [000215] n----------- arg2 +--* OBJ struct [000214] ------------ | \--* ADDR byref [000210] -------N---- | \--* LCL_VAR struct V16 loc13 [000212] ------------ arg3 \--* ADDR byref [000211] -------N---- \--* LCL_VAR struct V23 loc20 ***** BB28 STMT00049 (IL ???... ???) [000218] I-C-G------- * CALL long System.Numerics.BigInteger.op_Explicit (exactContextHnd=0x00000000D1FFAB1E) [000223] n----------- arg0 \--* OBJ struct [000222] ------------ \--* ADDR byref [000221] -------N---- \--* LCL_VAR struct V35 tmp5 ***** BB28 STMT00050 (IL ???... ???) [000226] -AC--------- * ASG long [000225] D------N---- +--* LCL_VAR long V24 loc21 [000224] --C--------- \--* RET_EXPR long (inl return from call [000218]) ***** BB28 STMT00051 (IL 0x18C...0x193) [000229] I-C-G------- * CALL int System.Numerics.BigInteger.get_IsZero (exactContextHnd=0x00000000D1FFAB1E) [000228] ------------ this in rcx \--* ADDR byref [000227] -------N---- \--* LCL_VAR struct V23 loc20 ***** BB28 STMT00052 (IL ???... ???) [000232] -AC--------- * ASG int [000231] D------N---- +--* LCL_VAR int V25 loc22 [000230] --C--------- \--* RET_EXPR int (inl return from call [000229]) ***** BB28 STMT00053 (IL 0x195...0x19C) [000234] I-C-G------- * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits (exactContextHnd=0x00000000D1FFAB1E) [000233] ------------ arg0 \--* LCL_VAR long V24 loc21 ***** BB28 STMT00054 (IL ???... ???) [000237] -AC--------- * ASG int [000236] D------N---- +--* LCL_VAR int V26 loc23 [000235] --C--------- \--* RET_EXPR int (inl return from call [000234]) ***** BB28 STMT00055 (IL 0x19E...0x1A2) [000241] ------------ * JTRUE void [000240] N--------U-- \--* LE int [000238] ------------ +--* LCL_VAR int V26 loc23 [000239] ------------ \--* LCL_VAR int V20 loc17 ------------ BB29 [1A4..1AF) -> BB31 (cond), preds={} succs={BB30,BB31} ***** BB29 STMT00063 (IL 0x1A4...0x1A9) [000286] -A---------- * ASG int [000285] D------N---- +--* LCL_VAR int V29 loc26 [000284] ------------ \--* SUB int [000282] ------------ +--* LCL_VAR int V26 loc23 [000283] ------------ \--* LCL_VAR int V20 loc17 ***** BB29 STMT00064 (IL 0x1AB...0x1AD) [000290] ------------ * JTRUE void [000289] ------------ \--* EQ int [000287] ------------ +--* LCL_VAR int V25 loc22 [000288] ------------ \--* CNS_INT int 0 ------------ BB30 [1AF..1C3) -> BB32 (always), preds={} succs={BB32} ***** BB30 STMT00068 (IL 0x1AF...0x1C1) [000320] -A---------- * ASG int [000319] D------N---- +--* LCL_VAR int V37 tmp7 [000318] ------------ \--* EQ int [000315] ------------ +--* AND long [000305] ------------ | +--* LCL_VAR long V24 loc21 [000314] ------------ | \--* SUB long [000311] ------------ | +--* LSH long [000307] ------------ | | +--* CAST long <- int [000306] ------------ | | | \--* CNS_INT int 1 [000310] ------------ | | \--* AND int [000308] ------------ | | +--* LCL_VAR int V29 loc26 [000309] ------------ | | \--* CNS_INT int 63 [000313] ------------ | \--* CAST long <- int [000312] ------------ | \--* CNS_INT int 1 [000317] ------------ \--* CAST long <- int [000316] ------------ \--* CNS_INT int 0 ------------ BB31 [1C3..1C4), preds={} succs={BB32} ***** BB31 STMT00065 (IL 0x1C3...0x1C3) [000293] -A---------- * ASG int [000292] D------N---- +--* LCL_VAR int V37 tmp7 [000291] ------------ \--* CNS_INT int 0 ------------ BB32 [1C4..1D0), preds={} succs={BB33} ***** BB32 STMT00066 (IL ???...0x1C4) [000297] -A---------- * ASG int [000296] D------N---- +--* LCL_VAR int V25 loc22 [000295] ------------ \--* LCL_VAR int V37 tmp7 ***** BB32 STMT00067 (IL 0x1C6...0x1CE) [000304] -A---------- * ASG long [000303] D------N---- +--* LCL_VAR long V24 loc21 [000302] ------------ \--* RSZ long [000298] ------------ +--* LCL_VAR long V24 loc21 [000301] ------------ \--* AND int [000299] ------------ +--* LCL_VAR int V29 loc26 [000300] ------------ \--* CNS_INT int 63 ------------ BB33 [1D0..1E7) -> BB35 (cond), preds={} succs={BB34,BB35} ***** BB33 STMT00056 (IL 0x1D0...0x1E0) [000243] I-C-G------- * CALL long System.Numerics.BigInteger.op_Explicit (exactContextHnd=0x00000000D1FFAB1E) [000245] n----------- arg0 \--* OBJ struct [000244] ------------ \--* ADDR byref [000242] -------N---- \--* LCL_VAR struct V11 loc8 ***** BB33 STMT00057 (IL ???... ???) [000254] -AC--------- * ASG long [000253] D------N---- +--* LCL_VAR long V27 loc24 [000252] --C--------- \--* ADD long [000250] --C--------- +--* LSH long [000246] --C--------- | +--* RET_EXPR long (inl return from call [000243]) [000249] ------------ | \--* AND int [000247] ------------ | +--* LCL_VAR int V20 loc17 [000248] ------------ | \--* CNS_INT int 63 [000251] ------------ \--* LCL_VAR long V24 loc21 ***** BB33 STMT00058 (IL 0x1E2...0x1E5) [000258] ------------ * JTRUE void [000257] N--------U-- \--* GT int [000255] ------------ +--* LCL_VAR int V13 loc10 [000256] ------------ \--* CNS_INT int 0 ------------ BB34 [1E7..1EE) -> BB36 (always), preds={} succs={BB36} ***** BB34 STMT00062 (IL 0x1E7...0x1EC) [000280] -A---------- * ASG int [000279] D------N---- +--* LCL_VAR int V36 tmp6 [000278] ------------ \--* SUB int [000276] ------------ +--* NEG int [000275] ------------ | \--* LCL_VAR int V22 loc19 [000277] ------------ \--* CNS_INT int 1 ------------ BB35 [1EE..1F2), preds={} succs={BB36} ***** BB35 STMT00059 (IL 0x1EE...0x1F1) [000263] -A---------- * ASG int [000262] D------N---- +--* LCL_VAR int V36 tmp6 [000261] ------------ \--* SUB int [000259] ------------ +--* LCL_VAR int V13 loc10 [000260] ------------ \--* CNS_INT int 2 ------------ BB36 [1F2..202) (return), preds={} succs={} ***** BB36 STMT00060 (IL ???...0x1F2) [000267] -A---------- * ASG int [000266] D------N---- +--* LCL_VAR int V28 loc25 [000265] ------------ \--* LCL_VAR int V36 tmp6 ***** BB36 STMT00061 (IL 0x1F4...0x201) [000274] --C-G------- * RETURN int [000273] --C-G------- \--* CALL nullcheck int FloatingPointType.AssembleFloatingPointValue [000268] ------------ this in rcx +--* LCL_VAR ref V01 arg1 [000269] ------------ arg1 +--* LCL_VAR long V27 loc24 [000270] ------------ arg2 +--* LCL_VAR int V28 loc25 [000271] ------------ arg3 +--* LCL_VAR int V25 loc22 [000272] ------------ arg4 \--* LCL_VAR byref V02 arg2 ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Indirect call transform -- no candidates to transform *************** Finishing PHASE Indirect call transform [no changes] *************** Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Finishing PHASE Expand patchpoints [no changes] *************** Starting PHASE Post-import *************** Finishing PHASE Post-import *************** Starting PHASE Morph - Init New BlockSet epoch 1, # of blocks (including unused BB00): 37, bitset array size: 1 (short) *************** In fgRemoveEmptyBlocks *************** Finishing PHASE Morph - Init *************** In fgDebugCheckBBlist *************** Starting PHASE Morph - Inlining **** Late devirt opportunity [000401] --C-G------- * CALLV ind long FloatingPointType.get_Zero [000400] ------------ this in rcx \--* LCL_VAR ref V01 arg1 impDevirtualizeCall: Trying to devirtualize virtual call: class for 'this' is FloatingPointType (attrib 20000400) base method is FloatingPointType::get_Zero devirt to FloatingPointType::get_Zero -- inexact or not final [000401] --C-G------- * CALLV ind long FloatingPointType.get_Zero [000400] ------------ this in rcx \--* LCL_VAR ref V01 arg1 Class not final or exact, and method not final No guarded devirt during late devirtualization Expanding INLINE_CANDIDATE in statement STMT00001 in BB03: STMT00001 (IL 0x017...0x01F) [000008] I-C-G------- * CALL nullcheck int FloatingPointType.get_NormalMantissaBits (exactContextHnd=0x00000000D1FFAB1E) [000007] ------------ this in rcx \--* LCL_VAR ref V01 arg1 thisArg: is a local var [000007] ------------ * LCL_VAR ref V01 arg1 INLINER: inlineInfo.tokenLookupContextHandle for FloatingPointType:get_NormalMantissaBits():ushort:this set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method FloatingPointType:get_NormalMantissaBits():ushort:this : IL to import: IL_0000 02 ldarg.0 IL_0001 6f 5a 20 00 06 callvirt 0x600205A IL_0006 17 ldc.i4.1 IL_0007 58 add IL_0008 d1 conv.u2 IL_0009 2a ret INLINER impTokenLookupContextHandle for FloatingPointType:get_NormalMantissaBits():ushort:this is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for FloatingPointType:get_NormalMantissaBits():ushort:this Jump targets: none Computing inlinee profile scale: ... call site not profiled New Basic Block BB37 [0036] created. BB37 [000..00A) Basic block list for 'FloatingPointType:get_NormalMantissaBits():ushort:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB37 [0036] 1 1 [000..00A) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000008] Starting PHASE Pre-import *************** Inline @[000008] Finishing PHASE Pre-import *************** Inline @[000008] Starting PHASE Importation *************** In impImport() for FloatingPointType:get_NormalMantissaBits():ushort:this impImportBlockPending for BB37 Importing BB37 (PC=000) of 'FloatingPointType:get_NormalMantissaBits():ushort:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) callvirt 0600205A In Compiler::impImportCall: opcode is callvirt, kind=4, callRetType is ushort, structSize is 0 impDevirtualizeCall: Trying to devirtualize virtual call: class for 'this' is FloatingPointType (attrib 20000400) base method is FloatingPointType::get_DenormalMantissaBits devirt to FloatingPointType::get_DenormalMantissaBits -- inexact or not final [000406] --C-G------- * CALLV ind int FloatingPointType.get_DenormalMantissaBits [000007] ------------ this in rcx \--* LCL_VAR ref V01 arg1 Class not final or exact, and method not final NOT Marking call [000406] as guarded devirtualization candidate -- disabled by jit config INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' for 'FloatingPointType:get_NormalMantissaBits():ushort:this' calling 'FloatingPointType:get_DenormalMantissaBits():ushort:this' INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' [ 1] 6 (0x006) ldc.i4.1 1 [ 2] 7 (0x007) add [ 1] 8 (0x008) conv.u2 [ 1] 9 (0x009) ret Inlinee Return expression (before normalization) => [000409] --C-G------- * CAST int <- ushort <- int [000408] --C-G------- \--* ADD int [000406] --C-G------- +--* CALLV ind int FloatingPointType.get_DenormalMantissaBits [000007] ------------ this in rcx | \--* LCL_VAR ref V01 arg1 [000407] ------------ \--* CNS_INT int 1 Inlinee Return expression (after normalization) => [000409] --C-G------- * CAST int <- ushort <- int [000408] --C-G------- \--* ADD int [000406] --C-G------- +--* CALLV ind int FloatingPointType.get_DenormalMantissaBits [000007] ------------ this in rcx | \--* LCL_VAR ref V01 arg1 [000407] ------------ \--* CNS_INT int 1 ** Note: inlinee IL was partially imported -- imported 0 of 10 bytes of method IL *************** Inline @[000008] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB37 [0036] 1 1 [000..00A) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB37 [000..00A) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000008] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000008] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000008] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000008] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000008] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000008] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000008] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000008] is [000409] --C-G------- * CAST int <- ushort <- int [000408] --C-G------- \--* ADD int [000406] --C-G------- +--* CALLV ind int FloatingPointType.get_DenormalMantissaBits [000007] ------------ this in rcx | \--* LCL_VAR ref V01 arg1 [000407] ------------ \--* CNS_INT int 1 Successfully inlined FloatingPointType:get_NormalMantissaBits():ushort:this (10 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' calling 'FloatingPointType:get_NormalMantissaBits():ushort:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000009] with [000409] [000009] --C--------- * RET_EXPR int (inl return from call [000409]) Inserting the inline return expression [000409] --C-G------- * CAST int <- ushort <- int [000408] --C-G------- \--* ADD int [000406] --C-G------- +--* CALLV ind int FloatingPointType.get_DenormalMantissaBits [000007] ------------ this in rcx | \--* LCL_VAR ref V01 arg1 [000407] ------------ \--* CNS_INT int 1 **** Late devirt opportunity [000406] --C-G------- * CALLV ind int FloatingPointType.get_DenormalMantissaBits [000007] ------------ this in rcx \--* LCL_VAR ref V01 arg1 impDevirtualizeCall: Trying to devirtualize virtual call: class for 'this' is FloatingPointType (attrib 20000400) base method is FloatingPointType::get_DenormalMantissaBits devirt to FloatingPointType::get_DenormalMantissaBits -- inexact or not final [000406] --C-G------- * CALLV ind int FloatingPointType.get_DenormalMantissaBits [000007] ------------ this in rcx \--* LCL_VAR ref V01 arg1 Class not final or exact, and method not final No guarded devirt during late devirtualization Expanding INLINE_CANDIDATE in statement STMT00003 in BB03: STMT00003 (IL 0x020...0x039) [000018] I-C-G------- * CALL int System.Math.Max (exactContextHnd=0x00000000D1FFAB1E) [000014] ------------ arg0 +--* CNS_INT int 0 [000017] ----G------- arg1 \--* FIELD int Exponent [000016] ------------ \--* ADDR byref [000015] -------N---- \--* LCL_VAR struct V00 arg0 Argument #0: is a constant [000014] ------------ * CNS_INT int 0 Argument #1: has global refs has caller local ref [000017] ----G------- * FIELD int Exponent [000016] ------------ \--* ADDR byref [000015] -------N---- \--* LCL_VAR struct V00 arg0 INLINER: inlineInfo.tokenLookupContextHandle for System.Math:Max(int,int):int set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method System.Math:Max(int,int):int : IL to import: IL_0000 02 ldarg.0 IL_0001 03 ldarg.1 IL_0002 2f 02 bge.s 2 (IL_0006) IL_0004 03 ldarg.1 IL_0005 2a ret IL_0006 02 ldarg.0 IL_0007 2a ret INLINER impTokenLookupContextHandle for System.Math:Max(int,int):int is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for System.Math:Max(int,int):int Jump targets: IL_0006 Computing inlinee profile scale: ... call site not profiled New Basic Block BB38 [0037] created. BB38 [000..004) New Basic Block BB39 [0038] created. BB39 [004..006) New Basic Block BB40 [0039] created. BB40 [006..008) lvaGrabTemp returning 39 (V39 tmp9) (a long lifetime temp) called for Inline return value spill temp. Basic block list for 'System.Math:Max(int,int):int' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB38 [0037] 1 1 [000..004)-> BB40 ( cond ) BB39 [0038] 1 1 [004..006) (return) BB40 [0039] 1 1 [006..008) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000018] Starting PHASE Pre-import *************** Inline @[000018] Finishing PHASE Pre-import *************** Inline @[000018] Starting PHASE Importation *************** In impImport() for System.Math:Max(int,int):int impImportBlockPending for BB38 Importing BB38 (PC=000) of 'System.Math:Max(int,int):int' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldarg.1 lvaGrabTemp returning 40 (V40 tmp10) called for Inlining Arg. [ 2] 2 (0x002) bge.s [000414] ------------ * JTRUE void [000413] ------------ \--* GE int [000411] ------------ +--* CNS_INT int 0 [000412] ------------ \--* LCL_VAR int V40 tmp10 impImportBlockPending for BB39 impImportBlockPending for BB40 Importing BB40 (PC=006) of 'System.Math:Max(int,int):int' [ 0] 6 (0x006) ldarg.0 [ 1] 7 (0x007) ret Inlinee Return expression (before normalization) => [000415] ------------ * CNS_INT int 0 [000417] -A---------- * ASG int [000416] D------N---- +--* LCL_VAR int V39 tmp9 [000415] ------------ \--* CNS_INT int 0 Inlinee Return expression (after normalization) => [000418] ------------ * LCL_VAR int V39 tmp9 Importing BB39 (PC=004) of 'System.Math:Max(int,int):int' [ 0] 4 (0x004) ldarg.1 [ 1] 5 (0x005) ret Inlinee Return expression (before normalization) => [000419] ------------ * LCL_VAR int V40 tmp10 [000421] -A---------- * ASG int [000420] D------N---- +--* LCL_VAR int V39 tmp9 [000419] ------------ \--* LCL_VAR int V40 tmp10 Inlinee Return expression (after normalization) => [000422] ------------ * LCL_VAR int V39 tmp9 *************** Inline @[000018] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB38 [0037] 1 1 [000..004)-> BB40 ( cond ) i BB39 [0038] 1 1 [004..006) (return) i BB40 [0039] 1 1 [006..008) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB38 [000..004) -> BB40 (cond), preds={} succs={BB39,BB40} ***** BB38 [000414] ------------ * JTRUE void [000413] ------------ \--* GE int [000411] ------------ +--* CNS_INT int 0 [000412] ------------ \--* LCL_VAR int V40 tmp10 ------------ BB39 [004..006) (return), preds={} succs={} ***** BB39 [000421] -A---------- * ASG int [000420] D------N---- +--* LCL_VAR int V39 tmp9 [000419] ------------ \--* LCL_VAR int V40 tmp10 ------------ BB40 [006..008) (return), preds={} succs={} ***** BB40 [000417] -A---------- * ASG int [000416] D------N---- +--* LCL_VAR int V39 tmp9 [000415] ------------ \--* CNS_INT int 0 ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000018] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000018] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000018] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000018] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000018] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000018] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000018] ----------- Arguments setup: STMT00092 (IL 0x020... ???) [000424] -A--G------- * ASG int [000423] D------N---- +--* LCL_VAR int V40 tmp10 [000017] ----G------- \--* FIELD int Exponent [000016] ------------ \--* ADDR byref [000015] -------N---- \--* LCL_VAR struct V00 arg0 Inlinee method body:New Basic Block BB41 [0040] created. Convert bbJumpKind of BB39 to BBJ_ALWAYS to bottomBlock BB41 Convert bbJumpKind of BB40 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB38 [0037] 1 1 [020..021)-> BB40 ( cond ) i BB39 [0038] 1 1 [020..021)-> BB41 (always) i BB40 [0039] 1 1 [020..021) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB38 [020..021) -> BB40 (cond), preds={} succs={BB39,BB40} ***** BB38 STMT00089 (IL 0x020... ???) [000414] ------------ * JTRUE void [000413] ------------ \--* GE int [000411] ------------ +--* CNS_INT int 0 [000412] ------------ \--* LCL_VAR int V40 tmp10 ------------ BB39 [020..021) -> BB41 (always), preds={} succs={BB41} ***** BB39 STMT00091 (IL 0x020... ???) [000421] -A---------- * ASG int [000420] D------N---- +--* LCL_VAR int V39 tmp9 [000419] ------------ \--* LCL_VAR int V40 tmp10 ------------ BB40 [020..021), preds={} succs={BB41} ***** BB40 STMT00090 (IL 0x020... ???) [000417] -A---------- * ASG int [000416] D------N---- +--* LCL_VAR int V39 tmp9 [000415] ------------ \--* CNS_INT int 0 ------------------------------------------------------------------------------------------------------------------- Return expression for call at [000018] is [000422] ------------ * LCL_VAR int V39 tmp9 Successfully inlined System.Math:Max(int,int):int (8 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' calling 'System.Math:Max(int,int):int' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000019] with [000422] [000019] --C--------- * RET_EXPR int (inl return from call [000422]) Inserting the inline return expression [000422] ------------ * LCL_VAR int V39 tmp9 Expanding INLINE_CANDIDATE in statement STMT00005 in BB41: STMT00005 (IL ???... ???) [000026] I-C-G------- * CALL int DecimalFloatingPointString.get_MantissaCount (exactContextHnd=0x00000000D1FFAB1E) [000025] ------------ this in rcx \--* ADDR byref [000024] -------N---- \--* LCL_VAR struct V00 arg0 thisArg: is a constant is byref to a struct local [000025] ------------ * ADDR byref [000024] -------N---- \--* LCL_VAR struct V00 arg0 INLINER: inlineInfo.tokenLookupContextHandle for DecimalFloatingPointString:get_MantissaCount():int:this set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method DecimalFloatingPointString:get_MantissaCount():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 38 10 00 04 ldfld 0x4001038 IL_0006 6f 9a 00 00 0a callvirt 0xA00009A IL_000b 2a ret INLINER impTokenLookupContextHandle for DecimalFloatingPointString:get_MantissaCount():int:this is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for DecimalFloatingPointString:get_MantissaCount():int:this Jump targets: none Computing inlinee profile scale: ... call site not profiled New Basic Block BB42 [0041] created. BB42 [000..00C) Basic block list for 'DecimalFloatingPointString:get_MantissaCount():int:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB42 [0041] 1 1 [000..00C) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000026] Starting PHASE Pre-import *************** Inline @[000026] Finishing PHASE Pre-import *************** Inline @[000026] Starting PHASE Importation *************** In impImport() for DecimalFloatingPointString:get_MantissaCount():int:this impImportBlockPending for BB42 Importing BB42 (PC=000) of 'DecimalFloatingPointString:get_MantissaCount():int:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 04001038 [ 1] 6 (0x006) callvirt 0A00009A In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is int, structSize is 0 [ 1] 11 (0x00b) ret Inlinee Return expression (before normalization) => [000429] ---XG------- * ARR_LENGTH int [000428] ----G------- \--* FIELD ref Mantissa [000426] ------------ \--* ADDR byref [000427] -------N---- \--* LCL_VAR struct V00 this Inlinee Return expression (after normalization) => [000429] ---XG------- * ARR_LENGTH int [000428] ----G------- \--* FIELD ref Mantissa [000426] ------------ \--* ADDR byref [000427] -------N---- \--* LCL_VAR struct V00 this ** Note: inlinee IL was partially imported -- imported 0 of 12 bytes of method IL *************** Inline @[000026] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB42 [0041] 1 1 [000..00C) (return) i idxlen ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB42 [000..00C) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000026] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000026] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000026] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000026] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000026] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000026] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000026] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000026] is [000429] ---XG------- * ARR_LENGTH int [000428] ----G------- \--* FIELD ref Mantissa [000426] ------------ \--* ADDR byref [000427] -------N---- \--* LCL_VAR struct V00 arg0 Successfully inlined DecimalFloatingPointString:get_MantissaCount():int:this (12 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' calling 'DecimalFloatingPointString:get_MantissaCount():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Expanding INLINE_CANDIDATE in statement STMT00006 in BB41: STMT00006 (IL ???... ???) [000028] I-C-G------- * CALL int System.Math.Min (exactContextHnd=0x00000000D1FFAB1E) [000023] ------------ arg0 +--* LCL_VAR int V31 tmp1 [000027] --C--------- arg1 \--* RET_EXPR int (inl return from call [000429]) Argument #0: is a local var [000023] ------------ * LCL_VAR int V31 tmp1 Argument #1: has global refs has caller local ref has side effects [000429] ---XG------- * ARR_LENGTH int [000428] ----G------- \--* FIELD ref Mantissa [000426] ------------ \--* ADDR byref [000427] -------N---- \--* LCL_VAR struct V00 arg0 INLINER: inlineInfo.tokenLookupContextHandle for System.Math:Min(int,int):int set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method System.Math:Min(int,int):int : IL to import: IL_0000 02 ldarg.0 IL_0001 03 ldarg.1 IL_0002 36 02 ble.un.s 2 (IL_0006) IL_0004 03 ldarg.1 IL_0005 2a ret IL_0006 02 ldarg.0 IL_0007 2a ret INLINER impTokenLookupContextHandle for System.Math:Min(int,int):int is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for System.Math:Min(int,int):int Jump targets: IL_0006 Computing inlinee profile scale: ... call site not profiled New Basic Block BB43 [0042] created. BB43 [000..004) New Basic Block BB44 [0043] created. BB44 [004..006) New Basic Block BB45 [0044] created. BB45 [006..008) lvaGrabTemp returning 41 (V41 tmp11) (a long lifetime temp) called for Inline return value spill temp. Basic block list for 'System.Math:Min(int,int):int' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB43 [0042] 1 1 [000..004)-> BB45 ( cond ) BB44 [0043] 1 1 [004..006) (return) BB45 [0044] 1 1 [006..008) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000028] Starting PHASE Pre-import *************** Inline @[000028] Finishing PHASE Pre-import *************** Inline @[000028] Starting PHASE Importation *************** In impImport() for System.Math:Min(int,int):int impImportBlockPending for BB43 Importing BB43 (PC=000) of 'System.Math:Min(int,int):int' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldarg.1 lvaGrabTemp returning 42 (V42 tmp12) called for Inlining Arg. [ 2] 2 (0x002) ble.un.s [000433] ------------ * JTRUE void [000432] N--------U-- \--* LE int [000023] ------------ +--* LCL_VAR int V31 tmp1 [000431] ------------ \--* LCL_VAR int V42 tmp12 impImportBlockPending for BB44 impImportBlockPending for BB45 Importing BB45 (PC=006) of 'System.Math:Min(int,int):int' [ 0] 6 (0x006) ldarg.0 [ 1] 7 (0x007) ret Inlinee Return expression (before normalization) => [000434] ------------ * LCL_VAR int V31 tmp1 [000436] -A---------- * ASG int [000435] D------N---- +--* LCL_VAR int V41 tmp11 [000434] ------------ \--* LCL_VAR int V31 tmp1 Inlinee Return expression (after normalization) => [000437] ------------ * LCL_VAR int V41 tmp11 Importing BB44 (PC=004) of 'System.Math:Min(int,int):int' [ 0] 4 (0x004) ldarg.1 [ 1] 5 (0x005) ret Inlinee Return expression (before normalization) => [000438] ------------ * LCL_VAR int V42 tmp12 [000440] -A---------- * ASG int [000439] D------N---- +--* LCL_VAR int V41 tmp11 [000438] ------------ \--* LCL_VAR int V42 tmp12 Inlinee Return expression (after normalization) => [000441] ------------ * LCL_VAR int V41 tmp11 *************** Inline @[000028] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB43 [0042] 1 1 [000..004)-> BB45 ( cond ) i BB44 [0043] 1 1 [004..006) (return) i BB45 [0044] 1 1 [006..008) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB43 [000..004) -> BB45 (cond), preds={} succs={BB44,BB45} ***** BB43 [000433] ------------ * JTRUE void [000432] N--------U-- \--* LE int [000023] ------------ +--* LCL_VAR int V31 tmp1 [000431] ------------ \--* LCL_VAR int V42 tmp12 ------------ BB44 [004..006) (return), preds={} succs={} ***** BB44 [000440] -A---------- * ASG int [000439] D------N---- +--* LCL_VAR int V41 tmp11 [000438] ------------ \--* LCL_VAR int V42 tmp12 ------------ BB45 [006..008) (return), preds={} succs={} ***** BB45 [000436] -A---------- * ASG int [000435] D------N---- +--* LCL_VAR int V41 tmp11 [000434] ------------ \--* LCL_VAR int V31 tmp1 ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000028] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000028] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000028] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000028] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000028] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000028] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000028] ----------- Arguments setup: STMT00096 (IL ???... ???) [000443] -A-XG------- * ASG int [000442] D------N---- +--* LCL_VAR int V42 tmp12 [000429] ---XG------- \--* ARR_LENGTH int [000428] ----G------- \--* FIELD ref Mantissa [000426] ------------ \--* ADDR byref [000427] -------N---- \--* LCL_VAR struct V00 arg0 Inlinee method body:New Basic Block BB46 [0045] created. Convert bbJumpKind of BB44 to BBJ_ALWAYS to bottomBlock BB46 Convert bbJumpKind of BB45 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB43 [0042] 1 1 [000..000)-> BB45 ( cond ) i internal BB44 [0043] 1 1 [000..000)-> BB46 (always) i internal BB45 [0044] 1 1 [000..000) i internal ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB43 [000..000) -> BB45 (cond), preds={} succs={BB44,BB45} ***** BB43 STMT00093 (IL ???... ???) [000433] ------------ * JTRUE void [000432] N--------U-- \--* LE int [000023] ------------ +--* LCL_VAR int V31 tmp1 [000431] ------------ \--* LCL_VAR int V42 tmp12 ------------ BB44 [000..000) -> BB46 (always), preds={} succs={BB46} ***** BB44 STMT00095 (IL ???... ???) [000440] -A---------- * ASG int [000439] D------N---- +--* LCL_VAR int V41 tmp11 [000438] ------------ \--* LCL_VAR int V42 tmp12 ------------ BB45 [000..000), preds={} succs={BB46} ***** BB45 STMT00094 (IL ???... ???) [000436] -A---------- * ASG int [000435] D------N---- +--* LCL_VAR int V41 tmp11 [000434] ------------ \--* LCL_VAR int V31 tmp1 ------------------------------------------------------------------------------------------------------------------- Return expression for call at [000028] is [000441] ------------ * LCL_VAR int V41 tmp11 Successfully inlined System.Math:Min(int,int):int (8 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' calling 'System.Math:Min(int,int):int' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000029] with [000441] [000029] --C--------- * RET_EXPR int (inl return from call [000441]) Inserting the inline return expression [000441] ------------ * LCL_VAR int V41 tmp11 Expanding INLINE_CANDIDATE in statement STMT00012 in BB46: STMT00012 (IL 0x046...0x04D) [000047] I-C-G------- * CALL int DecimalFloatingPointString.get_MantissaCount (exactContextHnd=0x00000000D1FFAB1E) [000046] ------------ this in rcx \--* ADDR byref [000045] -------N---- \--* LCL_VAR struct V00 arg0 thisArg: is a constant is byref to a struct local [000046] ------------ * ADDR byref [000045] -------N---- \--* LCL_VAR struct V00 arg0 INLINER: inlineInfo.tokenLookupContextHandle for DecimalFloatingPointString:get_MantissaCount():int:this set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method DecimalFloatingPointString:get_MantissaCount():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 38 10 00 04 ldfld 0x4001038 IL_0006 6f 9a 00 00 0a callvirt 0xA00009A IL_000b 2a ret INLINER impTokenLookupContextHandle for DecimalFloatingPointString:get_MantissaCount():int:this is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for DecimalFloatingPointString:get_MantissaCount():int:this Jump targets: none Computing inlinee profile scale: ... call site not profiled New Basic Block BB47 [0046] created. BB47 [000..00C) Basic block list for 'DecimalFloatingPointString:get_MantissaCount():int:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB47 [0046] 1 1 [000..00C) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000047] Starting PHASE Pre-import *************** Inline @[000047] Finishing PHASE Pre-import *************** Inline @[000047] Starting PHASE Importation *************** In impImport() for DecimalFloatingPointString:get_MantissaCount():int:this impImportBlockPending for BB47 Importing BB47 (PC=000) of 'DecimalFloatingPointString:get_MantissaCount():int:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 04001038 [ 1] 6 (0x006) callvirt 0A00009A In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is int, structSize is 0 [ 1] 11 (0x00b) ret Inlinee Return expression (before normalization) => [000448] ---XG------- * ARR_LENGTH int [000447] ----G------- \--* FIELD ref Mantissa [000445] ------------ \--* ADDR byref [000446] -------N---- \--* LCL_VAR struct V00 this Inlinee Return expression (after normalization) => [000448] ---XG------- * ARR_LENGTH int [000447] ----G------- \--* FIELD ref Mantissa [000445] ------------ \--* ADDR byref [000446] -------N---- \--* LCL_VAR struct V00 this ** Note: inlinee IL was partially imported -- imported 0 of 12 bytes of method IL *************** Inline @[000047] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB47 [0046] 1 1 [000..00C) (return) i idxlen ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB47 [000..00C) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000047] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000047] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000047] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000047] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000047] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000047] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000047] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000047] is [000448] ---XG------- * ARR_LENGTH int [000447] ----G------- \--* FIELD ref Mantissa [000445] ------------ \--* ADDR byref [000446] -------N---- \--* LCL_VAR struct V00 arg0 Successfully inlined DecimalFloatingPointString:get_MantissaCount():int:this (12 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' calling 'DecimalFloatingPointString:get_MantissaCount():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000048] with [000448] [000048] --C--------- * RET_EXPR int (inl return from call [000448]) Inserting the inline return expression [000448] ---XG------- * ARR_LENGTH int [000447] ----G------- \--* FIELD ref Mantissa [000445] ------------ \--* ADDR byref [000446] -------N---- \--* LCL_VAR struct V00 arg0 Expanding INLINE_CANDIDATE in statement STMT00015 in BB46: STMT00015 (IL 0x056...0x05F) [000059] I-C-G------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger (exactContextHnd=0x00000000D1FFAB1E) [000064] ------------ arg0 +--* ADDR byref [000063] -------N---- | \--* LCL_VAR struct V11 loc8 [000061] n----------- arg1 +--* OBJ struct [000060] ------------ | \--* ADDR byref [000056] -------N---- | \--* LCL_VAR struct V00 arg0 [000057] ------------ arg2 +--* LCL_VAR int V06 loc3 [000058] ------------ arg3 \--* LCL_VAR int V07 loc4 Argument #0: has caller local ref [000061] n----------- * OBJ struct [000060] ------------ \--* ADDR byref [000056] -------N---- \--* LCL_VAR struct V00 arg0 Argument #1: is a local var [000057] ------------ * LCL_VAR int V06 loc3 Argument #2: is a local var [000058] ------------ * LCL_VAR int V07 loc4 INLINER: inlineInfo.tokenLookupContextHandle for Microsoft.CodeAnalysis.RealParser:AccumulateDecimalDigitsIntoBigInteger(DecimalFloatingPointString,int,int):System.Numerics.BigInteger set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method Microsoft.CodeAnalysis.RealParser:AccumulateDecimalDigitsIntoBigInteger(DecimalFloatingPointString,int,int):System.Numerics.BigInteger : IL to import: IL_0000 03 ldarg.1 IL_0001 04 ldarg.2 IL_0002 33 06 bne.un.s 6 (IL_000a) IL_0004 7e 9c 02 00 04 ldsfld 0x400029C IL_0009 2a ret IL_000a 02 ldarg.0 IL_000b 7b 38 10 00 04 ldfld 0x4001038 IL_0010 03 ldarg.1 IL_0011 04 ldarg.2 IL_0012 03 ldarg.1 IL_0013 59 sub IL_0014 6f c7 03 00 0a callvirt 0xA0003C7 IL_0019 28 c8 03 00 0a call 0xA0003C8 IL_001e 2a ret INLINER impTokenLookupContextHandle for Microsoft.CodeAnalysis.RealParser:AccumulateDecimalDigitsIntoBigInteger(DecimalFloatingPointString,int,int):System.Numerics.BigInteger is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for Microsoft.CodeAnalysis.RealParser:AccumulateDecimalDigitsIntoBigInteger(DecimalFloatingPointString,int,int):System.Numerics.BigInteger weight= 16 : state 4 [ ldarg.1 ] weight= 35 : state 5 [ ldarg.2 ] weight= 12 : state 51 [ bne.un.s ] weight=159 : state 112 [ ldsfld ] weight= 19 : state 42 [ ret ] weight= 31 : state 191 [ ldarg.0 -> ldfld ] weight= 16 : state 4 [ ldarg.1 ] weight= 35 : state 5 [ ldarg.2 ] weight= 16 : state 4 [ ldarg.1 ] weight=-15 : state 77 [ sub ] weight= 83 : state 99 [ callvirt ] weight= 79 : state 40 [ call ] weight= 19 : state 42 [ ret ] Inline candidate looks like a wrapper method. Multiplier increased to 1. Inline candidate callsite is boring. Multiplier increased to 2.3. calleeNativeSizeEstimate=505 callsiteNativeSizeEstimate=165 benefit multiplier=2.3 threshold=379 Native estimate for function size exceeds threshold for inlining 50.5 > 37.9 (multiplier = 2.3) Inline expansion aborted, inline not profitable Inlining [000059] failed, so bashing STMT00015 to NOP INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' for 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' calling 'Microsoft.CodeAnalysis.RealParser:AccumulateDecimalDigitsIntoBigInteger(DecimalFloatingPointString,int,int):System.Numerics.BigInteger' INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' Replacing the return expression placeholder [000062] with [000059] [000062] --C--------- * RET_EXPR void (inl return from call [000059]) Inserting the inline return expression [000059] S-C-G------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger [000064] ------------ arg0 +--* ADDR byref [000063] -------N---- | \--* LCL_VAR struct V11 loc8 [000061] n----------- arg1 +--* OBJ struct [000060] ------------ | \--* ADDR byref [000056] -------N---- | \--* LCL_VAR struct V00 arg0 [000057] ------------ arg2 +--* LCL_VAR int V06 loc3 [000058] ------------ arg3 \--* LCL_VAR int V07 loc4 Expanding INLINE_CANDIDATE in statement STMT00082 in BB04: STMT00082 (IL 0x065...0x06E) [000383] I-C-G------- * CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent (exactContextHnd=0x00000000D1FFAB1E) [000382] ------------ this in rcx \--* LCL_VAR ref V01 arg1 thisArg: is a local var [000382] ------------ * LCL_VAR ref V01 arg1 INLINER: inlineInfo.tokenLookupContextHandle for FloatingPointType:get_OverflowDecimalExponent():int:this set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method FloatingPointType:get_OverflowDecimalExponent():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 6f 5e 20 00 06 callvirt 0x600205E IL_0006 18 ldc.i4.2 IL_0007 02 ldarg.0 IL_0008 28 5b 20 00 06 call 0x600205B IL_000d 5a mul IL_000e 58 add IL_000f 19 ldc.i4.3 IL_0010 5b div IL_0011 2a ret INLINER impTokenLookupContextHandle for FloatingPointType:get_OverflowDecimalExponent():int:this is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for FloatingPointType:get_OverflowDecimalExponent():int:this weight= 10 : state 3 [ ldarg.0 ] weight= 83 : state 99 [ callvirt ] weight= 34 : state 25 [ ldc.i4.2 ] weight= 10 : state 3 [ ldarg.0 ] weight= 79 : state 40 [ call ] weight= -9 : state 78 [ mul ] weight=-12 : state 76 [ add ] weight= -6 : state 26 [ ldc.i4.3 ] weight= 35 : state 79 [ div ] weight= 19 : state 42 [ ret ] Inline candidate callsite is boring. Multiplier increased to 1.3. calleeNativeSizeEstimate=243 callsiteNativeSizeEstimate=85 benefit multiplier=1.3 threshold=110 Native estimate for function size exceeds threshold for inlining 24.3 > 11 (multiplier = 1.3) Inline expansion aborted, inline not profitable Inlining [000383] failed, so bashing STMT00082 to NOP INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' for 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' calling 'FloatingPointType:get_OverflowDecimalExponent():int:this' INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' Replacing the return expression placeholder [000384] with [000383] [000384] --C--------- * RET_EXPR int (inl return from call [000383]) Inserting the inline return expression [000383] --C-G------- * CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent [000382] ------------ this in rcx \--* LCL_VAR ref V01 arg1 **** Late devirt opportunity [000394] --C-G------- * CALLV ind long FloatingPointType.get_Infinity [000393] ------------ this in rcx \--* LCL_VAR ref V01 arg1 impDevirtualizeCall: Trying to devirtualize virtual call: class for 'this' is FloatingPointType (attrib 20000400) base method is FloatingPointType::get_Infinity devirt to FloatingPointType::get_Infinity -- inexact or not final [000394] --C-G------- * CALLV ind long FloatingPointType.get_Infinity [000393] ------------ this in rcx \--* LCL_VAR ref V01 arg1 Class not final or exact, and method not final No guarded devirt during late devirtualization Expanding INLINE_CANDIDATE in statement STMT00084 in BB06: STMT00084 (IL 0x07A...0x07D) [000391] I-C-G------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen (exactContextHnd=0x00000000D1FFAB1E) [000389] ------------ arg0 +--* ADDR byref [000388] -------N---- | \--* LCL_VAR struct V11 loc8 [000390] ------------ arg1 \--* LCL_VAR int V05 loc2 Argument #0: is a constant is byref to a struct local [000389] ------------ * ADDR byref [000388] -------N---- \--* LCL_VAR struct V11 loc8 Argument #1: is a local var [000390] ------------ * LCL_VAR int V05 loc2 INLINER: inlineInfo.tokenLookupContextHandle for Microsoft.CodeAnalysis.RealParser:MultiplyByPowerOfTen(byref,int) set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method Microsoft.CodeAnalysis.RealParser:MultiplyByPowerOfTen(byref,int) : IL to import: IL_0000 7e 9f 02 00 04 ldsfld 0x400029F IL_0005 03 ldarg.1 IL_0006 28 ca 03 00 0a call 0xA0003CA IL_000b 0a stloc.0 IL_000c 02 ldarg.0 IL_000d 02 ldarg.0 IL_000e 71 67 00 00 01 ldobj 0x1000067 IL_0013 06 ldloc.0 IL_0014 28 cb 03 00 0a call 0xA0003CB IL_0019 81 67 00 00 01 stobj 0x1000067 IL_001e 2a ret INLINER impTokenLookupContextHandle for Microsoft.CodeAnalysis.RealParser:MultiplyByPowerOfTen(byref,int) is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for Microsoft.CodeAnalysis.RealParser:MultiplyByPowerOfTen(byref,int) weight=159 : state 112 [ ldsfld ] weight= 16 : state 4 [ ldarg.1 ] weight= 79 : state 40 [ call ] weight= 6 : state 11 [ stloc.0 ] weight= 10 : state 3 [ ldarg.0 ] weight= 10 : state 3 [ ldarg.0 ] weight= 29 : state 101 [ ldobj ] weight= 12 : state 7 [ ldloc.0 ] weight= 79 : state 40 [ call ] weight= 36 : state 115 [ stobj ] weight= 19 : state 42 [ ret ] Inline candidate callsite is boring. Multiplier increased to 1.3. calleeNativeSizeEstimate=455 callsiteNativeSizeEstimate=115 benefit multiplier=1.3 threshold=149 Native estimate for function size exceeds threshold for inlining 45.5 > 14.9 (multiplier = 1.3) Inline expansion aborted, inline not profitable INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' for 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' calling 'Microsoft.CodeAnalysis.RealParser:MultiplyByPowerOfTen(byref,int)' INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' Expanding INLINE_CANDIDATE in statement STMT00018 in BB07: STMT00018 (IL 0x082...0x08B) [000072] I-C-G------- * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits (exactContextHnd=0x00000000D1FFAB1E) [000074] n----------- arg0 +--* OBJ struct [000073] ------------ | \--* ADDR byref [000069] -------N---- | \--* LCL_VAR struct V11 loc8 [000071] ------------ arg1 \--* ADDR byref [000070] -------N---- \--* LCL_VAR ref V12 loc9 Argument #0: has caller local ref [000074] n----------- * OBJ struct [000073] ------------ \--* ADDR byref [000069] -------N---- \--* LCL_VAR struct V11 loc8 Argument #1: is a constant [000071] ------------ * ADDR byref [000070] -------N---- \--* LCL_VAR ref V12 loc9 INLINER: inlineInfo.tokenLookupContextHandle for Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger,byref):int set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger,byref):int : IL to import: IL_0000 0f 00 ldarga.s 0x0 IL_0002 28 c6 03 00 0a call 0xA0003C6 IL_0007 2c 0a brfalse.s 10 (IL_0013) IL_0009 03 ldarg.1 IL_000a 17 ldc.i4.1 IL_000b 8d 9a 00 00 01 newarr 0x100009A IL_0010 51 stind.ref IL_0011 16 ldc.i4.0 IL_0012 2a ret IL_0013 03 ldarg.1 IL_0014 0f 00 ldarga.s 0x0 IL_0016 28 c9 03 00 0a call 0xA0003C9 IL_001b 51 stind.ref IL_001c 03 ldarg.1 IL_001d 50 ldind.ref IL_001e 8e ldlen IL_001f 69 conv.i4 IL_0020 17 ldc.i4.1 IL_0021 59 sub IL_0022 0a stloc.0 IL_0023 2b 17 br.s 23 (IL_003c) IL_0025 03 ldarg.1 IL_0026 50 ldind.ref IL_0027 06 ldloc.0 IL_0028 91 ldelem.u1 IL_0029 0b stloc.1 IL_002a 07 ldloc.1 IL_002b 2c 0b brfalse.s 11 (IL_0038) IL_002d 1e ldc.i4.8 IL_002e 06 ldloc.0 IL_002f 5a mul IL_0030 07 ldloc.1 IL_0031 28 ed 06 00 06 call 0x60006ED IL_0036 58 add IL_0037 2a ret IL_0038 06 ldloc.0 IL_0039 17 ldc.i4.1 IL_003a 59 sub IL_003b 0a stloc.0 IL_003c 06 ldloc.0 IL_003d 16 ldc.i4.0 IL_003e 2f e5 bge.s -27 (IL_0025) IL_0040 16 ldc.i4.0 IL_0041 2a ret INLINER impTokenLookupContextHandle for Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger,byref):int is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger,byref):int weight= 77 : state 16 [ ldarga.s ] weight= 79 : state 40 [ call ] weight= 27 : state 44 [ brfalse.s ] weight= 16 : state 4 [ ldarg.1 ] weight= 28 : state 24 [ ldc.i4.1 ] weight=152 : state 118 [ newarr ] weight= 60 : state 69 [ stind.ref ] weight= 15 : state 23 [ ldc.i4.0 ] weight= 19 : state 42 [ ret ] weight= 16 : state 4 [ ldarg.1 ] weight= 77 : state 16 [ ldarga.s ] weight= 79 : state 40 [ call ] weight= 60 : state 69 [ stind.ref ] weight= 16 : state 4 [ ldarg.1 ] weight= 1 : state 68 [ ldind.ref ] weight= 7 : state 119 [ ldlen ] weight= 2 : state 93 [ conv.i4 ] weight= 28 : state 24 [ ldc.i4.1 ] weight=-15 : state 77 [ sub ] weight= 6 : state 11 [ stloc.0 ] weight= 44 : state 43 [ br.s ] weight= 16 : state 4 [ ldarg.1 ] weight= 1 : state 68 [ ldind.ref ] weight= 12 : state 7 [ ldloc.0 ] weight= 91 : state 122 [ ldelem.u1 ] weight= -7 : state 200 [ stloc.1 -> ldloc.1 ] weight= 27 : state 44 [ brfalse.s ] weight= 42 : state 31 [ ldc.i4.8 ] weight= 12 : state 7 [ ldloc.0 ] weight= -9 : state 78 [ mul ] weight= 9 : state 8 [ ldloc.1 ] weight= 79 : state 40 [ call ] weight=-12 : state 76 [ add ] weight= 19 : state 42 [ ret ] weight= 12 : state 7 [ ldloc.0 ] weight= 28 : state 24 [ ldc.i4.1 ] weight=-15 : state 77 [ sub ] weight= 20 : state 199 [ stloc.0 -> ldloc.0 ] weight= 15 : state 23 [ ldc.i4.0 ] weight= 20 : state 47 [ bge.s ] weight= 15 : state 23 [ ldc.i4.0 ] weight= 19 : state 42 [ ret ] Inline candidate has an arg that feeds a constant test. Multiplier increased to 1. Inline candidate callsite is boring. Multiplier increased to 2.3. calleeNativeSizeEstimate=1188 callsiteNativeSizeEstimate=135 benefit multiplier=2.3 threshold=310 Native estimate for function size exceeds threshold for inlining 118.8 > 31 (multiplier = 2.3) Inline expansion aborted, inline not profitable Inlining [000072] failed, so bashing STMT00018 to NOP INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' for 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' calling 'Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger,byref):int' INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' Replacing the return expression placeholder [000075] with [000072] [000075] --C--------- * RET_EXPR int (inl return from call [000072]) Inserting the inline return expression [000072] --C-G------- * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits [000074] n----------- arg0 +--* OBJ struct [000073] ------------ | \--* ADDR byref [000069] -------N---- | \--* LCL_VAR struct V11 loc8 [000071] ------------ arg1 \--* ADDR byref [000070] -------N---- \--* LCL_VAR ref V12 loc9 Expanding INLINE_CANDIDATE in statement STMT00075 in BB14: STMT00075 (IL 0x0C4...0x0D7) [000356] I-C-G------- * CALL int DecimalFloatingPointString.get_MantissaCount (exactContextHnd=0x00000000D1FFAB1E) [000355] ------------ this in rcx \--* ADDR byref [000354] -------N---- \--* LCL_VAR struct V00 arg0 thisArg: is a constant is byref to a struct local [000355] ------------ * ADDR byref [000354] -------N---- \--* LCL_VAR struct V00 arg0 INLINER: inlineInfo.tokenLookupContextHandle for DecimalFloatingPointString:get_MantissaCount():int:this set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method DecimalFloatingPointString:get_MantissaCount():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 38 10 00 04 ldfld 0x4001038 IL_0006 6f 9a 00 00 0a callvirt 0xA00009A IL_000b 2a ret INLINER impTokenLookupContextHandle for DecimalFloatingPointString:get_MantissaCount():int:this is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for DecimalFloatingPointString:get_MantissaCount():int:this Jump targets: none Computing inlinee profile scale: ... call site not profiled New Basic Block BB48 [0047] created. BB48 [000..00C) Basic block list for 'DecimalFloatingPointString:get_MantissaCount():int:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB48 [0047] 1 1 [000..00C) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000356] Starting PHASE Pre-import *************** Inline @[000356] Finishing PHASE Pre-import *************** Inline @[000356] Starting PHASE Importation *************** In impImport() for DecimalFloatingPointString:get_MantissaCount():int:this impImportBlockPending for BB48 Importing BB48 (PC=000) of 'DecimalFloatingPointString:get_MantissaCount():int:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 04001038 [ 1] 6 (0x006) callvirt 0A00009A In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is int, structSize is 0 [ 1] 11 (0x00b) ret Inlinee Return expression (before normalization) => [000456] ---XG------- * ARR_LENGTH int [000455] ----G------- \--* FIELD ref Mantissa [000453] ------------ \--* ADDR byref [000454] -------N---- \--* LCL_VAR struct V00 this Inlinee Return expression (after normalization) => [000456] ---XG------- * ARR_LENGTH int [000455] ----G------- \--* FIELD ref Mantissa [000453] ------------ \--* ADDR byref [000454] -------N---- \--* LCL_VAR struct V00 this ** Note: inlinee IL was partially imported -- imported 0 of 12 bytes of method IL *************** Inline @[000356] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB48 [0047] 1 1 [000..00C) (return) i idxlen ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB48 [000..00C) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000356] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000356] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000356] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000356] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000356] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000356] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000356] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000356] is [000456] ---XG------- * ARR_LENGTH int [000455] ----G------- \--* FIELD ref Mantissa [000453] ------------ \--* ADDR byref [000454] -------N---- \--* LCL_VAR struct V00 arg0 Successfully inlined DecimalFloatingPointString:get_MantissaCount():int:this (12 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' calling 'DecimalFloatingPointString:get_MantissaCount():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000357] with [000456] [000357] --C--------- * RET_EXPR int (inl return from call [000456]) Inserting the inline return expression [000456] ---XG------- * ARR_LENGTH int [000455] ----G------- \--* FIELD ref Mantissa [000453] ------------ \--* ADDR byref [000454] -------N---- \--* LCL_VAR struct V00 arg0 Expanding INLINE_CANDIDATE in statement STMT00076 in BB14: STMT00076 (IL ???... ???) [000361] I-C-G------- * CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent (exactContextHnd=0x00000000D1FFAB1E) [000360] ------------ this in rcx \--* LCL_VAR ref V01 arg1 thisArg: is a local var [000360] ------------ * LCL_VAR ref V01 arg1 INLINER: inlineInfo.tokenLookupContextHandle for FloatingPointType:get_OverflowDecimalExponent():int:this set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method FloatingPointType:get_OverflowDecimalExponent():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 6f 5e 20 00 06 callvirt 0x600205E IL_0006 18 ldc.i4.2 IL_0007 02 ldarg.0 IL_0008 28 5b 20 00 06 call 0x600205B IL_000d 5a mul IL_000e 58 add IL_000f 19 ldc.i4.3 IL_0010 5b div IL_0011 2a ret INLINER impTokenLookupContextHandle for FloatingPointType:get_OverflowDecimalExponent():int:this is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for FloatingPointType:get_OverflowDecimalExponent():int:this weight= 10 : state 3 [ ldarg.0 ] weight= 83 : state 99 [ callvirt ] weight= 34 : state 25 [ ldc.i4.2 ] weight= 10 : state 3 [ ldarg.0 ] weight= 79 : state 40 [ call ] weight= -9 : state 78 [ mul ] weight=-12 : state 76 [ add ] weight= -6 : state 26 [ ldc.i4.3 ] weight= 35 : state 79 [ div ] weight= 19 : state 42 [ ret ] Inline candidate callsite is boring. Multiplier increased to 1.3. calleeNativeSizeEstimate=243 callsiteNativeSizeEstimate=85 benefit multiplier=1.3 threshold=110 Native estimate for function size exceeds threshold for inlining 24.3 > 11 (multiplier = 1.3) Inline expansion aborted, inline not profitable Inlining [000361] failed, so bashing STMT00076 to NOP INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' for 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' calling 'FloatingPointType:get_OverflowDecimalExponent():int:this' INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' Replacing the return expression placeholder [000365] with [000361] [000365] --C--------- * RET_EXPR int (inl return from call [000361]) Inserting the inline return expression [000361] --C-G------- * CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent [000360] ------------ this in rcx \--* LCL_VAR ref V01 arg1 **** Late devirt opportunity [000371] --C-G------- * CALLV ind long FloatingPointType.get_Zero [000370] ------------ this in rcx \--* LCL_VAR ref V01 arg1 impDevirtualizeCall: Trying to devirtualize virtual call: class for 'this' is FloatingPointType (attrib 20000400) base method is FloatingPointType::get_Zero devirt to FloatingPointType::get_Zero -- inexact or not final [000371] --C-G------- * CALLV ind long FloatingPointType.get_Zero [000370] ------------ this in rcx \--* LCL_VAR ref V01 arg1 Class not final or exact, and method not final No guarded devirt during late devirtualization Expanding INLINE_CANDIDATE in statement STMT00027 in BB16: STMT00027 (IL 0x0E3...0x0ED) [000120] I-C-G------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger (exactContextHnd=0x00000000D1FFAB1E) [000125] ------------ arg0 +--* ADDR byref [000124] -------N---- | \--* LCL_VAR struct V15 loc12 [000122] n----------- arg1 +--* OBJ struct [000121] ------------ | \--* ADDR byref [000117] -------N---- | \--* LCL_VAR struct V00 arg0 [000118] ------------ arg2 +--* LCL_VAR int V08 loc5 [000119] ------------ arg3 \--* LCL_VAR int V09 loc6 Argument #0: has caller local ref [000122] n----------- * OBJ struct [000121] ------------ \--* ADDR byref [000117] -------N---- \--* LCL_VAR struct V00 arg0 Argument #1: is a local var [000118] ------------ * LCL_VAR int V08 loc5 Argument #2: is a local var [000119] ------------ * LCL_VAR int V09 loc6 INLINER: inlineInfo.tokenLookupContextHandle for Microsoft.CodeAnalysis.RealParser:AccumulateDecimalDigitsIntoBigInteger(DecimalFloatingPointString,int,int):System.Numerics.BigInteger set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method Microsoft.CodeAnalysis.RealParser:AccumulateDecimalDigitsIntoBigInteger(DecimalFloatingPointString,int,int):System.Numerics.BigInteger : IL to import: IL_0000 03 ldarg.1 IL_0001 04 ldarg.2 IL_0002 33 06 bne.un.s 6 (IL_000a) IL_0004 7e 9c 02 00 04 ldsfld 0x400029C IL_0009 2a ret IL_000a 02 ldarg.0 IL_000b 7b 38 10 00 04 ldfld 0x4001038 IL_0010 03 ldarg.1 IL_0011 04 ldarg.2 IL_0012 03 ldarg.1 IL_0013 59 sub IL_0014 6f c7 03 00 0a callvirt 0xA0003C7 IL_0019 28 c8 03 00 0a call 0xA0003C8 IL_001e 2a ret INLINER impTokenLookupContextHandle for Microsoft.CodeAnalysis.RealParser:AccumulateDecimalDigitsIntoBigInteger(DecimalFloatingPointString,int,int):System.Numerics.BigInteger is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for Microsoft.CodeAnalysis.RealParser:AccumulateDecimalDigitsIntoBigInteger(DecimalFloatingPointString,int,int):System.Numerics.BigInteger weight= 16 : state 4 [ ldarg.1 ] weight= 35 : state 5 [ ldarg.2 ] weight= 12 : state 51 [ bne.un.s ] weight=159 : state 112 [ ldsfld ] weight= 19 : state 42 [ ret ] weight= 31 : state 191 [ ldarg.0 -> ldfld ] weight= 16 : state 4 [ ldarg.1 ] weight= 35 : state 5 [ ldarg.2 ] weight= 16 : state 4 [ ldarg.1 ] weight=-15 : state 77 [ sub ] weight= 83 : state 99 [ callvirt ] weight= 79 : state 40 [ call ] weight= 19 : state 42 [ ret ] Inline candidate looks like a wrapper method. Multiplier increased to 1. Inline candidate callsite is boring. Multiplier increased to 2.3. calleeNativeSizeEstimate=505 callsiteNativeSizeEstimate=165 benefit multiplier=2.3 threshold=379 Native estimate for function size exceeds threshold for inlining 50.5 > 37.9 (multiplier = 2.3) Inline expansion aborted, inline not profitable Inlining [000120] failed, so bashing STMT00027 to NOP INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' for 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' calling 'Microsoft.CodeAnalysis.RealParser:AccumulateDecimalDigitsIntoBigInteger(DecimalFloatingPointString,int,int):System.Numerics.BigInteger' INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' Replacing the return expression placeholder [000123] with [000120] [000123] --C--------- * RET_EXPR void (inl return from call [000120]) Inserting the inline return expression [000120] S-C-G------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger [000125] ------------ arg0 +--* ADDR byref [000124] -------N---- | \--* LCL_VAR struct V15 loc12 [000122] n----------- arg1 +--* OBJ struct [000121] ------------ | \--* ADDR byref [000117] -------N---- | \--* LCL_VAR struct V00 arg0 [000118] ------------ arg2 +--* LCL_VAR int V08 loc5 [000119] ------------ arg3 \--* LCL_VAR int V09 loc6 Expanding INLINE_CANDIDATE in statement STMT00031 in BB16: STMT00031 (IL 0x0F6...0x106) [000141] I-C-G------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen (exactContextHnd=0x00000000D1FFAB1E) [000139] ------------ arg0 +--* ADDR byref [000138] -------N---- | \--* LCL_VAR struct V16 loc13 [000140] ------------ arg1 \--* LCL_VAR int V14 loc11 Argument #0: is a constant is byref to a struct local [000139] ------------ * ADDR byref [000138] -------N---- \--* LCL_VAR struct V16 loc13 Argument #1: is a local var [000140] ------------ * LCL_VAR int V14 loc11 INLINER: inlineInfo.tokenLookupContextHandle for Microsoft.CodeAnalysis.RealParser:MultiplyByPowerOfTen(byref,int) set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method Microsoft.CodeAnalysis.RealParser:MultiplyByPowerOfTen(byref,int) : IL to import: IL_0000 7e 9f 02 00 04 ldsfld 0x400029F IL_0005 03 ldarg.1 IL_0006 28 ca 03 00 0a call 0xA0003CA IL_000b 0a stloc.0 IL_000c 02 ldarg.0 IL_000d 02 ldarg.0 IL_000e 71 67 00 00 01 ldobj 0x1000067 IL_0013 06 ldloc.0 IL_0014 28 cb 03 00 0a call 0xA0003CB IL_0019 81 67 00 00 01 stobj 0x1000067 IL_001e 2a ret INLINER impTokenLookupContextHandle for Microsoft.CodeAnalysis.RealParser:MultiplyByPowerOfTen(byref,int) is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for Microsoft.CodeAnalysis.RealParser:MultiplyByPowerOfTen(byref,int) weight=159 : state 112 [ ldsfld ] weight= 16 : state 4 [ ldarg.1 ] weight= 79 : state 40 [ call ] weight= 6 : state 11 [ stloc.0 ] weight= 10 : state 3 [ ldarg.0 ] weight= 10 : state 3 [ ldarg.0 ] weight= 29 : state 101 [ ldobj ] weight= 12 : state 7 [ ldloc.0 ] weight= 79 : state 40 [ call ] weight= 36 : state 115 [ stobj ] weight= 19 : state 42 [ ret ] Inline candidate callsite is boring. Multiplier increased to 1.3. calleeNativeSizeEstimate=455 callsiteNativeSizeEstimate=115 benefit multiplier=1.3 threshold=149 Native estimate for function size exceeds threshold for inlining 45.5 > 14.9 (multiplier = 1.3) Inline expansion aborted, inline not profitable INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' for 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' calling 'Microsoft.CodeAnalysis.RealParser:MultiplyByPowerOfTen(byref,int)' INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' Expanding INLINE_CANDIDATE in statement STMT00032 in BB16: STMT00032 (IL 0x0FF... ???) [000143] I-C-G------- * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits (exactContextHnd=0x00000000D1FFAB1E) [000145] n----------- arg0 \--* OBJ struct [000144] ------------ \--* ADDR byref [000142] -------N---- \--* LCL_VAR struct V15 loc12 Argument #0: has caller local ref [000145] n----------- * OBJ struct [000144] ------------ \--* ADDR byref [000142] -------N---- \--* LCL_VAR struct V15 loc12 INLINER: inlineInfo.tokenLookupContextHandle for Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger):int set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger):int : IL to import: IL_0000 02 ldarg.0 IL_0001 12 00 ldloca.s 0x0 IL_0003 28 ee 06 00 06 call 0x60006EE IL_0008 2a ret INLINER impTokenLookupContextHandle for Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger):int is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger):int Jump targets: none Computing inlinee profile scale: ... call site not profiled New Basic Block BB49 [0048] created. BB49 [000..009) lvaGrabTemp returning 43 (V43 tmp13) (a long lifetime temp) called for Inline return value spill temp. Basic block list for 'Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger):int' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB49 [0048] 1 1 [000..009) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000143] Starting PHASE Pre-import *************** Inline @[000143] Finishing PHASE Pre-import *************** Inline @[000143] Starting PHASE Importation *************** In impImport() for Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger):int impImportBlockPending for BB49 Importing BB49 (PC=000) of 'Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger):int' [ 0] 0 (0x000) ldarg.0 lvaGrabTemp returning 44 (V44 tmp14) called for Inlining Arg. [ 1] 1 (0x001) ldloca.s 0 lvaGrabTemp returning 45 (V45 tmp15) (a long lifetime temp) called for Inline ldloca(s) first use temp. lvaSetClass: setting class for V45 to (00000000D1FFAB1E) System.Byte[] [ 2] 3 (0x003) call 060006EE In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 Calling impNormStructVal on: [000460] ------------ * LCL_VAR struct V44 tmp14 resulting tree: [000465] n----------- * OBJ struct [000464] ------------ \--* ADDR byref [000460] -------N---- \--* LCL_VAR struct V44 tmp14 [000463] I-C-G------- * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits (exactContextHnd=0x00000000D1FFAB1E) [000465] n----------- arg0 +--* OBJ struct [000464] ------------ | \--* ADDR byref [000460] -------N---- | \--* LCL_VAR struct V44 tmp14 [000462] ------------ arg1 \--* ADDR byref [000461] -------N---- \--* LCL_VAR ref V45 tmp15 [ 1] 8 (0x008) ret Inlinee Return expression (before normalization) => [000466] --C--------- * RET_EXPR int (inl return from call [000463]) [000468] -AC--------- * ASG int [000467] D------N---- +--* LCL_VAR int V43 tmp13 [000466] --C--------- \--* RET_EXPR int (inl return from call [000463]) Inlinee Return expression (after normalization) => [000469] ------------ * LCL_VAR int V43 tmp13 *************** Inline @[000143] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB49 [0048] 1 1 [000..009) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB49 [000..009) (return), preds={} succs={} ***** BB49 [000463] I-C-G------- * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits (exactContextHnd=0x00000000D1FFAB1E) [000465] n----------- arg0 +--* OBJ struct [000464] ------------ | \--* ADDR byref [000460] -------N---- | \--* LCL_VAR struct V44 tmp14 [000462] ------------ arg1 \--* ADDR byref [000461] -------N---- \--* LCL_VAR ref V45 tmp15 ***** BB49 [000468] -AC--------- * ASG int [000467] D------N---- +--* LCL_VAR int V43 tmp13 [000466] --C--------- \--* RET_EXPR int (inl return from call [000463]) ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000143] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000143] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000143] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000143] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000143] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000143] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000143] ----------- Arguments setup: STMT00099 (IL 0x0FF... ???) [000472] -A---------- * ASG struct (copy) [000470] D------N---- +--* LCL_VAR struct V44 tmp14 [000145] n----------- \--* OBJ struct [000144] ------------ \--* ADDR byref [000142] -------N---- \--* LCL_VAR struct V15 loc12 Inlinee method body: STMT00097 (IL 0x0FF... ???) [000463] I-C-G------- * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits (exactContextHnd=0x00000000D1FFAB1E) [000465] n----------- arg0 +--* OBJ struct [000464] ------------ | \--* ADDR byref [000460] -------N---- | \--* LCL_VAR struct V44 tmp14 [000462] ------------ arg1 \--* ADDR byref [000461] -------N---- \--* LCL_VAR ref V45 tmp15 STMT00098 (IL 0x0FF... ???) [000468] -AC--------- * ASG int [000467] D------N---- +--* LCL_VAR int V43 tmp13 [000466] --C--------- \--* RET_EXPR int (inl return from call [000463]) fgInlineAppendStatements: nulling out gc ref inlinee locals. STMT00100 (IL 0x0FF... ???) [000475] -A---------- * ASG ref [000474] D------N---- +--* LCL_VAR ref V45 tmp15 [000473] ------------ \--* CNS_INT ref null Return expression for call at [000143] is [000469] ------------ * LCL_VAR int V43 tmp13 Successfully inlined Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger):int (9 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' calling 'Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger):int' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Expanding INLINE_CANDIDATE in statement STMT00097 in BB16: STMT00097 (IL 0x0FF... ???) [000463] I-C-G------- * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits (exactContextHnd=0x00000000D1FFAB1E) [000465] n----------- arg0 +--* OBJ struct [000464] ------------ | \--* ADDR byref [000460] -------N---- | \--* LCL_VAR struct V44 tmp14 [000462] ------------ arg1 \--* ADDR byref [000461] -------N---- \--* LCL_VAR ref V45 tmp15 Argument #0: [000465] n----------- * OBJ struct [000464] ------------ \--* ADDR byref [000460] -------N---- \--* LCL_VAR struct V44 tmp14 Argument #1: is a constant [000462] ------------ * ADDR byref [000461] -------N---- \--* LCL_VAR ref V45 tmp15 INLINER: inlineInfo.tokenLookupContextHandle for Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger,byref):int set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger,byref):int : IL to import: IL_0000 0f 00 ldarga.s 0x0 IL_0002 28 c6 03 00 0a call 0xA0003C6 IL_0007 2c 0a brfalse.s 10 (IL_0013) IL_0009 03 ldarg.1 IL_000a 17 ldc.i4.1 IL_000b 8d 9a 00 00 01 newarr 0x100009A IL_0010 51 stind.ref IL_0011 16 ldc.i4.0 IL_0012 2a ret IL_0013 03 ldarg.1 IL_0014 0f 00 ldarga.s 0x0 IL_0016 28 c9 03 00 0a call 0xA0003C9 IL_001b 51 stind.ref IL_001c 03 ldarg.1 IL_001d 50 ldind.ref IL_001e 8e ldlen IL_001f 69 conv.i4 IL_0020 17 ldc.i4.1 IL_0021 59 sub IL_0022 0a stloc.0 IL_0023 2b 17 br.s 23 (IL_003c) IL_0025 03 ldarg.1 IL_0026 50 ldind.ref IL_0027 06 ldloc.0 IL_0028 91 ldelem.u1 IL_0029 0b stloc.1 IL_002a 07 ldloc.1 IL_002b 2c 0b brfalse.s 11 (IL_0038) IL_002d 1e ldc.i4.8 IL_002e 06 ldloc.0 IL_002f 5a mul IL_0030 07 ldloc.1 IL_0031 28 ed 06 00 06 call 0x60006ED IL_0036 58 add IL_0037 2a ret IL_0038 06 ldloc.0 IL_0039 17 ldc.i4.1 IL_003a 59 sub IL_003b 0a stloc.0 IL_003c 06 ldloc.0 IL_003d 16 ldc.i4.0 IL_003e 2f e5 bge.s -27 (IL_0025) IL_0040 16 ldc.i4.0 IL_0041 2a ret INLINER impTokenLookupContextHandle for Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger,byref):int is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger,byref):int weight= 77 : state 16 [ ldarga.s ] weight= 79 : state 40 [ call ] weight= 27 : state 44 [ brfalse.s ] weight= 16 : state 4 [ ldarg.1 ] weight= 28 : state 24 [ ldc.i4.1 ] weight=152 : state 118 [ newarr ] weight= 60 : state 69 [ stind.ref ] weight= 15 : state 23 [ ldc.i4.0 ] weight= 19 : state 42 [ ret ] weight= 16 : state 4 [ ldarg.1 ] weight= 77 : state 16 [ ldarga.s ] weight= 79 : state 40 [ call ] weight= 60 : state 69 [ stind.ref ] weight= 16 : state 4 [ ldarg.1 ] weight= 1 : state 68 [ ldind.ref ] weight= 7 : state 119 [ ldlen ] weight= 2 : state 93 [ conv.i4 ] weight= 28 : state 24 [ ldc.i4.1 ] weight=-15 : state 77 [ sub ] weight= 6 : state 11 [ stloc.0 ] weight= 44 : state 43 [ br.s ] weight= 16 : state 4 [ ldarg.1 ] weight= 1 : state 68 [ ldind.ref ] weight= 12 : state 7 [ ldloc.0 ] weight= 91 : state 122 [ ldelem.u1 ] weight= -7 : state 200 [ stloc.1 -> ldloc.1 ] weight= 27 : state 44 [ brfalse.s ] weight= 42 : state 31 [ ldc.i4.8 ] weight= 12 : state 7 [ ldloc.0 ] weight= -9 : state 78 [ mul ] weight= 9 : state 8 [ ldloc.1 ] weight= 79 : state 40 [ call ] weight=-12 : state 76 [ add ] weight= 19 : state 42 [ ret ] weight= 12 : state 7 [ ldloc.0 ] weight= 28 : state 24 [ ldc.i4.1 ] weight=-15 : state 77 [ sub ] weight= 20 : state 199 [ stloc.0 -> ldloc.0 ] weight= 15 : state 23 [ ldc.i4.0 ] weight= 20 : state 47 [ bge.s ] weight= 15 : state 23 [ ldc.i4.0 ] weight= 19 : state 42 [ ret ] Inline candidate has an arg that feeds a constant test. Multiplier increased to 1. Inline candidate callsite is boring. Multiplier increased to 2.3. calleeNativeSizeEstimate=1188 callsiteNativeSizeEstimate=135 benefit multiplier=2.3 threshold=310 Native estimate for function size exceeds threshold for inlining 118.8 > 31 (multiplier = 2.3) Inline expansion aborted, inline not profitable Inlining [000463] failed, so bashing STMT00097 to NOP INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' for 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' calling 'Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger,byref):int' INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' Replacing the return expression placeholder [000466] with [000463] [000466] --C--------- * RET_EXPR int (inl return from call [000463]) Inserting the inline return expression [000463] --C-G------- * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits [000465] n----------- arg0 +--* OBJ struct [000464] ------------ | \--* ADDR byref [000460] -------N---- | \--* LCL_VAR struct V44 tmp14 [000462] ------------ arg1 \--* ADDR byref [000461] -------N---- \--* LCL_VAR ref V45 tmp15 Replacing the return expression placeholder [000146] with [000469] [000146] --C--------- * RET_EXPR int (inl return from call [000469]) Inserting the inline return expression [000469] ------------ * LCL_VAR int V43 tmp13 Expanding INLINE_CANDIDATE in statement STMT00034 in BB16: STMT00034 (IL 0x108...0x10F) [000150] I-C-G------- * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits (exactContextHnd=0x00000000D1FFAB1E) [000152] n----------- arg0 \--* OBJ struct [000151] ------------ \--* ADDR byref [000149] -------N---- \--* LCL_VAR struct V16 loc13 Argument #0: has caller local ref [000152] n----------- * OBJ struct [000151] ------------ \--* ADDR byref [000149] -------N---- \--* LCL_VAR struct V16 loc13 INLINER: inlineInfo.tokenLookupContextHandle for Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger):int set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger):int : IL to import: IL_0000 02 ldarg.0 IL_0001 12 00 ldloca.s 0x0 IL_0003 28 ee 06 00 06 call 0x60006EE IL_0008 2a ret INLINER impTokenLookupContextHandle for Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger):int is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger):int Jump targets: none Computing inlinee profile scale: ... call site not profiled New Basic Block BB50 [0049] created. BB50 [000..009) lvaGrabTemp returning 46 (V46 tmp16) (a long lifetime temp) called for Inline return value spill temp. Basic block list for 'Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger):int' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB50 [0049] 1 1 [000..009) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000150] Starting PHASE Pre-import *************** Inline @[000150] Finishing PHASE Pre-import *************** Inline @[000150] Starting PHASE Importation *************** In impImport() for Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger):int impImportBlockPending for BB50 Importing BB50 (PC=000) of 'Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger):int' [ 0] 0 (0x000) ldarg.0 lvaGrabTemp returning 47 (V47 tmp17) called for Inlining Arg. [ 1] 1 (0x001) ldloca.s 0 lvaGrabTemp returning 48 (V48 tmp18) (a long lifetime temp) called for Inline ldloca(s) first use temp. lvaSetClass: setting class for V48 to (00000000D1FFAB1E) System.Byte[] [ 2] 3 (0x003) call 060006EE In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 Calling impNormStructVal on: [000478] ------------ * LCL_VAR struct V47 tmp17 resulting tree: [000483] n----------- * OBJ struct [000482] ------------ \--* ADDR byref [000478] -------N---- \--* LCL_VAR struct V47 tmp17 [000481] I-C-G------- * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits (exactContextHnd=0x00000000D1FFAB1E) [000483] n----------- arg0 +--* OBJ struct [000482] ------------ | \--* ADDR byref [000478] -------N---- | \--* LCL_VAR struct V47 tmp17 [000480] ------------ arg1 \--* ADDR byref [000479] -------N---- \--* LCL_VAR ref V48 tmp18 [ 1] 8 (0x008) ret Inlinee Return expression (before normalization) => [000484] --C--------- * RET_EXPR int (inl return from call [000481]) [000486] -AC--------- * ASG int [000485] D------N---- +--* LCL_VAR int V46 tmp16 [000484] --C--------- \--* RET_EXPR int (inl return from call [000481]) Inlinee Return expression (after normalization) => [000487] ------------ * LCL_VAR int V46 tmp16 *************** Inline @[000150] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB50 [0049] 1 1 [000..009) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB50 [000..009) (return), preds={} succs={} ***** BB50 [000481] I-C-G------- * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits (exactContextHnd=0x00000000D1FFAB1E) [000483] n----------- arg0 +--* OBJ struct [000482] ------------ | \--* ADDR byref [000478] -------N---- | \--* LCL_VAR struct V47 tmp17 [000480] ------------ arg1 \--* ADDR byref [000479] -------N---- \--* LCL_VAR ref V48 tmp18 ***** BB50 [000486] -AC--------- * ASG int [000485] D------N---- +--* LCL_VAR int V46 tmp16 [000484] --C--------- \--* RET_EXPR int (inl return from call [000481]) ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000150] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000150] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000150] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000150] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000150] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000150] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000150] ----------- Arguments setup: STMT00103 (IL 0x108... ???) [000490] -A---------- * ASG struct (copy) [000488] D------N---- +--* LCL_VAR struct V47 tmp17 [000152] n----------- \--* OBJ struct [000151] ------------ \--* ADDR byref [000149] -------N---- \--* LCL_VAR struct V16 loc13 Inlinee method body: STMT00101 (IL 0x108... ???) [000481] I-C-G------- * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits (exactContextHnd=0x00000000D1FFAB1E) [000483] n----------- arg0 +--* OBJ struct [000482] ------------ | \--* ADDR byref [000478] -------N---- | \--* LCL_VAR struct V47 tmp17 [000480] ------------ arg1 \--* ADDR byref [000479] -------N---- \--* LCL_VAR ref V48 tmp18 STMT00102 (IL 0x108... ???) [000486] -AC--------- * ASG int [000485] D------N---- +--* LCL_VAR int V46 tmp16 [000484] --C--------- \--* RET_EXPR int (inl return from call [000481]) fgInlineAppendStatements: nulling out gc ref inlinee locals. STMT00104 (IL 0x108... ???) [000493] -A---------- * ASG ref [000492] D------N---- +--* LCL_VAR ref V48 tmp18 [000491] ------------ \--* CNS_INT ref null Return expression for call at [000150] is [000487] ------------ * LCL_VAR int V46 tmp16 Successfully inlined Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger):int (9 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' calling 'Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger):int' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Expanding INLINE_CANDIDATE in statement STMT00101 in BB16: STMT00101 (IL 0x108... ???) [000481] I-C-G------- * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits (exactContextHnd=0x00000000D1FFAB1E) [000483] n----------- arg0 +--* OBJ struct [000482] ------------ | \--* ADDR byref [000478] -------N---- | \--* LCL_VAR struct V47 tmp17 [000480] ------------ arg1 \--* ADDR byref [000479] -------N---- \--* LCL_VAR ref V48 tmp18 Argument #0: [000483] n----------- * OBJ struct [000482] ------------ \--* ADDR byref [000478] -------N---- \--* LCL_VAR struct V47 tmp17 Argument #1: is a constant [000480] ------------ * ADDR byref [000479] -------N---- \--* LCL_VAR ref V48 tmp18 INLINER: inlineInfo.tokenLookupContextHandle for Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger,byref):int set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger,byref):int : IL to import: IL_0000 0f 00 ldarga.s 0x0 IL_0002 28 c6 03 00 0a call 0xA0003C6 IL_0007 2c 0a brfalse.s 10 (IL_0013) IL_0009 03 ldarg.1 IL_000a 17 ldc.i4.1 IL_000b 8d 9a 00 00 01 newarr 0x100009A IL_0010 51 stind.ref IL_0011 16 ldc.i4.0 IL_0012 2a ret IL_0013 03 ldarg.1 IL_0014 0f 00 ldarga.s 0x0 IL_0016 28 c9 03 00 0a call 0xA0003C9 IL_001b 51 stind.ref IL_001c 03 ldarg.1 IL_001d 50 ldind.ref IL_001e 8e ldlen IL_001f 69 conv.i4 IL_0020 17 ldc.i4.1 IL_0021 59 sub IL_0022 0a stloc.0 IL_0023 2b 17 br.s 23 (IL_003c) IL_0025 03 ldarg.1 IL_0026 50 ldind.ref IL_0027 06 ldloc.0 IL_0028 91 ldelem.u1 IL_0029 0b stloc.1 IL_002a 07 ldloc.1 IL_002b 2c 0b brfalse.s 11 (IL_0038) IL_002d 1e ldc.i4.8 IL_002e 06 ldloc.0 IL_002f 5a mul IL_0030 07 ldloc.1 IL_0031 28 ed 06 00 06 call 0x60006ED IL_0036 58 add IL_0037 2a ret IL_0038 06 ldloc.0 IL_0039 17 ldc.i4.1 IL_003a 59 sub IL_003b 0a stloc.0 IL_003c 06 ldloc.0 IL_003d 16 ldc.i4.0 IL_003e 2f e5 bge.s -27 (IL_0025) IL_0040 16 ldc.i4.0 IL_0041 2a ret INLINER impTokenLookupContextHandle for Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger,byref):int is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger,byref):int weight= 77 : state 16 [ ldarga.s ] weight= 79 : state 40 [ call ] weight= 27 : state 44 [ brfalse.s ] weight= 16 : state 4 [ ldarg.1 ] weight= 28 : state 24 [ ldc.i4.1 ] weight=152 : state 118 [ newarr ] weight= 60 : state 69 [ stind.ref ] weight= 15 : state 23 [ ldc.i4.0 ] weight= 19 : state 42 [ ret ] weight= 16 : state 4 [ ldarg.1 ] weight= 77 : state 16 [ ldarga.s ] weight= 79 : state 40 [ call ] weight= 60 : state 69 [ stind.ref ] weight= 16 : state 4 [ ldarg.1 ] weight= 1 : state 68 [ ldind.ref ] weight= 7 : state 119 [ ldlen ] weight= 2 : state 93 [ conv.i4 ] weight= 28 : state 24 [ ldc.i4.1 ] weight=-15 : state 77 [ sub ] weight= 6 : state 11 [ stloc.0 ] weight= 44 : state 43 [ br.s ] weight= 16 : state 4 [ ldarg.1 ] weight= 1 : state 68 [ ldind.ref ] weight= 12 : state 7 [ ldloc.0 ] weight= 91 : state 122 [ ldelem.u1 ] weight= -7 : state 200 [ stloc.1 -> ldloc.1 ] weight= 27 : state 44 [ brfalse.s ] weight= 42 : state 31 [ ldc.i4.8 ] weight= 12 : state 7 [ ldloc.0 ] weight= -9 : state 78 [ mul ] weight= 9 : state 8 [ ldloc.1 ] weight= 79 : state 40 [ call ] weight=-12 : state 76 [ add ] weight= 19 : state 42 [ ret ] weight= 12 : state 7 [ ldloc.0 ] weight= 28 : state 24 [ ldc.i4.1 ] weight=-15 : state 77 [ sub ] weight= 20 : state 199 [ stloc.0 -> ldloc.0 ] weight= 15 : state 23 [ ldc.i4.0 ] weight= 20 : state 47 [ bge.s ] weight= 15 : state 23 [ ldc.i4.0 ] weight= 19 : state 42 [ ret ] Inline candidate has an arg that feeds a constant test. Multiplier increased to 1. Inline candidate callsite is boring. Multiplier increased to 2.3. calleeNativeSizeEstimate=1188 callsiteNativeSizeEstimate=135 benefit multiplier=2.3 threshold=310 Native estimate for function size exceeds threshold for inlining 118.8 > 31 (multiplier = 2.3) Inline expansion aborted, inline not profitable Inlining [000481] failed, so bashing STMT00101 to NOP INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' for 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' calling 'Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger,byref):int' INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' Replacing the return expression placeholder [000484] with [000481] [000484] --C--------- * RET_EXPR int (inl return from call [000481]) Inserting the inline return expression [000481] --C-G------- * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits [000483] n----------- arg0 +--* OBJ struct [000482] ------------ | \--* ADDR byref [000478] -------N---- | \--* LCL_VAR struct V47 tmp17 [000480] ------------ arg1 \--* ADDR byref [000479] -------N---- \--* LCL_VAR ref V48 tmp18 Replacing the return expression placeholder [000153] with [000487] [000153] --C--------- * RET_EXPR int (inl return from call [000487]) Inserting the inline return expression [000487] ------------ * LCL_VAR int V46 tmp16 Expanding INLINE_CANDIDATE in statement STMT00073 in BB20: STMT00073 (IL 0x126...0x12A) [000347] I-C-G------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft (exactContextHnd=0x00000000D1FFAB1E) [000345] ------------ arg0 +--* ADDR byref [000344] -------N---- | \--* LCL_VAR struct V15 loc12 [000346] ------------ arg1 \--* LCL_VAR int V19 loc16 Argument #0: is a constant is byref to a struct local [000345] ------------ * ADDR byref [000344] -------N---- \--* LCL_VAR struct V15 loc12 Argument #1: is a local var [000346] ------------ * LCL_VAR int V19 loc16 INLINER: inlineInfo.tokenLookupContextHandle for Microsoft.CodeAnalysis.RealParser:ShiftLeft(byref,int) set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method Microsoft.CodeAnalysis.RealParser:ShiftLeft(byref,int) : IL to import: IL_0000 7e 9e 02 00 04 ldsfld 0x400029E IL_0005 03 ldarg.1 IL_0006 28 ca 03 00 0a call 0xA0003CA IL_000b 0a stloc.0 IL_000c 02 ldarg.0 IL_000d 02 ldarg.0 IL_000e 71 67 00 00 01 ldobj 0x1000067 IL_0013 06 ldloc.0 IL_0014 28 cb 03 00 0a call 0xA0003CB IL_0019 81 67 00 00 01 stobj 0x1000067 IL_001e 2a ret INLINER impTokenLookupContextHandle for Microsoft.CodeAnalysis.RealParser:ShiftLeft(byref,int) is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for Microsoft.CodeAnalysis.RealParser:ShiftLeft(byref,int) weight=159 : state 112 [ ldsfld ] weight= 16 : state 4 [ ldarg.1 ] weight= 79 : state 40 [ call ] weight= 6 : state 11 [ stloc.0 ] weight= 10 : state 3 [ ldarg.0 ] weight= 10 : state 3 [ ldarg.0 ] weight= 29 : state 101 [ ldobj ] weight= 12 : state 7 [ ldloc.0 ] weight= 79 : state 40 [ call ] weight= 36 : state 115 [ stobj ] weight= 19 : state 42 [ ret ] Inline candidate callsite is boring. Multiplier increased to 1.3. calleeNativeSizeEstimate=455 callsiteNativeSizeEstimate=115 benefit multiplier=1.3 threshold=149 Native estimate for function size exceeds threshold for inlining 45.5 > 14.9 (multiplier = 1.3) Inline expansion aborted, inline not profitable INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' for 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' calling 'Microsoft.CodeAnalysis.RealParser:ShiftLeft(byref,int)' INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' Expanding INLINE_CANDIDATE in statement STMT00043 in BB25: STMT00043 (IL 0x15C...0x165) [000187] I-C-G------- * CALL int System.Numerics.BigInteger.op_LessThan (exactContextHnd=0x00000000D1FFAB1E) [000191] n----------- arg0 +--* OBJ struct [000190] ------------ | \--* ADDR byref [000185] -------N---- | \--* LCL_VAR struct V15 loc12 [000189] n----------- arg1 \--* OBJ struct [000188] ------------ \--* ADDR byref [000186] -------N---- \--* LCL_VAR struct V16 loc13 Argument #0: has caller local ref [000191] n----------- * OBJ struct [000190] ------------ \--* ADDR byref [000185] -------N---- \--* LCL_VAR struct V15 loc12 Argument #1: has caller local ref [000189] n----------- * OBJ struct [000188] ------------ \--* ADDR byref [000186] -------N---- \--* LCL_VAR struct V16 loc13 INLINER: inlineInfo.tokenLookupContextHandle for System.Numerics.BigInteger:op_LessThan(System.Numerics.BigInteger,System.Numerics.BigInteger):bool set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method System.Numerics.BigInteger:op_LessThan(System.Numerics.BigInteger,System.Numerics.BigInteger):bool : IL to import: IL_0000 0f 00 ldarga.s 0x0 IL_0002 03 ldarg.1 IL_0003 28 c4 00 00 06 call 0x60000C4 IL_0008 16 ldc.i4.0 IL_0009 fe 04 clt IL_000b 2a ret INLINER impTokenLookupContextHandle for System.Numerics.BigInteger:op_LessThan(System.Numerics.BigInteger,System.Numerics.BigInteger):bool is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for System.Numerics.BigInteger:op_LessThan(System.Numerics.BigInteger,System.Numerics.BigInteger):bool Jump targets: none Computing inlinee profile scale: ... call site not profiled New Basic Block BB51 [0050] created. BB51 [000..00C) Basic block list for 'System.Numerics.BigInteger:op_LessThan(System.Numerics.BigInteger,System.Numerics.BigInteger):bool' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB51 [0050] 1 1 [000..00C) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000187] Starting PHASE Pre-import *************** Inline @[000187] Finishing PHASE Pre-import *************** Inline @[000187] Starting PHASE Importation *************** In impImport() for System.Numerics.BigInteger:op_LessThan(System.Numerics.BigInteger,System.Numerics.BigInteger):bool impImportBlockPending for BB51 Importing BB51 (PC=000) of 'System.Numerics.BigInteger:op_LessThan(System.Numerics.BigInteger,System.Numerics.BigInteger):bool' [ 0] 0 (0x000) ldarga.s 0 lvaGrabTemp returning 49 (V49 tmp19) called for Inlining Arg. [ 1] 2 (0x002) ldarg.1 lvaGrabTemp returning 50 (V50 tmp20) called for Inlining Arg. [ 2] 3 (0x003) call 060000C4 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 Calling impNormStructVal on: [000498] ------------ * LCL_VAR struct V50 tmp20 resulting tree: [000501] n----------- * OBJ struct [000500] ------------ \--* ADDR byref [000498] -------N---- \--* LCL_VAR struct V50 tmp20 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' for 'System.Numerics.BigInteger:op_LessThan(System.Numerics.BigInteger,System.Numerics.BigInteger):bool' calling 'System.Numerics.BigInteger:CompareTo(System.Numerics.BigInteger):int:this' INLINER: Marking System.Numerics.BigInteger:CompareTo(System.Numerics.BigInteger):int:this as NOINLINE because of too many il bytes INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' [ 1] 8 (0x008) ldc.i4.0 0 [ 2] 9 (0x009) clt [ 1] 11 (0x00b) ret Inlinee Return expression (before normalization) => [000503] --C-G------- * LT int [000499] --C-G------- +--* CALL int System.Numerics.BigInteger.CompareTo [000497] ------------ this in rcx | +--* ADDR byref [000496] -------N---- | | \--* LCL_VAR struct V49 tmp19 [000501] n----------- arg1 | \--* OBJ struct [000500] ------------ | \--* ADDR byref [000498] -------N---- | \--* LCL_VAR struct V50 tmp20 [000502] ------------ \--* CNS_INT int 0 Inlinee Return expression (after normalization) => [000503] --C-G------- * LT int [000499] --C-G------- +--* CALL int System.Numerics.BigInteger.CompareTo [000497] ------------ this in rcx | +--* ADDR byref [000496] -------N---- | | \--* LCL_VAR struct V49 tmp19 [000501] n----------- arg1 | \--* OBJ struct [000500] ------------ | \--* ADDR byref [000498] -------N---- | \--* LCL_VAR struct V50 tmp20 [000502] ------------ \--* CNS_INT int 0 ** Note: inlinee IL was partially imported -- imported 0 of 12 bytes of method IL *************** Inline @[000187] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB51 [0050] 1 1 [000..00C) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB51 [000..00C) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000187] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000187] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000187] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000187] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000187] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000187] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000187] ----------- Arguments setup: STMT00105 (IL 0x15C... ???) [000506] -A---------- * ASG struct (copy) [000504] D------N---- +--* LCL_VAR struct V49 tmp19 [000191] n----------- \--* OBJ struct [000190] ------------ \--* ADDR byref [000185] -------N---- \--* LCL_VAR struct V15 loc12 STMT00106 (IL 0x15C... ???) [000509] -A---------- * ASG struct (copy) [000507] D------N---- +--* LCL_VAR struct V50 tmp20 [000189] n----------- \--* OBJ struct [000188] ------------ \--* ADDR byref [000186] -------N---- \--* LCL_VAR struct V16 loc13 Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000187] is [000503] --C-G------- * LT int [000499] --C-G------- +--* CALL int System.Numerics.BigInteger.CompareTo [000497] ------------ this in rcx | +--* ADDR byref [000496] -------N---- | | \--* LCL_VAR struct V49 tmp19 [000501] n----------- arg1 | \--* OBJ struct [000500] ------------ | \--* ADDR byref [000498] -------N---- | \--* LCL_VAR struct V50 tmp20 [000502] ------------ \--* CNS_INT int 0 Successfully inlined System.Numerics.BigInteger:op_LessThan(System.Numerics.BigInteger,System.Numerics.BigInteger):bool (12 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' calling 'System.Numerics.BigInteger:op_LessThan(System.Numerics.BigInteger,System.Numerics.BigInteger):bool' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000192] with [000503] [000192] --C--------- * RET_EXPR int (inl return from call [000503]) Inserting the inline return expression [000503] --C-G------- * LT int [000499] --C-G------- +--* CALL int System.Numerics.BigInteger.CompareTo [000497] ------------ this in rcx | +--* ADDR byref [000496] -------N---- | | \--* LCL_VAR struct V49 tmp19 [000501] n----------- arg1 | \--* OBJ struct [000500] ------------ | \--* ADDR byref [000498] -------N---- | \--* LCL_VAR struct V50 tmp20 [000502] ------------ \--* CNS_INT int 0 Expanding INLINE_CANDIDATE in statement STMT00047 in BB28: STMT00047 (IL 0x171...0x18A) [000208] I-C-G------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft (exactContextHnd=0x00000000D1FFAB1E) [000206] ------------ arg0 +--* ADDR byref [000205] -------N---- | \--* LCL_VAR struct V15 loc12 [000207] ------------ arg1 \--* LCL_VAR int V21 loc18 Argument #0: is a constant is byref to a struct local [000206] ------------ * ADDR byref [000205] -------N---- \--* LCL_VAR struct V15 loc12 Argument #1: is a local var [000207] ------------ * LCL_VAR int V21 loc18 INLINER: inlineInfo.tokenLookupContextHandle for Microsoft.CodeAnalysis.RealParser:ShiftLeft(byref,int) set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method Microsoft.CodeAnalysis.RealParser:ShiftLeft(byref,int) : IL to import: IL_0000 7e 9e 02 00 04 ldsfld 0x400029E IL_0005 03 ldarg.1 IL_0006 28 ca 03 00 0a call 0xA0003CA IL_000b 0a stloc.0 IL_000c 02 ldarg.0 IL_000d 02 ldarg.0 IL_000e 71 67 00 00 01 ldobj 0x1000067 IL_0013 06 ldloc.0 IL_0014 28 cb 03 00 0a call 0xA0003CB IL_0019 81 67 00 00 01 stobj 0x1000067 IL_001e 2a ret INLINER impTokenLookupContextHandle for Microsoft.CodeAnalysis.RealParser:ShiftLeft(byref,int) is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for Microsoft.CodeAnalysis.RealParser:ShiftLeft(byref,int) weight=159 : state 112 [ ldsfld ] weight= 16 : state 4 [ ldarg.1 ] weight= 79 : state 40 [ call ] weight= 6 : state 11 [ stloc.0 ] weight= 10 : state 3 [ ldarg.0 ] weight= 10 : state 3 [ ldarg.0 ] weight= 29 : state 101 [ ldobj ] weight= 12 : state 7 [ ldloc.0 ] weight= 79 : state 40 [ call ] weight= 36 : state 115 [ stobj ] weight= 19 : state 42 [ ret ] Inline candidate callsite is boring. Multiplier increased to 1.3. calleeNativeSizeEstimate=455 callsiteNativeSizeEstimate=115 benefit multiplier=1.3 threshold=149 Native estimate for function size exceeds threshold for inlining 45.5 > 14.9 (multiplier = 1.3) Inline expansion aborted, inline not profitable INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' for 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' calling 'Microsoft.CodeAnalysis.RealParser:ShiftLeft(byref,int)' INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' Expanding INLINE_CANDIDATE in statement STMT00049 in BB28: STMT00049 (IL ???... ???) [000218] I-C-G------- * CALL long System.Numerics.BigInteger.op_Explicit (exactContextHnd=0x00000000D1FFAB1E) [000223] n----------- arg0 \--* OBJ struct [000222] ------------ \--* ADDR byref [000221] -------N---- \--* LCL_VAR struct V35 tmp5 Argument #0: [000223] n----------- * OBJ struct [000222] ------------ \--* ADDR byref [000221] -------N---- \--* LCL_VAR struct V35 tmp5 INLINER: inlineInfo.tokenLookupContextHandle for System.Numerics.BigInteger:op_Explicit(System.Numerics.BigInteger):long set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method System.Numerics.BigInteger:op_Explicit(System.Numerics.BigInteger):long : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 1e 00 00 04 ldfld 0x400001E IL_0006 2d 08 brtrue.s 8 (IL_0010) IL_0008 02 ldarg.0 IL_0009 7b 1d 00 00 04 ldfld 0x400001D IL_000e ba conv.ovf.u8 IL_000f 2a ret IL_0010 02 ldarg.0 IL_0011 7b 1e 00 00 04 ldfld 0x400001E IL_0016 8e ldlen IL_0017 69 conv.i4 IL_0018 0a stloc.0 IL_0019 06 ldloc.0 IL_001a 18 ldc.i4.2 IL_001b 30 09 bgt.s 9 (IL_0026) IL_001d 02 ldarg.0 IL_001e 7b 1d 00 00 04 ldfld 0x400001D IL_0023 16 ldc.i4.0 IL_0024 2f 0b bge.s 11 (IL_0031) IL_0026 28 17 00 00 06 call 0x6000017 IL_002b 73 4d 00 00 0a newobj 0xA00004D IL_0030 7a throw IL_0031 06 ldloc.0 IL_0032 17 ldc.i4.1 IL_0033 31 16 ble.s 22 (IL_004b) IL_0035 02 ldarg.0 IL_0036 7b 1e 00 00 04 ldfld 0x400001E IL_003b 17 ldc.i4.1 IL_003c 95 ldelem.u4 IL_003d 02 ldarg.0 IL_003e 7b 1e 00 00 04 ldfld 0x400001E IL_0043 16 ldc.i4.0 IL_0044 95 ldelem.u4 IL_0045 28 2b 01 00 06 call 0x600012B IL_004a 2a ret IL_004b 02 ldarg.0 IL_004c 7b 1e 00 00 04 ldfld 0x400001E IL_0051 16 ldc.i4.0 IL_0052 95 ldelem.u4 IL_0053 6e conv.u8 IL_0054 2a ret INLINER impTokenLookupContextHandle for System.Numerics.BigInteger:op_Explicit(System.Numerics.BigInteger):long is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for System.Numerics.BigInteger:op_Explicit(System.Numerics.BigInteger):long weight= 31 : state 191 [ ldarg.0 -> ldfld ] weight= 25 : state 45 [ brtrue.s ] weight= 31 : state 191 [ ldarg.0 -> ldfld ] weight=293 : state 150 [ conv.ovf.u8 ] weight= 19 : state 42 [ ret ] weight= 31 : state 191 [ ldarg.0 -> ldfld ] weight= 7 : state 119 [ ldlen ] weight= 2 : state 93 [ conv.i4 ] weight= 20 : state 199 [ stloc.0 -> ldloc.0 ] weight= 34 : state 25 [ ldc.i4.2 ] weight= 33 : state 48 [ bgt.s ] weight= 31 : state 191 [ ldarg.0 -> ldfld ] weight= 15 : state 23 [ ldc.i4.0 ] weight= 20 : state 47 [ bge.s ] weight= 79 : state 40 [ call ] weight=227 : state 103 [ newobj ] weight=210 : state 108 [ throw ] weight= 12 : state 7 [ ldloc.0 ] weight= 28 : state 24 [ ldc.i4.1 ] weight= 53 : state 49 [ ble.s ] weight= 31 : state 191 [ ldarg.0 -> ldfld ] weight= 28 : state 24 [ ldc.i4.1 ] weight=213 : state 126 [ ldelem.u4 ] weight= 31 : state 191 [ ldarg.0 -> ldfld ] weight= 15 : state 23 [ ldc.i4.0 ] weight=213 : state 126 [ ldelem.u4 ] weight= 79 : state 40 [ call ] weight= 19 : state 42 [ ret ] weight= 31 : state 191 [ ldarg.0 -> ldfld ] weight= 15 : state 23 [ ldc.i4.0 ] weight=213 : state 126 [ ldelem.u4 ] weight= 55 : state 98 [ conv.u8 ] weight= 19 : state 42 [ ret ] multiplier in methods of promotable struct increased to 3. Inline candidate looks like a wrapper method. Multiplier increased to 4. Inline candidate has an arg that feeds a constant test. Multiplier increased to 5. Inline candidate callsite is boring. Multiplier increased to 6.3. calleeNativeSizeEstimate=2163 callsiteNativeSizeEstimate=105 benefit multiplier=6.3 threshold=661 Native estimate for function size exceeds threshold for inlining 216.3 > 66.1 (multiplier = 6.3) Inline expansion aborted, inline not profitable Inlining [000218] failed, so bashing STMT00049 to NOP INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' for 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' calling 'System.Numerics.BigInteger:op_Explicit(System.Numerics.BigInteger):long' INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' Replacing the return expression placeholder [000224] with [000218] [000224] --C--------- * RET_EXPR long (inl return from call [000218]) Inserting the inline return expression [000218] --C-G------- * CALL long System.Numerics.BigInteger.op_Explicit [000223] n----------- arg0 \--* OBJ struct [000222] ------------ \--* ADDR byref [000221] -------N---- \--* LCL_VAR struct V35 tmp5 Expanding INLINE_CANDIDATE in statement STMT00051 in BB28: STMT00051 (IL 0x18C...0x193) [000229] I-C-G------- * CALL int System.Numerics.BigInteger.get_IsZero (exactContextHnd=0x00000000D1FFAB1E) [000228] ------------ this in rcx \--* ADDR byref [000227] -------N---- \--* LCL_VAR struct V23 loc20 thisArg: is a constant is byref to a struct local [000228] ------------ * ADDR byref [000227] -------N---- \--* LCL_VAR struct V23 loc20 INLINER: inlineInfo.tokenLookupContextHandle for System.Numerics.BigInteger:get_IsZero():bool:this set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method System.Numerics.BigInteger:get_IsZero():bool:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 1d 00 00 04 ldfld 0x400001D IL_0006 16 ldc.i4.0 IL_0007 fe 01 ceq IL_0009 2a ret INLINER impTokenLookupContextHandle for System.Numerics.BigInteger:get_IsZero():bool:this is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for System.Numerics.BigInteger:get_IsZero():bool:this Jump targets: none Computing inlinee profile scale: ... call site not profiled New Basic Block BB52 [0051] created. BB52 [000..00A) Basic block list for 'System.Numerics.BigInteger:get_IsZero():bool:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB52 [0051] 1 1 [000..00A) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000229] Starting PHASE Pre-import *************** Inline @[000229] Finishing PHASE Pre-import *************** Inline @[000229] Starting PHASE Importation *************** In impImport() for System.Numerics.BigInteger:get_IsZero():bool:this impImportBlockPending for BB52 Importing BB52 (PC=000) of 'System.Numerics.BigInteger:get_IsZero():bool:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 0400001D [ 1] 6 (0x006) ldc.i4.0 0 [ 2] 7 (0x007) ceq [ 1] 9 (0x009) ret Inlinee Return expression (before normalization) => [000516] ------------ * EQ int [000514] ------------ +--* FIELD int _sign [000512] ------------ | \--* ADDR byref [000513] -------N---- | \--* LCL_VAR struct V23 loc20 [000515] ------------ \--* CNS_INT int 0 Inlinee Return expression (after normalization) => [000516] ------------ * EQ int [000514] ------------ +--* FIELD int _sign [000512] ------------ | \--* ADDR byref [000513] -------N---- | \--* LCL_VAR struct V23 loc20 [000515] ------------ \--* CNS_INT int 0 ** Note: inlinee IL was partially imported -- imported 0 of 10 bytes of method IL *************** Inline @[000229] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB52 [0051] 1 1 [000..00A) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB52 [000..00A) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000229] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000229] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000229] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000229] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000229] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000229] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000229] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000229] is [000516] ------------ * EQ int [000514] ------------ +--* FIELD int _sign [000512] ------------ | \--* ADDR byref [000513] -------N---- | \--* LCL_VAR struct V23 loc20 [000515] ------------ \--* CNS_INT int 0 Successfully inlined System.Numerics.BigInteger:get_IsZero():bool:this (10 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' calling 'System.Numerics.BigInteger:get_IsZero():bool:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000230] with [000516] [000230] --C--------- * RET_EXPR int (inl return from call [000516]) Inserting the inline return expression [000516] ------------ * EQ int [000514] ------------ +--* FIELD int _sign [000512] ------------ | \--* ADDR byref [000513] -------N---- | \--* LCL_VAR struct V23 loc20 [000515] ------------ \--* CNS_INT int 0 Expanding INLINE_CANDIDATE in statement STMT00053 in BB28: STMT00053 (IL 0x195...0x19C) [000234] I-C-G------- * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits (exactContextHnd=0x00000000D1FFAB1E) [000233] ------------ arg0 \--* LCL_VAR long V24 loc21 Argument #0: is a local var [000233] ------------ * LCL_VAR long V24 loc21 INLINER: inlineInfo.tokenLookupContextHandle for Microsoft.CodeAnalysis.RealParser:CountSignificantBits(long):int set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method Microsoft.CodeAnalysis.RealParser:CountSignificantBits(long):int : IL to import: IL_0000 16 ldc.i4.0 IL_0001 0a stloc.0 IL_0002 2b 09 br.s 9 (IL_000d) IL_0004 02 ldarg.0 IL_0005 17 ldc.i4.1 IL_0006 64 shr.un IL_0007 10 00 starg.s 0x0 IL_0009 06 ldloc.0 IL_000a 17 ldc.i4.1 IL_000b 58 add IL_000c 0a stloc.0 IL_000d 02 ldarg.0 IL_000e 2d f4 brtrue.s -12 (IL_0004) IL_0010 06 ldloc.0 IL_0011 2a ret INLINER impTokenLookupContextHandle for Microsoft.CodeAnalysis.RealParser:CountSignificantBits(long):int is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for Microsoft.CodeAnalysis.RealParser:CountSignificantBits(long):int weight= 15 : state 23 [ ldc.i4.0 ] weight= 6 : state 11 [ stloc.0 ] weight= 44 : state 43 [ br.s ] weight= 10 : state 3 [ ldarg.0 ] weight= 28 : state 24 [ ldc.i4.1 ] weight= 27 : state 88 [ shr.un ] weight= 21 : state 17 [ starg.s ] weight= 12 : state 7 [ ldloc.0 ] weight= 28 : state 24 [ ldc.i4.1 ] weight=-12 : state 76 [ add ] weight= 6 : state 11 [ stloc.0 ] weight= 10 : state 3 [ ldarg.0 ] weight= 25 : state 45 [ brtrue.s ] weight= 12 : state 7 [ ldloc.0 ] weight= 19 : state 42 [ ret ] Inline candidate has an arg that feeds a constant test. Multiplier increased to 1. Inline candidate callsite is boring. Multiplier increased to 2.3. calleeNativeSizeEstimate=251 callsiteNativeSizeEstimate=85 benefit multiplier=2.3 threshold=195 Native estimate for function size exceeds threshold for inlining 25.1 > 19.5 (multiplier = 2.3) Inline expansion aborted, inline not profitable Inlining [000234] failed, so bashing STMT00053 to NOP INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' for 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' calling 'Microsoft.CodeAnalysis.RealParser:CountSignificantBits(long):int' INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' Replacing the return expression placeholder [000235] with [000234] [000235] --C--------- * RET_EXPR int (inl return from call [000234]) Inserting the inline return expression [000234] --C-G------- * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits [000233] ------------ arg0 \--* LCL_VAR long V24 loc21 Expanding INLINE_CANDIDATE in statement STMT00056 in BB33: STMT00056 (IL 0x1D0...0x1E0) [000243] I-C-G------- * CALL long System.Numerics.BigInteger.op_Explicit (exactContextHnd=0x00000000D1FFAB1E) [000245] n----------- arg0 \--* OBJ struct [000244] ------------ \--* ADDR byref [000242] -------N---- \--* LCL_VAR struct V11 loc8 Argument #0: has caller local ref [000245] n----------- * OBJ struct [000244] ------------ \--* ADDR byref [000242] -------N---- \--* LCL_VAR struct V11 loc8 INLINER: inlineInfo.tokenLookupContextHandle for System.Numerics.BigInteger:op_Explicit(System.Numerics.BigInteger):long set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method System.Numerics.BigInteger:op_Explicit(System.Numerics.BigInteger):long : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 1e 00 00 04 ldfld 0x400001E IL_0006 2d 08 brtrue.s 8 (IL_0010) IL_0008 02 ldarg.0 IL_0009 7b 1d 00 00 04 ldfld 0x400001D IL_000e ba conv.ovf.u8 IL_000f 2a ret IL_0010 02 ldarg.0 IL_0011 7b 1e 00 00 04 ldfld 0x400001E IL_0016 8e ldlen IL_0017 69 conv.i4 IL_0018 0a stloc.0 IL_0019 06 ldloc.0 IL_001a 18 ldc.i4.2 IL_001b 30 09 bgt.s 9 (IL_0026) IL_001d 02 ldarg.0 IL_001e 7b 1d 00 00 04 ldfld 0x400001D IL_0023 16 ldc.i4.0 IL_0024 2f 0b bge.s 11 (IL_0031) IL_0026 28 17 00 00 06 call 0x6000017 IL_002b 73 4d 00 00 0a newobj 0xA00004D IL_0030 7a throw IL_0031 06 ldloc.0 IL_0032 17 ldc.i4.1 IL_0033 31 16 ble.s 22 (IL_004b) IL_0035 02 ldarg.0 IL_0036 7b 1e 00 00 04 ldfld 0x400001E IL_003b 17 ldc.i4.1 IL_003c 95 ldelem.u4 IL_003d 02 ldarg.0 IL_003e 7b 1e 00 00 04 ldfld 0x400001E IL_0043 16 ldc.i4.0 IL_0044 95 ldelem.u4 IL_0045 28 2b 01 00 06 call 0x600012B IL_004a 2a ret IL_004b 02 ldarg.0 IL_004c 7b 1e 00 00 04 ldfld 0x400001E IL_0051 16 ldc.i4.0 IL_0052 95 ldelem.u4 IL_0053 6e conv.u8 IL_0054 2a ret INLINER impTokenLookupContextHandle for System.Numerics.BigInteger:op_Explicit(System.Numerics.BigInteger):long is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for System.Numerics.BigInteger:op_Explicit(System.Numerics.BigInteger):long weight= 31 : state 191 [ ldarg.0 -> ldfld ] weight= 25 : state 45 [ brtrue.s ] weight= 31 : state 191 [ ldarg.0 -> ldfld ] weight=293 : state 150 [ conv.ovf.u8 ] weight= 19 : state 42 [ ret ] weight= 31 : state 191 [ ldarg.0 -> ldfld ] weight= 7 : state 119 [ ldlen ] weight= 2 : state 93 [ conv.i4 ] weight= 20 : state 199 [ stloc.0 -> ldloc.0 ] weight= 34 : state 25 [ ldc.i4.2 ] weight= 33 : state 48 [ bgt.s ] weight= 31 : state 191 [ ldarg.0 -> ldfld ] weight= 15 : state 23 [ ldc.i4.0 ] weight= 20 : state 47 [ bge.s ] weight= 79 : state 40 [ call ] weight=227 : state 103 [ newobj ] weight=210 : state 108 [ throw ] weight= 12 : state 7 [ ldloc.0 ] weight= 28 : state 24 [ ldc.i4.1 ] weight= 53 : state 49 [ ble.s ] weight= 31 : state 191 [ ldarg.0 -> ldfld ] weight= 28 : state 24 [ ldc.i4.1 ] weight=213 : state 126 [ ldelem.u4 ] weight= 31 : state 191 [ ldarg.0 -> ldfld ] weight= 15 : state 23 [ ldc.i4.0 ] weight=213 : state 126 [ ldelem.u4 ] weight= 79 : state 40 [ call ] weight= 19 : state 42 [ ret ] weight= 31 : state 191 [ ldarg.0 -> ldfld ] weight= 15 : state 23 [ ldc.i4.0 ] weight=213 : state 126 [ ldelem.u4 ] weight= 55 : state 98 [ conv.u8 ] weight= 19 : state 42 [ ret ] multiplier in methods of promotable struct increased to 3. Inline candidate looks like a wrapper method. Multiplier increased to 4. Inline candidate has an arg that feeds a constant test. Multiplier increased to 5. Inline candidate callsite is boring. Multiplier increased to 6.3. calleeNativeSizeEstimate=2163 callsiteNativeSizeEstimate=105 benefit multiplier=6.3 threshold=661 Native estimate for function size exceeds threshold for inlining 216.3 > 66.1 (multiplier = 6.3) Inline expansion aborted, inline not profitable Inlining [000243] failed, so bashing STMT00056 to NOP INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' for 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' calling 'System.Numerics.BigInteger:op_Explicit(System.Numerics.BigInteger):long' INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' Replacing the return expression placeholder [000246] with [000243] [000246] --C--------- * RET_EXPR long (inl return from call [000243]) Inserting the inline return expression [000243] --C-G------- * CALL long System.Numerics.BigInteger.op_Explicit [000245] n----------- arg0 \--* OBJ struct [000244] ------------ \--* ADDR byref [000242] -------N---- \--* LCL_VAR struct V11 loc8 **************** Inline Tree Inlines into 060006E9 Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int [0 IL=0015 TR=000401 06002063] [FAILED: target not direct] FloatingPointType:get_Zero():long:this [1 IL=0024 TR=000008 0600205B] [below ALWAYS_INLINE size] FloatingPointType:get_NormalMantissaBits():ushort:this [2 IL=0039 TR=000018 06000418] [below ALWAYS_INLINE size] System.Math:Max(int,int):int [3 IL=0047 TR=000026 06002077] [below ALWAYS_INLINE size] DecimalFloatingPointString:get_MantissaCount():int:this [4 IL=0052 TR=000028 06000429] [below ALWAYS_INLINE size] System.Math:Min(int,int):int [5 IL=0072 TR=000047 06002077] [below ALWAYS_INLINE size] DecimalFloatingPointString:get_MantissaCount():int:this [0 IL=0090 TR=000059 060006EB] [FAILED: unprofitable inline] Microsoft.CodeAnalysis.RealParser:AccumulateDecimalDigitsIntoBigInteger(DecimalFloatingPointString,int,int):System.Numerics.BigInteger [0 IL=0104 TR=000383 0600205F] [FAILED: unprofitable inline] FloatingPointType:get_OverflowDecimalExponent():int:this [0 IL=0114 TR=000394 06002064] [FAILED: target not direct] FloatingPointType:get_Infinity():long:this [0 IL=0125 TR=000391 060006F3] [FAILED: unprofitable inline] Microsoft.CodeAnalysis.RealParser:MultiplyByPowerOfTen(byref,int) [0 IL=0134 TR=000072 060006EE] [FAILED: unprofitable inline] Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger,byref):int [0 IL=0161 TR=000089 060006EA] [FAILED: too many il bytes] Microsoft.CodeAnalysis.RealParser:ConvertBigIntegerToFloatingPointBits(System.Byte[],int,bool,FloatingPointType,byref):int [6 IL=0201 TR=000356 06002077] [below ALWAYS_INLINE size] DecimalFloatingPointString:get_MantissaCount():int:this [0 IL=0209 TR=000361 0600205F] [FAILED: unprofitable inline] FloatingPointType:get_OverflowDecimalExponent():int:this [0 IL=0219 TR=000371 06002063] [FAILED: target not direct] FloatingPointType:get_Zero():long:this [0 IL=0232 TR=000120 060006EB] [FAILED: unprofitable inline] Microsoft.CodeAnalysis.RealParser:AccumulateDecimalDigitsIntoBigInteger(DecimalFloatingPointString,int,int):System.Numerics.BigInteger [0 IL=0250 TR=000141 060006F3] [FAILED: unprofitable inline] Microsoft.CodeAnalysis.RealParser:MultiplyByPowerOfTen(byref,int) [7 IL=0257 TR=000143 060006EF] [below ALWAYS_INLINE size] Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger):int [0 IL=0003 TR=000463 060006EE] [FAILED: unprofitable inline] Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger,byref):int [8 IL=0266 TR=000150 060006EF] [below ALWAYS_INLINE size] Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger):int [0 IL=0003 TR=000481 060006EE] [FAILED: unprofitable inline] Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger,byref):int [0 IL=0298 TR=000347 060006F2] [FAILED: unprofitable inline] Microsoft.CodeAnalysis.RealParser:ShiftLeft(byref,int) [0 IL=0335 TR=000342 060006EA] [FAILED: noinline per IL/cached result] Microsoft.CodeAnalysis.RealParser:ConvertBigIntegerToFloatingPointBits(System.Byte[],int,bool,FloatingPointType,byref):int [9 IL=0352 TR=000187 060000F9] [below ALWAYS_INLINE size] System.Numerics.BigInteger:op_LessThan(System.Numerics.BigInteger,System.Numerics.BigInteger):bool [0 IL=0373 TR=000208 060006F2] [FAILED: unprofitable inline] Microsoft.CodeAnalysis.RealParser:ShiftLeft(byref,int) [0 IL=0384 TR=000213 060000B2] [FAILED: too many il bytes] System.Numerics.BigInteger:DivRem(System.Numerics.BigInteger,System.Numerics.BigInteger,byref):System.Numerics.BigInteger [0 IL=0389 TR=000218 060000E7] [FAILED: unprofitable inline] System.Numerics.BigInteger:op_Explicit(System.Numerics.BigInteger):long [10 IL=0398 TR=000229 0600009E] [below ALWAYS_INLINE size] System.Numerics.BigInteger:get_IsZero():bool:this [0 IL=0407 TR=000234 060006EC] [FAILED: unprofitable inline] Microsoft.CodeAnalysis.RealParser:CountSignificantBits(long):int [0 IL=0466 TR=000243 060000E7] [FAILED: unprofitable inline] System.Numerics.BigInteger:op_Explicit(System.Numerics.BigInteger):long [0 IL=0508 TR=000273 06002065] [FAILED: too many il bytes] FloatingPointType:AssembleFloatingPointValue(long,int,bool,byref):int:this Budget: initialTime=1602, finalTime=1530, initialBudget=16020, currentBudget=16020 Budget: initialSize=11850, finalSize=11850 *************** Finishing PHASE Morph - Inlining Trees after Morph - Inlining ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..00D)-> BB03 ( cond ) i idxlen BB02 [0001] 1 1 [00D..017) (return) i BB03 [0002] 1 1 [017..065) i BB38 [0037] 1 1 [020..021)-> BB40 ( cond ) i BB39 [0038] 1 1 [020..021)-> BB41 (always) i BB40 [0039] 1 1 [020..021) i BB41 [0040] 1 1 [???..???) i internal idxlen BB43 [0042] 1 1 [000..000)-> BB45 ( cond ) i internal BB44 [0043] 1 1 [000..000)-> BB46 (always) i internal BB45 [0044] 1 1 [000..000) i internal BB46 [0045] 1 1 [???..???)-> BB07 ( cond ) i internal idxlen BB04 [0003] 1 1 [065..070)-> BB06 ( cond ) i BB05 [0004] 1 1 [070..07A) (return) i BB06 [0005] 1 1 [07A..082) i BB07 [0006] 2 1 [082..092)-> BB09 ( cond ) i BB08 [0007] 1 1 [092..096)-> BB10 ( cond ) i BB09 [0008] 2 1 [096..0A7) (return) i BB10 [0009] 1 1 [0A7..0B0)-> BB12 ( cond ) i BB11 [0010] 1 1 [0B0..0B4)-> BB13 (always) i BB12 [0011] 1 1 [0B4..0BE) i BB13 [0012] 2 1 [0BE..0C4)-> BB16 ( cond ) i BB14 [0013] 1 1 [0C4..0D9)-> BB16 ( cond ) i idxlen BB15 [0014] 1 1 [0D9..0E3) (return) i BB16 [0015] 2 1 [0E3..117)-> BB18 ( cond ) i BB17 [0016] 1 1 [117..11A)-> BB19 (always) i BB18 [0017] 1 1 [11A..11F) i BB19 [0018] 2 1 [11F..126)-> BB21 ( cond ) i BB20 [0019] 1 1 [126..12F) i BB21 [0020] 2 1 [12F..13E)-> BB25 ( cond ) i BB22 [0021] 1 1 [13E..144)-> BB24 ( cond ) i BB23 [0022] 1 1 [144..155) (return) i BB24 [0023] 1 1 [155..15C) i BB25 [0024] 2 1 [15C..167)-> BB27 ( cond ) i BB26 [0025] 1 1 [167..16B)-> BB28 (always) i BB27 [0026] 1 1 [16B..16F) i BB28 [0027] 2 1 [16F..1A4)-> BB33 ( cond ) i BB29 [0028] 1 1 [1A4..1AF)-> BB31 ( cond ) i BB30 [0029] 1 1 [1AF..1C3)-> BB32 (always) i BB31 [0030] 1 1 [1C3..1C4) i BB32 [0031] 2 1 [1C4..1D0) i BB33 [0032] 2 1 [1D0..1E7)-> BB35 ( cond ) i BB34 [0033] 1 1 [1E7..1EE)-> BB36 (always) i BB35 [0034] 1 1 [1EE..1F2) i BB36 [0035] 2 1 [1F2..202) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..00D) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB01 STMT00000 (IL 0x000...0x00B) [000006] ---XG------- * JTRUE void [000005] ---XG------- \--* NE int [000003] ---XG------- +--* ARR_LENGTH int [000002] ----G------- | \--* FIELD ref Mantissa [000001] ------------ | \--* ADDR byref [000000] -------N---- | \--* LCL_VAR struct V00 arg0 [000004] ------------ \--* CNS_INT int 0 ------------ BB02 [00D..017) (return), preds={} succs={} ***** BB02 STMT00087 (IL 0x00D...0x014) [000403] -ACXG------- * ASG long [000402] *------N---- +--* IND long [000399] ------------ | \--* LCL_VAR byref V02 arg2 [000401] --C-G------- \--* CALLV ind long FloatingPointType.get_Zero [000400] ------------ this in rcx \--* LCL_VAR ref V01 arg1 ***** BB02 STMT00088 (IL 0x015...0x016) [000405] ------------ * RETURN int [000404] ------------ \--* CNS_INT int 1 ------------ BB03 [017..065), preds={} succs={BB38} ***** BB03 STMT00002 (IL ???... ???) [000013] -AC--------- * ASG int [000012] D------N---- +--* LCL_VAR int V03 loc0 [000011] --C--------- \--* ADD int [000409] --C-G------- +--* CAST int <- ushort <- int [000408] --C-G------- | \--* ADD int [000406] --C-G------- | +--* CALLV ind int FloatingPointType.get_DenormalMantissaBits [000007] ------------ this in rcx | | \--* LCL_VAR ref V01 arg1 [000407] ------------ | \--* CNS_INT int 1 [000010] ------------ \--* CNS_INT int 1 ***** BB03 STMT00092 (IL 0x020... ???) [000424] -A--G------- * ASG int [000423] D------N---- +--* LCL_VAR int V40 tmp10 [000017] ----G------- \--* FIELD int Exponent [000016] ------------ \--* ADDR byref [000015] -------N---- \--* LCL_VAR struct V00 arg0 ------------ BB38 [020..021) -> BB40 (cond), preds={} succs={BB39,BB40} ***** BB38 STMT00089 (IL 0x020... ???) [000414] ------------ * JTRUE void [000413] ------------ \--* GE int [000411] ------------ +--* CNS_INT int 0 [000412] ------------ \--* LCL_VAR int V40 tmp10 ------------ BB39 [020..021) -> BB41 (always), preds={} succs={BB41} ***** BB39 STMT00091 (IL 0x020... ???) [000421] -A---------- * ASG int [000420] D------N---- +--* LCL_VAR int V39 tmp9 [000419] ------------ \--* LCL_VAR int V40 tmp10 ------------ BB40 [020..021), preds={} succs={BB41} ***** BB40 STMT00090 (IL 0x020... ???) [000417] -A---------- * ASG int [000416] D------N---- +--* LCL_VAR int V39 tmp9 [000415] ------------ \--* CNS_INT int 0 ------------ BB41 [???..???), preds={} succs={BB43} ***** BB41 STMT00004 (IL ???... ???) [000021] -AC--------- * ASG int [000020] D------N---- +--* LCL_VAR int V31 tmp1 [000422] ------------ \--* LCL_VAR int V39 tmp9 ***** BB41 STMT00096 (IL ???... ???) [000443] -A-XG------- * ASG int [000442] D------N---- +--* LCL_VAR int V42 tmp12 [000429] ---XG------- \--* ARR_LENGTH int [000428] ----G------- \--* FIELD ref Mantissa [000426] ------------ \--* ADDR byref [000427] -------N---- \--* LCL_VAR struct V00 arg0 ------------ BB43 [000..000) -> BB45 (cond), preds={} succs={BB44,BB45} ***** BB43 STMT00093 (IL ???... ???) [000433] ------------ * JTRUE void [000432] N--------U-- \--* LE int [000023] ------------ +--* LCL_VAR int V31 tmp1 [000431] ------------ \--* LCL_VAR int V42 tmp12 ------------ BB44 [000..000) -> BB46 (always), preds={} succs={BB46} ***** BB44 STMT00095 (IL ???... ???) [000440] -A---------- * ASG int [000439] D------N---- +--* LCL_VAR int V41 tmp11 [000438] ------------ \--* LCL_VAR int V42 tmp12 ------------ BB45 [000..000), preds={} succs={BB46} ***** BB45 STMT00094 (IL ???... ???) [000436] -A---------- * ASG int [000435] D------N---- +--* LCL_VAR int V41 tmp11 [000434] ------------ \--* LCL_VAR int V31 tmp1 ------------ BB46 [???..???) -> BB07 (cond), preds={} succs={BB04,BB07} ***** BB46 STMT00007 (IL ???... ???) [000031] -AC--------- * ASG int [000030] D------N---- +--* LCL_VAR int V04 loc1 [000441] ------------ \--* LCL_VAR int V41 tmp11 ***** BB46 STMT00008 (IL ???...0x03C) [000035] -A---------- * ASG int [000034] D------N---- +--* LCL_VAR int V05 loc2 [000033] ------------ \--* SUB int [000022] ------------ +--* LCL_VAR int V31 tmp1 [000032] ------------ \--* LCL_VAR int V04 loc1 ***** BB46 STMT00009 (IL 0x03D...0x03E) [000038] -A---------- * ASG int [000037] D------N---- +--* LCL_VAR int V06 loc3 [000036] ------------ \--* CNS_INT int 0 ***** BB46 STMT00010 (IL 0x03F...0x040) [000041] -A---------- * ASG int [000040] D------N---- +--* LCL_VAR int V07 loc4 [000039] ------------ \--* LCL_VAR int V04 loc1 ***** BB46 STMT00011 (IL 0x042...0x044) [000044] -A---------- * ASG int [000043] D------N---- +--* LCL_VAR int V08 loc5 [000042] ------------ \--* LCL_VAR int V07 loc4 ***** BB46 STMT00013 (IL ???... ???) [000050] -AC--------- * ASG int [000049] D------N---- +--* LCL_VAR int V09 loc6 [000448] ---XG------- \--* ARR_LENGTH int [000447] ----G------- \--* FIELD ref Mantissa [000445] ------------ \--* ADDR byref [000446] -------N---- \--* LCL_VAR struct V00 arg0 ***** BB46 STMT00014 (IL 0x04F...0x054) [000055] -A---------- * ASG int [000054] D------N---- +--* LCL_VAR int V10 loc7 [000053] ------------ \--* SUB int [000051] ------------ +--* LCL_VAR int V09 loc6 [000052] ------------ \--* LCL_VAR int V08 loc5 ***** BB46 STMT00016 (IL ???... ???) [000059] S-C-G------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger [000064] ------------ arg0 +--* ADDR byref [000063] -------N---- | \--* LCL_VAR struct V11 loc8 [000061] n----------- arg1 +--* OBJ struct [000060] ------------ | \--* ADDR byref [000056] -------N---- | \--* LCL_VAR struct V00 arg0 [000057] ------------ arg2 +--* LCL_VAR int V06 loc3 [000058] ------------ arg3 \--* LCL_VAR int V07 loc4 ***** BB46 STMT00017 (IL 0x061...0x063) [000068] ------------ * JTRUE void [000067] N--------U-- \--* LE int [000065] ------------ +--* LCL_VAR int V05 loc2 [000066] ------------ \--* CNS_INT int 0 ------------ BB04 [065..070) -> BB06 (cond), preds={} succs={BB05,BB06} ***** BB04 STMT00083 (IL ???... ???) [000387] --C--------- * JTRUE void [000386] --C--------- \--* LE int [000381] ---------U-- +--* CAST long <- ulong <- uint [000380] ------------ | \--* LCL_VAR int V05 loc2 [000385] --C--------- \--* CAST long <- int [000383] --C-G------- \--* CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent [000382] ------------ this in rcx \--* LCL_VAR ref V01 arg1 ------------ BB05 [070..07A) (return), preds={} succs={} ***** BB05 STMT00085 (IL 0x070...0x077) [000396] -ACXG------- * ASG long [000395] *------N---- +--* IND long [000392] ------------ | \--* LCL_VAR byref V02 arg2 [000394] --C-G------- \--* CALLV ind long FloatingPointType.get_Infinity [000393] ------------ this in rcx \--* LCL_VAR ref V01 arg1 ***** BB05 STMT00086 (IL 0x078...0x079) [000398] ------------ * RETURN int [000397] ------------ \--* CNS_INT int 3 ------------ BB06 [07A..082), preds={} succs={BB07} ***** BB06 STMT00084 (IL 0x07A...0x07D) [000391] --C-G------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen [000389] ------------ arg0 +--* ADDR byref [000388] -------N---- | \--* LCL_VAR struct V11 loc8 [000390] ------------ arg1 \--* LCL_VAR int V05 loc2 ------------ BB07 [082..092) -> BB09 (cond), preds={} succs={BB08,BB09} ***** BB07 STMT00019 (IL ???... ???) [000077] -AC--------- * ASG int [000076] D------N---- +--* LCL_VAR int V13 loc10 [000072] --C-G------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits [000074] n----------- arg0 +--* OBJ struct [000073] ------------ | \--* ADDR byref [000069] -------N---- | \--* LCL_VAR struct V11 loc8 [000071] ------------ arg1 \--* ADDR byref [000070] -------N---- \--* LCL_VAR ref V12 loc9 ***** BB07 STMT00020 (IL 0x08D...0x090) [000081] ------------ * JTRUE void [000080] N--------U-- \--* GE int [000078] ------------ +--* LCL_VAR int V13 loc10 [000079] ------------ \--* LCL_VAR int V03 loc0 ------------ BB08 [092..096) -> BB10 (cond), preds={} succs={BB09,BB10} ***** BB08 STMT00022 (IL 0x092...0x094) [000094] ------------ * JTRUE void [000093] ------------ \--* NE int [000091] ------------ +--* LCL_VAR int V10 loc7 [000092] ------------ \--* CNS_INT int 0 ------------ BB09 [096..0A7) (return), preds={} succs={} ***** BB09 STMT00021 (IL 0x096...0x0A6) [000090] --C-G------- * RETURN int [000089] --C-G------- \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits [000082] ------------ arg0 +--* LCL_VAR ref V12 loc9 [000083] ------------ arg1 +--* LCL_VAR int V13 loc10 [000086] N--------U-- arg2 +--* GT int [000084] ------------ | +--* LCL_VAR int V10 loc7 [000085] ------------ | \--* CNS_INT int 0 [000087] ------------ arg3 +--* LCL_VAR ref V01 arg1 [000088] ------------ arg4 \--* LCL_VAR byref V02 arg2 ------------ BB10 [0A7..0B0) -> BB12 (cond), preds={} succs={BB11,BB12} ***** BB10 STMT00023 (IL 0x0A7...0x0AE) [000100] ----G------- * JTRUE void [000099] ----G------- \--* LT int [000097] ----G------- +--* FIELD int Exponent [000096] ------------ | \--* ADDR byref [000095] -------N---- | \--* LCL_VAR struct V00 arg0 [000098] ------------ \--* CNS_INT int 0 ------------ BB11 [0B0..0B4) -> BB13 (always), preds={} succs={BB13} ***** BB11 STMT00081 (IL 0x0B0...0x0B2) [000378] -A---------- * ASG int [000377] D------N---- +--* LCL_VAR int V32 tmp2 [000376] ------------ \--* LCL_VAR int V10 loc7 ------------ BB12 [0B4..0BE), preds={} succs={BB13} ***** BB12 STMT00024 (IL 0x0B4...0x0BD) [000108] -A--G------- * ASG int [000107] D------N---- +--* LCL_VAR int V32 tmp2 [000106] ----G------- \--* ADD int [000101] ------------ +--* LCL_VAR int V10 loc7 [000105] ----G------- \--* NEG int [000104] ----G------- \--* FIELD int Exponent [000103] ------------ \--* ADDR byref [000102] -------N---- \--* LCL_VAR struct V00 arg0 ------------ BB13 [0BE..0C4) -> BB16 (cond), preds={} succs={BB14,BB16} ***** BB13 STMT00025 (IL ???...0x0BE) [000112] -A---------- * ASG int [000111] D------N---- +--* LCL_VAR int V14 loc11 [000110] ------------ \--* LCL_VAR int V32 tmp2 ***** BB13 STMT00026 (IL 0x0C0...0x0C2) [000116] ------------ * JTRUE void [000115] ------------ \--* NE int [000113] ------------ +--* LCL_VAR int V13 loc10 [000114] ------------ \--* CNS_INT int 0 ------------ BB14 [0C4..0D9) -> BB16 (cond), preds={} succs={BB15,BB16} ***** BB14 STMT00077 (IL ???... ???) [000363] -AC--------- * ASG long [000362] D------N---- +--* LCL_VAR long V38 tmp8 [000359] --C--------- \--* SUB long [000353] ---------U-- +--* CAST long <- ulong <- uint [000352] ------------ | \--* LCL_VAR int V14 loc11 [000358] --C--------- \--* CAST long <- int [000456] ---XG------- \--* ARR_LENGTH int [000455] ----G------- \--* FIELD ref Mantissa [000453] ------------ \--* ADDR byref [000454] -------N---- \--* LCL_VAR struct V00 arg0 ***** BB14 STMT00078 (IL ???... ???) [000368] --C--------- * JTRUE void [000367] --C--------- \--* LE int [000364] ------------ +--* LCL_VAR long V38 tmp8 [000366] --C--------- \--* CAST long <- int [000361] --C-G------- \--* CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent [000360] ------------ this in rcx \--* LCL_VAR ref V01 arg1 ------------ BB15 [0D9..0E3) (return), preds={} succs={} ***** BB15 STMT00079 (IL 0x0D9...0x0E0) [000373] -ACXG------- * ASG long [000372] *------N---- +--* IND long [000369] ------------ | \--* LCL_VAR byref V02 arg2 [000371] --C-G------- \--* CALLV ind long FloatingPointType.get_Zero [000370] ------------ this in rcx \--* LCL_VAR ref V01 arg1 ***** BB15 STMT00080 (IL 0x0E1...0x0E2) [000375] ------------ * RETURN int [000374] ------------ \--* CNS_INT int 2 ------------ BB16 [0E3..117) -> BB18 (cond), preds={} succs={BB17,BB18} ***** BB16 STMT00028 (IL ???... ???) [000120] S-C-G------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger [000125] ------------ arg0 +--* ADDR byref [000124] -------N---- | \--* LCL_VAR struct V15 loc12 [000122] n----------- arg1 +--* OBJ struct [000121] ------------ | \--* ADDR byref [000117] -------N---- | \--* LCL_VAR struct V00 arg0 [000118] ------------ arg2 +--* LCL_VAR int V08 loc5 [000119] ------------ arg3 \--* LCL_VAR int V09 loc6 ***** BB16 STMT00029 (IL 0x0EF...0x0F4) [000133] H-CXG------- * CALL help long HELPER.CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE [000131] ------------ arg0 +--* CNS_INT long 0x7ff815262aa0 [000132] ------------ arg1 \--* CNS_INT int 173 ***** BB16 STMT00030 (IL ???... ???) [000137] -A--G------- * ASG struct (copy) [000135] D------N---- +--* LCL_VAR struct V16 loc13 [000129] ----G------- \--* OBJ struct [000128] ----G------- \--* ADD byref [000126] ----G------- +--* FIELD ref BigOne [000127] ------------ \--* CNS_INT long 8 Fseq[#FirstElem] ***** BB16 STMT00031 (IL 0x0F6...0x106) [000141] --C-G------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen [000139] ------------ arg0 +--* ADDR byref [000138] -------N---- | \--* LCL_VAR struct V16 loc13 [000140] ------------ arg1 \--* LCL_VAR int V14 loc11 ***** BB16 STMT00099 (IL 0x0FF... ???) [000472] -A---------- * ASG struct (copy) [000470] D------N---- +--* LCL_VAR struct V44 tmp14 [000145] n----------- \--* OBJ struct [000144] ------------ \--* ADDR byref [000142] -------N---- \--* LCL_VAR struct V15 loc12 ***** BB16 STMT00098 (IL 0x0FF... ???) [000468] -AC--------- * ASG int [000467] D------N---- +--* LCL_VAR int V43 tmp13 [000463] --C-G------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits [000465] n----------- arg0 +--* OBJ struct [000464] ------------ | \--* ADDR byref [000460] -------N---- | \--* LCL_VAR struct V44 tmp14 [000462] ------------ arg1 \--* ADDR byref [000461] -------N---- \--* LCL_VAR ref V45 tmp15 ***** BB16 STMT00100 (IL 0x0FF... ???) [000475] -A---------- * ASG ref [000474] D------N---- +--* LCL_VAR ref V45 tmp15 [000473] ------------ \--* CNS_INT ref null ***** BB16 STMT00033 (IL ???... ???) [000148] -AC--------- * ASG int [000147] D------N---- +--* LCL_VAR int V17 loc14 [000469] ------------ \--* LCL_VAR int V43 tmp13 ***** BB16 STMT00103 (IL 0x108... ???) [000490] -A---------- * ASG struct (copy) [000488] D------N---- +--* LCL_VAR struct V47 tmp17 [000152] n----------- \--* OBJ struct [000151] ------------ \--* ADDR byref [000149] -------N---- \--* LCL_VAR struct V16 loc13 ***** BB16 STMT00102 (IL 0x108... ???) [000486] -AC--------- * ASG int [000485] D------N---- +--* LCL_VAR int V46 tmp16 [000481] --C-G------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits [000483] n----------- arg0 +--* OBJ struct [000482] ------------ | \--* ADDR byref [000478] -------N---- | \--* LCL_VAR struct V47 tmp17 [000480] ------------ arg1 \--* ADDR byref [000479] -------N---- \--* LCL_VAR ref V48 tmp18 ***** BB16 STMT00104 (IL 0x108... ???) [000493] -A---------- * ASG ref [000492] D------N---- +--* LCL_VAR ref V48 tmp18 [000491] ------------ \--* CNS_INT ref null ***** BB16 STMT00035 (IL ???... ???) [000155] -AC--------- * ASG int [000154] D------N---- +--* LCL_VAR int V18 loc15 [000487] ------------ \--* LCL_VAR int V46 tmp16 ***** BB16 STMT00036 (IL 0x111...0x115) [000159] ------------ * JTRUE void [000158] N--------U-- \--* GT int [000156] ------------ +--* LCL_VAR int V18 loc15 [000157] ------------ \--* LCL_VAR int V17 loc14 ------------ BB17 [117..11A) -> BB19 (always), preds={} succs={BB19} ***** BB17 STMT00074 (IL 0x117...0x118) [000350] -A---------- * ASG int [000349] D------N---- +--* LCL_VAR int V33 tmp3 [000348] ------------ \--* CNS_INT int 0 ------------ BB18 [11A..11F), preds={} succs={BB19} ***** BB18 STMT00037 (IL 0x11A...0x11E) [000164] -A---------- * ASG int [000163] D------N---- +--* LCL_VAR int V33 tmp3 [000162] ------------ \--* SUB int [000160] ------------ +--* LCL_VAR int V18 loc15 [000161] ------------ \--* LCL_VAR int V17 loc14 ------------ BB19 [11F..126) -> BB21 (cond), preds={} succs={BB20,BB21} ***** BB19 STMT00038 (IL ???...0x11F) [000168] -A---------- * ASG int [000167] D------N---- +--* LCL_VAR int V19 loc16 [000166] ------------ \--* LCL_VAR int V33 tmp3 ***** BB19 STMT00039 (IL 0x121...0x124) [000172] ------------ * JTRUE void [000171] N--------U-- \--* LE int [000169] ------------ +--* LCL_VAR int V19 loc16 [000170] ------------ \--* CNS_INT int 0 ------------ BB20 [126..12F), preds={} succs={BB21} ***** BB20 STMT00073 (IL 0x126...0x12A) [000347] --C-G------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft [000345] ------------ arg0 +--* ADDR byref [000344] -------N---- | \--* LCL_VAR struct V15 loc12 [000346] ------------ arg1 \--* LCL_VAR int V19 loc16 ------------ BB21 [12F..13E) -> BB25 (cond), preds={} succs={BB22,BB25} ***** BB21 STMT00040 (IL 0x12F...0x133) [000177] -A---------- * ASG int [000176] D------N---- +--* LCL_VAR int V20 loc17 [000175] ------------ \--* SUB int [000173] ------------ +--* LCL_VAR int V03 loc0 [000174] ------------ \--* LCL_VAR int V13 loc10 ***** BB21 STMT00041 (IL 0x135...0x137) [000180] -A---------- * ASG int [000179] D------N---- +--* LCL_VAR int V21 loc18 [000178] ------------ \--* LCL_VAR int V20 loc17 ***** BB21 STMT00042 (IL 0x139...0x13C) [000184] ------------ * JTRUE void [000183] N--------U-- \--* LE int [000181] ------------ +--* LCL_VAR int V13 loc10 [000182] ------------ \--* CNS_INT int 0 ------------ BB22 [13E..144) -> BB24 (cond), preds={} succs={BB23,BB24} ***** BB22 STMT00070 (IL 0x13E...0x142) [000329] ------------ * JTRUE void [000328] N--------U-- \--* LE int [000326] ------------ +--* LCL_VAR int V19 loc16 [000327] ------------ \--* LCL_VAR int V21 loc18 ------------ BB23 [144..155) (return), preds={} succs={} ***** BB23 STMT00072 (IL 0x144...0x154) [000343] --C-G------- * RETURN int [000342] --C-G------- \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits [000335] ------------ arg0 +--* LCL_VAR ref V12 loc9 [000336] ------------ arg1 +--* LCL_VAR int V13 loc10 [000339] N--------U-- arg2 +--* GT int [000337] ------------ | +--* LCL_VAR int V10 loc7 [000338] ------------ | \--* CNS_INT int 0 [000340] ------------ arg3 +--* LCL_VAR ref V01 arg1 [000341] ------------ arg4 \--* LCL_VAR byref V02 arg2 ------------ BB24 [155..15C), preds={} succs={BB25} ***** BB24 STMT00071 (IL 0x155...0x15A) [000334] -A---------- * ASG int [000333] D------N---- +--* LCL_VAR int V21 loc18 [000332] ------------ \--* SUB int [000330] ------------ +--* LCL_VAR int V21 loc18 [000331] ------------ \--* LCL_VAR int V19 loc16 ------------ BB25 [15C..167) -> BB27 (cond), preds={} succs={BB26,BB27} ***** BB25 STMT00105 (IL 0x15C... ???) [000506] -A---------- * ASG struct (copy) [000504] D------N---- +--* LCL_VAR struct V49 tmp19 [000191] n----------- \--* OBJ struct [000190] ------------ \--* ADDR byref [000185] -------N---- \--* LCL_VAR struct V15 loc12 ***** BB25 STMT00106 (IL 0x15C... ???) [000509] -A---------- * ASG struct (copy) [000507] D------N---- +--* LCL_VAR struct V50 tmp20 [000189] n----------- \--* OBJ struct [000188] ------------ \--* ADDR byref [000186] -------N---- \--* LCL_VAR struct V16 loc13 ***** BB25 STMT00044 (IL ???... ???) [000195] --C--------- * JTRUE void [000194] --C--------- \--* NE int [000503] --C-G------- +--* LT int [000499] --C-G------- | +--* CALL int System.Numerics.BigInteger.CompareTo [000497] ------------ this in rcx | | +--* ADDR byref [000496] -------N---- | | | \--* LCL_VAR struct V49 tmp19 [000501] n----------- arg1 | | \--* OBJ struct [000500] ------------ | | \--* ADDR byref [000498] -------N---- | | \--* LCL_VAR struct V50 tmp20 [000502] ------------ | \--* CNS_INT int 0 [000193] ------------ \--* CNS_INT int 0 ------------ BB26 [167..16B) -> BB28 (always), preds={} succs={BB28} ***** BB26 STMT00069 (IL 0x167...0x169) [000324] -A---------- * ASG int [000323] D------N---- +--* LCL_VAR int V34 tmp4 [000322] ------------ \--* LCL_VAR int V19 loc16 ------------ BB27 [16B..16F), preds={} succs={BB28} ***** BB27 STMT00045 (IL 0x16B...0x16E) [000200] -A---------- * ASG int [000199] D------N---- +--* LCL_VAR int V34 tmp4 [000198] ------------ \--* ADD int [000196] ------------ +--* LCL_VAR int V19 loc16 [000197] ------------ \--* CNS_INT int 1 ------------ BB28 [16F..1A4) -> BB33 (cond), preds={} succs={BB29,BB33} ***** BB28 STMT00046 (IL ???...0x16F) [000204] -A---------- * ASG int [000203] D------N---- +--* LCL_VAR int V22 loc19 [000202] ------------ \--* LCL_VAR int V34 tmp4 ***** BB28 STMT00047 (IL 0x171...0x18A) [000208] --C-G------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft [000206] ------------ arg0 +--* ADDR byref [000205] -------N---- | \--* LCL_VAR struct V15 loc12 [000207] ------------ arg1 \--* LCL_VAR int V21 loc18 ***** BB28 STMT00048 (IL 0x17A... ???) [000213] S-C-G------- * CALL void System.Numerics.BigInteger.DivRem [000220] ------------ arg0 +--* ADDR byref [000219] -------N---- | \--* LCL_VAR struct V35 tmp5 [000217] n----------- arg1 +--* OBJ struct [000216] ------------ | \--* ADDR byref [000209] -------N---- | \--* LCL_VAR struct V15 loc12 [000215] n----------- arg2 +--* OBJ struct [000214] ------------ | \--* ADDR byref [000210] -------N---- | \--* LCL_VAR struct V16 loc13 [000212] ------------ arg3 \--* ADDR byref [000211] -------N---- \--* LCL_VAR struct V23 loc20 ***** BB28 STMT00050 (IL ???... ???) [000226] -AC--------- * ASG long [000225] D------N---- +--* LCL_VAR long V24 loc21 [000218] --C-G------- \--* CALL long System.Numerics.BigInteger.op_Explicit [000223] n----------- arg0 \--* OBJ struct [000222] ------------ \--* ADDR byref [000221] -------N---- \--* LCL_VAR struct V35 tmp5 ***** BB28 STMT00052 (IL ???... ???) [000232] -AC--------- * ASG int [000231] D------N---- +--* LCL_VAR int V25 loc22 [000516] ------------ \--* EQ int [000514] ------------ +--* FIELD int _sign [000512] ------------ | \--* ADDR byref [000513] -------N---- | \--* LCL_VAR struct V23 loc20 [000515] ------------ \--* CNS_INT int 0 ***** BB28 STMT00054 (IL ???... ???) [000237] -AC--------- * ASG int [000236] D------N---- +--* LCL_VAR int V26 loc23 [000234] --C-G------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits [000233] ------------ arg0 \--* LCL_VAR long V24 loc21 ***** BB28 STMT00055 (IL 0x19E...0x1A2) [000241] ------------ * JTRUE void [000240] N--------U-- \--* LE int [000238] ------------ +--* LCL_VAR int V26 loc23 [000239] ------------ \--* LCL_VAR int V20 loc17 ------------ BB29 [1A4..1AF) -> BB31 (cond), preds={} succs={BB30,BB31} ***** BB29 STMT00063 (IL 0x1A4...0x1A9) [000286] -A---------- * ASG int [000285] D------N---- +--* LCL_VAR int V29 loc26 [000284] ------------ \--* SUB int [000282] ------------ +--* LCL_VAR int V26 loc23 [000283] ------------ \--* LCL_VAR int V20 loc17 ***** BB29 STMT00064 (IL 0x1AB...0x1AD) [000290] ------------ * JTRUE void [000289] ------------ \--* EQ int [000287] ------------ +--* LCL_VAR int V25 loc22 [000288] ------------ \--* CNS_INT int 0 ------------ BB30 [1AF..1C3) -> BB32 (always), preds={} succs={BB32} ***** BB30 STMT00068 (IL 0x1AF...0x1C1) [000320] -A---------- * ASG int [000319] D------N---- +--* LCL_VAR int V37 tmp7 [000318] ------------ \--* EQ int [000315] ------------ +--* AND long [000305] ------------ | +--* LCL_VAR long V24 loc21 [000314] ------------ | \--* SUB long [000311] ------------ | +--* LSH long [000307] ------------ | | +--* CAST long <- int [000306] ------------ | | | \--* CNS_INT int 1 [000310] ------------ | | \--* AND int [000308] ------------ | | +--* LCL_VAR int V29 loc26 [000309] ------------ | | \--* CNS_INT int 63 [000313] ------------ | \--* CAST long <- int [000312] ------------ | \--* CNS_INT int 1 [000317] ------------ \--* CAST long <- int [000316] ------------ \--* CNS_INT int 0 ------------ BB31 [1C3..1C4), preds={} succs={BB32} ***** BB31 STMT00065 (IL 0x1C3...0x1C3) [000293] -A---------- * ASG int [000292] D------N---- +--* LCL_VAR int V37 tmp7 [000291] ------------ \--* CNS_INT int 0 ------------ BB32 [1C4..1D0), preds={} succs={BB33} ***** BB32 STMT00066 (IL ???...0x1C4) [000297] -A---------- * ASG int [000296] D------N---- +--* LCL_VAR int V25 loc22 [000295] ------------ \--* LCL_VAR int V37 tmp7 ***** BB32 STMT00067 (IL 0x1C6...0x1CE) [000304] -A---------- * ASG long [000303] D------N---- +--* LCL_VAR long V24 loc21 [000302] ------------ \--* RSZ long [000298] ------------ +--* LCL_VAR long V24 loc21 [000301] ------------ \--* AND int [000299] ------------ +--* LCL_VAR int V29 loc26 [000300] ------------ \--* CNS_INT int 63 ------------ BB33 [1D0..1E7) -> BB35 (cond), preds={} succs={BB34,BB35} ***** BB33 STMT00057 (IL ???... ???) [000254] -AC--------- * ASG long [000253] D------N---- +--* LCL_VAR long V27 loc24 [000252] --C--------- \--* ADD long [000250] --C--------- +--* LSH long [000243] --C-G------- | +--* CALL long System.Numerics.BigInteger.op_Explicit [000245] n----------- arg0 | | \--* OBJ struct [000244] ------------ | | \--* ADDR byref [000242] -------N---- | | \--* LCL_VAR struct V11 loc8 [000249] ------------ | \--* AND int [000247] ------------ | +--* LCL_VAR int V20 loc17 [000248] ------------ | \--* CNS_INT int 63 [000251] ------------ \--* LCL_VAR long V24 loc21 ***** BB33 STMT00058 (IL 0x1E2...0x1E5) [000258] ------------ * JTRUE void [000257] N--------U-- \--* GT int [000255] ------------ +--* LCL_VAR int V13 loc10 [000256] ------------ \--* CNS_INT int 0 ------------ BB34 [1E7..1EE) -> BB36 (always), preds={} succs={BB36} ***** BB34 STMT00062 (IL 0x1E7...0x1EC) [000280] -A---------- * ASG int [000279] D------N---- +--* LCL_VAR int V36 tmp6 [000278] ------------ \--* SUB int [000276] ------------ +--* NEG int [000275] ------------ | \--* LCL_VAR int V22 loc19 [000277] ------------ \--* CNS_INT int 1 ------------ BB35 [1EE..1F2), preds={} succs={BB36} ***** BB35 STMT00059 (IL 0x1EE...0x1F1) [000263] -A---------- * ASG int [000262] D------N---- +--* LCL_VAR int V36 tmp6 [000261] ------------ \--* SUB int [000259] ------------ +--* LCL_VAR int V13 loc10 [000260] ------------ \--* CNS_INT int 2 ------------ BB36 [1F2..202) (return), preds={} succs={} ***** BB36 STMT00060 (IL ???...0x1F2) [000267] -A---------- * ASG int [000266] D------N---- +--* LCL_VAR int V28 loc25 [000265] ------------ \--* LCL_VAR int V36 tmp6 ***** BB36 STMT00061 (IL 0x1F4...0x201) [000274] --C-G------- * RETURN int [000273] --C-G------- \--* CALL nullcheck int FloatingPointType.AssembleFloatingPointValue [000268] ------------ this in rcx +--* LCL_VAR ref V01 arg1 [000269] ------------ arg1 +--* LCL_VAR long V27 loc24 [000270] ------------ arg2 +--* LCL_VAR int V28 loc25 [000271] ------------ arg3 +--* LCL_VAR int V25 loc22 [000272] ------------ arg4 \--* LCL_VAR byref V02 arg2 ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Allocate Objects no newobjs in this method; punting *************** Finishing PHASE Allocate Objects [no changes] *************** Starting PHASE Morph - Add internal blocks fgNewBBinRegion(jumpKind=4, tryIndex=0, hndIndex=0, putInFilter=false, runRarely=false, insertAtEnd=true): inserting after BB36 New Basic Block BB53 [0052] created. newReturnBB [BB53] created mergeReturns statement tree [000520] added to genReturnBB BB53 [0052] [000520] ------------ * RETURN int [000404] ------------ \--* CNS_INT int 1 Removing statement STMT00088 (IL 0x015...0x016) [000405] ------------ * RETURN int [000404] ------------ \--* CNS_INT int 1 in BB02 as useless: fgNewBBinRegion(jumpKind=4, tryIndex=0, hndIndex=0, putInFilter=false, runRarely=false, insertAtEnd=true): inserting after BB53 New Basic Block BB54 [0053] created. newReturnBB [BB54] created mergeReturns statement tree [000521] added to genReturnBB BB54 [0053] [000521] ------------ * RETURN int [000397] ------------ \--* CNS_INT int 3 Removing statement STMT00086 (IL 0x078...0x079) [000398] ------------ * RETURN int [000397] ------------ \--* CNS_INT int 3 in BB05 as useless: fgNewBBinRegion(jumpKind=4, tryIndex=0, hndIndex=0, putInFilter=false, runRarely=false, insertAtEnd=true): inserting after BB54 New Basic Block BB55 [0054] created. newReturnBB [BB55] created lvaGrabTemp returning 51 (V51 tmp21) called for Single return block return value. mergeReturns statement tree [000523] added to genReturnBB BB55 [0054] [000523] ------------ * RETURN int [000522] -------N---- \--* LCL_VAR int V51 tmp21 fgNewBBinRegion(jumpKind=4, tryIndex=0, hndIndex=0, putInFilter=false, runRarely=false, insertAtEnd=true): inserting after BB55 New Basic Block BB56 [0055] created. newReturnBB [BB56] created mergeReturns statement tree [000524] added to genReturnBB BB56 [0055] [000524] ------------ * RETURN int [000374] ------------ \--* CNS_INT int 2 Removing statement STMT00080 (IL 0x0E1...0x0E2) [000375] ------------ * RETURN int [000374] ------------ \--* CNS_INT int 2 in BB15 as useless: Relocated block [BB53..BB53] inserted after BB02 Relocated block [BB54..BB54] inserted after BB05 Relocated block [BB56..BB56] inserted after BB15 *************** After fgAddInternal() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..00D)-> BB03 ( cond ) i idxlen BB02 [0001] 1 1 [00D..017)-> BB53 (always) i BB53 [0052] 1 1 [???..???) (return) internal target BB03 [0002] 1 1 [017..065) i BB38 [0037] 1 1 [020..021)-> BB40 ( cond ) i BB39 [0038] 1 1 [020..021)-> BB41 (always) i BB40 [0039] 1 1 [020..021) i BB41 [0040] 1 1 [???..???) i internal idxlen BB43 [0042] 1 1 [000..000)-> BB45 ( cond ) i internal BB44 [0043] 1 1 [000..000)-> BB46 (always) i internal BB45 [0044] 1 1 [000..000) i internal BB46 [0045] 1 1 [???..???)-> BB07 ( cond ) i internal idxlen BB04 [0003] 1 1 [065..070)-> BB06 ( cond ) i BB05 [0004] 1 1 [070..07A)-> BB54 (always) i BB54 [0053] 1 1 [???..???) (return) internal target BB06 [0005] 1 1 [07A..082) i BB07 [0006] 2 1 [082..092)-> BB09 ( cond ) i BB08 [0007] 1 1 [092..096)-> BB10 ( cond ) i BB09 [0008] 2 1 [096..0A7) (return) i BB10 [0009] 1 1 [0A7..0B0)-> BB12 ( cond ) i BB11 [0010] 1 1 [0B0..0B4)-> BB13 (always) i BB12 [0011] 1 1 [0B4..0BE) i BB13 [0012] 2 1 [0BE..0C4)-> BB16 ( cond ) i BB14 [0013] 1 1 [0C4..0D9)-> BB16 ( cond ) i idxlen BB15 [0014] 1 1 [0D9..0E3)-> BB56 (always) i BB56 [0055] 1 1 [???..???) (return) internal target BB16 [0015] 2 1 [0E3..117)-> BB18 ( cond ) i BB17 [0016] 1 1 [117..11A)-> BB19 (always) i BB18 [0017] 1 1 [11A..11F) i BB19 [0018] 2 1 [11F..126)-> BB21 ( cond ) i BB20 [0019] 1 1 [126..12F) i BB21 [0020] 2 1 [12F..13E)-> BB25 ( cond ) i BB22 [0021] 1 1 [13E..144)-> BB24 ( cond ) i BB23 [0022] 1 1 [144..155) (return) i BB24 [0023] 1 1 [155..15C) i BB25 [0024] 2 1 [15C..167)-> BB27 ( cond ) i BB26 [0025] 1 1 [167..16B)-> BB28 (always) i BB27 [0026] 1 1 [16B..16F) i BB28 [0027] 2 1 [16F..1A4)-> BB33 ( cond ) i BB29 [0028] 1 1 [1A4..1AF)-> BB31 ( cond ) i BB30 [0029] 1 1 [1AF..1C3)-> BB32 (always) i BB31 [0030] 1 1 [1C3..1C4) i BB32 [0031] 2 1 [1C4..1D0) i BB33 [0032] 2 1 [1D0..1E7)-> BB35 ( cond ) i BB34 [0033] 1 1 [1E7..1EE)-> BB36 (always) i BB35 [0034] 1 1 [1EE..1F2) i BB36 [0035] 2 1 [1F2..202) (return) i BB55 [0054] 1 1 [???..???) (return) keep internal target ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** Finishing PHASE Morph - Add internal blocks *************** Starting PHASE Remove empty try *************** In fgRemoveEmptyTry() No EH in this method, nothing to remove. *************** Finishing PHASE Remove empty try [no changes] *************** Starting PHASE Remove empty finally No EH in this method, nothing to remove. *************** Finishing PHASE Remove empty finally [no changes] *************** Starting PHASE Merge callfinally chains No EH in this method, nothing to merge. *************** Finishing PHASE Merge callfinally chains [no changes] *************** Starting PHASE Clone finally No EH in this method, no cloning. *************** Finishing PHASE Clone finally [no changes] *************** Starting PHASE Compute preds Renumbering the basic blocks for fgComputePred *************** Before renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..00D)-> BB03 ( cond ) i idxlen BB02 [0001] 1 1 [00D..017)-> BB53 (always) i BB53 [0052] 1 1 [???..???) (return) internal target BB03 [0002] 1 1 [017..065) i BB38 [0037] 1 1 [020..021)-> BB40 ( cond ) i BB39 [0038] 1 1 [020..021)-> BB41 (always) i BB40 [0039] 1 1 [020..021) i BB41 [0040] 1 1 [???..???) i internal idxlen BB43 [0042] 1 1 [000..000)-> BB45 ( cond ) i internal BB44 [0043] 1 1 [000..000)-> BB46 (always) i internal BB45 [0044] 1 1 [000..000) i internal BB46 [0045] 1 1 [???..???)-> BB07 ( cond ) i internal idxlen BB04 [0003] 1 1 [065..070)-> BB06 ( cond ) i BB05 [0004] 1 1 [070..07A)-> BB54 (always) i BB54 [0053] 1 1 [???..???) (return) internal target BB06 [0005] 1 1 [07A..082) i BB07 [0006] 2 1 [082..092)-> BB09 ( cond ) i BB08 [0007] 1 1 [092..096)-> BB10 ( cond ) i BB09 [0008] 2 1 [096..0A7) (return) i BB10 [0009] 1 1 [0A7..0B0)-> BB12 ( cond ) i BB11 [0010] 1 1 [0B0..0B4)-> BB13 (always) i BB12 [0011] 1 1 [0B4..0BE) i BB13 [0012] 2 1 [0BE..0C4)-> BB16 ( cond ) i BB14 [0013] 1 1 [0C4..0D9)-> BB16 ( cond ) i idxlen BB15 [0014] 1 1 [0D9..0E3)-> BB56 (always) i BB56 [0055] 1 1 [???..???) (return) internal target BB16 [0015] 2 1 [0E3..117)-> BB18 ( cond ) i BB17 [0016] 1 1 [117..11A)-> BB19 (always) i BB18 [0017] 1 1 [11A..11F) i BB19 [0018] 2 1 [11F..126)-> BB21 ( cond ) i BB20 [0019] 1 1 [126..12F) i BB21 [0020] 2 1 [12F..13E)-> BB25 ( cond ) i BB22 [0021] 1 1 [13E..144)-> BB24 ( cond ) i BB23 [0022] 1 1 [144..155) (return) i BB24 [0023] 1 1 [155..15C) i BB25 [0024] 2 1 [15C..167)-> BB27 ( cond ) i BB26 [0025] 1 1 [167..16B)-> BB28 (always) i BB27 [0026] 1 1 [16B..16F) i BB28 [0027] 2 1 [16F..1A4)-> BB33 ( cond ) i BB29 [0028] 1 1 [1A4..1AF)-> BB31 ( cond ) i BB30 [0029] 1 1 [1AF..1C3)-> BB32 (always) i BB31 [0030] 1 1 [1C3..1C4) i BB32 [0031] 2 1 [1C4..1D0) i BB33 [0032] 2 1 [1D0..1E7)-> BB35 ( cond ) i BB34 [0033] 1 1 [1E7..1EE)-> BB36 (always) i BB35 [0034] 1 1 [1EE..1F2) i BB36 [0035] 2 1 [1F2..202) (return) i BB55 [0054] 1 1 [???..???) (return) keep internal target ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty Renumber BB53 to BB03 Renumber BB03 to BB04 Renumber BB38 to BB05 Renumber BB39 to BB06 Renumber BB40 to BB07 Renumber BB41 to BB08 Renumber BB43 to BB09 Renumber BB44 to BB10 Renumber BB45 to BB11 Renumber BB46 to BB12 Renumber BB04 to BB13 Renumber BB05 to BB14 Renumber BB54 to BB15 Renumber BB06 to BB16 Renumber BB07 to BB17 Renumber BB08 to BB18 Renumber BB09 to BB19 Renumber BB10 to BB20 Renumber BB11 to BB21 Renumber BB12 to BB22 Renumber BB13 to BB23 Renumber BB14 to BB24 Renumber BB15 to BB25 Renumber BB56 to BB26 Renumber BB16 to BB27 Renumber BB17 to BB28 Renumber BB18 to BB29 Renumber BB19 to BB30 Renumber BB20 to BB31 Renumber BB21 to BB32 Renumber BB22 to BB33 Renumber BB23 to BB34 Renumber BB24 to BB35 Renumber BB25 to BB36 Renumber BB26 to BB37 Renumber BB27 to BB38 Renumber BB28 to BB39 Renumber BB29 to BB40 Renumber BB30 to BB41 Renumber BB31 to BB42 Renumber BB32 to BB43 Renumber BB33 to BB44 Renumber BB34 to BB45 Renumber BB35 to BB46 Renumber BB36 to BB47 Renumber BB55 to BB48 *************** After renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..00D)-> BB04 ( cond ) i idxlen BB02 [0001] 1 1 [00D..017)-> BB03 (always) i BB03 [0052] 1 1 [???..???) (return) internal target BB04 [0002] 1 1 [017..065) i BB05 [0037] 1 1 [020..021)-> BB07 ( cond ) i BB06 [0038] 1 1 [020..021)-> BB08 (always) i BB07 [0039] 1 1 [020..021) i BB08 [0040] 1 1 [???..???) i internal idxlen BB09 [0042] 1 1 [000..000)-> BB11 ( cond ) i internal BB10 [0043] 1 1 [000..000)-> BB12 (always) i internal BB11 [0044] 1 1 [000..000) i internal BB12 [0045] 1 1 [???..???)-> BB17 ( cond ) i internal idxlen BB13 [0003] 1 1 [065..070)-> BB16 ( cond ) i BB14 [0004] 1 1 [070..07A)-> BB15 (always) i BB15 [0053] 1 1 [???..???) (return) internal target BB16 [0005] 1 1 [07A..082) i BB17 [0006] 2 1 [082..092)-> BB19 ( cond ) i BB18 [0007] 1 1 [092..096)-> BB20 ( cond ) i BB19 [0008] 2 1 [096..0A7) (return) i BB20 [0009] 1 1 [0A7..0B0)-> BB22 ( cond ) i BB21 [0010] 1 1 [0B0..0B4)-> BB23 (always) i BB22 [0011] 1 1 [0B4..0BE) i BB23 [0012] 2 1 [0BE..0C4)-> BB27 ( cond ) i BB24 [0013] 1 1 [0C4..0D9)-> BB27 ( cond ) i idxlen BB25 [0014] 1 1 [0D9..0E3)-> BB26 (always) i BB26 [0055] 1 1 [???..???) (return) internal target BB27 [0015] 2 1 [0E3..117)-> BB29 ( cond ) i BB28 [0016] 1 1 [117..11A)-> BB30 (always) i BB29 [0017] 1 1 [11A..11F) i BB30 [0018] 2 1 [11F..126)-> BB32 ( cond ) i BB31 [0019] 1 1 [126..12F) i BB32 [0020] 2 1 [12F..13E)-> BB36 ( cond ) i BB33 [0021] 1 1 [13E..144)-> BB35 ( cond ) i BB34 [0022] 1 1 [144..155) (return) i BB35 [0023] 1 1 [155..15C) i BB36 [0024] 2 1 [15C..167)-> BB38 ( cond ) i BB37 [0025] 1 1 [167..16B)-> BB39 (always) i BB38 [0026] 1 1 [16B..16F) i BB39 [0027] 2 1 [16F..1A4)-> BB44 ( cond ) i BB40 [0028] 1 1 [1A4..1AF)-> BB42 ( cond ) i BB41 [0029] 1 1 [1AF..1C3)-> BB43 (always) i BB42 [0030] 1 1 [1C3..1C4) i BB43 [0031] 2 1 [1C4..1D0) i BB44 [0032] 2 1 [1D0..1E7)-> BB46 ( cond ) i BB45 [0033] 1 1 [1E7..1EE)-> BB47 (always) i BB46 [0034] 1 1 [1EE..1F2) i BB47 [0035] 2 1 [1F2..202) (return) i BB48 [0054] 1 1 [???..???) (return) keep internal target ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty New BlockSet epoch 2, # of blocks (including unused BB00): 49, bitset array size: 1 (short) *************** In fgComputePreds() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..00D)-> BB04 ( cond ) i idxlen BB02 [0001] 1 1 [00D..017)-> BB03 (always) i BB03 [0052] 1 1 [???..???) (return) internal target BB04 [0002] 1 1 [017..065) i BB05 [0037] 1 1 [020..021)-> BB07 ( cond ) i BB06 [0038] 1 1 [020..021)-> BB08 (always) i BB07 [0039] 1 1 [020..021) i BB08 [0040] 1 1 [???..???) i internal idxlen BB09 [0042] 1 1 [000..000)-> BB11 ( cond ) i internal BB10 [0043] 1 1 [000..000)-> BB12 (always) i internal BB11 [0044] 1 1 [000..000) i internal BB12 [0045] 1 1 [???..???)-> BB17 ( cond ) i internal idxlen BB13 [0003] 1 1 [065..070)-> BB16 ( cond ) i BB14 [0004] 1 1 [070..07A)-> BB15 (always) i BB15 [0053] 1 1 [???..???) (return) internal target BB16 [0005] 1 1 [07A..082) i BB17 [0006] 2 1 [082..092)-> BB19 ( cond ) i BB18 [0007] 1 1 [092..096)-> BB20 ( cond ) i BB19 [0008] 2 1 [096..0A7) (return) i BB20 [0009] 1 1 [0A7..0B0)-> BB22 ( cond ) i BB21 [0010] 1 1 [0B0..0B4)-> BB23 (always) i BB22 [0011] 1 1 [0B4..0BE) i BB23 [0012] 2 1 [0BE..0C4)-> BB27 ( cond ) i BB24 [0013] 1 1 [0C4..0D9)-> BB27 ( cond ) i idxlen BB25 [0014] 1 1 [0D9..0E3)-> BB26 (always) i BB26 [0055] 1 1 [???..???) (return) internal target BB27 [0015] 2 1 [0E3..117)-> BB29 ( cond ) i BB28 [0016] 1 1 [117..11A)-> BB30 (always) i BB29 [0017] 1 1 [11A..11F) i BB30 [0018] 2 1 [11F..126)-> BB32 ( cond ) i BB31 [0019] 1 1 [126..12F) i BB32 [0020] 2 1 [12F..13E)-> BB36 ( cond ) i BB33 [0021] 1 1 [13E..144)-> BB35 ( cond ) i BB34 [0022] 1 1 [144..155) (return) i BB35 [0023] 1 1 [155..15C) i BB36 [0024] 2 1 [15C..167)-> BB38 ( cond ) i BB37 [0025] 1 1 [167..16B)-> BB39 (always) i BB38 [0026] 1 1 [16B..16F) i BB39 [0027] 2 1 [16F..1A4)-> BB44 ( cond ) i BB40 [0028] 1 1 [1A4..1AF)-> BB42 ( cond ) i BB41 [0029] 1 1 [1AF..1C3)-> BB43 (always) i BB42 [0030] 1 1 [1C3..1C4) i BB43 [0031] 2 1 [1C4..1D0) i BB44 [0032] 2 1 [1D0..1E7)-> BB46 ( cond ) i BB45 [0033] 1 1 [1E7..1EE)-> BB47 (always) i BB46 [0034] 1 1 [1EE..1F2) i BB47 [0035] 2 1 [1F2..202) (return) i BB48 [0054] 1 1 [???..???) (return) keep internal target ----------------------------------------------------------------------------------------------------------------------------------------- *************** After fgComputePreds() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..00D)-> BB04 ( cond ) i label target idxlen BB02 [0001] 1 BB01 1 [00D..017)-> BB03 (always) i BB03 [0052] 1 BB02 1 [???..???) (return) internal label target BB04 [0002] 1 BB01 1 [017..065) i label target BB05 [0037] 1 BB04 1 [020..021)-> BB07 ( cond ) i BB06 [0038] 1 BB05 1 [020..021)-> BB08 (always) i BB07 [0039] 1 BB05 1 [020..021) i label target BB08 [0040] 2 BB06,BB07 1 [???..???) i internal label target idxlen BB09 [0042] 1 BB08 1 [000..000)-> BB11 ( cond ) i internal BB10 [0043] 1 BB09 1 [000..000)-> BB12 (always) i internal BB11 [0044] 1 BB09 1 [000..000) i internal label target BB12 [0045] 2 BB10,BB11 1 [???..???)-> BB17 ( cond ) i internal label target idxlen BB13 [0003] 1 BB12 1 [065..070)-> BB16 ( cond ) i BB14 [0004] 1 BB13 1 [070..07A)-> BB15 (always) i BB15 [0053] 1 BB14 1 [???..???) (return) internal label target BB16 [0005] 1 BB13 1 [07A..082) i label target BB17 [0006] 2 BB12,BB16 1 [082..092)-> BB19 ( cond ) i label target BB18 [0007] 1 BB17 1 [092..096)-> BB20 ( cond ) i BB19 [0008] 2 BB17,BB18 1 [096..0A7) (return) i label target BB20 [0009] 1 BB18 1 [0A7..0B0)-> BB22 ( cond ) i label target BB21 [0010] 1 BB20 1 [0B0..0B4)-> BB23 (always) i BB22 [0011] 1 BB20 1 [0B4..0BE) i label target BB23 [0012] 2 BB21,BB22 1 [0BE..0C4)-> BB27 ( cond ) i label target BB24 [0013] 1 BB23 1 [0C4..0D9)-> BB27 ( cond ) i idxlen BB25 [0014] 1 BB24 1 [0D9..0E3)-> BB26 (always) i BB26 [0055] 1 BB25 1 [???..???) (return) internal label target BB27 [0015] 2 BB23,BB24 1 [0E3..117)-> BB29 ( cond ) i label target BB28 [0016] 1 BB27 1 [117..11A)-> BB30 (always) i BB29 [0017] 1 BB27 1 [11A..11F) i label target BB30 [0018] 2 BB28,BB29 1 [11F..126)-> BB32 ( cond ) i label target BB31 [0019] 1 BB30 1 [126..12F) i BB32 [0020] 2 BB30,BB31 1 [12F..13E)-> BB36 ( cond ) i label target BB33 [0021] 1 BB32 1 [13E..144)-> BB35 ( cond ) i BB34 [0022] 1 BB33 1 [144..155) (return) i BB35 [0023] 1 BB33 1 [155..15C) i label target BB36 [0024] 2 BB32,BB35 1 [15C..167)-> BB38 ( cond ) i label target BB37 [0025] 1 BB36 1 [167..16B)-> BB39 (always) i BB38 [0026] 1 BB36 1 [16B..16F) i label target BB39 [0027] 2 BB37,BB38 1 [16F..1A4)-> BB44 ( cond ) i label target BB40 [0028] 1 BB39 1 [1A4..1AF)-> BB42 ( cond ) i BB41 [0029] 1 BB40 1 [1AF..1C3)-> BB43 (always) i BB42 [0030] 1 BB40 1 [1C3..1C4) i label target BB43 [0031] 2 BB41,BB42 1 [1C4..1D0) i label target BB44 [0032] 2 BB39,BB43 1 [1D0..1E7)-> BB46 ( cond ) i label target BB45 [0033] 1 BB44 1 [1E7..1EE)-> BB47 (always) i BB46 [0034] 1 BB44 1 [1EE..1F2) i label target BB47 [0035] 2 BB45,BB46 1 [1F2..202) (return) i label target BB48 [0054] 0 1 [???..???) (return) keep internal target ----------------------------------------------------------------------------------------------------------------------------------------- *************** Finishing PHASE Compute preds *************** Starting PHASE Merge throw blocks *************** In fgTailMergeThrows Method does not have multiple noreturn calls. *************** Finishing PHASE Merge throw blocks [no changes] *************** Starting PHASE Update flow graph early pass *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..00D)-> BB04 ( cond ) i label target idxlen BB02 [0001] 1 BB01 1 [00D..017)-> BB03 (always) i BB03 [0052] 1 BB02 1 [???..???) (return) internal label target BB04 [0002] 1 BB01 1 [017..065) i label target BB05 [0037] 1 BB04 1 [020..021)-> BB07 ( cond ) i BB06 [0038] 1 BB05 1 [020..021)-> BB08 (always) i BB07 [0039] 1 BB05 1 [020..021) i label target BB08 [0040] 2 BB06,BB07 1 [???..???) i internal label target idxlen BB09 [0042] 1 BB08 1 [000..000)-> BB11 ( cond ) i internal BB10 [0043] 1 BB09 1 [000..000)-> BB12 (always) i internal BB11 [0044] 1 BB09 1 [000..000) i internal label target BB12 [0045] 2 BB10,BB11 1 [???..???)-> BB17 ( cond ) i internal label target idxlen BB13 [0003] 1 BB12 1 [065..070)-> BB16 ( cond ) i BB14 [0004] 1 BB13 1 [070..07A)-> BB15 (always) i BB15 [0053] 1 BB14 1 [???..???) (return) internal label target BB16 [0005] 1 BB13 1 [07A..082) i label target BB17 [0006] 2 BB12,BB16 1 [082..092)-> BB19 ( cond ) i label target BB18 [0007] 1 BB17 1 [092..096)-> BB20 ( cond ) i BB19 [0008] 2 BB17,BB18 1 [096..0A7) (return) i label target BB20 [0009] 1 BB18 1 [0A7..0B0)-> BB22 ( cond ) i label target BB21 [0010] 1 BB20 1 [0B0..0B4)-> BB23 (always) i BB22 [0011] 1 BB20 1 [0B4..0BE) i label target BB23 [0012] 2 BB21,BB22 1 [0BE..0C4)-> BB27 ( cond ) i label target BB24 [0013] 1 BB23 1 [0C4..0D9)-> BB27 ( cond ) i idxlen BB25 [0014] 1 BB24 1 [0D9..0E3)-> BB26 (always) i BB26 [0055] 1 BB25 1 [???..???) (return) internal label target BB27 [0015] 2 BB23,BB24 1 [0E3..117)-> BB29 ( cond ) i label target BB28 [0016] 1 BB27 1 [117..11A)-> BB30 (always) i BB29 [0017] 1 BB27 1 [11A..11F) i label target BB30 [0018] 2 BB28,BB29 1 [11F..126)-> BB32 ( cond ) i label target BB31 [0019] 1 BB30 1 [126..12F) i BB32 [0020] 2 BB30,BB31 1 [12F..13E)-> BB36 ( cond ) i label target BB33 [0021] 1 BB32 1 [13E..144)-> BB35 ( cond ) i BB34 [0022] 1 BB33 1 [144..155) (return) i BB35 [0023] 1 BB33 1 [155..15C) i label target BB36 [0024] 2 BB32,BB35 1 [15C..167)-> BB38 ( cond ) i label target BB37 [0025] 1 BB36 1 [167..16B)-> BB39 (always) i BB38 [0026] 1 BB36 1 [16B..16F) i label target BB39 [0027] 2 BB37,BB38 1 [16F..1A4)-> BB44 ( cond ) i label target BB40 [0028] 1 BB39 1 [1A4..1AF)-> BB42 ( cond ) i BB41 [0029] 1 BB40 1 [1AF..1C3)-> BB43 (always) i BB42 [0030] 1 BB40 1 [1C3..1C4) i label target BB43 [0031] 2 BB41,BB42 1 [1C4..1D0) i label target BB44 [0032] 2 BB39,BB43 1 [1D0..1E7)-> BB46 ( cond ) i label target BB45 [0033] 1 BB44 1 [1E7..1EE)-> BB47 (always) i BB46 [0034] 1 BB44 1 [1EE..1F2) i label target BB47 [0035] 2 BB45,BB46 1 [1F2..202) (return) i label target BB48 [0054] 0 1 [???..???) (return) keep internal target ----------------------------------------------------------------------------------------------------------------------------------------- Removing unconditional jump to next block (BB02 -> BB03) (converted BB02 to fall-through) Compacting blocks BB02 and BB03: *************** In fgDebugCheckBBlist Compacting blocks BB04 and BB05: *************** In fgDebugCheckBBlist Compacting blocks BB08 and BB09: *************** In fgDebugCheckBBlist Removing unconditional jump to next block (BB14 -> BB15) (converted BB14 to fall-through) Compacting blocks BB14 and BB15: *************** In fgDebugCheckBBlist Removing unconditional jump to next block (BB25 -> BB26) (converted BB25 to fall-through) Compacting blocks BB25 and BB26: *************** In fgDebugCheckBBlist After updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..00D)-> BB04 ( cond ) i label target idxlen BB02 [0001] 1 BB01 1 [00D..017) (return) i BB04 [0002] 1 BB01 1 [017..065)-> BB07 ( cond ) i label target BB06 [0038] 1 BB04 1 [020..021)-> BB08 (always) i BB07 [0039] 1 BB04 1 [020..021) i label target BB08 [0040] 2 BB06,BB07 1 [000..000)-> BB11 ( cond ) i internal label target idxlen BB10 [0043] 1 BB08 1 [000..000)-> BB12 (always) i internal BB11 [0044] 1 BB08 1 [000..000) i internal label target BB12 [0045] 2 BB10,BB11 1 [???..???)-> BB17 ( cond ) i internal label target idxlen BB13 [0003] 1 BB12 1 [065..070)-> BB16 ( cond ) i BB14 [0004] 1 BB13 1 [070..07A) (return) i BB16 [0005] 1 BB13 1 [07A..082) i label target BB17 [0006] 2 BB12,BB16 1 [082..092)-> BB19 ( cond ) i label target BB18 [0007] 1 BB17 1 [092..096)-> BB20 ( cond ) i BB19 [0008] 2 BB17,BB18 1 [096..0A7) (return) i label target BB20 [0009] 1 BB18 1 [0A7..0B0)-> BB22 ( cond ) i label target BB21 [0010] 1 BB20 1 [0B0..0B4)-> BB23 (always) i BB22 [0011] 1 BB20 1 [0B4..0BE) i label target BB23 [0012] 2 BB21,BB22 1 [0BE..0C4)-> BB27 ( cond ) i label target BB24 [0013] 1 BB23 1 [0C4..0D9)-> BB27 ( cond ) i idxlen BB25 [0014] 1 BB24 1 [0D9..0E3) (return) i BB27 [0015] 2 BB23,BB24 1 [0E3..117)-> BB29 ( cond ) i label target BB28 [0016] 1 BB27 1 [117..11A)-> BB30 (always) i BB29 [0017] 1 BB27 1 [11A..11F) i label target BB30 [0018] 2 BB28,BB29 1 [11F..126)-> BB32 ( cond ) i label target BB31 [0019] 1 BB30 1 [126..12F) i BB32 [0020] 2 BB30,BB31 1 [12F..13E)-> BB36 ( cond ) i label target BB33 [0021] 1 BB32 1 [13E..144)-> BB35 ( cond ) i BB34 [0022] 1 BB33 1 [144..155) (return) i BB35 [0023] 1 BB33 1 [155..15C) i label target BB36 [0024] 2 BB32,BB35 1 [15C..167)-> BB38 ( cond ) i label target BB37 [0025] 1 BB36 1 [167..16B)-> BB39 (always) i BB38 [0026] 1 BB36 1 [16B..16F) i label target BB39 [0027] 2 BB37,BB38 1 [16F..1A4)-> BB44 ( cond ) i label target BB40 [0028] 1 BB39 1 [1A4..1AF)-> BB42 ( cond ) i BB41 [0029] 1 BB40 1 [1AF..1C3)-> BB43 (always) i BB42 [0030] 1 BB40 1 [1C3..1C4) i label target BB43 [0031] 2 BB41,BB42 1 [1C4..1D0) i label target BB44 [0032] 2 BB39,BB43 1 [1D0..1E7)-> BB46 ( cond ) i label target BB45 [0033] 1 BB44 1 [1E7..1EE)-> BB47 (always) i BB46 [0034] 1 BB44 1 [1EE..1F2) i label target BB47 [0035] 2 BB45,BB46 1 [1F2..202) (return) i label target BB48 [0054] 0 1 [???..???) (return) keep internal target ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** In fgDebugCheckBBlist *************** Finishing PHASE Update flow graph early pass *************** Starting PHASE Morph - Promote Structs *************** In fgResetImplicitByRefRefCount() *************** In fgPromoteStructs() lvaTable before fgPromoteStructs ; Initial local variable assignments ; ; V00 arg0 struct ld-addr-op ; V01 arg1 ref class-hnd ; V02 arg2 byref ; V03 loc0 int ; V04 loc1 int ; V05 loc2 int ; V06 loc3 int ; V07 loc4 int ; V08 loc5 int ; V09 loc6 int ; V10 loc7 int ; V11 loc8 struct ld-addr-op ; V12 loc9 ref ld-addr-op class-hnd ; V13 loc10 int ; V14 loc11 int ; V15 loc12 struct ld-addr-op ; V16 loc13 struct ld-addr-op ; V17 loc14 int ; V18 loc15 int ; V19 loc16 int ; V20 loc17 int ; V21 loc18 int ; V22 loc19 int ; V23 loc20 struct ld-addr-op ; V24 loc21 long ; V25 loc22 bool ; V26 loc23 int ; V27 loc24 long ; V28 loc25 int ; V29 loc26 int ; V30 OutArgs lclBlk "OutgoingArgSpace" ; V31 tmp1 int "dup spill" ; V32 tmp2 int ; V33 tmp3 int ; V34 tmp4 int ; V35 tmp5 struct "struct address for call/obj" ; V36 tmp6 int ; V37 tmp7 int ; V38 tmp8 long "impAppendStmt" ; V39 tmp9 int "Inline return value spill temp" ; V40 tmp10 int "Inlining Arg" ; V41 tmp11 int "Inline return value spill temp" ; V42 tmp12 int "Inlining Arg" ; V43 tmp13 int "Inline return value spill temp" ; V44 tmp14 struct "Inlining Arg" ; V45 tmp15 ref ld-addr-op class-hnd "Inline ldloca(s) first use temp" ; V46 tmp16 int "Inline return value spill temp" ; V47 tmp17 struct "Inlining Arg" ; V48 tmp18 ref ld-addr-op class-hnd "Inline ldloca(s) first use temp" ; V49 tmp19 struct ld-addr-op "Inlining Arg" ; V50 tmp20 struct "Inlining Arg" ; V51 tmp21 int "Single return block return value" Promoting struct local V00 (DecimalFloatingPointString): lvaGrabTemp returning 52 (V52 tmp22) (a long lifetime temp) called for field V00.Mantissa (fldOffset=0x0). lvaGrabTemp returning 53 (V53 tmp23) (a long lifetime temp) called for field V00.Exponent (fldOffset=0x8). Promoting struct local V11 (System.Numerics.BigInteger): lvaGrabTemp returning 54 (V54 tmp24) (a long lifetime temp) called for field V11._bits (fldOffset=0x0). lvaGrabTemp returning 55 (V55 tmp25) (a long lifetime temp) called for field V11._sign (fldOffset=0x8). Promoting struct local V15 (System.Numerics.BigInteger): lvaGrabTemp returning 56 (V56 tmp26) (a long lifetime temp) called for field V15._bits (fldOffset=0x0). lvaGrabTemp returning 57 (V57 tmp27) (a long lifetime temp) called for field V15._sign (fldOffset=0x8). Promoting struct local V16 (System.Numerics.BigInteger): lvaGrabTemp returning 58 (V58 tmp28) (a long lifetime temp) called for field V16._bits (fldOffset=0x0). lvaGrabTemp returning 59 (V59 tmp29) (a long lifetime temp) called for field V16._sign (fldOffset=0x8). Promoting struct local V23 (System.Numerics.BigInteger): lvaGrabTemp returning 60 (V60 tmp30) (a long lifetime temp) called for field V23._bits (fldOffset=0x0). lvaGrabTemp returning 61 (V61 tmp31) (a long lifetime temp) called for field V23._sign (fldOffset=0x8). Promoting struct local V35 (System.Numerics.BigInteger): lvaGrabTemp returning 62 (V62 tmp32) (a long lifetime temp) called for field V35._bits (fldOffset=0x0). lvaGrabTemp returning 63 (V63 tmp33) (a long lifetime temp) called for field V35._sign (fldOffset=0x8). Promoting struct local V44 (System.Numerics.BigInteger): lvaGrabTemp returning 64 (V64 tmp34) (a long lifetime temp) called for field V44._bits (fldOffset=0x0). lvaGrabTemp returning 65 (V65 tmp35) (a long lifetime temp) called for field V44._sign (fldOffset=0x8). Promoting struct local V47 (System.Numerics.BigInteger): lvaGrabTemp returning 66 (V66 tmp36) (a long lifetime temp) called for field V47._bits (fldOffset=0x0). lvaGrabTemp returning 67 (V67 tmp37) (a long lifetime temp) called for field V47._sign (fldOffset=0x8). Promoting struct local V49 (System.Numerics.BigInteger): lvaGrabTemp returning 68 (V68 tmp38) (a long lifetime temp) called for field V49._bits (fldOffset=0x0). lvaGrabTemp returning 69 (V69 tmp39) (a long lifetime temp) called for field V49._sign (fldOffset=0x8). Promoting struct local V50 (System.Numerics.BigInteger): lvaGrabTemp returning 70 (V70 tmp40) (a long lifetime temp) called for field V50._bits (fldOffset=0x0). lvaGrabTemp returning 71 (V71 tmp41) (a long lifetime temp) called for field V50._sign (fldOffset=0x8). lvaTable after fgPromoteStructs ; Initial local variable assignments ; ; V00 arg0 struct ld-addr-op ; V01 arg1 ref class-hnd ; V02 arg2 byref ; V03 loc0 int ; V04 loc1 int ; V05 loc2 int ; V06 loc3 int ; V07 loc4 int ; V08 loc5 int ; V09 loc6 int ; V10 loc7 int ; V11 loc8 struct ld-addr-op ; V12 loc9 ref ld-addr-op class-hnd ; V13 loc10 int ; V14 loc11 int ; V15 loc12 struct ld-addr-op ; V16 loc13 struct ld-addr-op ; V17 loc14 int ; V18 loc15 int ; V19 loc16 int ; V20 loc17 int ; V21 loc18 int ; V22 loc19 int ; V23 loc20 struct ld-addr-op ; V24 loc21 long ; V25 loc22 bool ; V26 loc23 int ; V27 loc24 long ; V28 loc25 int ; V29 loc26 int ; V30 OutArgs lclBlk "OutgoingArgSpace" ; V31 tmp1 int "dup spill" ; V32 tmp2 int ; V33 tmp3 int ; V34 tmp4 int ; V35 tmp5 struct "struct address for call/obj" ; V36 tmp6 int ; V37 tmp7 int ; V38 tmp8 long "impAppendStmt" ; V39 tmp9 int "Inline return value spill temp" ; V40 tmp10 int "Inlining Arg" ; V41 tmp11 int "Inline return value spill temp" ; V42 tmp12 int "Inlining Arg" ; V43 tmp13 int "Inline return value spill temp" ; V44 tmp14 struct "Inlining Arg" ; V45 tmp15 ref ld-addr-op class-hnd "Inline ldloca(s) first use temp" ; V46 tmp16 int "Inline return value spill temp" ; V47 tmp17 struct "Inlining Arg" ; V48 tmp18 ref ld-addr-op class-hnd "Inline ldloca(s) first use temp" ; V49 tmp19 struct ld-addr-op "Inlining Arg" ; V50 tmp20 struct "Inlining Arg" ; V51 tmp21 int "Single return block return value" ; V52 tmp22 ref V00.Mantissa(offs=0x00) P-INDEP "field V00.Mantissa (fldOffset=0x0)" ; V53 tmp23 int V00.Exponent(offs=0x08) P-INDEP "field V00.Exponent (fldOffset=0x8)" ; V54 tmp24 ref V11._bits(offs=0x00) P-INDEP "field V11._bits (fldOffset=0x0)" ; V55 tmp25 int V11._sign(offs=0x08) P-INDEP "field V11._sign (fldOffset=0x8)" ; V56 tmp26 ref V15._bits(offs=0x00) P-INDEP "field V15._bits (fldOffset=0x0)" ; V57 tmp27 int V15._sign(offs=0x08) P-INDEP "field V15._sign (fldOffset=0x8)" ; V58 tmp28 ref V16._bits(offs=0x00) P-INDEP "field V16._bits (fldOffset=0x0)" ; V59 tmp29 int V16._sign(offs=0x08) P-INDEP "field V16._sign (fldOffset=0x8)" ; V60 tmp30 ref V23._bits(offs=0x00) P-INDEP "field V23._bits (fldOffset=0x0)" ; V61 tmp31 int V23._sign(offs=0x08) P-INDEP "field V23._sign (fldOffset=0x8)" ; V62 tmp32 ref V35._bits(offs=0x00) P-INDEP "field V35._bits (fldOffset=0x0)" ; V63 tmp33 int V35._sign(offs=0x08) P-INDEP "field V35._sign (fldOffset=0x8)" ; V64 tmp34 ref V44._bits(offs=0x00) P-INDEP "field V44._bits (fldOffset=0x0)" ; V65 tmp35 int V44._sign(offs=0x08) P-INDEP "field V44._sign (fldOffset=0x8)" ; V66 tmp36 ref V47._bits(offs=0x00) P-INDEP "field V47._bits (fldOffset=0x0)" ; V67 tmp37 int V47._sign(offs=0x08) P-INDEP "field V47._sign (fldOffset=0x8)" ; V68 tmp38 ref V49._bits(offs=0x00) P-INDEP "field V49._bits (fldOffset=0x0)" ; V69 tmp39 int V49._sign(offs=0x08) P-INDEP "field V49._sign (fldOffset=0x8)" ; V70 tmp40 ref V50._bits(offs=0x00) P-INDEP "field V50._bits (fldOffset=0x0)" ; V71 tmp41 int V50._sign(offs=0x08) P-INDEP "field V50._sign (fldOffset=0x8)" *************** Finishing PHASE Morph - Promote Structs *************** Starting PHASE Morph - Structs/AddrExp *************** In fgMarkAddressExposedLocals() LocalAddressVisitor visiting statement: STMT00000 (IL 0x000...0x00B) [000006] ---XG------- * JTRUE void [000005] ---XG------- \--* NE int [000003] ---XG------- +--* ARR_LENGTH int [000002] ----G------- | \--* FIELD ref Mantissa [000001] ------------ | \--* ADDR byref [000000] -------N---- | \--* LCL_VAR struct(P) V00 arg0 | \--* ref V00.Mantissa (offs=0x00) -> V52 tmp22 | \--* int V00.Exponent (offs=0x08) -> V53 tmp23 [000004] ------------ \--* CNS_INT int 0 Replacing the field in promoted struct with local var V52 LocalAddressVisitor incrementing ref count from 0 to 1 for implict by-ref V00 LocalAddressVisitor modified statement: STMT00000 (IL 0x000...0x00B) [000006] ---XG------- * JTRUE void [000005] ---XG------- \--* NE int [000003] ---XG------- +--* ARR_LENGTH int [000002] ------------ | \--* LCL_VAR ref V52 tmp22 [000004] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00087 (IL 0x00D...0x014) [000403] -ACXG------- * ASG long [000402] *------N---- +--* IND long [000399] ------------ | \--* LCL_VAR byref V02 arg2 [000401] --C-G------- \--* CALLV ind long FloatingPointType.get_Zero [000400] ------------ this in rcx \--* LCL_VAR ref V01 arg1 LocalAddressVisitor visiting statement: STMT00107 (IL ???... ???) [000520] ------------ * RETURN int [000404] ------------ \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00002 (IL ???... ???) [000013] -AC--------- * ASG int [000012] D------N---- +--* LCL_VAR int V03 loc0 [000011] --C--------- \--* ADD int [000409] --C-G------- +--* CAST int <- ushort <- int [000408] --C-G------- | \--* ADD int [000406] --C-G------- | +--* CALLV ind int FloatingPointType.get_DenormalMantissaBits [000007] ------------ this in rcx | | \--* LCL_VAR ref V01 arg1 [000407] ------------ | \--* CNS_INT int 1 [000010] ------------ \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00092 (IL 0x020... ???) [000424] -A--G------- * ASG int [000423] D------N---- +--* LCL_VAR int V40 tmp10 [000017] ----G------- \--* FIELD int Exponent [000016] ------------ \--* ADDR byref [000015] -------N---- \--* LCL_VAR struct(P) V00 arg0 \--* ref V00.Mantissa (offs=0x00) -> V52 tmp22 \--* int V00.Exponent (offs=0x08) -> V53 tmp23 Replacing the field in promoted struct with local var V53 LocalAddressVisitor incrementing ref count from 1 to 2 for implict by-ref V00 LocalAddressVisitor modified statement: STMT00092 (IL 0x020... ???) [000424] -A--G------- * ASG int [000423] D------N---- +--* LCL_VAR int V40 tmp10 [000017] ------------ \--* LCL_VAR int V53 tmp23 LocalAddressVisitor visiting statement: STMT00089 (IL 0x020... ???) [000414] ------------ * JTRUE void [000413] ------------ \--* GE int [000411] ------------ +--* CNS_INT int 0 [000412] ------------ \--* LCL_VAR int V40 tmp10 LocalAddressVisitor visiting statement: STMT00091 (IL 0x020... ???) [000421] -A---------- * ASG int [000420] D------N---- +--* LCL_VAR int V39 tmp9 [000419] ------------ \--* LCL_VAR int V40 tmp10 LocalAddressVisitor visiting statement: STMT00090 (IL 0x020... ???) [000417] -A---------- * ASG int [000416] D------N---- +--* LCL_VAR int V39 tmp9 [000415] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00004 (IL ???... ???) [000021] -AC--------- * ASG int [000020] D------N---- +--* LCL_VAR int V31 tmp1 [000422] ------------ \--* LCL_VAR int V39 tmp9 LocalAddressVisitor visiting statement: STMT00096 (IL ???... ???) [000443] -A-XG------- * ASG int [000442] D------N---- +--* LCL_VAR int V42 tmp12 [000429] ---XG------- \--* ARR_LENGTH int [000428] ----G------- \--* FIELD ref Mantissa [000426] ------------ \--* ADDR byref [000427] -------N---- \--* LCL_VAR struct(P) V00 arg0 \--* ref V00.Mantissa (offs=0x00) -> V52 tmp22 \--* int V00.Exponent (offs=0x08) -> V53 tmp23 Replacing the field in promoted struct with local var V52 LocalAddressVisitor incrementing ref count from 2 to 3 for implict by-ref V00 LocalAddressVisitor modified statement: STMT00096 (IL ???... ???) [000443] -A-XG------- * ASG int [000442] D------N---- +--* LCL_VAR int V42 tmp12 [000429] ---XG------- \--* ARR_LENGTH int [000428] ------------ \--* LCL_VAR ref V52 tmp22 LocalAddressVisitor visiting statement: STMT00093 (IL ???... ???) [000433] ------------ * JTRUE void [000432] N--------U-- \--* LE int [000023] ------------ +--* LCL_VAR int V31 tmp1 [000431] ------------ \--* LCL_VAR int V42 tmp12 LocalAddressVisitor visiting statement: STMT00095 (IL ???... ???) [000440] -A---------- * ASG int [000439] D------N---- +--* LCL_VAR int V41 tmp11 [000438] ------------ \--* LCL_VAR int V42 tmp12 LocalAddressVisitor visiting statement: STMT00094 (IL ???... ???) [000436] -A---------- * ASG int [000435] D------N---- +--* LCL_VAR int V41 tmp11 [000434] ------------ \--* LCL_VAR int V31 tmp1 LocalAddressVisitor visiting statement: STMT00007 (IL ???... ???) [000031] -AC--------- * ASG int [000030] D------N---- +--* LCL_VAR int V04 loc1 [000441] ------------ \--* LCL_VAR int V41 tmp11 LocalAddressVisitor visiting statement: STMT00008 (IL ???...0x03C) [000035] -A---------- * ASG int [000034] D------N---- +--* LCL_VAR int V05 loc2 [000033] ------------ \--* SUB int [000022] ------------ +--* LCL_VAR int V31 tmp1 [000032] ------------ \--* LCL_VAR int V04 loc1 LocalAddressVisitor visiting statement: STMT00009 (IL 0x03D...0x03E) [000038] -A---------- * ASG int [000037] D------N---- +--* LCL_VAR int V06 loc3 [000036] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00010 (IL 0x03F...0x040) [000041] -A---------- * ASG int [000040] D------N---- +--* LCL_VAR int V07 loc4 [000039] ------------ \--* LCL_VAR int V04 loc1 LocalAddressVisitor visiting statement: STMT00011 (IL 0x042...0x044) [000044] -A---------- * ASG int [000043] D------N---- +--* LCL_VAR int V08 loc5 [000042] ------------ \--* LCL_VAR int V07 loc4 LocalAddressVisitor visiting statement: STMT00013 (IL ???... ???) [000050] -AC--------- * ASG int [000049] D------N---- +--* LCL_VAR int V09 loc6 [000448] ---XG------- \--* ARR_LENGTH int [000447] ----G------- \--* FIELD ref Mantissa [000445] ------------ \--* ADDR byref [000446] -------N---- \--* LCL_VAR struct(P) V00 arg0 \--* ref V00.Mantissa (offs=0x00) -> V52 tmp22 \--* int V00.Exponent (offs=0x08) -> V53 tmp23 Replacing the field in promoted struct with local var V52 LocalAddressVisitor incrementing ref count from 3 to 4 for implict by-ref V00 LocalAddressVisitor modified statement: STMT00013 (IL ???... ???) [000050] -AC--------- * ASG int [000049] D------N---- +--* LCL_VAR int V09 loc6 [000448] ---XG------- \--* ARR_LENGTH int [000447] ------------ \--* LCL_VAR ref V52 tmp22 LocalAddressVisitor visiting statement: STMT00014 (IL 0x04F...0x054) [000055] -A---------- * ASG int [000054] D------N---- +--* LCL_VAR int V10 loc7 [000053] ------------ \--* SUB int [000051] ------------ +--* LCL_VAR int V09 loc6 [000052] ------------ \--* LCL_VAR int V08 loc5 LocalAddressVisitor visiting statement: STMT00016 (IL ???... ???) [000059] S-C-G------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger [000064] ------------ arg0 +--* ADDR byref [000063] -------N---- | \--* LCL_VAR struct(P) V11 loc8 | \--* ref V11._bits (offs=0x00) -> V54 tmp24 | \--* int V11._sign (offs=0x08) -> V55 tmp25 [000061] n----------- arg1 +--* OBJ struct [000060] ------------ | \--* ADDR byref [000056] -------N---- | \--* LCL_VAR struct(P) V00 arg0 | \--* ref V00.Mantissa (offs=0x00) -> V52 tmp22 | \--* int V00.Exponent (offs=0x08) -> V53 tmp23 [000057] ------------ arg2 +--* LCL_VAR int V06 loc3 [000058] ------------ arg3 \--* LCL_VAR int V07 loc4 LocalAddressVisitor incrementing ref count from 4 to 5 for implict by-ref V00 LocalAddressVisitor incrementing weighted ref count from 0 to 1 for implict by-ref V00 arg passed to call Local V54 should not be enregistered because: it is address exposed Local V55 should not be enregistered because: it is address exposed Local V11 should not be enregistered because: it is address exposed LocalAddressVisitor visiting statement: STMT00017 (IL 0x061...0x063) [000068] ------------ * JTRUE void [000067] N--------U-- \--* LE int [000065] ------------ +--* LCL_VAR int V05 loc2 [000066] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00083 (IL ???... ???) [000387] --C--------- * JTRUE void [000386] --C--------- \--* LE int [000381] ---------U-- +--* CAST long <- ulong <- uint [000380] ------------ | \--* LCL_VAR int V05 loc2 [000385] --C--------- \--* CAST long <- int [000383] --C-G------- \--* CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent [000382] ------------ this in rcx \--* LCL_VAR ref V01 arg1 LocalAddressVisitor visiting statement: STMT00085 (IL 0x070...0x077) [000396] -ACXG------- * ASG long [000395] *------N---- +--* IND long [000392] ------------ | \--* LCL_VAR byref V02 arg2 [000394] --C-G------- \--* CALLV ind long FloatingPointType.get_Infinity [000393] ------------ this in rcx \--* LCL_VAR ref V01 arg1 LocalAddressVisitor visiting statement: STMT00108 (IL ???... ???) [000521] ------------ * RETURN int [000397] ------------ \--* CNS_INT int 3 LocalAddressVisitor visiting statement: STMT00084 (IL 0x07A...0x07D) [000391] --C-G------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen [000389] ------------ arg0 +--* ADDR byref [000388] -------N---- | \--* LCL_VAR struct(AX)(P) V11 loc8 | \--* ref V11._bits (offs=0x00) -> V54 tmp24 | \--* int V11._sign (offs=0x08) -> V55 tmp25 [000390] ------------ arg1 \--* LCL_VAR int V05 loc2 Local V54 should not be enregistered because: it is address exposed Local V55 should not be enregistered because: it is address exposed Local V11 should not be enregistered because: it is address exposed LocalAddressVisitor visiting statement: STMT00019 (IL ???... ???) [000077] -AC--------- * ASG int [000076] D------N---- +--* LCL_VAR int V13 loc10 [000072] --C-G------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits [000074] n----------- arg0 +--* OBJ struct [000073] ------------ | \--* ADDR byref [000069] -------N---- | \--* LCL_VAR struct(AX)(P) V11 loc8 | \--* ref V11._bits (offs=0x00) -> V54 tmp24 | \--* int V11._sign (offs=0x08) -> V55 tmp25 [000071] ------------ arg1 \--* ADDR byref [000070] -------N---- \--* LCL_VAR ref V12 loc9 Local V12 should not be enregistered because: it is address exposed LocalAddressVisitor modified statement: STMT00019 (IL ???... ???) [000077] -AC--------- * ASG int [000076] D------N---- +--* LCL_VAR int V13 loc10 [000072] --C-G------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits [000074] n----------- arg0 +--* OBJ struct [000073] ------------ | \--* ADDR byref [000069] -------N---- | \--* LCL_VAR struct(AX)(P) V11 loc8 | \--* ref V11._bits (offs=0x00) -> V54 tmp24 | \--* int V11._sign (offs=0x08) -> V55 tmp25 [000071] ------------ arg1 \--* LCL_VAR_ADDR byref V12 loc9 LocalAddressVisitor visiting statement: STMT00020 (IL 0x08D...0x090) [000081] ------------ * JTRUE void [000080] N--------U-- \--* GE int [000078] ------------ +--* LCL_VAR int V13 loc10 [000079] ------------ \--* LCL_VAR int V03 loc0 LocalAddressVisitor visiting statement: STMT00022 (IL 0x092...0x094) [000094] ------------ * JTRUE void [000093] ------------ \--* NE int [000091] ------------ +--* LCL_VAR int V10 loc7 [000092] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00021 (IL 0x096...0x0A6) [000090] --C-G------- * RETURN int [000089] --C-G------- \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits [000082] ------------ arg0 +--* LCL_VAR ref (AX) V12 loc9 [000083] ------------ arg1 +--* LCL_VAR int V13 loc10 [000086] N--------U-- arg2 +--* GT int [000084] ------------ | +--* LCL_VAR int V10 loc7 [000085] ------------ | \--* CNS_INT int 0 [000087] ------------ arg3 +--* LCL_VAR ref V01 arg1 [000088] ------------ arg4 \--* LCL_VAR byref V02 arg2 LocalAddressVisitor visiting statement: STMT00023 (IL 0x0A7...0x0AE) [000100] ----G------- * JTRUE void [000099] ----G------- \--* LT int [000097] ----G------- +--* FIELD int Exponent [000096] ------------ | \--* ADDR byref [000095] -------N---- | \--* LCL_VAR struct(P) V00 arg0 | \--* ref V00.Mantissa (offs=0x00) -> V52 tmp22 | \--* int V00.Exponent (offs=0x08) -> V53 tmp23 [000098] ------------ \--* CNS_INT int 0 Replacing the field in promoted struct with local var V53 LocalAddressVisitor incrementing ref count from 5 to 6 for implict by-ref V00 LocalAddressVisitor modified statement: STMT00023 (IL 0x0A7...0x0AE) [000100] ----G------- * JTRUE void [000099] ----G------- \--* LT int [000097] ------------ +--* LCL_VAR int V53 tmp23 [000098] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00081 (IL 0x0B0...0x0B2) [000378] -A---------- * ASG int [000377] D------N---- +--* LCL_VAR int V32 tmp2 [000376] ------------ \--* LCL_VAR int V10 loc7 LocalAddressVisitor visiting statement: STMT00024 (IL 0x0B4...0x0BD) [000108] -A--G------- * ASG int [000107] D------N---- +--* LCL_VAR int V32 tmp2 [000106] ----G------- \--* ADD int [000101] ------------ +--* LCL_VAR int V10 loc7 [000105] ----G------- \--* NEG int [000104] ----G------- \--* FIELD int Exponent [000103] ------------ \--* ADDR byref [000102] -------N---- \--* LCL_VAR struct(P) V00 arg0 \--* ref V00.Mantissa (offs=0x00) -> V52 tmp22 \--* int V00.Exponent (offs=0x08) -> V53 tmp23 Replacing the field in promoted struct with local var V53 LocalAddressVisitor incrementing ref count from 6 to 7 for implict by-ref V00 LocalAddressVisitor modified statement: STMT00024 (IL 0x0B4...0x0BD) [000108] -A--G------- * ASG int [000107] D------N---- +--* LCL_VAR int V32 tmp2 [000106] ----G------- \--* ADD int [000101] ------------ +--* LCL_VAR int V10 loc7 [000105] ----G------- \--* NEG int [000104] ------------ \--* LCL_VAR int V53 tmp23 LocalAddressVisitor visiting statement: STMT00025 (IL ???...0x0BE) [000112] -A---------- * ASG int [000111] D------N---- +--* LCL_VAR int V14 loc11 [000110] ------------ \--* LCL_VAR int V32 tmp2 LocalAddressVisitor visiting statement: STMT00026 (IL 0x0C0...0x0C2) [000116] ------------ * JTRUE void [000115] ------------ \--* NE int [000113] ------------ +--* LCL_VAR int V13 loc10 [000114] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00077 (IL ???... ???) [000363] -AC--------- * ASG long [000362] D------N---- +--* LCL_VAR long V38 tmp8 [000359] --C--------- \--* SUB long [000353] ---------U-- +--* CAST long <- ulong <- uint [000352] ------------ | \--* LCL_VAR int V14 loc11 [000358] --C--------- \--* CAST long <- int [000456] ---XG------- \--* ARR_LENGTH int [000455] ----G------- \--* FIELD ref Mantissa [000453] ------------ \--* ADDR byref [000454] -------N---- \--* LCL_VAR struct(P) V00 arg0 \--* ref V00.Mantissa (offs=0x00) -> V52 tmp22 \--* int V00.Exponent (offs=0x08) -> V53 tmp23 Replacing the field in promoted struct with local var V52 LocalAddressVisitor incrementing ref count from 7 to 8 for implict by-ref V00 LocalAddressVisitor modified statement: STMT00077 (IL ???... ???) [000363] -AC--------- * ASG long [000362] D------N---- +--* LCL_VAR long V38 tmp8 [000359] --C--------- \--* SUB long [000353] ---------U-- +--* CAST long <- ulong <- uint [000352] ------------ | \--* LCL_VAR int V14 loc11 [000358] --C--------- \--* CAST long <- int [000456] ---XG------- \--* ARR_LENGTH int [000455] ------------ \--* LCL_VAR ref V52 tmp22 LocalAddressVisitor visiting statement: STMT00078 (IL ???... ???) [000368] --C--------- * JTRUE void [000367] --C--------- \--* LE int [000364] ------------ +--* LCL_VAR long V38 tmp8 [000366] --C--------- \--* CAST long <- int [000361] --C-G------- \--* CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent [000360] ------------ this in rcx \--* LCL_VAR ref V01 arg1 LocalAddressVisitor visiting statement: STMT00079 (IL 0x0D9...0x0E0) [000373] -ACXG------- * ASG long [000372] *------N---- +--* IND long [000369] ------------ | \--* LCL_VAR byref V02 arg2 [000371] --C-G------- \--* CALLV ind long FloatingPointType.get_Zero [000370] ------------ this in rcx \--* LCL_VAR ref V01 arg1 LocalAddressVisitor visiting statement: STMT00110 (IL ???... ???) [000524] ------------ * RETURN int [000374] ------------ \--* CNS_INT int 2 LocalAddressVisitor visiting statement: STMT00028 (IL ???... ???) [000120] S-C-G------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger [000125] ------------ arg0 +--* ADDR byref [000124] -------N---- | \--* LCL_VAR struct(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 [000122] n----------- arg1 +--* OBJ struct [000121] ------------ | \--* ADDR byref [000117] -------N---- | \--* LCL_VAR struct(P) V00 arg0 | \--* ref V00.Mantissa (offs=0x00) -> V52 tmp22 | \--* int V00.Exponent (offs=0x08) -> V53 tmp23 [000118] ------------ arg2 +--* LCL_VAR int V08 loc5 [000119] ------------ arg3 \--* LCL_VAR int V09 loc6 LocalAddressVisitor incrementing ref count from 8 to 9 for implict by-ref V00 LocalAddressVisitor incrementing weighted ref count from 1 to 2 for implict by-ref V00 arg passed to call Local V56 should not be enregistered because: it is address exposed Local V57 should not be enregistered because: it is address exposed Local V15 should not be enregistered because: it is address exposed LocalAddressVisitor visiting statement: STMT00029 (IL 0x0EF...0x0F4) [000133] H-CXG------- * CALL help long HELPER.CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE [000131] ------------ arg0 +--* CNS_INT long 0x7ff815262aa0 [000132] ------------ arg1 \--* CNS_INT int 173 LocalAddressVisitor visiting statement: STMT00030 (IL ???... ???) [000137] -A--G------- * ASG struct (copy) [000135] D------N---- +--* LCL_VAR struct(P) V16 loc13 +--* ref V16._bits (offs=0x00) -> V58 tmp28 +--* int V16._sign (offs=0x08) -> V59 tmp29 [000129] ----G------- \--* OBJ struct [000128] ----G------- \--* ADD byref [000126] ----G------- +--* FIELD ref BigOne [000127] ------------ \--* CNS_INT long 8 Fseq[#FirstElem] LocalAddressVisitor visiting statement: STMT00031 (IL 0x0F6...0x106) [000141] --C-G------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen [000139] ------------ arg0 +--* ADDR byref [000138] -------N---- | \--* LCL_VAR struct(P) V16 loc13 | \--* ref V16._bits (offs=0x00) -> V58 tmp28 | \--* int V16._sign (offs=0x08) -> V59 tmp29 [000140] ------------ arg1 \--* LCL_VAR int V14 loc11 Local V58 should not be enregistered because: it is address exposed Local V59 should not be enregistered because: it is address exposed Local V16 should not be enregistered because: it is address exposed LocalAddressVisitor visiting statement: STMT00099 (IL 0x0FF... ???) [000472] -A---------- * ASG struct (copy) [000470] D------N---- +--* LCL_VAR struct(P) V44 tmp14 +--* ref V44._bits (offs=0x00) -> V64 tmp34 +--* int V44._sign (offs=0x08) -> V65 tmp35 [000145] n----------- \--* OBJ struct [000144] ------------ \--* ADDR byref [000142] -------N---- \--* LCL_VAR struct(AX)(P) V15 loc12 \--* ref V15._bits (offs=0x00) -> V56 tmp26 \--* int V15._sign (offs=0x08) -> V57 tmp27 LocalAddressVisitor visiting statement: STMT00098 (IL 0x0FF... ???) [000468] -AC--------- * ASG int [000467] D------N---- +--* LCL_VAR int V43 tmp13 [000463] --C-G------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits [000465] n----------- arg0 +--* OBJ struct [000464] ------------ | \--* ADDR byref [000460] -------N---- | \--* LCL_VAR struct(P) V44 tmp14 | \--* ref V44._bits (offs=0x00) -> V64 tmp34 | \--* int V44._sign (offs=0x08) -> V65 tmp35 [000462] ------------ arg1 \--* ADDR byref [000461] -------N---- \--* LCL_VAR ref V45 tmp15 Local V45 should not be enregistered because: it is address exposed LocalAddressVisitor modified statement: STMT00098 (IL 0x0FF... ???) [000468] -AC--------- * ASG int [000467] D------N---- +--* LCL_VAR int V43 tmp13 [000463] --C-G------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits [000465] n----------- arg0 +--* OBJ struct [000464] ------------ | \--* ADDR byref [000460] -------N---- | \--* LCL_VAR struct(P) V44 tmp14 | \--* ref V44._bits (offs=0x00) -> V64 tmp34 | \--* int V44._sign (offs=0x08) -> V65 tmp35 [000462] ------------ arg1 \--* LCL_VAR_ADDR byref V45 tmp15 LocalAddressVisitor visiting statement: STMT00100 (IL 0x0FF... ???) [000475] -A---------- * ASG ref [000474] D------N---- +--* LCL_VAR ref (AX) V45 tmp15 [000473] ------------ \--* CNS_INT ref null LocalAddressVisitor visiting statement: STMT00033 (IL ???... ???) [000148] -AC--------- * ASG int [000147] D------N---- +--* LCL_VAR int V17 loc14 [000469] ------------ \--* LCL_VAR int V43 tmp13 LocalAddressVisitor visiting statement: STMT00103 (IL 0x108... ???) [000490] -A---------- * ASG struct (copy) [000488] D------N---- +--* LCL_VAR struct(P) V47 tmp17 +--* ref V47._bits (offs=0x00) -> V66 tmp36 +--* int V47._sign (offs=0x08) -> V67 tmp37 [000152] n----------- \--* OBJ struct [000151] ------------ \--* ADDR byref [000149] -------N---- \--* LCL_VAR struct(AX)(P) V16 loc13 \--* ref V16._bits (offs=0x00) -> V58 tmp28 \--* int V16._sign (offs=0x08) -> V59 tmp29 LocalAddressVisitor visiting statement: STMT00102 (IL 0x108... ???) [000486] -AC--------- * ASG int [000485] D------N---- +--* LCL_VAR int V46 tmp16 [000481] --C-G------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits [000483] n----------- arg0 +--* OBJ struct [000482] ------------ | \--* ADDR byref [000478] -------N---- | \--* LCL_VAR struct(P) V47 tmp17 | \--* ref V47._bits (offs=0x00) -> V66 tmp36 | \--* int V47._sign (offs=0x08) -> V67 tmp37 [000480] ------------ arg1 \--* ADDR byref [000479] -------N---- \--* LCL_VAR ref V48 tmp18 Local V48 should not be enregistered because: it is address exposed LocalAddressVisitor modified statement: STMT00102 (IL 0x108... ???) [000486] -AC--------- * ASG int [000485] D------N---- +--* LCL_VAR int V46 tmp16 [000481] --C-G------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits [000483] n----------- arg0 +--* OBJ struct [000482] ------------ | \--* ADDR byref [000478] -------N---- | \--* LCL_VAR struct(P) V47 tmp17 | \--* ref V47._bits (offs=0x00) -> V66 tmp36 | \--* int V47._sign (offs=0x08) -> V67 tmp37 [000480] ------------ arg1 \--* LCL_VAR_ADDR byref V48 tmp18 LocalAddressVisitor visiting statement: STMT00104 (IL 0x108... ???) [000493] -A---------- * ASG ref [000492] D------N---- +--* LCL_VAR ref (AX) V48 tmp18 [000491] ------------ \--* CNS_INT ref null LocalAddressVisitor visiting statement: STMT00035 (IL ???... ???) [000155] -AC--------- * ASG int [000154] D------N---- +--* LCL_VAR int V18 loc15 [000487] ------------ \--* LCL_VAR int V46 tmp16 LocalAddressVisitor visiting statement: STMT00036 (IL 0x111...0x115) [000159] ------------ * JTRUE void [000158] N--------U-- \--* GT int [000156] ------------ +--* LCL_VAR int V18 loc15 [000157] ------------ \--* LCL_VAR int V17 loc14 LocalAddressVisitor visiting statement: STMT00074 (IL 0x117...0x118) [000350] -A---------- * ASG int [000349] D------N---- +--* LCL_VAR int V33 tmp3 [000348] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00037 (IL 0x11A...0x11E) [000164] -A---------- * ASG int [000163] D------N---- +--* LCL_VAR int V33 tmp3 [000162] ------------ \--* SUB int [000160] ------------ +--* LCL_VAR int V18 loc15 [000161] ------------ \--* LCL_VAR int V17 loc14 LocalAddressVisitor visiting statement: STMT00038 (IL ???...0x11F) [000168] -A---------- * ASG int [000167] D------N---- +--* LCL_VAR int V19 loc16 [000166] ------------ \--* LCL_VAR int V33 tmp3 LocalAddressVisitor visiting statement: STMT00039 (IL 0x121...0x124) [000172] ------------ * JTRUE void [000171] N--------U-- \--* LE int [000169] ------------ +--* LCL_VAR int V19 loc16 [000170] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00073 (IL 0x126...0x12A) [000347] --C-G------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft [000345] ------------ arg0 +--* ADDR byref [000344] -------N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 [000346] ------------ arg1 \--* LCL_VAR int V19 loc16 Local V56 should not be enregistered because: it is address exposed Local V57 should not be enregistered because: it is address exposed Local V15 should not be enregistered because: it is address exposed LocalAddressVisitor visiting statement: STMT00040 (IL 0x12F...0x133) [000177] -A---------- * ASG int [000176] D------N---- +--* LCL_VAR int V20 loc17 [000175] ------------ \--* SUB int [000173] ------------ +--* LCL_VAR int V03 loc0 [000174] ------------ \--* LCL_VAR int V13 loc10 LocalAddressVisitor visiting statement: STMT00041 (IL 0x135...0x137) [000180] -A---------- * ASG int [000179] D------N---- +--* LCL_VAR int V21 loc18 [000178] ------------ \--* LCL_VAR int V20 loc17 LocalAddressVisitor visiting statement: STMT00042 (IL 0x139...0x13C) [000184] ------------ * JTRUE void [000183] N--------U-- \--* LE int [000181] ------------ +--* LCL_VAR int V13 loc10 [000182] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00070 (IL 0x13E...0x142) [000329] ------------ * JTRUE void [000328] N--------U-- \--* LE int [000326] ------------ +--* LCL_VAR int V19 loc16 [000327] ------------ \--* LCL_VAR int V21 loc18 LocalAddressVisitor visiting statement: STMT00072 (IL 0x144...0x154) [000343] --C-G------- * RETURN int [000342] --C-G------- \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits [000335] ------------ arg0 +--* LCL_VAR ref (AX) V12 loc9 [000336] ------------ arg1 +--* LCL_VAR int V13 loc10 [000339] N--------U-- arg2 +--* GT int [000337] ------------ | +--* LCL_VAR int V10 loc7 [000338] ------------ | \--* CNS_INT int 0 [000340] ------------ arg3 +--* LCL_VAR ref V01 arg1 [000341] ------------ arg4 \--* LCL_VAR byref V02 arg2 LocalAddressVisitor visiting statement: STMT00071 (IL 0x155...0x15A) [000334] -A---------- * ASG int [000333] D------N---- +--* LCL_VAR int V21 loc18 [000332] ------------ \--* SUB int [000330] ------------ +--* LCL_VAR int V21 loc18 [000331] ------------ \--* LCL_VAR int V19 loc16 LocalAddressVisitor visiting statement: STMT00105 (IL 0x15C... ???) [000506] -A---------- * ASG struct (copy) [000504] D------N---- +--* LCL_VAR struct(P) V49 tmp19 +--* ref V49._bits (offs=0x00) -> V68 tmp38 +--* int V49._sign (offs=0x08) -> V69 tmp39 [000191] n----------- \--* OBJ struct [000190] ------------ \--* ADDR byref [000185] -------N---- \--* LCL_VAR struct(AX)(P) V15 loc12 \--* ref V15._bits (offs=0x00) -> V56 tmp26 \--* int V15._sign (offs=0x08) -> V57 tmp27 LocalAddressVisitor visiting statement: STMT00106 (IL 0x15C... ???) [000509] -A---------- * ASG struct (copy) [000507] D------N---- +--* LCL_VAR struct(P) V50 tmp20 +--* ref V50._bits (offs=0x00) -> V70 tmp40 +--* int V50._sign (offs=0x08) -> V71 tmp41 [000189] n----------- \--* OBJ struct [000188] ------------ \--* ADDR byref [000186] -------N---- \--* LCL_VAR struct(AX)(P) V16 loc13 \--* ref V16._bits (offs=0x00) -> V58 tmp28 \--* int V16._sign (offs=0x08) -> V59 tmp29 LocalAddressVisitor visiting statement: STMT00044 (IL ???... ???) [000195] --C--------- * JTRUE void [000194] --C--------- \--* NE int [000503] --C-G------- +--* LT int [000499] --C-G------- | +--* CALL int System.Numerics.BigInteger.CompareTo [000497] ------------ this in rcx | | +--* ADDR byref [000496] -------N---- | | | \--* LCL_VAR struct(P) V49 tmp19 | | | \--* ref V49._bits (offs=0x00) -> V68 tmp38 | | | \--* int V49._sign (offs=0x08) -> V69 tmp39 [000501] n----------- arg1 | | \--* OBJ struct [000500] ------------ | | \--* ADDR byref [000498] -------N---- | | \--* LCL_VAR struct(P) V50 tmp20 | | \--* ref V50._bits (offs=0x00) -> V70 tmp40 | | \--* int V50._sign (offs=0x08) -> V71 tmp41 [000502] ------------ | \--* CNS_INT int 0 [000193] ------------ \--* CNS_INT int 0 Local V68 should not be enregistered because: it is address exposed Local V69 should not be enregistered because: it is address exposed Local V49 should not be enregistered because: it is address exposed LocalAddressVisitor visiting statement: STMT00069 (IL 0x167...0x169) [000324] -A---------- * ASG int [000323] D------N---- +--* LCL_VAR int V34 tmp4 [000322] ------------ \--* LCL_VAR int V19 loc16 LocalAddressVisitor visiting statement: STMT00045 (IL 0x16B...0x16E) [000200] -A---------- * ASG int [000199] D------N---- +--* LCL_VAR int V34 tmp4 [000198] ------------ \--* ADD int [000196] ------------ +--* LCL_VAR int V19 loc16 [000197] ------------ \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00046 (IL ???...0x16F) [000204] -A---------- * ASG int [000203] D------N---- +--* LCL_VAR int V22 loc19 [000202] ------------ \--* LCL_VAR int V34 tmp4 LocalAddressVisitor visiting statement: STMT00047 (IL 0x171...0x18A) [000208] --C-G------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft [000206] ------------ arg0 +--* ADDR byref [000205] -------N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 [000207] ------------ arg1 \--* LCL_VAR int V21 loc18 Local V56 should not be enregistered because: it is address exposed Local V57 should not be enregistered because: it is address exposed Local V15 should not be enregistered because: it is address exposed LocalAddressVisitor visiting statement: STMT00048 (IL 0x17A... ???) [000213] S-C-G------- * CALL void System.Numerics.BigInteger.DivRem [000220] ------------ arg0 +--* ADDR byref [000219] -------N---- | \--* LCL_VAR struct(P) V35 tmp5 | \--* ref V35._bits (offs=0x00) -> V62 tmp32 | \--* int V35._sign (offs=0x08) -> V63 tmp33 [000217] n----------- arg1 +--* OBJ struct [000216] ------------ | \--* ADDR byref [000209] -------N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 [000215] n----------- arg2 +--* OBJ struct [000214] ------------ | \--* ADDR byref [000210] -------N---- | \--* LCL_VAR struct(AX)(P) V16 loc13 | \--* ref V16._bits (offs=0x00) -> V58 tmp28 | \--* int V16._sign (offs=0x08) -> V59 tmp29 [000212] ------------ arg3 \--* ADDR byref [000211] -------N---- \--* LCL_VAR struct(P) V23 loc20 \--* ref V23._bits (offs=0x00) -> V60 tmp30 \--* int V23._sign (offs=0x08) -> V61 tmp31 Local V60 should not be enregistered because: it is address exposed Local V61 should not be enregistered because: it is address exposed Local V23 should not be enregistered because: it is address exposed Local V62 should not be enregistered because: it is address exposed Local V63 should not be enregistered because: it is address exposed Local V35 should not be enregistered because: it is address exposed LocalAddressVisitor visiting statement: STMT00050 (IL ???... ???) [000226] -AC--------- * ASG long [000225] D------N---- +--* LCL_VAR long V24 loc21 [000218] --C-G------- \--* CALL long System.Numerics.BigInteger.op_Explicit [000223] n----------- arg0 \--* OBJ struct [000222] ------------ \--* ADDR byref [000221] -------N---- \--* LCL_VAR struct(AX)(P) V35 tmp5 \--* ref V35._bits (offs=0x00) -> V62 tmp32 \--* int V35._sign (offs=0x08) -> V63 tmp33 LocalAddressVisitor visiting statement: STMT00052 (IL ???... ???) [000232] -AC--------- * ASG int [000231] D------N---- +--* LCL_VAR int V25 loc22 [000516] ------------ \--* EQ int [000514] ------------ +--* FIELD int _sign [000512] ------------ | \--* ADDR byref [000513] -------N---- | \--* LCL_VAR struct(AX)(P) V23 loc20 | \--* ref V23._bits (offs=0x00) -> V60 tmp30 | \--* int V23._sign (offs=0x08) -> V61 tmp31 [000515] ------------ \--* CNS_INT int 0 Replacing the field in promoted struct with local var V61 LocalAddressVisitor modified statement: STMT00052 (IL ???... ???) [000232] -AC--------- * ASG int [000231] D------N---- +--* LCL_VAR int V25 loc22 [000516] ------------ \--* EQ int [000514] ------------ +--* LCL_VAR int (AX) V61 tmp31 [000515] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00054 (IL ???... ???) [000237] -AC--------- * ASG int [000236] D------N---- +--* LCL_VAR int V26 loc23 [000234] --C-G------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits [000233] ------------ arg0 \--* LCL_VAR long V24 loc21 LocalAddressVisitor visiting statement: STMT00055 (IL 0x19E...0x1A2) [000241] ------------ * JTRUE void [000240] N--------U-- \--* LE int [000238] ------------ +--* LCL_VAR int V26 loc23 [000239] ------------ \--* LCL_VAR int V20 loc17 LocalAddressVisitor visiting statement: STMT00063 (IL 0x1A4...0x1A9) [000286] -A---------- * ASG int [000285] D------N---- +--* LCL_VAR int V29 loc26 [000284] ------------ \--* SUB int [000282] ------------ +--* LCL_VAR int V26 loc23 [000283] ------------ \--* LCL_VAR int V20 loc17 LocalAddressVisitor visiting statement: STMT00064 (IL 0x1AB...0x1AD) [000290] ------------ * JTRUE void [000289] ------------ \--* EQ int [000287] ------------ +--* LCL_VAR int V25 loc22 [000288] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00068 (IL 0x1AF...0x1C1) [000320] -A---------- * ASG int [000319] D------N---- +--* LCL_VAR int V37 tmp7 [000318] ------------ \--* EQ int [000315] ------------ +--* AND long [000305] ------------ | +--* LCL_VAR long V24 loc21 [000314] ------------ | \--* SUB long [000311] ------------ | +--* LSH long [000307] ------------ | | +--* CAST long <- int [000306] ------------ | | | \--* CNS_INT int 1 [000310] ------------ | | \--* AND int [000308] ------------ | | +--* LCL_VAR int V29 loc26 [000309] ------------ | | \--* CNS_INT int 63 [000313] ------------ | \--* CAST long <- int [000312] ------------ | \--* CNS_INT int 1 [000317] ------------ \--* CAST long <- int [000316] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00065 (IL 0x1C3...0x1C3) [000293] -A---------- * ASG int [000292] D------N---- +--* LCL_VAR int V37 tmp7 [000291] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00066 (IL ???...0x1C4) [000297] -A---------- * ASG int [000296] D------N---- +--* LCL_VAR int V25 loc22 [000295] ------------ \--* LCL_VAR int V37 tmp7 LocalAddressVisitor visiting statement: STMT00067 (IL 0x1C6...0x1CE) [000304] -A---------- * ASG long [000303] D------N---- +--* LCL_VAR long V24 loc21 [000302] ------------ \--* RSZ long [000298] ------------ +--* LCL_VAR long V24 loc21 [000301] ------------ \--* AND int [000299] ------------ +--* LCL_VAR int V29 loc26 [000300] ------------ \--* CNS_INT int 63 LocalAddressVisitor visiting statement: STMT00057 (IL ???... ???) [000254] -AC--------- * ASG long [000253] D------N---- +--* LCL_VAR long V27 loc24 [000252] --C--------- \--* ADD long [000250] --C--------- +--* LSH long [000243] --C-G------- | +--* CALL long System.Numerics.BigInteger.op_Explicit [000245] n----------- arg0 | | \--* OBJ struct [000244] ------------ | | \--* ADDR byref [000242] -------N---- | | \--* LCL_VAR struct(AX)(P) V11 loc8 | | \--* ref V11._bits (offs=0x00) -> V54 tmp24 | | \--* int V11._sign (offs=0x08) -> V55 tmp25 [000249] ------------ | \--* AND int [000247] ------------ | +--* LCL_VAR int V20 loc17 [000248] ------------ | \--* CNS_INT int 63 [000251] ------------ \--* LCL_VAR long V24 loc21 LocalAddressVisitor visiting statement: STMT00058 (IL 0x1E2...0x1E5) [000258] ------------ * JTRUE void [000257] N--------U-- \--* GT int [000255] ------------ +--* LCL_VAR int V13 loc10 [000256] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00062 (IL 0x1E7...0x1EC) [000280] -A---------- * ASG int [000279] D------N---- +--* LCL_VAR int V36 tmp6 [000278] ------------ \--* SUB int [000276] ------------ +--* NEG int [000275] ------------ | \--* LCL_VAR int V22 loc19 [000277] ------------ \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00059 (IL 0x1EE...0x1F1) [000263] -A---------- * ASG int [000262] D------N---- +--* LCL_VAR int V36 tmp6 [000261] ------------ \--* SUB int [000259] ------------ +--* LCL_VAR int V13 loc10 [000260] ------------ \--* CNS_INT int 2 LocalAddressVisitor visiting statement: STMT00060 (IL ???...0x1F2) [000267] -A---------- * ASG int [000266] D------N---- +--* LCL_VAR int V28 loc25 [000265] ------------ \--* LCL_VAR int V36 tmp6 LocalAddressVisitor visiting statement: STMT00061 (IL 0x1F4...0x201) [000274] --C-G------- * RETURN int [000273] --C-G------- \--* CALL nullcheck int FloatingPointType.AssembleFloatingPointValue [000268] ------------ this in rcx +--* LCL_VAR ref V01 arg1 [000269] ------------ arg1 +--* LCL_VAR long V27 loc24 [000270] ------------ arg2 +--* LCL_VAR int V28 loc25 [000271] ------------ arg3 +--* LCL_VAR int V25 loc22 [000272] ------------ arg4 \--* LCL_VAR byref V02 arg2 LocalAddressVisitor visiting statement: STMT00109 (IL ???... ???) [000523] ------------ * RETURN int [000522] -------N---- \--* LCL_VAR int V51 tmp21 *************** Finishing PHASE Morph - Structs/AddrExp *************** Starting PHASE Morph - ByRefs *************** In fgRetypeImplicitByRefArgs() lvaGrabTemp returning 72 (V72 tmp42) (a long lifetime temp) called for Promoted implicit byref. Keeping promotion of implicit by-ref V00: total: 9 non-call: 7 fields: 2 New Basic Block BB49 [0056] created. New scratch BB49 Changing the lvType for struct parameter V00 to TYP_BYREF. *************** Finishing PHASE Morph - ByRefs *************** Starting PHASE Morph - Global *************** In fgMorphBlocks() Morphing BB49 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB49, STMT00111 (before) [000528] -A---------- * ASG struct (copy) [000525] D------N---- +--* LCL_VAR struct(P) V72 tmp42 +--* ref V72.Mantissa (offs=0x00) -> V52 tmp22 +--* int V72.Exponent (offs=0x08) -> V53 tmp23 [000527] ------------ \--* BLK struct<16> [000526] ------------ \--* LCL_VAR byref (P?!) V00 arg0 fgMorphCopyBlock: fgMorphBlkNode for dst tree, before: [000525] D----+-N---- * LCL_VAR struct(P) V72 tmp42 * ref V72.Mantissa (offs=0x00) -> V52 tmp22 * int V72.Exponent (offs=0x08) -> V53 tmp23 fgMorphBlkNode after: [000525] D----+-N---- * LCL_VAR struct(P) V72 tmp42 * ref V72.Mantissa (offs=0x00) -> V52 tmp22 * int V72.Exponent (offs=0x08) -> V53 tmp23 fgMorphBlkNode for src tree, before: [000527] n----+------ * BLK struct<16> [000526] -----+------ \--* LCL_VAR byref (P?!) V00 arg0 fgMorphBlkNode after: [000527] n----+------ * BLK struct<16> [000526] -----+------ \--* LCL_VAR byref (P?!) V00 arg0 block assignment to morph: [000528] -A---------- * ASG struct (copy) [000525] D----+-N---- +--* LCL_VAR struct(P) V72 tmp42 +--* ref V72.Mantissa (offs=0x00) -> V52 tmp22 +--* int V72.Exponent (offs=0x08) -> V53 tmp23 [000527] n----+------ \--* BLK struct<16> [000526] -----+------ \--* LCL_VAR byref (P?!) V00 arg0 (destDoFldAsg=true) using field by field assignments. fgAddFieldSeqForZeroOffset for Fseq[Mantissa] addr (Before) [000531] ------------ LCL_VAR byref (P?!) (After) [000531] ------------ LCL_VAR byref (P?!) Zero Fseq[Mantissa] GenTreeNode creates assertion: [000539] -A---------- * ASG int In BB49 New Local Subrange Assertion: V53 in [-2147483648..2147483647] index=#01, mask=0000000000000001 fgMorphCopyBlock (after): [000540] -A---+------ * COMMA void [000533] -A---------- +--* ASG ref [000530] D------N---- | +--* LCL_VAR ref V52 tmp22 [000532] n----------- | \--* IND ref [000531] ------------ | \--* LCL_VAR byref (P?!) V00 arg0 Zero Fseq[Mantissa] [000539] -A---------- \--* ASG int [000534] D------N---- +--* LCL_VAR int V53 tmp23 [000538] n----------- \--* IND int [000537] ------------ \--* ADD byref [000535] ------------ +--* LCL_VAR byref (P?!) V00 arg0 [000536] ------------ \--* CNS_INT long 8 Fseq[Exponent] fgMorphTree BB49, STMT00111 (after) [000540] -A---+------ * COMMA void [000533] -A---------- +--* ASG ref [000530] D------N---- | +--* LCL_VAR ref V52 tmp22 [000532] n----------- | \--* IND ref [000531] ------------ | \--* LCL_VAR byref (P?!) V00 arg0 Zero Fseq[Mantissa] [000539] -A---------- \--* ASG int [000534] D------N---- +--* LCL_VAR int V53 tmp23 [000538] n----------- \--* IND int [000537] ------------ \--* ADD byref [000535] ------------ +--* LCL_VAR byref (P?!) V00 arg0 [000536] ------------ \--* CNS_INT long 8 Fseq[Exponent] Morphing BB01 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB01, STMT00000 (before) [000006] ---XG------- * JTRUE void [000005] ---XG------- \--* NE int [000003] ---XG------- +--* ARR_LENGTH int [000002] ------------ | \--* LCL_VAR ref V52 tmp22 [000004] ------------ \--* CNS_INT int 0 GenTreeNode creates assertion: [000003] ---XG------- * ARR_LENGTH int In BB01 New Local Constant Assertion: V52 != null index=#01, mask=0000000000000001 Morphing BB02 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB02, STMT00087 (before) [000403] -ACXG------- * ASG long [000402] *------N---- +--* IND long [000399] ------------ | \--* LCL_VAR byref V02 arg2 [000401] --C-G------- \--* CALLV ind long FloatingPointType.get_Zero [000400] ------------ this in rcx \--* LCL_VAR ref V01 arg1 Initializing arg info for 401.CALL: ArgTable for 401.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 400.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8] Morphing args for 401.CALL: argSlots=1, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000400] -----+------ * LCL_VAR ref V01 arg1 Replaced with placeholder node: [000541] ----------L- * ARGPLACE ref Shuffled argument table: rcx ArgTable for 401.CALL after fgMorphArgs: fgArgTabEntry[arg 0 400.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed] GenTreeNode creates assertion: [000401] --CXG------- * CALLV ind long FloatingPointType.get_Zero In BB02 New Local Constant Assertion: V01 != null index=#01, mask=0000000000000001 fgMorphTree BB02, STMT00087 (after) [000403] -ACXG+------ * ASG long [000402] *--X-+-N---- +--* IND long [000399] -----+------ | \--* LCL_VAR byref V02 arg2 [000401] --CXG+------ \--* CALLV ind long FloatingPointType.get_Zero [000400] -----+------ this in rcx \--* LCL_VAR ref V01 arg1 fgMorphTree BB02, STMT00107 (before) [000520] ------------ * RETURN int [000404] ------------ \--* CNS_INT int 1 Morphing BB04 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB04, STMT00002 (before) [000013] -AC--------- * ASG int [000012] D------N---- +--* LCL_VAR int V03 loc0 [000011] --C--------- \--* ADD int [000409] --C-G------- +--* CAST int <- ushort <- int [000408] --C-G------- | \--* ADD int [000406] --C-G------- | +--* CALLV ind int FloatingPointType.get_DenormalMantissaBits [000007] ------------ this in rcx | | \--* LCL_VAR ref V01 arg1 [000407] ------------ | \--* CNS_INT int 1 [000010] ------------ \--* CNS_INT int 1 Initializing arg info for 406.CALL: ArgTable for 406.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 7.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8] Morphing args for 406.CALL: argSlots=1, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000007] -----+------ * LCL_VAR ref V01 arg1 Replaced with placeholder node: [000542] ----------L- * ARGPLACE ref Shuffled argument table: rcx ArgTable for 406.CALL after fgMorphArgs: fgArgTabEntry[arg 0 7.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed] GenTreeNode creates assertion: [000406] --CXG------- * CALLV ind int FloatingPointType.get_DenormalMantissaBits In BB04 New Local Constant Assertion: V01 != null index=#01, mask=0000000000000001 fgMorphTree BB04, STMT00002 (after) [000013] -ACXG+------ * ASG int [000012] D----+-N---- +--* LCL_VAR int V03 loc0 [000011] --CXG+------ \--* ADD int [000409] --CXG+------ +--* CAST int <- ushort <- int [000408] --CXG+------ | \--* ADD int [000406] --CXG+------ | +--* CALLV ind int FloatingPointType.get_DenormalMantissaBits [000007] -----+------ this in rcx | | \--* LCL_VAR ref V01 arg1 [000407] -----+------ | \--* CNS_INT int 1 [000010] -----+------ \--* CNS_INT int 1 fgMorphTree BB04, STMT00092 (before) [000424] -A--G------- * ASG int [000423] D------N---- +--* LCL_VAR int V40 tmp10 [000017] ------------ \--* LCL_VAR int V53 tmp23 GenTreeNode creates assertion: [000424] -A--G------- * ASG int In BB04 New Local Copy Assertion: V40 == V53 index=#02, mask=0000000000000002 fgMorphTree BB04, STMT00089 (before) [000414] ------------ * JTRUE void [000413] ------------ \--* GE int [000411] ------------ +--* CNS_INT int 0 [000412] ------------ \--* LCL_VAR int V40 tmp10 Assertion prop in BB04: Copy Assertion: V40 == V53 index=#02, mask=0000000000000002 [000412] ------------ * LCL_VAR int V53 tmp23 fgMorphTree BB04, STMT00089 (after) [000414] -----+------ * JTRUE void [000413] J----+-N---- \--* GE int [000411] -----+------ +--* CNS_INT int 0 [000412] -----+------ \--* LCL_VAR int V53 tmp23 Morphing BB06 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB06, STMT00091 (before) [000421] -A---------- * ASG int [000420] D------N---- +--* LCL_VAR int V39 tmp9 [000419] ------------ \--* LCL_VAR int V40 tmp10 GenTreeNode creates assertion: [000421] -A---------- * ASG int In BB06 New Local Copy Assertion: V39 == V40 index=#01, mask=0000000000000001 Morphing BB07 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB07, STMT00090 (before) [000417] -A---------- * ASG int [000416] D------N---- +--* LCL_VAR int V39 tmp9 [000415] ------------ \--* CNS_INT int 0 GenTreeNode creates assertion: [000417] -A---------- * ASG int In BB07 New Local Constant Assertion: V39 == 0 index=#01, mask=0000000000000001 Morphing BB08 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB08, STMT00004 (before) [000021] -AC--------- * ASG int [000020] D------N---- +--* LCL_VAR int V31 tmp1 [000422] ------------ \--* LCL_VAR int V39 tmp9 GenTreeNode creates assertion: [000021] -A---------- * ASG int In BB08 New Local Copy Assertion: V31 == V39 index=#01, mask=0000000000000001 fgMorphTree BB08, STMT00096 (before) [000443] -A-XG------- * ASG int [000442] D------N---- +--* LCL_VAR int V42 tmp12 [000429] ---XG------- \--* ARR_LENGTH int [000428] ------------ \--* LCL_VAR ref V52 tmp22 GenTreeNode creates assertion: [000429] ---XG------- * ARR_LENGTH int In BB08 New Local Constant Assertion: V52 != null index=#02, mask=0000000000000002 fgMorphTree BB08, STMT00093 (before) [000433] ------------ * JTRUE void [000432] N--------U-- \--* LE int [000023] ------------ +--* LCL_VAR int V31 tmp1 [000431] ------------ \--* LCL_VAR int V42 tmp12 Assertion prop in BB08: Copy Assertion: V31 == V39 index=#01, mask=0000000000000001 [000023] ------------ * LCL_VAR int V39 tmp9 fgMorphTree BB08, STMT00093 (after) [000433] -----+------ * JTRUE void [000432] N----+-N-U-- \--* LE int [000023] -----+------ +--* LCL_VAR int V39 tmp9 [000431] -----+------ \--* LCL_VAR int V42 tmp12 Morphing BB10 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB10, STMT00095 (before) [000440] -A---------- * ASG int [000439] D------N---- +--* LCL_VAR int V41 tmp11 [000438] ------------ \--* LCL_VAR int V42 tmp12 GenTreeNode creates assertion: [000440] -A---------- * ASG int In BB10 New Local Copy Assertion: V41 == V42 index=#01, mask=0000000000000001 Morphing BB11 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB11, STMT00094 (before) [000436] -A---------- * ASG int [000435] D------N---- +--* LCL_VAR int V41 tmp11 [000434] ------------ \--* LCL_VAR int V31 tmp1 GenTreeNode creates assertion: [000436] -A---------- * ASG int In BB11 New Local Copy Assertion: V41 == V31 index=#01, mask=0000000000000001 Morphing BB12 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB12, STMT00007 (before) [000031] -AC--------- * ASG int [000030] D------N---- +--* LCL_VAR int V04 loc1 [000441] ------------ \--* LCL_VAR int V41 tmp11 GenTreeNode creates assertion: [000031] -A---------- * ASG int In BB12 New Local Copy Assertion: V04 == V41 index=#01, mask=0000000000000001 fgMorphTree BB12, STMT00008 (before) [000035] -A---------- * ASG int [000034] D------N---- +--* LCL_VAR int V05 loc2 [000033] ------------ \--* SUB int [000022] ------------ +--* LCL_VAR int V31 tmp1 [000032] ------------ \--* LCL_VAR int V04 loc1 Assertion prop in BB12: Copy Assertion: V04 == V41 index=#01, mask=0000000000000001 [000032] ------------ * LCL_VAR int V41 tmp11 fgMorphTree BB12, STMT00008 (after) [000035] -A---+------ * ASG int [000034] D----+-N---- +--* LCL_VAR int V05 loc2 [000033] -----+------ \--* SUB int [000022] -----+------ +--* LCL_VAR int V31 tmp1 [000032] -----+------ \--* LCL_VAR int V41 tmp11 fgMorphTree BB12, STMT00009 (before) [000038] -A---------- * ASG int [000037] D------N---- +--* LCL_VAR int V06 loc3 [000036] ------------ \--* CNS_INT int 0 GenTreeNode creates assertion: [000038] -A---------- * ASG int In BB12 New Local Constant Assertion: V06 == 0 index=#02, mask=0000000000000002 fgMorphTree BB12, STMT00010 (before) [000041] -A---------- * ASG int [000040] D------N---- +--* LCL_VAR int V07 loc4 [000039] ------------ \--* LCL_VAR int V04 loc1 Assertion prop in BB12: Copy Assertion: V04 == V41 index=#01, mask=0000000000000001 [000039] ------------ * LCL_VAR int V41 tmp11 GenTreeNode creates assertion: [000041] -A---------- * ASG int In BB12 New Local Copy Assertion: V07 == V41 index=#03, mask=0000000000000004 fgMorphTree BB12, STMT00010 (after) [000041] -A---+------ * ASG int [000040] D----+-N---- +--* LCL_VAR int V07 loc4 [000039] -----+------ \--* LCL_VAR int V41 tmp11 fgMorphTree BB12, STMT00011 (before) [000044] -A---------- * ASG int [000043] D------N---- +--* LCL_VAR int V08 loc5 [000042] ------------ \--* LCL_VAR int V07 loc4 Assertion prop in BB12: Copy Assertion: V07 == V41 index=#03, mask=0000000000000004 [000042] ------------ * LCL_VAR int V41 tmp11 GenTreeNode creates assertion: [000044] -A---------- * ASG int In BB12 New Local Copy Assertion: V08 == V41 index=#04, mask=0000000000000008 fgMorphTree BB12, STMT00011 (after) [000044] -A---+------ * ASG int [000043] D----+-N---- +--* LCL_VAR int V08 loc5 [000042] -----+------ \--* LCL_VAR int V41 tmp11 fgMorphTree BB12, STMT00013 (before) [000050] -AC--------- * ASG int [000049] D------N---- +--* LCL_VAR int V09 loc6 [000448] ---XG------- \--* ARR_LENGTH int [000447] ------------ \--* LCL_VAR ref V52 tmp22 GenTreeNode creates assertion: [000448] ---XG------- * ARR_LENGTH int In BB12 New Local Constant Assertion: V52 != null index=#05, mask=0000000000000010 fgMorphTree BB12, STMT00014 (before) [000055] -A---------- * ASG int [000054] D------N---- +--* LCL_VAR int V10 loc7 [000053] ------------ \--* SUB int [000051] ------------ +--* LCL_VAR int V09 loc6 [000052] ------------ \--* LCL_VAR int V08 loc5 Assertion prop in BB12: Copy Assertion: V08 == V41 index=#04, mask=0000000000000008 [000052] ------------ * LCL_VAR int V41 tmp11 fgMorphTree BB12, STMT00014 (after) [000055] -A---+------ * ASG int [000054] D----+-N---- +--* LCL_VAR int V10 loc7 [000053] -----+------ \--* SUB int [000051] -----+------ +--* LCL_VAR int V09 loc6 [000052] -----+------ \--* LCL_VAR int V41 tmp11 fgMorphTree BB12, STMT00016 (before) [000059] S-C-G------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger [000064] ------------ arg0 +--* ADDR byref [000063] -------N---- | \--* LCL_VAR struct(AX)(P) V11 loc8 | \--* ref V11._bits (offs=0x00) -> V54 tmp24 | \--* int V11._sign (offs=0x08) -> V55 tmp25 [000061] n----------- arg1 +--* OBJ struct [000060] ------------ | \--* ADDR byref [000056] -------N---- | \--* LCL_VAR struct(P?!) V00 arg0 [000057] ------------ arg2 +--* LCL_VAR int V06 loc3 [000058] ------------ arg3 \--* LCL_VAR int V07 loc4 Initializing arg info for 59.CALL: ArgTable for 59.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 64.ADDR long (By ref), 1 reg: rcx, byteAlignment=8] fgArgTabEntry[arg 1 61.OBJ struct (By ref), 1 reg: rdx, byteAlignment=8, isStruct] fgArgTabEntry[arg 2 57.LCL_VAR int (By ref), 1 reg: r8, byteAlignment=8] fgArgTabEntry[arg 3 58.LCL_VAR int (By ref), 1 reg: r9, byteAlignment=8] Morphing args for 59.CALL: making an outgoing copy for struct arg lvaGrabTemp returning 73 (V73 tmp43) called for by-value struct argument. fgMorphCopyBlock: fgMorphBlkNode for dst tree, before: [000543] D------N---- * LCL_VAR struct V73 tmp43 fgMorphBlkNode after: [000543] D------N---- * LCL_VAR struct V73 tmp43 fgMorphBlkNode for src tree, before: [000056] -----+-N---- * LCL_VAR struct(P) V72 tmp42 * ref V72.Mantissa (offs=0x00) -> V52 tmp22 * int V72.Exponent (offs=0x08) -> V53 tmp23 fgMorphBlkNode after: [000056] -----+-N---- * LCL_VAR struct(P) V72 tmp42 * ref V72.Mantissa (offs=0x00) -> V52 tmp22 * int V72.Exponent (offs=0x08) -> V53 tmp23 block assignment to morph: [000544] -A---------- * ASG struct (copy) [000543] D------N---- +--* LCL_VAR struct V73 tmp43 [000056] -----+-N---- \--* LCL_VAR struct(P) V72 tmp42 \--* ref V72.Mantissa (offs=0x00) -> V52 tmp22 \--* int V72.Exponent (offs=0x08) -> V53 tmp23 (srcDoFldAsg=true) using field by field assignments. Local V73 should not be enregistered because: written in a block op lvaGrabTemp returning 74 (V74 tmp44) called for BlockOp address local. Local V73 should not be enregistered because: it is address exposed fgAddFieldSeqForZeroOffset for Fseq[Mantissa] addr (Before) [000550] ------------ LCL_VAR byref (After) [000550] ------------ LCL_VAR byref Zero Fseq[Mantissa] fgMorphCopyBlock (after): [000561] -A---+------ * COMMA void [000554] -A---------- +--* COMMA void [000549] -A---------- | +--* ASG byref [000548] D------N---- | | +--* LCL_VAR byref V74 tmp44 [000546] -----+------ | | \--* ADDR byref [000547] -----+-N---- | | \--* LCL_VAR struct(AX) V73 tmp43 [000553] -A---------- | \--* ASG ref [000551] *------N---- | +--* IND ref [000550] ------------ | | \--* LCL_VAR byref V74 tmp44 Zero Fseq[Mantissa] [000552] -------N---- | \--* LCL_VAR ref V52 tmp22 [000560] -A---------- \--* ASG int [000558] *------N---- +--* IND int [000557] ------------ | \--* ADD byref [000555] ------------ | +--* LCL_VAR byref V74 tmp44 [000556] ------------ | \--* CNS_INT long 8 Fseq[Exponent] [000559] -------N---- \--* LCL_VAR int V53 tmp23 Assertion prop in BB12: Constant Assertion: V06 == 0 index=#02, mask=0000000000000002 [000057] ------------ * CNS_INT int 0 Assertion prop in BB12: Copy Assertion: V07 == V41 index=#03, mask=0000000000000004 [000058] ------------ * LCL_VAR int V41 tmp11 argSlots=4, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Argument with 'side effect'... [000064] -----+------ * ADDR long [000063] ----G+-N---- \--* LCL_VAR struct(AX)(P) V11 loc8 \--* ref V11._bits (offs=0x00) -> V54 tmp24 \--* int V11._sign (offs=0x08) -> V55 tmp25 lvaGrabTemp returning 75 (V75 tmp45) called for argument with side effect. Evaluate to a temp: [000563] -A--------L- * ASG long [000562] D------N---- +--* LCL_VAR long V75 tmp45 [000064] -----+------ \--* ADDR long [000063] ----G+-N---- \--* LCL_VAR struct(AX)(P) V11 loc8 \--* ref V11._bits (offs=0x00) -> V54 tmp24 \--* int V11._sign (offs=0x08) -> V55 tmp25 Local V73 should not be enregistered because: it is address exposed Deferred argument ('r9'): [000058] -----+------ * LCL_VAR int V41 tmp11 Replaced with placeholder node: [000567] ----------L- * ARGPLACE int Deferred argument ('r8'): [000057] -----+------ * CNS_INT int 0 Replaced with placeholder node: [000568] ----------L- * ARGPLACE int Shuffled argument table: rcx rdx r9 r8 ArgTable for 59.CALL after fgMorphArgs: fgArgTabEntry[arg 0 564.LCL_VAR long (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, tmpNum=V75, isTmp, processed] fgArgTabEntry[arg 1 566.ADDR struct (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=1, tmpNum=V73, isTmp, processed, isStruct] fgArgTabEntry[arg 3 58.LCL_VAR int (By ref), 1 reg: r9, byteAlignment=8, lateArgInx=2, processed] fgArgTabEntry[arg 2 57.CNS_INT int (By ref), 1 reg: r8, byteAlignment=8, lateArgInx=3, processed] fgMorphTree BB12, STMT00016 (after) [000059] SACXG+------ * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger [000563] -A--------L- arg0 SETUP +--* ASG long [000562] D------N---- | +--* LCL_VAR long V75 tmp45 [000064] -----+------ | \--* ADDR long [000063] ----G+-N---- | \--* LCL_VAR struct(AX)(P) V11 loc8 | \--* ref V11._bits (offs=0x00) -> V54 tmp24 | \--* int V11._sign (offs=0x08) -> V55 tmp25 [000561] -A---+----L- arg1 SETUP +--* COMMA void [000554] -A---------- | +--* COMMA void [000549] -A---------- | | +--* ASG byref [000548] D------N---- | | | +--* LCL_VAR byref V74 tmp44 [000546] -----+------ | | | \--* ADDR byref [000547] -----+-N---- | | | \--* LCL_VAR struct(AX) V73 tmp43 [000553] -A---------- | | \--* ASG ref [000551] *------N---- | | +--* IND ref [000550] ------------ | | | \--* LCL_VAR byref V74 tmp44 Zero Fseq[Mantissa] [000552] -------N---- | | \--* LCL_VAR ref V52 tmp22 [000560] -A---------- | \--* ASG int [000558] *------N---- | +--* IND int [000557] ------------ | | \--* ADD byref [000555] ------------ | | +--* LCL_VAR byref V74 tmp44 [000556] ------------ | | \--* CNS_INT long 8 Fseq[Exponent] [000559] -------N---- | \--* LCL_VAR int V53 tmp23 [000564] ------------ arg0 in rcx +--* LCL_VAR long V75 tmp45 [000566] ------------ arg1 in rdx +--* ADDR byref [000565] -------N---- | \--* LCL_VAR struct(AX) V73 tmp43 [000058] -----+------ arg3 in r9 +--* LCL_VAR int V41 tmp11 [000057] -----+------ arg2 in r8 \--* CNS_INT int 0 fgMorphTree BB12, STMT00017 (before) [000068] ------------ * JTRUE void [000067] N--------U-- \--* LE int [000065] ------------ +--* LCL_VAR int V05 loc2 [000066] ------------ \--* CNS_INT int 0 fgMorphTree BB12, STMT00017 (after) [000068] -----+------ * JTRUE void [000067] N----+-N---- \--* EQ int [000065] -----+------ +--* LCL_VAR int V05 loc2 [000066] -----+------ \--* CNS_INT int 0 Morphing BB13 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB13, STMT00083 (before) [000387] --C--------- * JTRUE void [000386] --C--------- \--* LE int [000381] ---------U-- +--* CAST long <- ulong <- uint [000380] ------------ | \--* LCL_VAR int V05 loc2 [000385] --C--------- \--* CAST long <- int [000383] --C-G------- \--* CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent [000382] ------------ this in rcx \--* LCL_VAR ref V01 arg1 Initializing arg info for 383.CALL: ArgTable for 383.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 382.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8] Morphing args for 383.CALL: argSlots=1, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000382] -----+------ * LCL_VAR ref V01 arg1 Replaced with placeholder node: [000569] ----------L- * ARGPLACE ref Shuffled argument table: rcx ArgTable for 383.CALL after fgMorphArgs: fgArgTabEntry[arg 0 382.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed] GenTreeNode creates assertion: [000383] --CXG------- * CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent In BB13 New Local Constant Assertion: V01 != null index=#01, mask=0000000000000001 fgMorphTree BB13, STMT00083 (after) [000387] --CXG+------ * JTRUE void [000386] J-CXG+-N---- \--* LE int [000381] -----+---U-- +--* CAST long <- ulong <- uint [000380] -----+------ | \--* LCL_VAR int V05 loc2 [000385] --CXG+------ \--* CAST long <- int [000383] --CXG+------ \--* CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent [000382] -----+------ this in rcx \--* LCL_VAR ref V01 arg1 Morphing BB14 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB14, STMT00085 (before) [000396] -ACXG------- * ASG long [000395] *------N---- +--* IND long [000392] ------------ | \--* LCL_VAR byref V02 arg2 [000394] --C-G------- \--* CALLV ind long FloatingPointType.get_Infinity [000393] ------------ this in rcx \--* LCL_VAR ref V01 arg1 Initializing arg info for 394.CALL: ArgTable for 394.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 393.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8] Morphing args for 394.CALL: argSlots=1, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000393] -----+------ * LCL_VAR ref V01 arg1 Replaced with placeholder node: [000570] ----------L- * ARGPLACE ref Shuffled argument table: rcx ArgTable for 394.CALL after fgMorphArgs: fgArgTabEntry[arg 0 393.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed] GenTreeNode creates assertion: [000394] --CXG------- * CALLV ind long FloatingPointType.get_Infinity In BB14 New Local Constant Assertion: V01 != null index=#01, mask=0000000000000001 fgMorphTree BB14, STMT00085 (after) [000396] -ACXG+------ * ASG long [000395] *--X-+-N---- +--* IND long [000392] -----+------ | \--* LCL_VAR byref V02 arg2 [000394] --CXG+------ \--* CALLV ind long FloatingPointType.get_Infinity [000393] -----+------ this in rcx \--* LCL_VAR ref V01 arg1 fgMorphTree BB14, STMT00108 (before) [000521] ------------ * RETURN int [000397] ------------ \--* CNS_INT int 3 Morphing BB16 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB16, STMT00084 (before) [000391] --C-G------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen [000389] ------------ arg0 +--* ADDR byref [000388] -------N---- | \--* LCL_VAR struct(AX)(P) V11 loc8 | \--* ref V11._bits (offs=0x00) -> V54 tmp24 | \--* int V11._sign (offs=0x08) -> V55 tmp25 [000390] ------------ arg1 \--* LCL_VAR int V05 loc2 Initializing arg info for 391.CALL: ArgTable for 391.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 389.ADDR long (By ref), 1 reg: rcx, byteAlignment=8] fgArgTabEntry[arg 1 390.LCL_VAR int (By ref), 1 reg: rdx, byteAlignment=8] Morphing args for 391.CALL: argSlots=2, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000389] -----+------ * ADDR long [000388] ----G+-N---- \--* LCL_VAR struct(AX)(P) V11 loc8 \--* ref V11._bits (offs=0x00) -> V54 tmp24 \--* int V11._sign (offs=0x08) -> V55 tmp25 Replaced with placeholder node: [000571] ----------L- * ARGPLACE long Deferred argument ('rdx'): [000390] -----+------ * LCL_VAR int V05 loc2 Replaced with placeholder node: [000572] ----------L- * ARGPLACE int Shuffled argument table: rcx rdx ArgTable for 391.CALL after fgMorphArgs: fgArgTabEntry[arg 0 389.ADDR long (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed] fgArgTabEntry[arg 1 390.LCL_VAR int (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=1, processed] fgMorphTree BB16, STMT00084 (after) [000391] --CXG+------ * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen [000389] -----+------ arg0 in rcx +--* ADDR long [000388] ----G+-N---- | \--* LCL_VAR struct(AX)(P) V11 loc8 | \--* ref V11._bits (offs=0x00) -> V54 tmp24 | \--* int V11._sign (offs=0x08) -> V55 tmp25 [000390] -----+------ arg1 in rdx \--* LCL_VAR int V05 loc2 Morphing BB17 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB17, STMT00019 (before) [000077] -AC--------- * ASG int [000076] D------N---- +--* LCL_VAR int V13 loc10 [000072] --C-G------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits [000074] n----------- arg0 +--* OBJ struct [000073] ------------ | \--* ADDR byref [000069] -------N---- | \--* LCL_VAR struct(AX)(P) V11 loc8 | \--* ref V11._bits (offs=0x00) -> V54 tmp24 | \--* int V11._sign (offs=0x08) -> V55 tmp25 [000071] ------------ arg1 \--* LCL_VAR_ADDR byref V12 loc9 Initializing arg info for 72.CALL: ArgTable for 72.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 74.OBJ struct (By ref), 1 reg: rcx, byteAlignment=8, isStruct] fgArgTabEntry[arg 1 71.LCL_VAR_ADDR long (By ref), 1 reg: rdx, byteAlignment=8] Morphing args for 72.CALL: making an outgoing copy for struct arg lvaGrabTemp returning 76 (V76 tmp46) called for by-value struct argument. fgMorphCopyBlock: fgMorphBlkNode for dst tree, before: [000573] D------N---- * LCL_VAR struct V76 tmp46 fgMorphBlkNode after: [000573] D------N---- * LCL_VAR struct V76 tmp46 fgMorphBlkNode for src tree, before: [000069] ----G+-N---- * LCL_VAR struct(AX)(P) V11 loc8 * ref V11._bits (offs=0x00) -> V54 tmp24 * int V11._sign (offs=0x08) -> V55 tmp25 fgMorphBlkNode after: [000069] ----G+-N---- * LCL_VAR struct(AX)(P) V11 loc8 * ref V11._bits (offs=0x00) -> V54 tmp24 * int V11._sign (offs=0x08) -> V55 tmp25 block assignment to morph: [000574] -A--G------- * ASG struct (copy) [000573] D------N---- +--* LCL_VAR struct V76 tmp46 [000069] ----G+-N---- \--* LCL_VAR struct(AX)(P) V11 loc8 \--* ref V11._bits (offs=0x00) -> V54 tmp24 \--* int V11._sign (offs=0x08) -> V55 tmp25 (srcDoFldAsg=true) using field by field assignments. Local V76 should not be enregistered because: written in a block op lvaGrabTemp returning 77 (V77 tmp47) called for BlockOp address local. Local V76 should not be enregistered because: it is address exposed fgAddFieldSeqForZeroOffset for Fseq[_bits] addr (Before) [000580] ------------ LCL_VAR byref (After) [000580] ------------ LCL_VAR byref Zero Fseq[_bits] fgMorphCopyBlock (after): [000591] -A--G+------ * COMMA void [000584] -A--G------- +--* COMMA void [000579] -A---------- | +--* ASG byref [000578] D------N---- | | +--* LCL_VAR byref V77 tmp47 [000576] -----+------ | | \--* ADDR byref [000577] -----+-N---- | | \--* LCL_VAR struct(AX) V76 tmp46 [000583] -A--G------- | \--* ASG ref [000581] *------N---- | +--* IND ref [000580] ------------ | | \--* LCL_VAR byref V77 tmp47 Zero Fseq[_bits] [000582] ----G--N---- | \--* LCL_VAR ref (AX) V54 tmp24 [000590] -A--G------- \--* ASG int [000588] *------N---- +--* IND int [000587] ------------ | \--* ADD byref [000585] ------------ | +--* LCL_VAR byref V77 tmp47 [000586] ------------ | \--* CNS_INT long 8 Fseq[_sign] [000589] ----G--N---- \--* LCL_VAR int (AX) V55 tmp25 argSlots=2, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Local V76 should not be enregistered because: it is address exposed Deferred argument ('rdx'): [000071] -----+------ * LCL_VAR_ADDR long V12 loc9 Replaced with placeholder node: [000594] ----------L- * ARGPLACE long Shuffled argument table: rcx rdx ArgTable for 72.CALL after fgMorphArgs: fgArgTabEntry[arg 0 593.ADDR struct (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, tmpNum=V76, isTmp, processed, isStruct] fgArgTabEntry[arg 1 71.LCL_VAR_ADDR long (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=1, processed] fgMorphTree BB17, STMT00019 (after) [000077] -ACXG+------ * ASG int [000076] D----+-N---- +--* LCL_VAR int V13 loc10 [000072] -ACXG+------ \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits [000591] -A--G+----L- arg0 SETUP +--* COMMA void [000584] -A--G------- | +--* COMMA void [000579] -A---------- | | +--* ASG byref [000578] D------N---- | | | +--* LCL_VAR byref V77 tmp47 [000576] -----+------ | | | \--* ADDR byref [000577] -----+-N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 [000583] -A--G------- | | \--* ASG ref [000581] *------N---- | | +--* IND ref [000580] ------------ | | | \--* LCL_VAR byref V77 tmp47 Zero Fseq[_bits] [000582] ----G--N---- | | \--* LCL_VAR ref (AX) V54 tmp24 [000590] -A--G------- | \--* ASG int [000588] *------N---- | +--* IND int [000587] ------------ | | \--* ADD byref [000585] ------------ | | +--* LCL_VAR byref V77 tmp47 [000586] ------------ | | \--* CNS_INT long 8 Fseq[_sign] [000589] ----G--N---- | \--* LCL_VAR int (AX) V55 tmp25 [000593] ------------ arg0 in rcx +--* ADDR byref [000592] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 [000071] -----+------ arg1 in rdx \--* LCL_VAR_ADDR long V12 loc9 fgMorphTree BB17, STMT00020 (before) [000081] ------------ * JTRUE void [000080] N--------U-- \--* GE int [000078] ------------ +--* LCL_VAR int V13 loc10 [000079] ------------ \--* LCL_VAR int V03 loc0 Morphing BB18 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB18, STMT00022 (before) [000094] ------------ * JTRUE void [000093] ------------ \--* NE int [000091] ------------ +--* LCL_VAR int V10 loc7 [000092] ------------ \--* CNS_INT int 0 Morphing BB19 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB19, STMT00021 (before) [000090] --C-G------- * RETURN int [000089] --C-G------- \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits [000082] ------------ arg0 +--* LCL_VAR ref (AX) V12 loc9 [000083] ------------ arg1 +--* LCL_VAR int V13 loc10 [000086] N--------U-- arg2 +--* GT int [000084] ------------ | +--* LCL_VAR int V10 loc7 [000085] ------------ | \--* CNS_INT int 0 [000087] ------------ arg3 +--* LCL_VAR ref V01 arg1 [000088] ------------ arg4 \--* LCL_VAR byref V02 arg2 Rejecting tail call in morph for call [000089]: Local address taken V11 Initializing arg info for 89.CALL: ArgTable for 89.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 82.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8] fgArgTabEntry[arg 1 83.LCL_VAR int (By ref), 1 reg: rdx, byteAlignment=8] fgArgTabEntry[arg 2 86.GT int (By ref), 1 reg: r8, byteAlignment=8] fgArgTabEntry[arg 3 87.LCL_VAR ref (By ref), 1 reg: r9, byteAlignment=8] fgArgTabEntry[arg 4 88.LCL_VAR byref (By ref), numSlots=1, slotNum=4, byteSize=8, byteOffset=32, byteAlignment=8] Morphing args for 89.CALL: argSlots=5, preallocatedArgCount=5, nextSlotNum=5, nextSlotByteOffset=40, outgoingArgSpaceSize=40 Sorting the arguments: Deferred argument ('r8'): [000086] N----+------ * NE int [000084] -----+------ +--* LCL_VAR int V10 loc7 [000085] -----+------ \--* CNS_INT int 0 Replaced with placeholder node: [000595] ----------L- * ARGPLACE int Deferred argument ('rcx'): [000082] ----G+------ * LCL_VAR ref (AX) V12 loc9 Replaced with placeholder node: [000596] ----------L- * ARGPLACE ref Deferred argument ('rdx'): [000083] -----+------ * LCL_VAR int V13 loc10 Replaced with placeholder node: [000597] ----------L- * ARGPLACE int Deferred argument ('r9'): [000087] -----+------ * LCL_VAR ref V01 arg1 Replaced with placeholder node: [000598] ----------L- * ARGPLACE ref Shuffled argument table: r8 rcx rdx r9 ArgTable for 89.CALL after fgMorphArgs: fgArgTabEntry[arg 2 86.NE int (By ref), 1 reg: r8, byteAlignment=8, lateArgInx=0, processed] fgArgTabEntry[arg 0 82.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=1, processed] fgArgTabEntry[arg 1 83.LCL_VAR int (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=2, processed] fgArgTabEntry[arg 3 87.LCL_VAR ref (By ref), 1 reg: r9, byteAlignment=8, lateArgInx=3, processed] fgArgTabEntry[arg 4 88.LCL_VAR byref (By ref), numSlots=1, slotNum=4, byteSize=8, byteOffset=32, byteAlignment=8, processed] fgMorphTree BB19, STMT00021 (after) [000090] --CXG+------ * RETURN int [000089] --CXG+------ \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits [000088] -----+------ arg4 out+20 +--* LCL_VAR byref V02 arg2 [000086] N----+------ arg2 in r8 +--* NE int [000084] -----+------ | +--* LCL_VAR int V10 loc7 [000085] -----+------ | \--* CNS_INT int 0 [000082] ----G+------ arg0 in rcx +--* LCL_VAR ref (AX) V12 loc9 [000083] -----+------ arg1 in rdx +--* LCL_VAR int V13 loc10 [000087] -----+------ arg3 in r9 \--* LCL_VAR ref V01 arg1 morph BB19 to point at onereturn. New block is BB19 [0008] 2 BB17,BB18 1 [096..0A7)-> BB48 (always) i label target hascall gcsafe Morphing BB20 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB20, STMT00023 (before) [000100] ----G------- * JTRUE void [000099] ----G------- \--* LT int [000097] ------------ +--* LCL_VAR int V53 tmp23 [000098] ------------ \--* CNS_INT int 0 Morphing BB21 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB21, STMT00081 (before) [000378] -A---------- * ASG int [000377] D------N---- +--* LCL_VAR int V32 tmp2 [000376] ------------ \--* LCL_VAR int V10 loc7 GenTreeNode creates assertion: [000378] -A---------- * ASG int In BB21 New Local Copy Assertion: V32 == V10 index=#01, mask=0000000000000001 Morphing BB22 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB22, STMT00024 (before) [000108] -A--G------- * ASG int [000107] D------N---- +--* LCL_VAR int V32 tmp2 [000106] ----G------- \--* ADD int [000101] ------------ +--* LCL_VAR int V10 loc7 [000105] ----G------- \--* NEG int [000104] ------------ \--* LCL_VAR int V53 tmp23 fgMorphTree BB22, STMT00024 (after) [000108] -A--G+------ * ASG int [000107] D----+-N---- +--* LCL_VAR int V32 tmp2 [000106] ----G+------ \--* SUB int [000101] -----+------ +--* LCL_VAR int V10 loc7 [000104] -----+------ \--* LCL_VAR int V53 tmp23 Morphing BB23 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB23, STMT00025 (before) [000112] -A---------- * ASG int [000111] D------N---- +--* LCL_VAR int V14 loc11 [000110] ------------ \--* LCL_VAR int V32 tmp2 GenTreeNode creates assertion: [000112] -A---------- * ASG int In BB23 New Local Copy Assertion: V14 == V32 index=#01, mask=0000000000000001 fgMorphTree BB23, STMT00026 (before) [000116] ------------ * JTRUE void [000115] ------------ \--* NE int [000113] ------------ +--* LCL_VAR int V13 loc10 [000114] ------------ \--* CNS_INT int 0 Morphing BB24 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB24, STMT00077 (before) [000363] -AC--------- * ASG long [000362] D------N---- +--* LCL_VAR long V38 tmp8 [000359] --C--------- \--* SUB long [000353] ---------U-- +--* CAST long <- ulong <- uint [000352] ------------ | \--* LCL_VAR int V14 loc11 [000358] --C--------- \--* CAST long <- int [000456] ---XG------- \--* ARR_LENGTH int [000455] ------------ \--* LCL_VAR ref V52 tmp22 GenTreeNode creates assertion: [000456] ---XG------- * ARR_LENGTH int In BB24 New Local Constant Assertion: V52 != null index=#01, mask=0000000000000001 fgMorphTree BB24, STMT00078 (before) [000368] --C--------- * JTRUE void [000367] --C--------- \--* LE int [000364] ------------ +--* LCL_VAR long V38 tmp8 [000366] --C--------- \--* CAST long <- int [000361] --C-G------- \--* CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent [000360] ------------ this in rcx \--* LCL_VAR ref V01 arg1 Initializing arg info for 361.CALL: ArgTable for 361.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 360.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8] Morphing args for 361.CALL: argSlots=1, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000360] -----+------ * LCL_VAR ref V01 arg1 Replaced with placeholder node: [000601] ----------L- * ARGPLACE ref Shuffled argument table: rcx ArgTable for 361.CALL after fgMorphArgs: fgArgTabEntry[arg 0 360.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed] GenTreeNode creates assertion: [000361] --CXG------- * CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent In BB24 New Local Constant Assertion: V01 != null index=#02, mask=0000000000000002 fgMorphTree BB24, STMT00078 (after) [000368] --CXG+------ * JTRUE void [000367] J-CXG+-N---- \--* LE int [000364] -----+------ +--* LCL_VAR long V38 tmp8 [000366] --CXG+------ \--* CAST long <- int [000361] --CXG+------ \--* CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent [000360] -----+------ this in rcx \--* LCL_VAR ref V01 arg1 Morphing BB25 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB25, STMT00079 (before) [000373] -ACXG------- * ASG long [000372] *------N---- +--* IND long [000369] ------------ | \--* LCL_VAR byref V02 arg2 [000371] --C-G------- \--* CALLV ind long FloatingPointType.get_Zero [000370] ------------ this in rcx \--* LCL_VAR ref V01 arg1 Initializing arg info for 371.CALL: ArgTable for 371.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 370.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8] Morphing args for 371.CALL: argSlots=1, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000370] -----+------ * LCL_VAR ref V01 arg1 Replaced with placeholder node: [000602] ----------L- * ARGPLACE ref Shuffled argument table: rcx ArgTable for 371.CALL after fgMorphArgs: fgArgTabEntry[arg 0 370.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed] GenTreeNode creates assertion: [000371] --CXG------- * CALLV ind long FloatingPointType.get_Zero In BB25 New Local Constant Assertion: V01 != null index=#01, mask=0000000000000001 fgMorphTree BB25, STMT00079 (after) [000373] -ACXG+------ * ASG long [000372] *--X-+-N---- +--* IND long [000369] -----+------ | \--* LCL_VAR byref V02 arg2 [000371] --CXG+------ \--* CALLV ind long FloatingPointType.get_Zero [000370] -----+------ this in rcx \--* LCL_VAR ref V01 arg1 fgMorphTree BB25, STMT00110 (before) [000524] ------------ * RETURN int [000374] ------------ \--* CNS_INT int 2 Morphing BB27 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB27, STMT00028 (before) [000120] S-C-G------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger [000125] ------------ arg0 +--* ADDR byref [000124] -------N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 [000122] n----------- arg1 +--* OBJ struct [000121] ------------ | \--* ADDR byref [000117] -------N---- | \--* LCL_VAR struct(P?!) V00 arg0 [000118] ------------ arg2 +--* LCL_VAR int V08 loc5 [000119] ------------ arg3 \--* LCL_VAR int V09 loc6 Initializing arg info for 120.CALL: ArgTable for 120.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 125.ADDR long (By ref), 1 reg: rcx, byteAlignment=8] fgArgTabEntry[arg 1 122.OBJ struct (By ref), 1 reg: rdx, byteAlignment=8, isStruct] fgArgTabEntry[arg 2 118.LCL_VAR int (By ref), 1 reg: r8, byteAlignment=8] fgArgTabEntry[arg 3 119.LCL_VAR int (By ref), 1 reg: r9, byteAlignment=8] Morphing args for 120.CALL: making an outgoing copy for struct arg reusing outgoing struct argfgMorphCopyBlock: fgMorphBlkNode for dst tree, before: [000603] D------N---- * LCL_VAR struct(AX) V73 tmp43 fgMorphBlkNode after: [000603] D------N---- * LCL_VAR struct(AX) V73 tmp43 fgMorphBlkNode for src tree, before: [000117] -----+-N---- * LCL_VAR struct(P) V72 tmp42 * ref V72.Mantissa (offs=0x00) -> V52 tmp22 * int V72.Exponent (offs=0x08) -> V53 tmp23 fgMorphBlkNode after: [000117] -----+-N---- * LCL_VAR struct(P) V72 tmp42 * ref V72.Mantissa (offs=0x00) -> V52 tmp22 * int V72.Exponent (offs=0x08) -> V53 tmp23 block assignment to morph: [000604] -A---------- * ASG struct (copy) [000603] D------N---- +--* LCL_VAR struct(AX) V73 tmp43 [000117] -----+-N---- \--* LCL_VAR struct(P) V72 tmp42 \--* ref V72.Mantissa (offs=0x00) -> V52 tmp22 \--* int V72.Exponent (offs=0x08) -> V53 tmp23 (srcDoFldAsg=true) using field by field assignments. Local V73 should not be enregistered because: written in a block op lvaGrabTemp returning 78 (V78 tmp48) called for BlockOp address local. Local V73 should not be enregistered because: it is address exposed fgAddFieldSeqForZeroOffset for Fseq[Mantissa] addr (Before) [000610] ------------ LCL_VAR byref (After) [000610] ------------ LCL_VAR byref Zero Fseq[Mantissa] fgMorphCopyBlock (after): [000621] -A---+------ * COMMA void [000614] -A---------- +--* COMMA void [000609] -A---------- | +--* ASG byref [000608] D------N---- | | +--* LCL_VAR byref V78 tmp48 [000606] -----+------ | | \--* ADDR byref [000607] ----G+-N---- | | \--* LCL_VAR struct(AX) V73 tmp43 [000613] -A---------- | \--* ASG ref [000611] *------N---- | +--* IND ref [000610] ------------ | | \--* LCL_VAR byref V78 tmp48 Zero Fseq[Mantissa] [000612] -------N---- | \--* LCL_VAR ref V52 tmp22 [000620] -A---------- \--* ASG int [000618] *------N---- +--* IND int [000617] ------------ | \--* ADD byref [000615] ------------ | +--* LCL_VAR byref V78 tmp48 [000616] ------------ | \--* CNS_INT long 8 Fseq[Exponent] [000619] -------N---- \--* LCL_VAR int V53 tmp23 argSlots=4, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Argument with 'side effect'... [000125] -----+------ * ADDR long [000124] ----G+-N---- \--* LCL_VAR struct(AX)(P) V15 loc12 \--* ref V15._bits (offs=0x00) -> V56 tmp26 \--* int V15._sign (offs=0x08) -> V57 tmp27 lvaGrabTemp returning 79 (V79 tmp49) called for argument with side effect. Evaluate to a temp: [000623] -A--------L- * ASG long [000622] D------N---- +--* LCL_VAR long V79 tmp49 [000125] -----+------ \--* ADDR long [000124] ----G+-N---- \--* LCL_VAR struct(AX)(P) V15 loc12 \--* ref V15._bits (offs=0x00) -> V56 tmp26 \--* int V15._sign (offs=0x08) -> V57 tmp27 Local V73 should not be enregistered because: it is address exposed Deferred argument ('r8'): [000118] -----+------ * LCL_VAR int V08 loc5 Replaced with placeholder node: [000627] ----------L- * ARGPLACE int Deferred argument ('r9'): [000119] -----+------ * LCL_VAR int V09 loc6 Replaced with placeholder node: [000628] ----------L- * ARGPLACE int Shuffled argument table: rcx rdx r8 r9 ArgTable for 120.CALL after fgMorphArgs: fgArgTabEntry[arg 0 624.LCL_VAR long (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, tmpNum=V79, isTmp, processed] fgArgTabEntry[arg 1 626.ADDR struct (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=1, tmpNum=V73, isTmp, processed, isStruct] fgArgTabEntry[arg 2 118.LCL_VAR int (By ref), 1 reg: r8, byteAlignment=8, lateArgInx=2, processed] fgArgTabEntry[arg 3 119.LCL_VAR int (By ref), 1 reg: r9, byteAlignment=8, lateArgInx=3, processed] fgMorphTree BB27, STMT00028 (after) [000120] SACXG+------ * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger [000623] -A--------L- arg0 SETUP +--* ASG long [000622] D------N---- | +--* LCL_VAR long V79 tmp49 [000125] -----+------ | \--* ADDR long [000124] ----G+-N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 [000621] -A---+----L- arg1 SETUP +--* COMMA void [000614] -A---------- | +--* COMMA void [000609] -A---------- | | +--* ASG byref [000608] D------N---- | | | +--* LCL_VAR byref V78 tmp48 [000606] -----+------ | | | \--* ADDR byref [000607] ----G+-N---- | | | \--* LCL_VAR struct(AX) V73 tmp43 [000613] -A---------- | | \--* ASG ref [000611] *------N---- | | +--* IND ref [000610] ------------ | | | \--* LCL_VAR byref V78 tmp48 Zero Fseq[Mantissa] [000612] -------N---- | | \--* LCL_VAR ref V52 tmp22 [000620] -A---------- | \--* ASG int [000618] *------N---- | +--* IND int [000617] ------------ | | \--* ADD byref [000615] ------------ | | +--* LCL_VAR byref V78 tmp48 [000616] ------------ | | \--* CNS_INT long 8 Fseq[Exponent] [000619] -------N---- | \--* LCL_VAR int V53 tmp23 [000624] ------------ arg0 in rcx +--* LCL_VAR long V79 tmp49 [000626] ------------ arg1 in rdx +--* ADDR byref [000625] -------N---- | \--* LCL_VAR struct(AX) V73 tmp43 [000118] -----+------ arg2 in r8 +--* LCL_VAR int V08 loc5 [000119] -----+------ arg3 in r9 \--* LCL_VAR int V09 loc6 fgMorphTree BB27, STMT00029 (before) [000133] H-CXG------- * CALL help long HELPER.CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE [000131] ------------ arg0 +--* CNS_INT long 0x7ff815262aa0 [000132] ------------ arg1 \--* CNS_INT int 173 Initializing arg info for 133.CALL: ArgTable for 133.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 131.CNS_INT long (By ref), 1 reg: rcx, byteAlignment=8] fgArgTabEntry[arg 1 132.CNS_INT int (By ref), 1 reg: rdx, byteAlignment=8] Morphing args for 133.CALL: argSlots=2, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000131] -----+------ * CNS_INT long 0x7ff815262aa0 Replaced with placeholder node: [000629] ----------L- * ARGPLACE long Deferred argument ('rdx'): [000132] -----+------ * CNS_INT int 173 Replaced with placeholder node: [000630] ----------L- * ARGPLACE int Shuffled argument table: rcx rdx ArgTable for 133.CALL after fgMorphArgs: fgArgTabEntry[arg 0 131.CNS_INT long (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed] fgArgTabEntry[arg 1 132.CNS_INT int (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=1, processed] fgMorphTree BB27, STMT00029 (after) [000133] H-CXG+------ * CALL help long HELPER.CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE [000131] -----+------ arg0 in rcx +--* CNS_INT long 0x7ff815262aa0 [000132] -----+------ arg1 in rdx \--* CNS_INT int 173 fgMorphTree BB27, STMT00030 (before) [000137] -A--G------- * ASG struct (copy) [000135] D------N---- +--* LCL_VAR struct(AX)(P) V16 loc13 +--* ref V16._bits (offs=0x00) -> V58 tmp28 +--* int V16._sign (offs=0x08) -> V59 tmp29 [000129] ----G------- \--* OBJ struct [000128] ----G------- \--* ADD byref [000126] ----G------- +--* FIELD ref BigOne [000127] ------------ \--* CNS_INT long 8 Fseq[#FirstElem] fgMorphCopyBlock: fgMorphBlkNode for dst tree, before: [000135] D---G+-N---- * LCL_VAR struct(AX)(P) V16 loc13 * ref V16._bits (offs=0x00) -> V58 tmp28 * int V16._sign (offs=0x08) -> V59 tmp29 fgMorphBlkNode after: [000135] D---G+-N---- * LCL_VAR struct(AX)(P) V16 loc13 * ref V16._bits (offs=0x00) -> V58 tmp28 * int V16._sign (offs=0x08) -> V59 tmp29 fgMorphBlkNode for src tree, before: [000129] ---XG+------ * OBJ struct [000128] ----G+------ \--* ADD byref [000126] n---G+------ +--* IND ref [000631] I----+------ | \--* CNS_INT(h) long 0xd1ffab1e static Fseq[BigOne] [000127] -----+------ \--* CNS_INT long 8 Fseq[#FirstElem] fgMorphBlkNode after: [000129] ---XG+------ * OBJ struct [000128] ----G+------ \--* ADD byref [000126] n---G+------ +--* IND ref [000631] I----+------ | \--* CNS_INT(h) long 0xd1ffab1e static Fseq[BigOne] [000127] -----+------ \--* CNS_INT long 8 Fseq[#FirstElem] block assignment to morph: [000137] -A-XG------- * ASG struct (copy) [000135] D---G+-N---- +--* LCL_VAR struct(AX)(P) V16 loc13 +--* ref V16._bits (offs=0x00) -> V58 tmp28 +--* int V16._sign (offs=0x08) -> V59 tmp29 [000129] ---XG+------ \--* OBJ struct [000128] ----G+------ \--* ADD byref [000126] n---G+------ +--* IND ref [000631] I----+------ | \--* CNS_INT(h) long 0xd1ffab1e static Fseq[BigOne] [000127] -----+------ \--* CNS_INT long 8 Fseq[#FirstElem] (destDoFldAsg=true) using field by field assignments. lvaGrabTemp returning 80 (V80 tmp50) called for BlockOp address local. fgAddFieldSeqForZeroOffset for Fseq[_bits] addr (Before) [000639] ------------ LCL_VAR byref (After) [000639] ------------ LCL_VAR byref Zero Fseq[_bits] fgMorphCopyBlock (after): [000649] -A-XG+------ * COMMA void [000642] -A-XG------- +--* COMMA void [000637] -A--G------- | +--* ASG byref [000636] D------N---- | | +--* LCL_VAR byref V80 tmp50 [000632] ----G+------ | | \--* ADD byref [000633] n---G+------ | | +--* IND ref [000634] I----+------ | | | \--* CNS_INT(h) long 0xd1ffab1e static Fseq[BigOne] [000635] -----+------ | | \--* CNS_INT long 8 Fseq[#FirstElem] [000641] -A-XG------- | \--* ASG ref [000638] D---G--N---- | +--* LCL_VAR ref (AX) V58 tmp28 [000640] ---X-------- | \--* IND ref [000639] ------------ | \--* LCL_VAR byref V80 tmp50 Zero Fseq[_bits] [000648] -A-XG------- \--* ASG int [000643] D---G--N---- +--* LCL_VAR int (AX) V59 tmp29 [000647] ---X-------- \--* IND int [000646] ------------ \--* ADD byref [000644] ------------ +--* LCL_VAR byref V80 tmp50 [000645] ------------ \--* CNS_INT long 8 Fseq[_sign] fgMorphTree BB27, STMT00030 (after) [000649] -A-XG+------ * COMMA void [000642] -A-XG------- +--* COMMA void [000637] -A--G------- | +--* ASG byref [000636] D------N---- | | +--* LCL_VAR byref V80 tmp50 [000632] ----G+------ | | \--* ADD byref [000633] n---G+------ | | +--* IND ref [000634] I----+------ | | | \--* CNS_INT(h) long 0xd1ffab1e static Fseq[BigOne] [000635] -----+------ | | \--* CNS_INT long 8 Fseq[#FirstElem] [000641] -A-XG------- | \--* ASG ref [000638] D---G--N---- | +--* LCL_VAR ref (AX) V58 tmp28 [000640] ---X-------- | \--* IND ref [000639] ------------ | \--* LCL_VAR byref V80 tmp50 Zero Fseq[_bits] [000648] -A-XG------- \--* ASG int [000643] D---G--N---- +--* LCL_VAR int (AX) V59 tmp29 [000647] ---X-------- \--* IND int [000646] ------------ \--* ADD byref [000644] ------------ +--* LCL_VAR byref V80 tmp50 [000645] ------------ \--* CNS_INT long 8 Fseq[_sign] fgMorphTree BB27, STMT00031 (before) [000141] --C-G------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen [000139] ------------ arg0 +--* ADDR byref [000138] -------N---- | \--* LCL_VAR struct(AX)(P) V16 loc13 | \--* ref V16._bits (offs=0x00) -> V58 tmp28 | \--* int V16._sign (offs=0x08) -> V59 tmp29 [000140] ------------ arg1 \--* LCL_VAR int V14 loc11 Initializing arg info for 141.CALL: ArgTable for 141.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 139.ADDR long (By ref), 1 reg: rcx, byteAlignment=8] fgArgTabEntry[arg 1 140.LCL_VAR int (By ref), 1 reg: rdx, byteAlignment=8] Morphing args for 141.CALL: argSlots=2, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000139] -----+------ * ADDR long [000138] ----G+-N---- \--* LCL_VAR struct(AX)(P) V16 loc13 \--* ref V16._bits (offs=0x00) -> V58 tmp28 \--* int V16._sign (offs=0x08) -> V59 tmp29 Replaced with placeholder node: [000650] ----------L- * ARGPLACE long Deferred argument ('rdx'): [000140] -----+------ * LCL_VAR int V14 loc11 Replaced with placeholder node: [000651] ----------L- * ARGPLACE int Shuffled argument table: rcx rdx ArgTable for 141.CALL after fgMorphArgs: fgArgTabEntry[arg 0 139.ADDR long (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed] fgArgTabEntry[arg 1 140.LCL_VAR int (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=1, processed] fgMorphTree BB27, STMT00031 (after) [000141] --CXG+------ * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen [000139] -----+------ arg0 in rcx +--* ADDR long [000138] ----G+-N---- | \--* LCL_VAR struct(AX)(P) V16 loc13 | \--* ref V16._bits (offs=0x00) -> V58 tmp28 | \--* int V16._sign (offs=0x08) -> V59 tmp29 [000140] -----+------ arg1 in rdx \--* LCL_VAR int V14 loc11 fgMorphTree BB27, STMT00099 (before) [000472] -A---------- * ASG struct (copy) [000470] D------N---- +--* LCL_VAR struct(P) V44 tmp14 +--* ref V44._bits (offs=0x00) -> V64 tmp34 +--* int V44._sign (offs=0x08) -> V65 tmp35 [000145] n----------- \--* OBJ struct [000144] ------------ \--* ADDR byref [000142] -------N---- \--* LCL_VAR struct(AX)(P) V15 loc12 \--* ref V15._bits (offs=0x00) -> V56 tmp26 \--* int V15._sign (offs=0x08) -> V57 tmp27 fgMorphCopyBlock: fgMorphBlkNode for dst tree, before: [000470] D----+-N---- * LCL_VAR struct(P) V44 tmp14 * ref V44._bits (offs=0x00) -> V64 tmp34 * int V44._sign (offs=0x08) -> V65 tmp35 fgMorphBlkNode after: [000470] D----+-N---- * LCL_VAR struct(P) V44 tmp14 * ref V44._bits (offs=0x00) -> V64 tmp34 * int V44._sign (offs=0x08) -> V65 tmp35 fgMorphBlkNode for src tree, before: [000145] n---G+------ * OBJ struct [000144] -----+------ \--* ADDR byref [000142] ----G+-N---- \--* LCL_VAR struct(AX)(P) V15 loc12 \--* ref V15._bits (offs=0x00) -> V56 tmp26 \--* int V15._sign (offs=0x08) -> V57 tmp27 fgMorphBlkNode after: [000145] n---G+------ * OBJ struct [000144] -----+------ \--* ADDR byref [000142] ----G+-N---- \--* LCL_VAR struct(AX)(P) V15 loc12 \--* ref V15._bits (offs=0x00) -> V56 tmp26 \--* int V15._sign (offs=0x08) -> V57 tmp27 block assignment to morph: [000472] -A--G------- * ASG struct (copy) [000470] D----+-N---- +--* LCL_VAR struct(P) V44 tmp14 +--* ref V44._bits (offs=0x00) -> V64 tmp34 +--* int V44._sign (offs=0x08) -> V65 tmp35 [000145] n---G+------ \--* OBJ struct [000144] -----+------ \--* ADDR byref [000142] ----G+-N---- \--* LCL_VAR struct(AX)(P) V15 loc12 \--* ref V15._bits (offs=0x00) -> V56 tmp26 \--* int V15._sign (offs=0x08) -> V57 tmp27 (destDoFldAsg=true) (srcDoFldAsg=true) using field by field assignments. fgMorphCopyBlock (after): [000658] -A--G+------ * COMMA void [000654] -A--G------- +--* ASG ref [000652] D------N---- | +--* LCL_VAR ref V64 tmp34 [000653] ----G--N---- | \--* LCL_VAR ref (AX) V56 tmp26 [000657] -A--G------- \--* ASG int [000655] D------N---- +--* LCL_VAR int V65 tmp35 [000656] ----G--N---- \--* LCL_VAR int (AX) V57 tmp27 fgMorphTree BB27, STMT00099 (after) [000658] -A--G+------ * COMMA void [000654] -A--G------- +--* ASG ref [000652] D------N---- | +--* LCL_VAR ref V64 tmp34 [000653] ----G--N---- | \--* LCL_VAR ref (AX) V56 tmp26 [000657] -A--G------- \--* ASG int [000655] D------N---- +--* LCL_VAR int V65 tmp35 [000656] ----G--N---- \--* LCL_VAR int (AX) V57 tmp27 fgMorphTree BB27, STMT00098 (before) [000468] -AC--------- * ASG int [000467] D------N---- +--* LCL_VAR int V43 tmp13 [000463] --C-G------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits [000465] n----------- arg0 +--* OBJ struct [000464] ------------ | \--* ADDR byref [000460] -------N---- | \--* LCL_VAR struct(P) V44 tmp14 | \--* ref V44._bits (offs=0x00) -> V64 tmp34 | \--* int V44._sign (offs=0x08) -> V65 tmp35 [000462] ------------ arg1 \--* LCL_VAR_ADDR byref V45 tmp15 Initializing arg info for 463.CALL: ArgTable for 463.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 465.OBJ struct (By ref), 1 reg: rcx, byteAlignment=8, isStruct] fgArgTabEntry[arg 1 462.LCL_VAR_ADDR long (By ref), 1 reg: rdx, byteAlignment=8] Morphing args for 463.CALL: making an outgoing copy for struct arg reusing outgoing struct argfgMorphCopyBlock: fgMorphBlkNode for dst tree, before: [000659] D------N---- * LCL_VAR struct(AX) V76 tmp46 fgMorphBlkNode after: [000659] D------N---- * LCL_VAR struct(AX) V76 tmp46 fgMorphBlkNode for src tree, before: [000460] -----+-N---- * LCL_VAR struct(P) V44 tmp14 * ref V44._bits (offs=0x00) -> V64 tmp34 * int V44._sign (offs=0x08) -> V65 tmp35 fgMorphBlkNode after: [000460] -----+-N---- * LCL_VAR struct(P) V44 tmp14 * ref V44._bits (offs=0x00) -> V64 tmp34 * int V44._sign (offs=0x08) -> V65 tmp35 block assignment to morph: [000660] -A---------- * ASG struct (copy) [000659] D------N---- +--* LCL_VAR struct(AX) V76 tmp46 [000460] -----+-N---- \--* LCL_VAR struct(P) V44 tmp14 \--* ref V44._bits (offs=0x00) -> V64 tmp34 \--* int V44._sign (offs=0x08) -> V65 tmp35 (srcDoFldAsg=true) using field by field assignments. Local V76 should not be enregistered because: written in a block op lvaGrabTemp returning 81 (V81 tmp51) called for BlockOp address local. Local V76 should not be enregistered because: it is address exposed fgAddFieldSeqForZeroOffset for Fseq[_bits] addr (Before) [000666] ------------ LCL_VAR byref (After) [000666] ------------ LCL_VAR byref Zero Fseq[_bits] fgMorphCopyBlock (after): [000677] -A---+------ * COMMA void [000670] -A---------- +--* COMMA void [000665] -A---------- | +--* ASG byref [000664] D------N---- | | +--* LCL_VAR byref V81 tmp51 [000662] -----+------ | | \--* ADDR byref [000663] ----G+-N---- | | \--* LCL_VAR struct(AX) V76 tmp46 [000669] -A---------- | \--* ASG ref [000667] *------N---- | +--* IND ref [000666] ------------ | | \--* LCL_VAR byref V81 tmp51 Zero Fseq[_bits] [000668] -------N---- | \--* LCL_VAR ref V64 tmp34 [000676] -A---------- \--* ASG int [000674] *------N---- +--* IND int [000673] ------------ | \--* ADD byref [000671] ------------ | +--* LCL_VAR byref V81 tmp51 [000672] ------------ | \--* CNS_INT long 8 Fseq[_sign] [000675] -------N---- \--* LCL_VAR int V65 tmp35 argSlots=2, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Local V76 should not be enregistered because: it is address exposed Deferred argument ('rdx'): [000462] -----+------ * LCL_VAR_ADDR long V45 tmp15 Replaced with placeholder node: [000680] ----------L- * ARGPLACE long Shuffled argument table: rcx rdx ArgTable for 463.CALL after fgMorphArgs: fgArgTabEntry[arg 0 679.ADDR struct (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, tmpNum=V76, isTmp, processed, isStruct] fgArgTabEntry[arg 1 462.LCL_VAR_ADDR long (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=1, processed] fgMorphTree BB27, STMT00098 (after) [000468] -ACXG+------ * ASG int [000467] D----+-N---- +--* LCL_VAR int V43 tmp13 [000463] -ACXG+------ \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits [000677] -A---+----L- arg0 SETUP +--* COMMA void [000670] -A---------- | +--* COMMA void [000665] -A---------- | | +--* ASG byref [000664] D------N---- | | | +--* LCL_VAR byref V81 tmp51 [000662] -----+------ | | | \--* ADDR byref [000663] ----G+-N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 [000669] -A---------- | | \--* ASG ref [000667] *------N---- | | +--* IND ref [000666] ------------ | | | \--* LCL_VAR byref V81 tmp51 Zero Fseq[_bits] [000668] -------N---- | | \--* LCL_VAR ref V64 tmp34 [000676] -A---------- | \--* ASG int [000674] *------N---- | +--* IND int [000673] ------------ | | \--* ADD byref [000671] ------------ | | +--* LCL_VAR byref V81 tmp51 [000672] ------------ | | \--* CNS_INT long 8 Fseq[_sign] [000675] -------N---- | \--* LCL_VAR int V65 tmp35 [000679] ------------ arg0 in rcx +--* ADDR byref [000678] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 [000462] -----+------ arg1 in rdx \--* LCL_VAR_ADDR long V45 tmp15 fgMorphTree BB27, STMT00100 (before) [000475] -A---------- * ASG ref [000474] D------N---- +--* LCL_VAR ref (AX) V45 tmp15 [000473] ------------ \--* CNS_INT ref null fgMorphTree BB27, STMT00033 (before) [000148] -AC--------- * ASG int [000147] D------N---- +--* LCL_VAR int V17 loc14 [000469] ------------ \--* LCL_VAR int V43 tmp13 GenTreeNode creates assertion: [000148] -A---------- * ASG int In BB27 New Local Copy Assertion: V17 == V43 index=#01, mask=0000000000000001 fgMorphTree BB27, STMT00103 (before) [000490] -A---------- * ASG struct (copy) [000488] D------N---- +--* LCL_VAR struct(P) V47 tmp17 +--* ref V47._bits (offs=0x00) -> V66 tmp36 +--* int V47._sign (offs=0x08) -> V67 tmp37 [000152] n----------- \--* OBJ struct [000151] ------------ \--* ADDR byref [000149] -------N---- \--* LCL_VAR struct(AX)(P) V16 loc13 \--* ref V16._bits (offs=0x00) -> V58 tmp28 \--* int V16._sign (offs=0x08) -> V59 tmp29 fgMorphCopyBlock: fgMorphBlkNode for dst tree, before: [000488] D----+-N---- * LCL_VAR struct(P) V47 tmp17 * ref V47._bits (offs=0x00) -> V66 tmp36 * int V47._sign (offs=0x08) -> V67 tmp37 fgMorphBlkNode after: [000488] D----+-N---- * LCL_VAR struct(P) V47 tmp17 * ref V47._bits (offs=0x00) -> V66 tmp36 * int V47._sign (offs=0x08) -> V67 tmp37 fgMorphBlkNode for src tree, before: [000152] n---G+------ * OBJ struct [000151] -----+------ \--* ADDR byref [000149] ----G+-N---- \--* LCL_VAR struct(AX)(P) V16 loc13 \--* ref V16._bits (offs=0x00) -> V58 tmp28 \--* int V16._sign (offs=0x08) -> V59 tmp29 fgMorphBlkNode after: [000152] n---G+------ * OBJ struct [000151] -----+------ \--* ADDR byref [000149] ----G+-N---- \--* LCL_VAR struct(AX)(P) V16 loc13 \--* ref V16._bits (offs=0x00) -> V58 tmp28 \--* int V16._sign (offs=0x08) -> V59 tmp29 block assignment to morph: [000490] -A--G------- * ASG struct (copy) [000488] D----+-N---- +--* LCL_VAR struct(P) V47 tmp17 +--* ref V47._bits (offs=0x00) -> V66 tmp36 +--* int V47._sign (offs=0x08) -> V67 tmp37 [000152] n---G+------ \--* OBJ struct [000151] -----+------ \--* ADDR byref [000149] ----G+-N---- \--* LCL_VAR struct(AX)(P) V16 loc13 \--* ref V16._bits (offs=0x00) -> V58 tmp28 \--* int V16._sign (offs=0x08) -> V59 tmp29 (destDoFldAsg=true) (srcDoFldAsg=true) using field by field assignments. fgMorphCopyBlock (after): [000687] -A--G+------ * COMMA void [000683] -A--G------- +--* ASG ref [000681] D------N---- | +--* LCL_VAR ref V66 tmp36 [000682] ----G--N---- | \--* LCL_VAR ref (AX) V58 tmp28 [000686] -A--G------- \--* ASG int [000684] D------N---- +--* LCL_VAR int V67 tmp37 [000685] ----G--N---- \--* LCL_VAR int (AX) V59 tmp29 fgMorphTree BB27, STMT00103 (after) [000687] -A--G+------ * COMMA void [000683] -A--G------- +--* ASG ref [000681] D------N---- | +--* LCL_VAR ref V66 tmp36 [000682] ----G--N---- | \--* LCL_VAR ref (AX) V58 tmp28 [000686] -A--G------- \--* ASG int [000684] D------N---- +--* LCL_VAR int V67 tmp37 [000685] ----G--N---- \--* LCL_VAR int (AX) V59 tmp29 fgMorphTree BB27, STMT00102 (before) [000486] -AC--------- * ASG int [000485] D------N---- +--* LCL_VAR int V46 tmp16 [000481] --C-G------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits [000483] n----------- arg0 +--* OBJ struct [000482] ------------ | \--* ADDR byref [000478] -------N---- | \--* LCL_VAR struct(P) V47 tmp17 | \--* ref V47._bits (offs=0x00) -> V66 tmp36 | \--* int V47._sign (offs=0x08) -> V67 tmp37 [000480] ------------ arg1 \--* LCL_VAR_ADDR byref V48 tmp18 Initializing arg info for 481.CALL: ArgTable for 481.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 483.OBJ struct (By ref), 1 reg: rcx, byteAlignment=8, isStruct] fgArgTabEntry[arg 1 480.LCL_VAR_ADDR long (By ref), 1 reg: rdx, byteAlignment=8] Morphing args for 481.CALL: making an outgoing copy for struct arg reusing outgoing struct argfgMorphCopyBlock: fgMorphBlkNode for dst tree, before: [000688] D------N---- * LCL_VAR struct(AX) V76 tmp46 fgMorphBlkNode after: [000688] D------N---- * LCL_VAR struct(AX) V76 tmp46 fgMorphBlkNode for src tree, before: [000478] -----+-N---- * LCL_VAR struct(P) V47 tmp17 * ref V47._bits (offs=0x00) -> V66 tmp36 * int V47._sign (offs=0x08) -> V67 tmp37 fgMorphBlkNode after: [000478] -----+-N---- * LCL_VAR struct(P) V47 tmp17 * ref V47._bits (offs=0x00) -> V66 tmp36 * int V47._sign (offs=0x08) -> V67 tmp37 block assignment to morph: [000689] -A---------- * ASG struct (copy) [000688] D------N---- +--* LCL_VAR struct(AX) V76 tmp46 [000478] -----+-N---- \--* LCL_VAR struct(P) V47 tmp17 \--* ref V47._bits (offs=0x00) -> V66 tmp36 \--* int V47._sign (offs=0x08) -> V67 tmp37 (srcDoFldAsg=true) using field by field assignments. Local V76 should not be enregistered because: written in a block op lvaGrabTemp returning 82 (V82 tmp52) called for BlockOp address local. Local V76 should not be enregistered because: it is address exposed fgAddFieldSeqForZeroOffset for Fseq[_bits] addr (Before) [000695] ------------ LCL_VAR byref (After) [000695] ------------ LCL_VAR byref Zero Fseq[_bits] fgMorphCopyBlock (after): [000706] -A---+------ * COMMA void [000699] -A---------- +--* COMMA void [000694] -A---------- | +--* ASG byref [000693] D------N---- | | +--* LCL_VAR byref V82 tmp52 [000691] -----+------ | | \--* ADDR byref [000692] ----G+-N---- | | \--* LCL_VAR struct(AX) V76 tmp46 [000698] -A---------- | \--* ASG ref [000696] *------N---- | +--* IND ref [000695] ------------ | | \--* LCL_VAR byref V82 tmp52 Zero Fseq[_bits] [000697] -------N---- | \--* LCL_VAR ref V66 tmp36 [000705] -A---------- \--* ASG int [000703] *------N---- +--* IND int [000702] ------------ | \--* ADD byref [000700] ------------ | +--* LCL_VAR byref V82 tmp52 [000701] ------------ | \--* CNS_INT long 8 Fseq[_sign] [000704] -------N---- \--* LCL_VAR int V67 tmp37 argSlots=2, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Local V76 should not be enregistered because: it is address exposed Deferred argument ('rdx'): [000480] -----+------ * LCL_VAR_ADDR long V48 tmp18 Replaced with placeholder node: [000709] ----------L- * ARGPLACE long Shuffled argument table: rcx rdx ArgTable for 481.CALL after fgMorphArgs: fgArgTabEntry[arg 0 708.ADDR struct (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, tmpNum=V76, isTmp, processed, isStruct] fgArgTabEntry[arg 1 480.LCL_VAR_ADDR long (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=1, processed] fgMorphTree BB27, STMT00102 (after) [000486] -ACXG+------ * ASG int [000485] D----+-N---- +--* LCL_VAR int V46 tmp16 [000481] -ACXG+------ \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits [000706] -A---+----L- arg0 SETUP +--* COMMA void [000699] -A---------- | +--* COMMA void [000694] -A---------- | | +--* ASG byref [000693] D------N---- | | | +--* LCL_VAR byref V82 tmp52 [000691] -----+------ | | | \--* ADDR byref [000692] ----G+-N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 [000698] -A---------- | | \--* ASG ref [000696] *------N---- | | +--* IND ref [000695] ------------ | | | \--* LCL_VAR byref V82 tmp52 Zero Fseq[_bits] [000697] -------N---- | | \--* LCL_VAR ref V66 tmp36 [000705] -A---------- | \--* ASG int [000703] *------N---- | +--* IND int [000702] ------------ | | \--* ADD byref [000700] ------------ | | +--* LCL_VAR byref V82 tmp52 [000701] ------------ | | \--* CNS_INT long 8 Fseq[_sign] [000704] -------N---- | \--* LCL_VAR int V67 tmp37 [000708] ------------ arg0 in rcx +--* ADDR byref [000707] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 [000480] -----+------ arg1 in rdx \--* LCL_VAR_ADDR long V48 tmp18 fgMorphTree BB27, STMT00104 (before) [000493] -A---------- * ASG ref [000492] D------N---- +--* LCL_VAR ref (AX) V48 tmp18 [000491] ------------ \--* CNS_INT ref null fgMorphTree BB27, STMT00035 (before) [000155] -AC--------- * ASG int [000154] D------N---- +--* LCL_VAR int V18 loc15 [000487] ------------ \--* LCL_VAR int V46 tmp16 GenTreeNode creates assertion: [000155] -A---------- * ASG int In BB27 New Local Copy Assertion: V18 == V46 index=#02, mask=0000000000000002 fgMorphTree BB27, STMT00036 (before) [000159] ------------ * JTRUE void [000158] N--------U-- \--* GT int [000156] ------------ +--* LCL_VAR int V18 loc15 [000157] ------------ \--* LCL_VAR int V17 loc14 Assertion prop in BB27: Copy Assertion: V18 == V46 index=#02, mask=0000000000000002 [000156] ------------ * LCL_VAR int V46 tmp16 Assertion prop in BB27: Copy Assertion: V17 == V43 index=#01, mask=0000000000000001 [000157] ------------ * LCL_VAR int V43 tmp13 fgMorphTree BB27, STMT00036 (after) [000159] -----+------ * JTRUE void [000158] N----+-N-U-- \--* GT int [000156] -----+------ +--* LCL_VAR int V46 tmp16 [000157] -----+------ \--* LCL_VAR int V43 tmp13 Morphing BB28 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB28, STMT00074 (before) [000350] -A---------- * ASG int [000349] D------N---- +--* LCL_VAR int V33 tmp3 [000348] ------------ \--* CNS_INT int 0 GenTreeNode creates assertion: [000350] -A---------- * ASG int In BB28 New Local Constant Assertion: V33 == 0 index=#01, mask=0000000000000001 Morphing BB29 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB29, STMT00037 (before) [000164] -A---------- * ASG int [000163] D------N---- +--* LCL_VAR int V33 tmp3 [000162] ------------ \--* SUB int [000160] ------------ +--* LCL_VAR int V18 loc15 [000161] ------------ \--* LCL_VAR int V17 loc14 Morphing BB30 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB30, STMT00038 (before) [000168] -A---------- * ASG int [000167] D------N---- +--* LCL_VAR int V19 loc16 [000166] ------------ \--* LCL_VAR int V33 tmp3 GenTreeNode creates assertion: [000168] -A---------- * ASG int In BB30 New Local Copy Assertion: V19 == V33 index=#01, mask=0000000000000001 fgMorphTree BB30, STMT00039 (before) [000172] ------------ * JTRUE void [000171] N--------U-- \--* LE int [000169] ------------ +--* LCL_VAR int V19 loc16 [000170] ------------ \--* CNS_INT int 0 Assertion prop in BB30: Copy Assertion: V19 == V33 index=#01, mask=0000000000000001 [000169] ------------ * LCL_VAR int V33 tmp3 fgMorphTree BB30, STMT00039 (after) [000172] -----+------ * JTRUE void [000171] N----+-N---- \--* EQ int [000169] -----+------ +--* LCL_VAR int V33 tmp3 [000170] -----+------ \--* CNS_INT int 0 Morphing BB31 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB31, STMT00073 (before) [000347] --C-G------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft [000345] ------------ arg0 +--* ADDR byref [000344] -------N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 [000346] ------------ arg1 \--* LCL_VAR int V19 loc16 Initializing arg info for 347.CALL: ArgTable for 347.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 345.ADDR long (By ref), 1 reg: rcx, byteAlignment=8] fgArgTabEntry[arg 1 346.LCL_VAR int (By ref), 1 reg: rdx, byteAlignment=8] Morphing args for 347.CALL: argSlots=2, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000345] -----+------ * ADDR long [000344] ----G+-N---- \--* LCL_VAR struct(AX)(P) V15 loc12 \--* ref V15._bits (offs=0x00) -> V56 tmp26 \--* int V15._sign (offs=0x08) -> V57 tmp27 Replaced with placeholder node: [000710] ----------L- * ARGPLACE long Deferred argument ('rdx'): [000346] -----+------ * LCL_VAR int V19 loc16 Replaced with placeholder node: [000711] ----------L- * ARGPLACE int Shuffled argument table: rcx rdx ArgTable for 347.CALL after fgMorphArgs: fgArgTabEntry[arg 0 345.ADDR long (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed] fgArgTabEntry[arg 1 346.LCL_VAR int (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=1, processed] fgMorphTree BB31, STMT00073 (after) [000347] --CXG+------ * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft [000345] -----+------ arg0 in rcx +--* ADDR long [000344] ----G+-N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 [000346] -----+------ arg1 in rdx \--* LCL_VAR int V19 loc16 Morphing BB32 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB32, STMT00040 (before) [000177] -A---------- * ASG int [000176] D------N---- +--* LCL_VAR int V20 loc17 [000175] ------------ \--* SUB int [000173] ------------ +--* LCL_VAR int V03 loc0 [000174] ------------ \--* LCL_VAR int V13 loc10 fgMorphTree BB32, STMT00041 (before) [000180] -A---------- * ASG int [000179] D------N---- +--* LCL_VAR int V21 loc18 [000178] ------------ \--* LCL_VAR int V20 loc17 GenTreeNode creates assertion: [000180] -A---------- * ASG int In BB32 New Local Copy Assertion: V21 == V20 index=#01, mask=0000000000000001 fgMorphTree BB32, STMT00042 (before) [000184] ------------ * JTRUE void [000183] N--------U-- \--* LE int [000181] ------------ +--* LCL_VAR int V13 loc10 [000182] ------------ \--* CNS_INT int 0 fgMorphTree BB32, STMT00042 (after) [000184] -----+------ * JTRUE void [000183] N----+-N---- \--* EQ int [000181] -----+------ +--* LCL_VAR int V13 loc10 [000182] -----+------ \--* CNS_INT int 0 Morphing BB33 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB33, STMT00070 (before) [000329] ------------ * JTRUE void [000328] N--------U-- \--* LE int [000326] ------------ +--* LCL_VAR int V19 loc16 [000327] ------------ \--* LCL_VAR int V21 loc18 Morphing BB34 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB34, STMT00072 (before) [000343] --C-G------- * RETURN int [000342] --C-G------- \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits [000335] ------------ arg0 +--* LCL_VAR ref (AX) V12 loc9 [000336] ------------ arg1 +--* LCL_VAR int V13 loc10 [000339] N--------U-- arg2 +--* GT int [000337] ------------ | +--* LCL_VAR int V10 loc7 [000338] ------------ | \--* CNS_INT int 0 [000340] ------------ arg3 +--* LCL_VAR ref V01 arg1 [000341] ------------ arg4 \--* LCL_VAR byref V02 arg2 Rejecting tail call in morph for call [000342]: Local address taken V11 Initializing arg info for 342.CALL: ArgTable for 342.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 335.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8] fgArgTabEntry[arg 1 336.LCL_VAR int (By ref), 1 reg: rdx, byteAlignment=8] fgArgTabEntry[arg 2 339.GT int (By ref), 1 reg: r8, byteAlignment=8] fgArgTabEntry[arg 3 340.LCL_VAR ref (By ref), 1 reg: r9, byteAlignment=8] fgArgTabEntry[arg 4 341.LCL_VAR byref (By ref), numSlots=1, slotNum=4, byteSize=8, byteOffset=32, byteAlignment=8] Morphing args for 342.CALL: argSlots=5, preallocatedArgCount=5, nextSlotNum=5, nextSlotByteOffset=40, outgoingArgSpaceSize=40 Sorting the arguments: Deferred argument ('r8'): [000339] N----+------ * NE int [000337] -----+------ +--* LCL_VAR int V10 loc7 [000338] -----+------ \--* CNS_INT int 0 Replaced with placeholder node: [000712] ----------L- * ARGPLACE int Deferred argument ('rcx'): [000335] ----G+------ * LCL_VAR ref (AX) V12 loc9 Replaced with placeholder node: [000713] ----------L- * ARGPLACE ref Deferred argument ('rdx'): [000336] -----+------ * LCL_VAR int V13 loc10 Replaced with placeholder node: [000714] ----------L- * ARGPLACE int Deferred argument ('r9'): [000340] -----+------ * LCL_VAR ref V01 arg1 Replaced with placeholder node: [000715] ----------L- * ARGPLACE ref Shuffled argument table: r8 rcx rdx r9 ArgTable for 342.CALL after fgMorphArgs: fgArgTabEntry[arg 2 339.NE int (By ref), 1 reg: r8, byteAlignment=8, lateArgInx=0, processed] fgArgTabEntry[arg 0 335.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=1, processed] fgArgTabEntry[arg 1 336.LCL_VAR int (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=2, processed] fgArgTabEntry[arg 3 340.LCL_VAR ref (By ref), 1 reg: r9, byteAlignment=8, lateArgInx=3, processed] fgArgTabEntry[arg 4 341.LCL_VAR byref (By ref), numSlots=1, slotNum=4, byteSize=8, byteOffset=32, byteAlignment=8, processed] fgMorphTree BB34, STMT00072 (after) [000343] --CXG+------ * RETURN int [000342] --CXG+------ \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits [000341] -----+------ arg4 out+20 +--* LCL_VAR byref V02 arg2 [000339] N----+------ arg2 in r8 +--* NE int [000337] -----+------ | +--* LCL_VAR int V10 loc7 [000338] -----+------ | \--* CNS_INT int 0 [000335] ----G+------ arg0 in rcx +--* LCL_VAR ref (AX) V12 loc9 [000336] -----+------ arg1 in rdx +--* LCL_VAR int V13 loc10 [000340] -----+------ arg3 in r9 \--* LCL_VAR ref V01 arg1 morph BB34 to point at onereturn. New block is BB34 [0022] 1 BB33 1 [144..155)-> BB48 (always) i hascall gcsafe Morphing BB35 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB35, STMT00071 (before) [000334] -A---------- * ASG int [000333] D------N---- +--* LCL_VAR int V21 loc18 [000332] ------------ \--* SUB int [000330] ------------ +--* LCL_VAR int V21 loc18 [000331] ------------ \--* LCL_VAR int V19 loc16 Morphing BB36 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB36, STMT00105 (before) [000506] -A---------- * ASG struct (copy) [000504] D------N---- +--* LCL_VAR struct(AX)(P) V49 tmp19 +--* ref V49._bits (offs=0x00) -> V68 tmp38 +--* int V49._sign (offs=0x08) -> V69 tmp39 [000191] n----------- \--* OBJ struct [000190] ------------ \--* ADDR byref [000185] -------N---- \--* LCL_VAR struct(AX)(P) V15 loc12 \--* ref V15._bits (offs=0x00) -> V56 tmp26 \--* int V15._sign (offs=0x08) -> V57 tmp27 fgMorphCopyBlock: fgMorphBlkNode for dst tree, before: [000504] D---G+-N---- * LCL_VAR struct(AX)(P) V49 tmp19 * ref V49._bits (offs=0x00) -> V68 tmp38 * int V49._sign (offs=0x08) -> V69 tmp39 fgMorphBlkNode after: [000504] D---G+-N---- * LCL_VAR struct(AX)(P) V49 tmp19 * ref V49._bits (offs=0x00) -> V68 tmp38 * int V49._sign (offs=0x08) -> V69 tmp39 fgMorphBlkNode for src tree, before: [000191] n---G+------ * OBJ struct [000190] -----+------ \--* ADDR byref [000185] ----G+-N---- \--* LCL_VAR struct(AX)(P) V15 loc12 \--* ref V15._bits (offs=0x00) -> V56 tmp26 \--* int V15._sign (offs=0x08) -> V57 tmp27 fgMorphBlkNode after: [000191] n---G+------ * OBJ struct [000190] -----+------ \--* ADDR byref [000185] ----G+-N---- \--* LCL_VAR struct(AX)(P) V15 loc12 \--* ref V15._bits (offs=0x00) -> V56 tmp26 \--* int V15._sign (offs=0x08) -> V57 tmp27 block assignment to morph: [000506] -A--G------- * ASG struct (copy) [000504] D---G+-N---- +--* LCL_VAR struct(AX)(P) V49 tmp19 +--* ref V49._bits (offs=0x00) -> V68 tmp38 +--* int V49._sign (offs=0x08) -> V69 tmp39 [000191] n---G+------ \--* OBJ struct [000190] -----+------ \--* ADDR byref [000185] ----G+-N---- \--* LCL_VAR struct(AX)(P) V15 loc12 \--* ref V15._bits (offs=0x00) -> V56 tmp26 \--* int V15._sign (offs=0x08) -> V57 tmp27 (destDoFldAsg=true) (srcDoFldAsg=true) using field by field assignments. fgMorphCopyBlock (after): [000724] -A--G+------ * COMMA void [000720] -A--G------- +--* ASG ref [000718] D---G--N---- | +--* LCL_VAR ref (AX) V68 tmp38 [000719] ----G--N---- | \--* LCL_VAR ref (AX) V56 tmp26 [000723] -A--G------- \--* ASG int [000721] D---G--N---- +--* LCL_VAR int (AX) V69 tmp39 [000722] ----G--N---- \--* LCL_VAR int (AX) V57 tmp27 fgMorphTree BB36, STMT00105 (after) [000724] -A--G+------ * COMMA void [000720] -A--G------- +--* ASG ref [000718] D---G--N---- | +--* LCL_VAR ref (AX) V68 tmp38 [000719] ----G--N---- | \--* LCL_VAR ref (AX) V56 tmp26 [000723] -A--G------- \--* ASG int [000721] D---G--N---- +--* LCL_VAR int (AX) V69 tmp39 [000722] ----G--N---- \--* LCL_VAR int (AX) V57 tmp27 fgMorphTree BB36, STMT00106 (before) [000509] -A---------- * ASG struct (copy) [000507] D------N---- +--* LCL_VAR struct(P) V50 tmp20 +--* ref V50._bits (offs=0x00) -> V70 tmp40 +--* int V50._sign (offs=0x08) -> V71 tmp41 [000189] n----------- \--* OBJ struct [000188] ------------ \--* ADDR byref [000186] -------N---- \--* LCL_VAR struct(AX)(P) V16 loc13 \--* ref V16._bits (offs=0x00) -> V58 tmp28 \--* int V16._sign (offs=0x08) -> V59 tmp29 fgMorphCopyBlock: fgMorphBlkNode for dst tree, before: [000507] D----+-N---- * LCL_VAR struct(P) V50 tmp20 * ref V50._bits (offs=0x00) -> V70 tmp40 * int V50._sign (offs=0x08) -> V71 tmp41 fgMorphBlkNode after: [000507] D----+-N---- * LCL_VAR struct(P) V50 tmp20 * ref V50._bits (offs=0x00) -> V70 tmp40 * int V50._sign (offs=0x08) -> V71 tmp41 fgMorphBlkNode for src tree, before: [000189] n---G+------ * OBJ struct [000188] -----+------ \--* ADDR byref [000186] ----G+-N---- \--* LCL_VAR struct(AX)(P) V16 loc13 \--* ref V16._bits (offs=0x00) -> V58 tmp28 \--* int V16._sign (offs=0x08) -> V59 tmp29 fgMorphBlkNode after: [000189] n---G+------ * OBJ struct [000188] -----+------ \--* ADDR byref [000186] ----G+-N---- \--* LCL_VAR struct(AX)(P) V16 loc13 \--* ref V16._bits (offs=0x00) -> V58 tmp28 \--* int V16._sign (offs=0x08) -> V59 tmp29 block assignment to morph: [000509] -A--G------- * ASG struct (copy) [000507] D----+-N---- +--* LCL_VAR struct(P) V50 tmp20 +--* ref V50._bits (offs=0x00) -> V70 tmp40 +--* int V50._sign (offs=0x08) -> V71 tmp41 [000189] n---G+------ \--* OBJ struct [000188] -----+------ \--* ADDR byref [000186] ----G+-N---- \--* LCL_VAR struct(AX)(P) V16 loc13 \--* ref V16._bits (offs=0x00) -> V58 tmp28 \--* int V16._sign (offs=0x08) -> V59 tmp29 (destDoFldAsg=true) (srcDoFldAsg=true) using field by field assignments. fgMorphCopyBlock (after): [000731] -A--G+------ * COMMA void [000727] -A--G------- +--* ASG ref [000725] D------N---- | +--* LCL_VAR ref V70 tmp40 [000726] ----G--N---- | \--* LCL_VAR ref (AX) V58 tmp28 [000730] -A--G------- \--* ASG int [000728] D------N---- +--* LCL_VAR int V71 tmp41 [000729] ----G--N---- \--* LCL_VAR int (AX) V59 tmp29 fgMorphTree BB36, STMT00106 (after) [000731] -A--G+------ * COMMA void [000727] -A--G------- +--* ASG ref [000725] D------N---- | +--* LCL_VAR ref V70 tmp40 [000726] ----G--N---- | \--* LCL_VAR ref (AX) V58 tmp28 [000730] -A--G------- \--* ASG int [000728] D------N---- +--* LCL_VAR int V71 tmp41 [000729] ----G--N---- \--* LCL_VAR int (AX) V59 tmp29 fgMorphTree BB36, STMT00044 (before) [000195] --C--------- * JTRUE void [000194] --C--------- \--* NE int [000503] --C-G------- +--* LT int [000499] --C-G------- | +--* CALL int System.Numerics.BigInteger.CompareTo [000497] ------------ this in rcx | | +--* ADDR byref [000496] -------N---- | | | \--* LCL_VAR struct(AX)(P) V49 tmp19 | | | \--* ref V49._bits (offs=0x00) -> V68 tmp38 | | | \--* int V49._sign (offs=0x08) -> V69 tmp39 [000501] n----------- arg1 | | \--* OBJ struct [000500] ------------ | | \--* ADDR byref [000498] -------N---- | | \--* LCL_VAR struct(P) V50 tmp20 | | \--* ref V50._bits (offs=0x00) -> V70 tmp40 | | \--* int V50._sign (offs=0x08) -> V71 tmp41 [000502] ------------ | \--* CNS_INT int 0 [000193] ------------ \--* CNS_INT int 0 Initializing arg info for 499.CALL: ArgTable for 499.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 497.ADDR byref (By ref), 1 reg: rcx, byteAlignment=8] fgArgTabEntry[arg 1 501.OBJ struct (By ref), 1 reg: rdx, byteAlignment=8, isStruct] Morphing args for 499.CALL: making an outgoing copy for struct arg reusing outgoing struct argfgMorphCopyBlock: fgMorphBlkNode for dst tree, before: [000732] D------N---- * LCL_VAR struct(AX) V76 tmp46 fgMorphBlkNode after: [000732] D------N---- * LCL_VAR struct(AX) V76 tmp46 fgMorphBlkNode for src tree, before: [000498] -----+-N---- * LCL_VAR struct(P) V50 tmp20 * ref V50._bits (offs=0x00) -> V70 tmp40 * int V50._sign (offs=0x08) -> V71 tmp41 fgMorphBlkNode after: [000498] -----+-N---- * LCL_VAR struct(P) V50 tmp20 * ref V50._bits (offs=0x00) -> V70 tmp40 * int V50._sign (offs=0x08) -> V71 tmp41 block assignment to morph: [000733] -A---------- * ASG struct (copy) [000732] D------N---- +--* LCL_VAR struct(AX) V76 tmp46 [000498] -----+-N---- \--* LCL_VAR struct(P) V50 tmp20 \--* ref V50._bits (offs=0x00) -> V70 tmp40 \--* int V50._sign (offs=0x08) -> V71 tmp41 (srcDoFldAsg=true) using field by field assignments. Local V76 should not be enregistered because: written in a block op lvaGrabTemp returning 83 (V83 tmp53) called for BlockOp address local. Local V76 should not be enregistered because: it is address exposed fgAddFieldSeqForZeroOffset for Fseq[_bits] addr (Before) [000739] ------------ LCL_VAR byref (After) [000739] ------------ LCL_VAR byref Zero Fseq[_bits] fgMorphCopyBlock (after): [000750] -A---+------ * COMMA void [000743] -A---------- +--* COMMA void [000738] -A---------- | +--* ASG byref [000737] D------N---- | | +--* LCL_VAR byref V83 tmp53 [000735] -----+------ | | \--* ADDR byref [000736] ----G+-N---- | | \--* LCL_VAR struct(AX) V76 tmp46 [000742] -A---------- | \--* ASG ref [000740] *------N---- | +--* IND ref [000739] ------------ | | \--* LCL_VAR byref V83 tmp53 Zero Fseq[_bits] [000741] -------N---- | \--* LCL_VAR ref V70 tmp40 [000749] -A---------- \--* ASG int [000747] *------N---- +--* IND int [000746] ------------ | \--* ADD byref [000744] ------------ | +--* LCL_VAR byref V83 tmp53 [000745] ------------ | \--* CNS_INT long 8 Fseq[_sign] [000748] -------N---- \--* LCL_VAR int V71 tmp41 argSlots=2, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Argument with 'side effect'... [000497] -----+------ * ADDR byref [000496] ----G+-N---- \--* LCL_VAR struct(AX)(P) V49 tmp19 \--* ref V49._bits (offs=0x00) -> V68 tmp38 \--* int V49._sign (offs=0x08) -> V69 tmp39 lvaGrabTemp returning 84 (V84 tmp54) called for argument with side effect. Evaluate to a temp: [000752] -A--------L- * ASG byref [000751] D------N---- +--* LCL_VAR byref V84 tmp54 [000497] -----+------ \--* ADDR byref [000496] ----G+-N---- \--* LCL_VAR struct(AX)(P) V49 tmp19 \--* ref V49._bits (offs=0x00) -> V68 tmp38 \--* int V49._sign (offs=0x08) -> V69 tmp39 Local V76 should not be enregistered because: it is address exposed Shuffled argument table: rcx rdx ArgTable for 499.CALL after fgMorphArgs: fgArgTabEntry[arg 0 753.LCL_VAR byref (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, tmpNum=V84, isTmp, processed] fgArgTabEntry[arg 1 755.ADDR struct (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=1, tmpNum=V76, isTmp, processed, isStruct] fgMorphTree BB36, STMT00044 (after) [000195] -ACXG+------ * JTRUE void [000503] JACXG+-N---- \--* LT int [000499] -ACXG+------ +--* CALL int System.Numerics.BigInteger.CompareTo [000752] -A--------L- this SETUP | +--* ASG byref [000751] D------N---- | | +--* LCL_VAR byref V84 tmp54 [000497] -----+------ | | \--* ADDR byref [000496] ----G+-N---- | | \--* LCL_VAR struct(AX)(P) V49 tmp19 | | \--* ref V49._bits (offs=0x00) -> V68 tmp38 | | \--* int V49._sign (offs=0x08) -> V69 tmp39 [000750] -A---+----L- arg1 SETUP | +--* COMMA void [000743] -A---------- | | +--* COMMA void [000738] -A---------- | | | +--* ASG byref [000737] D------N---- | | | | +--* LCL_VAR byref V83 tmp53 [000735] -----+------ | | | | \--* ADDR byref [000736] ----G+-N---- | | | | \--* LCL_VAR struct(AX) V76 tmp46 [000742] -A---------- | | | \--* ASG ref [000740] *------N---- | | | +--* IND ref [000739] ------------ | | | | \--* LCL_VAR byref V83 tmp53 Zero Fseq[_bits] [000741] -------N---- | | | \--* LCL_VAR ref V70 tmp40 [000749] -A---------- | | \--* ASG int [000747] *------N---- | | +--* IND int [000746] ------------ | | | \--* ADD byref [000744] ------------ | | | +--* LCL_VAR byref V83 tmp53 [000745] ------------ | | | \--* CNS_INT long 8 Fseq[_sign] [000748] -------N---- | | \--* LCL_VAR int V71 tmp41 [000753] ------------ this in rcx | +--* LCL_VAR byref V84 tmp54 [000755] ------------ arg1 in rdx | \--* ADDR byref [000754] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 [000502] -----+------ \--* CNS_INT int 0 Morphing BB37 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB37, STMT00069 (before) [000324] -A---------- * ASG int [000323] D------N---- +--* LCL_VAR int V34 tmp4 [000322] ------------ \--* LCL_VAR int V19 loc16 GenTreeNode creates assertion: [000324] -A---------- * ASG int In BB37 New Local Copy Assertion: V34 == V19 index=#01, mask=0000000000000001 Morphing BB38 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB38, STMT00045 (before) [000200] -A---------- * ASG int [000199] D------N---- +--* LCL_VAR int V34 tmp4 [000198] ------------ \--* ADD int [000196] ------------ +--* LCL_VAR int V19 loc16 [000197] ------------ \--* CNS_INT int 1 Morphing BB39 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB39, STMT00046 (before) [000204] -A---------- * ASG int [000203] D------N---- +--* LCL_VAR int V22 loc19 [000202] ------------ \--* LCL_VAR int V34 tmp4 GenTreeNode creates assertion: [000204] -A---------- * ASG int In BB39 New Local Copy Assertion: V22 == V34 index=#01, mask=0000000000000001 fgMorphTree BB39, STMT00047 (before) [000208] --C-G------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft [000206] ------------ arg0 +--* ADDR byref [000205] -------N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 [000207] ------------ arg1 \--* LCL_VAR int V21 loc18 Initializing arg info for 208.CALL: ArgTable for 208.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 206.ADDR long (By ref), 1 reg: rcx, byteAlignment=8] fgArgTabEntry[arg 1 207.LCL_VAR int (By ref), 1 reg: rdx, byteAlignment=8] Morphing args for 208.CALL: argSlots=2, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000206] -----+------ * ADDR long [000205] ----G+-N---- \--* LCL_VAR struct(AX)(P) V15 loc12 \--* ref V15._bits (offs=0x00) -> V56 tmp26 \--* int V15._sign (offs=0x08) -> V57 tmp27 Replaced with placeholder node: [000756] ----------L- * ARGPLACE long Deferred argument ('rdx'): [000207] -----+------ * LCL_VAR int V21 loc18 Replaced with placeholder node: [000757] ----------L- * ARGPLACE int Shuffled argument table: rcx rdx ArgTable for 208.CALL after fgMorphArgs: fgArgTabEntry[arg 0 206.ADDR long (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed] fgArgTabEntry[arg 1 207.LCL_VAR int (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=1, processed] fgMorphTree BB39, STMT00047 (after) [000208] --CXG+------ * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft [000206] -----+------ arg0 in rcx +--* ADDR long [000205] ----G+-N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 [000207] -----+------ arg1 in rdx \--* LCL_VAR int V21 loc18 fgMorphTree BB39, STMT00048 (before) [000213] S-C-G------- * CALL void System.Numerics.BigInteger.DivRem [000220] ------------ arg0 +--* ADDR byref [000219] -------N---- | \--* LCL_VAR struct(AX)(P) V35 tmp5 | \--* ref V35._bits (offs=0x00) -> V62 tmp32 | \--* int V35._sign (offs=0x08) -> V63 tmp33 [000217] n----------- arg1 +--* OBJ struct [000216] ------------ | \--* ADDR byref [000209] -------N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 [000215] n----------- arg2 +--* OBJ struct [000214] ------------ | \--* ADDR byref [000210] -------N---- | \--* LCL_VAR struct(AX)(P) V16 loc13 | \--* ref V16._bits (offs=0x00) -> V58 tmp28 | \--* int V16._sign (offs=0x08) -> V59 tmp29 [000212] ------------ arg3 \--* ADDR byref [000211] -------N---- \--* LCL_VAR struct(AX)(P) V23 loc20 \--* ref V23._bits (offs=0x00) -> V60 tmp30 \--* int V23._sign (offs=0x08) -> V61 tmp31 Initializing arg info for 213.CALL: ArgTable for 213.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 220.ADDR long (By ref), 1 reg: rcx, byteAlignment=8] fgArgTabEntry[arg 1 217.OBJ struct (By ref), 1 reg: rdx, byteAlignment=8, isStruct] fgArgTabEntry[arg 2 215.OBJ struct (By ref), 1 reg: r8, byteAlignment=8, isStruct] fgArgTabEntry[arg 3 212.ADDR long (By ref), 1 reg: r9, byteAlignment=8] Morphing args for 213.CALL: making an outgoing copy for struct arg reusing outgoing struct argfgMorphCopyBlock: fgMorphBlkNode for dst tree, before: [000758] D------N---- * LCL_VAR struct(AX) V76 tmp46 fgMorphBlkNode after: [000758] D------N---- * LCL_VAR struct(AX) V76 tmp46 fgMorphBlkNode for src tree, before: [000209] ----G+-N---- * LCL_VAR struct(AX)(P) V15 loc12 * ref V15._bits (offs=0x00) -> V56 tmp26 * int V15._sign (offs=0x08) -> V57 tmp27 fgMorphBlkNode after: [000209] ----G+-N---- * LCL_VAR struct(AX)(P) V15 loc12 * ref V15._bits (offs=0x00) -> V56 tmp26 * int V15._sign (offs=0x08) -> V57 tmp27 block assignment to morph: [000759] -A--G------- * ASG struct (copy) [000758] D------N---- +--* LCL_VAR struct(AX) V76 tmp46 [000209] ----G+-N---- \--* LCL_VAR struct(AX)(P) V15 loc12 \--* ref V15._bits (offs=0x00) -> V56 tmp26 \--* int V15._sign (offs=0x08) -> V57 tmp27 (srcDoFldAsg=true) using field by field assignments. Local V76 should not be enregistered because: written in a block op lvaGrabTemp returning 85 (V85 tmp55) called for BlockOp address local. Local V76 should not be enregistered because: it is address exposed fgAddFieldSeqForZeroOffset for Fseq[_bits] addr (Before) [000765] ------------ LCL_VAR byref (After) [000765] ------------ LCL_VAR byref Zero Fseq[_bits] fgMorphCopyBlock (after): [000776] -A--G+------ * COMMA void [000769] -A--G------- +--* COMMA void [000764] -A---------- | +--* ASG byref [000763] D------N---- | | +--* LCL_VAR byref V85 tmp55 [000761] -----+------ | | \--* ADDR byref [000762] ----G+-N---- | | \--* LCL_VAR struct(AX) V76 tmp46 [000768] -A--G------- | \--* ASG ref [000766] *------N---- | +--* IND ref [000765] ------------ | | \--* LCL_VAR byref V85 tmp55 Zero Fseq[_bits] [000767] ----G--N---- | \--* LCL_VAR ref (AX) V56 tmp26 [000775] -A--G------- \--* ASG int [000773] *------N---- +--* IND int [000772] ------------ | \--* ADD byref [000770] ------------ | +--* LCL_VAR byref V85 tmp55 [000771] ------------ | \--* CNS_INT long 8 Fseq[_sign] [000774] ----G--N---- \--* LCL_VAR int (AX) V57 tmp27 making an outgoing copy for struct arg lvaGrabTemp returning 86 (V86 tmp56) called for by-value struct argument. fgMorphCopyBlock: fgMorphBlkNode for dst tree, before: [000777] D------N---- * LCL_VAR struct V86 tmp56 fgMorphBlkNode after: [000777] D------N---- * LCL_VAR struct V86 tmp56 fgMorphBlkNode for src tree, before: [000210] ----G+-N---- * LCL_VAR struct(AX)(P) V16 loc13 * ref V16._bits (offs=0x00) -> V58 tmp28 * int V16._sign (offs=0x08) -> V59 tmp29 fgMorphBlkNode after: [000210] ----G+-N---- * LCL_VAR struct(AX)(P) V16 loc13 * ref V16._bits (offs=0x00) -> V58 tmp28 * int V16._sign (offs=0x08) -> V59 tmp29 block assignment to morph: [000778] -A--G------- * ASG struct (copy) [000777] D------N---- +--* LCL_VAR struct V86 tmp56 [000210] ----G+-N---- \--* LCL_VAR struct(AX)(P) V16 loc13 \--* ref V16._bits (offs=0x00) -> V58 tmp28 \--* int V16._sign (offs=0x08) -> V59 tmp29 (srcDoFldAsg=true) using field by field assignments. Local V86 should not be enregistered because: written in a block op lvaGrabTemp returning 87 (V87 tmp57) called for BlockOp address local. Local V86 should not be enregistered because: it is address exposed fgAddFieldSeqForZeroOffset for Fseq[_bits] addr (Before) [000784] ------------ LCL_VAR byref (After) [000784] ------------ LCL_VAR byref Zero Fseq[_bits] fgMorphCopyBlock (after): [000795] -A--G+------ * COMMA void [000788] -A--G------- +--* COMMA void [000783] -A---------- | +--* ASG byref [000782] D------N---- | | +--* LCL_VAR byref V87 tmp57 [000780] -----+------ | | \--* ADDR byref [000781] -----+-N---- | | \--* LCL_VAR struct(AX) V86 tmp56 [000787] -A--G------- | \--* ASG ref [000785] *------N---- | +--* IND ref [000784] ------------ | | \--* LCL_VAR byref V87 tmp57 Zero Fseq[_bits] [000786] ----G--N---- | \--* LCL_VAR ref (AX) V58 tmp28 [000794] -A--G------- \--* ASG int [000792] *------N---- +--* IND int [000791] ------------ | \--* ADD byref [000789] ------------ | +--* LCL_VAR byref V87 tmp57 [000790] ------------ | \--* CNS_INT long 8 Fseq[_sign] [000793] ----G--N---- \--* LCL_VAR int (AX) V59 tmp29 argSlots=4, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Argument with 'side effect'... [000220] -----+------ * ADDR long [000219] ----G+-N---- \--* LCL_VAR struct(AX)(P) V35 tmp5 \--* ref V35._bits (offs=0x00) -> V62 tmp32 \--* int V35._sign (offs=0x08) -> V63 tmp33 lvaGrabTemp returning 88 (V88 tmp58) called for argument with side effect. Evaluate to a temp: [000797] -A--------L- * ASG long [000796] D------N---- +--* LCL_VAR long V88 tmp58 [000220] -----+------ \--* ADDR long [000219] ----G+-N---- \--* LCL_VAR struct(AX)(P) V35 tmp5 \--* ref V35._bits (offs=0x00) -> V62 tmp32 \--* int V35._sign (offs=0x08) -> V63 tmp33 Local V76 should not be enregistered because: it is address exposed Local V86 should not be enregistered because: it is address exposed Deferred argument ('r9'): [000212] -----+------ * ADDR long [000211] ----G+-N---- \--* LCL_VAR struct(AX)(P) V23 loc20 \--* ref V23._bits (offs=0x00) -> V60 tmp30 \--* int V23._sign (offs=0x08) -> V61 tmp31 Replaced with placeholder node: [000803] ----------L- * ARGPLACE long Shuffled argument table: rcx rdx r8 r9 ArgTable for 213.CALL after fgMorphArgs: fgArgTabEntry[arg 0 798.LCL_VAR long (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, tmpNum=V88, isTmp, processed] fgArgTabEntry[arg 1 800.ADDR struct (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=1, tmpNum=V76, isTmp, processed, isStruct] fgArgTabEntry[arg 2 802.ADDR struct (By ref), 1 reg: r8, byteAlignment=8, lateArgInx=2, tmpNum=V86, isTmp, processed, isStruct] fgArgTabEntry[arg 3 212.ADDR long (By ref), 1 reg: r9, byteAlignment=8, lateArgInx=3, processed] fgMorphTree BB39, STMT00048 (after) [000213] SACXG+------ * CALL void System.Numerics.BigInteger.DivRem [000797] -A--------L- arg0 SETUP +--* ASG long [000796] D------N---- | +--* LCL_VAR long V88 tmp58 [000220] -----+------ | \--* ADDR long [000219] ----G+-N---- | \--* LCL_VAR struct(AX)(P) V35 tmp5 | \--* ref V35._bits (offs=0x00) -> V62 tmp32 | \--* int V35._sign (offs=0x08) -> V63 tmp33 [000776] -A--G+----L- arg1 SETUP +--* COMMA void [000769] -A--G------- | +--* COMMA void [000764] -A---------- | | +--* ASG byref [000763] D------N---- | | | +--* LCL_VAR byref V85 tmp55 [000761] -----+------ | | | \--* ADDR byref [000762] ----G+-N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 [000768] -A--G------- | | \--* ASG ref [000766] *------N---- | | +--* IND ref [000765] ------------ | | | \--* LCL_VAR byref V85 tmp55 Zero Fseq[_bits] [000767] ----G--N---- | | \--* LCL_VAR ref (AX) V56 tmp26 [000775] -A--G------- | \--* ASG int [000773] *------N---- | +--* IND int [000772] ------------ | | \--* ADD byref [000770] ------------ | | +--* LCL_VAR byref V85 tmp55 [000771] ------------ | | \--* CNS_INT long 8 Fseq[_sign] [000774] ----G--N---- | \--* LCL_VAR int (AX) V57 tmp27 [000795] -A--G+----L- arg2 SETUP +--* COMMA void [000788] -A--G------- | +--* COMMA void [000783] -A---------- | | +--* ASG byref [000782] D------N---- | | | +--* LCL_VAR byref V87 tmp57 [000780] -----+------ | | | \--* ADDR byref [000781] -----+-N---- | | | \--* LCL_VAR struct(AX) V86 tmp56 [000787] -A--G------- | | \--* ASG ref [000785] *------N---- | | +--* IND ref [000784] ------------ | | | \--* LCL_VAR byref V87 tmp57 Zero Fseq[_bits] [000786] ----G--N---- | | \--* LCL_VAR ref (AX) V58 tmp28 [000794] -A--G------- | \--* ASG int [000792] *------N---- | +--* IND int [000791] ------------ | | \--* ADD byref [000789] ------------ | | +--* LCL_VAR byref V87 tmp57 [000790] ------------ | | \--* CNS_INT long 8 Fseq[_sign] [000793] ----G--N---- | \--* LCL_VAR int (AX) V59 tmp29 [000798] ------------ arg0 in rcx +--* LCL_VAR long V88 tmp58 [000800] ------------ arg1 in rdx +--* ADDR byref [000799] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 [000802] ------------ arg2 in r8 +--* ADDR byref [000801] -------N---- | \--* LCL_VAR struct(AX) V86 tmp56 [000212] -----+------ arg3 in r9 \--* ADDR long [000211] ----G+-N---- \--* LCL_VAR struct(AX)(P) V23 loc20 \--* ref V23._bits (offs=0x00) -> V60 tmp30 \--* int V23._sign (offs=0x08) -> V61 tmp31 fgMorphTree BB39, STMT00050 (before) [000226] -AC--------- * ASG long [000225] D------N---- +--* LCL_VAR long V24 loc21 [000218] --C-G------- \--* CALL long System.Numerics.BigInteger.op_Explicit [000223] n----------- arg0 \--* OBJ struct [000222] ------------ \--* ADDR byref [000221] -------N---- \--* LCL_VAR struct(AX)(P) V35 tmp5 \--* ref V35._bits (offs=0x00) -> V62 tmp32 \--* int V35._sign (offs=0x08) -> V63 tmp33 Initializing arg info for 218.CALL: ArgTable for 218.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 223.OBJ struct (By ref), 1 reg: rcx, byteAlignment=8, isStruct] Morphing args for 218.CALL: making an outgoing copy for struct arg reusing outgoing struct argfgMorphCopyBlock: fgMorphBlkNode for dst tree, before: [000804] D------N---- * LCL_VAR struct(AX) V76 tmp46 fgMorphBlkNode after: [000804] D------N---- * LCL_VAR struct(AX) V76 tmp46 fgMorphBlkNode for src tree, before: [000221] ----G+-N---- * LCL_VAR struct(AX)(P) V35 tmp5 * ref V35._bits (offs=0x00) -> V62 tmp32 * int V35._sign (offs=0x08) -> V63 tmp33 fgMorphBlkNode after: [000221] ----G+-N---- * LCL_VAR struct(AX)(P) V35 tmp5 * ref V35._bits (offs=0x00) -> V62 tmp32 * int V35._sign (offs=0x08) -> V63 tmp33 block assignment to morph: [000805] -A--G------- * ASG struct (copy) [000804] D------N---- +--* LCL_VAR struct(AX) V76 tmp46 [000221] ----G+-N---- \--* LCL_VAR struct(AX)(P) V35 tmp5 \--* ref V35._bits (offs=0x00) -> V62 tmp32 \--* int V35._sign (offs=0x08) -> V63 tmp33 (srcDoFldAsg=true) using field by field assignments. Local V76 should not be enregistered because: written in a block op lvaGrabTemp returning 89 (V89 tmp59) called for BlockOp address local. Local V76 should not be enregistered because: it is address exposed fgAddFieldSeqForZeroOffset for Fseq[_bits] addr (Before) [000811] ------------ LCL_VAR byref (After) [000811] ------------ LCL_VAR byref Zero Fseq[_bits] fgMorphCopyBlock (after): [000822] -A--G+------ * COMMA void [000815] -A--G------- +--* COMMA void [000810] -A---------- | +--* ASG byref [000809] D------N---- | | +--* LCL_VAR byref V89 tmp59 [000807] -----+------ | | \--* ADDR byref [000808] ----G+-N---- | | \--* LCL_VAR struct(AX) V76 tmp46 [000814] -A--G------- | \--* ASG ref [000812] *------N---- | +--* IND ref [000811] ------------ | | \--* LCL_VAR byref V89 tmp59 Zero Fseq[_bits] [000813] ----G--N---- | \--* LCL_VAR ref (AX) V62 tmp32 [000821] -A--G------- \--* ASG int [000819] *------N---- +--* IND int [000818] ------------ | \--* ADD byref [000816] ------------ | +--* LCL_VAR byref V89 tmp59 [000817] ------------ | \--* CNS_INT long 8 Fseq[_sign] [000820] ----G--N---- \--* LCL_VAR int (AX) V63 tmp33 argSlots=1, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Local V76 should not be enregistered because: it is address exposed Shuffled argument table: rcx ArgTable for 218.CALL after fgMorphArgs: fgArgTabEntry[arg 0 824.ADDR struct (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, tmpNum=V76, isTmp, processed, isStruct] fgMorphTree BB39, STMT00050 (after) [000226] -ACXG+------ * ASG long [000225] D----+-N---- +--* LCL_VAR long V24 loc21 [000218] -ACXG+------ \--* CALL long System.Numerics.BigInteger.op_Explicit [000822] -A--G+----L- arg0 SETUP +--* COMMA void [000815] -A--G------- | +--* COMMA void [000810] -A---------- | | +--* ASG byref [000809] D------N---- | | | +--* LCL_VAR byref V89 tmp59 [000807] -----+------ | | | \--* ADDR byref [000808] ----G+-N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 [000814] -A--G------- | | \--* ASG ref [000812] *------N---- | | +--* IND ref [000811] ------------ | | | \--* LCL_VAR byref V89 tmp59 Zero Fseq[_bits] [000813] ----G--N---- | | \--* LCL_VAR ref (AX) V62 tmp32 [000821] -A--G------- | \--* ASG int [000819] *------N---- | +--* IND int [000818] ------------ | | \--* ADD byref [000816] ------------ | | +--* LCL_VAR byref V89 tmp59 [000817] ------------ | | \--* CNS_INT long 8 Fseq[_sign] [000820] ----G--N---- | \--* LCL_VAR int (AX) V63 tmp33 [000824] ------------ arg0 in rcx \--* ADDR byref [000823] -------N---- \--* LCL_VAR struct(AX) V76 tmp46 fgMorphTree BB39, STMT00052 (before) [000232] -AC--------- * ASG int [000231] D------N---- +--* LCL_VAR int V25 loc22 [000516] ------------ \--* EQ int [000514] ------------ +--* LCL_VAR int (AX) V61 tmp31 [000515] ------------ \--* CNS_INT int 0 GenTreeNode creates assertion: [000232] -A--G------- * ASG int In BB39 New Local Subrange Assertion: V25 in [0..1] index=#02, mask=0000000000000002 fgMorphTree BB39, STMT00054 (before) [000237] -AC--------- * ASG int [000236] D------N---- +--* LCL_VAR int V26 loc23 [000234] --C-G------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits [000233] ------------ arg0 \--* LCL_VAR long V24 loc21 Initializing arg info for 234.CALL: ArgTable for 234.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 233.LCL_VAR long (By ref), 1 reg: rcx, byteAlignment=8] Morphing args for 234.CALL: argSlots=1, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000233] -----+------ * LCL_VAR long V24 loc21 Replaced with placeholder node: [000825] ----------L- * ARGPLACE long Shuffled argument table: rcx ArgTable for 234.CALL after fgMorphArgs: fgArgTabEntry[arg 0 233.LCL_VAR long (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed] fgMorphTree BB39, STMT00054 (after) [000237] -ACXG+------ * ASG int [000236] D----+-N---- +--* LCL_VAR int V26 loc23 [000234] --CXG+------ \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits [000233] -----+------ arg0 in rcx \--* LCL_VAR long V24 loc21 fgMorphTree BB39, STMT00055 (before) [000241] ------------ * JTRUE void [000240] N--------U-- \--* LE int [000238] ------------ +--* LCL_VAR int V26 loc23 [000239] ------------ \--* LCL_VAR int V20 loc17 Morphing BB40 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB40, STMT00063 (before) [000286] -A---------- * ASG int [000285] D------N---- +--* LCL_VAR int V29 loc26 [000284] ------------ \--* SUB int [000282] ------------ +--* LCL_VAR int V26 loc23 [000283] ------------ \--* LCL_VAR int V20 loc17 fgMorphTree BB40, STMT00064 (before) [000290] ------------ * JTRUE void [000289] ------------ \--* EQ int [000287] ------------ +--* LCL_VAR int V25 loc22 [000288] ------------ \--* CNS_INT int 0 Morphing BB41 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB41, STMT00068 (before) [000320] -A---------- * ASG int [000319] D------N---- +--* LCL_VAR int V37 tmp7 [000318] ------------ \--* EQ int [000315] ------------ +--* AND long [000305] ------------ | +--* LCL_VAR long V24 loc21 [000314] ------------ | \--* SUB long [000311] ------------ | +--* LSH long [000307] ------------ | | +--* CAST long <- int [000306] ------------ | | | \--* CNS_INT int 1 [000310] ------------ | | \--* AND int [000308] ------------ | | +--* LCL_VAR int V29 loc26 [000309] ------------ | | \--* CNS_INT int 63 [000313] ------------ | \--* CAST long <- int [000312] ------------ | \--* CNS_INT int 1 [000317] ------------ \--* CAST long <- int [000316] ------------ \--* CNS_INT int 0 Folding long operator with constant nodes into a constant: [000307] ------------ * CAST long <- int [000306] -----+------ \--* CNS_INT int 1 Bashed to long constant: [000307] ------------ * CNS_INT long 1 Folding long operator with constant nodes into a constant: [000313] ------------ * CAST long <- int [000312] -----+------ \--* CNS_INT int 1 Bashed to long constant: [000313] ------------ * CNS_INT long 1 Folding long operator with constant nodes into a constant: [000317] ------------ * CAST long <- int [000316] -----+------ \--* CNS_INT int 0 Bashed to long constant: [000317] ------------ * CNS_INT long 0 GenTreeNode creates assertion: [000320] -A---------- * ASG int In BB41 New Local Subrange Assertion: V37 in [0..1] index=#01, mask=0000000000000001 fgMorphTree BB41, STMT00068 (after) [000320] -A---+------ * ASG int [000319] D----+-N---- +--* LCL_VAR int V37 tmp7 [000318] -----+------ \--* EQ int [000315] -----+------ +--* AND long [000305] -----+------ | +--* LCL_VAR long V24 loc21 [000314] -----+------ | \--* ADD long [000311] -----+------ | +--* LSH long [000307] -----+------ | | +--* CNS_INT long 1 [000310] -----+------ | | \--* AND int [000308] -----+------ | | +--* LCL_VAR int V29 loc26 [000309] -----+------ | | \--* CNS_INT int 63 [000313] -----+------ | \--* CNS_INT long -1 [000317] -----+------ \--* CNS_INT long 0 Morphing BB42 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB42, STMT00065 (before) [000293] -A---------- * ASG int [000292] D------N---- +--* LCL_VAR int V37 tmp7 [000291] ------------ \--* CNS_INT int 0 GenTreeNode creates assertion: [000293] -A---------- * ASG int In BB42 New Local Constant Assertion: V37 == 0 index=#01, mask=0000000000000001 Morphing BB43 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB43, STMT00066 (before) [000297] -A---------- * ASG int [000296] D------N---- +--* LCL_VAR int V25 loc22 [000295] ------------ \--* LCL_VAR int V37 tmp7 GenTreeNode creates assertion: [000297] -A---------- * ASG int In BB43 New Local Subrange Assertion: V25 in [0..1] index=#01, mask=0000000000000001 fgMorphTree BB43, STMT00066 (after) [000297] -A---+------ * ASG int [000296] D----+-N---- +--* LCL_VAR int V25 loc22 [000826] -----+------ \--* CAST int <- bool <- int [000295] -----+------ \--* LCL_VAR int V37 tmp7 fgMorphTree BB43, STMT00067 (before) [000304] -A---------- * ASG long [000303] D------N---- +--* LCL_VAR long V24 loc21 [000302] ------------ \--* RSZ long [000298] ------------ +--* LCL_VAR long V24 loc21 [000301] ------------ \--* AND int [000299] ------------ +--* LCL_VAR int V29 loc26 [000300] ------------ \--* CNS_INT int 63 Morphing BB44 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB44, STMT00057 (before) [000254] -AC--------- * ASG long [000253] D------N---- +--* LCL_VAR long V27 loc24 [000252] --C--------- \--* ADD long [000250] --C--------- +--* LSH long [000243] --C-G------- | +--* CALL long System.Numerics.BigInteger.op_Explicit [000245] n----------- arg0 | | \--* OBJ struct [000244] ------------ | | \--* ADDR byref [000242] -------N---- | | \--* LCL_VAR struct(AX)(P) V11 loc8 | | \--* ref V11._bits (offs=0x00) -> V54 tmp24 | | \--* int V11._sign (offs=0x08) -> V55 tmp25 [000249] ------------ | \--* AND int [000247] ------------ | +--* LCL_VAR int V20 loc17 [000248] ------------ | \--* CNS_INT int 63 [000251] ------------ \--* LCL_VAR long V24 loc21 Initializing arg info for 243.CALL: ArgTable for 243.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 245.OBJ struct (By ref), 1 reg: rcx, byteAlignment=8, isStruct] Morphing args for 243.CALL: making an outgoing copy for struct arg reusing outgoing struct argfgMorphCopyBlock: fgMorphBlkNode for dst tree, before: [000827] D------N---- * LCL_VAR struct(AX) V76 tmp46 fgMorphBlkNode after: [000827] D------N---- * LCL_VAR struct(AX) V76 tmp46 fgMorphBlkNode for src tree, before: [000242] ----G+-N---- * LCL_VAR struct(AX)(P) V11 loc8 * ref V11._bits (offs=0x00) -> V54 tmp24 * int V11._sign (offs=0x08) -> V55 tmp25 fgMorphBlkNode after: [000242] ----G+-N---- * LCL_VAR struct(AX)(P) V11 loc8 * ref V11._bits (offs=0x00) -> V54 tmp24 * int V11._sign (offs=0x08) -> V55 tmp25 block assignment to morph: [000828] -A--G------- * ASG struct (copy) [000827] D------N---- +--* LCL_VAR struct(AX) V76 tmp46 [000242] ----G+-N---- \--* LCL_VAR struct(AX)(P) V11 loc8 \--* ref V11._bits (offs=0x00) -> V54 tmp24 \--* int V11._sign (offs=0x08) -> V55 tmp25 (srcDoFldAsg=true) using field by field assignments. Local V76 should not be enregistered because: written in a block op lvaGrabTemp returning 90 (V90 tmp60) called for BlockOp address local. Local V76 should not be enregistered because: it is address exposed fgAddFieldSeqForZeroOffset for Fseq[_bits] addr (Before) [000834] ------------ LCL_VAR byref (After) [000834] ------------ LCL_VAR byref Zero Fseq[_bits] fgMorphCopyBlock (after): [000845] -A--G+------ * COMMA void [000838] -A--G------- +--* COMMA void [000833] -A---------- | +--* ASG byref [000832] D------N---- | | +--* LCL_VAR byref V90 tmp60 [000830] -----+------ | | \--* ADDR byref [000831] ----G+-N---- | | \--* LCL_VAR struct(AX) V76 tmp46 [000837] -A--G------- | \--* ASG ref [000835] *------N---- | +--* IND ref [000834] ------------ | | \--* LCL_VAR byref V90 tmp60 Zero Fseq[_bits] [000836] ----G--N---- | \--* LCL_VAR ref (AX) V54 tmp24 [000844] -A--G------- \--* ASG int [000842] *------N---- +--* IND int [000841] ------------ | \--* ADD byref [000839] ------------ | +--* LCL_VAR byref V90 tmp60 [000840] ------------ | \--* CNS_INT long 8 Fseq[_sign] [000843] ----G--N---- \--* LCL_VAR int (AX) V55 tmp25 argSlots=1, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Local V76 should not be enregistered because: it is address exposed Shuffled argument table: rcx ArgTable for 243.CALL after fgMorphArgs: fgArgTabEntry[arg 0 847.ADDR struct (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, tmpNum=V76, isTmp, processed, isStruct] fgMorphTree BB44, STMT00057 (after) [000254] -ACXG+------ * ASG long [000253] D----+-N---- +--* LCL_VAR long V27 loc24 [000252] -ACXG+------ \--* ADD long [000250] -ACXG+------ +--* LSH long [000243] -ACXG+------ | +--* CALL long System.Numerics.BigInteger.op_Explicit [000845] -A--G+----L- arg0 SETUP | | +--* COMMA void [000838] -A--G------- | | | +--* COMMA void [000833] -A---------- | | | | +--* ASG byref [000832] D------N---- | | | | | +--* LCL_VAR byref V90 tmp60 [000830] -----+------ | | | | | \--* ADDR byref [000831] ----G+-N---- | | | | | \--* LCL_VAR struct(AX) V76 tmp46 [000837] -A--G------- | | | | \--* ASG ref [000835] *------N---- | | | | +--* IND ref [000834] ------------ | | | | | \--* LCL_VAR byref V90 tmp60 Zero Fseq[_bits] [000836] ----G--N---- | | | | \--* LCL_VAR ref (AX) V54 tmp24 [000844] -A--G------- | | | \--* ASG int [000842] *------N---- | | | +--* IND int [000841] ------------ | | | | \--* ADD byref [000839] ------------ | | | | +--* LCL_VAR byref V90 tmp60 [000840] ------------ | | | | \--* CNS_INT long 8 Fseq[_sign] [000843] ----G--N---- | | | \--* LCL_VAR int (AX) V55 tmp25 [000847] ------------ arg0 in rcx | | \--* ADDR byref [000846] -------N---- | | \--* LCL_VAR struct(AX) V76 tmp46 [000249] -----+------ | \--* AND int [000247] -----+------ | +--* LCL_VAR int V20 loc17 [000248] -----+------ | \--* CNS_INT int 63 [000251] -----+------ \--* LCL_VAR long V24 loc21 fgMorphTree BB44, STMT00058 (before) [000258] ------------ * JTRUE void [000257] N--------U-- \--* GT int [000255] ------------ +--* LCL_VAR int V13 loc10 [000256] ------------ \--* CNS_INT int 0 fgMorphTree BB44, STMT00058 (after) [000258] -----+------ * JTRUE void [000257] N----+-N---- \--* NE int [000255] -----+------ +--* LCL_VAR int V13 loc10 [000256] -----+------ \--* CNS_INT int 0 Morphing BB45 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB45, STMT00062 (before) [000280] -A---------- * ASG int [000279] D------N---- +--* LCL_VAR int V36 tmp6 [000278] ------------ \--* SUB int [000276] ------------ +--* NEG int [000275] ------------ | \--* LCL_VAR int V22 loc19 [000277] ------------ \--* CNS_INT int 1 fgMorphTree BB45, STMT00062 (after) [000280] -A---+------ * ASG int [000279] D----+-N---- +--* LCL_VAR int V36 tmp6 [000278] -----+------ \--* ADD int [000276] -----+------ +--* NEG int [000275] -----+------ | \--* LCL_VAR int V22 loc19 [000277] -----+------ \--* CNS_INT int -1 Morphing BB46 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB46, STMT00059 (before) [000263] -A---------- * ASG int [000262] D------N---- +--* LCL_VAR int V36 tmp6 [000261] ------------ \--* SUB int [000259] ------------ +--* LCL_VAR int V13 loc10 [000260] ------------ \--* CNS_INT int 2 fgMorphTree BB46, STMT00059 (after) [000263] -A---+------ * ASG int [000262] D----+-N---- +--* LCL_VAR int V36 tmp6 [000261] -----+------ \--* ADD int [000259] -----+------ +--* LCL_VAR int V13 loc10 [000260] -----+------ \--* CNS_INT int -2 Morphing BB47 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB47, STMT00060 (before) [000267] -A---------- * ASG int [000266] D------N---- +--* LCL_VAR int V28 loc25 [000265] ------------ \--* LCL_VAR int V36 tmp6 GenTreeNode creates assertion: [000267] -A---------- * ASG int In BB47 New Local Copy Assertion: V28 == V36 index=#01, mask=0000000000000001 fgMorphTree BB47, STMT00061 (before) [000274] --C-G------- * RETURN int [000273] --C-G------- \--* CALL nullcheck int FloatingPointType.AssembleFloatingPointValue [000268] ------------ this in rcx +--* LCL_VAR ref V01 arg1 [000269] ------------ arg1 +--* LCL_VAR long V27 loc24 [000270] ------------ arg2 +--* LCL_VAR int V28 loc25 [000271] ------------ arg3 +--* LCL_VAR int V25 loc22 [000272] ------------ arg4 \--* LCL_VAR byref V02 arg2 Rejecting tail call in morph for call [000273]: Local address taken V11 Initializing arg info for 273.CALL: ArgTable for 273.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 268.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8] fgArgTabEntry[arg 1 269.LCL_VAR long (By ref), 1 reg: rdx, byteAlignment=8] fgArgTabEntry[arg 2 270.LCL_VAR int (By ref), 1 reg: r8, byteAlignment=8] fgArgTabEntry[arg 3 271.LCL_VAR int (By ref), 1 reg: r9, byteAlignment=8] fgArgTabEntry[arg 4 272.LCL_VAR byref (By ref), numSlots=1, slotNum=4, byteSize=8, byteOffset=32, byteAlignment=8] Morphing args for 273.CALL: Assertion prop in BB47: Copy Assertion: V28 == V36 index=#01, mask=0000000000000001 [000270] ------------ * LCL_VAR int V36 tmp6 argSlots=5, preallocatedArgCount=5, nextSlotNum=5, nextSlotByteOffset=40, outgoingArgSpaceSize=40 Sorting the arguments: Deferred argument ('rcx'): [000268] -----+------ * LCL_VAR ref V01 arg1 Replaced with placeholder node: [000848] ----------L- * ARGPLACE ref Deferred argument ('rdx'): [000269] -----+------ * LCL_VAR long V27 loc24 Replaced with placeholder node: [000849] ----------L- * ARGPLACE long Deferred argument ('r8'): [000270] -----+------ * LCL_VAR int V36 tmp6 Replaced with placeholder node: [000850] ----------L- * ARGPLACE int Deferred argument ('r9'): [000271] -----+------ * LCL_VAR int V25 loc22 Replaced with placeholder node: [000851] ----------L- * ARGPLACE int Shuffled argument table: rcx rdx r8 r9 ArgTable for 273.CALL after fgMorphArgs: fgArgTabEntry[arg 0 268.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed] fgArgTabEntry[arg 1 269.LCL_VAR long (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=1, processed] fgArgTabEntry[arg 2 270.LCL_VAR int (By ref), 1 reg: r8, byteAlignment=8, lateArgInx=2, processed] fgArgTabEntry[arg 3 271.LCL_VAR int (By ref), 1 reg: r9, byteAlignment=8, lateArgInx=3, processed] fgArgTabEntry[arg 4 272.LCL_VAR byref (By ref), numSlots=1, slotNum=4, byteSize=8, byteOffset=32, byteAlignment=8, processed] GenTreeNode creates assertion: [000273] --CXG------- * CALL nullcheck int FloatingPointType.AssembleFloatingPointValue In BB47 New Local Constant Assertion: V01 != null index=#02, mask=0000000000000002 fgMorphTree BB47, STMT00061 (after) [000274] --CXG+------ * RETURN int [000273] --CXG+------ \--* CALL nullcheck int FloatingPointType.AssembleFloatingPointValue [000272] -----+------ arg4 out+20 +--* LCL_VAR byref V02 arg2 [000268] -----+------ this in rcx +--* LCL_VAR ref V01 arg1 [000269] -----+------ arg1 in rdx +--* LCL_VAR long V27 loc24 [000270] -----+------ arg2 in r8 +--* LCL_VAR int V36 tmp6 [000271] -----+------ arg3 in r9 \--* LCL_VAR int V25 loc22 morph BB47 to point at onereturn. New block is BB47 [0035] 2 BB45,BB46 1 [1F2..202)-> BB48 (always) i label target hascall gcsafe Morphing BB48 of 'Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int' fgMorphTree BB48, STMT00109 (before) [000523] ------------ * RETURN int [000522] -------N---- \--* LCL_VAR int V51 tmp21 *************** Finishing PHASE Morph - Global Trees after Morph - Global ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB49 [0056] 1 1 [???..???) i internal label target BB01 [0000] 1 BB49 1 [000..00D)-> BB04 ( cond ) i label target idxlen BB02 [0001] 1 BB01 1 [00D..017) (return) i hascall gcsafe BB04 [0002] 1 BB01 1 [017..065)-> BB07 ( cond ) i label target hascall gcsafe BB06 [0038] 1 BB04 1 [020..021)-> BB08 (always) i BB07 [0039] 1 BB04 1 [020..021) i label target BB08 [0040] 2 BB06,BB07 1 [000..000)-> BB11 ( cond ) i internal label target idxlen BB10 [0043] 1 BB08 1 [000..000)-> BB12 (always) i internal BB11 [0044] 1 BB08 1 [000..000) i internal label target BB12 [0045] 2 BB10,BB11 1 [???..???)-> BB17 ( cond ) i internal label target hascall gcsafe idxlen BB13 [0003] 1 BB12 1 [065..070)-> BB16 ( cond ) i hascall gcsafe BB14 [0004] 1 BB13 1 [070..07A) (return) i hascall gcsafe BB16 [0005] 1 BB13 1 [07A..082) i label target hascall gcsafe BB17 [0006] 2 BB12,BB16 1 [082..092)-> BB19 ( cond ) i label target hascall gcsafe BB18 [0007] 1 BB17 1 [092..096)-> BB20 ( cond ) i BB19 [0008] 2 BB17,BB18 1 [096..0A7)-> BB48 (always) i label target hascall gcsafe BB20 [0009] 1 BB18 1 [0A7..0B0)-> BB22 ( cond ) i label target BB21 [0010] 1 BB20 1 [0B0..0B4)-> BB23 (always) i BB22 [0011] 1 BB20 1 [0B4..0BE) i label target BB23 [0012] 2 BB21,BB22 1 [0BE..0C4)-> BB27 ( cond ) i label target BB24 [0013] 1 BB23 1 [0C4..0D9)-> BB27 ( cond ) i hascall gcsafe idxlen BB25 [0014] 1 BB24 1 [0D9..0E3) (return) i hascall gcsafe BB27 [0015] 2 BB23,BB24 1 [0E3..117)-> BB29 ( cond ) i label target hascall gcsafe BB28 [0016] 1 BB27 1 [117..11A)-> BB30 (always) i BB29 [0017] 1 BB27 1 [11A..11F) i label target BB30 [0018] 2 BB28,BB29 1 [11F..126)-> BB32 ( cond ) i label target BB31 [0019] 1 BB30 1 [126..12F) i hascall gcsafe BB32 [0020] 2 BB30,BB31 1 [12F..13E)-> BB36 ( cond ) i label target BB33 [0021] 1 BB32 1 [13E..144)-> BB35 ( cond ) i BB34 [0022] 1 BB33 1 [144..155)-> BB48 (always) i hascall gcsafe BB35 [0023] 1 BB33 1 [155..15C) i label target BB36 [0024] 2 BB32,BB35 1 [15C..167)-> BB38 ( cond ) i label target hascall gcsafe BB37 [0025] 1 BB36 1 [167..16B)-> BB39 (always) i BB38 [0026] 1 BB36 1 [16B..16F) i label target BB39 [0027] 2 BB37,BB38 1 [16F..1A4)-> BB44 ( cond ) i label target hascall gcsafe BB40 [0028] 1 BB39 1 [1A4..1AF)-> BB42 ( cond ) i BB41 [0029] 1 BB40 1 [1AF..1C3)-> BB43 (always) i BB42 [0030] 1 BB40 1 [1C3..1C4) i label target BB43 [0031] 2 BB41,BB42 1 [1C4..1D0) i label target BB44 [0032] 2 BB39,BB43 1 [1D0..1E7)-> BB46 ( cond ) i label target hascall gcsafe BB45 [0033] 1 BB44 1 [1E7..1EE)-> BB47 (always) i BB46 [0034] 1 BB44 1 [1EE..1F2) i label target BB47 [0035] 2 BB45,BB46 1 [1F2..202)-> BB48 (always) i label target hascall gcsafe BB48 [0054] 3 BB19,BB34,BB47 1 [???..???) (return) keep internal target ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB49 [???..???), preds={} succs={BB01} ***** BB49 STMT00111 (IL ???... ???) [000540] -A---+------ * COMMA void [000533] -A---------- +--* ASG ref [000530] D------N---- | +--* LCL_VAR ref V52 tmp22 [000532] n----------- | \--* IND ref [000531] ------------ | \--* LCL_VAR byref V00 arg0 Zero Fseq[Mantissa] [000539] -A---------- \--* ASG int [000534] D------N---- +--* LCL_VAR int V53 tmp23 [000538] n----------- \--* IND int [000537] ------------ \--* ADD byref [000535] ------------ +--* LCL_VAR byref V00 arg0 [000536] ------------ \--* CNS_INT long 8 Fseq[Exponent] ------------ BB01 [000..00D) -> BB04 (cond), preds={BB49} succs={BB02,BB04} ***** BB01 STMT00000 (IL 0x000...0x00B) [000006] ---XG+------ * JTRUE void [000005] J--XG+-N---- \--* NE int [000003] ---XG+------ +--* ARR_LENGTH int [000002] -----+------ | \--* LCL_VAR ref V52 tmp22 [000004] -----+------ \--* CNS_INT int 0 ------------ BB02 [00D..017) (return), preds={BB01} succs={} ***** BB02 STMT00087 (IL 0x00D...0x014) [000403] -ACXG+------ * ASG long [000402] *--X-+-N---- +--* IND long [000399] -----+------ | \--* LCL_VAR byref V02 arg2 [000401] --CXG+------ \--* CALLV ind long FloatingPointType.get_Zero [000400] -----+------ this in rcx \--* LCL_VAR ref V01 arg1 ***** BB02 STMT00107 (IL ???... ???) [000520] -----+------ * RETURN int [000404] -----+------ \--* CNS_INT int 1 ------------ BB04 [017..065) -> BB07 (cond), preds={BB01} succs={BB06,BB07} ***** BB04 STMT00002 (IL ???... ???) [000013] -ACXG+------ * ASG int [000012] D----+-N---- +--* LCL_VAR int V03 loc0 [000011] --CXG+------ \--* ADD int [000409] --CXG+------ +--* CAST int <- ushort <- int [000408] --CXG+------ | \--* ADD int [000406] --CXG+------ | +--* CALLV ind int FloatingPointType.get_DenormalMantissaBits [000007] -----+------ this in rcx | | \--* LCL_VAR ref V01 arg1 [000407] -----+------ | \--* CNS_INT int 1 [000010] -----+------ \--* CNS_INT int 1 ***** BB04 STMT00092 (IL 0x020... ???) [000424] -A--G+------ * ASG int [000423] D----+-N---- +--* LCL_VAR int V40 tmp10 [000017] -----+------ \--* LCL_VAR int V53 tmp23 ***** BB04 STMT00089 (IL 0x020... ???) [000414] -----+------ * JTRUE void [000413] J----+-N---- \--* GE int [000411] -----+------ +--* CNS_INT int 0 [000412] -----+------ \--* LCL_VAR int V53 tmp23 ------------ BB06 [020..021) -> BB08 (always), preds={BB04} succs={BB08} ***** BB06 STMT00091 (IL 0x020... ???) [000421] -A---+------ * ASG int [000420] D----+-N---- +--* LCL_VAR int V39 tmp9 [000419] -----+------ \--* LCL_VAR int V40 tmp10 ------------ BB07 [020..021), preds={BB04} succs={BB08} ***** BB07 STMT00090 (IL 0x020... ???) [000417] -A---+------ * ASG int [000416] D----+-N---- +--* LCL_VAR int V39 tmp9 [000415] -----+------ \--* CNS_INT int 0 ------------ BB08 [000..000) -> BB11 (cond), preds={BB06,BB07} succs={BB10,BB11} ***** BB08 STMT00004 (IL ???... ???) [000021] -A---+------ * ASG int [000020] D----+-N---- +--* LCL_VAR int V31 tmp1 [000422] -----+------ \--* LCL_VAR int V39 tmp9 ***** BB08 STMT00096 (IL ???... ???) [000443] -A-XG+------ * ASG int [000442] D----+-N---- +--* LCL_VAR int V42 tmp12 [000429] ---XG+------ \--* ARR_LENGTH int [000428] -----+------ \--* LCL_VAR ref V52 tmp22 ***** BB08 STMT00093 (IL ???... ???) [000433] -----+------ * JTRUE void [000432] N----+-N-U-- \--* LE int [000023] -----+------ +--* LCL_VAR int V39 tmp9 [000431] -----+------ \--* LCL_VAR int V42 tmp12 ------------ BB10 [000..000) -> BB12 (always), preds={BB08} succs={BB12} ***** BB10 STMT00095 (IL ???... ???) [000440] -A---+------ * ASG int [000439] D----+-N---- +--* LCL_VAR int V41 tmp11 [000438] -----+------ \--* LCL_VAR int V42 tmp12 ------------ BB11 [000..000), preds={BB08} succs={BB12} ***** BB11 STMT00094 (IL ???... ???) [000436] -A---+------ * ASG int [000435] D----+-N---- +--* LCL_VAR int V41 tmp11 [000434] -----+------ \--* LCL_VAR int V31 tmp1 ------------ BB12 [???..???) -> BB17 (cond), preds={BB10,BB11} succs={BB13,BB17} ***** BB12 STMT00007 (IL ???... ???) [000031] -A---+------ * ASG int [000030] D----+-N---- +--* LCL_VAR int V04 loc1 [000441] -----+------ \--* LCL_VAR int V41 tmp11 ***** BB12 STMT00008 (IL ???...0x03C) [000035] -A---+------ * ASG int [000034] D----+-N---- +--* LCL_VAR int V05 loc2 [000033] -----+------ \--* SUB int [000022] -----+------ +--* LCL_VAR int V31 tmp1 [000032] -----+------ \--* LCL_VAR int V41 tmp11 ***** BB12 STMT00009 (IL 0x03D...0x03E) [000038] -A---+------ * ASG int [000037] D----+-N---- +--* LCL_VAR int V06 loc3 [000036] -----+------ \--* CNS_INT int 0 ***** BB12 STMT00010 (IL 0x03F...0x040) [000041] -A---+------ * ASG int [000040] D----+-N---- +--* LCL_VAR int V07 loc4 [000039] -----+------ \--* LCL_VAR int V41 tmp11 ***** BB12 STMT00011 (IL 0x042...0x044) [000044] -A---+------ * ASG int [000043] D----+-N---- +--* LCL_VAR int V08 loc5 [000042] -----+------ \--* LCL_VAR int V41 tmp11 ***** BB12 STMT00013 (IL ???... ???) [000050] -A-XG+------ * ASG int [000049] D----+-N---- +--* LCL_VAR int V09 loc6 [000448] ---XG+------ \--* ARR_LENGTH int [000447] -----+------ \--* LCL_VAR ref V52 tmp22 ***** BB12 STMT00014 (IL 0x04F...0x054) [000055] -A---+------ * ASG int [000054] D----+-N---- +--* LCL_VAR int V10 loc7 [000053] -----+------ \--* SUB int [000051] -----+------ +--* LCL_VAR int V09 loc6 [000052] -----+------ \--* LCL_VAR int V41 tmp11 ***** BB12 STMT00016 (IL ???... ???) [000059] SACXG+------ * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger [000563] -A--------L- arg0 SETUP +--* ASG long [000562] D------N---- | +--* LCL_VAR long V75 tmp45 [000064] -----+------ | \--* ADDR long [000063] ----G+-N---- | \--* LCL_VAR struct(AX)(P) V11 loc8 | \--* ref V11._bits (offs=0x00) -> V54 tmp24 | \--* int V11._sign (offs=0x08) -> V55 tmp25 [000561] -A---+----L- arg1 SETUP +--* COMMA void [000554] -A---------- | +--* COMMA void [000549] -A---------- | | +--* ASG byref [000548] D------N---- | | | +--* LCL_VAR byref V74 tmp44 [000546] -----+------ | | | \--* ADDR byref [000547] -----+-N---- | | | \--* LCL_VAR struct(AX) V73 tmp43 [000553] -A---------- | | \--* ASG ref [000551] *------N---- | | +--* IND ref [000550] ------------ | | | \--* LCL_VAR byref V74 tmp44 Zero Fseq[Mantissa] [000552] -------N---- | | \--* LCL_VAR ref V52 tmp22 [000560] -A---------- | \--* ASG int [000558] *------N---- | +--* IND int [000557] ------------ | | \--* ADD byref [000555] ------------ | | +--* LCL_VAR byref V74 tmp44 [000556] ------------ | | \--* CNS_INT long 8 Fseq[Exponent] [000559] -------N---- | \--* LCL_VAR int V53 tmp23 [000564] ------------ arg0 in rcx +--* LCL_VAR long V75 tmp45 [000566] ------------ arg1 in rdx +--* ADDR byref [000565] -------N---- | \--* LCL_VAR struct(AX) V73 tmp43 [000058] -----+------ arg3 in r9 +--* LCL_VAR int V41 tmp11 [000057] -----+------ arg2 in r8 \--* CNS_INT int 0 ***** BB12 STMT00017 (IL 0x061...0x063) [000068] -----+------ * JTRUE void [000067] N----+-N---- \--* EQ int [000065] -----+------ +--* LCL_VAR int V05 loc2 [000066] -----+------ \--* CNS_INT int 0 ------------ BB13 [065..070) -> BB16 (cond), preds={BB12} succs={BB14,BB16} ***** BB13 STMT00083 (IL ???... ???) [000387] --CXG+------ * JTRUE void [000386] J-CXG+-N---- \--* LE int [000381] -----+---U-- +--* CAST long <- ulong <- uint [000380] -----+------ | \--* LCL_VAR int V05 loc2 [000385] --CXG+------ \--* CAST long <- int [000383] --CXG+------ \--* CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent [000382] -----+------ this in rcx \--* LCL_VAR ref V01 arg1 ------------ BB14 [070..07A) (return), preds={BB13} succs={} ***** BB14 STMT00085 (IL 0x070...0x077) [000396] -ACXG+------ * ASG long [000395] *--X-+-N---- +--* IND long [000392] -----+------ | \--* LCL_VAR byref V02 arg2 [000394] --CXG+------ \--* CALLV ind long FloatingPointType.get_Infinity [000393] -----+------ this in rcx \--* LCL_VAR ref V01 arg1 ***** BB14 STMT00108 (IL ???... ???) [000521] -----+------ * RETURN int [000397] -----+------ \--* CNS_INT int 3 ------------ BB16 [07A..082), preds={BB13} succs={BB17} ***** BB16 STMT00084 (IL 0x07A...0x07D) [000391] --CXG+------ * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen [000389] -----+------ arg0 in rcx +--* ADDR long [000388] ----G+-N---- | \--* LCL_VAR struct(AX)(P) V11 loc8 | \--* ref V11._bits (offs=0x00) -> V54 tmp24 | \--* int V11._sign (offs=0x08) -> V55 tmp25 [000390] -----+------ arg1 in rdx \--* LCL_VAR int V05 loc2 ------------ BB17 [082..092) -> BB19 (cond), preds={BB12,BB16} succs={BB18,BB19} ***** BB17 STMT00019 (IL ???... ???) [000077] -ACXG+------ * ASG int [000076] D----+-N---- +--* LCL_VAR int V13 loc10 [000072] -ACXG+------ \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits [000591] -A--G+----L- arg0 SETUP +--* COMMA void [000584] -A--G------- | +--* COMMA void [000579] -A---------- | | +--* ASG byref [000578] D------N---- | | | +--* LCL_VAR byref V77 tmp47 [000576] -----+------ | | | \--* ADDR byref [000577] -----+-N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 [000583] -A--G------- | | \--* ASG ref [000581] *------N---- | | +--* IND ref [000580] ------------ | | | \--* LCL_VAR byref V77 tmp47 Zero Fseq[_bits] [000582] ----G--N---- | | \--* LCL_VAR ref (AX) V54 tmp24 [000590] -A--G------- | \--* ASG int [000588] *------N---- | +--* IND int [000587] ------------ | | \--* ADD byref [000585] ------------ | | +--* LCL_VAR byref V77 tmp47 [000586] ------------ | | \--* CNS_INT long 8 Fseq[_sign] [000589] ----G--N---- | \--* LCL_VAR int (AX) V55 tmp25 [000593] ------------ arg0 in rcx +--* ADDR byref [000592] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 [000071] -----+------ arg1 in rdx \--* LCL_VAR_ADDR long V12 loc9 ***** BB17 STMT00020 (IL 0x08D...0x090) [000081] -----+------ * JTRUE void [000080] N----+-N-U-- \--* GE int [000078] -----+------ +--* LCL_VAR int V13 loc10 [000079] -----+------ \--* LCL_VAR int V03 loc0 ------------ BB18 [092..096) -> BB20 (cond), preds={BB17} succs={BB19,BB20} ***** BB18 STMT00022 (IL 0x092...0x094) [000094] -----+------ * JTRUE void [000093] J----+-N---- \--* NE int [000091] -----+------ +--* LCL_VAR int V10 loc7 [000092] -----+------ \--* CNS_INT int 0 ------------ BB19 [096..0A7) -> BB48 (always), preds={BB17,BB18} succs={BB48} ***** BB19 STMT00021 (IL 0x096...0x0A6) [000600] -ACXG------- * ASG int [000599] D------N---- +--* LCL_VAR int V51 tmp21 [000089] --CXG+------ \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits [000088] -----+------ arg4 out+20 +--* LCL_VAR byref V02 arg2 [000086] N----+------ arg2 in r8 +--* NE int [000084] -----+------ | +--* LCL_VAR int V10 loc7 [000085] -----+------ | \--* CNS_INT int 0 [000082] ----G+------ arg0 in rcx +--* LCL_VAR ref (AX) V12 loc9 [000083] -----+------ arg1 in rdx +--* LCL_VAR int V13 loc10 [000087] -----+------ arg3 in r9 \--* LCL_VAR ref V01 arg1 ------------ BB20 [0A7..0B0) -> BB22 (cond), preds={BB18} succs={BB21,BB22} ***** BB20 STMT00023 (IL 0x0A7...0x0AE) [000100] ----G+------ * JTRUE void [000099] J---G+-N---- \--* LT int [000097] -----+------ +--* LCL_VAR int V53 tmp23 [000098] -----+------ \--* CNS_INT int 0 ------------ BB21 [0B0..0B4) -> BB23 (always), preds={BB20} succs={BB23} ***** BB21 STMT00081 (IL 0x0B0...0x0B2) [000378] -A---+------ * ASG int [000377] D----+-N---- +--* LCL_VAR int V32 tmp2 [000376] -----+------ \--* LCL_VAR int V10 loc7 ------------ BB22 [0B4..0BE), preds={BB20} succs={BB23} ***** BB22 STMT00024 (IL 0x0B4...0x0BD) [000108] -A--G+------ * ASG int [000107] D----+-N---- +--* LCL_VAR int V32 tmp2 [000106] ----G+------ \--* SUB int [000101] -----+------ +--* LCL_VAR int V10 loc7 [000104] -----+------ \--* LCL_VAR int V53 tmp23 ------------ BB23 [0BE..0C4) -> BB27 (cond), preds={BB21,BB22} succs={BB24,BB27} ***** BB23 STMT00025 (IL ???...0x0BE) [000112] -A---+------ * ASG int [000111] D----+-N---- +--* LCL_VAR int V14 loc11 [000110] -----+------ \--* LCL_VAR int V32 tmp2 ***** BB23 STMT00026 (IL 0x0C0...0x0C2) [000116] -----+------ * JTRUE void [000115] J----+-N---- \--* NE int [000113] -----+------ +--* LCL_VAR int V13 loc10 [000114] -----+------ \--* CNS_INT int 0 ------------ BB24 [0C4..0D9) -> BB27 (cond), preds={BB23} succs={BB25,BB27} ***** BB24 STMT00077 (IL ???... ???) [000363] -A-XG+------ * ASG long [000362] D----+-N---- +--* LCL_VAR long V38 tmp8 [000359] ---XG+------ \--* SUB long [000353] -----+---U-- +--* CAST long <- ulong <- uint [000352] -----+------ | \--* LCL_VAR int V14 loc11 [000358] ---XG+------ \--* CAST long <- int [000456] ---XG+------ \--* ARR_LENGTH int [000455] -----+------ \--* LCL_VAR ref V52 tmp22 ***** BB24 STMT00078 (IL ???... ???) [000368] --CXG+------ * JTRUE void [000367] J-CXG+-N---- \--* LE int [000364] -----+------ +--* LCL_VAR long V38 tmp8 [000366] --CXG+------ \--* CAST long <- int [000361] --CXG+------ \--* CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent [000360] -----+------ this in rcx \--* LCL_VAR ref V01 arg1 ------------ BB25 [0D9..0E3) (return), preds={BB24} succs={} ***** BB25 STMT00079 (IL 0x0D9...0x0E0) [000373] -ACXG+------ * ASG long [000372] *--X-+-N---- +--* IND long [000369] -----+------ | \--* LCL_VAR byref V02 arg2 [000371] --CXG+------ \--* CALLV ind long FloatingPointType.get_Zero [000370] -----+------ this in rcx \--* LCL_VAR ref V01 arg1 ***** BB25 STMT00110 (IL ???... ???) [000524] -----+------ * RETURN int [000374] -----+------ \--* CNS_INT int 2 ------------ BB27 [0E3..117) -> BB29 (cond), preds={BB23,BB24} succs={BB28,BB29} ***** BB27 STMT00028 (IL ???... ???) [000120] SACXG+------ * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger [000623] -A--------L- arg0 SETUP +--* ASG long [000622] D------N---- | +--* LCL_VAR long V79 tmp49 [000125] -----+------ | \--* ADDR long [000124] ----G+-N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 [000621] -A---+----L- arg1 SETUP +--* COMMA void [000614] -A---------- | +--* COMMA void [000609] -A---------- | | +--* ASG byref [000608] D------N---- | | | +--* LCL_VAR byref V78 tmp48 [000606] -----+------ | | | \--* ADDR byref [000607] ----G+-N---- | | | \--* LCL_VAR struct(AX) V73 tmp43 [000613] -A---------- | | \--* ASG ref [000611] *------N---- | | +--* IND ref [000610] ------------ | | | \--* LCL_VAR byref V78 tmp48 Zero Fseq[Mantissa] [000612] -------N---- | | \--* LCL_VAR ref V52 tmp22 [000620] -A---------- | \--* ASG int [000618] *------N---- | +--* IND int [000617] ------------ | | \--* ADD byref [000615] ------------ | | +--* LCL_VAR byref V78 tmp48 [000616] ------------ | | \--* CNS_INT long 8 Fseq[Exponent] [000619] -------N---- | \--* LCL_VAR int V53 tmp23 [000624] ------------ arg0 in rcx +--* LCL_VAR long V79 tmp49 [000626] ------------ arg1 in rdx +--* ADDR byref [000625] -------N---- | \--* LCL_VAR struct(AX) V73 tmp43 [000118] -----+------ arg2 in r8 +--* LCL_VAR int V08 loc5 [000119] -----+------ arg3 in r9 \--* LCL_VAR int V09 loc6 ***** BB27 STMT00029 (IL 0x0EF...0x0F4) [000133] H-CXG+------ * CALL help long HELPER.CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE [000131] -----+------ arg0 in rcx +--* CNS_INT long 0x7ff815262aa0 [000132] -----+------ arg1 in rdx \--* CNS_INT int 173 ***** BB27 STMT00030 (IL ???... ???) [000649] -A-XG+------ * COMMA void [000642] -A-XG------- +--* COMMA void [000637] -A--G------- | +--* ASG byref [000636] D------N---- | | +--* LCL_VAR byref V80 tmp50 [000632] ----G+------ | | \--* ADD byref [000633] n---G+------ | | +--* IND ref [000634] I----+------ | | | \--* CNS_INT(h) long 0xd1ffab1e static Fseq[BigOne] [000635] -----+------ | | \--* CNS_INT long 8 Fseq[#FirstElem] [000641] -A-XG------- | \--* ASG ref [000638] D---G--N---- | +--* LCL_VAR ref (AX) V58 tmp28 [000640] ---X-------- | \--* IND ref [000639] ------------ | \--* LCL_VAR byref V80 tmp50 Zero Fseq[_bits] [000648] -A-XG------- \--* ASG int [000643] D---G--N---- +--* LCL_VAR int (AX) V59 tmp29 [000647] ---X-------- \--* IND int [000646] ------------ \--* ADD byref [000644] ------------ +--* LCL_VAR byref V80 tmp50 [000645] ------------ \--* CNS_INT long 8 Fseq[_sign] ***** BB27 STMT00031 (IL 0x0F6...0x106) [000141] --CXG+------ * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen [000139] -----+------ arg0 in rcx +--* ADDR long [000138] ----G+-N---- | \--* LCL_VAR struct(AX)(P) V16 loc13 | \--* ref V16._bits (offs=0x00) -> V58 tmp28 | \--* int V16._sign (offs=0x08) -> V59 tmp29 [000140] -----+------ arg1 in rdx \--* LCL_VAR int V14 loc11 ***** BB27 STMT00099 (IL 0x0FF... ???) [000658] -A--G+------ * COMMA void [000654] -A--G------- +--* ASG ref [000652] D------N---- | +--* LCL_VAR ref V64 tmp34 [000653] ----G--N---- | \--* LCL_VAR ref (AX) V56 tmp26 [000657] -A--G------- \--* ASG int [000655] D------N---- +--* LCL_VAR int V65 tmp35 [000656] ----G--N---- \--* LCL_VAR int (AX) V57 tmp27 ***** BB27 STMT00098 (IL 0x0FF... ???) [000468] -ACXG+------ * ASG int [000467] D----+-N---- +--* LCL_VAR int V43 tmp13 [000463] -ACXG+------ \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits [000677] -A---+----L- arg0 SETUP +--* COMMA void [000670] -A---------- | +--* COMMA void [000665] -A---------- | | +--* ASG byref [000664] D------N---- | | | +--* LCL_VAR byref V81 tmp51 [000662] -----+------ | | | \--* ADDR byref [000663] ----G+-N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 [000669] -A---------- | | \--* ASG ref [000667] *------N---- | | +--* IND ref [000666] ------------ | | | \--* LCL_VAR byref V81 tmp51 Zero Fseq[_bits] [000668] -------N---- | | \--* LCL_VAR ref V64 tmp34 [000676] -A---------- | \--* ASG int [000674] *------N---- | +--* IND int [000673] ------------ | | \--* ADD byref [000671] ------------ | | +--* LCL_VAR byref V81 tmp51 [000672] ------------ | | \--* CNS_INT long 8 Fseq[_sign] [000675] -------N---- | \--* LCL_VAR int V65 tmp35 [000679] ------------ arg0 in rcx +--* ADDR byref [000678] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 [000462] -----+------ arg1 in rdx \--* LCL_VAR_ADDR long V45 tmp15 ***** BB27 STMT00100 (IL 0x0FF... ???) [000475] -A--G+------ * ASG ref [000474] D---G+-N---- +--* LCL_VAR ref (AX) V45 tmp15 [000473] -----+------ \--* CNS_INT ref null ***** BB27 STMT00033 (IL ???... ???) [000148] -A---+------ * ASG int [000147] D----+-N---- +--* LCL_VAR int V17 loc14 [000469] -----+------ \--* LCL_VAR int V43 tmp13 ***** BB27 STMT00103 (IL 0x108... ???) [000687] -A--G+------ * COMMA void [000683] -A--G------- +--* ASG ref [000681] D------N---- | +--* LCL_VAR ref V66 tmp36 [000682] ----G--N---- | \--* LCL_VAR ref (AX) V58 tmp28 [000686] -A--G------- \--* ASG int [000684] D------N---- +--* LCL_VAR int V67 tmp37 [000685] ----G--N---- \--* LCL_VAR int (AX) V59 tmp29 ***** BB27 STMT00102 (IL 0x108... ???) [000486] -ACXG+------ * ASG int [000485] D----+-N---- +--* LCL_VAR int V46 tmp16 [000481] -ACXG+------ \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits [000706] -A---+----L- arg0 SETUP +--* COMMA void [000699] -A---------- | +--* COMMA void [000694] -A---------- | | +--* ASG byref [000693] D------N---- | | | +--* LCL_VAR byref V82 tmp52 [000691] -----+------ | | | \--* ADDR byref [000692] ----G+-N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 [000698] -A---------- | | \--* ASG ref [000696] *------N---- | | +--* IND ref [000695] ------------ | | | \--* LCL_VAR byref V82 tmp52 Zero Fseq[_bits] [000697] -------N---- | | \--* LCL_VAR ref V66 tmp36 [000705] -A---------- | \--* ASG int [000703] *------N---- | +--* IND int [000702] ------------ | | \--* ADD byref [000700] ------------ | | +--* LCL_VAR byref V82 tmp52 [000701] ------------ | | \--* CNS_INT long 8 Fseq[_sign] [000704] -------N---- | \--* LCL_VAR int V67 tmp37 [000708] ------------ arg0 in rcx +--* ADDR byref [000707] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 [000480] -----+------ arg1 in rdx \--* LCL_VAR_ADDR long V48 tmp18 ***** BB27 STMT00104 (IL 0x108... ???) [000493] -A--G+------ * ASG ref [000492] D---G+-N---- +--* LCL_VAR ref (AX) V48 tmp18 [000491] -----+------ \--* CNS_INT ref null ***** BB27 STMT00035 (IL ???... ???) [000155] -A---+------ * ASG int [000154] D----+-N---- +--* LCL_VAR int V18 loc15 [000487] -----+------ \--* LCL_VAR int V46 tmp16 ***** BB27 STMT00036 (IL 0x111...0x115) [000159] -----+------ * JTRUE void [000158] N----+-N-U-- \--* GT int [000156] -----+------ +--* LCL_VAR int V46 tmp16 [000157] -----+------ \--* LCL_VAR int V43 tmp13 ------------ BB28 [117..11A) -> BB30 (always), preds={BB27} succs={BB30} ***** BB28 STMT00074 (IL 0x117...0x118) [000350] -A---+------ * ASG int [000349] D----+-N---- +--* LCL_VAR int V33 tmp3 [000348] -----+------ \--* CNS_INT int 0 ------------ BB29 [11A..11F), preds={BB27} succs={BB30} ***** BB29 STMT00037 (IL 0x11A...0x11E) [000164] -A---+------ * ASG int [000163] D----+-N---- +--* LCL_VAR int V33 tmp3 [000162] -----+------ \--* SUB int [000160] -----+------ +--* LCL_VAR int V18 loc15 [000161] -----+------ \--* LCL_VAR int V17 loc14 ------------ BB30 [11F..126) -> BB32 (cond), preds={BB28,BB29} succs={BB31,BB32} ***** BB30 STMT00038 (IL ???...0x11F) [000168] -A---+------ * ASG int [000167] D----+-N---- +--* LCL_VAR int V19 loc16 [000166] -----+------ \--* LCL_VAR int V33 tmp3 ***** BB30 STMT00039 (IL 0x121...0x124) [000172] -----+------ * JTRUE void [000171] N----+-N---- \--* EQ int [000169] -----+------ +--* LCL_VAR int V33 tmp3 [000170] -----+------ \--* CNS_INT int 0 ------------ BB31 [126..12F), preds={BB30} succs={BB32} ***** BB31 STMT00073 (IL 0x126...0x12A) [000347] --CXG+------ * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft [000345] -----+------ arg0 in rcx +--* ADDR long [000344] ----G+-N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 [000346] -----+------ arg1 in rdx \--* LCL_VAR int V19 loc16 ------------ BB32 [12F..13E) -> BB36 (cond), preds={BB30,BB31} succs={BB33,BB36} ***** BB32 STMT00040 (IL 0x12F...0x133) [000177] -A---+------ * ASG int [000176] D----+-N---- +--* LCL_VAR int V20 loc17 [000175] -----+------ \--* SUB int [000173] -----+------ +--* LCL_VAR int V03 loc0 [000174] -----+------ \--* LCL_VAR int V13 loc10 ***** BB32 STMT00041 (IL 0x135...0x137) [000180] -A---+------ * ASG int [000179] D----+-N---- +--* LCL_VAR int V21 loc18 [000178] -----+------ \--* LCL_VAR int V20 loc17 ***** BB32 STMT00042 (IL 0x139...0x13C) [000184] -----+------ * JTRUE void [000183] N----+-N---- \--* EQ int [000181] -----+------ +--* LCL_VAR int V13 loc10 [000182] -----+------ \--* CNS_INT int 0 ------------ BB33 [13E..144) -> BB35 (cond), preds={BB32} succs={BB34,BB35} ***** BB33 STMT00070 (IL 0x13E...0x142) [000329] -----+------ * JTRUE void [000328] N----+-N-U-- \--* LE int [000326] -----+------ +--* LCL_VAR int V19 loc16 [000327] -----+------ \--* LCL_VAR int V21 loc18 ------------ BB34 [144..155) -> BB48 (always), preds={BB33} succs={BB48} ***** BB34 STMT00072 (IL 0x144...0x154) [000717] -ACXG------- * ASG int [000716] D------N---- +--* LCL_VAR int V51 tmp21 [000342] --CXG+------ \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits [000341] -----+------ arg4 out+20 +--* LCL_VAR byref V02 arg2 [000339] N----+------ arg2 in r8 +--* NE int [000337] -----+------ | +--* LCL_VAR int V10 loc7 [000338] -----+------ | \--* CNS_INT int 0 [000335] ----G+------ arg0 in rcx +--* LCL_VAR ref (AX) V12 loc9 [000336] -----+------ arg1 in rdx +--* LCL_VAR int V13 loc10 [000340] -----+------ arg3 in r9 \--* LCL_VAR ref V01 arg1 ------------ BB35 [155..15C), preds={BB33} succs={BB36} ***** BB35 STMT00071 (IL 0x155...0x15A) [000334] -A---+------ * ASG int [000333] D----+-N---- +--* LCL_VAR int V21 loc18 [000332] -----+------ \--* SUB int [000330] -----+------ +--* LCL_VAR int V21 loc18 [000331] -----+------ \--* LCL_VAR int V19 loc16 ------------ BB36 [15C..167) -> BB38 (cond), preds={BB32,BB35} succs={BB37,BB38} ***** BB36 STMT00105 (IL 0x15C... ???) [000724] -A--G+------ * COMMA void [000720] -A--G------- +--* ASG ref [000718] D---G--N---- | +--* LCL_VAR ref (AX) V68 tmp38 [000719] ----G--N---- | \--* LCL_VAR ref (AX) V56 tmp26 [000723] -A--G------- \--* ASG int [000721] D---G--N---- +--* LCL_VAR int (AX) V69 tmp39 [000722] ----G--N---- \--* LCL_VAR int (AX) V57 tmp27 ***** BB36 STMT00106 (IL 0x15C... ???) [000731] -A--G+------ * COMMA void [000727] -A--G------- +--* ASG ref [000725] D------N---- | +--* LCL_VAR ref V70 tmp40 [000726] ----G--N---- | \--* LCL_VAR ref (AX) V58 tmp28 [000730] -A--G------- \--* ASG int [000728] D------N---- +--* LCL_VAR int V71 tmp41 [000729] ----G--N---- \--* LCL_VAR int (AX) V59 tmp29 ***** BB36 STMT00044 (IL ???... ???) [000195] -ACXG+------ * JTRUE void [000503] JACXG+-N---- \--* LT int [000499] -ACXG+------ +--* CALL int System.Numerics.BigInteger.CompareTo [000752] -A--------L- this SETUP | +--* ASG byref [000751] D------N---- | | +--* LCL_VAR byref V84 tmp54 [000497] -----+------ | | \--* ADDR byref [000496] ----G+-N---- | | \--* LCL_VAR struct(AX)(P) V49 tmp19 | | \--* ref V49._bits (offs=0x00) -> V68 tmp38 | | \--* int V49._sign (offs=0x08) -> V69 tmp39 [000750] -A---+----L- arg1 SETUP | +--* COMMA void [000743] -A---------- | | +--* COMMA void [000738] -A---------- | | | +--* ASG byref [000737] D------N---- | | | | +--* LCL_VAR byref V83 tmp53 [000735] -----+------ | | | | \--* ADDR byref [000736] ----G+-N---- | | | | \--* LCL_VAR struct(AX) V76 tmp46 [000742] -A---------- | | | \--* ASG ref [000740] *------N---- | | | +--* IND ref [000739] ------------ | | | | \--* LCL_VAR byref V83 tmp53 Zero Fseq[_bits] [000741] -------N---- | | | \--* LCL_VAR ref V70 tmp40 [000749] -A---------- | | \--* ASG int [000747] *------N---- | | +--* IND int [000746] ------------ | | | \--* ADD byref [000744] ------------ | | | +--* LCL_VAR byref V83 tmp53 [000745] ------------ | | | \--* CNS_INT long 8 Fseq[_sign] [000748] -------N---- | | \--* LCL_VAR int V71 tmp41 [000753] ------------ this in rcx | +--* LCL_VAR byref V84 tmp54 [000755] ------------ arg1 in rdx | \--* ADDR byref [000754] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 [000502] -----+------ \--* CNS_INT int 0 ------------ BB37 [167..16B) -> BB39 (always), preds={BB36} succs={BB39} ***** BB37 STMT00069 (IL 0x167...0x169) [000324] -A---+------ * ASG int [000323] D----+-N---- +--* LCL_VAR int V34 tmp4 [000322] -----+------ \--* LCL_VAR int V19 loc16 ------------ BB38 [16B..16F), preds={BB36} succs={BB39} ***** BB38 STMT00045 (IL 0x16B...0x16E) [000200] -A---+------ * ASG int [000199] D----+-N---- +--* LCL_VAR int V34 tmp4 [000198] -----+------ \--* ADD int [000196] -----+------ +--* LCL_VAR int V19 loc16 [000197] -----+------ \--* CNS_INT int 1 ------------ BB39 [16F..1A4) -> BB44 (cond), preds={BB37,BB38} succs={BB40,BB44} ***** BB39 STMT00046 (IL ???...0x16F) [000204] -A---+------ * ASG int [000203] D----+-N---- +--* LCL_VAR int V22 loc19 [000202] -----+------ \--* LCL_VAR int V34 tmp4 ***** BB39 STMT00047 (IL 0x171...0x18A) [000208] --CXG+------ * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft [000206] -----+------ arg0 in rcx +--* ADDR long [000205] ----G+-N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 [000207] -----+------ arg1 in rdx \--* LCL_VAR int V21 loc18 ***** BB39 STMT00048 (IL 0x17A... ???) [000213] SACXG+------ * CALL void System.Numerics.BigInteger.DivRem [000797] -A--------L- arg0 SETUP +--* ASG long [000796] D------N---- | +--* LCL_VAR long V88 tmp58 [000220] -----+------ | \--* ADDR long [000219] ----G+-N---- | \--* LCL_VAR struct(AX)(P) V35 tmp5 | \--* ref V35._bits (offs=0x00) -> V62 tmp32 | \--* int V35._sign (offs=0x08) -> V63 tmp33 [000776] -A--G+----L- arg1 SETUP +--* COMMA void [000769] -A--G------- | +--* COMMA void [000764] -A---------- | | +--* ASG byref [000763] D------N---- | | | +--* LCL_VAR byref V85 tmp55 [000761] -----+------ | | | \--* ADDR byref [000762] ----G+-N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 [000768] -A--G------- | | \--* ASG ref [000766] *------N---- | | +--* IND ref [000765] ------------ | | | \--* LCL_VAR byref V85 tmp55 Zero Fseq[_bits] [000767] ----G--N---- | | \--* LCL_VAR ref (AX) V56 tmp26 [000775] -A--G------- | \--* ASG int [000773] *------N---- | +--* IND int [000772] ------------ | | \--* ADD byref [000770] ------------ | | +--* LCL_VAR byref V85 tmp55 [000771] ------------ | | \--* CNS_INT long 8 Fseq[_sign] [000774] ----G--N---- | \--* LCL_VAR int (AX) V57 tmp27 [000795] -A--G+----L- arg2 SETUP +--* COMMA void [000788] -A--G------- | +--* COMMA void [000783] -A---------- | | +--* ASG byref [000782] D------N---- | | | +--* LCL_VAR byref V87 tmp57 [000780] -----+------ | | | \--* ADDR byref [000781] -----+-N---- | | | \--* LCL_VAR struct(AX) V86 tmp56 [000787] -A--G------- | | \--* ASG ref [000785] *------N---- | | +--* IND ref [000784] ------------ | | | \--* LCL_VAR byref V87 tmp57 Zero Fseq[_bits] [000786] ----G--N---- | | \--* LCL_VAR ref (AX) V58 tmp28 [000794] -A--G------- | \--* ASG int [000792] *------N---- | +--* IND int [000791] ------------ | | \--* ADD byref [000789] ------------ | | +--* LCL_VAR byref V87 tmp57 [000790] ------------ | | \--* CNS_INT long 8 Fseq[_sign] [000793] ----G--N---- | \--* LCL_VAR int (AX) V59 tmp29 [000798] ------------ arg0 in rcx +--* LCL_VAR long V88 tmp58 [000800] ------------ arg1 in rdx +--* ADDR byref [000799] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 [000802] ------------ arg2 in r8 +--* ADDR byref [000801] -------N---- | \--* LCL_VAR struct(AX) V86 tmp56 [000212] -----+------ arg3 in r9 \--* ADDR long [000211] ----G+-N---- \--* LCL_VAR struct(AX)(P) V23 loc20 \--* ref V23._bits (offs=0x00) -> V60 tmp30 \--* int V23._sign (offs=0x08) -> V61 tmp31 ***** BB39 STMT00050 (IL ???... ???) [000226] -ACXG+------ * ASG long [000225] D----+-N---- +--* LCL_VAR long V24 loc21 [000218] -ACXG+------ \--* CALL long System.Numerics.BigInteger.op_Explicit [000822] -A--G+----L- arg0 SETUP +--* COMMA void [000815] -A--G------- | +--* COMMA void [000810] -A---------- | | +--* ASG byref [000809] D------N---- | | | +--* LCL_VAR byref V89 tmp59 [000807] -----+------ | | | \--* ADDR byref [000808] ----G+-N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 [000814] -A--G------- | | \--* ASG ref [000812] *------N---- | | +--* IND ref [000811] ------------ | | | \--* LCL_VAR byref V89 tmp59 Zero Fseq[_bits] [000813] ----G--N---- | | \--* LCL_VAR ref (AX) V62 tmp32 [000821] -A--G------- | \--* ASG int [000819] *------N---- | +--* IND int [000818] ------------ | | \--* ADD byref [000816] ------------ | | +--* LCL_VAR byref V89 tmp59 [000817] ------------ | | \--* CNS_INT long 8 Fseq[_sign] [000820] ----G--N---- | \--* LCL_VAR int (AX) V63 tmp33 [000824] ------------ arg0 in rcx \--* ADDR byref [000823] -------N---- \--* LCL_VAR struct(AX) V76 tmp46 ***** BB39 STMT00052 (IL ???... ???) [000232] -A--G+------ * ASG int [000231] D----+-N---- +--* LCL_VAR int V25 loc22 [000516] ----G+------ \--* EQ int [000514] ----G+------ +--* LCL_VAR int (AX) V61 tmp31 [000515] -----+------ \--* CNS_INT int 0 ***** BB39 STMT00054 (IL ???... ???) [000237] -ACXG+------ * ASG int [000236] D----+-N---- +--* LCL_VAR int V26 loc23 [000234] --CXG+------ \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits [000233] -----+------ arg0 in rcx \--* LCL_VAR long V24 loc21 ***** BB39 STMT00055 (IL 0x19E...0x1A2) [000241] -----+------ * JTRUE void [000240] N----+-N-U-- \--* LE int [000238] -----+------ +--* LCL_VAR int V26 loc23 [000239] -----+------ \--* LCL_VAR int V20 loc17 ------------ BB40 [1A4..1AF) -> BB42 (cond), preds={BB39} succs={BB41,BB42} ***** BB40 STMT00063 (IL 0x1A4...0x1A9) [000286] -A---+------ * ASG int [000285] D----+-N---- +--* LCL_VAR int V29 loc26 [000284] -----+------ \--* SUB int [000282] -----+------ +--* LCL_VAR int V26 loc23 [000283] -----+------ \--* LCL_VAR int V20 loc17 ***** BB40 STMT00064 (IL 0x1AB...0x1AD) [000290] -----+------ * JTRUE void [000289] J----+-N---- \--* EQ int [000287] -----+------ +--* LCL_VAR int V25 loc22 [000288] -----+------ \--* CNS_INT int 0 ------------ BB41 [1AF..1C3) -> BB43 (always), preds={BB40} succs={BB43} ***** BB41 STMT00068 (IL 0x1AF...0x1C1) [000320] -A---+------ * ASG int [000319] D----+-N---- +--* LCL_VAR int V37 tmp7 [000318] -----+------ \--* EQ int [000315] -----+------ +--* AND long [000305] -----+------ | +--* LCL_VAR long V24 loc21 [000314] -----+------ | \--* ADD long [000311] -----+------ | +--* LSH long [000307] -----+------ | | +--* CNS_INT long 1 [000310] -----+------ | | \--* AND int [000308] -----+------ | | +--* LCL_VAR int V29 loc26 [000309] -----+------ | | \--* CNS_INT int 63 [000313] -----+------ | \--* CNS_INT long -1 [000317] -----+------ \--* CNS_INT long 0 ------------ BB42 [1C3..1C4), preds={BB40} succs={BB43} ***** BB42 STMT00065 (IL 0x1C3...0x1C3) [000293] -A---+------ * ASG int [000292] D----+-N---- +--* LCL_VAR int V37 tmp7 [000291] -----+------ \--* CNS_INT int 0 ------------ BB43 [1C4..1D0), preds={BB41,BB42} succs={BB44} ***** BB43 STMT00066 (IL ???...0x1C4) [000297] -A---+------ * ASG int [000296] D----+-N---- +--* LCL_VAR int V25 loc22 [000826] -----+------ \--* CAST int <- bool <- int [000295] -----+------ \--* LCL_VAR int V37 tmp7 ***** BB43 STMT00067 (IL 0x1C6...0x1CE) [000304] -A---+------ * ASG long [000303] D----+-N---- +--* LCL_VAR long V24 loc21 [000302] -----+------ \--* RSZ long [000298] -----+------ +--* LCL_VAR long V24 loc21 [000301] -----+------ \--* AND int [000299] -----+------ +--* LCL_VAR int V29 loc26 [000300] -----+------ \--* CNS_INT int 63 ------------ BB44 [1D0..1E7) -> BB46 (cond), preds={BB39,BB43} succs={BB45,BB46} ***** BB44 STMT00057 (IL ???... ???) [000254] -ACXG+------ * ASG long [000253] D----+-N---- +--* LCL_VAR long V27 loc24 [000252] -ACXG+------ \--* ADD long [000250] -ACXG+------ +--* LSH long [000243] -ACXG+------ | +--* CALL long System.Numerics.BigInteger.op_Explicit [000845] -A--G+----L- arg0 SETUP | | +--* COMMA void [000838] -A--G------- | | | +--* COMMA void [000833] -A---------- | | | | +--* ASG byref [000832] D------N---- | | | | | +--* LCL_VAR byref V90 tmp60 [000830] -----+------ | | | | | \--* ADDR byref [000831] ----G+-N---- | | | | | \--* LCL_VAR struct(AX) V76 tmp46 [000837] -A--G------- | | | | \--* ASG ref [000835] *------N---- | | | | +--* IND ref [000834] ------------ | | | | | \--* LCL_VAR byref V90 tmp60 Zero Fseq[_bits] [000836] ----G--N---- | | | | \--* LCL_VAR ref (AX) V54 tmp24 [000844] -A--G------- | | | \--* ASG int [000842] *------N---- | | | +--* IND int [000841] ------------ | | | | \--* ADD byref [000839] ------------ | | | | +--* LCL_VAR byref V90 tmp60 [000840] ------------ | | | | \--* CNS_INT long 8 Fseq[_sign] [000843] ----G--N---- | | | \--* LCL_VAR int (AX) V55 tmp25 [000847] ------------ arg0 in rcx | | \--* ADDR byref [000846] -------N---- | | \--* LCL_VAR struct(AX) V76 tmp46 [000249] -----+------ | \--* AND int [000247] -----+------ | +--* LCL_VAR int V20 loc17 [000248] -----+------ | \--* CNS_INT int 63 [000251] -----+------ \--* LCL_VAR long V24 loc21 ***** BB44 STMT00058 (IL 0x1E2...0x1E5) [000258] -----+------ * JTRUE void [000257] N----+-N---- \--* NE int [000255] -----+------ +--* LCL_VAR int V13 loc10 [000256] -----+------ \--* CNS_INT int 0 ------------ BB45 [1E7..1EE) -> BB47 (always), preds={BB44} succs={BB47} ***** BB45 STMT00062 (IL 0x1E7...0x1EC) [000280] -A---+------ * ASG int [000279] D----+-N---- +--* LCL_VAR int V36 tmp6 [000278] -----+------ \--* ADD int [000276] -----+------ +--* NEG int [000275] -----+------ | \--* LCL_VAR int V22 loc19 [000277] -----+------ \--* CNS_INT int -1 ------------ BB46 [1EE..1F2), preds={BB44} succs={BB47} ***** BB46 STMT00059 (IL 0x1EE...0x1F1) [000263] -A---+------ * ASG int [000262] D----+-N---- +--* LCL_VAR int V36 tmp6 [000261] -----+------ \--* ADD int [000259] -----+------ +--* LCL_VAR int V13 loc10 [000260] -----+------ \--* CNS_INT int -2 ------------ BB47 [1F2..202) -> BB48 (always), preds={BB45,BB46} succs={BB48} ***** BB47 STMT00060 (IL ???...0x1F2) [000267] -A---+------ * ASG int [000266] D----+-N---- +--* LCL_VAR int V28 loc25 [000265] -----+------ \--* LCL_VAR int V36 tmp6 ***** BB47 STMT00061 (IL 0x1F4...0x201) [000853] -ACXG------- * ASG int [000852] D------N---- +--* LCL_VAR int V51 tmp21 [000273] --CXG+------ \--* CALL nullcheck int FloatingPointType.AssembleFloatingPointValue [000272] -----+------ arg4 out+20 +--* LCL_VAR byref V02 arg2 [000268] -----+------ this in rcx +--* LCL_VAR ref V01 arg1 [000269] -----+------ arg1 in rdx +--* LCL_VAR long V27 loc24 [000270] -----+------ arg2 in r8 +--* LCL_VAR int V36 tmp6 [000271] -----+------ arg3 in r9 \--* LCL_VAR int V25 loc22 ------------ BB48 [???..???) (return), preds={BB19,BB34,BB47} succs={} ***** BB48 STMT00109 (IL ???... ???) [000523] -----+------ * RETURN int [000522] -----+-N---- \--* LCL_VAR int V51 tmp21 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Starting PHASE GS Cookie No GS security needed *************** Finishing PHASE GS Cookie *************** Starting PHASE Compute edge weights (1, false) *************** In fgComputeBlockAndEdgeWeights() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB49 [0056] 1 1 [???..???) i internal label target BB01 [0000] 1 BB49 1 [000..00D)-> BB04 ( cond ) i label target idxlen BB02 [0001] 1 BB01 1 [00D..017) (return) i hascall gcsafe BB04 [0002] 1 BB01 1 [017..065)-> BB07 ( cond ) i label target hascall gcsafe BB06 [0038] 1 BB04 1 [020..021)-> BB08 (always) i BB07 [0039] 1 BB04 1 [020..021) i label target BB08 [0040] 2 BB06,BB07 1 [000..000)-> BB11 ( cond ) i internal label target idxlen BB10 [0043] 1 BB08 1 [000..000)-> BB12 (always) i internal BB11 [0044] 1 BB08 1 [000..000) i internal label target BB12 [0045] 2 BB10,BB11 1 [???..???)-> BB17 ( cond ) i internal label target hascall gcsafe idxlen BB13 [0003] 1 BB12 1 [065..070)-> BB16 ( cond ) i hascall gcsafe BB14 [0004] 1 BB13 1 [070..07A) (return) i hascall gcsafe BB16 [0005] 1 BB13 1 [07A..082) i label target hascall gcsafe BB17 [0006] 2 BB12,BB16 1 [082..092)-> BB19 ( cond ) i label target hascall gcsafe BB18 [0007] 1 BB17 1 [092..096)-> BB20 ( cond ) i BB19 [0008] 2 BB17,BB18 1 [096..0A7)-> BB48 (always) i label target hascall gcsafe BB20 [0009] 1 BB18 1 [0A7..0B0)-> BB22 ( cond ) i label target BB21 [0010] 1 BB20 1 [0B0..0B4)-> BB23 (always) i BB22 [0011] 1 BB20 1 [0B4..0BE) i label target BB23 [0012] 2 BB21,BB22 1 [0BE..0C4)-> BB27 ( cond ) i label target BB24 [0013] 1 BB23 1 [0C4..0D9)-> BB27 ( cond ) i hascall gcsafe idxlen BB25 [0014] 1 BB24 1 [0D9..0E3) (return) i hascall gcsafe BB27 [0015] 2 BB23,BB24 1 [0E3..117)-> BB29 ( cond ) i label target hascall gcsafe BB28 [0016] 1 BB27 1 [117..11A)-> BB30 (always) i BB29 [0017] 1 BB27 1 [11A..11F) i label target BB30 [0018] 2 BB28,BB29 1 [11F..126)-> BB32 ( cond ) i label target BB31 [0019] 1 BB30 1 [126..12F) i hascall gcsafe BB32 [0020] 2 BB30,BB31 1 [12F..13E)-> BB36 ( cond ) i label target BB33 [0021] 1 BB32 1 [13E..144)-> BB35 ( cond ) i BB34 [0022] 1 BB33 1 [144..155)-> BB48 (always) i hascall gcsafe BB35 [0023] 1 BB33 1 [155..15C) i label target BB36 [0024] 2 BB32,BB35 1 [15C..167)-> BB38 ( cond ) i label target hascall gcsafe BB37 [0025] 1 BB36 1 [167..16B)-> BB39 (always) i BB38 [0026] 1 BB36 1 [16B..16F) i label target BB39 [0027] 2 BB37,BB38 1 [16F..1A4)-> BB44 ( cond ) i label target hascall gcsafe BB40 [0028] 1 BB39 1 [1A4..1AF)-> BB42 ( cond ) i BB41 [0029] 1 BB40 1 [1AF..1C3)-> BB43 (always) i BB42 [0030] 1 BB40 1 [1C3..1C4) i label target BB43 [0031] 2 BB41,BB42 1 [1C4..1D0) i label target BB44 [0032] 2 BB39,BB43 1 [1D0..1E7)-> BB46 ( cond ) i label target hascall gcsafe BB45 [0033] 1 BB44 1 [1E7..1EE)-> BB47 (always) i BB46 [0034] 1 BB44 1 [1EE..1F2) i label target BB47 [0035] 2 BB45,BB46 1 [1F2..202)-> BB48 (always) i label target hascall gcsafe BB48 [0054] 3 BB19,BB34,BB47 1 [???..???) (return) keep internal target ----------------------------------------------------------------------------------------------------------------------------------------- -- no profile data, so using default called count fgComputeEdgeWeights() found inconsistent profile data, not using the edge weights *************** Finishing PHASE Compute edge weights (1, false) *************** Starting PHASE Create EH funclets *************** In fgCreateFunclets() After fgCreateFunclets() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB49 [0056] 1 1 [???..???) i internal label target BB01 [0000] 1 BB49 1 [000..00D)-> BB04 ( cond ) i label target idxlen BB02 [0001] 1 BB01 1 [00D..017) (return) i hascall gcsafe BB04 [0002] 1 BB01 1 [017..065)-> BB07 ( cond ) i label target hascall gcsafe BB06 [0038] 1 BB04 1 [020..021)-> BB08 (always) i BB07 [0039] 1 BB04 1 [020..021) i label target BB08 [0040] 2 BB06,BB07 1 [000..000)-> BB11 ( cond ) i internal label target idxlen BB10 [0043] 1 BB08 1 [000..000)-> BB12 (always) i internal BB11 [0044] 1 BB08 1 [000..000) i internal label target BB12 [0045] 2 BB10,BB11 1 [???..???)-> BB17 ( cond ) i internal label target hascall gcsafe idxlen BB13 [0003] 1 BB12 1 [065..070)-> BB16 ( cond ) i hascall gcsafe BB14 [0004] 1 BB13 1 [070..07A) (return) i hascall gcsafe BB16 [0005] 1 BB13 1 [07A..082) i label target hascall gcsafe BB17 [0006] 2 BB12,BB16 1 [082..092)-> BB19 ( cond ) i label target hascall gcsafe BB18 [0007] 1 BB17 1 [092..096)-> BB20 ( cond ) i BB19 [0008] 2 BB17,BB18 1 [096..0A7)-> BB48 (always) i label target hascall gcsafe BB20 [0009] 1 BB18 1 [0A7..0B0)-> BB22 ( cond ) i label target BB21 [0010] 1 BB20 1 [0B0..0B4)-> BB23 (always) i BB22 [0011] 1 BB20 1 [0B4..0BE) i label target BB23 [0012] 2 BB21,BB22 1 [0BE..0C4)-> BB27 ( cond ) i label target BB24 [0013] 1 BB23 1 [0C4..0D9)-> BB27 ( cond ) i hascall gcsafe idxlen BB25 [0014] 1 BB24 1 [0D9..0E3) (return) i hascall gcsafe BB27 [0015] 2 BB23,BB24 1 [0E3..117)-> BB29 ( cond ) i label target hascall gcsafe BB28 [0016] 1 BB27 1 [117..11A)-> BB30 (always) i BB29 [0017] 1 BB27 1 [11A..11F) i label target BB30 [0018] 2 BB28,BB29 1 [11F..126)-> BB32 ( cond ) i label target BB31 [0019] 1 BB30 1 [126..12F) i hascall gcsafe BB32 [0020] 2 BB30,BB31 1 [12F..13E)-> BB36 ( cond ) i label target BB33 [0021] 1 BB32 1 [13E..144)-> BB35 ( cond ) i BB34 [0022] 1 BB33 1 [144..155)-> BB48 (always) i hascall gcsafe BB35 [0023] 1 BB33 1 [155..15C) i label target BB36 [0024] 2 BB32,BB35 1 [15C..167)-> BB38 ( cond ) i label target hascall gcsafe BB37 [0025] 1 BB36 1 [167..16B)-> BB39 (always) i BB38 [0026] 1 BB36 1 [16B..16F) i label target BB39 [0027] 2 BB37,BB38 1 [16F..1A4)-> BB44 ( cond ) i label target hascall gcsafe BB40 [0028] 1 BB39 1 [1A4..1AF)-> BB42 ( cond ) i BB41 [0029] 1 BB40 1 [1AF..1C3)-> BB43 (always) i BB42 [0030] 1 BB40 1 [1C3..1C4) i label target BB43 [0031] 2 BB41,BB42 1 [1C4..1D0) i label target BB44 [0032] 2 BB39,BB43 1 [1D0..1E7)-> BB46 ( cond ) i label target hascall gcsafe BB45 [0033] 1 BB44 1 [1E7..1EE)-> BB47 (always) i BB46 [0034] 1 BB44 1 [1EE..1F2) i label target BB47 [0035] 2 BB45,BB46 1 [1F2..202)-> BB48 (always) i label target hascall gcsafe BB48 [0054] 3 BB19,BB34,BB47 1 [???..???) (return) keep internal target ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** In fgDebugCheckBBlist *************** Finishing PHASE Create EH funclets *************** Starting PHASE Optimize layout *************** In optOptimizeLayout() *************** Exception Handling table is empty *************** In fgDebugCheckBBlist *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB49 [0056] 1 1 [???..???) i internal label target BB01 [0000] 1 BB49 1 [000..00D)-> BB04 ( cond ) i label target idxlen BB02 [0001] 1 BB01 1 [00D..017) (return) i hascall gcsafe BB04 [0002] 1 BB01 1 [017..065)-> BB07 ( cond ) i label target hascall gcsafe BB06 [0038] 1 BB04 1 [020..021)-> BB08 (always) i BB07 [0039] 1 BB04 1 [020..021) i label target BB08 [0040] 2 BB06,BB07 1 [000..000)-> BB11 ( cond ) i internal label target idxlen BB10 [0043] 1 BB08 1 [000..000)-> BB12 (always) i internal BB11 [0044] 1 BB08 1 [000..000) i internal label target BB12 [0045] 2 BB10,BB11 1 [???..???)-> BB17 ( cond ) i internal label target hascall gcsafe idxlen BB13 [0003] 1 BB12 1 [065..070)-> BB16 ( cond ) i hascall gcsafe BB14 [0004] 1 BB13 1 [070..07A) (return) i hascall gcsafe BB16 [0005] 1 BB13 1 [07A..082) i label target hascall gcsafe BB17 [0006] 2 BB12,BB16 1 [082..092)-> BB19 ( cond ) i label target hascall gcsafe BB18 [0007] 1 BB17 1 [092..096)-> BB20 ( cond ) i BB19 [0008] 2 BB17,BB18 1 [096..0A7)-> BB48 (always) i label target hascall gcsafe BB20 [0009] 1 BB18 1 [0A7..0B0)-> BB22 ( cond ) i label target BB21 [0010] 1 BB20 1 [0B0..0B4)-> BB23 (always) i BB22 [0011] 1 BB20 1 [0B4..0BE) i label target BB23 [0012] 2 BB21,BB22 1 [0BE..0C4)-> BB27 ( cond ) i label target BB24 [0013] 1 BB23 1 [0C4..0D9)-> BB27 ( cond ) i hascall gcsafe idxlen BB25 [0014] 1 BB24 1 [0D9..0E3) (return) i hascall gcsafe BB27 [0015] 2 BB23,BB24 1 [0E3..117)-> BB29 ( cond ) i label target hascall gcsafe BB28 [0016] 1 BB27 1 [117..11A)-> BB30 (always) i BB29 [0017] 1 BB27 1 [11A..11F) i label target BB30 [0018] 2 BB28,BB29 1 [11F..126)-> BB32 ( cond ) i label target BB31 [0019] 1 BB30 1 [126..12F) i hascall gcsafe BB32 [0020] 2 BB30,BB31 1 [12F..13E)-> BB36 ( cond ) i label target BB33 [0021] 1 BB32 1 [13E..144)-> BB35 ( cond ) i BB34 [0022] 1 BB33 1 [144..155)-> BB48 (always) i hascall gcsafe BB35 [0023] 1 BB33 1 [155..15C) i label target BB36 [0024] 2 BB32,BB35 1 [15C..167)-> BB38 ( cond ) i label target hascall gcsafe BB37 [0025] 1 BB36 1 [167..16B)-> BB39 (always) i BB38 [0026] 1 BB36 1 [16B..16F) i label target BB39 [0027] 2 BB37,BB38 1 [16F..1A4)-> BB44 ( cond ) i label target hascall gcsafe BB40 [0028] 1 BB39 1 [1A4..1AF)-> BB42 ( cond ) i BB41 [0029] 1 BB40 1 [1AF..1C3)-> BB43 (always) i BB42 [0030] 1 BB40 1 [1C3..1C4) i label target BB43 [0031] 2 BB41,BB42 1 [1C4..1D0) i label target BB44 [0032] 2 BB39,BB43 1 [1D0..1E7)-> BB46 ( cond ) i label target hascall gcsafe BB45 [0033] 1 BB44 1 [1E7..1EE)-> BB47 (always) i BB46 [0034] 1 BB44 1 [1EE..1F2) i label target BB47 [0035] 2 BB45,BB46 1 [1F2..202)-> BB48 (always) i label target hascall gcsafe BB48 [0054] 3 BB19,BB34,BB47 1 [???..???) (return) keep internal target ----------------------------------------------------------------------------------------------------------------------------------------- Removing unconditional jump to next block (BB47 -> BB48) (converted BB47 to fall-through) After updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB49 [0056] 1 1 [???..???) i internal label target BB01 [0000] 1 BB49 1 [000..00D)-> BB04 ( cond ) i label target idxlen BB02 [0001] 1 BB01 1 [00D..017) (return) i hascall gcsafe BB04 [0002] 1 BB01 1 [017..065)-> BB07 ( cond ) i label target hascall gcsafe BB06 [0038] 1 BB04 1 [020..021)-> BB08 (always) i BB07 [0039] 1 BB04 1 [020..021) i label target BB08 [0040] 2 BB06,BB07 1 [000..000)-> BB11 ( cond ) i internal label target idxlen BB10 [0043] 1 BB08 1 [000..000)-> BB12 (always) i internal BB11 [0044] 1 BB08 1 [000..000) i internal label target BB12 [0045] 2 BB10,BB11 1 [???..???)-> BB17 ( cond ) i internal label target hascall gcsafe idxlen BB13 [0003] 1 BB12 1 [065..070)-> BB16 ( cond ) i hascall gcsafe BB14 [0004] 1 BB13 1 [070..07A) (return) i hascall gcsafe BB16 [0005] 1 BB13 1 [07A..082) i label target hascall gcsafe BB17 [0006] 2 BB12,BB16 1 [082..092)-> BB19 ( cond ) i label target hascall gcsafe BB18 [0007] 1 BB17 1 [092..096)-> BB20 ( cond ) i BB19 [0008] 2 BB17,BB18 1 [096..0A7)-> BB48 (always) i label target hascall gcsafe BB20 [0009] 1 BB18 1 [0A7..0B0)-> BB22 ( cond ) i label target BB21 [0010] 1 BB20 1 [0B0..0B4)-> BB23 (always) i BB22 [0011] 1 BB20 1 [0B4..0BE) i label target BB23 [0012] 2 BB21,BB22 1 [0BE..0C4)-> BB27 ( cond ) i label target BB24 [0013] 1 BB23 1 [0C4..0D9)-> BB27 ( cond ) i hascall gcsafe idxlen BB25 [0014] 1 BB24 1 [0D9..0E3) (return) i hascall gcsafe BB27 [0015] 2 BB23,BB24 1 [0E3..117)-> BB29 ( cond ) i label target hascall gcsafe BB28 [0016] 1 BB27 1 [117..11A)-> BB30 (always) i BB29 [0017] 1 BB27 1 [11A..11F) i label target BB30 [0018] 2 BB28,BB29 1 [11F..126)-> BB32 ( cond ) i label target BB31 [0019] 1 BB30 1 [126..12F) i hascall gcsafe BB32 [0020] 2 BB30,BB31 1 [12F..13E)-> BB36 ( cond ) i label target BB33 [0021] 1 BB32 1 [13E..144)-> BB35 ( cond ) i BB34 [0022] 1 BB33 1 [144..155)-> BB48 (always) i hascall gcsafe BB35 [0023] 1 BB33 1 [155..15C) i label target BB36 [0024] 2 BB32,BB35 1 [15C..167)-> BB38 ( cond ) i label target hascall gcsafe BB37 [0025] 1 BB36 1 [167..16B)-> BB39 (always) i BB38 [0026] 1 BB36 1 [16B..16F) i label target BB39 [0027] 2 BB37,BB38 1 [16F..1A4)-> BB44 ( cond ) i label target hascall gcsafe BB40 [0028] 1 BB39 1 [1A4..1AF)-> BB42 ( cond ) i BB41 [0029] 1 BB40 1 [1AF..1C3)-> BB43 (always) i BB42 [0030] 1 BB40 1 [1C3..1C4) i label target BB43 [0031] 2 BB41,BB42 1 [1C4..1D0) i label target BB44 [0032] 2 BB39,BB43 1 [1D0..1E7)-> BB46 ( cond ) i label target hascall gcsafe BB45 [0033] 1 BB44 1 [1E7..1EE)-> BB47 (always) i BB46 [0034] 1 BB44 1 [1EE..1F2) i label target BB47 [0035] 2 BB45,BB46 1 [1F2..202) i label target hascall gcsafe BB48 [0054] 3 BB19,BB34,BB47 1 [???..???) (return) keep internal target ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** In fgDebugCheckBBlist *************** In fgExpandRarelyRunBlocks() *************** In fgReorderBlocks() Initial BasicBlocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB49 [0056] 1 1 [???..???) i internal label target BB01 [0000] 1 BB49 1 [000..00D)-> BB04 ( cond ) i label target idxlen BB02 [0001] 1 BB01 1 [00D..017) (return) i hascall gcsafe BB04 [0002] 1 BB01 1 [017..065)-> BB07 ( cond ) i label target hascall gcsafe BB06 [0038] 1 BB04 1 [020..021)-> BB08 (always) i BB07 [0039] 1 BB04 1 [020..021) i label target BB08 [0040] 2 BB06,BB07 1 [000..000)-> BB11 ( cond ) i internal label target idxlen BB10 [0043] 1 BB08 1 [000..000)-> BB12 (always) i internal BB11 [0044] 1 BB08 1 [000..000) i internal label target BB12 [0045] 2 BB10,BB11 1 [???..???)-> BB17 ( cond ) i internal label target hascall gcsafe idxlen BB13 [0003] 1 BB12 1 [065..070)-> BB16 ( cond ) i hascall gcsafe BB14 [0004] 1 BB13 1 [070..07A) (return) i hascall gcsafe BB16 [0005] 1 BB13 1 [07A..082) i label target hascall gcsafe BB17 [0006] 2 BB12,BB16 1 [082..092)-> BB19 ( cond ) i label target hascall gcsafe BB18 [0007] 1 BB17 1 [092..096)-> BB20 ( cond ) i BB19 [0008] 2 BB17,BB18 1 [096..0A7)-> BB48 (always) i label target hascall gcsafe BB20 [0009] 1 BB18 1 [0A7..0B0)-> BB22 ( cond ) i label target BB21 [0010] 1 BB20 1 [0B0..0B4)-> BB23 (always) i BB22 [0011] 1 BB20 1 [0B4..0BE) i label target BB23 [0012] 2 BB21,BB22 1 [0BE..0C4)-> BB27 ( cond ) i label target BB24 [0013] 1 BB23 1 [0C4..0D9)-> BB27 ( cond ) i hascall gcsafe idxlen BB25 [0014] 1 BB24 1 [0D9..0E3) (return) i hascall gcsafe BB27 [0015] 2 BB23,BB24 1 [0E3..117)-> BB29 ( cond ) i label target hascall gcsafe BB28 [0016] 1 BB27 1 [117..11A)-> BB30 (always) i BB29 [0017] 1 BB27 1 [11A..11F) i label target BB30 [0018] 2 BB28,BB29 1 [11F..126)-> BB32 ( cond ) i label target BB31 [0019] 1 BB30 1 [126..12F) i hascall gcsafe BB32 [0020] 2 BB30,BB31 1 [12F..13E)-> BB36 ( cond ) i label target BB33 [0021] 1 BB32 1 [13E..144)-> BB35 ( cond ) i BB34 [0022] 1 BB33 1 [144..155)-> BB48 (always) i hascall gcsafe BB35 [0023] 1 BB33 1 [155..15C) i label target BB36 [0024] 2 BB32,BB35 1 [15C..167)-> BB38 ( cond ) i label target hascall gcsafe BB37 [0025] 1 BB36 1 [167..16B)-> BB39 (always) i BB38 [0026] 1 BB36 1 [16B..16F) i label target BB39 [0027] 2 BB37,BB38 1 [16F..1A4)-> BB44 ( cond ) i label target hascall gcsafe BB40 [0028] 1 BB39 1 [1A4..1AF)-> BB42 ( cond ) i BB41 [0029] 1 BB40 1 [1AF..1C3)-> BB43 (always) i BB42 [0030] 1 BB40 1 [1C3..1C4) i label target BB43 [0031] 2 BB41,BB42 1 [1C4..1D0) i label target BB44 [0032] 2 BB39,BB43 1 [1D0..1E7)-> BB46 ( cond ) i label target hascall gcsafe BB45 [0033] 1 BB44 1 [1E7..1EE)-> BB47 (always) i BB46 [0034] 1 BB44 1 [1EE..1F2) i label target BB47 [0035] 2 BB45,BB46 1 [1F2..202) i label target hascall gcsafe BB48 [0054] 3 BB19,BB34,BB47 1 [???..???) (return) keep internal target ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB49 [0056] 1 1 [???..???) i internal label target BB01 [0000] 1 BB49 1 [000..00D)-> BB04 ( cond ) i label target idxlen BB02 [0001] 1 BB01 1 [00D..017) (return) i hascall gcsafe BB04 [0002] 1 BB01 1 [017..065)-> BB07 ( cond ) i label target hascall gcsafe BB06 [0038] 1 BB04 1 [020..021)-> BB08 (always) i BB07 [0039] 1 BB04 1 [020..021) i label target BB08 [0040] 2 BB06,BB07 1 [000..000)-> BB11 ( cond ) i internal label target idxlen BB10 [0043] 1 BB08 1 [000..000)-> BB12 (always) i internal BB11 [0044] 1 BB08 1 [000..000) i internal label target BB12 [0045] 2 BB10,BB11 1 [???..???)-> BB17 ( cond ) i internal label target hascall gcsafe idxlen BB13 [0003] 1 BB12 1 [065..070)-> BB16 ( cond ) i hascall gcsafe BB14 [0004] 1 BB13 1 [070..07A) (return) i hascall gcsafe BB16 [0005] 1 BB13 1 [07A..082) i label target hascall gcsafe BB17 [0006] 2 BB12,BB16 1 [082..092)-> BB19 ( cond ) i label target hascall gcsafe BB18 [0007] 1 BB17 1 [092..096)-> BB20 ( cond ) i BB19 [0008] 2 BB17,BB18 1 [096..0A7)-> BB48 (always) i label target hascall gcsafe BB20 [0009] 1 BB18 1 [0A7..0B0)-> BB22 ( cond ) i label target BB21 [0010] 1 BB20 1 [0B0..0B4)-> BB23 (always) i BB22 [0011] 1 BB20 1 [0B4..0BE) i label target BB23 [0012] 2 BB21,BB22 1 [0BE..0C4)-> BB27 ( cond ) i label target BB24 [0013] 1 BB23 1 [0C4..0D9)-> BB27 ( cond ) i hascall gcsafe idxlen BB25 [0014] 1 BB24 1 [0D9..0E3) (return) i hascall gcsafe BB27 [0015] 2 BB23,BB24 1 [0E3..117)-> BB29 ( cond ) i label target hascall gcsafe BB28 [0016] 1 BB27 1 [117..11A)-> BB30 (always) i BB29 [0017] 1 BB27 1 [11A..11F) i label target BB30 [0018] 2 BB28,BB29 1 [11F..126)-> BB32 ( cond ) i label target BB31 [0019] 1 BB30 1 [126..12F) i hascall gcsafe BB32 [0020] 2 BB30,BB31 1 [12F..13E)-> BB36 ( cond ) i label target BB33 [0021] 1 BB32 1 [13E..144)-> BB35 ( cond ) i BB34 [0022] 1 BB33 1 [144..155)-> BB48 (always) i hascall gcsafe BB35 [0023] 1 BB33 1 [155..15C) i label target BB36 [0024] 2 BB32,BB35 1 [15C..167)-> BB38 ( cond ) i label target hascall gcsafe BB37 [0025] 1 BB36 1 [167..16B)-> BB39 (always) i BB38 [0026] 1 BB36 1 [16B..16F) i label target BB39 [0027] 2 BB37,BB38 1 [16F..1A4)-> BB44 ( cond ) i label target hascall gcsafe BB40 [0028] 1 BB39 1 [1A4..1AF)-> BB42 ( cond ) i BB41 [0029] 1 BB40 1 [1AF..1C3)-> BB43 (always) i BB42 [0030] 1 BB40 1 [1C3..1C4) i label target BB43 [0031] 2 BB41,BB42 1 [1C4..1D0) i label target BB44 [0032] 2 BB39,BB43 1 [1D0..1E7)-> BB46 ( cond ) i label target hascall gcsafe BB45 [0033] 1 BB44 1 [1E7..1EE)-> BB47 (always) i BB46 [0034] 1 BB44 1 [1EE..1F2) i label target BB47 [0035] 2 BB45,BB46 1 [1F2..202) i label target hascall gcsafe BB48 [0054] 3 BB19,BB34,BB47 1 [???..???) (return) keep internal target ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Finishing PHASE Optimize layout *************** Starting PHASE Compute blocks reachability *************** In fgComputeReachability *************** In fgDebugCheckBBlist Renumbering the basic blocks for fgComputeReachability pass #1 *************** Before renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB49 [0056] 1 1 [???..???) i internal label target BB01 [0000] 1 BB49 1 [000..00D)-> BB04 ( cond ) i label target idxlen BB02 [0001] 1 BB01 1 [00D..017) (return) i hascall gcsafe BB04 [0002] 1 BB01 1 [017..065)-> BB07 ( cond ) i label target hascall gcsafe BB06 [0038] 1 BB04 1 [020..021)-> BB08 (always) i BB07 [0039] 1 BB04 1 [020..021) i label target BB08 [0040] 2 BB06,BB07 1 [000..000)-> BB11 ( cond ) i internal label target idxlen BB10 [0043] 1 BB08 1 [000..000)-> BB12 (always) i internal BB11 [0044] 1 BB08 1 [000..000) i internal label target BB12 [0045] 2 BB10,BB11 1 [???..???)-> BB17 ( cond ) i internal label target hascall gcsafe idxlen BB13 [0003] 1 BB12 1 [065..070)-> BB16 ( cond ) i hascall gcsafe BB14 [0004] 1 BB13 1 [070..07A) (return) i hascall gcsafe BB16 [0005] 1 BB13 1 [07A..082) i label target hascall gcsafe BB17 [0006] 2 BB12,BB16 1 [082..092)-> BB19 ( cond ) i label target hascall gcsafe BB18 [0007] 1 BB17 1 [092..096)-> BB20 ( cond ) i BB19 [0008] 2 BB17,BB18 1 [096..0A7)-> BB48 (always) i label target hascall gcsafe BB20 [0009] 1 BB18 1 [0A7..0B0)-> BB22 ( cond ) i label target BB21 [0010] 1 BB20 1 [0B0..0B4)-> BB23 (always) i BB22 [0011] 1 BB20 1 [0B4..0BE) i label target BB23 [0012] 2 BB21,BB22 1 [0BE..0C4)-> BB27 ( cond ) i label target BB24 [0013] 1 BB23 1 [0C4..0D9)-> BB27 ( cond ) i hascall gcsafe idxlen BB25 [0014] 1 BB24 1 [0D9..0E3) (return) i hascall gcsafe BB27 [0015] 2 BB23,BB24 1 [0E3..117)-> BB29 ( cond ) i label target hascall gcsafe BB28 [0016] 1 BB27 1 [117..11A)-> BB30 (always) i BB29 [0017] 1 BB27 1 [11A..11F) i label target BB30 [0018] 2 BB28,BB29 1 [11F..126)-> BB32 ( cond ) i label target BB31 [0019] 1 BB30 1 [126..12F) i hascall gcsafe BB32 [0020] 2 BB30,BB31 1 [12F..13E)-> BB36 ( cond ) i label target BB33 [0021] 1 BB32 1 [13E..144)-> BB35 ( cond ) i BB34 [0022] 1 BB33 1 [144..155)-> BB48 (always) i hascall gcsafe BB35 [0023] 1 BB33 1 [155..15C) i label target BB36 [0024] 2 BB32,BB35 1 [15C..167)-> BB38 ( cond ) i label target hascall gcsafe BB37 [0025] 1 BB36 1 [167..16B)-> BB39 (always) i BB38 [0026] 1 BB36 1 [16B..16F) i label target BB39 [0027] 2 BB37,BB38 1 [16F..1A4)-> BB44 ( cond ) i label target hascall gcsafe BB40 [0028] 1 BB39 1 [1A4..1AF)-> BB42 ( cond ) i BB41 [0029] 1 BB40 1 [1AF..1C3)-> BB43 (always) i BB42 [0030] 1 BB40 1 [1C3..1C4) i label target BB43 [0031] 2 BB41,BB42 1 [1C4..1D0) i label target BB44 [0032] 2 BB39,BB43 1 [1D0..1E7)-> BB46 ( cond ) i label target hascall gcsafe BB45 [0033] 1 BB44 1 [1E7..1EE)-> BB47 (always) i BB46 [0034] 1 BB44 1 [1EE..1F2) i label target BB47 [0035] 2 BB45,BB46 1 [1F2..202) i label target hascall gcsafe BB48 [0054] 3 BB19,BB34,BB47 1 [???..???) (return) keep internal target ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty Renumber BB49 to BB01 Renumber BB01 to BB02 Renumber BB02 to BB03 Renumber BB06 to BB05 Renumber BB07 to BB06 Renumber BB08 to BB07 Renumber BB10 to BB08 Renumber BB11 to BB09 Renumber BB12 to BB10 Renumber BB13 to BB11 Renumber BB14 to BB12 Renumber BB16 to BB13 Renumber BB17 to BB14 Renumber BB18 to BB15 Renumber BB19 to BB16 Renumber BB20 to BB17 Renumber BB21 to BB18 Renumber BB22 to BB19 Renumber BB23 to BB20 Renumber BB24 to BB21 Renumber BB25 to BB22 Renumber BB27 to BB23 Renumber BB28 to BB24 Renumber BB29 to BB25 Renumber BB30 to BB26 Renumber BB31 to BB27 Renumber BB32 to BB28 Renumber BB33 to BB29 Renumber BB34 to BB30 Renumber BB35 to BB31 Renumber BB36 to BB32 Renumber BB37 to BB33 Renumber BB38 to BB34 Renumber BB39 to BB35 Renumber BB40 to BB36 Renumber BB41 to BB37 Renumber BB42 to BB38 Renumber BB43 to BB39 Renumber BB44 to BB40 Renumber BB45 to BB41 Renumber BB46 to BB42 Renumber BB47 to BB43 Renumber BB48 to BB44 *************** After renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0056] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..00D)-> BB04 ( cond ) i label target idxlen BB03 [0001] 1 BB02 1 [00D..017) (return) i hascall gcsafe BB04 [0002] 1 BB02 1 [017..065)-> BB06 ( cond ) i label target hascall gcsafe BB05 [0038] 1 BB04 1 [020..021)-> BB07 (always) i BB06 [0039] 1 BB04 1 [020..021) i label target BB07 [0040] 2 BB05,BB06 1 [000..000)-> BB09 ( cond ) i internal label target idxlen BB08 [0043] 1 BB07 1 [000..000)-> BB10 (always) i internal BB09 [0044] 1 BB07 1 [000..000) i internal label target BB10 [0045] 2 BB08,BB09 1 [???..???)-> BB14 ( cond ) i internal label target hascall gcsafe idxlen BB11 [0003] 1 BB10 1 [065..070)-> BB13 ( cond ) i hascall gcsafe BB12 [0004] 1 BB11 1 [070..07A) (return) i hascall gcsafe BB13 [0005] 1 BB11 1 [07A..082) i label target hascall gcsafe BB14 [0006] 2 BB10,BB13 1 [082..092)-> BB16 ( cond ) i label target hascall gcsafe BB15 [0007] 1 BB14 1 [092..096)-> BB17 ( cond ) i BB16 [0008] 2 BB14,BB15 1 [096..0A7)-> BB44 (always) i label target hascall gcsafe BB17 [0009] 1 BB15 1 [0A7..0B0)-> BB19 ( cond ) i label target BB18 [0010] 1 BB17 1 [0B0..0B4)-> BB20 (always) i BB19 [0011] 1 BB17 1 [0B4..0BE) i label target BB20 [0012] 2 BB18,BB19 1 [0BE..0C4)-> BB23 ( cond ) i label target BB21 [0013] 1 BB20 1 [0C4..0D9)-> BB23 ( cond ) i hascall gcsafe idxlen BB22 [0014] 1 BB21 1 [0D9..0E3) (return) i hascall gcsafe BB23 [0015] 2 BB20,BB21 1 [0E3..117)-> BB25 ( cond ) i label target hascall gcsafe BB24 [0016] 1 BB23 1 [117..11A)-> BB26 (always) i BB25 [0017] 1 BB23 1 [11A..11F) i label target BB26 [0018] 2 BB24,BB25 1 [11F..126)-> BB28 ( cond ) i label target BB27 [0019] 1 BB26 1 [126..12F) i hascall gcsafe BB28 [0020] 2 BB26,BB27 1 [12F..13E)-> BB32 ( cond ) i label target BB29 [0021] 1 BB28 1 [13E..144)-> BB31 ( cond ) i BB30 [0022] 1 BB29 1 [144..155)-> BB44 (always) i hascall gcsafe BB31 [0023] 1 BB29 1 [155..15C) i label target BB32 [0024] 2 BB28,BB31 1 [15C..167)-> BB34 ( cond ) i label target hascall gcsafe BB33 [0025] 1 BB32 1 [167..16B)-> BB35 (always) i BB34 [0026] 1 BB32 1 [16B..16F) i label target BB35 [0027] 2 BB33,BB34 1 [16F..1A4)-> BB40 ( cond ) i label target hascall gcsafe BB36 [0028] 1 BB35 1 [1A4..1AF)-> BB38 ( cond ) i BB37 [0029] 1 BB36 1 [1AF..1C3)-> BB39 (always) i BB38 [0030] 1 BB36 1 [1C3..1C4) i label target BB39 [0031] 2 BB37,BB38 1 [1C4..1D0) i label target BB40 [0032] 2 BB35,BB39 1 [1D0..1E7)-> BB42 ( cond ) i label target hascall gcsafe BB41 [0033] 1 BB40 1 [1E7..1EE)-> BB43 (always) i BB42 [0034] 1 BB40 1 [1EE..1F2) i label target BB43 [0035] 2 BB41,BB42 1 [1F2..202) i label target hascall gcsafe BB44 [0054] 3 BB16,BB30,BB43 1 [???..???) (return) keep internal target ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty New BlockSet epoch 3, # of blocks (including unused BB00): 45, bitset array size: 1 (short) Enter blocks: BB01 After computing reachability sets: ------------------------------------------------ BBnum Reachable by ------------------------------------------------ BB01 : BB01 BB02 : BB01 BB02 BB03 : BB01 BB02 BB03 BB04 : BB01 BB02 BB04 BB05 : BB01 BB02 BB04 BB05 BB06 : BB01 BB02 BB04 BB06 BB07 : BB01 BB02 BB04 BB05 BB06 BB07 BB08 : BB01 BB02 BB04 BB05 BB06 BB07 BB08 BB09 : BB01 BB02 BB04 BB05 BB06 BB07 BB09 BB10 : BB01 BB02 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 : BB01 BB02 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 : BB01 BB02 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 : BB01 BB02 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB13 BB14 : BB01 BB02 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB13 BB14 BB15 : BB01 BB02 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB13 BB14 BB15 BB16 : BB01 BB02 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB13 BB14 BB15 BB16 BB17 : BB01 BB02 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB13 BB14 BB15 BB17 BB18 : BB01 BB02 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB13 BB14 BB15 BB17 BB18 BB19 : BB01 BB02 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB13 BB14 BB15 BB17 BB19 BB20 : BB01 BB02 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB13 BB14 BB15 BB17 BB18 BB19 BB20 BB21 : BB01 BB02 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB13 BB14 BB15 BB17 BB18 BB19 BB20 BB21 BB22 : BB01 BB02 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB13 BB14 BB15 BB17 BB18 BB19 BB20 BB21 BB22 BB23 : BB01 BB02 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB13 BB14 BB15 BB17 BB18 BB19 BB20 BB21 BB23 BB24 : BB01 BB02 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB13 BB14 BB15 BB17 BB18 BB19 BB20 BB21 BB23 BB24 BB25 : BB01 BB02 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB13 BB14 BB15 BB17 BB18 BB19 BB20 BB21 BB23 BB25 BB26 : BB01 BB02 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB13 BB14 BB15 BB17 BB18 BB19 BB20 BB21 BB23 BB24 BB25 BB26 BB27 : BB01 BB02 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB13 BB14 BB15 BB17 BB18 BB19 BB20 BB21 BB23 BB24 BB25 BB26 BB27 BB28 : BB01 BB02 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB13 BB14 BB15 BB17 BB18 BB19 BB20 BB21 BB23 BB24 BB25 BB26 BB27 BB28 BB29 : BB01 BB02 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB13 BB14 BB15 BB17 BB18 BB19 BB20 BB21 BB23 BB24 BB25 BB26 BB27 BB28 BB29 BB30 : BB01 BB02 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB13 BB14 BB15 BB17 BB18 BB19 BB20 BB21 BB23 BB24 BB25 BB26 BB27 BB28 BB29 BB30 BB31 : BB01 BB02 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB13 BB14 BB15 BB17 BB18 BB19 BB20 BB21 BB23 BB24 BB25 BB26 BB27 BB28 BB29 BB31 BB32 : BB01 BB02 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB13 BB14 BB15 BB17 BB18 BB19 BB20 BB21 BB23 BB24 BB25 BB26 BB27 BB28 BB29 BB31 BB32 BB33 : BB01 BB02 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB13 BB14 BB15 BB17 BB18 BB19 BB20 BB21 BB23 BB24 BB25 BB26 BB27 BB28 BB29 BB31 BB32 BB33 BB34 : BB01 BB02 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB13 BB14 BB15 BB17 BB18 BB19 BB20 BB21 BB23 BB24 BB25 BB26 BB27 BB28 BB29 BB31 BB32 BB34 BB35 : BB01 BB02 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB13 BB14 BB15 BB17 BB18 BB19 BB20 BB21 BB23 BB24 BB25 BB26 BB27 BB28 BB29 BB31 BB32 BB33 BB34 BB35 BB36 : BB01 BB02 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB13 BB14 BB15 BB17 BB18 BB19 BB20 BB21 BB23 BB24 BB25 BB26 BB27 BB28 BB29 BB31 BB32 BB33 BB34 BB35 BB36 BB37 : BB01 BB02 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB13 BB14 BB15 BB17 BB18 BB19 BB20 BB21 BB23 BB24 BB25 BB26 BB27 BB28 BB29 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 : BB01 BB02 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB13 BB14 BB15 BB17 BB18 BB19 BB20 BB21 BB23 BB24 BB25 BB26 BB27 BB28 BB29 BB31 BB32 BB33 BB34 BB35 BB36 BB38 BB39 : BB01 BB02 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB13 BB14 BB15 BB17 BB18 BB19 BB20 BB21 BB23 BB24 BB25 BB26 BB27 BB28 BB29 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB39 BB40 : BB01 BB02 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB13 BB14 BB15 BB17 BB18 BB19 BB20 BB21 BB23 BB24 BB25 BB26 BB27 BB28 BB29 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB39 BB40 BB41 : BB01 BB02 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB13 BB14 BB15 BB17 BB18 BB19 BB20 BB21 BB23 BB24 BB25 BB26 BB27 BB28 BB29 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB39 BB40 BB41 BB42 : BB01 BB02 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB13 BB14 BB15 BB17 BB18 BB19 BB20 BB21 BB23 BB24 BB25 BB26 BB27 BB28 BB29 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB39 BB40 BB42 BB43 : BB01 BB02 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB13 BB14 BB15 BB17 BB18 BB19 BB20 BB21 BB23 BB24 BB25 BB26 BB27 BB28 BB29 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB39 BB40 BB41 BB42 BB43 BB44 : BB01 BB02 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB23 BB24 BB25 BB26 BB27 BB28 BB29 BB30 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB39 BB40 BB41 BB42 BB43 BB44 After computing reachability: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0056] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..00D)-> BB04 ( cond ) i label target idxlen BB03 [0001] 1 BB02 1 [00D..017) (return) i hascall gcsafe BB04 [0002] 1 BB02 1 [017..065)-> BB06 ( cond ) i label target hascall gcsafe BB05 [0038] 1 BB04 1 [020..021)-> BB07 (always) i gcsafe BB06 [0039] 1 BB04 1 [020..021) i label target gcsafe BB07 [0040] 2 BB05,BB06 1 [000..000)-> BB09 ( cond ) i internal label target gcsafe idxlen BB08 [0043] 1 BB07 1 [000..000)-> BB10 (always) i internal gcsafe BB09 [0044] 1 BB07 1 [000..000) i internal label target gcsafe BB10 [0045] 2 BB08,BB09 1 [???..???)-> BB14 ( cond ) i internal label target hascall gcsafe idxlen BB11 [0003] 1 BB10 1 [065..070)-> BB13 ( cond ) i hascall gcsafe BB12 [0004] 1 BB11 1 [070..07A) (return) i hascall gcsafe BB13 [0005] 1 BB11 1 [07A..082) i label target hascall gcsafe BB14 [0006] 2 BB10,BB13 1 [082..092)-> BB16 ( cond ) i label target hascall gcsafe BB15 [0007] 1 BB14 1 [092..096)-> BB17 ( cond ) i gcsafe BB16 [0008] 2 BB14,BB15 1 [096..0A7)-> BB44 (always) i label target hascall gcsafe BB17 [0009] 1 BB15 1 [0A7..0B0)-> BB19 ( cond ) i label target gcsafe BB18 [0010] 1 BB17 1 [0B0..0B4)-> BB20 (always) i gcsafe BB19 [0011] 1 BB17 1 [0B4..0BE) i label target gcsafe BB20 [0012] 2 BB18,BB19 1 [0BE..0C4)-> BB23 ( cond ) i label target gcsafe BB21 [0013] 1 BB20 1 [0C4..0D9)-> BB23 ( cond ) i hascall gcsafe idxlen BB22 [0014] 1 BB21 1 [0D9..0E3) (return) i hascall gcsafe BB23 [0015] 2 BB20,BB21 1 [0E3..117)-> BB25 ( cond ) i label target hascall gcsafe BB24 [0016] 1 BB23 1 [117..11A)-> BB26 (always) i gcsafe BB25 [0017] 1 BB23 1 [11A..11F) i label target gcsafe BB26 [0018] 2 BB24,BB25 1 [11F..126)-> BB28 ( cond ) i label target gcsafe BB27 [0019] 1 BB26 1 [126..12F) i hascall gcsafe BB28 [0020] 2 BB26,BB27 1 [12F..13E)-> BB32 ( cond ) i label target gcsafe BB29 [0021] 1 BB28 1 [13E..144)-> BB31 ( cond ) i gcsafe BB30 [0022] 1 BB29 1 [144..155)-> BB44 (always) i hascall gcsafe BB31 [0023] 1 BB29 1 [155..15C) i label target gcsafe BB32 [0024] 2 BB28,BB31 1 [15C..167)-> BB34 ( cond ) i label target hascall gcsafe BB33 [0025] 1 BB32 1 [167..16B)-> BB35 (always) i gcsafe BB34 [0026] 1 BB32 1 [16B..16F) i label target gcsafe BB35 [0027] 2 BB33,BB34 1 [16F..1A4)-> BB40 ( cond ) i label target hascall gcsafe BB36 [0028] 1 BB35 1 [1A4..1AF)-> BB38 ( cond ) i gcsafe BB37 [0029] 1 BB36 1 [1AF..1C3)-> BB39 (always) i gcsafe BB38 [0030] 1 BB36 1 [1C3..1C4) i label target gcsafe BB39 [0031] 2 BB37,BB38 1 [1C4..1D0) i label target gcsafe BB40 [0032] 2 BB35,BB39 1 [1D0..1E7)-> BB42 ( cond ) i label target hascall gcsafe BB41 [0033] 1 BB40 1 [1E7..1EE)-> BB43 (always) i gcsafe BB42 [0034] 1 BB40 1 [1EE..1F2) i label target gcsafe BB43 [0035] 2 BB41,BB42 1 [1F2..202) i label target hascall gcsafe BB44 [0054] 3 BB16,BB30,BB43 1 [???..???) (return) keep internal target gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgComputeDoms *************** In fgDebugCheckBBlist Dominator computation start blocks (those blocks with no incoming edges): BB01 ------------------------------------------------ BBnum Dominated by ------------------------------------------------ BB01: BB01 BB02: BB02 BB01 BB03: BB03 BB02 BB01 BB04: BB04 BB02 BB01 BB05: BB05 BB04 BB02 BB01 BB06: BB06 BB04 BB02 BB01 BB07: BB07 BB04 BB02 BB01 BB08: BB08 BB07 BB04 BB02 BB01 BB09: BB09 BB07 BB04 BB02 BB01 BB10: BB10 BB07 BB04 BB02 BB01 BB11: BB11 BB10 BB07 BB04 BB02 BB01 BB12: BB12 BB11 BB10 BB07 BB04 BB02 BB01 BB13: BB13 BB11 BB10 BB07 BB04 BB02 BB01 BB14: BB14 BB10 BB07 BB04 BB02 BB01 BB15: BB15 BB14 BB10 BB07 BB04 BB02 BB01 BB17: BB17 BB15 BB14 BB10 BB07 BB04 BB02 BB01 BB18: BB18 BB17 BB15 BB14 BB10 BB07 BB04 BB02 BB01 BB19: BB19 BB17 BB15 BB14 BB10 BB07 BB04 BB02 BB01 BB20: BB20 BB17 BB15 BB14 BB10 BB07 BB04 BB02 BB01 BB21: BB21 BB20 BB17 BB15 BB14 BB10 BB07 BB04 BB02 BB01 BB22: BB22 BB21 BB20 BB17 BB15 BB14 BB10 BB07 BB04 BB02 BB01 BB23: BB23 BB20 BB17 BB15 BB14 BB10 BB07 BB04 BB02 BB01 BB24: BB24 BB23 BB20 BB17 BB15 BB14 BB10 BB07 BB04 BB02 BB01 BB25: BB25 BB23 BB20 BB17 BB15 BB14 BB10 BB07 BB04 BB02 BB01 BB26: BB26 BB23 BB20 BB17 BB15 BB14 BB10 BB07 BB04 BB02 BB01 BB27: BB27 BB26 BB23 BB20 BB17 BB15 BB14 BB10 BB07 BB04 BB02 BB01 BB28: BB28 BB26 BB23 BB20 BB17 BB15 BB14 BB10 BB07 BB04 BB02 BB01 BB29: BB29 BB28 BB26 BB23 BB20 BB17 BB15 BB14 BB10 BB07 BB04 BB02 BB01 BB30: BB30 BB29 BB28 BB26 BB23 BB20 BB17 BB15 BB14 BB10 BB07 BB04 BB02 BB01 BB31: BB31 BB29 BB28 BB26 BB23 BB20 BB17 BB15 BB14 BB10 BB07 BB04 BB02 BB01 BB32: BB32 BB28 BB26 BB23 BB20 BB17 BB15 BB14 BB10 BB07 BB04 BB02 BB01 BB33: BB33 BB32 BB28 BB26 BB23 BB20 BB17 BB15 BB14 BB10 BB07 BB04 BB02 BB01 BB34: BB34 BB32 BB28 BB26 BB23 BB20 BB17 BB15 BB14 BB10 BB07 BB04 BB02 BB01 BB35: BB35 BB32 BB28 BB26 BB23 BB20 BB17 BB15 BB14 BB10 BB07 BB04 BB02 BB01 BB36: BB36 BB35 BB32 BB28 BB26 BB23 BB20 BB17 BB15 BB14 BB10 BB07 BB04 BB02 BB01 BB37: BB37 BB36 BB35 BB32 BB28 BB26 BB23 BB20 BB17 BB15 BB14 BB10 BB07 BB04 BB02 BB01 BB38: BB38 BB36 BB35 BB32 BB28 BB26 BB23 BB20 BB17 BB15 BB14 BB10 BB07 BB04 BB02 BB01 BB39: BB39 BB36 BB35 BB32 BB28 BB26 BB23 BB20 BB17 BB15 BB14 BB10 BB07 BB04 BB02 BB01 BB40: BB40 BB35 BB32 BB28 BB26 BB23 BB20 BB17 BB15 BB14 BB10 BB07 BB04 BB02 BB01 BB41: BB41 BB40 BB35 BB32 BB28 BB26 BB23 BB20 BB17 BB15 BB14 BB10 BB07 BB04 BB02 BB01 BB42: BB42 BB40 BB35 BB32 BB28 BB26 BB23 BB20 BB17 BB15 BB14 BB10 BB07 BB04 BB02 BB01 BB43: BB43 BB40 BB35 BB32 BB28 BB26 BB23 BB20 BB17 BB15 BB14 BB10 BB07 BB04 BB02 BB01 BB16: BB16 BB14 BB10 BB07 BB04 BB02 BB01 BB44: BB44 BB14 BB10 BB07 BB04 BB02 BB01 Inside fgBuildDomTree After computing the Dominance Tree: BB01 : BB02 BB02 : BB04 BB03 BB04 : BB07 BB06 BB05 BB07 : BB10 BB09 BB08 BB10 : BB14 BB11 BB11 : BB13 BB12 BB14 : BB44 BB16 BB15 BB15 : BB17 BB17 : BB20 BB19 BB18 BB20 : BB23 BB21 BB21 : BB22 BB23 : BB26 BB25 BB24 BB26 : BB28 BB27 BB28 : BB32 BB29 BB29 : BB31 BB30 BB32 : BB35 BB34 BB33 BB35 : BB40 BB36 BB36 : BB39 BB38 BB37 BB40 : BB43 BB42 BB41 After numbering the dominator tree: BB01: pre=01, post=44 BB02: pre=02, post=43 BB03: pre=44, post=42 BB04: pre=03, post=41 BB05: pre=43, post=40 BB06: pre=42, post=39 BB07: pre=04, post=38 BB08: pre=41, post=37 BB09: pre=40, post=36 BB10: pre=05, post=35 BB11: pre=37, post=34 BB12: pre=39, post=33 BB13: pre=38, post=32 BB14: pre=06, post=31 BB15: pre=09, post=30 BB16: pre=08, post=02 BB17: pre=10, post=29 BB18: pre=36, post=28 BB19: pre=35, post=27 BB20: pre=11, post=26 BB21: pre=33, post=25 BB22: pre=34, post=24 BB23: pre=12, post=23 BB24: pre=32, post=22 BB25: pre=31, post=21 BB26: pre=13, post=20 BB27: pre=30, post=19 BB28: pre=14, post=18 BB29: pre=27, post=17 BB30: pre=29, post=16 BB31: pre=28, post=15 BB32: pre=15, post=14 BB33: pre=26, post=13 BB34: pre=25, post=12 BB35: pre=16, post=11 BB36: pre=21, post=10 BB37: pre=24, post=09 BB38: pre=23, post=08 BB39: pre=22, post=07 BB40: pre=17, post=06 BB41: pre=20, post=05 BB42: pre=19, post=04 BB43: pre=18, post=03 BB44: pre=07, post=01 *************** Finishing PHASE Compute blocks reachability *************** Starting PHASE Optimize loops *************** In optOptimizeLoops() After optSetBlockWeights: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0056] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..00D)-> BB04 ( cond ) i label target idxlen BB03 [0001] 1 BB02 0.50 [00D..017) (return) i hascall gcsafe BB04 [0002] 1 BB02 0.50 [017..065)-> BB06 ( cond ) i label target hascall gcsafe BB05 [0038] 1 BB04 0.50 [020..021)-> BB07 (always) i gcsafe BB06 [0039] 1 BB04 0.50 [020..021) i label target gcsafe BB07 [0040] 2 BB05,BB06 0.50 [000..000)-> BB09 ( cond ) i internal label target gcsafe idxlen BB08 [0043] 1 BB07 0.50 [000..000)-> BB10 (always) i internal gcsafe BB09 [0044] 1 BB07 0.50 [000..000) i internal label target gcsafe BB10 [0045] 2 BB08,BB09 0.50 [???..???)-> BB14 ( cond ) i internal label target hascall gcsafe idxlen BB11 [0003] 1 BB10 0.50 [065..070)-> BB13 ( cond ) i hascall gcsafe BB12 [0004] 1 BB11 0.50 [070..07A) (return) i hascall gcsafe BB13 [0005] 1 BB11 0.50 [07A..082) i label target hascall gcsafe BB14 [0006] 2 BB10,BB13 0.50 [082..092)-> BB16 ( cond ) i label target hascall gcsafe BB15 [0007] 1 BB14 0.50 [092..096)-> BB17 ( cond ) i gcsafe BB16 [0008] 2 BB14,BB15 0.50 [096..0A7)-> BB44 (always) i label target hascall gcsafe BB17 [0009] 1 BB15 0.50 [0A7..0B0)-> BB19 ( cond ) i label target gcsafe BB18 [0010] 1 BB17 0.50 [0B0..0B4)-> BB20 (always) i gcsafe BB19 [0011] 1 BB17 0.50 [0B4..0BE) i label target gcsafe BB20 [0012] 2 BB18,BB19 0.50 [0BE..0C4)-> BB23 ( cond ) i label target gcsafe BB21 [0013] 1 BB20 0.50 [0C4..0D9)-> BB23 ( cond ) i hascall gcsafe idxlen BB22 [0014] 1 BB21 0.50 [0D9..0E3) (return) i hascall gcsafe BB23 [0015] 2 BB20,BB21 0.50 [0E3..117)-> BB25 ( cond ) i label target hascall gcsafe BB24 [0016] 1 BB23 0.50 [117..11A)-> BB26 (always) i gcsafe BB25 [0017] 1 BB23 0.50 [11A..11F) i label target gcsafe BB26 [0018] 2 BB24,BB25 0.50 [11F..126)-> BB28 ( cond ) i label target gcsafe BB27 [0019] 1 BB26 0.50 [126..12F) i hascall gcsafe BB28 [0020] 2 BB26,BB27 0.50 [12F..13E)-> BB32 ( cond ) i label target gcsafe BB29 [0021] 1 BB28 0.50 [13E..144)-> BB31 ( cond ) i gcsafe BB30 [0022] 1 BB29 0.50 [144..155)-> BB44 (always) i hascall gcsafe BB31 [0023] 1 BB29 0.50 [155..15C) i label target gcsafe BB32 [0024] 2 BB28,BB31 0.50 [15C..167)-> BB34 ( cond ) i label target hascall gcsafe BB33 [0025] 1 BB32 0.50 [167..16B)-> BB35 (always) i gcsafe BB34 [0026] 1 BB32 0.50 [16B..16F) i label target gcsafe BB35 [0027] 2 BB33,BB34 0.50 [16F..1A4)-> BB40 ( cond ) i label target hascall gcsafe BB36 [0028] 1 BB35 0.50 [1A4..1AF)-> BB38 ( cond ) i gcsafe BB37 [0029] 1 BB36 0.50 [1AF..1C3)-> BB39 (always) i gcsafe BB38 [0030] 1 BB36 0.50 [1C3..1C4) i label target gcsafe BB39 [0031] 2 BB37,BB38 0.50 [1C4..1D0) i label target gcsafe BB40 [0032] 2 BB35,BB39 0.50 [1D0..1E7)-> BB42 ( cond ) i label target hascall gcsafe BB41 [0033] 1 BB40 0.50 [1E7..1EE)-> BB43 (always) i gcsafe BB42 [0034] 1 BB40 0.50 [1EE..1F2) i label target gcsafe BB43 [0035] 2 BB41,BB42 0.50 [1F2..202) i label target hascall gcsafe BB44 [0054] 3 BB16,BB30,BB43 0.50 [???..???) (return) keep internal target gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Finishing PHASE Optimize loops *************** Starting PHASE Clone loops *************** In optCloneLoops() *************** Finishing PHASE Clone loops *************** Starting PHASE Unroll loops *************** Finishing PHASE Unroll loops *************** Starting PHASE Mark local vars *************** In lvaMarkLocalVars() *** lvaComputeRefCounts *** *** lvaComputeRefCounts -- explicit counts *** *** marking local variables in block BB01 (weight=1 ) STMT00111 (IL ???... ???) [000540] -A---+------ * COMMA void [000533] -A---------- +--* ASG ref [000530] D------N---- | +--* LCL_VAR ref V52 tmp22 [000532] n----------- | \--* IND ref [000531] ------------ | \--* LCL_VAR byref V00 arg0 Zero Fseq[Mantissa] [000539] -A---------- \--* ASG int [000534] D------N---- +--* LCL_VAR int V53 tmp23 [000538] n----------- \--* IND int [000537] ------------ \--* ADD byref [000535] ------------ +--* LCL_VAR byref V00 arg0 [000536] ------------ \--* CNS_INT long 8 Fseq[Exponent] New refCnts for V52: refCnt = 1, refCntWtd = 1 New refCnts for V00: refCnt = 1, refCntWtd = 2 New refCnts for V53: refCnt = 1, refCntWtd = 1 New refCnts for V00: refCnt = 2, refCntWtd = 4 *** marking local variables in block BB02 (weight=1 ) STMT00000 (IL 0x000...0x00B) [000006] ---XG+------ * JTRUE void [000005] J--XG+-N---- \--* NE int [000003] ---XG+------ +--* ARR_LENGTH int [000002] -----+------ | \--* LCL_VAR ref V52 tmp22 [000004] -----+------ \--* CNS_INT int 0 New refCnts for V52: refCnt = 2, refCntWtd = 2 *** marking local variables in block BB03 (weight=0.50) STMT00087 (IL 0x00D...0x014) [000403] -ACXG+------ * ASG long [000402] *--X-+-N---- +--* IND long [000399] -----+------ | \--* LCL_VAR byref V02 arg2 [000401] --CXG+------ \--* CALLV ind long FloatingPointType.get_Zero [000400] -----+------ this in rcx \--* LCL_VAR ref V01 arg1 New refCnts for V02: refCnt = 1, refCntWtd = 0.50 New refCnts for V01: refCnt = 1, refCntWtd = 0.50 STMT00107 (IL ???... ???) [000520] -----+------ * RETURN int [000404] -----+------ \--* CNS_INT int 1 *** marking local variables in block BB04 (weight=0.50) STMT00002 (IL ???... ???) [000013] -ACXG+------ * ASG int [000012] D----+-N---- +--* LCL_VAR int V03 loc0 [000011] --CXG+------ \--* ADD int [000409] --CXG+------ +--* CAST int <- ushort <- int [000408] --CXG+------ | \--* ADD int [000406] --CXG+------ | +--* CALLV ind int FloatingPointType.get_DenormalMantissaBits [000007] -----+------ this in rcx | | \--* LCL_VAR ref V01 arg1 [000407] -----+------ | \--* CNS_INT int 1 [000010] -----+------ \--* CNS_INT int 1 New refCnts for V03: refCnt = 1, refCntWtd = 0.50 New refCnts for V01: refCnt = 2, refCntWtd = 1 STMT00092 (IL 0x020... ???) [000424] -A--G+------ * ASG int [000423] D----+-N---- +--* LCL_VAR int V40 tmp10 [000017] -----+------ \--* LCL_VAR int V53 tmp23 New refCnts for V40: refCnt = 1, refCntWtd = 1 New refCnts for V53: refCnt = 2, refCntWtd = 1.50 STMT00089 (IL 0x020... ???) [000414] -----+------ * JTRUE void [000413] J----+-N---- \--* GE int [000411] -----+------ +--* CNS_INT int 0 [000412] -----+------ \--* LCL_VAR int V53 tmp23 New refCnts for V53: refCnt = 3, refCntWtd = 2 *** marking local variables in block BB05 (weight=0.50) STMT00091 (IL 0x020... ???) [000421] -A---+------ * ASG int [000420] D----+-N---- +--* LCL_VAR int V39 tmp9 [000419] -----+------ \--* LCL_VAR int V40 tmp10 New refCnts for V39: refCnt = 1, refCntWtd = 0.50 New refCnts for V40: refCnt = 2, refCntWtd = 2 *** marking local variables in block BB06 (weight=0.50) STMT00090 (IL 0x020... ???) [000417] -A---+------ * ASG int [000416] D----+-N---- +--* LCL_VAR int V39 tmp9 [000415] -----+------ \--* CNS_INT int 0 New refCnts for V39: refCnt = 2, refCntWtd = 1 *** marking local variables in block BB07 (weight=0.50) STMT00004 (IL ???... ???) [000021] -A---+------ * ASG int [000020] D----+-N---- +--* LCL_VAR int V31 tmp1 [000422] -----+------ \--* LCL_VAR int V39 tmp9 New refCnts for V31: refCnt = 1, refCntWtd = 1 New refCnts for V39: refCnt = 3, refCntWtd = 1.50 STMT00096 (IL ???... ???) [000443] -A-XG+------ * ASG int [000442] D----+-N---- +--* LCL_VAR int V42 tmp12 [000429] ---XG+------ \--* ARR_LENGTH int [000428] -----+------ \--* LCL_VAR ref V52 tmp22 New refCnts for V42: refCnt = 1, refCntWtd = 1 New refCnts for V52: refCnt = 3, refCntWtd = 2.50 STMT00093 (IL ???... ???) [000433] -----+------ * JTRUE void [000432] N----+-N-U-- \--* LE int [000023] -----+------ +--* LCL_VAR int V39 tmp9 [000431] -----+------ \--* LCL_VAR int V42 tmp12 New refCnts for V39: refCnt = 4, refCntWtd = 2 New refCnts for V42: refCnt = 2, refCntWtd = 2 *** marking local variables in block BB08 (weight=0.50) STMT00095 (IL ???... ???) [000440] -A---+------ * ASG int [000439] D----+-N---- +--* LCL_VAR int V41 tmp11 [000438] -----+------ \--* LCL_VAR int V42 tmp12 New refCnts for V41: refCnt = 1, refCntWtd = 0.50 New refCnts for V42: refCnt = 3, refCntWtd = 3 *** marking local variables in block BB09 (weight=0.50) STMT00094 (IL ???... ???) [000436] -A---+------ * ASG int [000435] D----+-N---- +--* LCL_VAR int V41 tmp11 [000434] -----+------ \--* LCL_VAR int V31 tmp1 New refCnts for V41: refCnt = 2, refCntWtd = 1 New refCnts for V31: refCnt = 2, refCntWtd = 2 *** marking local variables in block BB10 (weight=0.50) STMT00007 (IL ???... ???) [000031] -A---+------ * ASG int [000030] D----+-N---- +--* LCL_VAR int V04 loc1 [000441] -----+------ \--* LCL_VAR int V41 tmp11 New refCnts for V04: refCnt = 1, refCntWtd = 0.50 New refCnts for V41: refCnt = 3, refCntWtd = 1.50 STMT00008 (IL ???...0x03C) [000035] -A---+------ * ASG int [000034] D----+-N---- +--* LCL_VAR int V05 loc2 [000033] -----+------ \--* SUB int [000022] -----+------ +--* LCL_VAR int V31 tmp1 [000032] -----+------ \--* LCL_VAR int V41 tmp11 New refCnts for V05: refCnt = 1, refCntWtd = 0.50 New refCnts for V31: refCnt = 3, refCntWtd = 3 New refCnts for V41: refCnt = 4, refCntWtd = 2 STMT00009 (IL 0x03D...0x03E) [000038] -A---+------ * ASG int [000037] D----+-N---- +--* LCL_VAR int V06 loc3 [000036] -----+------ \--* CNS_INT int 0 New refCnts for V06: refCnt = 1, refCntWtd = 0.50 STMT00010 (IL 0x03F...0x040) [000041] -A---+------ * ASG int [000040] D----+-N---- +--* LCL_VAR int V07 loc4 [000039] -----+------ \--* LCL_VAR int V41 tmp11 New refCnts for V07: refCnt = 1, refCntWtd = 0.50 New refCnts for V41: refCnt = 5, refCntWtd = 2.50 STMT00011 (IL 0x042...0x044) [000044] -A---+------ * ASG int [000043] D----+-N---- +--* LCL_VAR int V08 loc5 [000042] -----+------ \--* LCL_VAR int V41 tmp11 New refCnts for V08: refCnt = 1, refCntWtd = 0.50 New refCnts for V41: refCnt = 6, refCntWtd = 3 STMT00013 (IL ???... ???) [000050] -A-XG+------ * ASG int [000049] D----+-N---- +--* LCL_VAR int V09 loc6 [000448] ---XG+------ \--* ARR_LENGTH int [000447] -----+------ \--* LCL_VAR ref V52 tmp22 New refCnts for V09: refCnt = 1, refCntWtd = 0.50 New refCnts for V52: refCnt = 4, refCntWtd = 3 STMT00014 (IL 0x04F...0x054) [000055] -A---+------ * ASG int [000054] D----+-N---- +--* LCL_VAR int V10 loc7 [000053] -----+------ \--* SUB int [000051] -----+------ +--* LCL_VAR int V09 loc6 [000052] -----+------ \--* LCL_VAR int V41 tmp11 New refCnts for V10: refCnt = 1, refCntWtd = 0.50 New refCnts for V09: refCnt = 2, refCntWtd = 1 New refCnts for V41: refCnt = 7, refCntWtd = 3.50 STMT00016 (IL ???... ???) [000059] SACXG+------ * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger [000563] -A--------L- arg0 SETUP +--* ASG long [000562] D------N---- | +--* LCL_VAR long V75 tmp45 [000064] -----+------ | \--* ADDR long [000063] ----G+-N---- | \--* LCL_VAR struct(AX)(P) V11 loc8 | \--* ref V11._bits (offs=0x00) -> V54 tmp24 | \--* int V11._sign (offs=0x08) -> V55 tmp25 [000561] -A---+----L- arg1 SETUP +--* COMMA void [000554] -A---------- | +--* COMMA void [000549] -A---------- | | +--* ASG byref [000548] D------N---- | | | +--* LCL_VAR byref V74 tmp44 [000546] -----+------ | | | \--* ADDR byref [000547] -----+-N---- | | | \--* LCL_VAR struct(AX) V73 tmp43 [000553] -A---------- | | \--* ASG ref [000551] *------N---- | | +--* IND ref [000550] ------------ | | | \--* LCL_VAR byref V74 tmp44 Zero Fseq[Mantissa] [000552] -------N---- | | \--* LCL_VAR ref V52 tmp22 [000560] -A---------- | \--* ASG int [000558] *------N---- | +--* IND int [000557] ------------ | | \--* ADD byref [000555] ------------ | | +--* LCL_VAR byref V74 tmp44 [000556] ------------ | | \--* CNS_INT long 8 Fseq[Exponent] [000559] -------N---- | \--* LCL_VAR int V53 tmp23 [000564] ------------ arg0 in rcx +--* LCL_VAR long V75 tmp45 [000566] ------------ arg1 in rdx +--* ADDR byref [000565] -------N---- | \--* LCL_VAR struct(AX) V73 tmp43 [000058] -----+------ arg3 in r9 +--* LCL_VAR int V41 tmp11 [000057] -----+------ arg2 in r8 \--* CNS_INT int 0 New refCnts for V75: refCnt = 1, refCntWtd = 1 New refCnts for V54: refCnt = 1, refCntWtd = 0.50 New refCnts for V55: refCnt = 1, refCntWtd = 0.50 New refCnts for V11: refCnt = 1, refCntWtd = 0.50 New refCnts for V74: refCnt = 1, refCntWtd = 1 New refCnts for V73: refCnt = 1, refCntWtd = 1 New refCnts for V74: refCnt = 2, refCntWtd = 2 New refCnts for V52: refCnt = 5, refCntWtd = 3.50 New refCnts for V74: refCnt = 3, refCntWtd = 3 New refCnts for V53: refCnt = 4, refCntWtd = 2.50 New refCnts for V75: refCnt = 2, refCntWtd = 2 New refCnts for V73: refCnt = 2, refCntWtd = 2 New refCnts for V41: refCnt = 8, refCntWtd = 4 STMT00017 (IL 0x061...0x063) [000068] -----+------ * JTRUE void [000067] N----+-N---- \--* EQ int [000065] -----+------ +--* LCL_VAR int V05 loc2 [000066] -----+------ \--* CNS_INT int 0 New refCnts for V05: refCnt = 2, refCntWtd = 1 *** marking local variables in block BB11 (weight=0.50) STMT00083 (IL ???... ???) [000387] --CXG+------ * JTRUE void [000386] J-CXG+-N---- \--* LE int [000381] -----+---U-- +--* CAST long <- ulong <- uint [000380] -----+------ | \--* LCL_VAR int V05 loc2 [000385] --CXG+------ \--* CAST long <- int [000383] --CXG+------ \--* CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent [000382] -----+------ this in rcx \--* LCL_VAR ref V01 arg1 New refCnts for V05: refCnt = 3, refCntWtd = 1.50 New refCnts for V01: refCnt = 3, refCntWtd = 1.50 *** marking local variables in block BB12 (weight=0.50) STMT00085 (IL 0x070...0x077) [000396] -ACXG+------ * ASG long [000395] *--X-+-N---- +--* IND long [000392] -----+------ | \--* LCL_VAR byref V02 arg2 [000394] --CXG+------ \--* CALLV ind long FloatingPointType.get_Infinity [000393] -----+------ this in rcx \--* LCL_VAR ref V01 arg1 New refCnts for V02: refCnt = 2, refCntWtd = 1 New refCnts for V01: refCnt = 4, refCntWtd = 2 STMT00108 (IL ???... ???) [000521] -----+------ * RETURN int [000397] -----+------ \--* CNS_INT int 3 *** marking local variables in block BB13 (weight=0.50) STMT00084 (IL 0x07A...0x07D) [000391] --CXG+------ * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen [000389] -----+------ arg0 in rcx +--* ADDR long [000388] ----G+-N---- | \--* LCL_VAR struct(AX)(P) V11 loc8 | \--* ref V11._bits (offs=0x00) -> V54 tmp24 | \--* int V11._sign (offs=0x08) -> V55 tmp25 [000390] -----+------ arg1 in rdx \--* LCL_VAR int V05 loc2 New refCnts for V54: refCnt = 2, refCntWtd = 1 New refCnts for V55: refCnt = 2, refCntWtd = 1 New refCnts for V11: refCnt = 2, refCntWtd = 1 New refCnts for V05: refCnt = 4, refCntWtd = 2 *** marking local variables in block BB14 (weight=0.50) STMT00019 (IL ???... ???) [000077] -ACXG+------ * ASG int [000076] D----+-N---- +--* LCL_VAR int V13 loc10 [000072] -ACXG+------ \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits [000591] -A--G+----L- arg0 SETUP +--* COMMA void [000584] -A--G------- | +--* COMMA void [000579] -A---------- | | +--* ASG byref [000578] D------N---- | | | +--* LCL_VAR byref V77 tmp47 [000576] -----+------ | | | \--* ADDR byref [000577] -----+-N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 [000583] -A--G------- | | \--* ASG ref [000581] *------N---- | | +--* IND ref [000580] ------------ | | | \--* LCL_VAR byref V77 tmp47 Zero Fseq[_bits] [000582] ----G--N---- | | \--* LCL_VAR ref (AX) V54 tmp24 [000590] -A--G------- | \--* ASG int [000588] *------N---- | +--* IND int [000587] ------------ | | \--* ADD byref [000585] ------------ | | +--* LCL_VAR byref V77 tmp47 [000586] ------------ | | \--* CNS_INT long 8 Fseq[_sign] [000589] ----G--N---- | \--* LCL_VAR int (AX) V55 tmp25 [000593] ------------ arg0 in rcx +--* ADDR byref [000592] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 [000071] -----+------ arg1 in rdx \--* LCL_VAR_ADDR long V12 loc9 New refCnts for V13: refCnt = 1, refCntWtd = 0.50 New refCnts for V77: refCnt = 1, refCntWtd = 1 New refCnts for V76: refCnt = 1, refCntWtd = 1 New refCnts for V77: refCnt = 2, refCntWtd = 2 New refCnts for V11: refCnt = 3, refCntWtd = 1.50 New refCnts for V54: refCnt = 3, refCntWtd = 1.50 New refCnts for V77: refCnt = 3, refCntWtd = 3 New refCnts for V11: refCnt = 4, refCntWtd = 2 New refCnts for V55: refCnt = 3, refCntWtd = 1.50 New refCnts for V76: refCnt = 2, refCntWtd = 2 New refCnts for V12: refCnt = 1, refCntWtd = 0.50 STMT00020 (IL 0x08D...0x090) [000081] -----+------ * JTRUE void [000080] N----+-N-U-- \--* GE int [000078] -----+------ +--* LCL_VAR int V13 loc10 [000079] -----+------ \--* LCL_VAR int V03 loc0 New refCnts for V13: refCnt = 2, refCntWtd = 1 New refCnts for V03: refCnt = 2, refCntWtd = 1 *** marking local variables in block BB15 (weight=0.50) STMT00022 (IL 0x092...0x094) [000094] -----+------ * JTRUE void [000093] J----+-N---- \--* NE int [000091] -----+------ +--* LCL_VAR int V10 loc7 [000092] -----+------ \--* CNS_INT int 0 New refCnts for V10: refCnt = 2, refCntWtd = 1 *** marking local variables in block BB16 (weight=0.50) STMT00021 (IL 0x096...0x0A6) [000600] -ACXG------- * ASG int [000599] D------N---- +--* LCL_VAR int V51 tmp21 [000089] --CXG+------ \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits [000088] -----+------ arg4 out+20 +--* LCL_VAR byref V02 arg2 [000086] N----+------ arg2 in r8 +--* NE int [000084] -----+------ | +--* LCL_VAR int V10 loc7 [000085] -----+------ | \--* CNS_INT int 0 [000082] ----G+------ arg0 in rcx +--* LCL_VAR ref (AX) V12 loc9 [000083] -----+------ arg1 in rdx +--* LCL_VAR int V13 loc10 [000087] -----+------ arg3 in r9 \--* LCL_VAR ref V01 arg1 New refCnts for V51: refCnt = 1, refCntWtd = 1 New refCnts for V02: refCnt = 3, refCntWtd = 1.50 New refCnts for V10: refCnt = 3, refCntWtd = 1.50 New refCnts for V12: refCnt = 2, refCntWtd = 1 New refCnts for V13: refCnt = 3, refCntWtd = 1.50 New refCnts for V01: refCnt = 5, refCntWtd = 2.50 *** marking local variables in block BB17 (weight=0.50) STMT00023 (IL 0x0A7...0x0AE) [000100] ----G+------ * JTRUE void [000099] J---G+-N---- \--* LT int [000097] -----+------ +--* LCL_VAR int V53 tmp23 [000098] -----+------ \--* CNS_INT int 0 New refCnts for V53: refCnt = 5, refCntWtd = 3 *** marking local variables in block BB18 (weight=0.50) STMT00081 (IL 0x0B0...0x0B2) [000378] -A---+------ * ASG int [000377] D----+-N---- +--* LCL_VAR int V32 tmp2 [000376] -----+------ \--* LCL_VAR int V10 loc7 New refCnts for V32: refCnt = 1, refCntWtd = 0.50 New refCnts for V10: refCnt = 4, refCntWtd = 2 *** marking local variables in block BB19 (weight=0.50) STMT00024 (IL 0x0B4...0x0BD) [000108] -A--G+------ * ASG int [000107] D----+-N---- +--* LCL_VAR int V32 tmp2 [000106] ----G+------ \--* SUB int [000101] -----+------ +--* LCL_VAR int V10 loc7 [000104] -----+------ \--* LCL_VAR int V53 tmp23 New refCnts for V32: refCnt = 2, refCntWtd = 1 New refCnts for V10: refCnt = 5, refCntWtd = 2.50 New refCnts for V53: refCnt = 6, refCntWtd = 3.50 *** marking local variables in block BB20 (weight=0.50) STMT00025 (IL ???...0x0BE) [000112] -A---+------ * ASG int [000111] D----+-N---- +--* LCL_VAR int V14 loc11 [000110] -----+------ \--* LCL_VAR int V32 tmp2 New refCnts for V14: refCnt = 1, refCntWtd = 0.50 New refCnts for V32: refCnt = 3, refCntWtd = 1.50 STMT00026 (IL 0x0C0...0x0C2) [000116] -----+------ * JTRUE void [000115] J----+-N---- \--* NE int [000113] -----+------ +--* LCL_VAR int V13 loc10 [000114] -----+------ \--* CNS_INT int 0 New refCnts for V13: refCnt = 4, refCntWtd = 2 *** marking local variables in block BB21 (weight=0.50) STMT00077 (IL ???... ???) [000363] -A-XG+------ * ASG long [000362] D----+-N---- +--* LCL_VAR long V38 tmp8 [000359] ---XG+------ \--* SUB long [000353] -----+---U-- +--* CAST long <- ulong <- uint [000352] -----+------ | \--* LCL_VAR int V14 loc11 [000358] ---XG+------ \--* CAST long <- int [000456] ---XG+------ \--* ARR_LENGTH int [000455] -----+------ \--* LCL_VAR ref V52 tmp22 New refCnts for V38: refCnt = 1, refCntWtd = 1 New refCnts for V14: refCnt = 2, refCntWtd = 1 New refCnts for V52: refCnt = 6, refCntWtd = 4 STMT00078 (IL ???... ???) [000368] --CXG+------ * JTRUE void [000367] J-CXG+-N---- \--* LE int [000364] -----+------ +--* LCL_VAR long V38 tmp8 [000366] --CXG+------ \--* CAST long <- int [000361] --CXG+------ \--* CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent [000360] -----+------ this in rcx \--* LCL_VAR ref V01 arg1 New refCnts for V38: refCnt = 2, refCntWtd = 2 New refCnts for V01: refCnt = 6, refCntWtd = 3 *** marking local variables in block BB22 (weight=0.50) STMT00079 (IL 0x0D9...0x0E0) [000373] -ACXG+------ * ASG long [000372] *--X-+-N---- +--* IND long [000369] -----+------ | \--* LCL_VAR byref V02 arg2 [000371] --CXG+------ \--* CALLV ind long FloatingPointType.get_Zero [000370] -----+------ this in rcx \--* LCL_VAR ref V01 arg1 New refCnts for V02: refCnt = 4, refCntWtd = 2 New refCnts for V01: refCnt = 7, refCntWtd = 3.50 STMT00110 (IL ???... ???) [000524] -----+------ * RETURN int [000374] -----+------ \--* CNS_INT int 2 *** marking local variables in block BB23 (weight=0.50) STMT00028 (IL ???... ???) [000120] SACXG+------ * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger [000623] -A--------L- arg0 SETUP +--* ASG long [000622] D------N---- | +--* LCL_VAR long V79 tmp49 [000125] -----+------ | \--* ADDR long [000124] ----G+-N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 [000621] -A---+----L- arg1 SETUP +--* COMMA void [000614] -A---------- | +--* COMMA void [000609] -A---------- | | +--* ASG byref [000608] D------N---- | | | +--* LCL_VAR byref V78 tmp48 [000606] -----+------ | | | \--* ADDR byref [000607] ----G+-N---- | | | \--* LCL_VAR struct(AX) V73 tmp43 [000613] -A---------- | | \--* ASG ref [000611] *------N---- | | +--* IND ref [000610] ------------ | | | \--* LCL_VAR byref V78 tmp48 Zero Fseq[Mantissa] [000612] -------N---- | | \--* LCL_VAR ref V52 tmp22 [000620] -A---------- | \--* ASG int [000618] *------N---- | +--* IND int [000617] ------------ | | \--* ADD byref [000615] ------------ | | +--* LCL_VAR byref V78 tmp48 [000616] ------------ | | \--* CNS_INT long 8 Fseq[Exponent] [000619] -------N---- | \--* LCL_VAR int V53 tmp23 [000624] ------------ arg0 in rcx +--* LCL_VAR long V79 tmp49 [000626] ------------ arg1 in rdx +--* ADDR byref [000625] -------N---- | \--* LCL_VAR struct(AX) V73 tmp43 [000118] -----+------ arg2 in r8 +--* LCL_VAR int V08 loc5 [000119] -----+------ arg3 in r9 \--* LCL_VAR int V09 loc6 New refCnts for V79: refCnt = 1, refCntWtd = 1 New refCnts for V56: refCnt = 1, refCntWtd = 0.50 New refCnts for V57: refCnt = 1, refCntWtd = 0.50 New refCnts for V15: refCnt = 1, refCntWtd = 0.50 New refCnts for V78: refCnt = 1, refCntWtd = 1 New refCnts for V73: refCnt = 3, refCntWtd = 3 New refCnts for V78: refCnt = 2, refCntWtd = 2 New refCnts for V52: refCnt = 7, refCntWtd = 4.50 New refCnts for V78: refCnt = 3, refCntWtd = 3 New refCnts for V53: refCnt = 7, refCntWtd = 4 New refCnts for V79: refCnt = 2, refCntWtd = 2 New refCnts for V73: refCnt = 4, refCntWtd = 4 New refCnts for V08: refCnt = 2, refCntWtd = 1 New refCnts for V09: refCnt = 3, refCntWtd = 1.50 STMT00029 (IL 0x0EF...0x0F4) [000133] H-CXG+------ * CALL help long HELPER.CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE [000131] -----+------ arg0 in rcx +--* CNS_INT long 0x7ff815262aa0 [000132] -----+------ arg1 in rdx \--* CNS_INT int 173 STMT00030 (IL ???... ???) [000649] -A-XG+------ * COMMA void [000642] -A-XG------- +--* COMMA void [000637] -A--G------- | +--* ASG byref [000636] D------N---- | | +--* LCL_VAR byref V80 tmp50 [000632] ----G+------ | | \--* ADD byref [000633] n---G+------ | | +--* IND ref [000634] I----+------ | | | \--* CNS_INT(h) long 0xd1ffab1e static Fseq[BigOne] [000635] -----+------ | | \--* CNS_INT long 8 Fseq[#FirstElem] [000641] -A-XG------- | \--* ASG ref [000638] D---G--N---- | +--* LCL_VAR ref (AX) V58 tmp28 [000640] ---X-------- | \--* IND ref [000639] ------------ | \--* LCL_VAR byref V80 tmp50 Zero Fseq[_bits] [000648] -A-XG------- \--* ASG int [000643] D---G--N---- +--* LCL_VAR int (AX) V59 tmp29 [000647] ---X-------- \--* IND int [000646] ------------ \--* ADD byref [000644] ------------ +--* LCL_VAR byref V80 tmp50 [000645] ------------ \--* CNS_INT long 8 Fseq[_sign] New refCnts for V80: refCnt = 1, refCntWtd = 1 New refCnts for V16: refCnt = 1, refCntWtd = 0.50 New refCnts for V58: refCnt = 1, refCntWtd = 0.50 New refCnts for V80: refCnt = 2, refCntWtd = 2 New refCnts for V16: refCnt = 2, refCntWtd = 1 New refCnts for V59: refCnt = 1, refCntWtd = 0.50 New refCnts for V80: refCnt = 3, refCntWtd = 3 STMT00031 (IL 0x0F6...0x106) [000141] --CXG+------ * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen [000139] -----+------ arg0 in rcx +--* ADDR long [000138] ----G+-N---- | \--* LCL_VAR struct(AX)(P) V16 loc13 | \--* ref V16._bits (offs=0x00) -> V58 tmp28 | \--* int V16._sign (offs=0x08) -> V59 tmp29 [000140] -----+------ arg1 in rdx \--* LCL_VAR int V14 loc11 New refCnts for V58: refCnt = 2, refCntWtd = 1 New refCnts for V59: refCnt = 2, refCntWtd = 1 New refCnts for V16: refCnt = 3, refCntWtd = 1.50 New refCnts for V14: refCnt = 3, refCntWtd = 1.50 STMT00099 (IL 0x0FF... ???) [000658] -A--G+------ * COMMA void [000654] -A--G------- +--* ASG ref [000652] D------N---- | +--* LCL_VAR ref V64 tmp34 [000653] ----G--N---- | \--* LCL_VAR ref (AX) V56 tmp26 [000657] -A--G------- \--* ASG int [000655] D------N---- +--* LCL_VAR int V65 tmp35 [000656] ----G--N---- \--* LCL_VAR int (AX) V57 tmp27 New refCnts for V64: refCnt = 1, refCntWtd = 0.50 New refCnts for V15: refCnt = 2, refCntWtd = 1 New refCnts for V56: refCnt = 2, refCntWtd = 1 New refCnts for V65: refCnt = 1, refCntWtd = 0.50 New refCnts for V15: refCnt = 3, refCntWtd = 1.50 New refCnts for V57: refCnt = 2, refCntWtd = 1 STMT00098 (IL 0x0FF... ???) [000468] -ACXG+------ * ASG int [000467] D----+-N---- +--* LCL_VAR int V43 tmp13 [000463] -ACXG+------ \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits [000677] -A---+----L- arg0 SETUP +--* COMMA void [000670] -A---------- | +--* COMMA void [000665] -A---------- | | +--* ASG byref [000664] D------N---- | | | +--* LCL_VAR byref V81 tmp51 [000662] -----+------ | | | \--* ADDR byref [000663] ----G+-N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 [000669] -A---------- | | \--* ASG ref [000667] *------N---- | | +--* IND ref [000666] ------------ | | | \--* LCL_VAR byref V81 tmp51 Zero Fseq[_bits] [000668] -------N---- | | \--* LCL_VAR ref V64 tmp34 [000676] -A---------- | \--* ASG int [000674] *------N---- | +--* IND int [000673] ------------ | | \--* ADD byref [000671] ------------ | | +--* LCL_VAR byref V81 tmp51 [000672] ------------ | | \--* CNS_INT long 8 Fseq[_sign] [000675] -------N---- | \--* LCL_VAR int V65 tmp35 [000679] ------------ arg0 in rcx +--* ADDR byref [000678] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 [000462] -----+------ arg1 in rdx \--* LCL_VAR_ADDR long V45 tmp15 New refCnts for V43: refCnt = 1, refCntWtd = 0.50 New refCnts for V81: refCnt = 1, refCntWtd = 1 New refCnts for V76: refCnt = 3, refCntWtd = 3 New refCnts for V81: refCnt = 2, refCntWtd = 2 New refCnts for V64: refCnt = 2, refCntWtd = 1 New refCnts for V81: refCnt = 3, refCntWtd = 3 New refCnts for V65: refCnt = 2, refCntWtd = 1 New refCnts for V76: refCnt = 4, refCntWtd = 4 New refCnts for V45: refCnt = 1, refCntWtd = 0.50 STMT00100 (IL 0x0FF... ???) [000475] -A--G+------ * ASG ref [000474] D---G+-N---- +--* LCL_VAR ref (AX) V45 tmp15 [000473] -----+------ \--* CNS_INT ref null New refCnts for V45: refCnt = 2, refCntWtd = 1 STMT00033 (IL ???... ???) [000148] -A---+------ * ASG int [000147] D----+-N---- +--* LCL_VAR int V17 loc14 [000469] -----+------ \--* LCL_VAR int V43 tmp13 New refCnts for V17: refCnt = 1, refCntWtd = 0.50 New refCnts for V43: refCnt = 2, refCntWtd = 1 STMT00103 (IL 0x108... ???) [000687] -A--G+------ * COMMA void [000683] -A--G------- +--* ASG ref [000681] D------N---- | +--* LCL_VAR ref V66 tmp36 [000682] ----G--N---- | \--* LCL_VAR ref (AX) V58 tmp28 [000686] -A--G------- \--* ASG int [000684] D------N---- +--* LCL_VAR int V67 tmp37 [000685] ----G--N---- \--* LCL_VAR int (AX) V59 tmp29 New refCnts for V66: refCnt = 1, refCntWtd = 0.50 New refCnts for V16: refCnt = 4, refCntWtd = 2 New refCnts for V58: refCnt = 3, refCntWtd = 1.50 New refCnts for V67: refCnt = 1, refCntWtd = 0.50 New refCnts for V16: refCnt = 5, refCntWtd = 2.50 New refCnts for V59: refCnt = 3, refCntWtd = 1.50 STMT00102 (IL 0x108... ???) [000486] -ACXG+------ * ASG int [000485] D----+-N---- +--* LCL_VAR int V46 tmp16 [000481] -ACXG+------ \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits [000706] -A---+----L- arg0 SETUP +--* COMMA void [000699] -A---------- | +--* COMMA void [000694] -A---------- | | +--* ASG byref [000693] D------N---- | | | +--* LCL_VAR byref V82 tmp52 [000691] -----+------ | | | \--* ADDR byref [000692] ----G+-N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 [000698] -A---------- | | \--* ASG ref [000696] *------N---- | | +--* IND ref [000695] ------------ | | | \--* LCL_VAR byref V82 tmp52 Zero Fseq[_bits] [000697] -------N---- | | \--* LCL_VAR ref V66 tmp36 [000705] -A---------- | \--* ASG int [000703] *------N---- | +--* IND int [000702] ------------ | | \--* ADD byref [000700] ------------ | | +--* LCL_VAR byref V82 tmp52 [000701] ------------ | | \--* CNS_INT long 8 Fseq[_sign] [000704] -------N---- | \--* LCL_VAR int V67 tmp37 [000708] ------------ arg0 in rcx +--* ADDR byref [000707] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 [000480] -----+------ arg1 in rdx \--* LCL_VAR_ADDR long V48 tmp18 New refCnts for V46: refCnt = 1, refCntWtd = 0.50 New refCnts for V82: refCnt = 1, refCntWtd = 1 New refCnts for V76: refCnt = 5, refCntWtd = 5 New refCnts for V82: refCnt = 2, refCntWtd = 2 New refCnts for V66: refCnt = 2, refCntWtd = 1 New refCnts for V82: refCnt = 3, refCntWtd = 3 New refCnts for V67: refCnt = 2, refCntWtd = 1 New refCnts for V76: refCnt = 6, refCntWtd = 6 New refCnts for V48: refCnt = 1, refCntWtd = 0.50 STMT00104 (IL 0x108... ???) [000493] -A--G+------ * ASG ref [000492] D---G+-N---- +--* LCL_VAR ref (AX) V48 tmp18 [000491] -----+------ \--* CNS_INT ref null New refCnts for V48: refCnt = 2, refCntWtd = 1 STMT00035 (IL ???... ???) [000155] -A---+------ * ASG int [000154] D----+-N---- +--* LCL_VAR int V18 loc15 [000487] -----+------ \--* LCL_VAR int V46 tmp16 New refCnts for V18: refCnt = 1, refCntWtd = 0.50 New refCnts for V46: refCnt = 2, refCntWtd = 1 STMT00036 (IL 0x111...0x115) [000159] -----+------ * JTRUE void [000158] N----+-N-U-- \--* GT int [000156] -----+------ +--* LCL_VAR int V46 tmp16 [000157] -----+------ \--* LCL_VAR int V43 tmp13 New refCnts for V46: refCnt = 3, refCntWtd = 1.50 New refCnts for V43: refCnt = 3, refCntWtd = 1.50 *** marking local variables in block BB24 (weight=0.50) STMT00074 (IL 0x117...0x118) [000350] -A---+------ * ASG int [000349] D----+-N---- +--* LCL_VAR int V33 tmp3 [000348] -----+------ \--* CNS_INT int 0 New refCnts for V33: refCnt = 1, refCntWtd = 0.50 *** marking local variables in block BB25 (weight=0.50) STMT00037 (IL 0x11A...0x11E) [000164] -A---+------ * ASG int [000163] D----+-N---- +--* LCL_VAR int V33 tmp3 [000162] -----+------ \--* SUB int [000160] -----+------ +--* LCL_VAR int V18 loc15 [000161] -----+------ \--* LCL_VAR int V17 loc14 New refCnts for V33: refCnt = 2, refCntWtd = 1 New refCnts for V18: refCnt = 2, refCntWtd = 1 New refCnts for V17: refCnt = 2, refCntWtd = 1 *** marking local variables in block BB26 (weight=0.50) STMT00038 (IL ???...0x11F) [000168] -A---+------ * ASG int [000167] D----+-N---- +--* LCL_VAR int V19 loc16 [000166] -----+------ \--* LCL_VAR int V33 tmp3 New refCnts for V19: refCnt = 1, refCntWtd = 0.50 New refCnts for V33: refCnt = 3, refCntWtd = 1.50 STMT00039 (IL 0x121...0x124) [000172] -----+------ * JTRUE void [000171] N----+-N---- \--* EQ int [000169] -----+------ +--* LCL_VAR int V33 tmp3 [000170] -----+------ \--* CNS_INT int 0 New refCnts for V33: refCnt = 4, refCntWtd = 2 *** marking local variables in block BB27 (weight=0.50) STMT00073 (IL 0x126...0x12A) [000347] --CXG+------ * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft [000345] -----+------ arg0 in rcx +--* ADDR long [000344] ----G+-N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 [000346] -----+------ arg1 in rdx \--* LCL_VAR int V19 loc16 New refCnts for V56: refCnt = 3, refCntWtd = 1.50 New refCnts for V57: refCnt = 3, refCntWtd = 1.50 New refCnts for V15: refCnt = 4, refCntWtd = 2 New refCnts for V19: refCnt = 2, refCntWtd = 1 *** marking local variables in block BB28 (weight=0.50) STMT00040 (IL 0x12F...0x133) [000177] -A---+------ * ASG int [000176] D----+-N---- +--* LCL_VAR int V20 loc17 [000175] -----+------ \--* SUB int [000173] -----+------ +--* LCL_VAR int V03 loc0 [000174] -----+------ \--* LCL_VAR int V13 loc10 New refCnts for V20: refCnt = 1, refCntWtd = 0.50 New refCnts for V03: refCnt = 3, refCntWtd = 1.50 New refCnts for V13: refCnt = 5, refCntWtd = 2.50 STMT00041 (IL 0x135...0x137) [000180] -A---+------ * ASG int [000179] D----+-N---- +--* LCL_VAR int V21 loc18 [000178] -----+------ \--* LCL_VAR int V20 loc17 New refCnts for V21: refCnt = 1, refCntWtd = 0.50 New refCnts for V20: refCnt = 2, refCntWtd = 1 STMT00042 (IL 0x139...0x13C) [000184] -----+------ * JTRUE void [000183] N----+-N---- \--* EQ int [000181] -----+------ +--* LCL_VAR int V13 loc10 [000182] -----+------ \--* CNS_INT int 0 New refCnts for V13: refCnt = 6, refCntWtd = 3 *** marking local variables in block BB29 (weight=0.50) STMT00070 (IL 0x13E...0x142) [000329] -----+------ * JTRUE void [000328] N----+-N-U-- \--* LE int [000326] -----+------ +--* LCL_VAR int V19 loc16 [000327] -----+------ \--* LCL_VAR int V21 loc18 New refCnts for V19: refCnt = 3, refCntWtd = 1.50 New refCnts for V21: refCnt = 2, refCntWtd = 1 *** marking local variables in block BB30 (weight=0.50) STMT00072 (IL 0x144...0x154) [000717] -ACXG------- * ASG int [000716] D------N---- +--* LCL_VAR int V51 tmp21 [000342] --CXG+------ \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits [000341] -----+------ arg4 out+20 +--* LCL_VAR byref V02 arg2 [000339] N----+------ arg2 in r8 +--* NE int [000337] -----+------ | +--* LCL_VAR int V10 loc7 [000338] -----+------ | \--* CNS_INT int 0 [000335] ----G+------ arg0 in rcx +--* LCL_VAR ref (AX) V12 loc9 [000336] -----+------ arg1 in rdx +--* LCL_VAR int V13 loc10 [000340] -----+------ arg3 in r9 \--* LCL_VAR ref V01 arg1 New refCnts for V51: refCnt = 2, refCntWtd = 2 New refCnts for V02: refCnt = 5, refCntWtd = 2.50 New refCnts for V10: refCnt = 6, refCntWtd = 3 New refCnts for V12: refCnt = 3, refCntWtd = 1.50 New refCnts for V13: refCnt = 7, refCntWtd = 3.50 New refCnts for V01: refCnt = 8, refCntWtd = 4 *** marking local variables in block BB31 (weight=0.50) STMT00071 (IL 0x155...0x15A) [000334] -A---+------ * ASG int [000333] D----+-N---- +--* LCL_VAR int V21 loc18 [000332] -----+------ \--* SUB int [000330] -----+------ +--* LCL_VAR int V21 loc18 [000331] -----+------ \--* LCL_VAR int V19 loc16 New refCnts for V21: refCnt = 3, refCntWtd = 1.50 New refCnts for V21: refCnt = 4, refCntWtd = 2 New refCnts for V19: refCnt = 4, refCntWtd = 2 *** marking local variables in block BB32 (weight=0.50) STMT00105 (IL 0x15C... ???) [000724] -A--G+------ * COMMA void [000720] -A--G------- +--* ASG ref [000718] D---G--N---- | +--* LCL_VAR ref (AX) V68 tmp38 [000719] ----G--N---- | \--* LCL_VAR ref (AX) V56 tmp26 [000723] -A--G------- \--* ASG int [000721] D---G--N---- +--* LCL_VAR int (AX) V69 tmp39 [000722] ----G--N---- \--* LCL_VAR int (AX) V57 tmp27 New refCnts for V49: refCnt = 1, refCntWtd = 1 New refCnts for V68: refCnt = 1, refCntWtd = 0.50 New refCnts for V15: refCnt = 5, refCntWtd = 2.50 New refCnts for V56: refCnt = 4, refCntWtd = 2 New refCnts for V49: refCnt = 2, refCntWtd = 2 New refCnts for V69: refCnt = 1, refCntWtd = 0.50 New refCnts for V15: refCnt = 6, refCntWtd = 3 New refCnts for V57: refCnt = 4, refCntWtd = 2 STMT00106 (IL 0x15C... ???) [000731] -A--G+------ * COMMA void [000727] -A--G------- +--* ASG ref [000725] D------N---- | +--* LCL_VAR ref V70 tmp40 [000726] ----G--N---- | \--* LCL_VAR ref (AX) V58 tmp28 [000730] -A--G------- \--* ASG int [000728] D------N---- +--* LCL_VAR int V71 tmp41 [000729] ----G--N---- \--* LCL_VAR int (AX) V59 tmp29 New refCnts for V70: refCnt = 1, refCntWtd = 0.50 New refCnts for V16: refCnt = 6, refCntWtd = 3 New refCnts for V58: refCnt = 4, refCntWtd = 2 New refCnts for V71: refCnt = 1, refCntWtd = 0.50 New refCnts for V16: refCnt = 7, refCntWtd = 3.50 New refCnts for V59: refCnt = 4, refCntWtd = 2 STMT00044 (IL ???... ???) [000195] -ACXG+------ * JTRUE void [000503] JACXG+-N---- \--* LT int [000499] -ACXG+------ +--* CALL int System.Numerics.BigInteger.CompareTo [000752] -A--------L- this SETUP | +--* ASG byref [000751] D------N---- | | +--* LCL_VAR byref V84 tmp54 [000497] -----+------ | | \--* ADDR byref [000496] ----G+-N---- | | \--* LCL_VAR struct(AX)(P) V49 tmp19 | | \--* ref V49._bits (offs=0x00) -> V68 tmp38 | | \--* int V49._sign (offs=0x08) -> V69 tmp39 [000750] -A---+----L- arg1 SETUP | +--* COMMA void [000743] -A---------- | | +--* COMMA void [000738] -A---------- | | | +--* ASG byref [000737] D------N---- | | | | +--* LCL_VAR byref V83 tmp53 [000735] -----+------ | | | | \--* ADDR byref [000736] ----G+-N---- | | | | \--* LCL_VAR struct(AX) V76 tmp46 [000742] -A---------- | | | \--* ASG ref [000740] *------N---- | | | +--* IND ref [000739] ------------ | | | | \--* LCL_VAR byref V83 tmp53 Zero Fseq[_bits] [000741] -------N---- | | | \--* LCL_VAR ref V70 tmp40 [000749] -A---------- | | \--* ASG int [000747] *------N---- | | +--* IND int [000746] ------------ | | | \--* ADD byref [000744] ------------ | | | +--* LCL_VAR byref V83 tmp53 [000745] ------------ | | | \--* CNS_INT long 8 Fseq[_sign] [000748] -------N---- | | \--* LCL_VAR int V71 tmp41 [000753] ------------ this in rcx | +--* LCL_VAR byref V84 tmp54 [000755] ------------ arg1 in rdx | \--* ADDR byref [000754] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 [000502] -----+------ \--* CNS_INT int 0 New refCnts for V84: refCnt = 1, refCntWtd = 1 New refCnts for V68: refCnt = 2, refCntWtd = 1.50 New refCnts for V69: refCnt = 2, refCntWtd = 1.50 New refCnts for V49: refCnt = 3, refCntWtd = 3 New refCnts for V83: refCnt = 1, refCntWtd = 1 New refCnts for V76: refCnt = 7, refCntWtd = 7 New refCnts for V83: refCnt = 2, refCntWtd = 2 New refCnts for V70: refCnt = 2, refCntWtd = 1 New refCnts for V83: refCnt = 3, refCntWtd = 3 New refCnts for V71: refCnt = 2, refCntWtd = 1 New refCnts for V84: refCnt = 2, refCntWtd = 2 New refCnts for V76: refCnt = 8, refCntWtd = 8 *** marking local variables in block BB33 (weight=0.50) STMT00069 (IL 0x167...0x169) [000324] -A---+------ * ASG int [000323] D----+-N---- +--* LCL_VAR int V34 tmp4 [000322] -----+------ \--* LCL_VAR int V19 loc16 New refCnts for V34: refCnt = 1, refCntWtd = 0.50 New refCnts for V19: refCnt = 5, refCntWtd = 2.50 *** marking local variables in block BB34 (weight=0.50) STMT00045 (IL 0x16B...0x16E) [000200] -A---+------ * ASG int [000199] D----+-N---- +--* LCL_VAR int V34 tmp4 [000198] -----+------ \--* ADD int [000196] -----+------ +--* LCL_VAR int V19 loc16 [000197] -----+------ \--* CNS_INT int 1 New refCnts for V34: refCnt = 2, refCntWtd = 1 New refCnts for V19: refCnt = 6, refCntWtd = 3 *** marking local variables in block BB35 (weight=0.50) STMT00046 (IL ???...0x16F) [000204] -A---+------ * ASG int [000203] D----+-N---- +--* LCL_VAR int V22 loc19 [000202] -----+------ \--* LCL_VAR int V34 tmp4 New refCnts for V22: refCnt = 1, refCntWtd = 0.50 New refCnts for V34: refCnt = 3, refCntWtd = 1.50 STMT00047 (IL 0x171...0x18A) [000208] --CXG+------ * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft [000206] -----+------ arg0 in rcx +--* ADDR long [000205] ----G+-N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 [000207] -----+------ arg1 in rdx \--* LCL_VAR int V21 loc18 New refCnts for V56: refCnt = 5, refCntWtd = 2.50 New refCnts for V57: refCnt = 5, refCntWtd = 2.50 New refCnts for V15: refCnt = 7, refCntWtd = 3.50 New refCnts for V21: refCnt = 5, refCntWtd = 2.50 STMT00048 (IL 0x17A... ???) [000213] SACXG+------ * CALL void System.Numerics.BigInteger.DivRem [000797] -A--------L- arg0 SETUP +--* ASG long [000796] D------N---- | +--* LCL_VAR long V88 tmp58 [000220] -----+------ | \--* ADDR long [000219] ----G+-N---- | \--* LCL_VAR struct(AX)(P) V35 tmp5 | \--* ref V35._bits (offs=0x00) -> V62 tmp32 | \--* int V35._sign (offs=0x08) -> V63 tmp33 [000776] -A--G+----L- arg1 SETUP +--* COMMA void [000769] -A--G------- | +--* COMMA void [000764] -A---------- | | +--* ASG byref [000763] D------N---- | | | +--* LCL_VAR byref V85 tmp55 [000761] -----+------ | | | \--* ADDR byref [000762] ----G+-N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 [000768] -A--G------- | | \--* ASG ref [000766] *------N---- | | +--* IND ref [000765] ------------ | | | \--* LCL_VAR byref V85 tmp55 Zero Fseq[_bits] [000767] ----G--N---- | | \--* LCL_VAR ref (AX) V56 tmp26 [000775] -A--G------- | \--* ASG int [000773] *------N---- | +--* IND int [000772] ------------ | | \--* ADD byref [000770] ------------ | | +--* LCL_VAR byref V85 tmp55 [000771] ------------ | | \--* CNS_INT long 8 Fseq[_sign] [000774] ----G--N---- | \--* LCL_VAR int (AX) V57 tmp27 [000795] -A--G+----L- arg2 SETUP +--* COMMA void [000788] -A--G------- | +--* COMMA void [000783] -A---------- | | +--* ASG byref [000782] D------N---- | | | +--* LCL_VAR byref V87 tmp57 [000780] -----+------ | | | \--* ADDR byref [000781] -----+-N---- | | | \--* LCL_VAR struct(AX) V86 tmp56 [000787] -A--G------- | | \--* ASG ref [000785] *------N---- | | +--* IND ref [000784] ------------ | | | \--* LCL_VAR byref V87 tmp57 Zero Fseq[_bits] [000786] ----G--N---- | | \--* LCL_VAR ref (AX) V58 tmp28 [000794] -A--G------- | \--* ASG int [000792] *------N---- | +--* IND int [000791] ------------ | | \--* ADD byref [000789] ------------ | | +--* LCL_VAR byref V87 tmp57 [000790] ------------ | | \--* CNS_INT long 8 Fseq[_sign] [000793] ----G--N---- | \--* LCL_VAR int (AX) V59 tmp29 [000798] ------------ arg0 in rcx +--* LCL_VAR long V88 tmp58 [000800] ------------ arg1 in rdx +--* ADDR byref [000799] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 [000802] ------------ arg2 in r8 +--* ADDR byref [000801] -------N---- | \--* LCL_VAR struct(AX) V86 tmp56 [000212] -----+------ arg3 in r9 \--* ADDR long [000211] ----G+-N---- \--* LCL_VAR struct(AX)(P) V23 loc20 \--* ref V23._bits (offs=0x00) -> V60 tmp30 \--* int V23._sign (offs=0x08) -> V61 tmp31 New refCnts for V88: refCnt = 1, refCntWtd = 1 New refCnts for V62: refCnt = 1, refCntWtd = 1 New refCnts for V63: refCnt = 1, refCntWtd = 1 New refCnts for V35: refCnt = 1, refCntWtd = 1 New refCnts for V85: refCnt = 1, refCntWtd = 1 New refCnts for V76: refCnt = 9, refCntWtd = 9 New refCnts for V85: refCnt = 2, refCntWtd = 2 New refCnts for V15: refCnt = 8, refCntWtd = 4 New refCnts for V56: refCnt = 6, refCntWtd = 3 New refCnts for V85: refCnt = 3, refCntWtd = 3 New refCnts for V15: refCnt = 9, refCntWtd = 4.50 New refCnts for V57: refCnt = 6, refCntWtd = 3 New refCnts for V87: refCnt = 1, refCntWtd = 1 New refCnts for V86: refCnt = 1, refCntWtd = 1 New refCnts for V87: refCnt = 2, refCntWtd = 2 New refCnts for V16: refCnt = 8, refCntWtd = 4 New refCnts for V58: refCnt = 5, refCntWtd = 2.50 New refCnts for V87: refCnt = 3, refCntWtd = 3 New refCnts for V16: refCnt = 9, refCntWtd = 4.50 New refCnts for V59: refCnt = 5, refCntWtd = 2.50 New refCnts for V88: refCnt = 2, refCntWtd = 2 New refCnts for V76: refCnt = 10, refCntWtd = 10 New refCnts for V86: refCnt = 2, refCntWtd = 2 New refCnts for V60: refCnt = 1, refCntWtd = 0.50 New refCnts for V61: refCnt = 1, refCntWtd = 0.50 New refCnts for V23: refCnt = 1, refCntWtd = 0.50 STMT00050 (IL ???... ???) [000226] -ACXG+------ * ASG long [000225] D----+-N---- +--* LCL_VAR long V24 loc21 [000218] -ACXG+------ \--* CALL long System.Numerics.BigInteger.op_Explicit [000822] -A--G+----L- arg0 SETUP +--* COMMA void [000815] -A--G------- | +--* COMMA void [000810] -A---------- | | +--* ASG byref [000809] D------N---- | | | +--* LCL_VAR byref V89 tmp59 [000807] -----+------ | | | \--* ADDR byref [000808] ----G+-N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 [000814] -A--G------- | | \--* ASG ref [000812] *------N---- | | +--* IND ref [000811] ------------ | | | \--* LCL_VAR byref V89 tmp59 Zero Fseq[_bits] [000813] ----G--N---- | | \--* LCL_VAR ref (AX) V62 tmp32 [000821] -A--G------- | \--* ASG int [000819] *------N---- | +--* IND int [000818] ------------ | | \--* ADD byref [000816] ------------ | | +--* LCL_VAR byref V89 tmp59 [000817] ------------ | | \--* CNS_INT long 8 Fseq[_sign] [000820] ----G--N---- | \--* LCL_VAR int (AX) V63 tmp33 [000824] ------------ arg0 in rcx \--* ADDR byref [000823] -------N---- \--* LCL_VAR struct(AX) V76 tmp46 New refCnts for V24: refCnt = 1, refCntWtd = 0.50 New refCnts for V89: refCnt = 1, refCntWtd = 1 New refCnts for V76: refCnt = 11, refCntWtd = 11 New refCnts for V89: refCnt = 2, refCntWtd = 2 New refCnts for V35: refCnt = 2, refCntWtd = 2 New refCnts for V62: refCnt = 2, refCntWtd = 1.50 New refCnts for V89: refCnt = 3, refCntWtd = 3 New refCnts for V35: refCnt = 3, refCntWtd = 3 New refCnts for V63: refCnt = 2, refCntWtd = 1.50 New refCnts for V76: refCnt = 12, refCntWtd = 12 STMT00052 (IL ???... ???) [000232] -A--G+------ * ASG int [000231] D----+-N---- +--* LCL_VAR int V25 loc22 [000516] ----G+------ \--* EQ int [000514] ----G+------ +--* LCL_VAR int (AX) V61 tmp31 [000515] -----+------ \--* CNS_INT int 0 New refCnts for V25: refCnt = 1, refCntWtd = 0.50 New refCnts for V23: refCnt = 2, refCntWtd = 1 New refCnts for V61: refCnt = 2, refCntWtd = 1 STMT00054 (IL ???... ???) [000237] -ACXG+------ * ASG int [000236] D----+-N---- +--* LCL_VAR int V26 loc23 [000234] --CXG+------ \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits [000233] -----+------ arg0 in rcx \--* LCL_VAR long V24 loc21 New refCnts for V26: refCnt = 1, refCntWtd = 0.50 New refCnts for V24: refCnt = 2, refCntWtd = 1 STMT00055 (IL 0x19E...0x1A2) [000241] -----+------ * JTRUE void [000240] N----+-N-U-- \--* LE int [000238] -----+------ +--* LCL_VAR int V26 loc23 [000239] -----+------ \--* LCL_VAR int V20 loc17 New refCnts for V26: refCnt = 2, refCntWtd = 1 New refCnts for V20: refCnt = 3, refCntWtd = 1.50 *** marking local variables in block BB36 (weight=0.50) STMT00063 (IL 0x1A4...0x1A9) [000286] -A---+------ * ASG int [000285] D----+-N---- +--* LCL_VAR int V29 loc26 [000284] -----+------ \--* SUB int [000282] -----+------ +--* LCL_VAR int V26 loc23 [000283] -----+------ \--* LCL_VAR int V20 loc17 New refCnts for V29: refCnt = 1, refCntWtd = 0.50 New refCnts for V26: refCnt = 3, refCntWtd = 1.50 New refCnts for V20: refCnt = 4, refCntWtd = 2 STMT00064 (IL 0x1AB...0x1AD) [000290] -----+------ * JTRUE void [000289] J----+-N---- \--* EQ int [000287] -----+------ +--* LCL_VAR int V25 loc22 [000288] -----+------ \--* CNS_INT int 0 New refCnts for V25: refCnt = 2, refCntWtd = 1 *** marking local variables in block BB37 (weight=0.50) STMT00068 (IL 0x1AF...0x1C1) [000320] -A---+------ * ASG int [000319] D----+-N---- +--* LCL_VAR int V37 tmp7 [000318] -----+------ \--* EQ int [000315] -----+------ +--* AND long [000305] -----+------ | +--* LCL_VAR long V24 loc21 [000314] -----+------ | \--* ADD long [000311] -----+------ | +--* LSH long [000307] -----+------ | | +--* CNS_INT long 1 [000310] -----+------ | | \--* AND int [000308] -----+------ | | +--* LCL_VAR int V29 loc26 [000309] -----+------ | | \--* CNS_INT int 63 [000313] -----+------ | \--* CNS_INT long -1 [000317] -----+------ \--* CNS_INT long 0 New refCnts for V37: refCnt = 1, refCntWtd = 0.50 New refCnts for V24: refCnt = 3, refCntWtd = 1.50 New refCnts for V29: refCnt = 2, refCntWtd = 1 *** marking local variables in block BB38 (weight=0.50) STMT00065 (IL 0x1C3...0x1C3) [000293] -A---+------ * ASG int [000292] D----+-N---- +--* LCL_VAR int V37 tmp7 [000291] -----+------ \--* CNS_INT int 0 New refCnts for V37: refCnt = 2, refCntWtd = 1 *** marking local variables in block BB39 (weight=0.50) STMT00066 (IL ???...0x1C4) [000297] -A---+------ * ASG int [000296] D----+-N---- +--* LCL_VAR int V25 loc22 [000826] -----+------ \--* CAST int <- bool <- int [000295] -----+------ \--* LCL_VAR int V37 tmp7 New refCnts for V25: refCnt = 3, refCntWtd = 1.50 New refCnts for V37: refCnt = 3, refCntWtd = 1.50 STMT00067 (IL 0x1C6...0x1CE) [000304] -A---+------ * ASG long [000303] D----+-N---- +--* LCL_VAR long V24 loc21 [000302] -----+------ \--* RSZ long [000298] -----+------ +--* LCL_VAR long V24 loc21 [000301] -----+------ \--* AND int [000299] -----+------ +--* LCL_VAR int V29 loc26 [000300] -----+------ \--* CNS_INT int 63 New refCnts for V24: refCnt = 4, refCntWtd = 2 New refCnts for V24: refCnt = 5, refCntWtd = 2.50 New refCnts for V29: refCnt = 3, refCntWtd = 1.50 *** marking local variables in block BB40 (weight=0.50) STMT00057 (IL ???... ???) [000254] -ACXG+------ * ASG long [000253] D----+-N---- +--* LCL_VAR long V27 loc24 [000252] -ACXG+------ \--* ADD long [000250] -ACXG+------ +--* LSH long [000243] -ACXG+------ | +--* CALL long System.Numerics.BigInteger.op_Explicit [000845] -A--G+----L- arg0 SETUP | | +--* COMMA void [000838] -A--G------- | | | +--* COMMA void [000833] -A---------- | | | | +--* ASG byref [000832] D------N---- | | | | | +--* LCL_VAR byref V90 tmp60 [000830] -----+------ | | | | | \--* ADDR byref [000831] ----G+-N---- | | | | | \--* LCL_VAR struct(AX) V76 tmp46 [000837] -A--G------- | | | | \--* ASG ref [000835] *------N---- | | | | +--* IND ref [000834] ------------ | | | | | \--* LCL_VAR byref V90 tmp60 Zero Fseq[_bits] [000836] ----G--N---- | | | | \--* LCL_VAR ref (AX) V54 tmp24 [000844] -A--G------- | | | \--* ASG int [000842] *------N---- | | | +--* IND int [000841] ------------ | | | | \--* ADD byref [000839] ------------ | | | | +--* LCL_VAR byref V90 tmp60 [000840] ------------ | | | | \--* CNS_INT long 8 Fseq[_sign] [000843] ----G--N---- | | | \--* LCL_VAR int (AX) V55 tmp25 [000847] ------------ arg0 in rcx | | \--* ADDR byref [000846] -------N---- | | \--* LCL_VAR struct(AX) V76 tmp46 [000249] -----+------ | \--* AND int [000247] -----+------ | +--* LCL_VAR int V20 loc17 [000248] -----+------ | \--* CNS_INT int 63 [000251] -----+------ \--* LCL_VAR long V24 loc21 New refCnts for V27: refCnt = 1, refCntWtd = 0.50 New refCnts for V90: refCnt = 1, refCntWtd = 1 New refCnts for V76: refCnt = 13, refCntWtd = 13 New refCnts for V90: refCnt = 2, refCntWtd = 2 New refCnts for V11: refCnt = 5, refCntWtd = 2.50 New refCnts for V54: refCnt = 4, refCntWtd = 2 New refCnts for V90: refCnt = 3, refCntWtd = 3 New refCnts for V11: refCnt = 6, refCntWtd = 3 New refCnts for V55: refCnt = 4, refCntWtd = 2 New refCnts for V76: refCnt = 14, refCntWtd = 14 New refCnts for V20: refCnt = 5, refCntWtd = 2.50 New refCnts for V24: refCnt = 6, refCntWtd = 3 STMT00058 (IL 0x1E2...0x1E5) [000258] -----+------ * JTRUE void [000257] N----+-N---- \--* NE int [000255] -----+------ +--* LCL_VAR int V13 loc10 [000256] -----+------ \--* CNS_INT int 0 New refCnts for V13: refCnt = 8, refCntWtd = 4 *** marking local variables in block BB41 (weight=0.50) STMT00062 (IL 0x1E7...0x1EC) [000280] -A---+------ * ASG int [000279] D----+-N---- +--* LCL_VAR int V36 tmp6 [000278] -----+------ \--* ADD int [000276] -----+------ +--* NEG int [000275] -----+------ | \--* LCL_VAR int V22 loc19 [000277] -----+------ \--* CNS_INT int -1 New refCnts for V36: refCnt = 1, refCntWtd = 0.50 New refCnts for V22: refCnt = 2, refCntWtd = 1 *** marking local variables in block BB42 (weight=0.50) STMT00059 (IL 0x1EE...0x1F1) [000263] -A---+------ * ASG int [000262] D----+-N---- +--* LCL_VAR int V36 tmp6 [000261] -----+------ \--* ADD int [000259] -----+------ +--* LCL_VAR int V13 loc10 [000260] -----+------ \--* CNS_INT int -2 New refCnts for V36: refCnt = 2, refCntWtd = 1 New refCnts for V13: refCnt = 9, refCntWtd = 4.50 *** marking local variables in block BB43 (weight=0.50) STMT00060 (IL ???...0x1F2) [000267] -A---+------ * ASG int [000266] D----+-N---- +--* LCL_VAR int V28 loc25 [000265] -----+------ \--* LCL_VAR int V36 tmp6 New refCnts for V28: refCnt = 1, refCntWtd = 0.50 New refCnts for V36: refCnt = 3, refCntWtd = 1.50 STMT00061 (IL 0x1F4...0x201) [000853] -ACXG------- * ASG int [000852] D------N---- +--* LCL_VAR int V51 tmp21 [000273] --CXG+------ \--* CALL nullcheck int FloatingPointType.AssembleFloatingPointValue [000272] -----+------ arg4 out+20 +--* LCL_VAR byref V02 arg2 [000268] -----+------ this in rcx +--* LCL_VAR ref V01 arg1 [000269] -----+------ arg1 in rdx +--* LCL_VAR long V27 loc24 [000270] -----+------ arg2 in r8 +--* LCL_VAR int V36 tmp6 [000271] -----+------ arg3 in r9 \--* LCL_VAR int V25 loc22 New refCnts for V51: refCnt = 3, refCntWtd = 3 New refCnts for V02: refCnt = 6, refCntWtd = 3 New refCnts for V01: refCnt = 9, refCntWtd = 4.50 New refCnts for V27: refCnt = 2, refCntWtd = 1 New refCnts for V36: refCnt = 4, refCntWtd = 2 New refCnts for V25: refCnt = 4, refCntWtd = 2 *** marking local variables in block BB44 (weight=0.50) STMT00109 (IL ???... ???) [000523] -----+------ * RETURN int [000522] -----+-N---- \--* LCL_VAR int V51 tmp21 New refCnts for V51: refCnt = 4, refCntWtd = 4 *** lvaComputeRefCounts -- implicit counts *** New refCnts for V00: refCnt = 3, refCntWtd = 6 New refCnts for V00: refCnt = 4, refCntWtd = 8 New refCnts for V01: refCnt = 10, refCntWtd = 5.50 New refCnts for V01: refCnt = 11, refCntWtd = 6.50 New refCnts for V02: refCnt = 7, refCntWtd = 4 New refCnts for V02: refCnt = 8, refCntWtd = 5 *************** In optAddCopies() *************** Finishing PHASE Mark local vars *************** Starting PHASE Optimize bools *************** In optOptimizeBools() *************** In fgDebugCheckBBlist *************** Finishing PHASE Optimize bools *************** Starting PHASE Find oper order *************** In fgFindOperOrder() *************** Finishing PHASE Find oper order *************** Starting PHASE Set block order *************** In fgSetBlockOrder() The biggest BB has 45 tree nodes *************** Finishing PHASE Set block order Trees before Build SSA representation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0056] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..00D)-> BB04 ( cond ) i label target idxlen BB03 [0001] 1 BB02 0.50 [00D..017) (return) i hascall gcsafe BB04 [0002] 1 BB02 0.50 [017..065)-> BB06 ( cond ) i label target hascall gcsafe BB05 [0038] 1 BB04 0.50 [020..021)-> BB07 (always) i gcsafe BB06 [0039] 1 BB04 0.50 [020..021) i label target gcsafe BB07 [0040] 2 BB05,BB06 0.50 [000..000)-> BB09 ( cond ) i internal label target gcsafe idxlen BB08 [0043] 1 BB07 0.50 [000..000)-> BB10 (always) i internal gcsafe BB09 [0044] 1 BB07 0.50 [000..000) i internal label target gcsafe BB10 [0045] 2 BB08,BB09 0.50 [???..???)-> BB14 ( cond ) i internal label target hascall gcsafe idxlen BB11 [0003] 1 BB10 0.50 [065..070)-> BB13 ( cond ) i hascall gcsafe BB12 [0004] 1 BB11 0.50 [070..07A) (return) i hascall gcsafe BB13 [0005] 1 BB11 0.50 [07A..082) i label target hascall gcsafe BB14 [0006] 2 BB10,BB13 0.50 [082..092)-> BB16 ( cond ) i label target hascall gcsafe BB15 [0007] 1 BB14 0.50 [092..096)-> BB17 ( cond ) i gcsafe BB16 [0008] 2 BB14,BB15 0.50 [096..0A7)-> BB44 (always) i label target hascall gcsafe BB17 [0009] 1 BB15 0.50 [0A7..0B0)-> BB19 ( cond ) i label target gcsafe BB18 [0010] 1 BB17 0.50 [0B0..0B4)-> BB20 (always) i gcsafe BB19 [0011] 1 BB17 0.50 [0B4..0BE) i label target gcsafe BB20 [0012] 2 BB18,BB19 0.50 [0BE..0C4)-> BB23 ( cond ) i label target gcsafe BB21 [0013] 1 BB20 0.50 [0C4..0D9)-> BB23 ( cond ) i hascall gcsafe idxlen BB22 [0014] 1 BB21 0.50 [0D9..0E3) (return) i hascall gcsafe BB23 [0015] 2 BB20,BB21 0.50 [0E3..117)-> BB25 ( cond ) i label target hascall gcsafe BB24 [0016] 1 BB23 0.50 [117..11A)-> BB26 (always) i gcsafe BB25 [0017] 1 BB23 0.50 [11A..11F) i label target gcsafe BB26 [0018] 2 BB24,BB25 0.50 [11F..126)-> BB28 ( cond ) i label target gcsafe BB27 [0019] 1 BB26 0.50 [126..12F) i hascall gcsafe BB28 [0020] 2 BB26,BB27 0.50 [12F..13E)-> BB32 ( cond ) i label target gcsafe BB29 [0021] 1 BB28 0.50 [13E..144)-> BB31 ( cond ) i gcsafe BB30 [0022] 1 BB29 0.50 [144..155)-> BB44 (always) i hascall gcsafe BB31 [0023] 1 BB29 0.50 [155..15C) i label target gcsafe BB32 [0024] 2 BB28,BB31 0.50 [15C..167)-> BB34 ( cond ) i label target hascall gcsafe BB33 [0025] 1 BB32 0.50 [167..16B)-> BB35 (always) i gcsafe BB34 [0026] 1 BB32 0.50 [16B..16F) i label target gcsafe BB35 [0027] 2 BB33,BB34 0.50 [16F..1A4)-> BB40 ( cond ) i label target hascall gcsafe BB36 [0028] 1 BB35 0.50 [1A4..1AF)-> BB38 ( cond ) i gcsafe BB37 [0029] 1 BB36 0.50 [1AF..1C3)-> BB39 (always) i gcsafe BB38 [0030] 1 BB36 0.50 [1C3..1C4) i label target gcsafe BB39 [0031] 2 BB37,BB38 0.50 [1C4..1D0) i label target gcsafe BB40 [0032] 2 BB35,BB39 0.50 [1D0..1E7)-> BB42 ( cond ) i label target hascall gcsafe BB41 [0033] 1 BB40 0.50 [1E7..1EE)-> BB43 (always) i gcsafe BB42 [0034] 1 BB40 0.50 [1EE..1F2) i label target gcsafe BB43 [0035] 2 BB41,BB42 0.50 [1F2..202) i label target hascall gcsafe BB44 [0054] 3 BB16,BB30,BB43 0.50 [???..???) (return) keep internal target gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} ***** BB01 STMT00111 (IL ???... ???) N011 ( 7, 7) [000540] -A---------- * COMMA void N004 ( 3, 3) [000533] -A------R--- +--* ASG ref N003 ( 1, 1) [000530] D------N---- | +--* LCL_VAR ref V52 tmp22 N002 ( 3, 2) [000532] n----------- | \--* IND ref N001 ( 1, 1) [000531] ------------ | \--* LCL_VAR byref V00 arg0 Zero Fseq[Mantissa] N010 ( 4, 4) [000539] -A------R--- \--* ASG int N009 ( 1, 1) [000534] D------N---- +--* LCL_VAR int V53 tmp23 N008 ( 4, 4) [000538] n----------- \--* IND int N007 ( 2, 2) [000537] -------N---- \--* ADD byref N005 ( 1, 1) [000535] ------------ +--* LCL_VAR byref V00 arg0 N006 ( 1, 1) [000536] ------------ \--* CNS_INT long 8 Fseq[Exponent] ------------ BB02 [000..00D) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00000 (IL 0x000...0x00B) N005 ( 7, 7) [000006] ---XG------- * JTRUE void N004 ( 5, 5) [000005] J--XG--N---- \--* NE int N002 ( 3, 3) [000003] ---XG------- +--* ARR_LENGTH int N001 ( 1, 1) [000002] ------------ | \--* LCL_VAR ref V52 tmp22 N003 ( 1, 1) [000004] ------------ \--* CNS_INT int 0 ------------ BB03 [00D..017) (return), preds={BB02} succs={} ***** BB03 STMT00087 (IL 0x00D...0x014) N006 ( 25, 13) [000403] -ACXG---R--- * ASG long N005 ( 3, 2) [000402] *--X---N---- +--* IND long N004 ( 1, 1) [000399] ------------ | \--* LCL_VAR byref V02 arg2 N003 ( 21, 10) [000401] --CXG------- \--* CALLV ind long FloatingPointType.get_Zero N002 ( 1, 1) [000400] ------------ this in rcx \--* LCL_VAR ref V01 arg1 ***** BB03 STMT00107 (IL ???... ???) N002 ( 2, 2) [000520] ------------ * RETURN int N001 ( 1, 1) [000404] ------------ \--* CNS_INT int 1 ------------ BB04 [017..065) -> BB06 (cond), preds={BB02} succs={BB05,BB06} ***** BB04 STMT00002 (IL ???... ???) N010 ( 30, 19) [000013] -ACXG---R--- * ASG int N009 ( 3, 2) [000012] D------N---- +--* LCL_VAR int V03 loc0 N008 ( 26, 16) [000011] --CXG------- \--* ADD int N006 ( 24, 14) [000409] --CXG------- +--* CAST int <- ushort <- int N005 ( 23, 12) [000408] --CXG------- | \--* ADD int N003 ( 21, 10) [000406] --CXG------- | +--* CALLV ind int FloatingPointType.get_DenormalMantissaBits N002 ( 1, 1) [000007] ------------ this in rcx | | \--* LCL_VAR ref V01 arg1 N004 ( 1, 1) [000407] ------------ | \--* CNS_INT int 1 N007 ( 1, 1) [000010] ------------ \--* CNS_INT int 1 ***** BB04 STMT00092 (IL 0x020... ???) N003 ( 5, 4) [000424] -A--G---R--- * ASG int N002 ( 3, 2) [000423] D------N---- +--* LCL_VAR int V40 tmp10 N001 ( 1, 1) [000017] ------------ \--* LCL_VAR int V53 tmp23 ***** BB04 STMT00089 (IL 0x020... ???) N004 ( 5, 5) [000414] ------------ * JTRUE void N003 ( 3, 3) [000413] J------N---- \--* LE int N001 ( 1, 1) [000412] ------------ +--* LCL_VAR int V53 tmp23 N002 ( 1, 1) [000411] ------------ \--* CNS_INT int 0 ------------ BB05 [020..021) -> BB07 (always), preds={BB04} succs={BB07} ***** BB05 STMT00091 (IL 0x020... ???) N003 ( 7, 5) [000421] -A------R--- * ASG int N002 ( 3, 2) [000420] D------N---- +--* LCL_VAR int V39 tmp9 N001 ( 3, 2) [000419] ------------ \--* LCL_VAR int V40 tmp10 ------------ BB06 [020..021), preds={BB04} succs={BB07} ***** BB06 STMT00090 (IL 0x020... ???) N003 ( 5, 4) [000417] -A------R--- * ASG int N002 ( 3, 2) [000416] D------N---- +--* LCL_VAR int V39 tmp9 N001 ( 1, 1) [000415] ------------ \--* CNS_INT int 0 ------------ BB07 [000..000) -> BB09 (cond), preds={BB05,BB06} succs={BB08,BB09} ***** BB07 STMT00004 (IL ???... ???) N003 ( 3, 3) [000021] -A------R--- * ASG int N002 ( 1, 1) [000020] D------N---- +--* LCL_VAR int V31 tmp1 N001 ( 3, 2) [000422] ------------ \--* LCL_VAR int V39 tmp9 ***** BB07 STMT00096 (IL ???... ???) N004 ( 3, 3) [000443] -A-XG---R--- * ASG int N003 ( 1, 1) [000442] D------N---- +--* LCL_VAR int V42 tmp12 N002 ( 3, 3) [000429] ---XG------- \--* ARR_LENGTH int N001 ( 1, 1) [000428] ------------ \--* LCL_VAR ref V52 tmp22 ***** BB07 STMT00093 (IL ???... ???) N004 ( 7, 6) [000433] ------------ * JTRUE void N003 ( 5, 4) [000432] N------N-U-- \--* LE int N001 ( 3, 2) [000023] ------------ +--* LCL_VAR int V39 tmp9 N002 ( 1, 1) [000431] ------------ \--* LCL_VAR int V42 tmp12 ------------ BB08 [000..000) -> BB10 (always), preds={BB07} succs={BB10} ***** BB08 STMT00095 (IL ???... ???) N003 ( 1, 3) [000440] -A------R--- * ASG int N002 ( 1, 1) [000439] D------N---- +--* LCL_VAR int V41 tmp11 N001 ( 1, 1) [000438] ------------ \--* LCL_VAR int V42 tmp12 ------------ BB09 [000..000), preds={BB07} succs={BB10} ***** BB09 STMT00094 (IL ???... ???) N003 ( 1, 3) [000436] -A------R--- * ASG int N002 ( 1, 1) [000435] D------N---- +--* LCL_VAR int V41 tmp11 N001 ( 1, 1) [000434] ------------ \--* LCL_VAR int V31 tmp1 ------------ BB10 [???..???) -> BB14 (cond), preds={BB08,BB09} succs={BB11,BB14} ***** BB10 STMT00007 (IL ???... ???) N003 ( 5, 4) [000031] -A------R--- * ASG int N002 ( 3, 2) [000030] D------N---- +--* LCL_VAR int V04 loc1 N001 ( 1, 1) [000441] ------------ \--* LCL_VAR int V41 tmp11 ***** BB10 STMT00008 (IL ???...0x03C) N005 ( 7, 6) [000035] -A------R--- * ASG int N004 ( 3, 2) [000034] D------N---- +--* LCL_VAR int V05 loc2 N003 ( 3, 3) [000033] ------------ \--* SUB int N001 ( 1, 1) [000022] ------------ +--* LCL_VAR int V31 tmp1 N002 ( 1, 1) [000032] ------------ \--* LCL_VAR int V41 tmp11 ***** BB10 STMT00009 (IL 0x03D...0x03E) N003 ( 5, 4) [000038] -A------R--- * ASG int N002 ( 3, 2) [000037] D------N---- +--* LCL_VAR int V06 loc3 N001 ( 1, 1) [000036] ------------ \--* CNS_INT int 0 ***** BB10 STMT00010 (IL 0x03F...0x040) N003 ( 5, 4) [000041] -A------R--- * ASG int N002 ( 3, 2) [000040] D------N---- +--* LCL_VAR int V07 loc4 N001 ( 1, 1) [000039] ------------ \--* LCL_VAR int V41 tmp11 ***** BB10 STMT00011 (IL 0x042...0x044) N003 ( 5, 4) [000044] -A------R--- * ASG int N002 ( 3, 2) [000043] D------N---- +--* LCL_VAR int V08 loc5 N001 ( 1, 1) [000042] ------------ \--* LCL_VAR int V41 tmp11 ***** BB10 STMT00013 (IL ???... ???) N004 ( 7, 6) [000050] -A-XG---R--- * ASG int N003 ( 3, 2) [000049] D------N---- +--* LCL_VAR int V09 loc6 N002 ( 3, 3) [000448] ---XG------- \--* ARR_LENGTH int N001 ( 1, 1) [000447] ------------ \--* LCL_VAR ref V52 tmp22 ***** BB10 STMT00014 (IL 0x04F...0x054) N005 ( 5, 4) [000055] -A------R--- * ASG int N004 ( 1, 1) [000054] D------N---- +--* LCL_VAR int V10 loc7 N003 ( 5, 4) [000053] ------------ \--* SUB int N001 ( 3, 2) [000051] ------------ +--* LCL_VAR int V09 loc6 N002 ( 1, 1) [000052] ------------ \--* LCL_VAR int V41 tmp11 ***** BB10 STMT00016 (IL ???... ???) N028 ( 49, 35) [000059] SACXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger N004 ( 7, 6) [000563] -A------R-L- arg0 SETUP +--* ASG long N003 ( 3, 2) [000562] D------N---- | +--* LCL_VAR long V75 tmp45 N002 ( 3, 3) [000064] ------------ | \--* ADDR long N001 ( 3, 2) [000063] ----G--N---- | \--* LCL_VAR struct(AX)(P) V11 loc8 | \--* ref V11._bits (offs=0x00) -> V54 tmp24 | \--* int V11._sign (offs=0x08) -> V55 tmp25 N020 ( 14, 13) [000561] -A--------L- arg1 SETUP +--* COMMA void N013 ( 8, 7) [000554] -A---------- | +--* COMMA void N008 ( 3, 3) [000549] -A------R--- | | +--* ASG byref N007 ( 1, 1) [000548] D------N---- | | | +--* LCL_VAR byref V74 tmp44 N006 ( 3, 3) [000546] ------------ | | | \--* ADDR byref N005 ( 3, 2) [000547] -------N---- | | | \--* LCL_VAR struct(AX) V73 tmp43 N012 ( 5, 4) [000553] -A---------- | | \--* ASG ref N010 ( 3, 2) [000551] *------N---- | | +--* IND ref N009 ( 1, 1) [000550] ------------ | | | \--* LCL_VAR byref V74 tmp44 Zero Fseq[Mantissa] N011 ( 1, 1) [000552] -------N---- | | \--* LCL_VAR ref V52 tmp22 N019 ( 6, 6) [000560] -A---------- | \--* ASG int N017 ( 4, 4) [000558] *------N---- | +--* IND int N016 ( 2, 2) [000557] -------N---- | | \--* ADD byref N014 ( 1, 1) [000555] ------------ | | +--* LCL_VAR byref V74 tmp44 N015 ( 1, 1) [000556] ------------ | | \--* CNS_INT long 8 Fseq[Exponent] N018 ( 1, 1) [000559] -------N---- | \--* LCL_VAR int V53 tmp23 N023 ( 3, 2) [000564] ------------ arg0 in rcx +--* LCL_VAR long V75 tmp45 N025 ( 3, 3) [000566] ------------ arg1 in rdx +--* ADDR byref N024 ( 3, 2) [000565] -------N---- | \--* LCL_VAR struct(AX) V73 tmp43 N026 ( 1, 1) [000058] ------------ arg3 in r9 +--* LCL_VAR int V41 tmp11 N027 ( 1, 1) [000057] ------------ arg2 in r8 \--* CNS_INT int 0 ***** BB10 STMT00017 (IL 0x061...0x063) N004 ( 7, 6) [000068] ------------ * JTRUE void N003 ( 5, 4) [000067] N------N---- \--* EQ int N001 ( 3, 2) [000065] ------------ +--* LCL_VAR int V05 loc2 N002 ( 1, 1) [000066] ------------ \--* CNS_INT int 0 ------------ BB11 [065..070) -> BB13 (cond), preds={BB10} succs={BB12,BB13} ***** BB11 STMT00083 (IL ???... ???) N008 ( 23, 17) [000387] --CXG------- * JTRUE void N007 ( 21, 15) [000386] J-CXG--N---- \--* GE int N004 ( 16, 10) [000385] --CXG------- +--* CAST long <- int N003 ( 15, 8) [000383] --CXG------- | \--* CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent N002 ( 1, 1) [000382] ------------ this in rcx | \--* LCL_VAR ref V01 arg1 N006 ( 4, 4) [000381] ---------U-- \--* CAST long <- ulong <- uint N005 ( 3, 2) [000380] ------------ \--* LCL_VAR int V05 loc2 ------------ BB12 [070..07A) (return), preds={BB11} succs={} ***** BB12 STMT00085 (IL 0x070...0x077) N006 ( 25, 13) [000396] -ACXG---R--- * ASG long N005 ( 3, 2) [000395] *--X---N---- +--* IND long N004 ( 1, 1) [000392] ------------ | \--* LCL_VAR byref V02 arg2 N003 ( 21, 10) [000394] --CXG------- \--* CALLV ind long FloatingPointType.get_Infinity N002 ( 1, 1) [000393] ------------ this in rcx \--* LCL_VAR ref V01 arg1 ***** BB12 STMT00108 (IL ???... ???) N002 ( 2, 2) [000521] ------------ * RETURN int N001 ( 1, 1) [000397] ------------ \--* CNS_INT int 3 ------------ BB13 [07A..082), preds={BB11} succs={BB14} ***** BB13 STMT00084 (IL 0x07A...0x07D) N006 ( 20, 12) [000391] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen N004 ( 3, 3) [000389] ------------ arg0 in rcx +--* ADDR long N003 ( 3, 2) [000388] ----G--N---- | \--* LCL_VAR struct(AX)(P) V11 loc8 | \--* ref V11._bits (offs=0x00) -> V54 tmp24 | \--* int V11._sign (offs=0x08) -> V55 tmp25 N005 ( 3, 2) [000390] ------------ arg1 in rdx \--* LCL_VAR int V05 loc2 ------------ BB14 [082..092) -> BB16 (cond), preds={BB10,BB13} succs={BB15,BB16} ***** BB14 STMT00019 (IL ???... ???) N023 ( 41, 28) [000077] -ACXG---R--- * ASG int N022 ( 1, 1) [000076] D------N---- +--* LCL_VAR int V13 loc10 N021 ( 41, 28) [000072] -ACXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits N016 ( 18, 15) [000591] -A--G-----L- arg0 SETUP +--* COMMA void N009 ( 10, 8) [000584] -A--G------- | +--* COMMA void N004 ( 3, 3) [000579] -A------R--- | | +--* ASG byref N003 ( 1, 1) [000578] D------N---- | | | +--* LCL_VAR byref V77 tmp47 N002 ( 3, 3) [000576] ------------ | | | \--* ADDR byref N001 ( 3, 2) [000577] -------N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 N008 ( 7, 5) [000583] -A--G------- | | \--* ASG ref N006 ( 3, 2) [000581] *------N---- | | +--* IND ref N005 ( 1, 1) [000580] ------------ | | | \--* LCL_VAR byref V77 tmp47 Zero Fseq[_bits] N007 ( 3, 2) [000582] ----G--N---- | | \--* LCL_VAR ref (AX) V54 tmp24 N015 ( 8, 7) [000590] -A--G------- | \--* ASG int N013 ( 4, 4) [000588] *------N---- | +--* IND int N012 ( 2, 2) [000587] -------N---- | | \--* ADD byref N010 ( 1, 1) [000585] ------------ | | +--* LCL_VAR byref V77 tmp47 N011 ( 1, 1) [000586] ------------ | | \--* CNS_INT long 8 Fseq[_sign] N014 ( 3, 2) [000589] ----G--N---- | \--* LCL_VAR int (AX) V55 tmp25 N019 ( 3, 3) [000593] ------------ arg0 in rcx +--* ADDR byref N018 ( 3, 2) [000592] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 N020 ( 3, 3) [000071] ------------ arg1 in rdx \--* LCL_VAR_ADDR long V12 loc9 ***** BB14 STMT00020 (IL 0x08D...0x090) N004 ( 7, 6) [000081] ------------ * JTRUE void N003 ( 5, 4) [000080] N------N-U-- \--* GE int N001 ( 1, 1) [000078] ------------ +--* LCL_VAR int V13 loc10 N002 ( 3, 2) [000079] ------------ \--* LCL_VAR int V03 loc0 ------------ BB15 [092..096) -> BB17 (cond), preds={BB14} succs={BB16,BB17} ***** BB15 STMT00022 (IL 0x092...0x094) N004 ( 5, 5) [000094] ------------ * JTRUE void N003 ( 3, 3) [000093] J------N---- \--* NE int N001 ( 1, 1) [000091] ------------ +--* LCL_VAR int V10 loc7 N002 ( 1, 1) [000092] ------------ \--* CNS_INT int 0 ------------ BB16 [096..0A7) -> BB44 (always), preds={BB14,BB15} succs={BB44} ***** BB16 STMT00021 (IL 0x096...0x0A6) N014 ( 29, 17) [000600] -ACXG---R--- * ASG int N013 ( 1, 1) [000599] D------N---- +--* LCL_VAR int V51 tmp21 N012 ( 29, 17) [000089] --CXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits N005 ( 1, 1) [000088] ------------ arg4 out+20 +--* LCL_VAR byref V02 arg2 N008 ( 6, 3) [000086] N----------- arg2 in r8 +--* NE int N006 ( 1, 1) [000084] ------------ | +--* LCL_VAR int V10 loc7 N007 ( 1, 1) [000085] ------------ | \--* CNS_INT int 0 N009 ( 3, 2) [000082] ----G------- arg0 in rcx +--* LCL_VAR ref (AX) V12 loc9 N010 ( 1, 1) [000083] ------------ arg1 in rdx +--* LCL_VAR int V13 loc10 N011 ( 1, 1) [000087] ------------ arg3 in r9 \--* LCL_VAR ref V01 arg1 ------------ BB17 [0A7..0B0) -> BB19 (cond), preds={BB15} succs={BB18,BB19} ***** BB17 STMT00023 (IL 0x0A7...0x0AE) N004 ( 5, 5) [000100] ----G------- * JTRUE void N003 ( 3, 3) [000099] J---G--N---- \--* LT int N001 ( 1, 1) [000097] ------------ +--* LCL_VAR int V53 tmp23 N002 ( 1, 1) [000098] ------------ \--* CNS_INT int 0 ------------ BB18 [0B0..0B4) -> BB20 (always), preds={BB17} succs={BB20} ***** BB18 STMT00081 (IL 0x0B0...0x0B2) N003 ( 5, 4) [000378] -A------R--- * ASG int N002 ( 3, 2) [000377] D------N---- +--* LCL_VAR int V32 tmp2 N001 ( 1, 1) [000376] ------------ \--* LCL_VAR int V10 loc7 ------------ BB19 [0B4..0BE), preds={BB17} succs={BB20} ***** BB19 STMT00024 (IL 0x0B4...0x0BD) N005 ( 7, 6) [000108] -A--G---R--- * ASG int N004 ( 3, 2) [000107] D------N---- +--* LCL_VAR int V32 tmp2 N003 ( 3, 3) [000106] ----G------- \--* SUB int N001 ( 1, 1) [000101] ------------ +--* LCL_VAR int V10 loc7 N002 ( 1, 1) [000104] ------------ \--* LCL_VAR int V53 tmp23 ------------ BB20 [0BE..0C4) -> BB23 (cond), preds={BB18,BB19} succs={BB21,BB23} ***** BB20 STMT00025 (IL ???...0x0BE) N003 ( 7, 5) [000112] -A------R--- * ASG int N002 ( 3, 2) [000111] D------N---- +--* LCL_VAR int V14 loc11 N001 ( 3, 2) [000110] ------------ \--* LCL_VAR int V32 tmp2 ***** BB20 STMT00026 (IL 0x0C0...0x0C2) N004 ( 5, 5) [000116] ------------ * JTRUE void N003 ( 3, 3) [000115] J------N---- \--* NE int N001 ( 1, 1) [000113] ------------ +--* LCL_VAR int V13 loc10 N002 ( 1, 1) [000114] ------------ \--* CNS_INT int 0 ------------ BB21 [0C4..0D9) -> BB23 (cond), preds={BB20} succs={BB22,BB23} ***** BB21 STMT00077 (IL ???... ???) N008 ( 13, 13) [000363] -A-XG---R--- * ASG long N007 ( 3, 2) [000362] D------N---- +--* LCL_VAR long V38 tmp8 N006 ( 9, 10) [000359] ---XG---R--- \--* SUB long N005 ( 4, 4) [000353] ---------U-- +--* CAST long <- ulong <- uint N004 ( 3, 2) [000352] ------------ | \--* LCL_VAR int V14 loc11 N003 ( 4, 5) [000358] ---XG------- \--* CAST long <- int N002 ( 3, 3) [000456] ---XG------- \--* ARR_LENGTH int N001 ( 1, 1) [000455] ------------ \--* LCL_VAR ref V52 tmp22 ***** BB21 STMT00078 (IL ???... ???) N007 ( 22, 15) [000368] --CXG------- * JTRUE void N006 ( 20, 13) [000367] J-CXG--N---- \--* GE int N004 ( 16, 10) [000366] --CXG------- +--* CAST long <- int N003 ( 15, 8) [000361] --CXG------- | \--* CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent N002 ( 1, 1) [000360] ------------ this in rcx | \--* LCL_VAR ref V01 arg1 N005 ( 3, 2) [000364] ------------ \--* LCL_VAR long V38 tmp8 ------------ BB22 [0D9..0E3) (return), preds={BB21} succs={} ***** BB22 STMT00079 (IL 0x0D9...0x0E0) N006 ( 25, 13) [000373] -ACXG---R--- * ASG long N005 ( 3, 2) [000372] *--X---N---- +--* IND long N004 ( 1, 1) [000369] ------------ | \--* LCL_VAR byref V02 arg2 N003 ( 21, 10) [000371] --CXG------- \--* CALLV ind long FloatingPointType.get_Zero N002 ( 1, 1) [000370] ------------ this in rcx \--* LCL_VAR ref V01 arg1 ***** BB22 STMT00110 (IL ???... ???) N002 ( 2, 2) [000524] ------------ * RETURN int N001 ( 1, 1) [000374] ------------ \--* CNS_INT int 2 ------------ BB23 [0E3..117) -> BB25 (cond), preds={BB20,BB21} succs={BB24,BB25} ***** BB23 STMT00028 (IL ???... ???) N028 ( 53, 37) [000120] SACXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger N004 ( 7, 6) [000623] -A------R-L- arg0 SETUP +--* ASG long N003 ( 3, 2) [000622] D------N---- | +--* LCL_VAR long V79 tmp49 N002 ( 3, 3) [000125] ------------ | \--* ADDR long N001 ( 3, 2) [000124] ----G--N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 N020 ( 14, 13) [000621] -A--------L- arg1 SETUP +--* COMMA void N013 ( 8, 7) [000614] -A---------- | +--* COMMA void N008 ( 3, 3) [000609] -A------R--- | | +--* ASG byref N007 ( 1, 1) [000608] D------N---- | | | +--* LCL_VAR byref V78 tmp48 N006 ( 3, 3) [000606] ------------ | | | \--* ADDR byref N005 ( 3, 2) [000607] ----G--N---- | | | \--* LCL_VAR struct(AX) V73 tmp43 N012 ( 5, 4) [000613] -A---------- | | \--* ASG ref N010 ( 3, 2) [000611] *------N---- | | +--* IND ref N009 ( 1, 1) [000610] ------------ | | | \--* LCL_VAR byref V78 tmp48 Zero Fseq[Mantissa] N011 ( 1, 1) [000612] -------N---- | | \--* LCL_VAR ref V52 tmp22 N019 ( 6, 6) [000620] -A---------- | \--* ASG int N017 ( 4, 4) [000618] *------N---- | +--* IND int N016 ( 2, 2) [000617] -------N---- | | \--* ADD byref N014 ( 1, 1) [000615] ------------ | | +--* LCL_VAR byref V78 tmp48 N015 ( 1, 1) [000616] ------------ | | \--* CNS_INT long 8 Fseq[Exponent] N018 ( 1, 1) [000619] -------N---- | \--* LCL_VAR int V53 tmp23 N023 ( 3, 2) [000624] ------------ arg0 in rcx +--* LCL_VAR long V79 tmp49 N025 ( 3, 3) [000626] ------------ arg1 in rdx +--* ADDR byref N024 ( 3, 2) [000625] -------N---- | \--* LCL_VAR struct(AX) V73 tmp43 N026 ( 3, 2) [000118] ------------ arg2 in r8 +--* LCL_VAR int V08 loc5 N027 ( 3, 2) [000119] ------------ arg3 in r9 \--* LCL_VAR int V09 loc6 ***** BB23 STMT00029 (IL 0x0EF...0x0F4) N005 ( 17, 21) [000133] H-CXG------- * CALL help long HELPER.CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE N003 ( 2, 10) [000131] ------------ arg0 in rcx +--* CNS_INT long 0x7ff815262aa0 N004 ( 1, 4) [000132] ------------ arg1 in rdx \--* CNS_INT int 173 ***** BB23 STMT00030 (IL ???... ???) N018 ( 21, 26) [000649] -A-XG------- * COMMA void N011 ( 13, 19) [000642] -A-XG------- +--* COMMA void N006 ( 6, 14) [000637] -A--G---R--- | +--* ASG byref N005 ( 1, 1) [000636] D------N---- | | +--* LCL_VAR byref V80 tmp50 N004 ( 6, 14) [000632] ----G------- | | \--* ADD byref N002 ( 4, 12) [000633] n---G------- | | +--* IND ref N001 ( 2, 10) [000634] I----------- | | | \--* CNS_INT(h) long 0xd1ffab1e static Fseq[BigOne] N003 ( 1, 1) [000635] ------------ | | \--* CNS_INT long 8 Fseq[#FirstElem] N010 ( 7, 5) [000641] -A-XG---R--- | \--* ASG ref N009 ( 3, 2) [000638] D---G--N---- | +--* LCL_VAR ref (AX) V58 tmp28 N008 ( 3, 2) [000640] ---X-------- | \--* IND ref N007 ( 1, 1) [000639] ------------ | \--* LCL_VAR byref V80 tmp50 Zero Fseq[_bits] N017 ( 8, 7) [000648] -A-XG---R--- \--* ASG int N016 ( 3, 2) [000643] D---G--N---- +--* LCL_VAR int (AX) V59 tmp29 N015 ( 4, 4) [000647] ---X-------- \--* IND int N014 ( 2, 2) [000646] -------N---- \--* ADD byref N012 ( 1, 1) [000644] ------------ +--* LCL_VAR byref V80 tmp50 N013 ( 1, 1) [000645] ------------ \--* CNS_INT long 8 Fseq[_sign] ***** BB23 STMT00031 (IL 0x0F6...0x106) N006 ( 20, 12) [000141] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen N004 ( 3, 3) [000139] ------------ arg0 in rcx +--* ADDR long N003 ( 3, 2) [000138] ----G--N---- | \--* LCL_VAR struct(AX)(P) V16 loc13 | \--* ref V16._bits (offs=0x00) -> V58 tmp28 | \--* int V16._sign (offs=0x08) -> V59 tmp29 N005 ( 3, 2) [000140] ------------ arg1 in rdx \--* LCL_VAR int V14 loc11 ***** BB23 STMT00099 (IL 0x0FF... ???) N007 ( 14, 10) [000658] -A--G------- * COMMA void N003 ( 7, 5) [000654] -A--G---R--- +--* ASG ref N002 ( 3, 2) [000652] D------N---- | +--* LCL_VAR ref V64 tmp34 N001 ( 3, 2) [000653] ----G--N---- | \--* LCL_VAR ref (AX) V56 tmp26 N006 ( 7, 5) [000657] -A--G---R--- \--* ASG int N005 ( 3, 2) [000655] D------N---- +--* LCL_VAR int V65 tmp35 N004 ( 3, 2) [000656] ----G--N---- \--* LCL_VAR int (AX) V57 tmp27 ***** BB23 STMT00098 (IL 0x0FF... ???) N023 ( 45, 31) [000468] -ACXG---R--- * ASG int N022 ( 3, 2) [000467] D------N---- +--* LCL_VAR int V43 tmp13 N021 ( 41, 28) [000463] -ACXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits N016 ( 18, 15) [000677] -A--------L- arg0 SETUP +--* COMMA void N009 ( 10, 8) [000670] -A---------- | +--* COMMA void N004 ( 3, 3) [000665] -A------R--- | | +--* ASG byref N003 ( 1, 1) [000664] D------N---- | | | +--* LCL_VAR byref V81 tmp51 N002 ( 3, 3) [000662] ------------ | | | \--* ADDR byref N001 ( 3, 2) [000663] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 N008 ( 7, 5) [000669] -A---------- | | \--* ASG ref N006 ( 3, 2) [000667] *------N---- | | +--* IND ref N005 ( 1, 1) [000666] ------------ | | | \--* LCL_VAR byref V81 tmp51 Zero Fseq[_bits] N007 ( 3, 2) [000668] -------N---- | | \--* LCL_VAR ref V64 tmp34 N015 ( 8, 7) [000676] -A---------- | \--* ASG int N013 ( 4, 4) [000674] *------N---- | +--* IND int N012 ( 2, 2) [000673] -------N---- | | \--* ADD byref N010 ( 1, 1) [000671] ------------ | | +--* LCL_VAR byref V81 tmp51 N011 ( 1, 1) [000672] ------------ | | \--* CNS_INT long 8 Fseq[_sign] N014 ( 3, 2) [000675] -------N---- | \--* LCL_VAR int V65 tmp35 N019 ( 3, 3) [000679] ------------ arg0 in rcx +--* ADDR byref N018 ( 3, 2) [000678] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 N020 ( 3, 3) [000462] ------------ arg1 in rdx \--* LCL_VAR_ADDR long V45 tmp15 ***** BB23 STMT00100 (IL 0x0FF... ???) N003 ( 5, 4) [000475] -A--G---R--- * ASG ref N002 ( 3, 2) [000474] D---G--N---- +--* LCL_VAR ref (AX) V45 tmp15 N001 ( 1, 1) [000473] ------------ \--* CNS_INT ref null ***** BB23 STMT00033 (IL ???... ???) N003 ( 7, 5) [000148] -A------R--- * ASG int N002 ( 3, 2) [000147] D------N---- +--* LCL_VAR int V17 loc14 N001 ( 3, 2) [000469] ------------ \--* LCL_VAR int V43 tmp13 ***** BB23 STMT00103 (IL 0x108... ???) N007 ( 14, 10) [000687] -A--G------- * COMMA void N003 ( 7, 5) [000683] -A--G---R--- +--* ASG ref N002 ( 3, 2) [000681] D------N---- | +--* LCL_VAR ref V66 tmp36 N001 ( 3, 2) [000682] ----G--N---- | \--* LCL_VAR ref (AX) V58 tmp28 N006 ( 7, 5) [000686] -A--G---R--- \--* ASG int N005 ( 3, 2) [000684] D------N---- +--* LCL_VAR int V67 tmp37 N004 ( 3, 2) [000685] ----G--N---- \--* LCL_VAR int (AX) V59 tmp29 ***** BB23 STMT00102 (IL 0x108... ???) N023 ( 45, 31) [000486] -ACXG---R--- * ASG int N022 ( 3, 2) [000485] D------N---- +--* LCL_VAR int V46 tmp16 N021 ( 41, 28) [000481] -ACXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits N016 ( 18, 15) [000706] -A--------L- arg0 SETUP +--* COMMA void N009 ( 10, 8) [000699] -A---------- | +--* COMMA void N004 ( 3, 3) [000694] -A------R--- | | +--* ASG byref N003 ( 1, 1) [000693] D------N---- | | | +--* LCL_VAR byref V82 tmp52 N002 ( 3, 3) [000691] ------------ | | | \--* ADDR byref N001 ( 3, 2) [000692] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 N008 ( 7, 5) [000698] -A---------- | | \--* ASG ref N006 ( 3, 2) [000696] *------N---- | | +--* IND ref N005 ( 1, 1) [000695] ------------ | | | \--* LCL_VAR byref V82 tmp52 Zero Fseq[_bits] N007 ( 3, 2) [000697] -------N---- | | \--* LCL_VAR ref V66 tmp36 N015 ( 8, 7) [000705] -A---------- | \--* ASG int N013 ( 4, 4) [000703] *------N---- | +--* IND int N012 ( 2, 2) [000702] -------N---- | | \--* ADD byref N010 ( 1, 1) [000700] ------------ | | +--* LCL_VAR byref V82 tmp52 N011 ( 1, 1) [000701] ------------ | | \--* CNS_INT long 8 Fseq[_sign] N014 ( 3, 2) [000704] -------N---- | \--* LCL_VAR int V67 tmp37 N019 ( 3, 3) [000708] ------------ arg0 in rcx +--* ADDR byref N018 ( 3, 2) [000707] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 N020 ( 3, 3) [000480] ------------ arg1 in rdx \--* LCL_VAR_ADDR long V48 tmp18 ***** BB23 STMT00104 (IL 0x108... ???) N003 ( 5, 4) [000493] -A--G---R--- * ASG ref N002 ( 3, 2) [000492] D---G--N---- +--* LCL_VAR ref (AX) V48 tmp18 N001 ( 1, 1) [000491] ------------ \--* CNS_INT ref null ***** BB23 STMT00035 (IL ???... ???) N003 ( 7, 5) [000155] -A------R--- * ASG int N002 ( 3, 2) [000154] D------N---- +--* LCL_VAR int V18 loc15 N001 ( 3, 2) [000487] ------------ \--* LCL_VAR int V46 tmp16 ***** BB23 STMT00036 (IL 0x111...0x115) N004 ( 9, 7) [000159] ------------ * JTRUE void N003 ( 7, 5) [000158] N------N-U-- \--* GT int N001 ( 3, 2) [000156] ------------ +--* LCL_VAR int V46 tmp16 N002 ( 3, 2) [000157] ------------ \--* LCL_VAR int V43 tmp13 ------------ BB24 [117..11A) -> BB26 (always), preds={BB23} succs={BB26} ***** BB24 STMT00074 (IL 0x117...0x118) N003 ( 5, 4) [000350] -A------R--- * ASG int N002 ( 3, 2) [000349] D------N---- +--* LCL_VAR int V33 tmp3 N001 ( 1, 1) [000348] ------------ \--* CNS_INT int 0 ------------ BB25 [11A..11F), preds={BB23} succs={BB26} ***** BB25 STMT00037 (IL 0x11A...0x11E) N005 ( 11, 8) [000164] -A------R--- * ASG int N004 ( 3, 2) [000163] D------N---- +--* LCL_VAR int V33 tmp3 N003 ( 7, 5) [000162] ------------ \--* SUB int N001 ( 3, 2) [000160] ------------ +--* LCL_VAR int V18 loc15 N002 ( 3, 2) [000161] ------------ \--* LCL_VAR int V17 loc14 ------------ BB26 [11F..126) -> BB28 (cond), preds={BB24,BB25} succs={BB27,BB28} ***** BB26 STMT00038 (IL ???...0x11F) N003 ( 3, 3) [000168] -A------R--- * ASG int N002 ( 1, 1) [000167] D------N---- +--* LCL_VAR int V19 loc16 N001 ( 3, 2) [000166] ------------ \--* LCL_VAR int V33 tmp3 ***** BB26 STMT00039 (IL 0x121...0x124) N004 ( 7, 6) [000172] ------------ * JTRUE void N003 ( 5, 4) [000171] N------N---- \--* EQ int N001 ( 3, 2) [000169] ------------ +--* LCL_VAR int V33 tmp3 N002 ( 1, 1) [000170] ------------ \--* CNS_INT int 0 ------------ BB27 [126..12F), preds={BB26} succs={BB28} ***** BB27 STMT00073 (IL 0x126...0x12A) N006 ( 18, 11) [000347] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft N004 ( 3, 3) [000345] ------------ arg0 in rcx +--* ADDR long N003 ( 3, 2) [000344] ----G--N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 N005 ( 1, 1) [000346] ------------ arg1 in rdx \--* LCL_VAR int V19 loc16 ------------ BB28 [12F..13E) -> BB32 (cond), preds={BB26,BB27} succs={BB29,BB32} ***** BB28 STMT00040 (IL 0x12F...0x133) N005 ( 9, 7) [000177] -A------R--- * ASG int N004 ( 3, 2) [000176] D------N---- +--* LCL_VAR int V20 loc17 N003 ( 5, 4) [000175] ------------ \--* SUB int N001 ( 3, 2) [000173] ------------ +--* LCL_VAR int V03 loc0 N002 ( 1, 1) [000174] ------------ \--* LCL_VAR int V13 loc10 ***** BB28 STMT00041 (IL 0x135...0x137) N003 ( 7, 5) [000180] -A------R--- * ASG int N002 ( 3, 2) [000179] D------N---- +--* LCL_VAR int V21 loc18 N001 ( 3, 2) [000178] ------------ \--* LCL_VAR int V20 loc17 ***** BB28 STMT00042 (IL 0x139...0x13C) N004 ( 5, 5) [000184] ------------ * JTRUE void N003 ( 3, 3) [000183] N------N---- \--* EQ int N001 ( 1, 1) [000181] ------------ +--* LCL_VAR int V13 loc10 N002 ( 1, 1) [000182] ------------ \--* CNS_INT int 0 ------------ BB29 [13E..144) -> BB31 (cond), preds={BB28} succs={BB30,BB31} ***** BB29 STMT00070 (IL 0x13E...0x142) N004 ( 7, 6) [000329] ------------ * JTRUE void N003 ( 5, 4) [000328] N------N-U-- \--* LE int N001 ( 1, 1) [000326] ------------ +--* LCL_VAR int V19 loc16 N002 ( 3, 2) [000327] ------------ \--* LCL_VAR int V21 loc18 ------------ BB30 [144..155) -> BB44 (always), preds={BB29} succs={BB44} ***** BB30 STMT00072 (IL 0x144...0x154) N014 ( 29, 17) [000717] -ACXG---R--- * ASG int N013 ( 1, 1) [000716] D------N---- +--* LCL_VAR int V51 tmp21 N012 ( 29, 17) [000342] --CXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits N005 ( 1, 1) [000341] ------------ arg4 out+20 +--* LCL_VAR byref V02 arg2 N008 ( 6, 3) [000339] N----------- arg2 in r8 +--* NE int N006 ( 1, 1) [000337] ------------ | +--* LCL_VAR int V10 loc7 N007 ( 1, 1) [000338] ------------ | \--* CNS_INT int 0 N009 ( 3, 2) [000335] ----G------- arg0 in rcx +--* LCL_VAR ref (AX) V12 loc9 N010 ( 1, 1) [000336] ------------ arg1 in rdx +--* LCL_VAR int V13 loc10 N011 ( 1, 1) [000340] ------------ arg3 in r9 \--* LCL_VAR ref V01 arg1 ------------ BB31 [155..15C), preds={BB29} succs={BB32} ***** BB31 STMT00071 (IL 0x155...0x15A) N005 ( 9, 7) [000334] -A------R--- * ASG int N004 ( 3, 2) [000333] D------N---- +--* LCL_VAR int V21 loc18 N003 ( 5, 4) [000332] ------------ \--* SUB int N001 ( 3, 2) [000330] ------------ +--* LCL_VAR int V21 loc18 N002 ( 1, 1) [000331] ------------ \--* LCL_VAR int V19 loc16 ------------ BB32 [15C..167) -> BB34 (cond), preds={BB28,BB31} succs={BB33,BB34} ***** BB32 STMT00105 (IL 0x15C... ???) N007 ( 14, 10) [000724] -A--G------- * COMMA void N003 ( 7, 5) [000720] -A--G---R--- +--* ASG ref N002 ( 3, 2) [000718] D---G--N---- | +--* LCL_VAR ref (AX) V68 tmp38 N001 ( 3, 2) [000719] ----G--N---- | \--* LCL_VAR ref (AX) V56 tmp26 N006 ( 7, 5) [000723] -A--G---R--- \--* ASG int N005 ( 3, 2) [000721] D---G--N---- +--* LCL_VAR int (AX) V69 tmp39 N004 ( 3, 2) [000722] ----G--N---- \--* LCL_VAR int (AX) V57 tmp27 ***** BB32 STMT00106 (IL 0x15C... ???) N007 ( 14, 10) [000731] -A--G------- * COMMA void N003 ( 7, 5) [000727] -A--G---R--- +--* ASG ref N002 ( 3, 2) [000725] D------N---- | +--* LCL_VAR ref V70 tmp40 N001 ( 3, 2) [000726] ----G--N---- | \--* LCL_VAR ref (AX) V58 tmp28 N006 ( 7, 5) [000730] -A--G---R--- \--* ASG int N005 ( 3, 2) [000728] D------N---- +--* LCL_VAR int V71 tmp41 N004 ( 3, 2) [000729] ----G--N---- \--* LCL_VAR int (AX) V59 tmp29 ***** BB32 STMT00044 (IL ???... ???) N027 ( 52, 38) [000195] -ACXG------- * JTRUE void N026 ( 50, 36) [000503] JACXG--N---- \--* LT int N024 ( 48, 34) [000499] -ACXG------- +--* CALL int System.Numerics.BigInteger.CompareTo N004 ( 7, 6) [000752] -A------R-L- this SETUP | +--* ASG byref N003 ( 3, 2) [000751] D------N---- | | +--* LCL_VAR byref V84 tmp54 N002 ( 3, 3) [000497] ------------ | | \--* ADDR byref N001 ( 3, 2) [000496] ----G--N---- | | \--* LCL_VAR struct(AX)(P) V49 tmp19 | | \--* ref V49._bits (offs=0x00) -> V68 tmp38 | | \--* int V49._sign (offs=0x08) -> V69 tmp39 N020 ( 18, 15) [000750] -A--------L- arg1 SETUP | +--* COMMA void N013 ( 10, 8) [000743] -A---------- | | +--* COMMA void N008 ( 3, 3) [000738] -A------R--- | | | +--* ASG byref N007 ( 1, 1) [000737] D------N---- | | | | +--* LCL_VAR byref V83 tmp53 N006 ( 3, 3) [000735] ------------ | | | | \--* ADDR byref N005 ( 3, 2) [000736] ----G--N---- | | | | \--* LCL_VAR struct(AX) V76 tmp46 N012 ( 7, 5) [000742] -A---------- | | | \--* ASG ref N010 ( 3, 2) [000740] *------N---- | | | +--* IND ref N009 ( 1, 1) [000739] ------------ | | | | \--* LCL_VAR byref V83 tmp53 Zero Fseq[_bits] N011 ( 3, 2) [000741] -------N---- | | | \--* LCL_VAR ref V70 tmp40 N019 ( 8, 7) [000749] -A---------- | | \--* ASG int N017 ( 4, 4) [000747] *------N---- | | +--* IND int N016 ( 2, 2) [000746] -------N---- | | | \--* ADD byref N014 ( 1, 1) [000744] ------------ | | | +--* LCL_VAR byref V83 tmp53 N015 ( 1, 1) [000745] ------------ | | | \--* CNS_INT long 8 Fseq[_sign] N018 ( 3, 2) [000748] -------N---- | | \--* LCL_VAR int V71 tmp41 N021 ( 3, 2) [000753] ------------ this in rcx | +--* LCL_VAR byref V84 tmp54 N023 ( 3, 3) [000755] ------------ arg1 in rdx | \--* ADDR byref N022 ( 3, 2) [000754] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 N025 ( 1, 1) [000502] ------------ \--* CNS_INT int 0 ------------ BB33 [167..16B) -> BB35 (always), preds={BB32} succs={BB35} ***** BB33 STMT00069 (IL 0x167...0x169) N003 ( 5, 4) [000324] -A------R--- * ASG int N002 ( 3, 2) [000323] D------N---- +--* LCL_VAR int V34 tmp4 N001 ( 1, 1) [000322] ------------ \--* LCL_VAR int V19 loc16 ------------ BB34 [16B..16F), preds={BB32} succs={BB35} ***** BB34 STMT00045 (IL 0x16B...0x16E) N005 ( 7, 6) [000200] -A------R--- * ASG int N004 ( 3, 2) [000199] D------N---- +--* LCL_VAR int V34 tmp4 N003 ( 3, 3) [000198] ------------ \--* ADD int N001 ( 1, 1) [000196] ------------ +--* LCL_VAR int V19 loc16 N002 ( 1, 1) [000197] ------------ \--* CNS_INT int 1 ------------ BB35 [16F..1A4) -> BB40 (cond), preds={BB33,BB34} succs={BB36,BB40} ***** BB35 STMT00046 (IL ???...0x16F) N003 ( 7, 5) [000204] -A------R--- * ASG int N002 ( 3, 2) [000203] D------N---- +--* LCL_VAR int V22 loc19 N001 ( 3, 2) [000202] ------------ \--* LCL_VAR int V34 tmp4 ***** BB35 STMT00047 (IL 0x171...0x18A) N006 ( 20, 12) [000208] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft N004 ( 3, 3) [000206] ------------ arg0 in rcx +--* ADDR long N003 ( 3, 2) [000205] ----G--N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 N005 ( 3, 2) [000207] ------------ arg1 in rdx \--* LCL_VAR int V21 loc18 ***** BB35 STMT00048 (IL 0x17A... ???) N045 ( 78, 56) [000213] SACXG------- * CALL void System.Numerics.BigInteger.DivRem N004 ( 7, 6) [000797] -A------R-L- arg0 SETUP +--* ASG long N003 ( 3, 2) [000796] D------N---- | +--* LCL_VAR long V88 tmp58 N002 ( 3, 3) [000220] ------------ | \--* ADDR long N001 ( 3, 2) [000219] ----G--N---- | \--* LCL_VAR struct(AX)(P) V35 tmp5 | \--* ref V35._bits (offs=0x00) -> V62 tmp32 | \--* int V35._sign (offs=0x08) -> V63 tmp33 N020 ( 18, 15) [000776] -A--G-----L- arg1 SETUP +--* COMMA void N013 ( 10, 8) [000769] -A--G------- | +--* COMMA void N008 ( 3, 3) [000764] -A------R--- | | +--* ASG byref N007 ( 1, 1) [000763] D------N---- | | | +--* LCL_VAR byref V85 tmp55 N006 ( 3, 3) [000761] ------------ | | | \--* ADDR byref N005 ( 3, 2) [000762] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 N012 ( 7, 5) [000768] -A--G------- | | \--* ASG ref N010 ( 3, 2) [000766] *------N---- | | +--* IND ref N009 ( 1, 1) [000765] ------------ | | | \--* LCL_VAR byref V85 tmp55 Zero Fseq[_bits] N011 ( 3, 2) [000767] ----G--N---- | | \--* LCL_VAR ref (AX) V56 tmp26 N019 ( 8, 7) [000775] -A--G------- | \--* ASG int N017 ( 4, 4) [000773] *------N---- | +--* IND int N016 ( 2, 2) [000772] -------N---- | | \--* ADD byref N014 ( 1, 1) [000770] ------------ | | +--* LCL_VAR byref V85 tmp55 N015 ( 1, 1) [000771] ------------ | | \--* CNS_INT long 8 Fseq[_sign] N018 ( 3, 2) [000774] ----G--N---- | \--* LCL_VAR int (AX) V57 tmp27 N036 ( 18, 15) [000795] -A--G-----L- arg2 SETUP +--* COMMA void N029 ( 10, 8) [000788] -A--G------- | +--* COMMA void N024 ( 3, 3) [000783] -A------R--- | | +--* ASG byref N023 ( 1, 1) [000782] D------N---- | | | +--* LCL_VAR byref V87 tmp57 N022 ( 3, 3) [000780] ------------ | | | \--* ADDR byref N021 ( 3, 2) [000781] -------N---- | | | \--* LCL_VAR struct(AX) V86 tmp56 N028 ( 7, 5) [000787] -A--G------- | | \--* ASG ref N026 ( 3, 2) [000785] *------N---- | | +--* IND ref N025 ( 1, 1) [000784] ------------ | | | \--* LCL_VAR byref V87 tmp57 Zero Fseq[_bits] N027 ( 3, 2) [000786] ----G--N---- | | \--* LCL_VAR ref (AX) V58 tmp28 N035 ( 8, 7) [000794] -A--G------- | \--* ASG int N033 ( 4, 4) [000792] *------N---- | +--* IND int N032 ( 2, 2) [000791] -------N---- | | \--* ADD byref N030 ( 1, 1) [000789] ------------ | | +--* LCL_VAR byref V87 tmp57 N031 ( 1, 1) [000790] ------------ | | \--* CNS_INT long 8 Fseq[_sign] N034 ( 3, 2) [000793] ----G--N---- | \--* LCL_VAR int (AX) V59 tmp29 N038 ( 3, 2) [000798] ------------ arg0 in rcx +--* LCL_VAR long V88 tmp58 N040 ( 3, 3) [000800] ------------ arg1 in rdx +--* ADDR byref N039 ( 3, 2) [000799] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 N042 ( 3, 3) [000802] ------------ arg2 in r8 +--* ADDR byref N041 ( 3, 2) [000801] -------N---- | \--* LCL_VAR struct(AX) V86 tmp56 N044 ( 3, 3) [000212] ------------ arg3 in r9 \--* ADDR long N043 ( 3, 2) [000211] ----G--N---- \--* LCL_VAR struct(AX)(P) V23 loc20 \--* ref V23._bits (offs=0x00) -> V60 tmp30 \--* int V23._sign (offs=0x08) -> V61 tmp31 ***** BB35 STMT00050 (IL ???... ???) N021 ( 38, 24) [000226] -ACXG---R--- * ASG long N020 ( 1, 1) [000225] D------N---- +--* LCL_VAR long V24 loc21 N019 ( 38, 24) [000218] -ACXG------- \--* CALL long System.Numerics.BigInteger.op_Explicit N016 ( 18, 15) [000822] -A--G-----L- arg0 SETUP +--* COMMA void N009 ( 10, 8) [000815] -A--G------- | +--* COMMA void N004 ( 3, 3) [000810] -A------R--- | | +--* ASG byref N003 ( 1, 1) [000809] D------N---- | | | +--* LCL_VAR byref V89 tmp59 N002 ( 3, 3) [000807] ------------ | | | \--* ADDR byref N001 ( 3, 2) [000808] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 N008 ( 7, 5) [000814] -A--G------- | | \--* ASG ref N006 ( 3, 2) [000812] *------N---- | | +--* IND ref N005 ( 1, 1) [000811] ------------ | | | \--* LCL_VAR byref V89 tmp59 Zero Fseq[_bits] N007 ( 3, 2) [000813] ----G--N---- | | \--* LCL_VAR ref (AX) V62 tmp32 N015 ( 8, 7) [000821] -A--G------- | \--* ASG int N013 ( 4, 4) [000819] *------N---- | +--* IND int N012 ( 2, 2) [000818] -------N---- | | \--* ADD byref N010 ( 1, 1) [000816] ------------ | | +--* LCL_VAR byref V89 tmp59 N011 ( 1, 1) [000817] ------------ | | \--* CNS_INT long 8 Fseq[_sign] N014 ( 3, 2) [000820] ----G--N---- | \--* LCL_VAR int (AX) V63 tmp33 N018 ( 3, 3) [000824] ------------ arg0 in rcx \--* ADDR byref N017 ( 3, 2) [000823] -------N---- \--* LCL_VAR struct(AX) V76 tmp46 ***** BB35 STMT00052 (IL ???... ???) N005 ( 12, 7) [000232] -A--G---R--- * ASG int N004 ( 3, 2) [000231] D------N---- +--* LCL_VAR int V25 loc22 N003 ( 8, 4) [000516] ----G------- \--* EQ int N001 ( 3, 2) [000514] ----G------- +--* LCL_VAR int (AX) V61 tmp31 N002 ( 1, 1) [000515] ------------ \--* CNS_INT int 0 ***** BB35 STMT00054 (IL ???... ???) N005 ( 19, 10) [000237] -ACXG---R--- * ASG int N004 ( 3, 2) [000236] D------N---- +--* LCL_VAR int V26 loc23 N003 ( 15, 7) [000234] --CXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits N002 ( 1, 1) [000233] ------------ arg0 in rcx \--* LCL_VAR long V24 loc21 ***** BB35 STMT00055 (IL 0x19E...0x1A2) N004 ( 9, 7) [000241] ------------ * JTRUE void N003 ( 7, 5) [000240] N------N-U-- \--* LE int N001 ( 3, 2) [000238] ------------ +--* LCL_VAR int V26 loc23 N002 ( 3, 2) [000239] ------------ \--* LCL_VAR int V20 loc17 ------------ BB36 [1A4..1AF) -> BB38 (cond), preds={BB35} succs={BB37,BB38} ***** BB36 STMT00063 (IL 0x1A4...0x1A9) N005 ( 11, 8) [000286] -A------R--- * ASG int N004 ( 3, 2) [000285] D------N---- +--* LCL_VAR int V29 loc26 N003 ( 7, 5) [000284] ------------ \--* SUB int N001 ( 3, 2) [000282] ------------ +--* LCL_VAR int V26 loc23 N002 ( 3, 2) [000283] ------------ \--* LCL_VAR int V20 loc17 ***** BB36 STMT00064 (IL 0x1AB...0x1AD) N004 ( 7, 6) [000290] ------------ * JTRUE void N003 ( 5, 4) [000289] J------N---- \--* EQ int N001 ( 3, 2) [000287] ------------ +--* LCL_VAR int V25 loc22 N002 ( 1, 1) [000288] ------------ \--* CNS_INT int 0 ------------ BB37 [1AF..1C3) -> BB39 (always), preds={BB36} succs={BB39} ***** BB37 STMT00068 (IL 0x1AF...0x1C1) N013 ( 23, 15) [000320] -A------R--- * ASG int N012 ( 3, 2) [000319] D------N---- +--* LCL_VAR int V37 tmp7 N011 ( 19, 12) [000318] ------------ \--* EQ int N009 ( 14, 10) [000315] ------------ +--* AND long N001 ( 1, 1) [000305] ------------ | +--* LCL_VAR long V24 loc21 N008 ( 12, 8) [000314] ------------ | \--* ADD long N006 ( 10, 6) [000311] --------R--- | +--* LSH long N005 ( 1, 1) [000307] ------------ | | +--* CNS_INT long 1 N004 ( 5, 4) [000310] ------------ | | \--* AND int N002 ( 3, 2) [000308] ------------ | | +--* LCL_VAR int V29 loc26 N003 ( 1, 1) [000309] ------------ | | \--* CNS_INT int 63 N007 ( 1, 1) [000313] ------------ | \--* CNS_INT long -1 N010 ( 1, 1) [000317] ------------ \--* CNS_INT long 0 ------------ BB38 [1C3..1C4), preds={BB36} succs={BB39} ***** BB38 STMT00065 (IL 0x1C3...0x1C3) N003 ( 5, 4) [000293] -A------R--- * ASG int N002 ( 3, 2) [000292] D------N---- +--* LCL_VAR int V37 tmp7 N001 ( 1, 1) [000291] ------------ \--* CNS_INT int 0 ------------ BB39 [1C4..1D0), preds={BB37,BB38} succs={BB40} ***** BB39 STMT00066 (IL ???...0x1C4) N004 ( 8, 7) [000297] -A------R--- * ASG int N003 ( 3, 2) [000296] D------N---- +--* LCL_VAR int V25 loc22 N002 ( 4, 4) [000826] ------------ \--* CAST int <- bool <- int N001 ( 3, 2) [000295] ------------ \--* LCL_VAR int V37 tmp7 ***** BB39 STMT00067 (IL 0x1C6...0x1CE) N007 ( 10, 6) [000304] -A------R--- * ASG long N006 ( 1, 1) [000303] D------N---- +--* LCL_VAR long V24 loc21 N005 ( 10, 6) [000302] ------------ \--* RSZ long N001 ( 1, 1) [000298] ------------ +--* LCL_VAR long V24 loc21 N004 ( 5, 4) [000301] ------------ \--* AND int N002 ( 3, 2) [000299] ------------ +--* LCL_VAR int V29 loc26 N003 ( 1, 1) [000300] ------------ \--* CNS_INT int 63 ------------ BB40 [1D0..1E7) -> BB42 (cond), preds={BB35,BB39} succs={BB41,BB42} ***** BB40 STMT00057 (IL ???... ???) N027 ( 53, 34) [000254] -ACXG---R--- * ASG long N026 ( 3, 2) [000253] D------N---- +--* LCL_VAR long V27 loc24 N025 ( 49, 31) [000252] -ACXG------- \--* ADD long N023 ( 47, 29) [000250] -ACXG------- +--* LSH long N019 ( 38, 24) [000243] -ACXG------- | +--* CALL long System.Numerics.BigInteger.op_Explicit N016 ( 18, 15) [000845] -A--G-----L- arg0 SETUP | | +--* COMMA void N009 ( 10, 8) [000838] -A--G------- | | | +--* COMMA void N004 ( 3, 3) [000833] -A------R--- | | | | +--* ASG byref N003 ( 1, 1) [000832] D------N---- | | | | | +--* LCL_VAR byref V90 tmp60 N002 ( 3, 3) [000830] ------------ | | | | | \--* ADDR byref N001 ( 3, 2) [000831] ----G--N---- | | | | | \--* LCL_VAR struct(AX) V76 tmp46 N008 ( 7, 5) [000837] -A--G------- | | | | \--* ASG ref N006 ( 3, 2) [000835] *------N---- | | | | +--* IND ref N005 ( 1, 1) [000834] ------------ | | | | | \--* LCL_VAR byref V90 tmp60 Zero Fseq[_bits] N007 ( 3, 2) [000836] ----G--N---- | | | | \--* LCL_VAR ref (AX) V54 tmp24 N015 ( 8, 7) [000844] -A--G------- | | | \--* ASG int N013 ( 4, 4) [000842] *------N---- | | | +--* IND int N012 ( 2, 2) [000841] -------N---- | | | | \--* ADD byref N010 ( 1, 1) [000839] ------------ | | | | +--* LCL_VAR byref V90 tmp60 N011 ( 1, 1) [000840] ------------ | | | | \--* CNS_INT long 8 Fseq[_sign] N014 ( 3, 2) [000843] ----G--N---- | | | \--* LCL_VAR int (AX) V55 tmp25 N018 ( 3, 3) [000847] ------------ arg0 in rcx | | \--* ADDR byref N017 ( 3, 2) [000846] -------N---- | | \--* LCL_VAR struct(AX) V76 tmp46 N022 ( 5, 4) [000249] ------------ | \--* AND int N020 ( 3, 2) [000247] ------------ | +--* LCL_VAR int V20 loc17 N021 ( 1, 1) [000248] ------------ | \--* CNS_INT int 63 N024 ( 1, 1) [000251] ------------ \--* LCL_VAR long V24 loc21 ***** BB40 STMT00058 (IL 0x1E2...0x1E5) N004 ( 5, 5) [000258] ------------ * JTRUE void N003 ( 3, 3) [000257] N------N---- \--* NE int N001 ( 1, 1) [000255] ------------ +--* LCL_VAR int V13 loc10 N002 ( 1, 1) [000256] ------------ \--* CNS_INT int 0 ------------ BB41 [1E7..1EE) -> BB43 (always), preds={BB40} succs={BB43} ***** BB41 STMT00062 (IL 0x1E7...0x1EC) N006 ( 10, 8) [000280] -A------R--- * ASG int N005 ( 3, 2) [000279] D------N---- +--* LCL_VAR int V36 tmp6 N004 ( 6, 5) [000278] ------------ \--* ADD int N002 ( 4, 3) [000276] ------------ +--* NEG int N001 ( 3, 2) [000275] ------------ | \--* LCL_VAR int V22 loc19 N003 ( 1, 1) [000277] ------------ \--* CNS_INT int -1 ------------ BB42 [1EE..1F2), preds={BB40} succs={BB43} ***** BB42 STMT00059 (IL 0x1EE...0x1F1) N005 ( 7, 6) [000263] -A------R--- * ASG int N004 ( 3, 2) [000262] D------N---- +--* LCL_VAR int V36 tmp6 N003 ( 3, 3) [000261] ------------ \--* ADD int N001 ( 1, 1) [000259] ------------ +--* LCL_VAR int V13 loc10 N002 ( 1, 1) [000260] ------------ \--* CNS_INT int -2 ------------ BB43 [1F2..202), preds={BB41,BB42} succs={BB44} ***** BB43 STMT00060 (IL ???...0x1F2) N003 ( 7, 5) [000267] -A------R--- * ASG int N002 ( 3, 2) [000266] D------N---- +--* LCL_VAR int V28 loc25 N001 ( 3, 2) [000265] ------------ \--* LCL_VAR int V36 tmp6 ***** BB43 STMT00061 (IL 0x1F4...0x201) N012 ( 28, 18) [000853] -ACXG---R--- * ASG int N011 ( 1, 1) [000852] D------N---- +--* LCL_VAR int V51 tmp21 N010 ( 28, 18) [000273] --CXG------- \--* CALL nullcheck int FloatingPointType.AssembleFloatingPointValue N005 ( 1, 1) [000272] ------------ arg4 out+20 +--* LCL_VAR byref V02 arg2 N006 ( 1, 1) [000268] ------------ this in rcx +--* LCL_VAR ref V01 arg1 N007 ( 3, 2) [000269] ------------ arg1 in rdx +--* LCL_VAR long V27 loc24 N008 ( 3, 2) [000270] ------------ arg2 in r8 +--* LCL_VAR int V36 tmp6 N009 ( 3, 2) [000271] ------------ arg3 in r9 \--* LCL_VAR int V25 loc22 ------------ BB44 [???..???) (return), preds={BB16,BB30,BB43} succs={} ***** BB44 STMT00109 (IL ???... ???) N002 ( 2, 2) [000523] ------------ * RETURN int N001 ( 1, 1) [000522] -------N---- \--* LCL_VAR int V51 tmp21 ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Build SSA representation *************** In SsaBuilder::Build() [SsaBuilder] Max block count is 45. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0056] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..00D)-> BB04 ( cond ) i label target idxlen BB03 [0001] 1 BB02 0.50 [00D..017) (return) i hascall gcsafe BB04 [0002] 1 BB02 0.50 [017..065)-> BB06 ( cond ) i label target hascall gcsafe BB05 [0038] 1 BB04 0.50 [020..021)-> BB07 (always) i gcsafe BB06 [0039] 1 BB04 0.50 [020..021) i label target gcsafe BB07 [0040] 2 BB05,BB06 0.50 [000..000)-> BB09 ( cond ) i internal label target gcsafe idxlen BB08 [0043] 1 BB07 0.50 [000..000)-> BB10 (always) i internal gcsafe BB09 [0044] 1 BB07 0.50 [000..000) i internal label target gcsafe BB10 [0045] 2 BB08,BB09 0.50 [???..???)-> BB14 ( cond ) i internal label target hascall gcsafe idxlen BB11 [0003] 1 BB10 0.50 [065..070)-> BB13 ( cond ) i hascall gcsafe BB12 [0004] 1 BB11 0.50 [070..07A) (return) i hascall gcsafe BB13 [0005] 1 BB11 0.50 [07A..082) i label target hascall gcsafe BB14 [0006] 2 BB10,BB13 0.50 [082..092)-> BB16 ( cond ) i label target hascall gcsafe BB15 [0007] 1 BB14 0.50 [092..096)-> BB17 ( cond ) i gcsafe BB16 [0008] 2 BB14,BB15 0.50 [096..0A7)-> BB44 (always) i label target hascall gcsafe BB17 [0009] 1 BB15 0.50 [0A7..0B0)-> BB19 ( cond ) i label target gcsafe BB18 [0010] 1 BB17 0.50 [0B0..0B4)-> BB20 (always) i gcsafe BB19 [0011] 1 BB17 0.50 [0B4..0BE) i label target gcsafe BB20 [0012] 2 BB18,BB19 0.50 [0BE..0C4)-> BB23 ( cond ) i label target gcsafe BB21 [0013] 1 BB20 0.50 [0C4..0D9)-> BB23 ( cond ) i hascall gcsafe idxlen BB22 [0014] 1 BB21 0.50 [0D9..0E3) (return) i hascall gcsafe BB23 [0015] 2 BB20,BB21 0.50 [0E3..117)-> BB25 ( cond ) i label target hascall gcsafe BB24 [0016] 1 BB23 0.50 [117..11A)-> BB26 (always) i gcsafe BB25 [0017] 1 BB23 0.50 [11A..11F) i label target gcsafe BB26 [0018] 2 BB24,BB25 0.50 [11F..126)-> BB28 ( cond ) i label target gcsafe BB27 [0019] 1 BB26 0.50 [126..12F) i hascall gcsafe BB28 [0020] 2 BB26,BB27 0.50 [12F..13E)-> BB32 ( cond ) i label target gcsafe BB29 [0021] 1 BB28 0.50 [13E..144)-> BB31 ( cond ) i gcsafe BB30 [0022] 1 BB29 0.50 [144..155)-> BB44 (always) i hascall gcsafe BB31 [0023] 1 BB29 0.50 [155..15C) i label target gcsafe BB32 [0024] 2 BB28,BB31 0.50 [15C..167)-> BB34 ( cond ) i label target hascall gcsafe BB33 [0025] 1 BB32 0.50 [167..16B)-> BB35 (always) i gcsafe BB34 [0026] 1 BB32 0.50 [16B..16F) i label target gcsafe BB35 [0027] 2 BB33,BB34 0.50 [16F..1A4)-> BB40 ( cond ) i label target hascall gcsafe BB36 [0028] 1 BB35 0.50 [1A4..1AF)-> BB38 ( cond ) i gcsafe BB37 [0029] 1 BB36 0.50 [1AF..1C3)-> BB39 (always) i gcsafe BB38 [0030] 1 BB36 0.50 [1C3..1C4) i label target gcsafe BB39 [0031] 2 BB37,BB38 0.50 [1C4..1D0) i label target gcsafe BB40 [0032] 2 BB35,BB39 0.50 [1D0..1E7)-> BB42 ( cond ) i label target hascall gcsafe BB41 [0033] 1 BB40 0.50 [1E7..1EE)-> BB43 (always) i gcsafe BB42 [0034] 1 BB40 0.50 [1EE..1F2) i label target gcsafe BB43 [0035] 2 BB41,BB42 0.50 [1F2..202) i label target hascall gcsafe BB44 [0054] 3 BB16,BB30,BB43 0.50 [???..???) (return) keep internal target gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty [SsaBuilder] Topologically sorted the graph. [SsaBuilder::ComputeImmediateDom] Inside fgBuildDomTree After computing the Dominance Tree: BB01 : BB02 BB02 : BB04 BB03 BB04 : BB07 BB06 BB05 BB07 : BB10 BB09 BB08 BB10 : BB14 BB11 BB11 : BB13 BB12 BB14 : BB44 BB16 BB15 BB15 : BB17 BB17 : BB20 BB19 BB18 BB20 : BB23 BB21 BB21 : BB22 BB23 : BB26 BB25 BB24 BB26 : BB28 BB27 BB28 : BB32 BB29 BB29 : BB31 BB30 BB32 : BB35 BB34 BB33 BB35 : BB40 BB36 BB36 : BB39 BB38 BB37 BB40 : BB43 BB42 BB41 *************** In fgLocalVarLiveness() In fgLocalVarLivenessInit Tracked variable (62 out of 91) table: V00 arg0 [ byref]: refCnt = 4, refCntWtd = 8 V01 arg1 [ ref]: refCnt = 11, refCntWtd = 6.50 V02 arg2 [ byref]: refCnt = 8, refCntWtd = 5 V13 loc10 [ int]: refCnt = 9, refCntWtd = 4.50 V52 tmp22 [ ref]: refCnt = 7, refCntWtd = 4.50 V41 tmp11 [ int]: refCnt = 8, refCntWtd = 4 V53 tmp23 [ int]: refCnt = 7, refCntWtd = 4 V51 tmp21 [ int]: refCnt = 4, refCntWtd = 4 V10 loc7 [ int]: refCnt = 6, refCntWtd = 3 V19 loc16 [ int]: refCnt = 6, refCntWtd = 3 V24 loc21 [ long]: refCnt = 6, refCntWtd = 3 V74 tmp44 [ byref]: refCnt = 3, refCntWtd = 3 V77 tmp47 [ byref]: refCnt = 3, refCntWtd = 3 V78 tmp48 [ byref]: refCnt = 3, refCntWtd = 3 V80 tmp50 [ byref]: refCnt = 3, refCntWtd = 3 V81 tmp51 [ byref]: refCnt = 3, refCntWtd = 3 V82 tmp52 [ byref]: refCnt = 3, refCntWtd = 3 V83 tmp53 [ byref]: refCnt = 3, refCntWtd = 3 V85 tmp55 [ byref]: refCnt = 3, refCntWtd = 3 V87 tmp57 [ byref]: refCnt = 3, refCntWtd = 3 V89 tmp59 [ byref]: refCnt = 3, refCntWtd = 3 V90 tmp60 [ byref]: refCnt = 3, refCntWtd = 3 V31 tmp1 [ int]: refCnt = 3, refCntWtd = 3 V42 tmp12 [ int]: refCnt = 3, refCntWtd = 3 V20 loc17 [ int]: refCnt = 5, refCntWtd = 2.50 V21 loc18 [ int]: refCnt = 5, refCntWtd = 2.50 V05 loc2 [ int]: refCnt = 4, refCntWtd = 2 V25 loc22 [ bool]: refCnt = 4, refCntWtd = 2 V33 tmp3 [ int]: refCnt = 4, refCntWtd = 2 V36 tmp6 [ int]: refCnt = 4, refCntWtd = 2 V39 tmp9 [ int]: refCnt = 4, refCntWtd = 2 V84 tmp54 [ byref]: refCnt = 2, refCntWtd = 2 V38 tmp8 [ long]: refCnt = 2, refCntWtd = 2 V40 tmp10 [ int]: refCnt = 2, refCntWtd = 2 V75 tmp45 [ long]: refCnt = 2, refCntWtd = 2 V79 tmp49 [ long]: refCnt = 2, refCntWtd = 2 V88 tmp58 [ long]: refCnt = 2, refCntWtd = 2 V03 loc0 [ int]: refCnt = 3, refCntWtd = 1.50 V09 loc6 [ int]: refCnt = 3, refCntWtd = 1.50 V14 loc11 [ int]: refCnt = 3, refCntWtd = 1.50 V26 loc23 [ int]: refCnt = 3, refCntWtd = 1.50 V29 loc26 [ int]: refCnt = 3, refCntWtd = 1.50 V32 tmp2 [ int]: refCnt = 3, refCntWtd = 1.50 V34 tmp4 [ int]: refCnt = 3, refCntWtd = 1.50 V37 tmp7 [ int]: refCnt = 3, refCntWtd = 1.50 V43 tmp13 [ int]: refCnt = 3, refCntWtd = 1.50 V46 tmp16 [ int]: refCnt = 3, refCntWtd = 1.50 V64 tmp34 [ ref]: refCnt = 2, refCntWtd = 1 V66 tmp36 [ ref]: refCnt = 2, refCntWtd = 1 V70 tmp40 [ ref]: refCnt = 2, refCntWtd = 1 V08 loc5 [ int]: refCnt = 2, refCntWtd = 1 V17 loc14 [ int]: refCnt = 2, refCntWtd = 1 V18 loc15 [ int]: refCnt = 2, refCntWtd = 1 V22 loc19 [ int]: refCnt = 2, refCntWtd = 1 V27 loc24 [ long]: refCnt = 2, refCntWtd = 1 V65 tmp35 [ int]: refCnt = 2, refCntWtd = 1 V67 tmp37 [ int]: refCnt = 2, refCntWtd = 1 V71 tmp41 [ int]: refCnt = 2, refCntWtd = 1 V04 loc1 [ int]: refCnt = 1, refCntWtd = 0.50 V06 loc3 [ int]: refCnt = 1, refCntWtd = 0.50 V07 loc4 [ int]: refCnt = 1, refCntWtd = 0.50 V28 loc25 [ int]: refCnt = 1, refCntWtd = 0.50 *************** In fgPerBlockLocalVarLiveness() BB01 USE(1)={V00 } + ByrefExposed + GcHeap DEF(2)={ V52 V53} BB02 USE(1)={V52} DEF(0)={ } BB03 USE(2)={V01 V02} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB04 USE(2)={V01 V53 } + ByrefExposed + GcHeap DEF(2)={ V40 V03} + ByrefExposed* + GcHeap* BB05 USE(1)={ V40} DEF(1)={V39 } BB06 USE(0)={ } DEF(1)={V39} BB07 USE(2)={V52 V39} DEF(2)={ V31 V42 } BB08 USE(1)={ V42} DEF(1)={V41 } BB09 USE(1)={ V31} DEF(1)={V41 } BB10 USE(4)={V52 V41 V53 V31 } + ByrefExposed + GcHeap DEF(9)={ V10 V74 V05 V75 V09 V08 V04 V06 V07} + ByrefExposed* + GcHeap* BB11 USE(2)={V01 V05} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB12 USE(2)={V01 V02} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB13 USE(1)={V05} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB14 USE(1)={ V03} + ByrefExposed + GcHeap DEF(2)={V13 V77 } + ByrefExposed* + GcHeap* BB15 USE(1)={V10} DEF(0)={ } BB16 USE(4)={V01 V02 V13 V10} + ByrefExposed + GcHeap DEF(1)={ V51 } + ByrefExposed* + GcHeap* BB17 USE(1)={V53} DEF(0)={ } BB18 USE(1)={V10 } DEF(1)={ V32} BB19 USE(2)={V53 V10 } DEF(1)={ V32} BB20 USE(2)={V13 V32} DEF(1)={ V14 } BB21 USE(3)={V01 V52 V14} + ByrefExposed + GcHeap DEF(1)={ V38 } + ByrefExposed* + GcHeap* BB22 USE(2)={V01 V02} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB23 USE(5)={V52 V53 V09 V14 V08 } + ByrefExposed + GcHeap DEF(13)={ V78 V80 V81 V82 V79 V43 V46 V64 V66 V17 V18 V65 V67} + ByrefExposed* + GcHeap* BB24 USE(0)={ } DEF(1)={V33} BB25 USE(2)={ V17 V18} DEF(1)={V33 } BB26 USE(1)={ V33} DEF(1)={V19 } BB27 USE(1)={V19} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB28 USE(2)={V13 V03} DEF(2)={ V20 V21 } BB29 USE(2)={V19 V21} DEF(0)={ } BB30 USE(4)={V01 V02 V13 V10} + ByrefExposed + GcHeap DEF(1)={ V51 } + ByrefExposed* + GcHeap* BB31 USE(2)={V19 V21} DEF(1)={ V21} BB32 USE(0)={ } + ByrefExposed + GcHeap DEF(4)={V83 V84 V70 V71} + ByrefExposed* + GcHeap* BB33 USE(1)={V19 } DEF(1)={ V34} BB34 USE(1)={V19 } DEF(1)={ V34} BB35 USE(3)={ V20 V21 V34 } + ByrefExposed + GcHeap DEF(8)={V24 V85 V87 V89 V25 V88 V26 V22} + ByrefExposed* + GcHeap* BB36 USE(3)={V20 V25 V26 } DEF(1)={ V29} BB37 USE(2)={V24 V29 } DEF(1)={ V37} BB38 USE(0)={ } DEF(1)={V37} BB39 USE(3)={V24 V29 V37} DEF(2)={V24 V25 } BB40 USE(3)={V13 V24 V20 } + ByrefExposed + GcHeap DEF(2)={ V90 V27} + ByrefExposed* + GcHeap* BB41 USE(1)={ V22} DEF(1)={V36 } BB42 USE(1)={V13 } DEF(1)={ V36} BB43 USE(5)={V01 V02 V25 V36 V27 } + ByrefExposed + GcHeap DEF(2)={ V51 V28} + ByrefExposed* + GcHeap* BB44 USE(1)={V51} DEF(0)={ } ** Memory liveness computed, GcHeap states and ByrefExposed states diverge *************** In fgInterBlockLocalVarLiveness() BB liveness after fgLiveVarAnalysis(): BB01 IN (3)={V00 V01 V02 } + ByrefExposed + GcHeap OUT(4)={ V01 V02 V52 V53} + ByrefExposed + GcHeap BB02 IN (4)={V01 V02 V52 V53} + ByrefExposed + GcHeap OUT(4)={V01 V02 V52 V53} + ByrefExposed + GcHeap BB03 IN (2)={V01 V02} + ByrefExposed + GcHeap OUT(0)={ } BB04 IN (4)={V01 V02 V52 V53 } + ByrefExposed + GcHeap OUT(6)={V01 V02 V52 V53 V40 V03} + ByrefExposed + GcHeap BB05 IN (6)={V01 V02 V52 V53 V40 V03} + ByrefExposed + GcHeap OUT(6)={V01 V02 V52 V53 V39 V03} + ByrefExposed + GcHeap BB06 IN (5)={V01 V02 V52 V53 V03} + ByrefExposed + GcHeap OUT(6)={V01 V02 V52 V53 V39 V03} + ByrefExposed + GcHeap BB07 IN (6)={V01 V02 V52 V53 V39 V03} + ByrefExposed + GcHeap OUT(7)={V01 V02 V52 V53 V31 V42 V03} + ByrefExposed + GcHeap BB08 IN (7)={V01 V02 V52 V53 V31 V42 V03} + ByrefExposed + GcHeap OUT(7)={V01 V02 V52 V41 V53 V31 V03} + ByrefExposed + GcHeap BB09 IN (6)={V01 V02 V52 V53 V31 V03} + ByrefExposed + GcHeap OUT(7)={V01 V02 V52 V41 V53 V31 V03} + ByrefExposed + GcHeap BB10 IN (7)={V01 V02 V52 V41 V53 V31 V03 } + ByrefExposed + GcHeap OUT(9)={V01 V02 V52 V53 V10 V05 V03 V09 V08} + ByrefExposed + GcHeap BB11 IN (9)={V01 V02 V52 V53 V10 V05 V03 V09 V08} + ByrefExposed + GcHeap OUT(9)={V01 V02 V52 V53 V10 V05 V03 V09 V08} + ByrefExposed + GcHeap BB12 IN (2)={V01 V02} + ByrefExposed + GcHeap OUT(0)={ } BB13 IN (9)={V01 V02 V52 V53 V10 V05 V03 V09 V08} + ByrefExposed + GcHeap OUT(8)={V01 V02 V52 V53 V10 V03 V09 V08} + ByrefExposed + GcHeap BB14 IN (8)={V01 V02 V52 V53 V10 V03 V09 V08} + ByrefExposed + GcHeap OUT(9)={V01 V02 V13 V52 V53 V10 V03 V09 V08} + ByrefExposed + GcHeap BB15 IN (9)={V01 V02 V13 V52 V53 V10 V03 V09 V08} + ByrefExposed + GcHeap OUT(9)={V01 V02 V13 V52 V53 V10 V03 V09 V08} + ByrefExposed + GcHeap BB16 IN (4)={V01 V02 V13 V10} + ByrefExposed + GcHeap OUT(1)={ V51 } BB17 IN (9)={V01 V02 V13 V52 V53 V10 V03 V09 V08} + ByrefExposed + GcHeap OUT(9)={V01 V02 V13 V52 V53 V10 V03 V09 V08} + ByrefExposed + GcHeap BB18 IN (9)={V01 V02 V13 V52 V53 V10 V03 V09 V08} + ByrefExposed + GcHeap OUT(10)={V01 V02 V13 V52 V53 V10 V03 V09 V32 V08} + ByrefExposed + GcHeap BB19 IN (9)={V01 V02 V13 V52 V53 V10 V03 V09 V08} + ByrefExposed + GcHeap OUT(10)={V01 V02 V13 V52 V53 V10 V03 V09 V32 V08} + ByrefExposed + GcHeap BB20 IN (10)={V01 V02 V13 V52 V53 V10 V03 V09 V32 V08} + ByrefExposed + GcHeap OUT(10)={V01 V02 V13 V52 V53 V10 V03 V09 V14 V08} + ByrefExposed + GcHeap BB21 IN (10)={V01 V02 V13 V52 V53 V10 V03 V09 V14 V08} + ByrefExposed + GcHeap OUT(10)={V01 V02 V13 V52 V53 V10 V03 V09 V14 V08} + ByrefExposed + GcHeap BB22 IN (2)={V01 V02} + ByrefExposed + GcHeap OUT(0)={ } BB23 IN (10)={V01 V02 V13 V52 V53 V10 V03 V09 V14 V08 } + ByrefExposed + GcHeap OUT(7)={V01 V02 V13 V10 V03 V17 V18} + ByrefExposed + GcHeap BB24 IN (5)={V01 V02 V13 V10 V03} + ByrefExposed + GcHeap OUT(6)={V01 V02 V13 V10 V33 V03} + ByrefExposed + GcHeap BB25 IN (7)={V01 V02 V13 V10 V03 V17 V18} + ByrefExposed + GcHeap OUT(6)={V01 V02 V13 V10 V33 V03 } + ByrefExposed + GcHeap BB26 IN (6)={V01 V02 V13 V10 V33 V03} + ByrefExposed + GcHeap OUT(6)={V01 V02 V13 V10 V19 V03} + ByrefExposed + GcHeap BB27 IN (6)={V01 V02 V13 V10 V19 V03} + ByrefExposed + GcHeap OUT(6)={V01 V02 V13 V10 V19 V03} + ByrefExposed + GcHeap BB28 IN (6)={V01 V02 V13 V10 V19 V03} + ByrefExposed + GcHeap OUT(7)={V01 V02 V13 V10 V19 V20 V21 } + ByrefExposed + GcHeap BB29 IN (7)={V01 V02 V13 V10 V19 V20 V21} + ByrefExposed + GcHeap OUT(7)={V01 V02 V13 V10 V19 V20 V21} + ByrefExposed + GcHeap BB30 IN (4)={V01 V02 V13 V10} + ByrefExposed + GcHeap OUT(1)={ V51 } BB31 IN (6)={V01 V02 V13 V19 V20 V21} + ByrefExposed + GcHeap OUT(6)={V01 V02 V13 V19 V20 V21} + ByrefExposed + GcHeap BB32 IN (6)={V01 V02 V13 V19 V20 V21} + ByrefExposed + GcHeap OUT(6)={V01 V02 V13 V19 V20 V21} + ByrefExposed + GcHeap BB33 IN (6)={V01 V02 V13 V19 V20 V21 } + ByrefExposed + GcHeap OUT(6)={V01 V02 V13 V20 V21 V34} + ByrefExposed + GcHeap BB34 IN (6)={V01 V02 V13 V19 V20 V21 } + ByrefExposed + GcHeap OUT(6)={V01 V02 V13 V20 V21 V34} + ByrefExposed + GcHeap BB35 IN (6)={V01 V02 V13 V20 V21 V34 } + ByrefExposed + GcHeap OUT(8)={V01 V02 V13 V24 V20 V25 V26 V22} + ByrefExposed + GcHeap BB36 IN (8)={V01 V02 V13 V24 V20 V25 V26 V22} + ByrefExposed + GcHeap OUT(7)={V01 V02 V13 V24 V20 V29 V22} + ByrefExposed + GcHeap BB37 IN (7)={V01 V02 V13 V24 V20 V29 V22} + ByrefExposed + GcHeap OUT(8)={V01 V02 V13 V24 V20 V29 V37 V22} + ByrefExposed + GcHeap BB38 IN (7)={V01 V02 V13 V24 V20 V29 V22} + ByrefExposed + GcHeap OUT(8)={V01 V02 V13 V24 V20 V29 V37 V22} + ByrefExposed + GcHeap BB39 IN (8)={V01 V02 V13 V24 V20 V29 V37 V22} + ByrefExposed + GcHeap OUT(7)={V01 V02 V13 V24 V20 V25 V22} + ByrefExposed + GcHeap BB40 IN (7)={V01 V02 V13 V24 V20 V25 V22 } + ByrefExposed + GcHeap OUT(6)={V01 V02 V13 V25 V22 V27} + ByrefExposed + GcHeap BB41 IN (5)={V01 V02 V25 V22 V27} + ByrefExposed + GcHeap OUT(5)={V01 V02 V25 V36 V27} + ByrefExposed + GcHeap BB42 IN (5)={V01 V02 V13 V25 V27} + ByrefExposed + GcHeap OUT(5)={V01 V02 V25 V36 V27} + ByrefExposed + GcHeap BB43 IN (5)={V01 V02 V25 V36 V27} + ByrefExposed + GcHeap OUT(1)={ V51 } BB44 IN (1)={V51} OUT(0)={ } top level assign removing stmt with no side effects Removing statement STMT00010 (IL 0x03F...0x040) N003 ( 5, 4) [000041] -A------R--- * ASG int N002 ( 3, 2) [000040] D------N---- +--* LCL_VAR int V07 loc4 N001 ( 1, 1) [000039] ------------ \--* LCL_VAR int V41 tmp11 in BB10 as useless: top level assign removing stmt with no side effects Removing statement STMT00009 (IL 0x03D...0x03E) N003 ( 5, 4) [000038] -A------R--- * ASG int N002 ( 3, 2) [000037] D------N---- +--* LCL_VAR int V06 loc3 N001 ( 1, 1) [000036] ------------ \--* CNS_INT int 0 in BB10 as useless: top level assign removing stmt with no side effects Removing statement STMT00007 (IL ???... ???) N003 ( 5, 4) [000031] -A------R--- * ASG int N002 ( 3, 2) [000030] D------N---- +--* LCL_VAR int V04 loc1 N001 ( 1, 1) [000441] ------------ \--* LCL_VAR int V41 tmp11 in BB10 as useless: top level assign removing stmt with no side effects Removing statement STMT00060 (IL ???...0x1F2) N003 ( 7, 5) [000267] -A------R--- * ASG int N002 ( 3, 2) [000266] D------N---- +--* LCL_VAR int V28 loc25 N001 ( 3, 2) [000265] ------------ \--* LCL_VAR int V36 tmp6 in BB43 as useless: *************** In optRemoveRedundantZeroInits() *************** In SsaBuilder::InsertPhiFunctions() Inserting phi functions: Added PHI definition for V51 at start of BB44. Added PHI definition for V36 at start of BB43. Added PHI definition for V24 at start of BB40. Added PHI definition for V25 at start of BB40. Added PHI definition for V37 at start of BB39. Added PHI definition for V34 at start of BB35. Added PHI definition for V21 at start of BB32. Inserting phi definition for ByrefExposed at start of BB28. Inserting phi definition for GcHeap at start of BB28. Added PHI definition for V33 at start of BB26. Inserting phi definition for ByrefExposed at start of BB23. Inserting phi definition for GcHeap at start of BB23. Added PHI definition for V32 at start of BB20. Inserting phi definition for ByrefExposed at start of BB14. Inserting phi definition for GcHeap at start of BB14. Added PHI definition for V41 at start of BB10. Added PHI definition for V39 at start of BB07. *************** In SsaBuilder::RenameVariables() After fgSsaBuild: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0056] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..00D)-> BB04 ( cond ) i label target idxlen BB03 [0001] 1 BB02 0.50 [00D..017) (return) i hascall gcsafe BB04 [0002] 1 BB02 0.50 [017..065)-> BB06 ( cond ) i label target hascall gcsafe BB05 [0038] 1 BB04 0.50 [020..021)-> BB07 (always) i gcsafe BB06 [0039] 1 BB04 0.50 [020..021) i label target gcsafe BB07 [0040] 2 BB05,BB06 0.50 [000..000)-> BB09 ( cond ) i internal label target gcsafe idxlen BB08 [0043] 1 BB07 0.50 [000..000)-> BB10 (always) i internal gcsafe BB09 [0044] 1 BB07 0.50 [000..000) i internal label target gcsafe BB10 [0045] 2 BB08,BB09 0.50 [???..???)-> BB14 ( cond ) i internal label target hascall gcsafe idxlen BB11 [0003] 1 BB10 0.50 [065..070)-> BB13 ( cond ) i hascall gcsafe BB12 [0004] 1 BB11 0.50 [070..07A) (return) i hascall gcsafe BB13 [0005] 1 BB11 0.50 [07A..082) i label target hascall gcsafe BB14 [0006] 2 BB10,BB13 0.50 [082..092)-> BB16 ( cond ) i label target hascall gcsafe BB15 [0007] 1 BB14 0.50 [092..096)-> BB17 ( cond ) i gcsafe BB16 [0008] 2 BB14,BB15 0.50 [096..0A7)-> BB44 (always) i label target hascall gcsafe BB17 [0009] 1 BB15 0.50 [0A7..0B0)-> BB19 ( cond ) i label target gcsafe BB18 [0010] 1 BB17 0.50 [0B0..0B4)-> BB20 (always) i gcsafe BB19 [0011] 1 BB17 0.50 [0B4..0BE) i label target gcsafe BB20 [0012] 2 BB18,BB19 0.50 [0BE..0C4)-> BB23 ( cond ) i label target gcsafe BB21 [0013] 1 BB20 0.50 [0C4..0D9)-> BB23 ( cond ) i hascall gcsafe idxlen BB22 [0014] 1 BB21 0.50 [0D9..0E3) (return) i hascall gcsafe BB23 [0015] 2 BB20,BB21 0.50 [0E3..117)-> BB25 ( cond ) i label target hascall gcsafe BB24 [0016] 1 BB23 0.50 [117..11A)-> BB26 (always) i gcsafe BB25 [0017] 1 BB23 0.50 [11A..11F) i label target gcsafe BB26 [0018] 2 BB24,BB25 0.50 [11F..126)-> BB28 ( cond ) i label target gcsafe BB27 [0019] 1 BB26 0.50 [126..12F) i hascall gcsafe BB28 [0020] 2 BB26,BB27 0.50 [12F..13E)-> BB32 ( cond ) i label target gcsafe BB29 [0021] 1 BB28 0.50 [13E..144)-> BB31 ( cond ) i gcsafe BB30 [0022] 1 BB29 0.50 [144..155)-> BB44 (always) i hascall gcsafe BB31 [0023] 1 BB29 0.50 [155..15C) i label target gcsafe BB32 [0024] 2 BB28,BB31 0.50 [15C..167)-> BB34 ( cond ) i label target hascall gcsafe BB33 [0025] 1 BB32 0.50 [167..16B)-> BB35 (always) i gcsafe BB34 [0026] 1 BB32 0.50 [16B..16F) i label target gcsafe BB35 [0027] 2 BB33,BB34 0.50 [16F..1A4)-> BB40 ( cond ) i label target hascall gcsafe BB36 [0028] 1 BB35 0.50 [1A4..1AF)-> BB38 ( cond ) i gcsafe BB37 [0029] 1 BB36 0.50 [1AF..1C3)-> BB39 (always) i gcsafe BB38 [0030] 1 BB36 0.50 [1C3..1C4) i label target gcsafe BB39 [0031] 2 BB37,BB38 0.50 [1C4..1D0) i label target gcsafe BB40 [0032] 2 BB35,BB39 0.50 [1D0..1E7)-> BB42 ( cond ) i label target hascall gcsafe BB41 [0033] 1 BB40 0.50 [1E7..1EE)-> BB43 (always) i gcsafe BB42 [0034] 1 BB40 0.50 [1EE..1F2) i label target gcsafe BB43 [0035] 2 BB41,BB42 0.50 [1F2..202) i label target hascall gcsafe BB44 [0054] 3 BB16,BB30,BB43 0.50 [???..???) (return) keep internal target gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} ***** BB01 STMT00111 (IL ???... ???) N011 ( 7, 7) [000540] -A---------- * COMMA void N004 ( 3, 3) [000533] -A------R--- +--* ASG ref N003 ( 1, 1) [000530] D------N---- | +--* LCL_VAR ref V52 tmp22 d:2 N002 ( 3, 2) [000532] n----------- | \--* IND ref N001 ( 1, 1) [000531] ------------ | \--* LCL_VAR byref V00 arg0 u:1 Zero Fseq[Mantissa] N010 ( 4, 4) [000539] -A------R--- \--* ASG int N009 ( 1, 1) [000534] D------N---- +--* LCL_VAR int V53 tmp23 d:2 N008 ( 4, 4) [000538] n----------- \--* IND int N007 ( 2, 2) [000537] -------N---- \--* ADD byref N005 ( 1, 1) [000535] ------------ +--* LCL_VAR byref V00 arg0 u:1 (last use) N006 ( 1, 1) [000536] ------------ \--* CNS_INT long 8 Fseq[Exponent] ------------ BB02 [000..00D) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00000 (IL 0x000...0x00B) N005 ( 7, 7) [000006] ---XG------- * JTRUE void N004 ( 5, 5) [000005] J--XG--N---- \--* NE int N002 ( 3, 3) [000003] ---XG------- +--* ARR_LENGTH int N001 ( 1, 1) [000002] ------------ | \--* LCL_VAR ref V52 tmp22 u:2 N003 ( 1, 1) [000004] ------------ \--* CNS_INT int 0 ------------ BB03 [00D..017) (return), preds={BB02} succs={} ***** BB03 STMT00087 (IL 0x00D...0x014) N006 ( 25, 13) [000403] -ACXG---R--- * ASG long N005 ( 3, 2) [000402] *--X---N---- +--* IND long N004 ( 1, 1) [000399] ------------ | \--* LCL_VAR byref V02 arg2 u:1 (last use) N003 ( 21, 10) [000401] --CXG------- \--* CALLV ind long FloatingPointType.get_Zero N002 ( 1, 1) [000400] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 (last use) ***** BB03 STMT00107 (IL ???... ???) N002 ( 2, 2) [000520] ------------ * RETURN int N001 ( 1, 1) [000404] ------------ \--* CNS_INT int 1 ------------ BB04 [017..065) -> BB06 (cond), preds={BB02} succs={BB05,BB06} ***** BB04 STMT00002 (IL ???... ???) N010 ( 30, 19) [000013] -ACXG---R--- * ASG int N009 ( 3, 2) [000012] D------N---- +--* LCL_VAR int V03 loc0 d:2 N008 ( 26, 16) [000011] --CXG------- \--* ADD int N006 ( 24, 14) [000409] --CXG------- +--* CAST int <- ushort <- int N005 ( 23, 12) [000408] --CXG------- | \--* ADD int N003 ( 21, 10) [000406] --CXG------- | +--* CALLV ind int FloatingPointType.get_DenormalMantissaBits N002 ( 1, 1) [000007] ------------ this in rcx | | \--* LCL_VAR ref V01 arg1 u:1 N004 ( 1, 1) [000407] ------------ | \--* CNS_INT int 1 N007 ( 1, 1) [000010] ------------ \--* CNS_INT int 1 ***** BB04 STMT00092 (IL 0x020... ???) N003 ( 5, 4) [000424] -A--G---R--- * ASG int N002 ( 3, 2) [000423] D------N---- +--* LCL_VAR int V40 tmp10 d:2 N001 ( 1, 1) [000017] ------------ \--* LCL_VAR int V53 tmp23 u:2 ***** BB04 STMT00089 (IL 0x020... ???) N004 ( 5, 5) [000414] ------------ * JTRUE void N003 ( 3, 3) [000413] J------N---- \--* LE int N001 ( 1, 1) [000412] ------------ +--* LCL_VAR int V53 tmp23 u:2 N002 ( 1, 1) [000411] ------------ \--* CNS_INT int 0 ------------ BB05 [020..021) -> BB07 (always), preds={BB04} succs={BB07} ***** BB05 STMT00091 (IL 0x020... ???) N003 ( 7, 5) [000421] -A------R--- * ASG int N002 ( 3, 2) [000420] D------N---- +--* LCL_VAR int V39 tmp9 d:4 N001 ( 3, 2) [000419] ------------ \--* LCL_VAR int V40 tmp10 u:2 (last use) ------------ BB06 [020..021), preds={BB04} succs={BB07} ***** BB06 STMT00090 (IL 0x020... ???) N003 ( 5, 4) [000417] -A------R--- * ASG int N002 ( 3, 2) [000416] D------N---- +--* LCL_VAR int V39 tmp9 d:3 N001 ( 1, 1) [000415] ------------ \--* CNS_INT int 0 ------------ BB07 [000..000) -> BB09 (cond), preds={BB05,BB06} succs={BB08,BB09} ***** BB07 STMT00122 (IL ???... ???) N005 ( 0, 0) [000886] -A------R--- * ASG int N004 ( 0, 0) [000884] D------N---- +--* LCL_VAR int V39 tmp9 d:2 N003 ( 0, 0) [000885] ------------ \--* PHI int N001 ( 0, 0) [000909] ------------ pred BB05 +--* PHI_ARG int V39 tmp9 u:4 N002 ( 0, 0) [000908] ------------ pred BB06 \--* PHI_ARG int V39 tmp9 u:3 ***** BB07 STMT00004 (IL ???... ???) N003 ( 3, 3) [000021] -A------R--- * ASG int N002 ( 1, 1) [000020] D------N---- +--* LCL_VAR int V31 tmp1 d:2 N001 ( 3, 2) [000422] ------------ \--* LCL_VAR int V39 tmp9 u:2 ***** BB07 STMT00096 (IL ???... ???) N004 ( 3, 3) [000443] -A-XG---R--- * ASG int N003 ( 1, 1) [000442] D------N---- +--* LCL_VAR int V42 tmp12 d:2 N002 ( 3, 3) [000429] ---XG------- \--* ARR_LENGTH int N001 ( 1, 1) [000428] ------------ \--* LCL_VAR ref V52 tmp22 u:2 ***** BB07 STMT00093 (IL ???... ???) N004 ( 7, 6) [000433] ------------ * JTRUE void N003 ( 5, 4) [000432] N------N-U-- \--* LE int N001 ( 3, 2) [000023] ------------ +--* LCL_VAR int V39 tmp9 u:2 (last use) N002 ( 1, 1) [000431] ------------ \--* LCL_VAR int V42 tmp12 u:2 ------------ BB08 [000..000) -> BB10 (always), preds={BB07} succs={BB10} ***** BB08 STMT00095 (IL ???... ???) N003 ( 1, 3) [000440] -A------R--- * ASG int N002 ( 1, 1) [000439] D------N---- +--* LCL_VAR int V41 tmp11 d:4 N001 ( 1, 1) [000438] ------------ \--* LCL_VAR int V42 tmp12 u:2 (last use) ------------ BB09 [000..000), preds={BB07} succs={BB10} ***** BB09 STMT00094 (IL ???... ???) N003 ( 1, 3) [000436] -A------R--- * ASG int N002 ( 1, 1) [000435] D------N---- +--* LCL_VAR int V41 tmp11 d:3 N001 ( 1, 1) [000434] ------------ \--* LCL_VAR int V31 tmp1 u:2 ------------ BB10 [???..???) -> BB14 (cond), preds={BB08,BB09} succs={BB11,BB14} ***** BB10 STMT00121 (IL ???... ???) N005 ( 0, 0) [000883] -A------R--- * ASG int N004 ( 0, 0) [000881] D------N---- +--* LCL_VAR int V41 tmp11 d:2 N003 ( 0, 0) [000882] ------------ \--* PHI int N001 ( 0, 0) [000907] ------------ pred BB08 +--* PHI_ARG int V41 tmp11 u:4 N002 ( 0, 0) [000906] ------------ pred BB09 \--* PHI_ARG int V41 tmp11 u:3 ***** BB10 STMT00008 (IL ???...0x03C) N005 ( 7, 6) [000035] -A------R--- * ASG int N004 ( 3, 2) [000034] D------N---- +--* LCL_VAR int V05 loc2 d:2 N003 ( 3, 3) [000033] ------------ \--* SUB int N001 ( 1, 1) [000022] ------------ +--* LCL_VAR int V31 tmp1 u:2 (last use) N002 ( 1, 1) [000032] ------------ \--* LCL_VAR int V41 tmp11 u:2 ***** BB10 STMT00011 (IL 0x042...0x044) N003 ( 5, 4) [000044] -A------R--- * ASG int N002 ( 3, 2) [000043] D------N---- +--* LCL_VAR int V08 loc5 d:2 N001 ( 1, 1) [000042] ------------ \--* LCL_VAR int V41 tmp11 u:2 ***** BB10 STMT00013 (IL ???... ???) N004 ( 7, 6) [000050] -A-XG---R--- * ASG int N003 ( 3, 2) [000049] D------N---- +--* LCL_VAR int V09 loc6 d:2 N002 ( 3, 3) [000448] ---XG------- \--* ARR_LENGTH int N001 ( 1, 1) [000447] ------------ \--* LCL_VAR ref V52 tmp22 u:2 ***** BB10 STMT00014 (IL 0x04F...0x054) N005 ( 5, 4) [000055] -A------R--- * ASG int N004 ( 1, 1) [000054] D------N---- +--* LCL_VAR int V10 loc7 d:2 N003 ( 5, 4) [000053] ------------ \--* SUB int N001 ( 3, 2) [000051] ------------ +--* LCL_VAR int V09 loc6 u:2 N002 ( 1, 1) [000052] ------------ \--* LCL_VAR int V41 tmp11 u:2 ***** BB10 STMT00016 (IL ???... ???) N028 ( 49, 35) [000059] SACXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger N004 ( 7, 6) [000563] -A------R-L- arg0 SETUP +--* ASG long N003 ( 3, 2) [000562] D------N---- | +--* LCL_VAR long V75 tmp45 d:2 N002 ( 3, 3) [000064] ------------ | \--* ADDR long N001 ( 3, 2) [000063] ----G--N---- | \--* LCL_VAR struct(AX)(P) V11 loc8 | \--* ref V11._bits (offs=0x00) -> V54 tmp24 | \--* int V11._sign (offs=0x08) -> V55 tmp25 N020 ( 14, 13) [000561] -A--------L- arg1 SETUP +--* COMMA void N013 ( 8, 7) [000554] -A---------- | +--* COMMA void N008 ( 3, 3) [000549] -A------R--- | | +--* ASG byref N007 ( 1, 1) [000548] D------N---- | | | +--* LCL_VAR byref V74 tmp44 d:2 N006 ( 3, 3) [000546] ------------ | | | \--* ADDR byref N005 ( 3, 2) [000547] -------N---- | | | \--* LCL_VAR struct(AX) V73 tmp43 N012 ( 5, 4) [000553] -A---------- | | \--* ASG ref N010 ( 3, 2) [000551] *------N---- | | +--* IND ref N009 ( 1, 1) [000550] ------------ | | | \--* LCL_VAR byref V74 tmp44 u:2 Zero Fseq[Mantissa] N011 ( 1, 1) [000552] -------N---- | | \--* LCL_VAR ref V52 tmp22 u:2 N019 ( 6, 6) [000560] -A---------- | \--* ASG int N017 ( 4, 4) [000558] *------N---- | +--* IND int N016 ( 2, 2) [000557] -------N---- | | \--* ADD byref N014 ( 1, 1) [000555] ------------ | | +--* LCL_VAR byref V74 tmp44 u:2 (last use) N015 ( 1, 1) [000556] ------------ | | \--* CNS_INT long 8 Fseq[Exponent] N018 ( 1, 1) [000559] -------N---- | \--* LCL_VAR int V53 tmp23 u:2 N023 ( 3, 2) [000564] ------------ arg0 in rcx +--* LCL_VAR long V75 tmp45 u:2 (last use) N025 ( 3, 3) [000566] ------------ arg1 in rdx +--* ADDR byref N024 ( 3, 2) [000565] -------N---- | \--* LCL_VAR struct(AX) V73 tmp43 N026 ( 1, 1) [000058] ------------ arg3 in r9 +--* LCL_VAR int V41 tmp11 u:2 (last use) N027 ( 1, 1) [000057] ------------ arg2 in r8 \--* CNS_INT int 0 ***** BB10 STMT00017 (IL 0x061...0x063) N004 ( 7, 6) [000068] ------------ * JTRUE void N003 ( 5, 4) [000067] N------N---- \--* EQ int N001 ( 3, 2) [000065] ------------ +--* LCL_VAR int V05 loc2 u:2 N002 ( 1, 1) [000066] ------------ \--* CNS_INT int 0 ------------ BB11 [065..070) -> BB13 (cond), preds={BB10} succs={BB12,BB13} ***** BB11 STMT00083 (IL ???... ???) N008 ( 23, 17) [000387] --CXG------- * JTRUE void N007 ( 21, 15) [000386] J-CXG--N---- \--* GE int N004 ( 16, 10) [000385] --CXG------- +--* CAST long <- int N003 ( 15, 8) [000383] --CXG------- | \--* CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent N002 ( 1, 1) [000382] ------------ this in rcx | \--* LCL_VAR ref V01 arg1 u:1 N006 ( 4, 4) [000381] ---------U-- \--* CAST long <- ulong <- uint N005 ( 3, 2) [000380] ------------ \--* LCL_VAR int V05 loc2 u:2 ------------ BB12 [070..07A) (return), preds={BB11} succs={} ***** BB12 STMT00085 (IL 0x070...0x077) N006 ( 25, 13) [000396] -ACXG---R--- * ASG long N005 ( 3, 2) [000395] *--X---N---- +--* IND long N004 ( 1, 1) [000392] ------------ | \--* LCL_VAR byref V02 arg2 u:1 (last use) N003 ( 21, 10) [000394] --CXG------- \--* CALLV ind long FloatingPointType.get_Infinity N002 ( 1, 1) [000393] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 (last use) ***** BB12 STMT00108 (IL ???... ???) N002 ( 2, 2) [000521] ------------ * RETURN int N001 ( 1, 1) [000397] ------------ \--* CNS_INT int 3 ------------ BB13 [07A..082), preds={BB11} succs={BB14} ***** BB13 STMT00084 (IL 0x07A...0x07D) N006 ( 20, 12) [000391] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen N004 ( 3, 3) [000389] ------------ arg0 in rcx +--* ADDR long N003 ( 3, 2) [000388] ----G--N---- | \--* LCL_VAR struct(AX)(P) V11 loc8 | \--* ref V11._bits (offs=0x00) -> V54 tmp24 | \--* int V11._sign (offs=0x08) -> V55 tmp25 N005 ( 3, 2) [000390] ------------ arg1 in rdx \--* LCL_VAR int V05 loc2 u:2 (last use) ------------ BB14 [082..092) -> BB16 (cond), preds={BB10,BB13} succs={BB15,BB16} ***** BB14 STMT00019 (IL ???... ???) N023 ( 41, 28) [000077] -ACXG---R--- * ASG int N022 ( 1, 1) [000076] D------N---- +--* LCL_VAR int V13 loc10 d:2 N021 ( 41, 28) [000072] -ACXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits N016 ( 18, 15) [000591] -A--G-----L- arg0 SETUP +--* COMMA void N009 ( 10, 8) [000584] -A--G------- | +--* COMMA void N004 ( 3, 3) [000579] -A------R--- | | +--* ASG byref N003 ( 1, 1) [000578] D------N---- | | | +--* LCL_VAR byref V77 tmp47 d:2 N002 ( 3, 3) [000576] ------------ | | | \--* ADDR byref N001 ( 3, 2) [000577] -------N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 N008 ( 7, 5) [000583] -A--G------- | | \--* ASG ref N006 ( 3, 2) [000581] *------N---- | | +--* IND ref N005 ( 1, 1) [000580] ------------ | | | \--* LCL_VAR byref V77 tmp47 u:2 Zero Fseq[_bits] N007 ( 3, 2) [000582] ----G--N---- | | \--* LCL_VAR ref (AX) V54 tmp24 N015 ( 8, 7) [000590] -A--G------- | \--* ASG int N013 ( 4, 4) [000588] *------N---- | +--* IND int N012 ( 2, 2) [000587] -------N---- | | \--* ADD byref N010 ( 1, 1) [000585] ------------ | | +--* LCL_VAR byref V77 tmp47 u:2 (last use) N011 ( 1, 1) [000586] ------------ | | \--* CNS_INT long 8 Fseq[_sign] N014 ( 3, 2) [000589] ----G--N---- | \--* LCL_VAR int (AX) V55 tmp25 N019 ( 3, 3) [000593] ------------ arg0 in rcx +--* ADDR byref N018 ( 3, 2) [000592] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 N020 ( 3, 3) [000071] ------------ arg1 in rdx \--* LCL_VAR_ADDR long V12 loc9 ***** BB14 STMT00020 (IL 0x08D...0x090) N004 ( 7, 6) [000081] ------------ * JTRUE void N003 ( 5, 4) [000080] N------N-U-- \--* GE int N001 ( 1, 1) [000078] ------------ +--* LCL_VAR int V13 loc10 u:2 N002 ( 3, 2) [000079] ------------ \--* LCL_VAR int V03 loc0 u:2 ------------ BB15 [092..096) -> BB17 (cond), preds={BB14} succs={BB16,BB17} ***** BB15 STMT00022 (IL 0x092...0x094) N004 ( 5, 5) [000094] ------------ * JTRUE void N003 ( 3, 3) [000093] J------N---- \--* NE int N001 ( 1, 1) [000091] ------------ +--* LCL_VAR int V10 loc7 u:2 N002 ( 1, 1) [000092] ------------ \--* CNS_INT int 0 ------------ BB16 [096..0A7) -> BB44 (always), preds={BB14,BB15} succs={BB44} ***** BB16 STMT00021 (IL 0x096...0x0A6) N014 ( 29, 17) [000600] -ACXG---R--- * ASG int N013 ( 1, 1) [000599] D------N---- +--* LCL_VAR int V51 tmp21 d:3 N012 ( 29, 17) [000089] --CXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits N005 ( 1, 1) [000088] ------------ arg4 out+20 +--* LCL_VAR byref V02 arg2 u:1 (last use) N008 ( 6, 3) [000086] N----------- arg2 in r8 +--* NE int N006 ( 1, 1) [000084] ------------ | +--* LCL_VAR int V10 loc7 u:2 (last use) N007 ( 1, 1) [000085] ------------ | \--* CNS_INT int 0 N009 ( 3, 2) [000082] ----G------- arg0 in rcx +--* LCL_VAR ref (AX) V12 loc9 N010 ( 1, 1) [000083] ------------ arg1 in rdx +--* LCL_VAR int V13 loc10 u:2 (last use) N011 ( 1, 1) [000087] ------------ arg3 in r9 \--* LCL_VAR ref V01 arg1 u:1 (last use) ------------ BB17 [0A7..0B0) -> BB19 (cond), preds={BB15} succs={BB18,BB19} ***** BB17 STMT00023 (IL 0x0A7...0x0AE) N004 ( 5, 5) [000100] ----G------- * JTRUE void N003 ( 3, 3) [000099] J---G--N---- \--* LT int N001 ( 1, 1) [000097] ------------ +--* LCL_VAR int V53 tmp23 u:2 N002 ( 1, 1) [000098] ------------ \--* CNS_INT int 0 ------------ BB18 [0B0..0B4) -> BB20 (always), preds={BB17} succs={BB20} ***** BB18 STMT00081 (IL 0x0B0...0x0B2) N003 ( 5, 4) [000378] -A------R--- * ASG int N002 ( 3, 2) [000377] D------N---- +--* LCL_VAR int V32 tmp2 d:4 N001 ( 1, 1) [000376] ------------ \--* LCL_VAR int V10 loc7 u:2 ------------ BB19 [0B4..0BE), preds={BB17} succs={BB20} ***** BB19 STMT00024 (IL 0x0B4...0x0BD) N005 ( 7, 6) [000108] -A--G---R--- * ASG int N004 ( 3, 2) [000107] D------N---- +--* LCL_VAR int V32 tmp2 d:3 N003 ( 3, 3) [000106] ----G------- \--* SUB int N001 ( 1, 1) [000101] ------------ +--* LCL_VAR int V10 loc7 u:2 N002 ( 1, 1) [000104] ------------ \--* LCL_VAR int V53 tmp23 u:2 ------------ BB20 [0BE..0C4) -> BB23 (cond), preds={BB18,BB19} succs={BB21,BB23} ***** BB20 STMT00120 (IL ???... ???) N005 ( 0, 0) [000880] -A------R--- * ASG int N004 ( 0, 0) [000878] D------N---- +--* LCL_VAR int V32 tmp2 d:2 N003 ( 0, 0) [000879] ------------ \--* PHI int N001 ( 0, 0) [000905] ------------ pred BB18 +--* PHI_ARG int V32 tmp2 u:4 N002 ( 0, 0) [000904] ------------ pred BB19 \--* PHI_ARG int V32 tmp2 u:3 ***** BB20 STMT00025 (IL ???...0x0BE) N003 ( 7, 5) [000112] -A------R--- * ASG int N002 ( 3, 2) [000111] D------N---- +--* LCL_VAR int V14 loc11 d:2 N001 ( 3, 2) [000110] ------------ \--* LCL_VAR int V32 tmp2 u:2 (last use) ***** BB20 STMT00026 (IL 0x0C0...0x0C2) N004 ( 5, 5) [000116] ------------ * JTRUE void N003 ( 3, 3) [000115] J------N---- \--* NE int N001 ( 1, 1) [000113] ------------ +--* LCL_VAR int V13 loc10 u:2 N002 ( 1, 1) [000114] ------------ \--* CNS_INT int 0 ------------ BB21 [0C4..0D9) -> BB23 (cond), preds={BB20} succs={BB22,BB23} ***** BB21 STMT00077 (IL ???... ???) N008 ( 13, 13) [000363] -A-XG---R--- * ASG long N007 ( 3, 2) [000362] D------N---- +--* LCL_VAR long V38 tmp8 d:2 N006 ( 9, 10) [000359] ---XG---R--- \--* SUB long N005 ( 4, 4) [000353] ---------U-- +--* CAST long <- ulong <- uint N004 ( 3, 2) [000352] ------------ | \--* LCL_VAR int V14 loc11 u:2 N003 ( 4, 5) [000358] ---XG------- \--* CAST long <- int N002 ( 3, 3) [000456] ---XG------- \--* ARR_LENGTH int N001 ( 1, 1) [000455] ------------ \--* LCL_VAR ref V52 tmp22 u:2 ***** BB21 STMT00078 (IL ???... ???) N007 ( 22, 15) [000368] --CXG------- * JTRUE void N006 ( 20, 13) [000367] J-CXG--N---- \--* GE int N004 ( 16, 10) [000366] --CXG------- +--* CAST long <- int N003 ( 15, 8) [000361] --CXG------- | \--* CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent N002 ( 1, 1) [000360] ------------ this in rcx | \--* LCL_VAR ref V01 arg1 u:1 N005 ( 3, 2) [000364] ------------ \--* LCL_VAR long V38 tmp8 u:2 (last use) ------------ BB22 [0D9..0E3) (return), preds={BB21} succs={} ***** BB22 STMT00079 (IL 0x0D9...0x0E0) N006 ( 25, 13) [000373] -ACXG---R--- * ASG long N005 ( 3, 2) [000372] *--X---N---- +--* IND long N004 ( 1, 1) [000369] ------------ | \--* LCL_VAR byref V02 arg2 u:1 (last use) N003 ( 21, 10) [000371] --CXG------- \--* CALLV ind long FloatingPointType.get_Zero N002 ( 1, 1) [000370] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 (last use) ***** BB22 STMT00110 (IL ???... ???) N002 ( 2, 2) [000524] ------------ * RETURN int N001 ( 1, 1) [000374] ------------ \--* CNS_INT int 2 ------------ BB23 [0E3..117) -> BB25 (cond), preds={BB20,BB21} succs={BB24,BB25} ***** BB23 STMT00028 (IL ???... ???) N028 ( 53, 37) [000120] SACXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger N004 ( 7, 6) [000623] -A------R-L- arg0 SETUP +--* ASG long N003 ( 3, 2) [000622] D------N---- | +--* LCL_VAR long V79 tmp49 d:2 N002 ( 3, 3) [000125] ------------ | \--* ADDR long N001 ( 3, 2) [000124] ----G--N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 N020 ( 14, 13) [000621] -A--------L- arg1 SETUP +--* COMMA void N013 ( 8, 7) [000614] -A---------- | +--* COMMA void N008 ( 3, 3) [000609] -A------R--- | | +--* ASG byref N007 ( 1, 1) [000608] D------N---- | | | +--* LCL_VAR byref V78 tmp48 d:2 N006 ( 3, 3) [000606] ------------ | | | \--* ADDR byref N005 ( 3, 2) [000607] ----G--N---- | | | \--* LCL_VAR struct(AX) V73 tmp43 N012 ( 5, 4) [000613] -A---------- | | \--* ASG ref N010 ( 3, 2) [000611] *------N---- | | +--* IND ref N009 ( 1, 1) [000610] ------------ | | | \--* LCL_VAR byref V78 tmp48 u:2 Zero Fseq[Mantissa] N011 ( 1, 1) [000612] -------N---- | | \--* LCL_VAR ref V52 tmp22 u:2 (last use) N019 ( 6, 6) [000620] -A---------- | \--* ASG int N017 ( 4, 4) [000618] *------N---- | +--* IND int N016 ( 2, 2) [000617] -------N---- | | \--* ADD byref N014 ( 1, 1) [000615] ------------ | | +--* LCL_VAR byref V78 tmp48 u:2 (last use) N015 ( 1, 1) [000616] ------------ | | \--* CNS_INT long 8 Fseq[Exponent] N018 ( 1, 1) [000619] -------N---- | \--* LCL_VAR int V53 tmp23 u:2 (last use) N023 ( 3, 2) [000624] ------------ arg0 in rcx +--* LCL_VAR long V79 tmp49 u:2 (last use) N025 ( 3, 3) [000626] ------------ arg1 in rdx +--* ADDR byref N024 ( 3, 2) [000625] -------N---- | \--* LCL_VAR struct(AX) V73 tmp43 N026 ( 3, 2) [000118] ------------ arg2 in r8 +--* LCL_VAR int V08 loc5 u:2 (last use) N027 ( 3, 2) [000119] ------------ arg3 in r9 \--* LCL_VAR int V09 loc6 u:2 (last use) ***** BB23 STMT00029 (IL 0x0EF...0x0F4) N005 ( 17, 21) [000133] H-CXG------- * CALL help long HELPER.CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE N003 ( 2, 10) [000131] ------------ arg0 in rcx +--* CNS_INT long 0x7ff815262aa0 N004 ( 1, 4) [000132] ------------ arg1 in rdx \--* CNS_INT int 173 ***** BB23 STMT00030 (IL ???... ???) N018 ( 21, 26) [000649] -A-XG------- * COMMA void N011 ( 13, 19) [000642] -A-XG------- +--* COMMA void N006 ( 6, 14) [000637] -A--G---R--- | +--* ASG byref N005 ( 1, 1) [000636] D------N---- | | +--* LCL_VAR byref V80 tmp50 d:2 N004 ( 6, 14) [000632] ----G------- | | \--* ADD byref N002 ( 4, 12) [000633] n---G------- | | +--* IND ref N001 ( 2, 10) [000634] I----------- | | | \--* CNS_INT(h) long 0xd1ffab1e static Fseq[BigOne] N003 ( 1, 1) [000635] ------------ | | \--* CNS_INT long 8 Fseq[#FirstElem] N010 ( 7, 5) [000641] -A-XG---R--- | \--* ASG ref N009 ( 3, 2) [000638] D---G--N---- | +--* LCL_VAR ref (AX) V58 tmp28 N008 ( 3, 2) [000640] ---X-------- | \--* IND ref N007 ( 1, 1) [000639] ------------ | \--* LCL_VAR byref V80 tmp50 u:2 Zero Fseq[_bits] N017 ( 8, 7) [000648] -A-XG---R--- \--* ASG int N016 ( 3, 2) [000643] D---G--N---- +--* LCL_VAR int (AX) V59 tmp29 N015 ( 4, 4) [000647] ---X-------- \--* IND int N014 ( 2, 2) [000646] -------N---- \--* ADD byref N012 ( 1, 1) [000644] ------------ +--* LCL_VAR byref V80 tmp50 u:2 (last use) N013 ( 1, 1) [000645] ------------ \--* CNS_INT long 8 Fseq[_sign] ***** BB23 STMT00031 (IL 0x0F6...0x106) N006 ( 20, 12) [000141] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen N004 ( 3, 3) [000139] ------------ arg0 in rcx +--* ADDR long N003 ( 3, 2) [000138] ----G--N---- | \--* LCL_VAR struct(AX)(P) V16 loc13 | \--* ref V16._bits (offs=0x00) -> V58 tmp28 | \--* int V16._sign (offs=0x08) -> V59 tmp29 N005 ( 3, 2) [000140] ------------ arg1 in rdx \--* LCL_VAR int V14 loc11 u:2 (last use) ***** BB23 STMT00099 (IL 0x0FF... ???) N007 ( 14, 10) [000658] -A--G------- * COMMA void N003 ( 7, 5) [000654] -A--G---R--- +--* ASG ref N002 ( 3, 2) [000652] D------N---- | +--* LCL_VAR ref V64 tmp34 d:2 N001 ( 3, 2) [000653] ----G--N---- | \--* LCL_VAR ref (AX) V56 tmp26 N006 ( 7, 5) [000657] -A--G---R--- \--* ASG int N005 ( 3, 2) [000655] D------N---- +--* LCL_VAR int V65 tmp35 d:2 N004 ( 3, 2) [000656] ----G--N---- \--* LCL_VAR int (AX) V57 tmp27 ***** BB23 STMT00098 (IL 0x0FF... ???) N023 ( 45, 31) [000468] -ACXG---R--- * ASG int N022 ( 3, 2) [000467] D------N---- +--* LCL_VAR int V43 tmp13 d:2 N021 ( 41, 28) [000463] -ACXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits N016 ( 18, 15) [000677] -A--------L- arg0 SETUP +--* COMMA void N009 ( 10, 8) [000670] -A---------- | +--* COMMA void N004 ( 3, 3) [000665] -A------R--- | | +--* ASG byref N003 ( 1, 1) [000664] D------N---- | | | +--* LCL_VAR byref V81 tmp51 d:2 N002 ( 3, 3) [000662] ------------ | | | \--* ADDR byref N001 ( 3, 2) [000663] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 N008 ( 7, 5) [000669] -A---------- | | \--* ASG ref N006 ( 3, 2) [000667] *------N---- | | +--* IND ref N005 ( 1, 1) [000666] ------------ | | | \--* LCL_VAR byref V81 tmp51 u:2 Zero Fseq[_bits] N007 ( 3, 2) [000668] -------N---- | | \--* LCL_VAR ref V64 tmp34 u:2 (last use) N015 ( 8, 7) [000676] -A---------- | \--* ASG int N013 ( 4, 4) [000674] *------N---- | +--* IND int N012 ( 2, 2) [000673] -------N---- | | \--* ADD byref N010 ( 1, 1) [000671] ------------ | | +--* LCL_VAR byref V81 tmp51 u:2 (last use) N011 ( 1, 1) [000672] ------------ | | \--* CNS_INT long 8 Fseq[_sign] N014 ( 3, 2) [000675] -------N---- | \--* LCL_VAR int V65 tmp35 u:2 (last use) N019 ( 3, 3) [000679] ------------ arg0 in rcx +--* ADDR byref N018 ( 3, 2) [000678] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 N020 ( 3, 3) [000462] ------------ arg1 in rdx \--* LCL_VAR_ADDR long V45 tmp15 ***** BB23 STMT00100 (IL 0x0FF... ???) N003 ( 5, 4) [000475] -A--G---R--- * ASG ref N002 ( 3, 2) [000474] D---G--N---- +--* LCL_VAR ref (AX) V45 tmp15 N001 ( 1, 1) [000473] ------------ \--* CNS_INT ref null ***** BB23 STMT00033 (IL ???... ???) N003 ( 7, 5) [000148] -A------R--- * ASG int N002 ( 3, 2) [000147] D------N---- +--* LCL_VAR int V17 loc14 d:2 N001 ( 3, 2) [000469] ------------ \--* LCL_VAR int V43 tmp13 u:2 ***** BB23 STMT00103 (IL 0x108... ???) N007 ( 14, 10) [000687] -A--G------- * COMMA void N003 ( 7, 5) [000683] -A--G---R--- +--* ASG ref N002 ( 3, 2) [000681] D------N---- | +--* LCL_VAR ref V66 tmp36 d:2 N001 ( 3, 2) [000682] ----G--N---- | \--* LCL_VAR ref (AX) V58 tmp28 N006 ( 7, 5) [000686] -A--G---R--- \--* ASG int N005 ( 3, 2) [000684] D------N---- +--* LCL_VAR int V67 tmp37 d:2 N004 ( 3, 2) [000685] ----G--N---- \--* LCL_VAR int (AX) V59 tmp29 ***** BB23 STMT00102 (IL 0x108... ???) N023 ( 45, 31) [000486] -ACXG---R--- * ASG int N022 ( 3, 2) [000485] D------N---- +--* LCL_VAR int V46 tmp16 d:2 N021 ( 41, 28) [000481] -ACXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits N016 ( 18, 15) [000706] -A--------L- arg0 SETUP +--* COMMA void N009 ( 10, 8) [000699] -A---------- | +--* COMMA void N004 ( 3, 3) [000694] -A------R--- | | +--* ASG byref N003 ( 1, 1) [000693] D------N---- | | | +--* LCL_VAR byref V82 tmp52 d:2 N002 ( 3, 3) [000691] ------------ | | | \--* ADDR byref N001 ( 3, 2) [000692] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 N008 ( 7, 5) [000698] -A---------- | | \--* ASG ref N006 ( 3, 2) [000696] *------N---- | | +--* IND ref N005 ( 1, 1) [000695] ------------ | | | \--* LCL_VAR byref V82 tmp52 u:2 Zero Fseq[_bits] N007 ( 3, 2) [000697] -------N---- | | \--* LCL_VAR ref V66 tmp36 u:2 (last use) N015 ( 8, 7) [000705] -A---------- | \--* ASG int N013 ( 4, 4) [000703] *------N---- | +--* IND int N012 ( 2, 2) [000702] -------N---- | | \--* ADD byref N010 ( 1, 1) [000700] ------------ | | +--* LCL_VAR byref V82 tmp52 u:2 (last use) N011 ( 1, 1) [000701] ------------ | | \--* CNS_INT long 8 Fseq[_sign] N014 ( 3, 2) [000704] -------N---- | \--* LCL_VAR int V67 tmp37 u:2 (last use) N019 ( 3, 3) [000708] ------------ arg0 in rcx +--* ADDR byref N018 ( 3, 2) [000707] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 N020 ( 3, 3) [000480] ------------ arg1 in rdx \--* LCL_VAR_ADDR long V48 tmp18 ***** BB23 STMT00104 (IL 0x108... ???) N003 ( 5, 4) [000493] -A--G---R--- * ASG ref N002 ( 3, 2) [000492] D---G--N---- +--* LCL_VAR ref (AX) V48 tmp18 N001 ( 1, 1) [000491] ------------ \--* CNS_INT ref null ***** BB23 STMT00035 (IL ???... ???) N003 ( 7, 5) [000155] -A------R--- * ASG int N002 ( 3, 2) [000154] D------N---- +--* LCL_VAR int V18 loc15 d:2 N001 ( 3, 2) [000487] ------------ \--* LCL_VAR int V46 tmp16 u:2 ***** BB23 STMT00036 (IL 0x111...0x115) N004 ( 9, 7) [000159] ------------ * JTRUE void N003 ( 7, 5) [000158] N------N-U-- \--* GT int N001 ( 3, 2) [000156] ------------ +--* LCL_VAR int V46 tmp16 u:2 (last use) N002 ( 3, 2) [000157] ------------ \--* LCL_VAR int V43 tmp13 u:2 (last use) ------------ BB24 [117..11A) -> BB26 (always), preds={BB23} succs={BB26} ***** BB24 STMT00074 (IL 0x117...0x118) N003 ( 5, 4) [000350] -A------R--- * ASG int N002 ( 3, 2) [000349] D------N---- +--* LCL_VAR int V33 tmp3 d:4 N001 ( 1, 1) [000348] ------------ \--* CNS_INT int 0 ------------ BB25 [11A..11F), preds={BB23} succs={BB26} ***** BB25 STMT00037 (IL 0x11A...0x11E) N005 ( 11, 8) [000164] -A------R--- * ASG int N004 ( 3, 2) [000163] D------N---- +--* LCL_VAR int V33 tmp3 d:3 N003 ( 7, 5) [000162] ------------ \--* SUB int N001 ( 3, 2) [000160] ------------ +--* LCL_VAR int V18 loc15 u:2 (last use) N002 ( 3, 2) [000161] ------------ \--* LCL_VAR int V17 loc14 u:2 (last use) ------------ BB26 [11F..126) -> BB28 (cond), preds={BB24,BB25} succs={BB27,BB28} ***** BB26 STMT00119 (IL ???... ???) N005 ( 0, 0) [000877] -A------R--- * ASG int N004 ( 0, 0) [000875] D------N---- +--* LCL_VAR int V33 tmp3 d:2 N003 ( 0, 0) [000876] ------------ \--* PHI int N001 ( 0, 0) [000903] ------------ pred BB24 +--* PHI_ARG int V33 tmp3 u:4 N002 ( 0, 0) [000902] ------------ pred BB25 \--* PHI_ARG int V33 tmp3 u:3 ***** BB26 STMT00038 (IL ???...0x11F) N003 ( 3, 3) [000168] -A------R--- * ASG int N002 ( 1, 1) [000167] D------N---- +--* LCL_VAR int V19 loc16 d:2 N001 ( 3, 2) [000166] ------------ \--* LCL_VAR int V33 tmp3 u:2 ***** BB26 STMT00039 (IL 0x121...0x124) N004 ( 7, 6) [000172] ------------ * JTRUE void N003 ( 5, 4) [000171] N------N---- \--* EQ int N001 ( 3, 2) [000169] ------------ +--* LCL_VAR int V33 tmp3 u:2 (last use) N002 ( 1, 1) [000170] ------------ \--* CNS_INT int 0 ------------ BB27 [126..12F), preds={BB26} succs={BB28} ***** BB27 STMT00073 (IL 0x126...0x12A) N006 ( 18, 11) [000347] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft N004 ( 3, 3) [000345] ------------ arg0 in rcx +--* ADDR long N003 ( 3, 2) [000344] ----G--N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 N005 ( 1, 1) [000346] ------------ arg1 in rdx \--* LCL_VAR int V19 loc16 u:2 ------------ BB28 [12F..13E) -> BB32 (cond), preds={BB26,BB27} succs={BB29,BB32} ***** BB28 STMT00040 (IL 0x12F...0x133) N005 ( 9, 7) [000177] -A------R--- * ASG int N004 ( 3, 2) [000176] D------N---- +--* LCL_VAR int V20 loc17 d:2 N003 ( 5, 4) [000175] ------------ \--* SUB int N001 ( 3, 2) [000173] ------------ +--* LCL_VAR int V03 loc0 u:2 (last use) N002 ( 1, 1) [000174] ------------ \--* LCL_VAR int V13 loc10 u:2 ***** BB28 STMT00041 (IL 0x135...0x137) N003 ( 7, 5) [000180] -A------R--- * ASG int N002 ( 3, 2) [000179] D------N---- +--* LCL_VAR int V21 loc18 d:2 N001 ( 3, 2) [000178] ------------ \--* LCL_VAR int V20 loc17 u:2 ***** BB28 STMT00042 (IL 0x139...0x13C) N004 ( 5, 5) [000184] ------------ * JTRUE void N003 ( 3, 3) [000183] N------N---- \--* EQ int N001 ( 1, 1) [000181] ------------ +--* LCL_VAR int V13 loc10 u:2 N002 ( 1, 1) [000182] ------------ \--* CNS_INT int 0 ------------ BB29 [13E..144) -> BB31 (cond), preds={BB28} succs={BB30,BB31} ***** BB29 STMT00070 (IL 0x13E...0x142) N004 ( 7, 6) [000329] ------------ * JTRUE void N003 ( 5, 4) [000328] N------N-U-- \--* LE int N001 ( 1, 1) [000326] ------------ +--* LCL_VAR int V19 loc16 u:2 N002 ( 3, 2) [000327] ------------ \--* LCL_VAR int V21 loc18 u:2 ------------ BB30 [144..155) -> BB44 (always), preds={BB29} succs={BB44} ***** BB30 STMT00072 (IL 0x144...0x154) N014 ( 29, 17) [000717] -ACXG---R--- * ASG int N013 ( 1, 1) [000716] D------N---- +--* LCL_VAR int V51 tmp21 d:5 N012 ( 29, 17) [000342] --CXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits N005 ( 1, 1) [000341] ------------ arg4 out+20 +--* LCL_VAR byref V02 arg2 u:1 (last use) N008 ( 6, 3) [000339] N----------- arg2 in r8 +--* NE int N006 ( 1, 1) [000337] ------------ | +--* LCL_VAR int V10 loc7 u:2 (last use) N007 ( 1, 1) [000338] ------------ | \--* CNS_INT int 0 N009 ( 3, 2) [000335] ----G------- arg0 in rcx +--* LCL_VAR ref (AX) V12 loc9 N010 ( 1, 1) [000336] ------------ arg1 in rdx +--* LCL_VAR int V13 loc10 u:2 (last use) N011 ( 1, 1) [000340] ------------ arg3 in r9 \--* LCL_VAR ref V01 arg1 u:1 (last use) ------------ BB31 [155..15C), preds={BB29} succs={BB32} ***** BB31 STMT00071 (IL 0x155...0x15A) N005 ( 9, 7) [000334] -A------R--- * ASG int N004 ( 3, 2) [000333] D------N---- +--* LCL_VAR int V21 loc18 d:4 N003 ( 5, 4) [000332] ------------ \--* SUB int N001 ( 3, 2) [000330] ------------ +--* LCL_VAR int V21 loc18 u:2 (last use) N002 ( 1, 1) [000331] ------------ \--* LCL_VAR int V19 loc16 u:2 ------------ BB32 [15C..167) -> BB34 (cond), preds={BB28,BB31} succs={BB33,BB34} ***** BB32 STMT00118 (IL ???... ???) N005 ( 0, 0) [000874] -A------R--- * ASG int N004 ( 0, 0) [000872] D------N---- +--* LCL_VAR int V21 loc18 d:3 N003 ( 0, 0) [000873] ------------ \--* PHI int N001 ( 0, 0) [000900] ------------ pred BB31 +--* PHI_ARG int V21 loc18 u:4 N002 ( 0, 0) [000888] ------------ pred BB28 \--* PHI_ARG int V21 loc18 u:2 ***** BB32 STMT00105 (IL 0x15C... ???) N007 ( 14, 10) [000724] -A--G------- * COMMA void N003 ( 7, 5) [000720] -A--G---R--- +--* ASG ref N002 ( 3, 2) [000718] D---G--N---- | +--* LCL_VAR ref (AX) V68 tmp38 N001 ( 3, 2) [000719] ----G--N---- | \--* LCL_VAR ref (AX) V56 tmp26 N006 ( 7, 5) [000723] -A--G---R--- \--* ASG int N005 ( 3, 2) [000721] D---G--N---- +--* LCL_VAR int (AX) V69 tmp39 N004 ( 3, 2) [000722] ----G--N---- \--* LCL_VAR int (AX) V57 tmp27 ***** BB32 STMT00106 (IL 0x15C... ???) N007 ( 14, 10) [000731] -A--G------- * COMMA void N003 ( 7, 5) [000727] -A--G---R--- +--* ASG ref N002 ( 3, 2) [000725] D------N---- | +--* LCL_VAR ref V70 tmp40 d:2 N001 ( 3, 2) [000726] ----G--N---- | \--* LCL_VAR ref (AX) V58 tmp28 N006 ( 7, 5) [000730] -A--G---R--- \--* ASG int N005 ( 3, 2) [000728] D------N---- +--* LCL_VAR int V71 tmp41 d:2 N004 ( 3, 2) [000729] ----G--N---- \--* LCL_VAR int (AX) V59 tmp29 ***** BB32 STMT00044 (IL ???... ???) N027 ( 52, 38) [000195] -ACXG------- * JTRUE void N026 ( 50, 36) [000503] JACXG--N---- \--* LT int N024 ( 48, 34) [000499] -ACXG------- +--* CALL int System.Numerics.BigInteger.CompareTo N004 ( 7, 6) [000752] -A------R-L- this SETUP | +--* ASG byref N003 ( 3, 2) [000751] D------N---- | | +--* LCL_VAR byref V84 tmp54 d:2 N002 ( 3, 3) [000497] ------------ | | \--* ADDR byref N001 ( 3, 2) [000496] ----G--N---- | | \--* LCL_VAR struct(AX)(P) V49 tmp19 | | \--* ref V49._bits (offs=0x00) -> V68 tmp38 | | \--* int V49._sign (offs=0x08) -> V69 tmp39 N020 ( 18, 15) [000750] -A--------L- arg1 SETUP | +--* COMMA void N013 ( 10, 8) [000743] -A---------- | | +--* COMMA void N008 ( 3, 3) [000738] -A------R--- | | | +--* ASG byref N007 ( 1, 1) [000737] D------N---- | | | | +--* LCL_VAR byref V83 tmp53 d:2 N006 ( 3, 3) [000735] ------------ | | | | \--* ADDR byref N005 ( 3, 2) [000736] ----G--N---- | | | | \--* LCL_VAR struct(AX) V76 tmp46 N012 ( 7, 5) [000742] -A---------- | | | \--* ASG ref N010 ( 3, 2) [000740] *------N---- | | | +--* IND ref N009 ( 1, 1) [000739] ------------ | | | | \--* LCL_VAR byref V83 tmp53 u:2 Zero Fseq[_bits] N011 ( 3, 2) [000741] -------N---- | | | \--* LCL_VAR ref V70 tmp40 u:2 (last use) N019 ( 8, 7) [000749] -A---------- | | \--* ASG int N017 ( 4, 4) [000747] *------N---- | | +--* IND int N016 ( 2, 2) [000746] -------N---- | | | \--* ADD byref N014 ( 1, 1) [000744] ------------ | | | +--* LCL_VAR byref V83 tmp53 u:2 (last use) N015 ( 1, 1) [000745] ------------ | | | \--* CNS_INT long 8 Fseq[_sign] N018 ( 3, 2) [000748] -------N---- | | \--* LCL_VAR int V71 tmp41 u:2 (last use) N021 ( 3, 2) [000753] ------------ this in rcx | +--* LCL_VAR byref V84 tmp54 u:2 (last use) N023 ( 3, 3) [000755] ------------ arg1 in rdx | \--* ADDR byref N022 ( 3, 2) [000754] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 N025 ( 1, 1) [000502] ------------ \--* CNS_INT int 0 ------------ BB33 [167..16B) -> BB35 (always), preds={BB32} succs={BB35} ***** BB33 STMT00069 (IL 0x167...0x169) N003 ( 5, 4) [000324] -A------R--- * ASG int N002 ( 3, 2) [000323] D------N---- +--* LCL_VAR int V34 tmp4 d:4 N001 ( 1, 1) [000322] ------------ \--* LCL_VAR int V19 loc16 u:2 (last use) ------------ BB34 [16B..16F), preds={BB32} succs={BB35} ***** BB34 STMT00045 (IL 0x16B...0x16E) N005 ( 7, 6) [000200] -A------R--- * ASG int N004 ( 3, 2) [000199] D------N---- +--* LCL_VAR int V34 tmp4 d:3 N003 ( 3, 3) [000198] ------------ \--* ADD int N001 ( 1, 1) [000196] ------------ +--* LCL_VAR int V19 loc16 u:2 (last use) N002 ( 1, 1) [000197] ------------ \--* CNS_INT int 1 ------------ BB35 [16F..1A4) -> BB40 (cond), preds={BB33,BB34} succs={BB36,BB40} ***** BB35 STMT00117 (IL ???... ???) N005 ( 0, 0) [000871] -A------R--- * ASG int N004 ( 0, 0) [000869] D------N---- +--* LCL_VAR int V34 tmp4 d:2 N003 ( 0, 0) [000870] ------------ \--* PHI int N001 ( 0, 0) [000899] ------------ pred BB33 +--* PHI_ARG int V34 tmp4 u:4 N002 ( 0, 0) [000898] ------------ pred BB34 \--* PHI_ARG int V34 tmp4 u:3 ***** BB35 STMT00046 (IL ???...0x16F) N003 ( 7, 5) [000204] -A------R--- * ASG int N002 ( 3, 2) [000203] D------N---- +--* LCL_VAR int V22 loc19 d:2 N001 ( 3, 2) [000202] ------------ \--* LCL_VAR int V34 tmp4 u:2 (last use) ***** BB35 STMT00047 (IL 0x171...0x18A) N006 ( 20, 12) [000208] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft N004 ( 3, 3) [000206] ------------ arg0 in rcx +--* ADDR long N003 ( 3, 2) [000205] ----G--N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 N005 ( 3, 2) [000207] ------------ arg1 in rdx \--* LCL_VAR int V21 loc18 u:3 (last use) ***** BB35 STMT00048 (IL 0x17A... ???) N045 ( 78, 56) [000213] SACXG------- * CALL void System.Numerics.BigInteger.DivRem N004 ( 7, 6) [000797] -A------R-L- arg0 SETUP +--* ASG long N003 ( 3, 2) [000796] D------N---- | +--* LCL_VAR long V88 tmp58 d:2 N002 ( 3, 3) [000220] ------------ | \--* ADDR long N001 ( 3, 2) [000219] ----G--N---- | \--* LCL_VAR struct(AX)(P) V35 tmp5 | \--* ref V35._bits (offs=0x00) -> V62 tmp32 | \--* int V35._sign (offs=0x08) -> V63 tmp33 N020 ( 18, 15) [000776] -A--G-----L- arg1 SETUP +--* COMMA void N013 ( 10, 8) [000769] -A--G------- | +--* COMMA void N008 ( 3, 3) [000764] -A------R--- | | +--* ASG byref N007 ( 1, 1) [000763] D------N---- | | | +--* LCL_VAR byref V85 tmp55 d:2 N006 ( 3, 3) [000761] ------------ | | | \--* ADDR byref N005 ( 3, 2) [000762] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 N012 ( 7, 5) [000768] -A--G------- | | \--* ASG ref N010 ( 3, 2) [000766] *------N---- | | +--* IND ref N009 ( 1, 1) [000765] ------------ | | | \--* LCL_VAR byref V85 tmp55 u:2 Zero Fseq[_bits] N011 ( 3, 2) [000767] ----G--N---- | | \--* LCL_VAR ref (AX) V56 tmp26 N019 ( 8, 7) [000775] -A--G------- | \--* ASG int N017 ( 4, 4) [000773] *------N---- | +--* IND int N016 ( 2, 2) [000772] -------N---- | | \--* ADD byref N014 ( 1, 1) [000770] ------------ | | +--* LCL_VAR byref V85 tmp55 u:2 (last use) N015 ( 1, 1) [000771] ------------ | | \--* CNS_INT long 8 Fseq[_sign] N018 ( 3, 2) [000774] ----G--N---- | \--* LCL_VAR int (AX) V57 tmp27 N036 ( 18, 15) [000795] -A--G-----L- arg2 SETUP +--* COMMA void N029 ( 10, 8) [000788] -A--G------- | +--* COMMA void N024 ( 3, 3) [000783] -A------R--- | | +--* ASG byref N023 ( 1, 1) [000782] D------N---- | | | +--* LCL_VAR byref V87 tmp57 d:2 N022 ( 3, 3) [000780] ------------ | | | \--* ADDR byref N021 ( 3, 2) [000781] -------N---- | | | \--* LCL_VAR struct(AX) V86 tmp56 N028 ( 7, 5) [000787] -A--G------- | | \--* ASG ref N026 ( 3, 2) [000785] *------N---- | | +--* IND ref N025 ( 1, 1) [000784] ------------ | | | \--* LCL_VAR byref V87 tmp57 u:2 Zero Fseq[_bits] N027 ( 3, 2) [000786] ----G--N---- | | \--* LCL_VAR ref (AX) V58 tmp28 N035 ( 8, 7) [000794] -A--G------- | \--* ASG int N033 ( 4, 4) [000792] *------N---- | +--* IND int N032 ( 2, 2) [000791] -------N---- | | \--* ADD byref N030 ( 1, 1) [000789] ------------ | | +--* LCL_VAR byref V87 tmp57 u:2 (last use) N031 ( 1, 1) [000790] ------------ | | \--* CNS_INT long 8 Fseq[_sign] N034 ( 3, 2) [000793] ----G--N---- | \--* LCL_VAR int (AX) V59 tmp29 N038 ( 3, 2) [000798] ------------ arg0 in rcx +--* LCL_VAR long V88 tmp58 u:2 (last use) N040 ( 3, 3) [000800] ------------ arg1 in rdx +--* ADDR byref N039 ( 3, 2) [000799] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 N042 ( 3, 3) [000802] ------------ arg2 in r8 +--* ADDR byref N041 ( 3, 2) [000801] -------N---- | \--* LCL_VAR struct(AX) V86 tmp56 N044 ( 3, 3) [000212] ------------ arg3 in r9 \--* ADDR long N043 ( 3, 2) [000211] ----G--N---- \--* LCL_VAR struct(AX)(P) V23 loc20 \--* ref V23._bits (offs=0x00) -> V60 tmp30 \--* int V23._sign (offs=0x08) -> V61 tmp31 ***** BB35 STMT00050 (IL ???... ???) N021 ( 38, 24) [000226] -ACXG---R--- * ASG long N020 ( 1, 1) [000225] D------N---- +--* LCL_VAR long V24 loc21 d:2 N019 ( 38, 24) [000218] -ACXG------- \--* CALL long System.Numerics.BigInteger.op_Explicit N016 ( 18, 15) [000822] -A--G-----L- arg0 SETUP +--* COMMA void N009 ( 10, 8) [000815] -A--G------- | +--* COMMA void N004 ( 3, 3) [000810] -A------R--- | | +--* ASG byref N003 ( 1, 1) [000809] D------N---- | | | +--* LCL_VAR byref V89 tmp59 d:2 N002 ( 3, 3) [000807] ------------ | | | \--* ADDR byref N001 ( 3, 2) [000808] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 N008 ( 7, 5) [000814] -A--G------- | | \--* ASG ref N006 ( 3, 2) [000812] *------N---- | | +--* IND ref N005 ( 1, 1) [000811] ------------ | | | \--* LCL_VAR byref V89 tmp59 u:2 Zero Fseq[_bits] N007 ( 3, 2) [000813] ----G--N---- | | \--* LCL_VAR ref (AX) V62 tmp32 N015 ( 8, 7) [000821] -A--G------- | \--* ASG int N013 ( 4, 4) [000819] *------N---- | +--* IND int N012 ( 2, 2) [000818] -------N---- | | \--* ADD byref N010 ( 1, 1) [000816] ------------ | | +--* LCL_VAR byref V89 tmp59 u:2 (last use) N011 ( 1, 1) [000817] ------------ | | \--* CNS_INT long 8 Fseq[_sign] N014 ( 3, 2) [000820] ----G--N---- | \--* LCL_VAR int (AX) V63 tmp33 N018 ( 3, 3) [000824] ------------ arg0 in rcx \--* ADDR byref N017 ( 3, 2) [000823] -------N---- \--* LCL_VAR struct(AX) V76 tmp46 ***** BB35 STMT00052 (IL ???... ???) N005 ( 12, 7) [000232] -A--G---R--- * ASG int N004 ( 3, 2) [000231] D------N---- +--* LCL_VAR int V25 loc22 d:2 N003 ( 8, 4) [000516] ----G------- \--* EQ int N001 ( 3, 2) [000514] ----G------- +--* LCL_VAR int (AX) V61 tmp31 N002 ( 1, 1) [000515] ------------ \--* CNS_INT int 0 ***** BB35 STMT00054 (IL ???... ???) N005 ( 19, 10) [000237] -ACXG---R--- * ASG int N004 ( 3, 2) [000236] D------N---- +--* LCL_VAR int V26 loc23 d:2 N003 ( 15, 7) [000234] --CXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits N002 ( 1, 1) [000233] ------------ arg0 in rcx \--* LCL_VAR long V24 loc21 u:2 ***** BB35 STMT00055 (IL 0x19E...0x1A2) N004 ( 9, 7) [000241] ------------ * JTRUE void N003 ( 7, 5) [000240] N------N-U-- \--* LE int N001 ( 3, 2) [000238] ------------ +--* LCL_VAR int V26 loc23 u:2 N002 ( 3, 2) [000239] ------------ \--* LCL_VAR int V20 loc17 u:2 ------------ BB36 [1A4..1AF) -> BB38 (cond), preds={BB35} succs={BB37,BB38} ***** BB36 STMT00063 (IL 0x1A4...0x1A9) N005 ( 11, 8) [000286] -A------R--- * ASG int N004 ( 3, 2) [000285] D------N---- +--* LCL_VAR int V29 loc26 d:2 N003 ( 7, 5) [000284] ------------ \--* SUB int N001 ( 3, 2) [000282] ------------ +--* LCL_VAR int V26 loc23 u:2 (last use) N002 ( 3, 2) [000283] ------------ \--* LCL_VAR int V20 loc17 u:2 ***** BB36 STMT00064 (IL 0x1AB...0x1AD) N004 ( 7, 6) [000290] ------------ * JTRUE void N003 ( 5, 4) [000289] J------N---- \--* EQ int N001 ( 3, 2) [000287] ------------ +--* LCL_VAR int V25 loc22 u:2 (last use) N002 ( 1, 1) [000288] ------------ \--* CNS_INT int 0 ------------ BB37 [1AF..1C3) -> BB39 (always), preds={BB36} succs={BB39} ***** BB37 STMT00068 (IL 0x1AF...0x1C1) N013 ( 23, 15) [000320] -A------R--- * ASG int N012 ( 3, 2) [000319] D------N---- +--* LCL_VAR int V37 tmp7 d:4 N011 ( 19, 12) [000318] ------------ \--* EQ int N009 ( 14, 10) [000315] ------------ +--* AND long N001 ( 1, 1) [000305] ------------ | +--* LCL_VAR long V24 loc21 u:2 N008 ( 12, 8) [000314] ------------ | \--* ADD long N006 ( 10, 6) [000311] --------R--- | +--* LSH long N005 ( 1, 1) [000307] ------------ | | +--* CNS_INT long 1 N004 ( 5, 4) [000310] ------------ | | \--* AND int N002 ( 3, 2) [000308] ------------ | | +--* LCL_VAR int V29 loc26 u:2 N003 ( 1, 1) [000309] ------------ | | \--* CNS_INT int 63 N007 ( 1, 1) [000313] ------------ | \--* CNS_INT long -1 N010 ( 1, 1) [000317] ------------ \--* CNS_INT long 0 ------------ BB38 [1C3..1C4), preds={BB36} succs={BB39} ***** BB38 STMT00065 (IL 0x1C3...0x1C3) N003 ( 5, 4) [000293] -A------R--- * ASG int N002 ( 3, 2) [000292] D------N---- +--* LCL_VAR int V37 tmp7 d:3 N001 ( 1, 1) [000291] ------------ \--* CNS_INT int 0 ------------ BB39 [1C4..1D0), preds={BB37,BB38} succs={BB40} ***** BB39 STMT00116 (IL ???... ???) N005 ( 0, 0) [000868] -A------R--- * ASG int N004 ( 0, 0) [000866] D------N---- +--* LCL_VAR int V37 tmp7 d:2 N003 ( 0, 0) [000867] ------------ \--* PHI int N001 ( 0, 0) [000897] ------------ pred BB37 +--* PHI_ARG int V37 tmp7 u:4 N002 ( 0, 0) [000896] ------------ pred BB38 \--* PHI_ARG int V37 tmp7 u:3 ***** BB39 STMT00066 (IL ???...0x1C4) N004 ( 8, 7) [000297] -A------R--- * ASG int N003 ( 3, 2) [000296] D------N---- +--* LCL_VAR int V25 loc22 d:4 N002 ( 4, 4) [000826] ------------ \--* CAST int <- bool <- int N001 ( 3, 2) [000295] ------------ \--* LCL_VAR int V37 tmp7 u:2 (last use) ***** BB39 STMT00067 (IL 0x1C6...0x1CE) N007 ( 10, 6) [000304] -A------R--- * ASG long N006 ( 1, 1) [000303] D------N---- +--* LCL_VAR long V24 loc21 d:4 N005 ( 10, 6) [000302] ------------ \--* RSZ long N001 ( 1, 1) [000298] ------------ +--* LCL_VAR long V24 loc21 u:2 (last use) N004 ( 5, 4) [000301] ------------ \--* AND int N002 ( 3, 2) [000299] ------------ +--* LCL_VAR int V29 loc26 u:2 (last use) N003 ( 1, 1) [000300] ------------ \--* CNS_INT int 63 ------------ BB40 [1D0..1E7) -> BB42 (cond), preds={BB35,BB39} succs={BB41,BB42} ***** BB40 STMT00115 (IL ???... ???) N005 ( 0, 0) [000865] -A------R--- * ASG bool N004 ( 0, 0) [000863] D------N---- +--* LCL_VAR bool V25 loc22 d:3 N003 ( 0, 0) [000864] ------------ \--* PHI bool N001 ( 0, 0) [000894] ------------ pred BB39 +--* PHI_ARG bool V25 loc22 u:4 N002 ( 0, 0) [000889] ------------ pred BB35 \--* PHI_ARG bool V25 loc22 u:2 ***** BB40 STMT00114 (IL ???... ???) N005 ( 0, 0) [000862] -A------R--- * ASG long N004 ( 0, 0) [000860] D------N---- +--* LCL_VAR long V24 loc21 d:3 N003 ( 0, 0) [000861] ------------ \--* PHI long N001 ( 0, 0) [000895] ------------ pred BB39 +--* PHI_ARG long V24 loc21 u:4 N002 ( 0, 0) [000890] ------------ pred BB35 \--* PHI_ARG long V24 loc21 u:2 ***** BB40 STMT00057 (IL ???... ???) N027 ( 53, 34) [000254] -ACXG---R--- * ASG long N026 ( 3, 2) [000253] D------N---- +--* LCL_VAR long V27 loc24 d:2 N025 ( 49, 31) [000252] -ACXG------- \--* ADD long N023 ( 47, 29) [000250] -ACXG------- +--* LSH long N019 ( 38, 24) [000243] -ACXG------- | +--* CALL long System.Numerics.BigInteger.op_Explicit N016 ( 18, 15) [000845] -A--G-----L- arg0 SETUP | | +--* COMMA void N009 ( 10, 8) [000838] -A--G------- | | | +--* COMMA void N004 ( 3, 3) [000833] -A------R--- | | | | +--* ASG byref N003 ( 1, 1) [000832] D------N---- | | | | | +--* LCL_VAR byref V90 tmp60 d:2 N002 ( 3, 3) [000830] ------------ | | | | | \--* ADDR byref N001 ( 3, 2) [000831] ----G--N---- | | | | | \--* LCL_VAR struct(AX) V76 tmp46 N008 ( 7, 5) [000837] -A--G------- | | | | \--* ASG ref N006 ( 3, 2) [000835] *------N---- | | | | +--* IND ref N005 ( 1, 1) [000834] ------------ | | | | | \--* LCL_VAR byref V90 tmp60 u:2 Zero Fseq[_bits] N007 ( 3, 2) [000836] ----G--N---- | | | | \--* LCL_VAR ref (AX) V54 tmp24 N015 ( 8, 7) [000844] -A--G------- | | | \--* ASG int N013 ( 4, 4) [000842] *------N---- | | | +--* IND int N012 ( 2, 2) [000841] -------N---- | | | | \--* ADD byref N010 ( 1, 1) [000839] ------------ | | | | +--* LCL_VAR byref V90 tmp60 u:2 (last use) N011 ( 1, 1) [000840] ------------ | | | | \--* CNS_INT long 8 Fseq[_sign] N014 ( 3, 2) [000843] ----G--N---- | | | \--* LCL_VAR int (AX) V55 tmp25 N018 ( 3, 3) [000847] ------------ arg0 in rcx | | \--* ADDR byref N017 ( 3, 2) [000846] -------N---- | | \--* LCL_VAR struct(AX) V76 tmp46 N022 ( 5, 4) [000249] ------------ | \--* AND int N020 ( 3, 2) [000247] ------------ | +--* LCL_VAR int V20 loc17 u:2 (last use) N021 ( 1, 1) [000248] ------------ | \--* CNS_INT int 63 N024 ( 1, 1) [000251] ------------ \--* LCL_VAR long V24 loc21 u:3 (last use) ***** BB40 STMT00058 (IL 0x1E2...0x1E5) N004 ( 5, 5) [000258] ------------ * JTRUE void N003 ( 3, 3) [000257] N------N---- \--* NE int N001 ( 1, 1) [000255] ------------ +--* LCL_VAR int V13 loc10 u:2 N002 ( 1, 1) [000256] ------------ \--* CNS_INT int 0 ------------ BB41 [1E7..1EE) -> BB43 (always), preds={BB40} succs={BB43} ***** BB41 STMT00062 (IL 0x1E7...0x1EC) N006 ( 10, 8) [000280] -A------R--- * ASG int N005 ( 3, 2) [000279] D------N---- +--* LCL_VAR int V36 tmp6 d:4 N004 ( 6, 5) [000278] ------------ \--* ADD int N002 ( 4, 3) [000276] ------------ +--* NEG int N001 ( 3, 2) [000275] ------------ | \--* LCL_VAR int V22 loc19 u:2 (last use) N003 ( 1, 1) [000277] ------------ \--* CNS_INT int -1 ------------ BB42 [1EE..1F2), preds={BB40} succs={BB43} ***** BB42 STMT00059 (IL 0x1EE...0x1F1) N005 ( 7, 6) [000263] -A------R--- * ASG int N004 ( 3, 2) [000262] D------N---- +--* LCL_VAR int V36 tmp6 d:3 N003 ( 3, 3) [000261] ------------ \--* ADD int N001 ( 1, 1) [000259] ------------ +--* LCL_VAR int V13 loc10 u:2 (last use) N002 ( 1, 1) [000260] ------------ \--* CNS_INT int -2 ------------ BB43 [1F2..202), preds={BB41,BB42} succs={BB44} ***** BB43 STMT00113 (IL ???... ???) N005 ( 0, 0) [000859] -A------R--- * ASG int N004 ( 0, 0) [000857] D------N---- +--* LCL_VAR int V36 tmp6 d:2 N003 ( 0, 0) [000858] ------------ \--* PHI int N001 ( 0, 0) [000893] ------------ pred BB41 +--* PHI_ARG int V36 tmp6 u:4 N002 ( 0, 0) [000892] ------------ pred BB42 \--* PHI_ARG int V36 tmp6 u:3 ***** BB43 STMT00061 (IL 0x1F4...0x201) N012 ( 28, 18) [000853] -ACXG---R--- * ASG int N011 ( 1, 1) [000852] D------N---- +--* LCL_VAR int V51 tmp21 d:4 N010 ( 28, 18) [000273] --CXG------- \--* CALL nullcheck int FloatingPointType.AssembleFloatingPointValue N005 ( 1, 1) [000272] ------------ arg4 out+20 +--* LCL_VAR byref V02 arg2 u:1 (last use) N006 ( 1, 1) [000268] ------------ this in rcx +--* LCL_VAR ref V01 arg1 u:1 (last use) N007 ( 3, 2) [000269] ------------ arg1 in rdx +--* LCL_VAR long V27 loc24 u:2 (last use) N008 ( 3, 2) [000270] ------------ arg2 in r8 +--* LCL_VAR int V36 tmp6 u:2 (last use) N009 ( 3, 2) [000271] ------------ arg3 in r9 \--* LCL_VAR int V25 loc22 u:3 (last use) ------------ BB44 [???..???) (return), preds={BB16,BB30,BB43} succs={} ***** BB44 STMT00112 (IL ???... ???) N006 ( 0, 0) [000856] -A------R--- * ASG int N005 ( 0, 0) [000854] D------N---- +--* LCL_VAR int V51 tmp21 d:2 N004 ( 0, 0) [000855] ------------ \--* PHI int N001 ( 0, 0) [000901] ------------ pred BB30 +--* PHI_ARG int V51 tmp21 u:5 N002 ( 0, 0) [000891] ------------ pred BB43 +--* PHI_ARG int V51 tmp21 u:4 N003 ( 0, 0) [000887] ------------ pred BB16 \--* PHI_ARG int V51 tmp21 u:3 ***** BB44 STMT00109 (IL ???... ???) N002 ( 2, 2) [000523] ------------ * RETURN int N001 ( 1, 1) [000522] -------N---- \--* LCL_VAR int V51 tmp21 u:2 (last use) ------------------------------------------------------------------------------------------------------------------- *************** Finishing PHASE Build SSA representation Trees after Build SSA representation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0056] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..00D)-> BB04 ( cond ) i label target idxlen BB03 [0001] 1 BB02 0.50 [00D..017) (return) i hascall gcsafe BB04 [0002] 1 BB02 0.50 [017..065)-> BB06 ( cond ) i label target hascall gcsafe BB05 [0038] 1 BB04 0.50 [020..021)-> BB07 (always) i gcsafe BB06 [0039] 1 BB04 0.50 [020..021) i label target gcsafe BB07 [0040] 2 BB05,BB06 0.50 [000..000)-> BB09 ( cond ) i internal label target gcsafe idxlen BB08 [0043] 1 BB07 0.50 [000..000)-> BB10 (always) i internal gcsafe BB09 [0044] 1 BB07 0.50 [000..000) i internal label target gcsafe BB10 [0045] 2 BB08,BB09 0.50 [???..???)-> BB14 ( cond ) i internal label target hascall gcsafe idxlen BB11 [0003] 1 BB10 0.50 [065..070)-> BB13 ( cond ) i hascall gcsafe BB12 [0004] 1 BB11 0.50 [070..07A) (return) i hascall gcsafe BB13 [0005] 1 BB11 0.50 [07A..082) i label target hascall gcsafe BB14 [0006] 2 BB10,BB13 0.50 [082..092)-> BB16 ( cond ) i label target hascall gcsafe BB15 [0007] 1 BB14 0.50 [092..096)-> BB17 ( cond ) i gcsafe BB16 [0008] 2 BB14,BB15 0.50 [096..0A7)-> BB44 (always) i label target hascall gcsafe BB17 [0009] 1 BB15 0.50 [0A7..0B0)-> BB19 ( cond ) i label target gcsafe BB18 [0010] 1 BB17 0.50 [0B0..0B4)-> BB20 (always) i gcsafe BB19 [0011] 1 BB17 0.50 [0B4..0BE) i label target gcsafe BB20 [0012] 2 BB18,BB19 0.50 [0BE..0C4)-> BB23 ( cond ) i label target gcsafe BB21 [0013] 1 BB20 0.50 [0C4..0D9)-> BB23 ( cond ) i hascall gcsafe idxlen BB22 [0014] 1 BB21 0.50 [0D9..0E3) (return) i hascall gcsafe BB23 [0015] 2 BB20,BB21 0.50 [0E3..117)-> BB25 ( cond ) i label target hascall gcsafe BB24 [0016] 1 BB23 0.50 [117..11A)-> BB26 (always) i gcsafe BB25 [0017] 1 BB23 0.50 [11A..11F) i label target gcsafe BB26 [0018] 2 BB24,BB25 0.50 [11F..126)-> BB28 ( cond ) i label target gcsafe BB27 [0019] 1 BB26 0.50 [126..12F) i hascall gcsafe BB28 [0020] 2 BB26,BB27 0.50 [12F..13E)-> BB32 ( cond ) i label target gcsafe BB29 [0021] 1 BB28 0.50 [13E..144)-> BB31 ( cond ) i gcsafe BB30 [0022] 1 BB29 0.50 [144..155)-> BB44 (always) i hascall gcsafe BB31 [0023] 1 BB29 0.50 [155..15C) i label target gcsafe BB32 [0024] 2 BB28,BB31 0.50 [15C..167)-> BB34 ( cond ) i label target hascall gcsafe BB33 [0025] 1 BB32 0.50 [167..16B)-> BB35 (always) i gcsafe BB34 [0026] 1 BB32 0.50 [16B..16F) i label target gcsafe BB35 [0027] 2 BB33,BB34 0.50 [16F..1A4)-> BB40 ( cond ) i label target hascall gcsafe BB36 [0028] 1 BB35 0.50 [1A4..1AF)-> BB38 ( cond ) i gcsafe BB37 [0029] 1 BB36 0.50 [1AF..1C3)-> BB39 (always) i gcsafe BB38 [0030] 1 BB36 0.50 [1C3..1C4) i label target gcsafe BB39 [0031] 2 BB37,BB38 0.50 [1C4..1D0) i label target gcsafe BB40 [0032] 2 BB35,BB39 0.50 [1D0..1E7)-> BB42 ( cond ) i label target hascall gcsafe BB41 [0033] 1 BB40 0.50 [1E7..1EE)-> BB43 (always) i gcsafe BB42 [0034] 1 BB40 0.50 [1EE..1F2) i label target gcsafe BB43 [0035] 2 BB41,BB42 0.50 [1F2..202) i label target hascall gcsafe BB44 [0054] 3 BB16,BB30,BB43 0.50 [???..???) (return) keep internal target gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} ***** BB01 STMT00111 (IL ???... ???) N011 ( 7, 7) [000540] -A---------- * COMMA void N004 ( 3, 3) [000533] -A------R--- +--* ASG ref N003 ( 1, 1) [000530] D------N---- | +--* LCL_VAR ref V52 tmp22 d:2 N002 ( 3, 2) [000532] n----------- | \--* IND ref N001 ( 1, 1) [000531] ------------ | \--* LCL_VAR byref V00 arg0 u:1 Zero Fseq[Mantissa] N010 ( 4, 4) [000539] -A------R--- \--* ASG int N009 ( 1, 1) [000534] D------N---- +--* LCL_VAR int V53 tmp23 d:2 N008 ( 4, 4) [000538] n----------- \--* IND int N007 ( 2, 2) [000537] -------N---- \--* ADD byref N005 ( 1, 1) [000535] ------------ +--* LCL_VAR byref V00 arg0 u:1 (last use) N006 ( 1, 1) [000536] ------------ \--* CNS_INT long 8 Fseq[Exponent] ------------ BB02 [000..00D) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00000 (IL 0x000...0x00B) N005 ( 7, 7) [000006] ---XG------- * JTRUE void N004 ( 5, 5) [000005] J--XG--N---- \--* NE int N002 ( 3, 3) [000003] ---XG------- +--* ARR_LENGTH int N001 ( 1, 1) [000002] ------------ | \--* LCL_VAR ref V52 tmp22 u:2 N003 ( 1, 1) [000004] ------------ \--* CNS_INT int 0 ------------ BB03 [00D..017) (return), preds={BB02} succs={} ***** BB03 STMT00087 (IL 0x00D...0x014) N006 ( 25, 13) [000403] -ACXG---R--- * ASG long N005 ( 3, 2) [000402] *--X---N---- +--* IND long N004 ( 1, 1) [000399] ------------ | \--* LCL_VAR byref V02 arg2 u:1 (last use) N003 ( 21, 10) [000401] --CXG------- \--* CALLV ind long FloatingPointType.get_Zero N002 ( 1, 1) [000400] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 (last use) ***** BB03 STMT00107 (IL ???... ???) N002 ( 2, 2) [000520] ------------ * RETURN int N001 ( 1, 1) [000404] ------------ \--* CNS_INT int 1 ------------ BB04 [017..065) -> BB06 (cond), preds={BB02} succs={BB05,BB06} ***** BB04 STMT00002 (IL ???... ???) N010 ( 30, 19) [000013] -ACXG---R--- * ASG int N009 ( 3, 2) [000012] D------N---- +--* LCL_VAR int V03 loc0 d:2 N008 ( 26, 16) [000011] --CXG------- \--* ADD int N006 ( 24, 14) [000409] --CXG------- +--* CAST int <- ushort <- int N005 ( 23, 12) [000408] --CXG------- | \--* ADD int N003 ( 21, 10) [000406] --CXG------- | +--* CALLV ind int FloatingPointType.get_DenormalMantissaBits N002 ( 1, 1) [000007] ------------ this in rcx | | \--* LCL_VAR ref V01 arg1 u:1 N004 ( 1, 1) [000407] ------------ | \--* CNS_INT int 1 N007 ( 1, 1) [000010] ------------ \--* CNS_INT int 1 ***** BB04 STMT00092 (IL 0x020... ???) N003 ( 5, 4) [000424] -A--G---R--- * ASG int N002 ( 3, 2) [000423] D------N---- +--* LCL_VAR int V40 tmp10 d:2 N001 ( 1, 1) [000017] ------------ \--* LCL_VAR int V53 tmp23 u:2 ***** BB04 STMT00089 (IL 0x020... ???) N004 ( 5, 5) [000414] ------------ * JTRUE void N003 ( 3, 3) [000413] J------N---- \--* LE int N001 ( 1, 1) [000412] ------------ +--* LCL_VAR int V53 tmp23 u:2 N002 ( 1, 1) [000411] ------------ \--* CNS_INT int 0 ------------ BB05 [020..021) -> BB07 (always), preds={BB04} succs={BB07} ***** BB05 STMT00091 (IL 0x020... ???) N003 ( 7, 5) [000421] -A------R--- * ASG int N002 ( 3, 2) [000420] D------N---- +--* LCL_VAR int V39 tmp9 d:4 N001 ( 3, 2) [000419] ------------ \--* LCL_VAR int V40 tmp10 u:2 (last use) ------------ BB06 [020..021), preds={BB04} succs={BB07} ***** BB06 STMT00090 (IL 0x020... ???) N003 ( 5, 4) [000417] -A------R--- * ASG int N002 ( 3, 2) [000416] D------N---- +--* LCL_VAR int V39 tmp9 d:3 N001 ( 1, 1) [000415] ------------ \--* CNS_INT int 0 ------------ BB07 [000..000) -> BB09 (cond), preds={BB05,BB06} succs={BB08,BB09} ***** BB07 STMT00122 (IL ???... ???) N005 ( 0, 0) [000886] -A------R--- * ASG int N004 ( 0, 0) [000884] D------N---- +--* LCL_VAR int V39 tmp9 d:2 N003 ( 0, 0) [000885] ------------ \--* PHI int N001 ( 0, 0) [000909] ------------ pred BB05 +--* PHI_ARG int V39 tmp9 u:4 N002 ( 0, 0) [000908] ------------ pred BB06 \--* PHI_ARG int V39 tmp9 u:3 ***** BB07 STMT00004 (IL ???... ???) N003 ( 3, 3) [000021] -A------R--- * ASG int N002 ( 1, 1) [000020] D------N---- +--* LCL_VAR int V31 tmp1 d:2 N001 ( 3, 2) [000422] ------------ \--* LCL_VAR int V39 tmp9 u:2 ***** BB07 STMT00096 (IL ???... ???) N004 ( 3, 3) [000443] -A-XG---R--- * ASG int N003 ( 1, 1) [000442] D------N---- +--* LCL_VAR int V42 tmp12 d:2 N002 ( 3, 3) [000429] ---XG------- \--* ARR_LENGTH int N001 ( 1, 1) [000428] ------------ \--* LCL_VAR ref V52 tmp22 u:2 ***** BB07 STMT00093 (IL ???... ???) N004 ( 7, 6) [000433] ------------ * JTRUE void N003 ( 5, 4) [000432] N------N-U-- \--* LE int N001 ( 3, 2) [000023] ------------ +--* LCL_VAR int V39 tmp9 u:2 (last use) N002 ( 1, 1) [000431] ------------ \--* LCL_VAR int V42 tmp12 u:2 ------------ BB08 [000..000) -> BB10 (always), preds={BB07} succs={BB10} ***** BB08 STMT00095 (IL ???... ???) N003 ( 1, 3) [000440] -A------R--- * ASG int N002 ( 1, 1) [000439] D------N---- +--* LCL_VAR int V41 tmp11 d:4 N001 ( 1, 1) [000438] ------------ \--* LCL_VAR int V42 tmp12 u:2 (last use) ------------ BB09 [000..000), preds={BB07} succs={BB10} ***** BB09 STMT00094 (IL ???... ???) N003 ( 1, 3) [000436] -A------R--- * ASG int N002 ( 1, 1) [000435] D------N---- +--* LCL_VAR int V41 tmp11 d:3 N001 ( 1, 1) [000434] ------------ \--* LCL_VAR int V31 tmp1 u:2 ------------ BB10 [???..???) -> BB14 (cond), preds={BB08,BB09} succs={BB11,BB14} ***** BB10 STMT00121 (IL ???... ???) N005 ( 0, 0) [000883] -A------R--- * ASG int N004 ( 0, 0) [000881] D------N---- +--* LCL_VAR int V41 tmp11 d:2 N003 ( 0, 0) [000882] ------------ \--* PHI int N001 ( 0, 0) [000907] ------------ pred BB08 +--* PHI_ARG int V41 tmp11 u:4 N002 ( 0, 0) [000906] ------------ pred BB09 \--* PHI_ARG int V41 tmp11 u:3 ***** BB10 STMT00008 (IL ???...0x03C) N005 ( 7, 6) [000035] -A------R--- * ASG int N004 ( 3, 2) [000034] D------N---- +--* LCL_VAR int V05 loc2 d:2 N003 ( 3, 3) [000033] ------------ \--* SUB int N001 ( 1, 1) [000022] ------------ +--* LCL_VAR int V31 tmp1 u:2 (last use) N002 ( 1, 1) [000032] ------------ \--* LCL_VAR int V41 tmp11 u:2 ***** BB10 STMT00011 (IL 0x042...0x044) N003 ( 5, 4) [000044] -A------R--- * ASG int N002 ( 3, 2) [000043] D------N---- +--* LCL_VAR int V08 loc5 d:2 N001 ( 1, 1) [000042] ------------ \--* LCL_VAR int V41 tmp11 u:2 ***** BB10 STMT00013 (IL ???... ???) N004 ( 7, 6) [000050] -A-XG---R--- * ASG int N003 ( 3, 2) [000049] D------N---- +--* LCL_VAR int V09 loc6 d:2 N002 ( 3, 3) [000448] ---XG------- \--* ARR_LENGTH int N001 ( 1, 1) [000447] ------------ \--* LCL_VAR ref V52 tmp22 u:2 ***** BB10 STMT00014 (IL 0x04F...0x054) N005 ( 5, 4) [000055] -A------R--- * ASG int N004 ( 1, 1) [000054] D------N---- +--* LCL_VAR int V10 loc7 d:2 N003 ( 5, 4) [000053] ------------ \--* SUB int N001 ( 3, 2) [000051] ------------ +--* LCL_VAR int V09 loc6 u:2 N002 ( 1, 1) [000052] ------------ \--* LCL_VAR int V41 tmp11 u:2 ***** BB10 STMT00016 (IL ???... ???) N028 ( 49, 35) [000059] SACXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger N004 ( 7, 6) [000563] -A------R-L- arg0 SETUP +--* ASG long N003 ( 3, 2) [000562] D------N---- | +--* LCL_VAR long V75 tmp45 d:2 N002 ( 3, 3) [000064] ------------ | \--* ADDR long N001 ( 3, 2) [000063] ----G--N---- | \--* LCL_VAR struct(AX)(P) V11 loc8 | \--* ref V11._bits (offs=0x00) -> V54 tmp24 | \--* int V11._sign (offs=0x08) -> V55 tmp25 N020 ( 14, 13) [000561] -A--------L- arg1 SETUP +--* COMMA void N013 ( 8, 7) [000554] -A---------- | +--* COMMA void N008 ( 3, 3) [000549] -A------R--- | | +--* ASG byref N007 ( 1, 1) [000548] D------N---- | | | +--* LCL_VAR byref V74 tmp44 d:2 N006 ( 3, 3) [000546] ------------ | | | \--* ADDR byref N005 ( 3, 2) [000547] -------N---- | | | \--* LCL_VAR struct(AX) V73 tmp43 N012 ( 5, 4) [000553] -A---------- | | \--* ASG ref N010 ( 3, 2) [000551] *------N---- | | +--* IND ref N009 ( 1, 1) [000550] ------------ | | | \--* LCL_VAR byref V74 tmp44 u:2 Zero Fseq[Mantissa] N011 ( 1, 1) [000552] -------N---- | | \--* LCL_VAR ref V52 tmp22 u:2 N019 ( 6, 6) [000560] -A---------- | \--* ASG int N017 ( 4, 4) [000558] *------N---- | +--* IND int N016 ( 2, 2) [000557] -------N---- | | \--* ADD byref N014 ( 1, 1) [000555] ------------ | | +--* LCL_VAR byref V74 tmp44 u:2 (last use) N015 ( 1, 1) [000556] ------------ | | \--* CNS_INT long 8 Fseq[Exponent] N018 ( 1, 1) [000559] -------N---- | \--* LCL_VAR int V53 tmp23 u:2 N023 ( 3, 2) [000564] ------------ arg0 in rcx +--* LCL_VAR long V75 tmp45 u:2 (last use) N025 ( 3, 3) [000566] ------------ arg1 in rdx +--* ADDR byref N024 ( 3, 2) [000565] -------N---- | \--* LCL_VAR struct(AX) V73 tmp43 N026 ( 1, 1) [000058] ------------ arg3 in r9 +--* LCL_VAR int V41 tmp11 u:2 (last use) N027 ( 1, 1) [000057] ------------ arg2 in r8 \--* CNS_INT int 0 ***** BB10 STMT00017 (IL 0x061...0x063) N004 ( 7, 6) [000068] ------------ * JTRUE void N003 ( 5, 4) [000067] N------N---- \--* EQ int N001 ( 3, 2) [000065] ------------ +--* LCL_VAR int V05 loc2 u:2 N002 ( 1, 1) [000066] ------------ \--* CNS_INT int 0 ------------ BB11 [065..070) -> BB13 (cond), preds={BB10} succs={BB12,BB13} ***** BB11 STMT00083 (IL ???... ???) N008 ( 23, 17) [000387] --CXG------- * JTRUE void N007 ( 21, 15) [000386] J-CXG--N---- \--* GE int N004 ( 16, 10) [000385] --CXG------- +--* CAST long <- int N003 ( 15, 8) [000383] --CXG------- | \--* CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent N002 ( 1, 1) [000382] ------------ this in rcx | \--* LCL_VAR ref V01 arg1 u:1 N006 ( 4, 4) [000381] ---------U-- \--* CAST long <- ulong <- uint N005 ( 3, 2) [000380] ------------ \--* LCL_VAR int V05 loc2 u:2 ------------ BB12 [070..07A) (return), preds={BB11} succs={} ***** BB12 STMT00085 (IL 0x070...0x077) N006 ( 25, 13) [000396] -ACXG---R--- * ASG long N005 ( 3, 2) [000395] *--X---N---- +--* IND long N004 ( 1, 1) [000392] ------------ | \--* LCL_VAR byref V02 arg2 u:1 (last use) N003 ( 21, 10) [000394] --CXG------- \--* CALLV ind long FloatingPointType.get_Infinity N002 ( 1, 1) [000393] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 (last use) ***** BB12 STMT00108 (IL ???... ???) N002 ( 2, 2) [000521] ------------ * RETURN int N001 ( 1, 1) [000397] ------------ \--* CNS_INT int 3 ------------ BB13 [07A..082), preds={BB11} succs={BB14} ***** BB13 STMT00084 (IL 0x07A...0x07D) N006 ( 20, 12) [000391] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen N004 ( 3, 3) [000389] ------------ arg0 in rcx +--* ADDR long N003 ( 3, 2) [000388] ----G--N---- | \--* LCL_VAR struct(AX)(P) V11 loc8 | \--* ref V11._bits (offs=0x00) -> V54 tmp24 | \--* int V11._sign (offs=0x08) -> V55 tmp25 N005 ( 3, 2) [000390] ------------ arg1 in rdx \--* LCL_VAR int V05 loc2 u:2 (last use) ------------ BB14 [082..092) -> BB16 (cond), preds={BB10,BB13} succs={BB15,BB16} ***** BB14 STMT00019 (IL ???... ???) N023 ( 41, 28) [000077] -ACXG---R--- * ASG int N022 ( 1, 1) [000076] D------N---- +--* LCL_VAR int V13 loc10 d:2 N021 ( 41, 28) [000072] -ACXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits N016 ( 18, 15) [000591] -A--G-----L- arg0 SETUP +--* COMMA void N009 ( 10, 8) [000584] -A--G------- | +--* COMMA void N004 ( 3, 3) [000579] -A------R--- | | +--* ASG byref N003 ( 1, 1) [000578] D------N---- | | | +--* LCL_VAR byref V77 tmp47 d:2 N002 ( 3, 3) [000576] ------------ | | | \--* ADDR byref N001 ( 3, 2) [000577] -------N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 N008 ( 7, 5) [000583] -A--G------- | | \--* ASG ref N006 ( 3, 2) [000581] *------N---- | | +--* IND ref N005 ( 1, 1) [000580] ------------ | | | \--* LCL_VAR byref V77 tmp47 u:2 Zero Fseq[_bits] N007 ( 3, 2) [000582] ----G--N---- | | \--* LCL_VAR ref (AX) V54 tmp24 N015 ( 8, 7) [000590] -A--G------- | \--* ASG int N013 ( 4, 4) [000588] *------N---- | +--* IND int N012 ( 2, 2) [000587] -------N---- | | \--* ADD byref N010 ( 1, 1) [000585] ------------ | | +--* LCL_VAR byref V77 tmp47 u:2 (last use) N011 ( 1, 1) [000586] ------------ | | \--* CNS_INT long 8 Fseq[_sign] N014 ( 3, 2) [000589] ----G--N---- | \--* LCL_VAR int (AX) V55 tmp25 N019 ( 3, 3) [000593] ------------ arg0 in rcx +--* ADDR byref N018 ( 3, 2) [000592] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 N020 ( 3, 3) [000071] ------------ arg1 in rdx \--* LCL_VAR_ADDR long V12 loc9 ***** BB14 STMT00020 (IL 0x08D...0x090) N004 ( 7, 6) [000081] ------------ * JTRUE void N003 ( 5, 4) [000080] N------N-U-- \--* GE int N001 ( 1, 1) [000078] ------------ +--* LCL_VAR int V13 loc10 u:2 N002 ( 3, 2) [000079] ------------ \--* LCL_VAR int V03 loc0 u:2 ------------ BB15 [092..096) -> BB17 (cond), preds={BB14} succs={BB16,BB17} ***** BB15 STMT00022 (IL 0x092...0x094) N004 ( 5, 5) [000094] ------------ * JTRUE void N003 ( 3, 3) [000093] J------N---- \--* NE int N001 ( 1, 1) [000091] ------------ +--* LCL_VAR int V10 loc7 u:2 N002 ( 1, 1) [000092] ------------ \--* CNS_INT int 0 ------------ BB16 [096..0A7) -> BB44 (always), preds={BB14,BB15} succs={BB44} ***** BB16 STMT00021 (IL 0x096...0x0A6) N014 ( 29, 17) [000600] -ACXG---R--- * ASG int N013 ( 1, 1) [000599] D------N---- +--* LCL_VAR int V51 tmp21 d:3 N012 ( 29, 17) [000089] --CXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits N005 ( 1, 1) [000088] ------------ arg4 out+20 +--* LCL_VAR byref V02 arg2 u:1 (last use) N008 ( 6, 3) [000086] N----------- arg2 in r8 +--* NE int N006 ( 1, 1) [000084] ------------ | +--* LCL_VAR int V10 loc7 u:2 (last use) N007 ( 1, 1) [000085] ------------ | \--* CNS_INT int 0 N009 ( 3, 2) [000082] ----G------- arg0 in rcx +--* LCL_VAR ref (AX) V12 loc9 N010 ( 1, 1) [000083] ------------ arg1 in rdx +--* LCL_VAR int V13 loc10 u:2 (last use) N011 ( 1, 1) [000087] ------------ arg3 in r9 \--* LCL_VAR ref V01 arg1 u:1 (last use) ------------ BB17 [0A7..0B0) -> BB19 (cond), preds={BB15} succs={BB18,BB19} ***** BB17 STMT00023 (IL 0x0A7...0x0AE) N004 ( 5, 5) [000100] ----G------- * JTRUE void N003 ( 3, 3) [000099] J---G--N---- \--* LT int N001 ( 1, 1) [000097] ------------ +--* LCL_VAR int V53 tmp23 u:2 N002 ( 1, 1) [000098] ------------ \--* CNS_INT int 0 ------------ BB18 [0B0..0B4) -> BB20 (always), preds={BB17} succs={BB20} ***** BB18 STMT00081 (IL 0x0B0...0x0B2) N003 ( 5, 4) [000378] -A------R--- * ASG int N002 ( 3, 2) [000377] D------N---- +--* LCL_VAR int V32 tmp2 d:4 N001 ( 1, 1) [000376] ------------ \--* LCL_VAR int V10 loc7 u:2 ------------ BB19 [0B4..0BE), preds={BB17} succs={BB20} ***** BB19 STMT00024 (IL 0x0B4...0x0BD) N005 ( 7, 6) [000108] -A--G---R--- * ASG int N004 ( 3, 2) [000107] D------N---- +--* LCL_VAR int V32 tmp2 d:3 N003 ( 3, 3) [000106] ----G------- \--* SUB int N001 ( 1, 1) [000101] ------------ +--* LCL_VAR int V10 loc7 u:2 N002 ( 1, 1) [000104] ------------ \--* LCL_VAR int V53 tmp23 u:2 ------------ BB20 [0BE..0C4) -> BB23 (cond), preds={BB18,BB19} succs={BB21,BB23} ***** BB20 STMT00120 (IL ???... ???) N005 ( 0, 0) [000880] -A------R--- * ASG int N004 ( 0, 0) [000878] D------N---- +--* LCL_VAR int V32 tmp2 d:2 N003 ( 0, 0) [000879] ------------ \--* PHI int N001 ( 0, 0) [000905] ------------ pred BB18 +--* PHI_ARG int V32 tmp2 u:4 N002 ( 0, 0) [000904] ------------ pred BB19 \--* PHI_ARG int V32 tmp2 u:3 ***** BB20 STMT00025 (IL ???...0x0BE) N003 ( 7, 5) [000112] -A------R--- * ASG int N002 ( 3, 2) [000111] D------N---- +--* LCL_VAR int V14 loc11 d:2 N001 ( 3, 2) [000110] ------------ \--* LCL_VAR int V32 tmp2 u:2 (last use) ***** BB20 STMT00026 (IL 0x0C0...0x0C2) N004 ( 5, 5) [000116] ------------ * JTRUE void N003 ( 3, 3) [000115] J------N---- \--* NE int N001 ( 1, 1) [000113] ------------ +--* LCL_VAR int V13 loc10 u:2 N002 ( 1, 1) [000114] ------------ \--* CNS_INT int 0 ------------ BB21 [0C4..0D9) -> BB23 (cond), preds={BB20} succs={BB22,BB23} ***** BB21 STMT00077 (IL ???... ???) N008 ( 13, 13) [000363] -A-XG---R--- * ASG long N007 ( 3, 2) [000362] D------N---- +--* LCL_VAR long V38 tmp8 d:2 N006 ( 9, 10) [000359] ---XG---R--- \--* SUB long N005 ( 4, 4) [000353] ---------U-- +--* CAST long <- ulong <- uint N004 ( 3, 2) [000352] ------------ | \--* LCL_VAR int V14 loc11 u:2 N003 ( 4, 5) [000358] ---XG------- \--* CAST long <- int N002 ( 3, 3) [000456] ---XG------- \--* ARR_LENGTH int N001 ( 1, 1) [000455] ------------ \--* LCL_VAR ref V52 tmp22 u:2 ***** BB21 STMT00078 (IL ???... ???) N007 ( 22, 15) [000368] --CXG------- * JTRUE void N006 ( 20, 13) [000367] J-CXG--N---- \--* GE int N004 ( 16, 10) [000366] --CXG------- +--* CAST long <- int N003 ( 15, 8) [000361] --CXG------- | \--* CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent N002 ( 1, 1) [000360] ------------ this in rcx | \--* LCL_VAR ref V01 arg1 u:1 N005 ( 3, 2) [000364] ------------ \--* LCL_VAR long V38 tmp8 u:2 (last use) ------------ BB22 [0D9..0E3) (return), preds={BB21} succs={} ***** BB22 STMT00079 (IL 0x0D9...0x0E0) N006 ( 25, 13) [000373] -ACXG---R--- * ASG long N005 ( 3, 2) [000372] *--X---N---- +--* IND long N004 ( 1, 1) [000369] ------------ | \--* LCL_VAR byref V02 arg2 u:1 (last use) N003 ( 21, 10) [000371] --CXG------- \--* CALLV ind long FloatingPointType.get_Zero N002 ( 1, 1) [000370] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 (last use) ***** BB22 STMT00110 (IL ???... ???) N002 ( 2, 2) [000524] ------------ * RETURN int N001 ( 1, 1) [000374] ------------ \--* CNS_INT int 2 ------------ BB23 [0E3..117) -> BB25 (cond), preds={BB20,BB21} succs={BB24,BB25} ***** BB23 STMT00028 (IL ???... ???) N028 ( 53, 37) [000120] SACXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger N004 ( 7, 6) [000623] -A------R-L- arg0 SETUP +--* ASG long N003 ( 3, 2) [000622] D------N---- | +--* LCL_VAR long V79 tmp49 d:2 N002 ( 3, 3) [000125] ------------ | \--* ADDR long N001 ( 3, 2) [000124] ----G--N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 N020 ( 14, 13) [000621] -A--------L- arg1 SETUP +--* COMMA void N013 ( 8, 7) [000614] -A---------- | +--* COMMA void N008 ( 3, 3) [000609] -A------R--- | | +--* ASG byref N007 ( 1, 1) [000608] D------N---- | | | +--* LCL_VAR byref V78 tmp48 d:2 N006 ( 3, 3) [000606] ------------ | | | \--* ADDR byref N005 ( 3, 2) [000607] ----G--N---- | | | \--* LCL_VAR struct(AX) V73 tmp43 N012 ( 5, 4) [000613] -A---------- | | \--* ASG ref N010 ( 3, 2) [000611] *------N---- | | +--* IND ref N009 ( 1, 1) [000610] ------------ | | | \--* LCL_VAR byref V78 tmp48 u:2 Zero Fseq[Mantissa] N011 ( 1, 1) [000612] -------N---- | | \--* LCL_VAR ref V52 tmp22 u:2 (last use) N019 ( 6, 6) [000620] -A---------- | \--* ASG int N017 ( 4, 4) [000618] *------N---- | +--* IND int N016 ( 2, 2) [000617] -------N---- | | \--* ADD byref N014 ( 1, 1) [000615] ------------ | | +--* LCL_VAR byref V78 tmp48 u:2 (last use) N015 ( 1, 1) [000616] ------------ | | \--* CNS_INT long 8 Fseq[Exponent] N018 ( 1, 1) [000619] -------N---- | \--* LCL_VAR int V53 tmp23 u:2 (last use) N023 ( 3, 2) [000624] ------------ arg0 in rcx +--* LCL_VAR long V79 tmp49 u:2 (last use) N025 ( 3, 3) [000626] ------------ arg1 in rdx +--* ADDR byref N024 ( 3, 2) [000625] -------N---- | \--* LCL_VAR struct(AX) V73 tmp43 N026 ( 3, 2) [000118] ------------ arg2 in r8 +--* LCL_VAR int V08 loc5 u:2 (last use) N027 ( 3, 2) [000119] ------------ arg3 in r9 \--* LCL_VAR int V09 loc6 u:2 (last use) ***** BB23 STMT00029 (IL 0x0EF...0x0F4) N005 ( 17, 21) [000133] H-CXG------- * CALL help long HELPER.CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE N003 ( 2, 10) [000131] ------------ arg0 in rcx +--* CNS_INT long 0x7ff815262aa0 N004 ( 1, 4) [000132] ------------ arg1 in rdx \--* CNS_INT int 173 ***** BB23 STMT00030 (IL ???... ???) N018 ( 21, 26) [000649] -A-XG------- * COMMA void N011 ( 13, 19) [000642] -A-XG------- +--* COMMA void N006 ( 6, 14) [000637] -A--G---R--- | +--* ASG byref N005 ( 1, 1) [000636] D------N---- | | +--* LCL_VAR byref V80 tmp50 d:2 N004 ( 6, 14) [000632] ----G------- | | \--* ADD byref N002 ( 4, 12) [000633] n---G------- | | +--* IND ref N001 ( 2, 10) [000634] I----------- | | | \--* CNS_INT(h) long 0xd1ffab1e static Fseq[BigOne] N003 ( 1, 1) [000635] ------------ | | \--* CNS_INT long 8 Fseq[#FirstElem] N010 ( 7, 5) [000641] -A-XG---R--- | \--* ASG ref N009 ( 3, 2) [000638] D---G--N---- | +--* LCL_VAR ref (AX) V58 tmp28 N008 ( 3, 2) [000640] ---X-------- | \--* IND ref N007 ( 1, 1) [000639] ------------ | \--* LCL_VAR byref V80 tmp50 u:2 Zero Fseq[_bits] N017 ( 8, 7) [000648] -A-XG---R--- \--* ASG int N016 ( 3, 2) [000643] D---G--N---- +--* LCL_VAR int (AX) V59 tmp29 N015 ( 4, 4) [000647] ---X-------- \--* IND int N014 ( 2, 2) [000646] -------N---- \--* ADD byref N012 ( 1, 1) [000644] ------------ +--* LCL_VAR byref V80 tmp50 u:2 (last use) N013 ( 1, 1) [000645] ------------ \--* CNS_INT long 8 Fseq[_sign] ***** BB23 STMT00031 (IL 0x0F6...0x106) N006 ( 20, 12) [000141] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen N004 ( 3, 3) [000139] ------------ arg0 in rcx +--* ADDR long N003 ( 3, 2) [000138] ----G--N---- | \--* LCL_VAR struct(AX)(P) V16 loc13 | \--* ref V16._bits (offs=0x00) -> V58 tmp28 | \--* int V16._sign (offs=0x08) -> V59 tmp29 N005 ( 3, 2) [000140] ------------ arg1 in rdx \--* LCL_VAR int V14 loc11 u:2 (last use) ***** BB23 STMT00099 (IL 0x0FF... ???) N007 ( 14, 10) [000658] -A--G------- * COMMA void N003 ( 7, 5) [000654] -A--G---R--- +--* ASG ref N002 ( 3, 2) [000652] D------N---- | +--* LCL_VAR ref V64 tmp34 d:2 N001 ( 3, 2) [000653] ----G--N---- | \--* LCL_VAR ref (AX) V56 tmp26 N006 ( 7, 5) [000657] -A--G---R--- \--* ASG int N005 ( 3, 2) [000655] D------N---- +--* LCL_VAR int V65 tmp35 d:2 N004 ( 3, 2) [000656] ----G--N---- \--* LCL_VAR int (AX) V57 tmp27 ***** BB23 STMT00098 (IL 0x0FF... ???) N023 ( 45, 31) [000468] -ACXG---R--- * ASG int N022 ( 3, 2) [000467] D------N---- +--* LCL_VAR int V43 tmp13 d:2 N021 ( 41, 28) [000463] -ACXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits N016 ( 18, 15) [000677] -A--------L- arg0 SETUP +--* COMMA void N009 ( 10, 8) [000670] -A---------- | +--* COMMA void N004 ( 3, 3) [000665] -A------R--- | | +--* ASG byref N003 ( 1, 1) [000664] D------N---- | | | +--* LCL_VAR byref V81 tmp51 d:2 N002 ( 3, 3) [000662] ------------ | | | \--* ADDR byref N001 ( 3, 2) [000663] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 N008 ( 7, 5) [000669] -A---------- | | \--* ASG ref N006 ( 3, 2) [000667] *------N---- | | +--* IND ref N005 ( 1, 1) [000666] ------------ | | | \--* LCL_VAR byref V81 tmp51 u:2 Zero Fseq[_bits] N007 ( 3, 2) [000668] -------N---- | | \--* LCL_VAR ref V64 tmp34 u:2 (last use) N015 ( 8, 7) [000676] -A---------- | \--* ASG int N013 ( 4, 4) [000674] *------N---- | +--* IND int N012 ( 2, 2) [000673] -------N---- | | \--* ADD byref N010 ( 1, 1) [000671] ------------ | | +--* LCL_VAR byref V81 tmp51 u:2 (last use) N011 ( 1, 1) [000672] ------------ | | \--* CNS_INT long 8 Fseq[_sign] N014 ( 3, 2) [000675] -------N---- | \--* LCL_VAR int V65 tmp35 u:2 (last use) N019 ( 3, 3) [000679] ------------ arg0 in rcx +--* ADDR byref N018 ( 3, 2) [000678] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 N020 ( 3, 3) [000462] ------------ arg1 in rdx \--* LCL_VAR_ADDR long V45 tmp15 ***** BB23 STMT00100 (IL 0x0FF... ???) N003 ( 5, 4) [000475] -A--G---R--- * ASG ref N002 ( 3, 2) [000474] D---G--N---- +--* LCL_VAR ref (AX) V45 tmp15 N001 ( 1, 1) [000473] ------------ \--* CNS_INT ref null ***** BB23 STMT00033 (IL ???... ???) N003 ( 7, 5) [000148] -A------R--- * ASG int N002 ( 3, 2) [000147] D------N---- +--* LCL_VAR int V17 loc14 d:2 N001 ( 3, 2) [000469] ------------ \--* LCL_VAR int V43 tmp13 u:2 ***** BB23 STMT00103 (IL 0x108... ???) N007 ( 14, 10) [000687] -A--G------- * COMMA void N003 ( 7, 5) [000683] -A--G---R--- +--* ASG ref N002 ( 3, 2) [000681] D------N---- | +--* LCL_VAR ref V66 tmp36 d:2 N001 ( 3, 2) [000682] ----G--N---- | \--* LCL_VAR ref (AX) V58 tmp28 N006 ( 7, 5) [000686] -A--G---R--- \--* ASG int N005 ( 3, 2) [000684] D------N---- +--* LCL_VAR int V67 tmp37 d:2 N004 ( 3, 2) [000685] ----G--N---- \--* LCL_VAR int (AX) V59 tmp29 ***** BB23 STMT00102 (IL 0x108... ???) N023 ( 45, 31) [000486] -ACXG---R--- * ASG int N022 ( 3, 2) [000485] D------N---- +--* LCL_VAR int V46 tmp16 d:2 N021 ( 41, 28) [000481] -ACXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits N016 ( 18, 15) [000706] -A--------L- arg0 SETUP +--* COMMA void N009 ( 10, 8) [000699] -A---------- | +--* COMMA void N004 ( 3, 3) [000694] -A------R--- | | +--* ASG byref N003 ( 1, 1) [000693] D------N---- | | | +--* LCL_VAR byref V82 tmp52 d:2 N002 ( 3, 3) [000691] ------------ | | | \--* ADDR byref N001 ( 3, 2) [000692] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 N008 ( 7, 5) [000698] -A---------- | | \--* ASG ref N006 ( 3, 2) [000696] *------N---- | | +--* IND ref N005 ( 1, 1) [000695] ------------ | | | \--* LCL_VAR byref V82 tmp52 u:2 Zero Fseq[_bits] N007 ( 3, 2) [000697] -------N---- | | \--* LCL_VAR ref V66 tmp36 u:2 (last use) N015 ( 8, 7) [000705] -A---------- | \--* ASG int N013 ( 4, 4) [000703] *------N---- | +--* IND int N012 ( 2, 2) [000702] -------N---- | | \--* ADD byref N010 ( 1, 1) [000700] ------------ | | +--* LCL_VAR byref V82 tmp52 u:2 (last use) N011 ( 1, 1) [000701] ------------ | | \--* CNS_INT long 8 Fseq[_sign] N014 ( 3, 2) [000704] -------N---- | \--* LCL_VAR int V67 tmp37 u:2 (last use) N019 ( 3, 3) [000708] ------------ arg0 in rcx +--* ADDR byref N018 ( 3, 2) [000707] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 N020 ( 3, 3) [000480] ------------ arg1 in rdx \--* LCL_VAR_ADDR long V48 tmp18 ***** BB23 STMT00104 (IL 0x108... ???) N003 ( 5, 4) [000493] -A--G---R--- * ASG ref N002 ( 3, 2) [000492] D---G--N---- +--* LCL_VAR ref (AX) V48 tmp18 N001 ( 1, 1) [000491] ------------ \--* CNS_INT ref null ***** BB23 STMT00035 (IL ???... ???) N003 ( 7, 5) [000155] -A------R--- * ASG int N002 ( 3, 2) [000154] D------N---- +--* LCL_VAR int V18 loc15 d:2 N001 ( 3, 2) [000487] ------------ \--* LCL_VAR int V46 tmp16 u:2 ***** BB23 STMT00036 (IL 0x111...0x115) N004 ( 9, 7) [000159] ------------ * JTRUE void N003 ( 7, 5) [000158] N------N-U-- \--* GT int N001 ( 3, 2) [000156] ------------ +--* LCL_VAR int V46 tmp16 u:2 (last use) N002 ( 3, 2) [000157] ------------ \--* LCL_VAR int V43 tmp13 u:2 (last use) ------------ BB24 [117..11A) -> BB26 (always), preds={BB23} succs={BB26} ***** BB24 STMT00074 (IL 0x117...0x118) N003 ( 5, 4) [000350] -A------R--- * ASG int N002 ( 3, 2) [000349] D------N---- +--* LCL_VAR int V33 tmp3 d:4 N001 ( 1, 1) [000348] ------------ \--* CNS_INT int 0 ------------ BB25 [11A..11F), preds={BB23} succs={BB26} ***** BB25 STMT00037 (IL 0x11A...0x11E) N005 ( 11, 8) [000164] -A------R--- * ASG int N004 ( 3, 2) [000163] D------N---- +--* LCL_VAR int V33 tmp3 d:3 N003 ( 7, 5) [000162] ------------ \--* SUB int N001 ( 3, 2) [000160] ------------ +--* LCL_VAR int V18 loc15 u:2 (last use) N002 ( 3, 2) [000161] ------------ \--* LCL_VAR int V17 loc14 u:2 (last use) ------------ BB26 [11F..126) -> BB28 (cond), preds={BB24,BB25} succs={BB27,BB28} ***** BB26 STMT00119 (IL ???... ???) N005 ( 0, 0) [000877] -A------R--- * ASG int N004 ( 0, 0) [000875] D------N---- +--* LCL_VAR int V33 tmp3 d:2 N003 ( 0, 0) [000876] ------------ \--* PHI int N001 ( 0, 0) [000903] ------------ pred BB24 +--* PHI_ARG int V33 tmp3 u:4 N002 ( 0, 0) [000902] ------------ pred BB25 \--* PHI_ARG int V33 tmp3 u:3 ***** BB26 STMT00038 (IL ???...0x11F) N003 ( 3, 3) [000168] -A------R--- * ASG int N002 ( 1, 1) [000167] D------N---- +--* LCL_VAR int V19 loc16 d:2 N001 ( 3, 2) [000166] ------------ \--* LCL_VAR int V33 tmp3 u:2 ***** BB26 STMT00039 (IL 0x121...0x124) N004 ( 7, 6) [000172] ------------ * JTRUE void N003 ( 5, 4) [000171] N------N---- \--* EQ int N001 ( 3, 2) [000169] ------------ +--* LCL_VAR int V33 tmp3 u:2 (last use) N002 ( 1, 1) [000170] ------------ \--* CNS_INT int 0 ------------ BB27 [126..12F), preds={BB26} succs={BB28} ***** BB27 STMT00073 (IL 0x126...0x12A) N006 ( 18, 11) [000347] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft N004 ( 3, 3) [000345] ------------ arg0 in rcx +--* ADDR long N003 ( 3, 2) [000344] ----G--N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 N005 ( 1, 1) [000346] ------------ arg1 in rdx \--* LCL_VAR int V19 loc16 u:2 ------------ BB28 [12F..13E) -> BB32 (cond), preds={BB26,BB27} succs={BB29,BB32} ***** BB28 STMT00040 (IL 0x12F...0x133) N005 ( 9, 7) [000177] -A------R--- * ASG int N004 ( 3, 2) [000176] D------N---- +--* LCL_VAR int V20 loc17 d:2 N003 ( 5, 4) [000175] ------------ \--* SUB int N001 ( 3, 2) [000173] ------------ +--* LCL_VAR int V03 loc0 u:2 (last use) N002 ( 1, 1) [000174] ------------ \--* LCL_VAR int V13 loc10 u:2 ***** BB28 STMT00041 (IL 0x135...0x137) N003 ( 7, 5) [000180] -A------R--- * ASG int N002 ( 3, 2) [000179] D------N---- +--* LCL_VAR int V21 loc18 d:2 N001 ( 3, 2) [000178] ------------ \--* LCL_VAR int V20 loc17 u:2 ***** BB28 STMT00042 (IL 0x139...0x13C) N004 ( 5, 5) [000184] ------------ * JTRUE void N003 ( 3, 3) [000183] N------N---- \--* EQ int N001 ( 1, 1) [000181] ------------ +--* LCL_VAR int V13 loc10 u:2 N002 ( 1, 1) [000182] ------------ \--* CNS_INT int 0 ------------ BB29 [13E..144) -> BB31 (cond), preds={BB28} succs={BB30,BB31} ***** BB29 STMT00070 (IL 0x13E...0x142) N004 ( 7, 6) [000329] ------------ * JTRUE void N003 ( 5, 4) [000328] N------N-U-- \--* LE int N001 ( 1, 1) [000326] ------------ +--* LCL_VAR int V19 loc16 u:2 N002 ( 3, 2) [000327] ------------ \--* LCL_VAR int V21 loc18 u:2 ------------ BB30 [144..155) -> BB44 (always), preds={BB29} succs={BB44} ***** BB30 STMT00072 (IL 0x144...0x154) N014 ( 29, 17) [000717] -ACXG---R--- * ASG int N013 ( 1, 1) [000716] D------N---- +--* LCL_VAR int V51 tmp21 d:5 N012 ( 29, 17) [000342] --CXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits N005 ( 1, 1) [000341] ------------ arg4 out+20 +--* LCL_VAR byref V02 arg2 u:1 (last use) N008 ( 6, 3) [000339] N----------- arg2 in r8 +--* NE int N006 ( 1, 1) [000337] ------------ | +--* LCL_VAR int V10 loc7 u:2 (last use) N007 ( 1, 1) [000338] ------------ | \--* CNS_INT int 0 N009 ( 3, 2) [000335] ----G------- arg0 in rcx +--* LCL_VAR ref (AX) V12 loc9 N010 ( 1, 1) [000336] ------------ arg1 in rdx +--* LCL_VAR int V13 loc10 u:2 (last use) N011 ( 1, 1) [000340] ------------ arg3 in r9 \--* LCL_VAR ref V01 arg1 u:1 (last use) ------------ BB31 [155..15C), preds={BB29} succs={BB32} ***** BB31 STMT00071 (IL 0x155...0x15A) N005 ( 9, 7) [000334] -A------R--- * ASG int N004 ( 3, 2) [000333] D------N---- +--* LCL_VAR int V21 loc18 d:4 N003 ( 5, 4) [000332] ------------ \--* SUB int N001 ( 3, 2) [000330] ------------ +--* LCL_VAR int V21 loc18 u:2 (last use) N002 ( 1, 1) [000331] ------------ \--* LCL_VAR int V19 loc16 u:2 ------------ BB32 [15C..167) -> BB34 (cond), preds={BB28,BB31} succs={BB33,BB34} ***** BB32 STMT00118 (IL ???... ???) N005 ( 0, 0) [000874] -A------R--- * ASG int N004 ( 0, 0) [000872] D------N---- +--* LCL_VAR int V21 loc18 d:3 N003 ( 0, 0) [000873] ------------ \--* PHI int N001 ( 0, 0) [000900] ------------ pred BB31 +--* PHI_ARG int V21 loc18 u:4 N002 ( 0, 0) [000888] ------------ pred BB28 \--* PHI_ARG int V21 loc18 u:2 ***** BB32 STMT00105 (IL 0x15C... ???) N007 ( 14, 10) [000724] -A--G------- * COMMA void N003 ( 7, 5) [000720] -A--G---R--- +--* ASG ref N002 ( 3, 2) [000718] D---G--N---- | +--* LCL_VAR ref (AX) V68 tmp38 N001 ( 3, 2) [000719] ----G--N---- | \--* LCL_VAR ref (AX) V56 tmp26 N006 ( 7, 5) [000723] -A--G---R--- \--* ASG int N005 ( 3, 2) [000721] D---G--N---- +--* LCL_VAR int (AX) V69 tmp39 N004 ( 3, 2) [000722] ----G--N---- \--* LCL_VAR int (AX) V57 tmp27 ***** BB32 STMT00106 (IL 0x15C... ???) N007 ( 14, 10) [000731] -A--G------- * COMMA void N003 ( 7, 5) [000727] -A--G---R--- +--* ASG ref N002 ( 3, 2) [000725] D------N---- | +--* LCL_VAR ref V70 tmp40 d:2 N001 ( 3, 2) [000726] ----G--N---- | \--* LCL_VAR ref (AX) V58 tmp28 N006 ( 7, 5) [000730] -A--G---R--- \--* ASG int N005 ( 3, 2) [000728] D------N---- +--* LCL_VAR int V71 tmp41 d:2 N004 ( 3, 2) [000729] ----G--N---- \--* LCL_VAR int (AX) V59 tmp29 ***** BB32 STMT00044 (IL ???... ???) N027 ( 52, 38) [000195] -ACXG------- * JTRUE void N026 ( 50, 36) [000503] JACXG--N---- \--* LT int N024 ( 48, 34) [000499] -ACXG------- +--* CALL int System.Numerics.BigInteger.CompareTo N004 ( 7, 6) [000752] -A------R-L- this SETUP | +--* ASG byref N003 ( 3, 2) [000751] D------N---- | | +--* LCL_VAR byref V84 tmp54 d:2 N002 ( 3, 3) [000497] ------------ | | \--* ADDR byref N001 ( 3, 2) [000496] ----G--N---- | | \--* LCL_VAR struct(AX)(P) V49 tmp19 | | \--* ref V49._bits (offs=0x00) -> V68 tmp38 | | \--* int V49._sign (offs=0x08) -> V69 tmp39 N020 ( 18, 15) [000750] -A--------L- arg1 SETUP | +--* COMMA void N013 ( 10, 8) [000743] -A---------- | | +--* COMMA void N008 ( 3, 3) [000738] -A------R--- | | | +--* ASG byref N007 ( 1, 1) [000737] D------N---- | | | | +--* LCL_VAR byref V83 tmp53 d:2 N006 ( 3, 3) [000735] ------------ | | | | \--* ADDR byref N005 ( 3, 2) [000736] ----G--N---- | | | | \--* LCL_VAR struct(AX) V76 tmp46 N012 ( 7, 5) [000742] -A---------- | | | \--* ASG ref N010 ( 3, 2) [000740] *------N---- | | | +--* IND ref N009 ( 1, 1) [000739] ------------ | | | | \--* LCL_VAR byref V83 tmp53 u:2 Zero Fseq[_bits] N011 ( 3, 2) [000741] -------N---- | | | \--* LCL_VAR ref V70 tmp40 u:2 (last use) N019 ( 8, 7) [000749] -A---------- | | \--* ASG int N017 ( 4, 4) [000747] *------N---- | | +--* IND int N016 ( 2, 2) [000746] -------N---- | | | \--* ADD byref N014 ( 1, 1) [000744] ------------ | | | +--* LCL_VAR byref V83 tmp53 u:2 (last use) N015 ( 1, 1) [000745] ------------ | | | \--* CNS_INT long 8 Fseq[_sign] N018 ( 3, 2) [000748] -------N---- | | \--* LCL_VAR int V71 tmp41 u:2 (last use) N021 ( 3, 2) [000753] ------------ this in rcx | +--* LCL_VAR byref V84 tmp54 u:2 (last use) N023 ( 3, 3) [000755] ------------ arg1 in rdx | \--* ADDR byref N022 ( 3, 2) [000754] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 N025 ( 1, 1) [000502] ------------ \--* CNS_INT int 0 ------------ BB33 [167..16B) -> BB35 (always), preds={BB32} succs={BB35} ***** BB33 STMT00069 (IL 0x167...0x169) N003 ( 5, 4) [000324] -A------R--- * ASG int N002 ( 3, 2) [000323] D------N---- +--* LCL_VAR int V34 tmp4 d:4 N001 ( 1, 1) [000322] ------------ \--* LCL_VAR int V19 loc16 u:2 (last use) ------------ BB34 [16B..16F), preds={BB32} succs={BB35} ***** BB34 STMT00045 (IL 0x16B...0x16E) N005 ( 7, 6) [000200] -A------R--- * ASG int N004 ( 3, 2) [000199] D------N---- +--* LCL_VAR int V34 tmp4 d:3 N003 ( 3, 3) [000198] ------------ \--* ADD int N001 ( 1, 1) [000196] ------------ +--* LCL_VAR int V19 loc16 u:2 (last use) N002 ( 1, 1) [000197] ------------ \--* CNS_INT int 1 ------------ BB35 [16F..1A4) -> BB40 (cond), preds={BB33,BB34} succs={BB36,BB40} ***** BB35 STMT00117 (IL ???... ???) N005 ( 0, 0) [000871] -A------R--- * ASG int N004 ( 0, 0) [000869] D------N---- +--* LCL_VAR int V34 tmp4 d:2 N003 ( 0, 0) [000870] ------------ \--* PHI int N001 ( 0, 0) [000899] ------------ pred BB33 +--* PHI_ARG int V34 tmp4 u:4 N002 ( 0, 0) [000898] ------------ pred BB34 \--* PHI_ARG int V34 tmp4 u:3 ***** BB35 STMT00046 (IL ???...0x16F) N003 ( 7, 5) [000204] -A------R--- * ASG int N002 ( 3, 2) [000203] D------N---- +--* LCL_VAR int V22 loc19 d:2 N001 ( 3, 2) [000202] ------------ \--* LCL_VAR int V34 tmp4 u:2 (last use) ***** BB35 STMT00047 (IL 0x171...0x18A) N006 ( 20, 12) [000208] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft N004 ( 3, 3) [000206] ------------ arg0 in rcx +--* ADDR long N003 ( 3, 2) [000205] ----G--N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 N005 ( 3, 2) [000207] ------------ arg1 in rdx \--* LCL_VAR int V21 loc18 u:3 (last use) ***** BB35 STMT00048 (IL 0x17A... ???) N045 ( 78, 56) [000213] SACXG------- * CALL void System.Numerics.BigInteger.DivRem N004 ( 7, 6) [000797] -A------R-L- arg0 SETUP +--* ASG long N003 ( 3, 2) [000796] D------N---- | +--* LCL_VAR long V88 tmp58 d:2 N002 ( 3, 3) [000220] ------------ | \--* ADDR long N001 ( 3, 2) [000219] ----G--N---- | \--* LCL_VAR struct(AX)(P) V35 tmp5 | \--* ref V35._bits (offs=0x00) -> V62 tmp32 | \--* int V35._sign (offs=0x08) -> V63 tmp33 N020 ( 18, 15) [000776] -A--G-----L- arg1 SETUP +--* COMMA void N013 ( 10, 8) [000769] -A--G------- | +--* COMMA void N008 ( 3, 3) [000764] -A------R--- | | +--* ASG byref N007 ( 1, 1) [000763] D------N---- | | | +--* LCL_VAR byref V85 tmp55 d:2 N006 ( 3, 3) [000761] ------------ | | | \--* ADDR byref N005 ( 3, 2) [000762] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 N012 ( 7, 5) [000768] -A--G------- | | \--* ASG ref N010 ( 3, 2) [000766] *------N---- | | +--* IND ref N009 ( 1, 1) [000765] ------------ | | | \--* LCL_VAR byref V85 tmp55 u:2 Zero Fseq[_bits] N011 ( 3, 2) [000767] ----G--N---- | | \--* LCL_VAR ref (AX) V56 tmp26 N019 ( 8, 7) [000775] -A--G------- | \--* ASG int N017 ( 4, 4) [000773] *------N---- | +--* IND int N016 ( 2, 2) [000772] -------N---- | | \--* ADD byref N014 ( 1, 1) [000770] ------------ | | +--* LCL_VAR byref V85 tmp55 u:2 (last use) N015 ( 1, 1) [000771] ------------ | | \--* CNS_INT long 8 Fseq[_sign] N018 ( 3, 2) [000774] ----G--N---- | \--* LCL_VAR int (AX) V57 tmp27 N036 ( 18, 15) [000795] -A--G-----L- arg2 SETUP +--* COMMA void N029 ( 10, 8) [000788] -A--G------- | +--* COMMA void N024 ( 3, 3) [000783] -A------R--- | | +--* ASG byref N023 ( 1, 1) [000782] D------N---- | | | +--* LCL_VAR byref V87 tmp57 d:2 N022 ( 3, 3) [000780] ------------ | | | \--* ADDR byref N021 ( 3, 2) [000781] -------N---- | | | \--* LCL_VAR struct(AX) V86 tmp56 N028 ( 7, 5) [000787] -A--G------- | | \--* ASG ref N026 ( 3, 2) [000785] *------N---- | | +--* IND ref N025 ( 1, 1) [000784] ------------ | | | \--* LCL_VAR byref V87 tmp57 u:2 Zero Fseq[_bits] N027 ( 3, 2) [000786] ----G--N---- | | \--* LCL_VAR ref (AX) V58 tmp28 N035 ( 8, 7) [000794] -A--G------- | \--* ASG int N033 ( 4, 4) [000792] *------N---- | +--* IND int N032 ( 2, 2) [000791] -------N---- | | \--* ADD byref N030 ( 1, 1) [000789] ------------ | | +--* LCL_VAR byref V87 tmp57 u:2 (last use) N031 ( 1, 1) [000790] ------------ | | \--* CNS_INT long 8 Fseq[_sign] N034 ( 3, 2) [000793] ----G--N---- | \--* LCL_VAR int (AX) V59 tmp29 N038 ( 3, 2) [000798] ------------ arg0 in rcx +--* LCL_VAR long V88 tmp58 u:2 (last use) N040 ( 3, 3) [000800] ------------ arg1 in rdx +--* ADDR byref N039 ( 3, 2) [000799] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 N042 ( 3, 3) [000802] ------------ arg2 in r8 +--* ADDR byref N041 ( 3, 2) [000801] -------N---- | \--* LCL_VAR struct(AX) V86 tmp56 N044 ( 3, 3) [000212] ------------ arg3 in r9 \--* ADDR long N043 ( 3, 2) [000211] ----G--N---- \--* LCL_VAR struct(AX)(P) V23 loc20 \--* ref V23._bits (offs=0x00) -> V60 tmp30 \--* int V23._sign (offs=0x08) -> V61 tmp31 ***** BB35 STMT00050 (IL ???... ???) N021 ( 38, 24) [000226] -ACXG---R--- * ASG long N020 ( 1, 1) [000225] D------N---- +--* LCL_VAR long V24 loc21 d:2 N019 ( 38, 24) [000218] -ACXG------- \--* CALL long System.Numerics.BigInteger.op_Explicit N016 ( 18, 15) [000822] -A--G-----L- arg0 SETUP +--* COMMA void N009 ( 10, 8) [000815] -A--G------- | +--* COMMA void N004 ( 3, 3) [000810] -A------R--- | | +--* ASG byref N003 ( 1, 1) [000809] D------N---- | | | +--* LCL_VAR byref V89 tmp59 d:2 N002 ( 3, 3) [000807] ------------ | | | \--* ADDR byref N001 ( 3, 2) [000808] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 N008 ( 7, 5) [000814] -A--G------- | | \--* ASG ref N006 ( 3, 2) [000812] *------N---- | | +--* IND ref N005 ( 1, 1) [000811] ------------ | | | \--* LCL_VAR byref V89 tmp59 u:2 Zero Fseq[_bits] N007 ( 3, 2) [000813] ----G--N---- | | \--* LCL_VAR ref (AX) V62 tmp32 N015 ( 8, 7) [000821] -A--G------- | \--* ASG int N013 ( 4, 4) [000819] *------N---- | +--* IND int N012 ( 2, 2) [000818] -------N---- | | \--* ADD byref N010 ( 1, 1) [000816] ------------ | | +--* LCL_VAR byref V89 tmp59 u:2 (last use) N011 ( 1, 1) [000817] ------------ | | \--* CNS_INT long 8 Fseq[_sign] N014 ( 3, 2) [000820] ----G--N---- | \--* LCL_VAR int (AX) V63 tmp33 N018 ( 3, 3) [000824] ------------ arg0 in rcx \--* ADDR byref N017 ( 3, 2) [000823] -------N---- \--* LCL_VAR struct(AX) V76 tmp46 ***** BB35 STMT00052 (IL ???... ???) N005 ( 12, 7) [000232] -A--G---R--- * ASG int N004 ( 3, 2) [000231] D------N---- +--* LCL_VAR int V25 loc22 d:2 N003 ( 8, 4) [000516] ----G------- \--* EQ int N001 ( 3, 2) [000514] ----G------- +--* LCL_VAR int (AX) V61 tmp31 N002 ( 1, 1) [000515] ------------ \--* CNS_INT int 0 ***** BB35 STMT00054 (IL ???... ???) N005 ( 19, 10) [000237] -ACXG---R--- * ASG int N004 ( 3, 2) [000236] D------N---- +--* LCL_VAR int V26 loc23 d:2 N003 ( 15, 7) [000234] --CXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits N002 ( 1, 1) [000233] ------------ arg0 in rcx \--* LCL_VAR long V24 loc21 u:2 ***** BB35 STMT00055 (IL 0x19E...0x1A2) N004 ( 9, 7) [000241] ------------ * JTRUE void N003 ( 7, 5) [000240] N------N-U-- \--* LE int N001 ( 3, 2) [000238] ------------ +--* LCL_VAR int V26 loc23 u:2 N002 ( 3, 2) [000239] ------------ \--* LCL_VAR int V20 loc17 u:2 ------------ BB36 [1A4..1AF) -> BB38 (cond), preds={BB35} succs={BB37,BB38} ***** BB36 STMT00063 (IL 0x1A4...0x1A9) N005 ( 11, 8) [000286] -A------R--- * ASG int N004 ( 3, 2) [000285] D------N---- +--* LCL_VAR int V29 loc26 d:2 N003 ( 7, 5) [000284] ------------ \--* SUB int N001 ( 3, 2) [000282] ------------ +--* LCL_VAR int V26 loc23 u:2 (last use) N002 ( 3, 2) [000283] ------------ \--* LCL_VAR int V20 loc17 u:2 ***** BB36 STMT00064 (IL 0x1AB...0x1AD) N004 ( 7, 6) [000290] ------------ * JTRUE void N003 ( 5, 4) [000289] J------N---- \--* EQ int N001 ( 3, 2) [000287] ------------ +--* LCL_VAR int V25 loc22 u:2 (last use) N002 ( 1, 1) [000288] ------------ \--* CNS_INT int 0 ------------ BB37 [1AF..1C3) -> BB39 (always), preds={BB36} succs={BB39} ***** BB37 STMT00068 (IL 0x1AF...0x1C1) N013 ( 23, 15) [000320] -A------R--- * ASG int N012 ( 3, 2) [000319] D------N---- +--* LCL_VAR int V37 tmp7 d:4 N011 ( 19, 12) [000318] ------------ \--* EQ int N009 ( 14, 10) [000315] ------------ +--* AND long N001 ( 1, 1) [000305] ------------ | +--* LCL_VAR long V24 loc21 u:2 N008 ( 12, 8) [000314] ------------ | \--* ADD long N006 ( 10, 6) [000311] --------R--- | +--* LSH long N005 ( 1, 1) [000307] ------------ | | +--* CNS_INT long 1 N004 ( 5, 4) [000310] ------------ | | \--* AND int N002 ( 3, 2) [000308] ------------ | | +--* LCL_VAR int V29 loc26 u:2 N003 ( 1, 1) [000309] ------------ | | \--* CNS_INT int 63 N007 ( 1, 1) [000313] ------------ | \--* CNS_INT long -1 N010 ( 1, 1) [000317] ------------ \--* CNS_INT long 0 ------------ BB38 [1C3..1C4), preds={BB36} succs={BB39} ***** BB38 STMT00065 (IL 0x1C3...0x1C3) N003 ( 5, 4) [000293] -A------R--- * ASG int N002 ( 3, 2) [000292] D------N---- +--* LCL_VAR int V37 tmp7 d:3 N001 ( 1, 1) [000291] ------------ \--* CNS_INT int 0 ------------ BB39 [1C4..1D0), preds={BB37,BB38} succs={BB40} ***** BB39 STMT00116 (IL ???... ???) N005 ( 0, 0) [000868] -A------R--- * ASG int N004 ( 0, 0) [000866] D------N---- +--* LCL_VAR int V37 tmp7 d:2 N003 ( 0, 0) [000867] ------------ \--* PHI int N001 ( 0, 0) [000897] ------------ pred BB37 +--* PHI_ARG int V37 tmp7 u:4 N002 ( 0, 0) [000896] ------------ pred BB38 \--* PHI_ARG int V37 tmp7 u:3 ***** BB39 STMT00066 (IL ???...0x1C4) N004 ( 8, 7) [000297] -A------R--- * ASG int N003 ( 3, 2) [000296] D------N---- +--* LCL_VAR int V25 loc22 d:4 N002 ( 4, 4) [000826] ------------ \--* CAST int <- bool <- int N001 ( 3, 2) [000295] ------------ \--* LCL_VAR int V37 tmp7 u:2 (last use) ***** BB39 STMT00067 (IL 0x1C6...0x1CE) N007 ( 10, 6) [000304] -A------R--- * ASG long N006 ( 1, 1) [000303] D------N---- +--* LCL_VAR long V24 loc21 d:4 N005 ( 10, 6) [000302] ------------ \--* RSZ long N001 ( 1, 1) [000298] ------------ +--* LCL_VAR long V24 loc21 u:2 (last use) N004 ( 5, 4) [000301] ------------ \--* AND int N002 ( 3, 2) [000299] ------------ +--* LCL_VAR int V29 loc26 u:2 (last use) N003 ( 1, 1) [000300] ------------ \--* CNS_INT int 63 ------------ BB40 [1D0..1E7) -> BB42 (cond), preds={BB35,BB39} succs={BB41,BB42} ***** BB40 STMT00115 (IL ???... ???) N005 ( 0, 0) [000865] -A------R--- * ASG bool N004 ( 0, 0) [000863] D------N---- +--* LCL_VAR bool V25 loc22 d:3 N003 ( 0, 0) [000864] ------------ \--* PHI bool N001 ( 0, 0) [000894] ------------ pred BB39 +--* PHI_ARG bool V25 loc22 u:4 N002 ( 0, 0) [000889] ------------ pred BB35 \--* PHI_ARG bool V25 loc22 u:2 ***** BB40 STMT00114 (IL ???... ???) N005 ( 0, 0) [000862] -A------R--- * ASG long N004 ( 0, 0) [000860] D------N---- +--* LCL_VAR long V24 loc21 d:3 N003 ( 0, 0) [000861] ------------ \--* PHI long N001 ( 0, 0) [000895] ------------ pred BB39 +--* PHI_ARG long V24 loc21 u:4 N002 ( 0, 0) [000890] ------------ pred BB35 \--* PHI_ARG long V24 loc21 u:2 ***** BB40 STMT00057 (IL ???... ???) N027 ( 53, 34) [000254] -ACXG---R--- * ASG long N026 ( 3, 2) [000253] D------N---- +--* LCL_VAR long V27 loc24 d:2 N025 ( 49, 31) [000252] -ACXG------- \--* ADD long N023 ( 47, 29) [000250] -ACXG------- +--* LSH long N019 ( 38, 24) [000243] -ACXG------- | +--* CALL long System.Numerics.BigInteger.op_Explicit N016 ( 18, 15) [000845] -A--G-----L- arg0 SETUP | | +--* COMMA void N009 ( 10, 8) [000838] -A--G------- | | | +--* COMMA void N004 ( 3, 3) [000833] -A------R--- | | | | +--* ASG byref N003 ( 1, 1) [000832] D------N---- | | | | | +--* LCL_VAR byref V90 tmp60 d:2 N002 ( 3, 3) [000830] ------------ | | | | | \--* ADDR byref N001 ( 3, 2) [000831] ----G--N---- | | | | | \--* LCL_VAR struct(AX) V76 tmp46 N008 ( 7, 5) [000837] -A--G------- | | | | \--* ASG ref N006 ( 3, 2) [000835] *------N---- | | | | +--* IND ref N005 ( 1, 1) [000834] ------------ | | | | | \--* LCL_VAR byref V90 tmp60 u:2 Zero Fseq[_bits] N007 ( 3, 2) [000836] ----G--N---- | | | | \--* LCL_VAR ref (AX) V54 tmp24 N015 ( 8, 7) [000844] -A--G------- | | | \--* ASG int N013 ( 4, 4) [000842] *------N---- | | | +--* IND int N012 ( 2, 2) [000841] -------N---- | | | | \--* ADD byref N010 ( 1, 1) [000839] ------------ | | | | +--* LCL_VAR byref V90 tmp60 u:2 (last use) N011 ( 1, 1) [000840] ------------ | | | | \--* CNS_INT long 8 Fseq[_sign] N014 ( 3, 2) [000843] ----G--N---- | | | \--* LCL_VAR int (AX) V55 tmp25 N018 ( 3, 3) [000847] ------------ arg0 in rcx | | \--* ADDR byref N017 ( 3, 2) [000846] -------N---- | | \--* LCL_VAR struct(AX) V76 tmp46 N022 ( 5, 4) [000249] ------------ | \--* AND int N020 ( 3, 2) [000247] ------------ | +--* LCL_VAR int V20 loc17 u:2 (last use) N021 ( 1, 1) [000248] ------------ | \--* CNS_INT int 63 N024 ( 1, 1) [000251] ------------ \--* LCL_VAR long V24 loc21 u:3 (last use) ***** BB40 STMT00058 (IL 0x1E2...0x1E5) N004 ( 5, 5) [000258] ------------ * JTRUE void N003 ( 3, 3) [000257] N------N---- \--* NE int N001 ( 1, 1) [000255] ------------ +--* LCL_VAR int V13 loc10 u:2 N002 ( 1, 1) [000256] ------------ \--* CNS_INT int 0 ------------ BB41 [1E7..1EE) -> BB43 (always), preds={BB40} succs={BB43} ***** BB41 STMT00062 (IL 0x1E7...0x1EC) N006 ( 10, 8) [000280] -A------R--- * ASG int N005 ( 3, 2) [000279] D------N---- +--* LCL_VAR int V36 tmp6 d:4 N004 ( 6, 5) [000278] ------------ \--* ADD int N002 ( 4, 3) [000276] ------------ +--* NEG int N001 ( 3, 2) [000275] ------------ | \--* LCL_VAR int V22 loc19 u:2 (last use) N003 ( 1, 1) [000277] ------------ \--* CNS_INT int -1 ------------ BB42 [1EE..1F2), preds={BB40} succs={BB43} ***** BB42 STMT00059 (IL 0x1EE...0x1F1) N005 ( 7, 6) [000263] -A------R--- * ASG int N004 ( 3, 2) [000262] D------N---- +--* LCL_VAR int V36 tmp6 d:3 N003 ( 3, 3) [000261] ------------ \--* ADD int N001 ( 1, 1) [000259] ------------ +--* LCL_VAR int V13 loc10 u:2 (last use) N002 ( 1, 1) [000260] ------------ \--* CNS_INT int -2 ------------ BB43 [1F2..202), preds={BB41,BB42} succs={BB44} ***** BB43 STMT00113 (IL ???... ???) N005 ( 0, 0) [000859] -A------R--- * ASG int N004 ( 0, 0) [000857] D------N---- +--* LCL_VAR int V36 tmp6 d:2 N003 ( 0, 0) [000858] ------------ \--* PHI int N001 ( 0, 0) [000893] ------------ pred BB41 +--* PHI_ARG int V36 tmp6 u:4 N002 ( 0, 0) [000892] ------------ pred BB42 \--* PHI_ARG int V36 tmp6 u:3 ***** BB43 STMT00061 (IL 0x1F4...0x201) N012 ( 28, 18) [000853] -ACXG---R--- * ASG int N011 ( 1, 1) [000852] D------N---- +--* LCL_VAR int V51 tmp21 d:4 N010 ( 28, 18) [000273] --CXG------- \--* CALL nullcheck int FloatingPointType.AssembleFloatingPointValue N005 ( 1, 1) [000272] ------------ arg4 out+20 +--* LCL_VAR byref V02 arg2 u:1 (last use) N006 ( 1, 1) [000268] ------------ this in rcx +--* LCL_VAR ref V01 arg1 u:1 (last use) N007 ( 3, 2) [000269] ------------ arg1 in rdx +--* LCL_VAR long V27 loc24 u:2 (last use) N008 ( 3, 2) [000270] ------------ arg2 in r8 +--* LCL_VAR int V36 tmp6 u:2 (last use) N009 ( 3, 2) [000271] ------------ arg3 in r9 \--* LCL_VAR int V25 loc22 u:3 (last use) ------------ BB44 [???..???) (return), preds={BB16,BB30,BB43} succs={} ***** BB44 STMT00112 (IL ???... ???) N006 ( 0, 0) [000856] -A------R--- * ASG int N005 ( 0, 0) [000854] D------N---- +--* LCL_VAR int V51 tmp21 d:2 N004 ( 0, 0) [000855] ------------ \--* PHI int N001 ( 0, 0) [000901] ------------ pred BB30 +--* PHI_ARG int V51 tmp21 u:5 N002 ( 0, 0) [000891] ------------ pred BB43 +--* PHI_ARG int V51 tmp21 u:4 N003 ( 0, 0) [000887] ------------ pred BB16 \--* PHI_ARG int V51 tmp21 u:3 ***** BB44 STMT00109 (IL ???... ???) N002 ( 2, 2) [000523] ------------ * RETURN int N001 ( 1, 1) [000522] -------N---- \--* LCL_VAR int V51 tmp21 u:2 (last use) ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Starting PHASE Early Value Propagation *************** In optEarlyProp() After optEarlyProp: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0056] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..00D)-> BB04 ( cond ) i label target idxlen BB03 [0001] 1 BB02 0.50 [00D..017) (return) i hascall gcsafe BB04 [0002] 1 BB02 0.50 [017..065)-> BB06 ( cond ) i label target hascall gcsafe BB05 [0038] 1 BB04 0.50 [020..021)-> BB07 (always) i gcsafe BB06 [0039] 1 BB04 0.50 [020..021) i label target gcsafe BB07 [0040] 2 BB05,BB06 0.50 [000..000)-> BB09 ( cond ) i internal label target gcsafe idxlen BB08 [0043] 1 BB07 0.50 [000..000)-> BB10 (always) i internal gcsafe BB09 [0044] 1 BB07 0.50 [000..000) i internal label target gcsafe BB10 [0045] 2 BB08,BB09 0.50 [???..???)-> BB14 ( cond ) i internal label target hascall gcsafe idxlen BB11 [0003] 1 BB10 0.50 [065..070)-> BB13 ( cond ) i hascall gcsafe BB12 [0004] 1 BB11 0.50 [070..07A) (return) i hascall gcsafe BB13 [0005] 1 BB11 0.50 [07A..082) i label target hascall gcsafe BB14 [0006] 2 BB10,BB13 0.50 [082..092)-> BB16 ( cond ) i label target hascall gcsafe BB15 [0007] 1 BB14 0.50 [092..096)-> BB17 ( cond ) i gcsafe BB16 [0008] 2 BB14,BB15 0.50 [096..0A7)-> BB44 (always) i label target hascall gcsafe BB17 [0009] 1 BB15 0.50 [0A7..0B0)-> BB19 ( cond ) i label target gcsafe BB18 [0010] 1 BB17 0.50 [0B0..0B4)-> BB20 (always) i gcsafe BB19 [0011] 1 BB17 0.50 [0B4..0BE) i label target gcsafe BB20 [0012] 2 BB18,BB19 0.50 [0BE..0C4)-> BB23 ( cond ) i label target gcsafe BB21 [0013] 1 BB20 0.50 [0C4..0D9)-> BB23 ( cond ) i hascall gcsafe idxlen BB22 [0014] 1 BB21 0.50 [0D9..0E3) (return) i hascall gcsafe BB23 [0015] 2 BB20,BB21 0.50 [0E3..117)-> BB25 ( cond ) i label target hascall gcsafe BB24 [0016] 1 BB23 0.50 [117..11A)-> BB26 (always) i gcsafe BB25 [0017] 1 BB23 0.50 [11A..11F) i label target gcsafe BB26 [0018] 2 BB24,BB25 0.50 [11F..126)-> BB28 ( cond ) i label target gcsafe BB27 [0019] 1 BB26 0.50 [126..12F) i hascall gcsafe BB28 [0020] 2 BB26,BB27 0.50 [12F..13E)-> BB32 ( cond ) i label target gcsafe BB29 [0021] 1 BB28 0.50 [13E..144)-> BB31 ( cond ) i gcsafe BB30 [0022] 1 BB29 0.50 [144..155)-> BB44 (always) i hascall gcsafe BB31 [0023] 1 BB29 0.50 [155..15C) i label target gcsafe BB32 [0024] 2 BB28,BB31 0.50 [15C..167)-> BB34 ( cond ) i label target hascall gcsafe BB33 [0025] 1 BB32 0.50 [167..16B)-> BB35 (always) i gcsafe BB34 [0026] 1 BB32 0.50 [16B..16F) i label target gcsafe BB35 [0027] 2 BB33,BB34 0.50 [16F..1A4)-> BB40 ( cond ) i label target hascall gcsafe BB36 [0028] 1 BB35 0.50 [1A4..1AF)-> BB38 ( cond ) i gcsafe BB37 [0029] 1 BB36 0.50 [1AF..1C3)-> BB39 (always) i gcsafe BB38 [0030] 1 BB36 0.50 [1C3..1C4) i label target gcsafe BB39 [0031] 2 BB37,BB38 0.50 [1C4..1D0) i label target gcsafe BB40 [0032] 2 BB35,BB39 0.50 [1D0..1E7)-> BB42 ( cond ) i label target hascall gcsafe BB41 [0033] 1 BB40 0.50 [1E7..1EE)-> BB43 (always) i gcsafe BB42 [0034] 1 BB40 0.50 [1EE..1F2) i label target gcsafe BB43 [0035] 2 BB41,BB42 0.50 [1F2..202) i label target hascall gcsafe BB44 [0054] 3 BB16,BB30,BB43 0.50 [???..???) (return) keep internal target gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} ***** BB01 STMT00111 (IL ???... ???) N011 ( 7, 7) [000540] -A---------- * COMMA void N004 ( 3, 3) [000533] -A------R--- +--* ASG ref N003 ( 1, 1) [000530] D------N---- | +--* LCL_VAR ref V52 tmp22 d:2 N002 ( 3, 2) [000532] n----------- | \--* IND ref N001 ( 1, 1) [000531] ------------ | \--* LCL_VAR byref V00 arg0 u:1 Zero Fseq[Mantissa] N010 ( 4, 4) [000539] -A------R--- \--* ASG int N009 ( 1, 1) [000534] D------N---- +--* LCL_VAR int V53 tmp23 d:2 N008 ( 4, 4) [000538] n----------- \--* IND int N007 ( 2, 2) [000537] -------N---- \--* ADD byref N005 ( 1, 1) [000535] ------------ +--* LCL_VAR byref V00 arg0 u:1 (last use) N006 ( 1, 1) [000536] ------------ \--* CNS_INT long 8 Fseq[Exponent] ------------ BB02 [000..00D) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00000 (IL 0x000...0x00B) N005 ( 7, 7) [000006] ---XG------- * JTRUE void N004 ( 5, 5) [000005] J--XG--N---- \--* NE int N002 ( 3, 3) [000003] ---XG------- +--* ARR_LENGTH int N001 ( 1, 1) [000002] ------------ | \--* LCL_VAR ref V52 tmp22 u:2 N003 ( 1, 1) [000004] ------------ \--* CNS_INT int 0 ------------ BB03 [00D..017) (return), preds={BB02} succs={} ***** BB03 STMT00087 (IL 0x00D...0x014) N006 ( 25, 13) [000403] -ACXG---R--- * ASG long N005 ( 3, 2) [000402] *--X---N---- +--* IND long N004 ( 1, 1) [000399] ------------ | \--* LCL_VAR byref V02 arg2 u:1 (last use) N003 ( 21, 10) [000401] --CXG------- \--* CALLV ind long FloatingPointType.get_Zero N002 ( 1, 1) [000400] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 (last use) ***** BB03 STMT00107 (IL ???... ???) N002 ( 2, 2) [000520] ------------ * RETURN int N001 ( 1, 1) [000404] ------------ \--* CNS_INT int 1 ------------ BB04 [017..065) -> BB06 (cond), preds={BB02} succs={BB05,BB06} ***** BB04 STMT00002 (IL ???... ???) N010 ( 30, 19) [000013] -ACXG---R--- * ASG int N009 ( 3, 2) [000012] D------N---- +--* LCL_VAR int V03 loc0 d:2 N008 ( 26, 16) [000011] --CXG------- \--* ADD int N006 ( 24, 14) [000409] --CXG------- +--* CAST int <- ushort <- int N005 ( 23, 12) [000408] --CXG------- | \--* ADD int N003 ( 21, 10) [000406] --CXG------- | +--* CALLV ind int FloatingPointType.get_DenormalMantissaBits N002 ( 1, 1) [000007] ------------ this in rcx | | \--* LCL_VAR ref V01 arg1 u:1 N004 ( 1, 1) [000407] ------------ | \--* CNS_INT int 1 N007 ( 1, 1) [000010] ------------ \--* CNS_INT int 1 ***** BB04 STMT00092 (IL 0x020... ???) N003 ( 5, 4) [000424] -A--G---R--- * ASG int N002 ( 3, 2) [000423] D------N---- +--* LCL_VAR int V40 tmp10 d:2 N001 ( 1, 1) [000017] ------------ \--* LCL_VAR int V53 tmp23 u:2 ***** BB04 STMT00089 (IL 0x020... ???) N004 ( 5, 5) [000414] ------------ * JTRUE void N003 ( 3, 3) [000413] J------N---- \--* LE int N001 ( 1, 1) [000412] ------------ +--* LCL_VAR int V53 tmp23 u:2 N002 ( 1, 1) [000411] ------------ \--* CNS_INT int 0 ------------ BB05 [020..021) -> BB07 (always), preds={BB04} succs={BB07} ***** BB05 STMT00091 (IL 0x020... ???) N003 ( 7, 5) [000421] -A------R--- * ASG int N002 ( 3, 2) [000420] D------N---- +--* LCL_VAR int V39 tmp9 d:4 N001 ( 3, 2) [000419] ------------ \--* LCL_VAR int V40 tmp10 u:2 (last use) ------------ BB06 [020..021), preds={BB04} succs={BB07} ***** BB06 STMT00090 (IL 0x020... ???) N003 ( 5, 4) [000417] -A------R--- * ASG int N002 ( 3, 2) [000416] D------N---- +--* LCL_VAR int V39 tmp9 d:3 N001 ( 1, 1) [000415] ------------ \--* CNS_INT int 0 ------------ BB07 [000..000) -> BB09 (cond), preds={BB05,BB06} succs={BB08,BB09} ***** BB07 STMT00122 (IL ???... ???) N005 ( 0, 0) [000886] -A------R--- * ASG int N004 ( 0, 0) [000884] D------N---- +--* LCL_VAR int V39 tmp9 d:2 N003 ( 0, 0) [000885] ------------ \--* PHI int N001 ( 0, 0) [000909] ------------ pred BB05 +--* PHI_ARG int V39 tmp9 u:4 N002 ( 0, 0) [000908] ------------ pred BB06 \--* PHI_ARG int V39 tmp9 u:3 ***** BB07 STMT00004 (IL ???... ???) N003 ( 3, 3) [000021] -A------R--- * ASG int N002 ( 1, 1) [000020] D------N---- +--* LCL_VAR int V31 tmp1 d:2 N001 ( 3, 2) [000422] ------------ \--* LCL_VAR int V39 tmp9 u:2 ***** BB07 STMT00096 (IL ???... ???) N004 ( 3, 3) [000443] -A-XG---R--- * ASG int N003 ( 1, 1) [000442] D------N---- +--* LCL_VAR int V42 tmp12 d:2 N002 ( 3, 3) [000429] ---XG------- \--* ARR_LENGTH int N001 ( 1, 1) [000428] ------------ \--* LCL_VAR ref V52 tmp22 u:2 ***** BB07 STMT00093 (IL ???... ???) N004 ( 7, 6) [000433] ------------ * JTRUE void N003 ( 5, 4) [000432] N------N-U-- \--* LE int N001 ( 3, 2) [000023] ------------ +--* LCL_VAR int V39 tmp9 u:2 (last use) N002 ( 1, 1) [000431] ------------ \--* LCL_VAR int V42 tmp12 u:2 ------------ BB08 [000..000) -> BB10 (always), preds={BB07} succs={BB10} ***** BB08 STMT00095 (IL ???... ???) N003 ( 1, 3) [000440] -A------R--- * ASG int N002 ( 1, 1) [000439] D------N---- +--* LCL_VAR int V41 tmp11 d:4 N001 ( 1, 1) [000438] ------------ \--* LCL_VAR int V42 tmp12 u:2 (last use) ------------ BB09 [000..000), preds={BB07} succs={BB10} ***** BB09 STMT00094 (IL ???... ???) N003 ( 1, 3) [000436] -A------R--- * ASG int N002 ( 1, 1) [000435] D------N---- +--* LCL_VAR int V41 tmp11 d:3 N001 ( 1, 1) [000434] ------------ \--* LCL_VAR int V31 tmp1 u:2 ------------ BB10 [???..???) -> BB14 (cond), preds={BB08,BB09} succs={BB11,BB14} ***** BB10 STMT00121 (IL ???... ???) N005 ( 0, 0) [000883] -A------R--- * ASG int N004 ( 0, 0) [000881] D------N---- +--* LCL_VAR int V41 tmp11 d:2 N003 ( 0, 0) [000882] ------------ \--* PHI int N001 ( 0, 0) [000907] ------------ pred BB08 +--* PHI_ARG int V41 tmp11 u:4 N002 ( 0, 0) [000906] ------------ pred BB09 \--* PHI_ARG int V41 tmp11 u:3 ***** BB10 STMT00008 (IL ???...0x03C) N005 ( 7, 6) [000035] -A------R--- * ASG int N004 ( 3, 2) [000034] D------N---- +--* LCL_VAR int V05 loc2 d:2 N003 ( 3, 3) [000033] ------------ \--* SUB int N001 ( 1, 1) [000022] ------------ +--* LCL_VAR int V31 tmp1 u:2 (last use) N002 ( 1, 1) [000032] ------------ \--* LCL_VAR int V41 tmp11 u:2 ***** BB10 STMT00011 (IL 0x042...0x044) N003 ( 5, 4) [000044] -A------R--- * ASG int N002 ( 3, 2) [000043] D------N---- +--* LCL_VAR int V08 loc5 d:2 N001 ( 1, 1) [000042] ------------ \--* LCL_VAR int V41 tmp11 u:2 ***** BB10 STMT00013 (IL ???... ???) N004 ( 7, 6) [000050] -A-XG---R--- * ASG int N003 ( 3, 2) [000049] D------N---- +--* LCL_VAR int V09 loc6 d:2 N002 ( 3, 3) [000448] ---XG------- \--* ARR_LENGTH int N001 ( 1, 1) [000447] ------------ \--* LCL_VAR ref V52 tmp22 u:2 ***** BB10 STMT00014 (IL 0x04F...0x054) N005 ( 5, 4) [000055] -A------R--- * ASG int N004 ( 1, 1) [000054] D------N---- +--* LCL_VAR int V10 loc7 d:2 N003 ( 5, 4) [000053] ------------ \--* SUB int N001 ( 3, 2) [000051] ------------ +--* LCL_VAR int V09 loc6 u:2 N002 ( 1, 1) [000052] ------------ \--* LCL_VAR int V41 tmp11 u:2 ***** BB10 STMT00016 (IL ???... ???) N028 ( 49, 35) [000059] SACXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger N004 ( 7, 6) [000563] -A------R-L- arg0 SETUP +--* ASG long N003 ( 3, 2) [000562] D------N---- | +--* LCL_VAR long V75 tmp45 d:2 N002 ( 3, 3) [000064] ------------ | \--* ADDR long N001 ( 3, 2) [000063] ----G--N---- | \--* LCL_VAR struct(AX)(P) V11 loc8 | \--* ref V11._bits (offs=0x00) -> V54 tmp24 | \--* int V11._sign (offs=0x08) -> V55 tmp25 N020 ( 14, 13) [000561] -A--------L- arg1 SETUP +--* COMMA void N013 ( 8, 7) [000554] -A---------- | +--* COMMA void N008 ( 3, 3) [000549] -A------R--- | | +--* ASG byref N007 ( 1, 1) [000548] D------N---- | | | +--* LCL_VAR byref V74 tmp44 d:2 N006 ( 3, 3) [000546] ------------ | | | \--* ADDR byref N005 ( 3, 2) [000547] -------N---- | | | \--* LCL_VAR struct(AX) V73 tmp43 N012 ( 5, 4) [000553] -A---------- | | \--* ASG ref N010 ( 3, 2) [000551] *------N---- | | +--* IND ref N009 ( 1, 1) [000550] ------------ | | | \--* LCL_VAR byref V74 tmp44 u:2 Zero Fseq[Mantissa] N011 ( 1, 1) [000552] -------N---- | | \--* LCL_VAR ref V52 tmp22 u:2 N019 ( 6, 6) [000560] -A---------- | \--* ASG int N017 ( 4, 4) [000558] *------N---- | +--* IND int N016 ( 2, 2) [000557] -------N---- | | \--* ADD byref N014 ( 1, 1) [000555] ------------ | | +--* LCL_VAR byref V74 tmp44 u:2 (last use) N015 ( 1, 1) [000556] ------------ | | \--* CNS_INT long 8 Fseq[Exponent] N018 ( 1, 1) [000559] -------N---- | \--* LCL_VAR int V53 tmp23 u:2 N023 ( 3, 2) [000564] ------------ arg0 in rcx +--* LCL_VAR long V75 tmp45 u:2 (last use) N025 ( 3, 3) [000566] ------------ arg1 in rdx +--* ADDR byref N024 ( 3, 2) [000565] -------N---- | \--* LCL_VAR struct(AX) V73 tmp43 N026 ( 1, 1) [000058] ------------ arg3 in r9 +--* LCL_VAR int V41 tmp11 u:2 (last use) N027 ( 1, 1) [000057] ------------ arg2 in r8 \--* CNS_INT int 0 ***** BB10 STMT00017 (IL 0x061...0x063) N004 ( 7, 6) [000068] ------------ * JTRUE void N003 ( 5, 4) [000067] N------N---- \--* EQ int N001 ( 3, 2) [000065] ------------ +--* LCL_VAR int V05 loc2 u:2 N002 ( 1, 1) [000066] ------------ \--* CNS_INT int 0 ------------ BB11 [065..070) -> BB13 (cond), preds={BB10} succs={BB12,BB13} ***** BB11 STMT00083 (IL ???... ???) N008 ( 23, 17) [000387] --CXG------- * JTRUE void N007 ( 21, 15) [000386] J-CXG--N---- \--* GE int N004 ( 16, 10) [000385] --CXG------- +--* CAST long <- int N003 ( 15, 8) [000383] --CXG------- | \--* CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent N002 ( 1, 1) [000382] ------------ this in rcx | \--* LCL_VAR ref V01 arg1 u:1 N006 ( 4, 4) [000381] ---------U-- \--* CAST long <- ulong <- uint N005 ( 3, 2) [000380] ------------ \--* LCL_VAR int V05 loc2 u:2 ------------ BB12 [070..07A) (return), preds={BB11} succs={} ***** BB12 STMT00085 (IL 0x070...0x077) N006 ( 25, 13) [000396] -ACXG---R--- * ASG long N005 ( 3, 2) [000395] *--X---N---- +--* IND long N004 ( 1, 1) [000392] ------------ | \--* LCL_VAR byref V02 arg2 u:1 (last use) N003 ( 21, 10) [000394] --CXG------- \--* CALLV ind long FloatingPointType.get_Infinity N002 ( 1, 1) [000393] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 (last use) ***** BB12 STMT00108 (IL ???... ???) N002 ( 2, 2) [000521] ------------ * RETURN int N001 ( 1, 1) [000397] ------------ \--* CNS_INT int 3 ------------ BB13 [07A..082), preds={BB11} succs={BB14} ***** BB13 STMT00084 (IL 0x07A...0x07D) N006 ( 20, 12) [000391] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen N004 ( 3, 3) [000389] ------------ arg0 in rcx +--* ADDR long N003 ( 3, 2) [000388] ----G--N---- | \--* LCL_VAR struct(AX)(P) V11 loc8 | \--* ref V11._bits (offs=0x00) -> V54 tmp24 | \--* int V11._sign (offs=0x08) -> V55 tmp25 N005 ( 3, 2) [000390] ------------ arg1 in rdx \--* LCL_VAR int V05 loc2 u:2 (last use) ------------ BB14 [082..092) -> BB16 (cond), preds={BB10,BB13} succs={BB15,BB16} ***** BB14 STMT00019 (IL ???... ???) N023 ( 41, 28) [000077] -ACXG---R--- * ASG int N022 ( 1, 1) [000076] D------N---- +--* LCL_VAR int V13 loc10 d:2 N021 ( 41, 28) [000072] -ACXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits N016 ( 18, 15) [000591] -A--G-----L- arg0 SETUP +--* COMMA void N009 ( 10, 8) [000584] -A--G------- | +--* COMMA void N004 ( 3, 3) [000579] -A------R--- | | +--* ASG byref N003 ( 1, 1) [000578] D------N---- | | | +--* LCL_VAR byref V77 tmp47 d:2 N002 ( 3, 3) [000576] ------------ | | | \--* ADDR byref N001 ( 3, 2) [000577] -------N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 N008 ( 7, 5) [000583] -A--G------- | | \--* ASG ref N006 ( 3, 2) [000581] *------N---- | | +--* IND ref N005 ( 1, 1) [000580] ------------ | | | \--* LCL_VAR byref V77 tmp47 u:2 Zero Fseq[_bits] N007 ( 3, 2) [000582] ----G--N---- | | \--* LCL_VAR ref (AX) V54 tmp24 N015 ( 8, 7) [000590] -A--G------- | \--* ASG int N013 ( 4, 4) [000588] *------N---- | +--* IND int N012 ( 2, 2) [000587] -------N---- | | \--* ADD byref N010 ( 1, 1) [000585] ------------ | | +--* LCL_VAR byref V77 tmp47 u:2 (last use) N011 ( 1, 1) [000586] ------------ | | \--* CNS_INT long 8 Fseq[_sign] N014 ( 3, 2) [000589] ----G--N---- | \--* LCL_VAR int (AX) V55 tmp25 N019 ( 3, 3) [000593] ------------ arg0 in rcx +--* ADDR byref N018 ( 3, 2) [000592] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 N020 ( 3, 3) [000071] ------------ arg1 in rdx \--* LCL_VAR_ADDR long V12 loc9 ***** BB14 STMT00020 (IL 0x08D...0x090) N004 ( 7, 6) [000081] ------------ * JTRUE void N003 ( 5, 4) [000080] N------N-U-- \--* GE int N001 ( 1, 1) [000078] ------------ +--* LCL_VAR int V13 loc10 u:2 N002 ( 3, 2) [000079] ------------ \--* LCL_VAR int V03 loc0 u:2 ------------ BB15 [092..096) -> BB17 (cond), preds={BB14} succs={BB16,BB17} ***** BB15 STMT00022 (IL 0x092...0x094) N004 ( 5, 5) [000094] ------------ * JTRUE void N003 ( 3, 3) [000093] J------N---- \--* NE int N001 ( 1, 1) [000091] ------------ +--* LCL_VAR int V10 loc7 u:2 N002 ( 1, 1) [000092] ------------ \--* CNS_INT int 0 ------------ BB16 [096..0A7) -> BB44 (always), preds={BB14,BB15} succs={BB44} ***** BB16 STMT00021 (IL 0x096...0x0A6) N014 ( 29, 17) [000600] -ACXG---R--- * ASG int N013 ( 1, 1) [000599] D------N---- +--* LCL_VAR int V51 tmp21 d:3 N012 ( 29, 17) [000089] --CXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits N005 ( 1, 1) [000088] ------------ arg4 out+20 +--* LCL_VAR byref V02 arg2 u:1 (last use) N008 ( 6, 3) [000086] N----------- arg2 in r8 +--* NE int N006 ( 1, 1) [000084] ------------ | +--* LCL_VAR int V10 loc7 u:2 (last use) N007 ( 1, 1) [000085] ------------ | \--* CNS_INT int 0 N009 ( 3, 2) [000082] ----G------- arg0 in rcx +--* LCL_VAR ref (AX) V12 loc9 N010 ( 1, 1) [000083] ------------ arg1 in rdx +--* LCL_VAR int V13 loc10 u:2 (last use) N011 ( 1, 1) [000087] ------------ arg3 in r9 \--* LCL_VAR ref V01 arg1 u:1 (last use) ------------ BB17 [0A7..0B0) -> BB19 (cond), preds={BB15} succs={BB18,BB19} ***** BB17 STMT00023 (IL 0x0A7...0x0AE) N004 ( 5, 5) [000100] ----G------- * JTRUE void N003 ( 3, 3) [000099] J---G--N---- \--* LT int N001 ( 1, 1) [000097] ------------ +--* LCL_VAR int V53 tmp23 u:2 N002 ( 1, 1) [000098] ------------ \--* CNS_INT int 0 ------------ BB18 [0B0..0B4) -> BB20 (always), preds={BB17} succs={BB20} ***** BB18 STMT00081 (IL 0x0B0...0x0B2) N003 ( 5, 4) [000378] -A------R--- * ASG int N002 ( 3, 2) [000377] D------N---- +--* LCL_VAR int V32 tmp2 d:4 N001 ( 1, 1) [000376] ------------ \--* LCL_VAR int V10 loc7 u:2 ------------ BB19 [0B4..0BE), preds={BB17} succs={BB20} ***** BB19 STMT00024 (IL 0x0B4...0x0BD) N005 ( 7, 6) [000108] -A--G---R--- * ASG int N004 ( 3, 2) [000107] D------N---- +--* LCL_VAR int V32 tmp2 d:3 N003 ( 3, 3) [000106] ----G------- \--* SUB int N001 ( 1, 1) [000101] ------------ +--* LCL_VAR int V10 loc7 u:2 N002 ( 1, 1) [000104] ------------ \--* LCL_VAR int V53 tmp23 u:2 ------------ BB20 [0BE..0C4) -> BB23 (cond), preds={BB18,BB19} succs={BB21,BB23} ***** BB20 STMT00120 (IL ???... ???) N005 ( 0, 0) [000880] -A------R--- * ASG int N004 ( 0, 0) [000878] D------N---- +--* LCL_VAR int V32 tmp2 d:2 N003 ( 0, 0) [000879] ------------ \--* PHI int N001 ( 0, 0) [000905] ------------ pred BB18 +--* PHI_ARG int V32 tmp2 u:4 N002 ( 0, 0) [000904] ------------ pred BB19 \--* PHI_ARG int V32 tmp2 u:3 ***** BB20 STMT00025 (IL ???...0x0BE) N003 ( 7, 5) [000112] -A------R--- * ASG int N002 ( 3, 2) [000111] D------N---- +--* LCL_VAR int V14 loc11 d:2 N001 ( 3, 2) [000110] ------------ \--* LCL_VAR int V32 tmp2 u:2 (last use) ***** BB20 STMT00026 (IL 0x0C0...0x0C2) N004 ( 5, 5) [000116] ------------ * JTRUE void N003 ( 3, 3) [000115] J------N---- \--* NE int N001 ( 1, 1) [000113] ------------ +--* LCL_VAR int V13 loc10 u:2 N002 ( 1, 1) [000114] ------------ \--* CNS_INT int 0 ------------ BB21 [0C4..0D9) -> BB23 (cond), preds={BB20} succs={BB22,BB23} ***** BB21 STMT00077 (IL ???... ???) N008 ( 13, 13) [000363] -A-XG---R--- * ASG long N007 ( 3, 2) [000362] D------N---- +--* LCL_VAR long V38 tmp8 d:2 N006 ( 9, 10) [000359] ---XG---R--- \--* SUB long N005 ( 4, 4) [000353] ---------U-- +--* CAST long <- ulong <- uint N004 ( 3, 2) [000352] ------------ | \--* LCL_VAR int V14 loc11 u:2 N003 ( 4, 5) [000358] ---XG------- \--* CAST long <- int N002 ( 3, 3) [000456] ---XG------- \--* ARR_LENGTH int N001 ( 1, 1) [000455] ------------ \--* LCL_VAR ref V52 tmp22 u:2 ***** BB21 STMT00078 (IL ???... ???) N007 ( 22, 15) [000368] --CXG------- * JTRUE void N006 ( 20, 13) [000367] J-CXG--N---- \--* GE int N004 ( 16, 10) [000366] --CXG------- +--* CAST long <- int N003 ( 15, 8) [000361] --CXG------- | \--* CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent N002 ( 1, 1) [000360] ------------ this in rcx | \--* LCL_VAR ref V01 arg1 u:1 N005 ( 3, 2) [000364] ------------ \--* LCL_VAR long V38 tmp8 u:2 (last use) ------------ BB22 [0D9..0E3) (return), preds={BB21} succs={} ***** BB22 STMT00079 (IL 0x0D9...0x0E0) N006 ( 25, 13) [000373] -ACXG---R--- * ASG long N005 ( 3, 2) [000372] *--X---N---- +--* IND long N004 ( 1, 1) [000369] ------------ | \--* LCL_VAR byref V02 arg2 u:1 (last use) N003 ( 21, 10) [000371] --CXG------- \--* CALLV ind long FloatingPointType.get_Zero N002 ( 1, 1) [000370] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 (last use) ***** BB22 STMT00110 (IL ???... ???) N002 ( 2, 2) [000524] ------------ * RETURN int N001 ( 1, 1) [000374] ------------ \--* CNS_INT int 2 ------------ BB23 [0E3..117) -> BB25 (cond), preds={BB20,BB21} succs={BB24,BB25} ***** BB23 STMT00028 (IL ???... ???) N028 ( 53, 37) [000120] SACXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger N004 ( 7, 6) [000623] -A------R-L- arg0 SETUP +--* ASG long N003 ( 3, 2) [000622] D------N---- | +--* LCL_VAR long V79 tmp49 d:2 N002 ( 3, 3) [000125] ------------ | \--* ADDR long N001 ( 3, 2) [000124] ----G--N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 N020 ( 14, 13) [000621] -A--------L- arg1 SETUP +--* COMMA void N013 ( 8, 7) [000614] -A---------- | +--* COMMA void N008 ( 3, 3) [000609] -A------R--- | | +--* ASG byref N007 ( 1, 1) [000608] D------N---- | | | +--* LCL_VAR byref V78 tmp48 d:2 N006 ( 3, 3) [000606] ------------ | | | \--* ADDR byref N005 ( 3, 2) [000607] ----G--N---- | | | \--* LCL_VAR struct(AX) V73 tmp43 N012 ( 5, 4) [000613] -A---------- | | \--* ASG ref N010 ( 3, 2) [000611] *------N---- | | +--* IND ref N009 ( 1, 1) [000610] ------------ | | | \--* LCL_VAR byref V78 tmp48 u:2 Zero Fseq[Mantissa] N011 ( 1, 1) [000612] -------N---- | | \--* LCL_VAR ref V52 tmp22 u:2 (last use) N019 ( 6, 6) [000620] -A---------- | \--* ASG int N017 ( 4, 4) [000618] *------N---- | +--* IND int N016 ( 2, 2) [000617] -------N---- | | \--* ADD byref N014 ( 1, 1) [000615] ------------ | | +--* LCL_VAR byref V78 tmp48 u:2 (last use) N015 ( 1, 1) [000616] ------------ | | \--* CNS_INT long 8 Fseq[Exponent] N018 ( 1, 1) [000619] -------N---- | \--* LCL_VAR int V53 tmp23 u:2 (last use) N023 ( 3, 2) [000624] ------------ arg0 in rcx +--* LCL_VAR long V79 tmp49 u:2 (last use) N025 ( 3, 3) [000626] ------------ arg1 in rdx +--* ADDR byref N024 ( 3, 2) [000625] -------N---- | \--* LCL_VAR struct(AX) V73 tmp43 N026 ( 3, 2) [000118] ------------ arg2 in r8 +--* LCL_VAR int V08 loc5 u:2 (last use) N027 ( 3, 2) [000119] ------------ arg3 in r9 \--* LCL_VAR int V09 loc6 u:2 (last use) ***** BB23 STMT00029 (IL 0x0EF...0x0F4) N005 ( 17, 21) [000133] H-CXG------- * CALL help long HELPER.CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE N003 ( 2, 10) [000131] ------------ arg0 in rcx +--* CNS_INT long 0x7ff815262aa0 N004 ( 1, 4) [000132] ------------ arg1 in rdx \--* CNS_INT int 173 ***** BB23 STMT00030 (IL ???... ???) N018 ( 21, 26) [000649] -A-XG------- * COMMA void N011 ( 13, 19) [000642] -A-XG------- +--* COMMA void N006 ( 6, 14) [000637] -A--G---R--- | +--* ASG byref N005 ( 1, 1) [000636] D------N---- | | +--* LCL_VAR byref V80 tmp50 d:2 N004 ( 6, 14) [000632] ----G------- | | \--* ADD byref N002 ( 4, 12) [000633] n---G------- | | +--* IND ref N001 ( 2, 10) [000634] I----------- | | | \--* CNS_INT(h) long 0xd1ffab1e static Fseq[BigOne] N003 ( 1, 1) [000635] ------------ | | \--* CNS_INT long 8 Fseq[#FirstElem] N010 ( 7, 5) [000641] -A-XG---R--- | \--* ASG ref N009 ( 3, 2) [000638] D---G--N---- | +--* LCL_VAR ref (AX) V58 tmp28 N008 ( 3, 2) [000640] ---X-------- | \--* IND ref N007 ( 1, 1) [000639] ------------ | \--* LCL_VAR byref V80 tmp50 u:2 Zero Fseq[_bits] N017 ( 8, 7) [000648] -A-XG---R--- \--* ASG int N016 ( 3, 2) [000643] D---G--N---- +--* LCL_VAR int (AX) V59 tmp29 N015 ( 4, 4) [000647] ---X-------- \--* IND int N014 ( 2, 2) [000646] -------N---- \--* ADD byref N012 ( 1, 1) [000644] ------------ +--* LCL_VAR byref V80 tmp50 u:2 (last use) N013 ( 1, 1) [000645] ------------ \--* CNS_INT long 8 Fseq[_sign] ***** BB23 STMT00031 (IL 0x0F6...0x106) N006 ( 20, 12) [000141] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen N004 ( 3, 3) [000139] ------------ arg0 in rcx +--* ADDR long N003 ( 3, 2) [000138] ----G--N---- | \--* LCL_VAR struct(AX)(P) V16 loc13 | \--* ref V16._bits (offs=0x00) -> V58 tmp28 | \--* int V16._sign (offs=0x08) -> V59 tmp29 N005 ( 3, 2) [000140] ------------ arg1 in rdx \--* LCL_VAR int V14 loc11 u:2 (last use) ***** BB23 STMT00099 (IL 0x0FF... ???) N007 ( 14, 10) [000658] -A--G------- * COMMA void N003 ( 7, 5) [000654] -A--G---R--- +--* ASG ref N002 ( 3, 2) [000652] D------N---- | +--* LCL_VAR ref V64 tmp34 d:2 N001 ( 3, 2) [000653] ----G--N---- | \--* LCL_VAR ref (AX) V56 tmp26 N006 ( 7, 5) [000657] -A--G---R--- \--* ASG int N005 ( 3, 2) [000655] D------N---- +--* LCL_VAR int V65 tmp35 d:2 N004 ( 3, 2) [000656] ----G--N---- \--* LCL_VAR int (AX) V57 tmp27 ***** BB23 STMT00098 (IL 0x0FF... ???) N023 ( 45, 31) [000468] -ACXG---R--- * ASG int N022 ( 3, 2) [000467] D------N---- +--* LCL_VAR int V43 tmp13 d:2 N021 ( 41, 28) [000463] -ACXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits N016 ( 18, 15) [000677] -A--------L- arg0 SETUP +--* COMMA void N009 ( 10, 8) [000670] -A---------- | +--* COMMA void N004 ( 3, 3) [000665] -A------R--- | | +--* ASG byref N003 ( 1, 1) [000664] D------N---- | | | +--* LCL_VAR byref V81 tmp51 d:2 N002 ( 3, 3) [000662] ------------ | | | \--* ADDR byref N001 ( 3, 2) [000663] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 N008 ( 7, 5) [000669] -A---------- | | \--* ASG ref N006 ( 3, 2) [000667] *------N---- | | +--* IND ref N005 ( 1, 1) [000666] ------------ | | | \--* LCL_VAR byref V81 tmp51 u:2 Zero Fseq[_bits] N007 ( 3, 2) [000668] -------N---- | | \--* LCL_VAR ref V64 tmp34 u:2 (last use) N015 ( 8, 7) [000676] -A---------- | \--* ASG int N013 ( 4, 4) [000674] *------N---- | +--* IND int N012 ( 2, 2) [000673] -------N---- | | \--* ADD byref N010 ( 1, 1) [000671] ------------ | | +--* LCL_VAR byref V81 tmp51 u:2 (last use) N011 ( 1, 1) [000672] ------------ | | \--* CNS_INT long 8 Fseq[_sign] N014 ( 3, 2) [000675] -------N---- | \--* LCL_VAR int V65 tmp35 u:2 (last use) N019 ( 3, 3) [000679] ------------ arg0 in rcx +--* ADDR byref N018 ( 3, 2) [000678] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 N020 ( 3, 3) [000462] ------------ arg1 in rdx \--* LCL_VAR_ADDR long V45 tmp15 ***** BB23 STMT00100 (IL 0x0FF... ???) N003 ( 5, 4) [000475] -A--G---R--- * ASG ref N002 ( 3, 2) [000474] D---G--N---- +--* LCL_VAR ref (AX) V45 tmp15 N001 ( 1, 1) [000473] ------------ \--* CNS_INT ref null ***** BB23 STMT00033 (IL ???... ???) N003 ( 7, 5) [000148] -A------R--- * ASG int N002 ( 3, 2) [000147] D------N---- +--* LCL_VAR int V17 loc14 d:2 N001 ( 3, 2) [000469] ------------ \--* LCL_VAR int V43 tmp13 u:2 ***** BB23 STMT00103 (IL 0x108... ???) N007 ( 14, 10) [000687] -A--G------- * COMMA void N003 ( 7, 5) [000683] -A--G---R--- +--* ASG ref N002 ( 3, 2) [000681] D------N---- | +--* LCL_VAR ref V66 tmp36 d:2 N001 ( 3, 2) [000682] ----G--N---- | \--* LCL_VAR ref (AX) V58 tmp28 N006 ( 7, 5) [000686] -A--G---R--- \--* ASG int N005 ( 3, 2) [000684] D------N---- +--* LCL_VAR int V67 tmp37 d:2 N004 ( 3, 2) [000685] ----G--N---- \--* LCL_VAR int (AX) V59 tmp29 ***** BB23 STMT00102 (IL 0x108... ???) N023 ( 45, 31) [000486] -ACXG---R--- * ASG int N022 ( 3, 2) [000485] D------N---- +--* LCL_VAR int V46 tmp16 d:2 N021 ( 41, 28) [000481] -ACXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits N016 ( 18, 15) [000706] -A--------L- arg0 SETUP +--* COMMA void N009 ( 10, 8) [000699] -A---------- | +--* COMMA void N004 ( 3, 3) [000694] -A------R--- | | +--* ASG byref N003 ( 1, 1) [000693] D------N---- | | | +--* LCL_VAR byref V82 tmp52 d:2 N002 ( 3, 3) [000691] ------------ | | | \--* ADDR byref N001 ( 3, 2) [000692] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 N008 ( 7, 5) [000698] -A---------- | | \--* ASG ref N006 ( 3, 2) [000696] *------N---- | | +--* IND ref N005 ( 1, 1) [000695] ------------ | | | \--* LCL_VAR byref V82 tmp52 u:2 Zero Fseq[_bits] N007 ( 3, 2) [000697] -------N---- | | \--* LCL_VAR ref V66 tmp36 u:2 (last use) N015 ( 8, 7) [000705] -A---------- | \--* ASG int N013 ( 4, 4) [000703] *------N---- | +--* IND int N012 ( 2, 2) [000702] -------N---- | | \--* ADD byref N010 ( 1, 1) [000700] ------------ | | +--* LCL_VAR byref V82 tmp52 u:2 (last use) N011 ( 1, 1) [000701] ------------ | | \--* CNS_INT long 8 Fseq[_sign] N014 ( 3, 2) [000704] -------N---- | \--* LCL_VAR int V67 tmp37 u:2 (last use) N019 ( 3, 3) [000708] ------------ arg0 in rcx +--* ADDR byref N018 ( 3, 2) [000707] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 N020 ( 3, 3) [000480] ------------ arg1 in rdx \--* LCL_VAR_ADDR long V48 tmp18 ***** BB23 STMT00104 (IL 0x108... ???) N003 ( 5, 4) [000493] -A--G---R--- * ASG ref N002 ( 3, 2) [000492] D---G--N---- +--* LCL_VAR ref (AX) V48 tmp18 N001 ( 1, 1) [000491] ------------ \--* CNS_INT ref null ***** BB23 STMT00035 (IL ???... ???) N003 ( 7, 5) [000155] -A------R--- * ASG int N002 ( 3, 2) [000154] D------N---- +--* LCL_VAR int V18 loc15 d:2 N001 ( 3, 2) [000487] ------------ \--* LCL_VAR int V46 tmp16 u:2 ***** BB23 STMT00036 (IL 0x111...0x115) N004 ( 9, 7) [000159] ------------ * JTRUE void N003 ( 7, 5) [000158] N------N-U-- \--* GT int N001 ( 3, 2) [000156] ------------ +--* LCL_VAR int V46 tmp16 u:2 (last use) N002 ( 3, 2) [000157] ------------ \--* LCL_VAR int V43 tmp13 u:2 (last use) ------------ BB24 [117..11A) -> BB26 (always), preds={BB23} succs={BB26} ***** BB24 STMT00074 (IL 0x117...0x118) N003 ( 5, 4) [000350] -A------R--- * ASG int N002 ( 3, 2) [000349] D------N---- +--* LCL_VAR int V33 tmp3 d:4 N001 ( 1, 1) [000348] ------------ \--* CNS_INT int 0 ------------ BB25 [11A..11F), preds={BB23} succs={BB26} ***** BB25 STMT00037 (IL 0x11A...0x11E) N005 ( 11, 8) [000164] -A------R--- * ASG int N004 ( 3, 2) [000163] D------N---- +--* LCL_VAR int V33 tmp3 d:3 N003 ( 7, 5) [000162] ------------ \--* SUB int N001 ( 3, 2) [000160] ------------ +--* LCL_VAR int V18 loc15 u:2 (last use) N002 ( 3, 2) [000161] ------------ \--* LCL_VAR int V17 loc14 u:2 (last use) ------------ BB26 [11F..126) -> BB28 (cond), preds={BB24,BB25} succs={BB27,BB28} ***** BB26 STMT00119 (IL ???... ???) N005 ( 0, 0) [000877] -A------R--- * ASG int N004 ( 0, 0) [000875] D------N---- +--* LCL_VAR int V33 tmp3 d:2 N003 ( 0, 0) [000876] ------------ \--* PHI int N001 ( 0, 0) [000903] ------------ pred BB24 +--* PHI_ARG int V33 tmp3 u:4 N002 ( 0, 0) [000902] ------------ pred BB25 \--* PHI_ARG int V33 tmp3 u:3 ***** BB26 STMT00038 (IL ???...0x11F) N003 ( 3, 3) [000168] -A------R--- * ASG int N002 ( 1, 1) [000167] D------N---- +--* LCL_VAR int V19 loc16 d:2 N001 ( 3, 2) [000166] ------------ \--* LCL_VAR int V33 tmp3 u:2 ***** BB26 STMT00039 (IL 0x121...0x124) N004 ( 7, 6) [000172] ------------ * JTRUE void N003 ( 5, 4) [000171] N------N---- \--* EQ int N001 ( 3, 2) [000169] ------------ +--* LCL_VAR int V33 tmp3 u:2 (last use) N002 ( 1, 1) [000170] ------------ \--* CNS_INT int 0 ------------ BB27 [126..12F), preds={BB26} succs={BB28} ***** BB27 STMT00073 (IL 0x126...0x12A) N006 ( 18, 11) [000347] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft N004 ( 3, 3) [000345] ------------ arg0 in rcx +--* ADDR long N003 ( 3, 2) [000344] ----G--N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 N005 ( 1, 1) [000346] ------------ arg1 in rdx \--* LCL_VAR int V19 loc16 u:2 ------------ BB28 [12F..13E) -> BB32 (cond), preds={BB26,BB27} succs={BB29,BB32} ***** BB28 STMT00040 (IL 0x12F...0x133) N005 ( 9, 7) [000177] -A------R--- * ASG int N004 ( 3, 2) [000176] D------N---- +--* LCL_VAR int V20 loc17 d:2 N003 ( 5, 4) [000175] ------------ \--* SUB int N001 ( 3, 2) [000173] ------------ +--* LCL_VAR int V03 loc0 u:2 (last use) N002 ( 1, 1) [000174] ------------ \--* LCL_VAR int V13 loc10 u:2 ***** BB28 STMT00041 (IL 0x135...0x137) N003 ( 7, 5) [000180] -A------R--- * ASG int N002 ( 3, 2) [000179] D------N---- +--* LCL_VAR int V21 loc18 d:2 N001 ( 3, 2) [000178] ------------ \--* LCL_VAR int V20 loc17 u:2 ***** BB28 STMT00042 (IL 0x139...0x13C) N004 ( 5, 5) [000184] ------------ * JTRUE void N003 ( 3, 3) [000183] N------N---- \--* EQ int N001 ( 1, 1) [000181] ------------ +--* LCL_VAR int V13 loc10 u:2 N002 ( 1, 1) [000182] ------------ \--* CNS_INT int 0 ------------ BB29 [13E..144) -> BB31 (cond), preds={BB28} succs={BB30,BB31} ***** BB29 STMT00070 (IL 0x13E...0x142) N004 ( 7, 6) [000329] ------------ * JTRUE void N003 ( 5, 4) [000328] N------N-U-- \--* LE int N001 ( 1, 1) [000326] ------------ +--* LCL_VAR int V19 loc16 u:2 N002 ( 3, 2) [000327] ------------ \--* LCL_VAR int V21 loc18 u:2 ------------ BB30 [144..155) -> BB44 (always), preds={BB29} succs={BB44} ***** BB30 STMT00072 (IL 0x144...0x154) N014 ( 29, 17) [000717] -ACXG---R--- * ASG int N013 ( 1, 1) [000716] D------N---- +--* LCL_VAR int V51 tmp21 d:5 N012 ( 29, 17) [000342] --CXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits N005 ( 1, 1) [000341] ------------ arg4 out+20 +--* LCL_VAR byref V02 arg2 u:1 (last use) N008 ( 6, 3) [000339] N----------- arg2 in r8 +--* NE int N006 ( 1, 1) [000337] ------------ | +--* LCL_VAR int V10 loc7 u:2 (last use) N007 ( 1, 1) [000338] ------------ | \--* CNS_INT int 0 N009 ( 3, 2) [000335] ----G------- arg0 in rcx +--* LCL_VAR ref (AX) V12 loc9 N010 ( 1, 1) [000336] ------------ arg1 in rdx +--* LCL_VAR int V13 loc10 u:2 (last use) N011 ( 1, 1) [000340] ------------ arg3 in r9 \--* LCL_VAR ref V01 arg1 u:1 (last use) ------------ BB31 [155..15C), preds={BB29} succs={BB32} ***** BB31 STMT00071 (IL 0x155...0x15A) N005 ( 9, 7) [000334] -A------R--- * ASG int N004 ( 3, 2) [000333] D------N---- +--* LCL_VAR int V21 loc18 d:4 N003 ( 5, 4) [000332] ------------ \--* SUB int N001 ( 3, 2) [000330] ------------ +--* LCL_VAR int V21 loc18 u:2 (last use) N002 ( 1, 1) [000331] ------------ \--* LCL_VAR int V19 loc16 u:2 ------------ BB32 [15C..167) -> BB34 (cond), preds={BB28,BB31} succs={BB33,BB34} ***** BB32 STMT00118 (IL ???... ???) N005 ( 0, 0) [000874] -A------R--- * ASG int N004 ( 0, 0) [000872] D------N---- +--* LCL_VAR int V21 loc18 d:3 N003 ( 0, 0) [000873] ------------ \--* PHI int N001 ( 0, 0) [000900] ------------ pred BB31 +--* PHI_ARG int V21 loc18 u:4 N002 ( 0, 0) [000888] ------------ pred BB28 \--* PHI_ARG int V21 loc18 u:2 ***** BB32 STMT00105 (IL 0x15C... ???) N007 ( 14, 10) [000724] -A--G------- * COMMA void N003 ( 7, 5) [000720] -A--G---R--- +--* ASG ref N002 ( 3, 2) [000718] D---G--N---- | +--* LCL_VAR ref (AX) V68 tmp38 N001 ( 3, 2) [000719] ----G--N---- | \--* LCL_VAR ref (AX) V56 tmp26 N006 ( 7, 5) [000723] -A--G---R--- \--* ASG int N005 ( 3, 2) [000721] D---G--N---- +--* LCL_VAR int (AX) V69 tmp39 N004 ( 3, 2) [000722] ----G--N---- \--* LCL_VAR int (AX) V57 tmp27 ***** BB32 STMT00106 (IL 0x15C... ???) N007 ( 14, 10) [000731] -A--G------- * COMMA void N003 ( 7, 5) [000727] -A--G---R--- +--* ASG ref N002 ( 3, 2) [000725] D------N---- | +--* LCL_VAR ref V70 tmp40 d:2 N001 ( 3, 2) [000726] ----G--N---- | \--* LCL_VAR ref (AX) V58 tmp28 N006 ( 7, 5) [000730] -A--G---R--- \--* ASG int N005 ( 3, 2) [000728] D------N---- +--* LCL_VAR int V71 tmp41 d:2 N004 ( 3, 2) [000729] ----G--N---- \--* LCL_VAR int (AX) V59 tmp29 ***** BB32 STMT00044 (IL ???... ???) N027 ( 52, 38) [000195] -ACXG------- * JTRUE void N026 ( 50, 36) [000503] JACXG--N---- \--* LT int N024 ( 48, 34) [000499] -ACXG------- +--* CALL int System.Numerics.BigInteger.CompareTo N004 ( 7, 6) [000752] -A------R-L- this SETUP | +--* ASG byref N003 ( 3, 2) [000751] D------N---- | | +--* LCL_VAR byref V84 tmp54 d:2 N002 ( 3, 3) [000497] ------------ | | \--* ADDR byref N001 ( 3, 2) [000496] ----G--N---- | | \--* LCL_VAR struct(AX)(P) V49 tmp19 | | \--* ref V49._bits (offs=0x00) -> V68 tmp38 | | \--* int V49._sign (offs=0x08) -> V69 tmp39 N020 ( 18, 15) [000750] -A--------L- arg1 SETUP | +--* COMMA void N013 ( 10, 8) [000743] -A---------- | | +--* COMMA void N008 ( 3, 3) [000738] -A------R--- | | | +--* ASG byref N007 ( 1, 1) [000737] D------N---- | | | | +--* LCL_VAR byref V83 tmp53 d:2 N006 ( 3, 3) [000735] ------------ | | | | \--* ADDR byref N005 ( 3, 2) [000736] ----G--N---- | | | | \--* LCL_VAR struct(AX) V76 tmp46 N012 ( 7, 5) [000742] -A---------- | | | \--* ASG ref N010 ( 3, 2) [000740] *------N---- | | | +--* IND ref N009 ( 1, 1) [000739] ------------ | | | | \--* LCL_VAR byref V83 tmp53 u:2 Zero Fseq[_bits] N011 ( 3, 2) [000741] -------N---- | | | \--* LCL_VAR ref V70 tmp40 u:2 (last use) N019 ( 8, 7) [000749] -A---------- | | \--* ASG int N017 ( 4, 4) [000747] *------N---- | | +--* IND int N016 ( 2, 2) [000746] -------N---- | | | \--* ADD byref N014 ( 1, 1) [000744] ------------ | | | +--* LCL_VAR byref V83 tmp53 u:2 (last use) N015 ( 1, 1) [000745] ------------ | | | \--* CNS_INT long 8 Fseq[_sign] N018 ( 3, 2) [000748] -------N---- | | \--* LCL_VAR int V71 tmp41 u:2 (last use) N021 ( 3, 2) [000753] ------------ this in rcx | +--* LCL_VAR byref V84 tmp54 u:2 (last use) N023 ( 3, 3) [000755] ------------ arg1 in rdx | \--* ADDR byref N022 ( 3, 2) [000754] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 N025 ( 1, 1) [000502] ------------ \--* CNS_INT int 0 ------------ BB33 [167..16B) -> BB35 (always), preds={BB32} succs={BB35} ***** BB33 STMT00069 (IL 0x167...0x169) N003 ( 5, 4) [000324] -A------R--- * ASG int N002 ( 3, 2) [000323] D------N---- +--* LCL_VAR int V34 tmp4 d:4 N001 ( 1, 1) [000322] ------------ \--* LCL_VAR int V19 loc16 u:2 (last use) ------------ BB34 [16B..16F), preds={BB32} succs={BB35} ***** BB34 STMT00045 (IL 0x16B...0x16E) N005 ( 7, 6) [000200] -A------R--- * ASG int N004 ( 3, 2) [000199] D------N---- +--* LCL_VAR int V34 tmp4 d:3 N003 ( 3, 3) [000198] ------------ \--* ADD int N001 ( 1, 1) [000196] ------------ +--* LCL_VAR int V19 loc16 u:2 (last use) N002 ( 1, 1) [000197] ------------ \--* CNS_INT int 1 ------------ BB35 [16F..1A4) -> BB40 (cond), preds={BB33,BB34} succs={BB36,BB40} ***** BB35 STMT00117 (IL ???... ???) N005 ( 0, 0) [000871] -A------R--- * ASG int N004 ( 0, 0) [000869] D------N---- +--* LCL_VAR int V34 tmp4 d:2 N003 ( 0, 0) [000870] ------------ \--* PHI int N001 ( 0, 0) [000899] ------------ pred BB33 +--* PHI_ARG int V34 tmp4 u:4 N002 ( 0, 0) [000898] ------------ pred BB34 \--* PHI_ARG int V34 tmp4 u:3 ***** BB35 STMT00046 (IL ???...0x16F) N003 ( 7, 5) [000204] -A------R--- * ASG int N002 ( 3, 2) [000203] D------N---- +--* LCL_VAR int V22 loc19 d:2 N001 ( 3, 2) [000202] ------------ \--* LCL_VAR int V34 tmp4 u:2 (last use) ***** BB35 STMT00047 (IL 0x171...0x18A) N006 ( 20, 12) [000208] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft N004 ( 3, 3) [000206] ------------ arg0 in rcx +--* ADDR long N003 ( 3, 2) [000205] ----G--N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 N005 ( 3, 2) [000207] ------------ arg1 in rdx \--* LCL_VAR int V21 loc18 u:3 (last use) ***** BB35 STMT00048 (IL 0x17A... ???) N045 ( 78, 56) [000213] SACXG------- * CALL void System.Numerics.BigInteger.DivRem N004 ( 7, 6) [000797] -A------R-L- arg0 SETUP +--* ASG long N003 ( 3, 2) [000796] D------N---- | +--* LCL_VAR long V88 tmp58 d:2 N002 ( 3, 3) [000220] ------------ | \--* ADDR long N001 ( 3, 2) [000219] ----G--N---- | \--* LCL_VAR struct(AX)(P) V35 tmp5 | \--* ref V35._bits (offs=0x00) -> V62 tmp32 | \--* int V35._sign (offs=0x08) -> V63 tmp33 N020 ( 18, 15) [000776] -A--G-----L- arg1 SETUP +--* COMMA void N013 ( 10, 8) [000769] -A--G------- | +--* COMMA void N008 ( 3, 3) [000764] -A------R--- | | +--* ASG byref N007 ( 1, 1) [000763] D------N---- | | | +--* LCL_VAR byref V85 tmp55 d:2 N006 ( 3, 3) [000761] ------------ | | | \--* ADDR byref N005 ( 3, 2) [000762] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 N012 ( 7, 5) [000768] -A--G------- | | \--* ASG ref N010 ( 3, 2) [000766] *------N---- | | +--* IND ref N009 ( 1, 1) [000765] ------------ | | | \--* LCL_VAR byref V85 tmp55 u:2 Zero Fseq[_bits] N011 ( 3, 2) [000767] ----G--N---- | | \--* LCL_VAR ref (AX) V56 tmp26 N019 ( 8, 7) [000775] -A--G------- | \--* ASG int N017 ( 4, 4) [000773] *------N---- | +--* IND int N016 ( 2, 2) [000772] -------N---- | | \--* ADD byref N014 ( 1, 1) [000770] ------------ | | +--* LCL_VAR byref V85 tmp55 u:2 (last use) N015 ( 1, 1) [000771] ------------ | | \--* CNS_INT long 8 Fseq[_sign] N018 ( 3, 2) [000774] ----G--N---- | \--* LCL_VAR int (AX) V57 tmp27 N036 ( 18, 15) [000795] -A--G-----L- arg2 SETUP +--* COMMA void N029 ( 10, 8) [000788] -A--G------- | +--* COMMA void N024 ( 3, 3) [000783] -A------R--- | | +--* ASG byref N023 ( 1, 1) [000782] D------N---- | | | +--* LCL_VAR byref V87 tmp57 d:2 N022 ( 3, 3) [000780] ------------ | | | \--* ADDR byref N021 ( 3, 2) [000781] -------N---- | | | \--* LCL_VAR struct(AX) V86 tmp56 N028 ( 7, 5) [000787] -A--G------- | | \--* ASG ref N026 ( 3, 2) [000785] *------N---- | | +--* IND ref N025 ( 1, 1) [000784] ------------ | | | \--* LCL_VAR byref V87 tmp57 u:2 Zero Fseq[_bits] N027 ( 3, 2) [000786] ----G--N---- | | \--* LCL_VAR ref (AX) V58 tmp28 N035 ( 8, 7) [000794] -A--G------- | \--* ASG int N033 ( 4, 4) [000792] *------N---- | +--* IND int N032 ( 2, 2) [000791] -------N---- | | \--* ADD byref N030 ( 1, 1) [000789] ------------ | | +--* LCL_VAR byref V87 tmp57 u:2 (last use) N031 ( 1, 1) [000790] ------------ | | \--* CNS_INT long 8 Fseq[_sign] N034 ( 3, 2) [000793] ----G--N---- | \--* LCL_VAR int (AX) V59 tmp29 N038 ( 3, 2) [000798] ------------ arg0 in rcx +--* LCL_VAR long V88 tmp58 u:2 (last use) N040 ( 3, 3) [000800] ------------ arg1 in rdx +--* ADDR byref N039 ( 3, 2) [000799] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 N042 ( 3, 3) [000802] ------------ arg2 in r8 +--* ADDR byref N041 ( 3, 2) [000801] -------N---- | \--* LCL_VAR struct(AX) V86 tmp56 N044 ( 3, 3) [000212] ------------ arg3 in r9 \--* ADDR long N043 ( 3, 2) [000211] ----G--N---- \--* LCL_VAR struct(AX)(P) V23 loc20 \--* ref V23._bits (offs=0x00) -> V60 tmp30 \--* int V23._sign (offs=0x08) -> V61 tmp31 ***** BB35 STMT00050 (IL ???... ???) N021 ( 38, 24) [000226] -ACXG---R--- * ASG long N020 ( 1, 1) [000225] D------N---- +--* LCL_VAR long V24 loc21 d:2 N019 ( 38, 24) [000218] -ACXG------- \--* CALL long System.Numerics.BigInteger.op_Explicit N016 ( 18, 15) [000822] -A--G-----L- arg0 SETUP +--* COMMA void N009 ( 10, 8) [000815] -A--G------- | +--* COMMA void N004 ( 3, 3) [000810] -A------R--- | | +--* ASG byref N003 ( 1, 1) [000809] D------N---- | | | +--* LCL_VAR byref V89 tmp59 d:2 N002 ( 3, 3) [000807] ------------ | | | \--* ADDR byref N001 ( 3, 2) [000808] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 N008 ( 7, 5) [000814] -A--G------- | | \--* ASG ref N006 ( 3, 2) [000812] *------N---- | | +--* IND ref N005 ( 1, 1) [000811] ------------ | | | \--* LCL_VAR byref V89 tmp59 u:2 Zero Fseq[_bits] N007 ( 3, 2) [000813] ----G--N---- | | \--* LCL_VAR ref (AX) V62 tmp32 N015 ( 8, 7) [000821] -A--G------- | \--* ASG int N013 ( 4, 4) [000819] *------N---- | +--* IND int N012 ( 2, 2) [000818] -------N---- | | \--* ADD byref N010 ( 1, 1) [000816] ------------ | | +--* LCL_VAR byref V89 tmp59 u:2 (last use) N011 ( 1, 1) [000817] ------------ | | \--* CNS_INT long 8 Fseq[_sign] N014 ( 3, 2) [000820] ----G--N---- | \--* LCL_VAR int (AX) V63 tmp33 N018 ( 3, 3) [000824] ------------ arg0 in rcx \--* ADDR byref N017 ( 3, 2) [000823] -------N---- \--* LCL_VAR struct(AX) V76 tmp46 ***** BB35 STMT00052 (IL ???... ???) N005 ( 12, 7) [000232] -A--G---R--- * ASG int N004 ( 3, 2) [000231] D------N---- +--* LCL_VAR int V25 loc22 d:2 N003 ( 8, 4) [000516] ----G------- \--* EQ int N001 ( 3, 2) [000514] ----G------- +--* LCL_VAR int (AX) V61 tmp31 N002 ( 1, 1) [000515] ------------ \--* CNS_INT int 0 ***** BB35 STMT00054 (IL ???... ???) N005 ( 19, 10) [000237] -ACXG---R--- * ASG int N004 ( 3, 2) [000236] D------N---- +--* LCL_VAR int V26 loc23 d:2 N003 ( 15, 7) [000234] --CXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits N002 ( 1, 1) [000233] ------------ arg0 in rcx \--* LCL_VAR long V24 loc21 u:2 ***** BB35 STMT00055 (IL 0x19E...0x1A2) N004 ( 9, 7) [000241] ------------ * JTRUE void N003 ( 7, 5) [000240] N------N-U-- \--* LE int N001 ( 3, 2) [000238] ------------ +--* LCL_VAR int V26 loc23 u:2 N002 ( 3, 2) [000239] ------------ \--* LCL_VAR int V20 loc17 u:2 ------------ BB36 [1A4..1AF) -> BB38 (cond), preds={BB35} succs={BB37,BB38} ***** BB36 STMT00063 (IL 0x1A4...0x1A9) N005 ( 11, 8) [000286] -A------R--- * ASG int N004 ( 3, 2) [000285] D------N---- +--* LCL_VAR int V29 loc26 d:2 N003 ( 7, 5) [000284] ------------ \--* SUB int N001 ( 3, 2) [000282] ------------ +--* LCL_VAR int V26 loc23 u:2 (last use) N002 ( 3, 2) [000283] ------------ \--* LCL_VAR int V20 loc17 u:2 ***** BB36 STMT00064 (IL 0x1AB...0x1AD) N004 ( 7, 6) [000290] ------------ * JTRUE void N003 ( 5, 4) [000289] J------N---- \--* EQ int N001 ( 3, 2) [000287] ------------ +--* LCL_VAR int V25 loc22 u:2 (last use) N002 ( 1, 1) [000288] ------------ \--* CNS_INT int 0 ------------ BB37 [1AF..1C3) -> BB39 (always), preds={BB36} succs={BB39} ***** BB37 STMT00068 (IL 0x1AF...0x1C1) N013 ( 23, 15) [000320] -A------R--- * ASG int N012 ( 3, 2) [000319] D------N---- +--* LCL_VAR int V37 tmp7 d:4 N011 ( 19, 12) [000318] ------------ \--* EQ int N009 ( 14, 10) [000315] ------------ +--* AND long N001 ( 1, 1) [000305] ------------ | +--* LCL_VAR long V24 loc21 u:2 N008 ( 12, 8) [000314] ------------ | \--* ADD long N006 ( 10, 6) [000311] --------R--- | +--* LSH long N005 ( 1, 1) [000307] ------------ | | +--* CNS_INT long 1 N004 ( 5, 4) [000310] ------------ | | \--* AND int N002 ( 3, 2) [000308] ------------ | | +--* LCL_VAR int V29 loc26 u:2 N003 ( 1, 1) [000309] ------------ | | \--* CNS_INT int 63 N007 ( 1, 1) [000313] ------------ | \--* CNS_INT long -1 N010 ( 1, 1) [000317] ------------ \--* CNS_INT long 0 ------------ BB38 [1C3..1C4), preds={BB36} succs={BB39} ***** BB38 STMT00065 (IL 0x1C3...0x1C3) N003 ( 5, 4) [000293] -A------R--- * ASG int N002 ( 3, 2) [000292] D------N---- +--* LCL_VAR int V37 tmp7 d:3 N001 ( 1, 1) [000291] ------------ \--* CNS_INT int 0 ------------ BB39 [1C4..1D0), preds={BB37,BB38} succs={BB40} ***** BB39 STMT00116 (IL ???... ???) N005 ( 0, 0) [000868] -A------R--- * ASG int N004 ( 0, 0) [000866] D------N---- +--* LCL_VAR int V37 tmp7 d:2 N003 ( 0, 0) [000867] ------------ \--* PHI int N001 ( 0, 0) [000897] ------------ pred BB37 +--* PHI_ARG int V37 tmp7 u:4 N002 ( 0, 0) [000896] ------------ pred BB38 \--* PHI_ARG int V37 tmp7 u:3 ***** BB39 STMT00066 (IL ???...0x1C4) N004 ( 8, 7) [000297] -A------R--- * ASG int N003 ( 3, 2) [000296] D------N---- +--* LCL_VAR int V25 loc22 d:4 N002 ( 4, 4) [000826] ------------ \--* CAST int <- bool <- int N001 ( 3, 2) [000295] ------------ \--* LCL_VAR int V37 tmp7 u:2 (last use) ***** BB39 STMT00067 (IL 0x1C6...0x1CE) N007 ( 10, 6) [000304] -A------R--- * ASG long N006 ( 1, 1) [000303] D------N---- +--* LCL_VAR long V24 loc21 d:4 N005 ( 10, 6) [000302] ------------ \--* RSZ long N001 ( 1, 1) [000298] ------------ +--* LCL_VAR long V24 loc21 u:2 (last use) N004 ( 5, 4) [000301] ------------ \--* AND int N002 ( 3, 2) [000299] ------------ +--* LCL_VAR int V29 loc26 u:2 (last use) N003 ( 1, 1) [000300] ------------ \--* CNS_INT int 63 ------------ BB40 [1D0..1E7) -> BB42 (cond), preds={BB35,BB39} succs={BB41,BB42} ***** BB40 STMT00115 (IL ???... ???) N005 ( 0, 0) [000865] -A------R--- * ASG bool N004 ( 0, 0) [000863] D------N---- +--* LCL_VAR bool V25 loc22 d:3 N003 ( 0, 0) [000864] ------------ \--* PHI bool N001 ( 0, 0) [000894] ------------ pred BB39 +--* PHI_ARG bool V25 loc22 u:4 N002 ( 0, 0) [000889] ------------ pred BB35 \--* PHI_ARG bool V25 loc22 u:2 ***** BB40 STMT00114 (IL ???... ???) N005 ( 0, 0) [000862] -A------R--- * ASG long N004 ( 0, 0) [000860] D------N---- +--* LCL_VAR long V24 loc21 d:3 N003 ( 0, 0) [000861] ------------ \--* PHI long N001 ( 0, 0) [000895] ------------ pred BB39 +--* PHI_ARG long V24 loc21 u:4 N002 ( 0, 0) [000890] ------------ pred BB35 \--* PHI_ARG long V24 loc21 u:2 ***** BB40 STMT00057 (IL ???... ???) N027 ( 53, 34) [000254] -ACXG---R--- * ASG long N026 ( 3, 2) [000253] D------N---- +--* LCL_VAR long V27 loc24 d:2 N025 ( 49, 31) [000252] -ACXG------- \--* ADD long N023 ( 47, 29) [000250] -ACXG------- +--* LSH long N019 ( 38, 24) [000243] -ACXG------- | +--* CALL long System.Numerics.BigInteger.op_Explicit N016 ( 18, 15) [000845] -A--G-----L- arg0 SETUP | | +--* COMMA void N009 ( 10, 8) [000838] -A--G------- | | | +--* COMMA void N004 ( 3, 3) [000833] -A------R--- | | | | +--* ASG byref N003 ( 1, 1) [000832] D------N---- | | | | | +--* LCL_VAR byref V90 tmp60 d:2 N002 ( 3, 3) [000830] ------------ | | | | | \--* ADDR byref N001 ( 3, 2) [000831] ----G--N---- | | | | | \--* LCL_VAR struct(AX) V76 tmp46 N008 ( 7, 5) [000837] -A--G------- | | | | \--* ASG ref N006 ( 3, 2) [000835] *------N---- | | | | +--* IND ref N005 ( 1, 1) [000834] ------------ | | | | | \--* LCL_VAR byref V90 tmp60 u:2 Zero Fseq[_bits] N007 ( 3, 2) [000836] ----G--N---- | | | | \--* LCL_VAR ref (AX) V54 tmp24 N015 ( 8, 7) [000844] -A--G------- | | | \--* ASG int N013 ( 4, 4) [000842] *------N---- | | | +--* IND int N012 ( 2, 2) [000841] -------N---- | | | | \--* ADD byref N010 ( 1, 1) [000839] ------------ | | | | +--* LCL_VAR byref V90 tmp60 u:2 (last use) N011 ( 1, 1) [000840] ------------ | | | | \--* CNS_INT long 8 Fseq[_sign] N014 ( 3, 2) [000843] ----G--N---- | | | \--* LCL_VAR int (AX) V55 tmp25 N018 ( 3, 3) [000847] ------------ arg0 in rcx | | \--* ADDR byref N017 ( 3, 2) [000846] -------N---- | | \--* LCL_VAR struct(AX) V76 tmp46 N022 ( 5, 4) [000249] ------------ | \--* AND int N020 ( 3, 2) [000247] ------------ | +--* LCL_VAR int V20 loc17 u:2 (last use) N021 ( 1, 1) [000248] ------------ | \--* CNS_INT int 63 N024 ( 1, 1) [000251] ------------ \--* LCL_VAR long V24 loc21 u:3 (last use) ***** BB40 STMT00058 (IL 0x1E2...0x1E5) N004 ( 5, 5) [000258] ------------ * JTRUE void N003 ( 3, 3) [000257] N------N---- \--* NE int N001 ( 1, 1) [000255] ------------ +--* LCL_VAR int V13 loc10 u:2 N002 ( 1, 1) [000256] ------------ \--* CNS_INT int 0 ------------ BB41 [1E7..1EE) -> BB43 (always), preds={BB40} succs={BB43} ***** BB41 STMT00062 (IL 0x1E7...0x1EC) N006 ( 10, 8) [000280] -A------R--- * ASG int N005 ( 3, 2) [000279] D------N---- +--* LCL_VAR int V36 tmp6 d:4 N004 ( 6, 5) [000278] ------------ \--* ADD int N002 ( 4, 3) [000276] ------------ +--* NEG int N001 ( 3, 2) [000275] ------------ | \--* LCL_VAR int V22 loc19 u:2 (last use) N003 ( 1, 1) [000277] ------------ \--* CNS_INT int -1 ------------ BB42 [1EE..1F2), preds={BB40} succs={BB43} ***** BB42 STMT00059 (IL 0x1EE...0x1F1) N005 ( 7, 6) [000263] -A------R--- * ASG int N004 ( 3, 2) [000262] D------N---- +--* LCL_VAR int V36 tmp6 d:3 N003 ( 3, 3) [000261] ------------ \--* ADD int N001 ( 1, 1) [000259] ------------ +--* LCL_VAR int V13 loc10 u:2 (last use) N002 ( 1, 1) [000260] ------------ \--* CNS_INT int -2 ------------ BB43 [1F2..202), preds={BB41,BB42} succs={BB44} ***** BB43 STMT00113 (IL ???... ???) N005 ( 0, 0) [000859] -A------R--- * ASG int N004 ( 0, 0) [000857] D------N---- +--* LCL_VAR int V36 tmp6 d:2 N003 ( 0, 0) [000858] ------------ \--* PHI int N001 ( 0, 0) [000893] ------------ pred BB41 +--* PHI_ARG int V36 tmp6 u:4 N002 ( 0, 0) [000892] ------------ pred BB42 \--* PHI_ARG int V36 tmp6 u:3 ***** BB43 STMT00061 (IL 0x1F4...0x201) N012 ( 28, 18) [000853] -ACXG---R--- * ASG int N011 ( 1, 1) [000852] D------N---- +--* LCL_VAR int V51 tmp21 d:4 N010 ( 28, 18) [000273] --CXG------- \--* CALL nullcheck int FloatingPointType.AssembleFloatingPointValue N005 ( 1, 1) [000272] ------------ arg4 out+20 +--* LCL_VAR byref V02 arg2 u:1 (last use) N006 ( 1, 1) [000268] ------------ this in rcx +--* LCL_VAR ref V01 arg1 u:1 (last use) N007 ( 3, 2) [000269] ------------ arg1 in rdx +--* LCL_VAR long V27 loc24 u:2 (last use) N008 ( 3, 2) [000270] ------------ arg2 in r8 +--* LCL_VAR int V36 tmp6 u:2 (last use) N009 ( 3, 2) [000271] ------------ arg3 in r9 \--* LCL_VAR int V25 loc22 u:3 (last use) ------------ BB44 [???..???) (return), preds={BB16,BB30,BB43} succs={} ***** BB44 STMT00112 (IL ???... ???) N006 ( 0, 0) [000856] -A------R--- * ASG int N005 ( 0, 0) [000854] D------N---- +--* LCL_VAR int V51 tmp21 d:2 N004 ( 0, 0) [000855] ------------ \--* PHI int N001 ( 0, 0) [000901] ------------ pred BB30 +--* PHI_ARG int V51 tmp21 u:5 N002 ( 0, 0) [000891] ------------ pred BB43 +--* PHI_ARG int V51 tmp21 u:4 N003 ( 0, 0) [000887] ------------ pred BB16 \--* PHI_ARG int V51 tmp21 u:3 ***** BB44 STMT00109 (IL ???... ???) N002 ( 2, 2) [000523] ------------ * RETURN int N001 ( 1, 1) [000522] -------N---- \--* LCL_VAR int V51 tmp21 u:2 (last use) ------------------------------------------------------------------------------------------------------------------- *************** Finishing PHASE Early Value Propagation *************** Starting PHASE Do value numbering *************** In fgValueNumber() Memory Initial Value in BB01 is: $c1 The SSA definition for ByrefExposed (#1) at start of BB01 is $c1 {InitVal($43)} The SSA definition for GcHeap (#1) at start of BB01 is $c1 {InitVal($43)} ***** BB01, STMT00111(before) N011 ( 7, 7) [000540] -A---------- * COMMA void N004 ( 3, 3) [000533] -A------R--- +--* ASG ref N003 ( 1, 1) [000530] D------N---- | +--* LCL_VAR ref V52 tmp22 d:2 N002 ( 3, 2) [000532] n----------- | \--* IND ref N001 ( 1, 1) [000531] ------------ | \--* LCL_VAR byref V00 arg0 u:1 Zero Fseq[Mantissa] N010 ( 4, 4) [000539] -A------R--- \--* ASG int N009 ( 1, 1) [000534] D------N---- +--* LCL_VAR int V53 tmp23 d:2 N008 ( 4, 4) [000538] n----------- \--* IND int N007 ( 2, 2) [000537] -------N---- \--* ADD byref N005 ( 1, 1) [000535] ------------ +--* LCL_VAR byref V00 arg0 u:1 (last use) N006 ( 1, 1) [000536] ------------ \--* CNS_INT long 8 Fseq[Exponent] N001 [000531] LCL_VAR V00 arg0 u:1 => $80 {InitVal($40)} N002 [000532] IND => N003 [000530] LCL_VAR V52 tmp22 d:2 => N004 [000533] ASG => N005 [000535] LCL_VAR V00 arg0 u:1 (last use) => $80 {InitVal($40)} N006 [000536] CNS_INT 8 Fseq[Exponent] => $101 {LngCns: 8} N007 [000537] ADD => $200 {ADD($80, $101)} N008 [000538] IND => N009 [000534] LCL_VAR V53 tmp23 d:2 => N010 [000539] ASG => N011 [000540] COMMA => ***** BB01, STMT00111(after) N011 ( 7, 7) [000540] -A---------- * COMMA void N004 ( 3, 3) [000533] -A------R--- +--* ASG ref N003 ( 1, 1) [000530] D------N---- | +--* LCL_VAR ref V52 tmp22 d:2 N002 ( 3, 2) [000532] n----------- | \--* IND ref N001 ( 1, 1) [000531] ------------ | \--* LCL_VAR byref V00 arg0 u:1 Zero Fseq[Mantissa] $80 N010 ( 4, 4) [000539] -A------R--- \--* ASG int N009 ( 1, 1) [000534] D------N---- +--* LCL_VAR int V53 tmp23 d:2 N008 ( 4, 4) [000538] n----------- \--* IND int N007 ( 2, 2) [000537] -------N---- \--* ADD byref $200 N005 ( 1, 1) [000535] ------------ +--* LCL_VAR byref V00 arg0 u:1 (last use) $80 N006 ( 1, 1) [000536] ------------ \--* CNS_INT long 8 Fseq[Exponent] $101 finish(BB01). Succ(BB02). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#1) at start of BB02 is $c1 {InitVal($43)} The SSA definition for GcHeap (#1) at start of BB02 is $c1 {InitVal($43)} ***** BB02, STMT00000(before) N005 ( 7, 7) [000006] ---XG------- * JTRUE void N004 ( 5, 5) [000005] J--XG--N---- \--* NE int N002 ( 3, 3) [000003] ---XG------- +--* ARR_LENGTH int N001 ( 1, 1) [000002] ------------ | \--* LCL_VAR ref V52 tmp22 u:2 N003 ( 1, 1) [000004] ------------ \--* CNS_INT int 0 N001 [000002] LCL_VAR V52 tmp22 u:2 => N002 [000003] ARR_LENGTH => N003 [000004] CNS_INT 0 => $40 {IntCns 0} N004 [000005] NE => ***** BB02, STMT00000(after) N005 ( 7, 7) [000006] ---XG------- * JTRUE void N004 ( 5, 5) [000005] J--XG--N---- \--* NE int N002 ( 3, 3) [000003] ---XG------- +--* ARR_LENGTH int N001 ( 1, 1) [000002] ------------ | \--* LCL_VAR ref V52 tmp22 u:2 N003 ( 1, 1) [000004] ------------ \--* CNS_INT int 0 $40 finish(BB02). Succ(BB03). Not yet completed. All preds complete, adding to allDone. Succ(BB04). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#1) at start of BB04 is $c1 {InitVal($43)} The SSA definition for GcHeap (#1) at start of BB04 is $c1 {InitVal($43)} ***** BB04, STMT00002(before) N010 ( 30, 19) [000013] -ACXG---R--- * ASG int N009 ( 3, 2) [000012] D------N---- +--* LCL_VAR int V03 loc0 d:2 N008 ( 26, 16) [000011] --CXG------- \--* ADD int N006 ( 24, 14) [000409] --CXG------- +--* CAST int <- ushort <- int N005 ( 23, 12) [000408] --CXG------- | \--* ADD int N003 ( 21, 10) [000406] --CXG------- | +--* CALLV ind int FloatingPointType.get_DenormalMantissaBits N002 ( 1, 1) [000007] ------------ this in rcx | | \--* LCL_VAR ref V01 arg1 u:1 N004 ( 1, 1) [000407] ------------ | \--* CNS_INT int 1 N007 ( 1, 1) [000010] ------------ \--* CNS_INT int 1 N001 [000542] ARGPLACE => $1c2 {1c2} N002 [000007] LCL_VAR V01 arg1 u:1 => $c0 {InitVal($41)} fgCurMemoryVN[GcHeap] assigned for CALL at [000406] to VN: $1c3. N003 [000406] CALLV ind => $282 {282} N004 [000407] CNS_INT 1 => $41 {IntCns 1} N005 [000408] ADD => $346 {ADD($41, $282)} VNForCastOper(ushort) is $46 N006 [000409] CAST => $347 {Cast($346, $46)} N007 [000010] CNS_INT 1 => $41 {IntCns 1} N008 [000011] ADD => $348 {ADD($41, $347)} N009 [000012] LCL_VAR V03 loc0 d:2 => $348 {ADD($41, $347)} N010 [000013] ASG => $348 {ADD($41, $347)} ***** BB04, STMT00002(after) N010 ( 30, 19) [000013] -ACXG---R--- * ASG int $348 N009 ( 3, 2) [000012] D------N---- +--* LCL_VAR int V03 loc0 d:2 $348 N008 ( 26, 16) [000011] --CXG------- \--* ADD int $348 N006 ( 24, 14) [000409] --CXG------- +--* CAST int <- ushort <- int $347 N005 ( 23, 12) [000408] --CXG------- | \--* ADD int $346 N003 ( 21, 10) [000406] --CXG------- | +--* CALLV ind int FloatingPointType.get_DenormalMantissaBits $282 N002 ( 1, 1) [000007] ------------ this in rcx | | \--* LCL_VAR ref V01 arg1 u:1 $c0 N004 ( 1, 1) [000407] ------------ | \--* CNS_INT int 1 $41 N007 ( 1, 1) [000010] ------------ \--* CNS_INT int 1 $41 --------- ***** BB04, STMT00092(before) N003 ( 5, 4) [000424] -A--G---R--- * ASG int N002 ( 3, 2) [000423] D------N---- +--* LCL_VAR int V40 tmp10 d:2 N001 ( 1, 1) [000017] ------------ \--* LCL_VAR int V53 tmp23 u:2 N001 [000017] LCL_VAR V53 tmp23 u:2 => N002 [000423] LCL_VAR V40 tmp10 d:2 => N003 [000424] ASG => ***** BB04, STMT00092(after) N003 ( 5, 4) [000424] -A--G---R--- * ASG int N002 ( 3, 2) [000423] D------N---- +--* LCL_VAR int V40 tmp10 d:2 N001 ( 1, 1) [000017] ------------ \--* LCL_VAR int V53 tmp23 u:2 --------- ***** BB04, STMT00089(before) N004 ( 5, 5) [000414] ------------ * JTRUE void N003 ( 3, 3) [000413] J------N---- \--* LE int N001 ( 1, 1) [000412] ------------ +--* LCL_VAR int V53 tmp23 u:2 N002 ( 1, 1) [000411] ------------ \--* CNS_INT int 0 N001 [000412] LCL_VAR V53 tmp23 u:2 => N002 [000411] CNS_INT 0 => $40 {IntCns 0} N003 [000413] LE => ***** BB04, STMT00089(after) N004 ( 5, 5) [000414] ------------ * JTRUE void N003 ( 3, 3) [000413] J------N---- \--* LE int N001 ( 1, 1) [000412] ------------ +--* LCL_VAR int V53 tmp23 u:2 N002 ( 1, 1) [000411] ------------ \--* CNS_INT int 0 $40 finish(BB04). Succ(BB05). Not yet completed. All preds complete, adding to allDone. Succ(BB06). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#2) at start of BB06 is $380 {380} The SSA definition for GcHeap (#3) at start of BB06 is $1c3 {1c3} ***** BB06, STMT00090(before) N003 ( 5, 4) [000417] -A------R--- * ASG int N002 ( 3, 2) [000416] D------N---- +--* LCL_VAR int V39 tmp9 d:3 N001 ( 1, 1) [000415] ------------ \--* CNS_INT int 0 N001 [000415] CNS_INT 0 => $40 {IntCns 0} N002 [000416] LCL_VAR V39 tmp9 d:3 => $40 {IntCns 0} N003 [000417] ASG => $40 {IntCns 0} ***** BB06, STMT00090(after) N003 ( 5, 4) [000417] -A------R--- * ASG int $40 N002 ( 3, 2) [000416] D------N---- +--* LCL_VAR int V39 tmp9 d:3 $40 N001 ( 1, 1) [000415] ------------ \--* CNS_INT int 0 $40 finish(BB06). Succ(BB07). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#2) at start of BB05 is $380 {380} The SSA definition for GcHeap (#3) at start of BB05 is $1c3 {1c3} ***** BB05, STMT00091(before) N003 ( 7, 5) [000421] -A------R--- * ASG int N002 ( 3, 2) [000420] D------N---- +--* LCL_VAR int V39 tmp9 d:4 N001 ( 3, 2) [000419] ------------ \--* LCL_VAR int V40 tmp10 u:2 (last use) N001 [000419] LCL_VAR V40 tmp10 u:2 (last use) => N002 [000420] LCL_VAR V39 tmp9 d:4 => N003 [000421] ASG => ***** BB05, STMT00091(after) N003 ( 7, 5) [000421] -A------R--- * ASG int N002 ( 3, 2) [000420] D------N---- +--* LCL_VAR int V39 tmp9 d:4 N001 ( 3, 2) [000419] ------------ \--* LCL_VAR int V40 tmp10 u:2 (last use) finish(BB05). Succ(BB07). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 39/2 to $241 {PhiDef($27, $2, $34b)} . The SSA definition for ByrefExposed (#2) at start of BB07 is $380 {380} The SSA definition for GcHeap (#3) at start of BB07 is $1c3 {1c3} ***** BB07, STMT00004(before) N003 ( 3, 3) [000021] -A------R--- * ASG int N002 ( 1, 1) [000020] D------N---- +--* LCL_VAR int V31 tmp1 d:2 N001 ( 3, 2) [000422] ------------ \--* LCL_VAR int V39 tmp9 u:2 N001 [000422] LCL_VAR V39 tmp9 u:2 => $241 {PhiDef($27, $2, $34b)} N002 [000020] LCL_VAR V31 tmp1 d:2 => $241 {PhiDef($27, $2, $34b)} N003 [000021] ASG => $241 {PhiDef($27, $2, $34b)} ***** BB07, STMT00004(after) N003 ( 3, 3) [000021] -A------R--- * ASG int $241 N002 ( 1, 1) [000020] D------N---- +--* LCL_VAR int V31 tmp1 d:2 $241 N001 ( 3, 2) [000422] ------------ \--* LCL_VAR int V39 tmp9 u:2 $241 --------- ***** BB07, STMT00096(before) N004 ( 3, 3) [000443] -A-XG---R--- * ASG int N003 ( 1, 1) [000442] D------N---- +--* LCL_VAR int V42 tmp12 d:2 N002 ( 3, 3) [000429] ---XG------- \--* ARR_LENGTH int N001 ( 1, 1) [000428] ------------ \--* LCL_VAR ref V52 tmp22 u:2 N001 [000428] LCL_VAR V52 tmp22 u:2 => N002 [000429] ARR_LENGTH => N003 [000442] LCL_VAR V42 tmp12 d:2 => N004 [000443] ASG => ***** BB07, STMT00096(after) N004 ( 3, 3) [000443] -A-XG---R--- * ASG int N003 ( 1, 1) [000442] D------N---- +--* LCL_VAR int V42 tmp12 d:2 N002 ( 3, 3) [000429] ---XG------- \--* ARR_LENGTH int N001 ( 1, 1) [000428] ------------ \--* LCL_VAR ref V52 tmp22 u:2 --------- ***** BB07, STMT00093(before) N004 ( 7, 6) [000433] ------------ * JTRUE void N003 ( 5, 4) [000432] N------N-U-- \--* LE int N001 ( 3, 2) [000023] ------------ +--* LCL_VAR int V39 tmp9 u:2 (last use) N002 ( 1, 1) [000431] ------------ \--* LCL_VAR int V42 tmp12 u:2 N001 [000023] LCL_VAR V39 tmp9 u:2 (last use) => $241 {PhiDef($27, $2, $34b)} N002 [000431] LCL_VAR V42 tmp12 u:2 => N003 [000432] LE => ***** BB07, STMT00093(after) N004 ( 7, 6) [000433] ------------ * JTRUE void N003 ( 5, 4) [000432] N------N-U-- \--* LE int N001 ( 3, 2) [000023] ------------ +--* LCL_VAR int V39 tmp9 u:2 (last use) $241 N002 ( 1, 1) [000431] ------------ \--* LCL_VAR int V42 tmp12 u:2 finish(BB07). Succ(BB08). Not yet completed. All preds complete, adding to allDone. Succ(BB09). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#2) at start of BB09 is $380 {380} The SSA definition for GcHeap (#3) at start of BB09 is $1c3 {1c3} ***** BB09, STMT00094(before) N003 ( 1, 3) [000436] -A------R--- * ASG int N002 ( 1, 1) [000435] D------N---- +--* LCL_VAR int V41 tmp11 d:3 N001 ( 1, 1) [000434] ------------ \--* LCL_VAR int V31 tmp1 u:2 N001 [000434] LCL_VAR V31 tmp1 u:2 => $241 {PhiDef($27, $2, $34b)} N002 [000435] LCL_VAR V41 tmp11 d:3 => $241 {PhiDef($27, $2, $34b)} N003 [000436] ASG => $241 {PhiDef($27, $2, $34b)} ***** BB09, STMT00094(after) N003 ( 1, 3) [000436] -A------R--- * ASG int $241 N002 ( 1, 1) [000435] D------N---- +--* LCL_VAR int V41 tmp11 d:3 $241 N001 ( 1, 1) [000434] ------------ \--* LCL_VAR int V31 tmp1 u:2 $241 finish(BB09). Succ(BB10). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#2) at start of BB08 is $380 {380} The SSA definition for GcHeap (#3) at start of BB08 is $1c3 {1c3} ***** BB08, STMT00095(before) N003 ( 1, 3) [000440] -A------R--- * ASG int N002 ( 1, 1) [000439] D------N---- +--* LCL_VAR int V41 tmp11 d:4 N001 ( 1, 1) [000438] ------------ \--* LCL_VAR int V42 tmp12 u:2 (last use) N001 [000438] LCL_VAR V42 tmp12 u:2 (last use) => N002 [000439] LCL_VAR V41 tmp11 d:4 => N003 [000440] ASG => ***** BB08, STMT00095(after) N003 ( 1, 3) [000440] -A------R--- * ASG int N002 ( 1, 1) [000439] D------N---- +--* LCL_VAR int V41 tmp11 d:4 N001 ( 1, 1) [000438] ------------ \--* LCL_VAR int V42 tmp12 u:2 (last use) finish(BB08). Succ(BB10). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 41/2 to $242 {PhiDef($29, $2, $34b)} . The SSA definition for ByrefExposed (#2) at start of BB10 is $380 {380} The SSA definition for GcHeap (#3) at start of BB10 is $1c3 {1c3} ***** BB10, STMT00008(before) N005 ( 7, 6) [000035] -A------R--- * ASG int N004 ( 3, 2) [000034] D------N---- +--* LCL_VAR int V05 loc2 d:2 N003 ( 3, 3) [000033] ------------ \--* SUB int N001 ( 1, 1) [000022] ------------ +--* LCL_VAR int V31 tmp1 u:2 (last use) N002 ( 1, 1) [000032] ------------ \--* LCL_VAR int V41 tmp11 u:2 N001 [000022] LCL_VAR V31 tmp1 u:2 (last use) => $241 {PhiDef($27, $2, $34b)} N002 [000032] LCL_VAR V41 tmp11 u:2 => $242 {PhiDef($29, $2, $34b)} N003 [000033] SUB => $34e {SUB($241, $242)} N004 [000034] LCL_VAR V05 loc2 d:2 => $34e {SUB($241, $242)} N005 [000035] ASG => $34e {SUB($241, $242)} ***** BB10, STMT00008(after) N005 ( 7, 6) [000035] -A------R--- * ASG int $34e N004 ( 3, 2) [000034] D------N---- +--* LCL_VAR int V05 loc2 d:2 $34e N003 ( 3, 3) [000033] ------------ \--* SUB int $34e N001 ( 1, 1) [000022] ------------ +--* LCL_VAR int V31 tmp1 u:2 (last use) $241 N002 ( 1, 1) [000032] ------------ \--* LCL_VAR int V41 tmp11 u:2 $242 --------- ***** BB10, STMT00011(before) N003 ( 5, 4) [000044] -A------R--- * ASG int N002 ( 3, 2) [000043] D------N---- +--* LCL_VAR int V08 loc5 d:2 N001 ( 1, 1) [000042] ------------ \--* LCL_VAR int V41 tmp11 u:2 N001 [000042] LCL_VAR V41 tmp11 u:2 => $242 {PhiDef($29, $2, $34b)} N002 [000043] LCL_VAR V08 loc5 d:2 => $242 {PhiDef($29, $2, $34b)} N003 [000044] ASG => $242 {PhiDef($29, $2, $34b)} ***** BB10, STMT00011(after) N003 ( 5, 4) [000044] -A------R--- * ASG int $242 N002 ( 3, 2) [000043] D------N---- +--* LCL_VAR int V08 loc5 d:2 $242 N001 ( 1, 1) [000042] ------------ \--* LCL_VAR int V41 tmp11 u:2 $242 --------- ***** BB10, STMT00013(before) N004 ( 7, 6) [000050] -A-XG---R--- * ASG int N003 ( 3, 2) [000049] D------N---- +--* LCL_VAR int V09 loc6 d:2 N002 ( 3, 3) [000448] ---XG------- \--* ARR_LENGTH int N001 ( 1, 1) [000447] ------------ \--* LCL_VAR ref V52 tmp22 u:2 N001 [000447] LCL_VAR V52 tmp22 u:2 => N002 [000448] ARR_LENGTH => N003 [000049] LCL_VAR V09 loc6 d:2 => N004 [000050] ASG => ***** BB10, STMT00013(after) N004 ( 7, 6) [000050] -A-XG---R--- * ASG int N003 ( 3, 2) [000049] D------N---- +--* LCL_VAR int V09 loc6 d:2 N002 ( 3, 3) [000448] ---XG------- \--* ARR_LENGTH int N001 ( 1, 1) [000447] ------------ \--* LCL_VAR ref V52 tmp22 u:2 --------- ***** BB10, STMT00014(before) N005 ( 5, 4) [000055] -A------R--- * ASG int N004 ( 1, 1) [000054] D------N---- +--* LCL_VAR int V10 loc7 d:2 N003 ( 5, 4) [000053] ------------ \--* SUB int N001 ( 3, 2) [000051] ------------ +--* LCL_VAR int V09 loc6 u:2 N002 ( 1, 1) [000052] ------------ \--* LCL_VAR int V41 tmp11 u:2 N001 [000051] LCL_VAR V09 loc6 u:2 => N002 [000052] LCL_VAR V41 tmp11 u:2 => $242 {PhiDef($29, $2, $34b)} N003 [000053] SUB => N004 [000054] LCL_VAR V10 loc7 d:2 => N005 [000055] ASG => ***** BB10, STMT00014(after) N005 ( 5, 4) [000055] -A------R--- * ASG int N004 ( 1, 1) [000054] D------N---- +--* LCL_VAR int V10 loc7 d:2 N003 ( 5, 4) [000053] ------------ \--* SUB int N001 ( 3, 2) [000051] ------------ +--* LCL_VAR int V09 loc6 u:2 N002 ( 1, 1) [000052] ------------ \--* LCL_VAR int V41 tmp11 u:2 $242 --------- ***** BB10, STMT00016(before) N028 ( 49, 35) [000059] SACXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger N004 ( 7, 6) [000563] -A------R-L- arg0 SETUP +--* ASG long N003 ( 3, 2) [000562] D------N---- | +--* LCL_VAR long V75 tmp45 d:2 N002 ( 3, 3) [000064] ------------ | \--* ADDR long N001 ( 3, 2) [000063] ----G--N---- | \--* LCL_VAR struct(AX)(P) V11 loc8 | \--* ref V11._bits (offs=0x00) -> V54 tmp24 | \--* int V11._sign (offs=0x08) -> V55 tmp25 N020 ( 14, 13) [000561] -A--------L- arg1 SETUP +--* COMMA void N013 ( 8, 7) [000554] -A---------- | +--* COMMA void N008 ( 3, 3) [000549] -A------R--- | | +--* ASG byref N007 ( 1, 1) [000548] D------N---- | | | +--* LCL_VAR byref V74 tmp44 d:2 N006 ( 3, 3) [000546] ------------ | | | \--* ADDR byref N005 ( 3, 2) [000547] -------N---- | | | \--* LCL_VAR struct(AX) V73 tmp43 N012 ( 5, 4) [000553] -A---------- | | \--* ASG ref N010 ( 3, 2) [000551] *------N---- | | +--* IND ref N009 ( 1, 1) [000550] ------------ | | | \--* LCL_VAR byref V74 tmp44 u:2 Zero Fseq[Mantissa] N011 ( 1, 1) [000552] -------N---- | | \--* LCL_VAR ref V52 tmp22 u:2 N019 ( 6, 6) [000560] -A---------- | \--* ASG int N017 ( 4, 4) [000558] *------N---- | +--* IND int N016 ( 2, 2) [000557] -------N---- | | \--* ADD byref N014 ( 1, 1) [000555] ------------ | | +--* LCL_VAR byref V74 tmp44 u:2 (last use) N015 ( 1, 1) [000556] ------------ | | \--* CNS_INT long 8 Fseq[Exponent] N018 ( 1, 1) [000559] -------N---- | \--* LCL_VAR int V53 tmp23 u:2 N023 ( 3, 2) [000564] ------------ arg0 in rcx +--* LCL_VAR long V75 tmp45 u:2 (last use) N025 ( 3, 3) [000566] ------------ arg1 in rdx +--* ADDR byref N024 ( 3, 2) [000565] -------N---- | \--* LCL_VAR struct(AX) V73 tmp43 N026 ( 1, 1) [000058] ------------ arg3 in r9 +--* LCL_VAR int V41 tmp11 u:2 (last use) N027 ( 1, 1) [000057] ------------ arg2 in r8 \--* CNS_INT int 0 N001 [000063] LCL_VAR V11 loc8 ref V11._bits (offs=0x00) -> V54 tmp24 int V11._sign (offs=0x08) -> V55 tmp25 => $3c0 {3c0} N002 [000064] ADDR => $400 {400} N003 [000562] LCL_VAR V75 tmp45 d:2 => $400 {400} N004 [000563] ASG => $400 {400} N005 [000547] LCL_VAR V73 tmp43 => $3c1 {3c1} N006 [000546] ADDR => $401 {401} N007 [000548] LCL_VAR V74 tmp44 d:2 => $401 {401} N008 [000549] ASG => $401 {401} N009 [000550] LCL_VAR V74 tmp44 u:2 => $401 {401} N011 [000552] LCL_VAR V52 tmp22 u:2 => fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [000553] to VN: $1c4. N012 [000553] ASG => $VN.Void N013 [000554] COMMA => $VN.Void N014 [000555] LCL_VAR V74 tmp44 u:2 (last use) => $401 {401} N015 [000556] CNS_INT 8 Fseq[Exponent] => $101 {LngCns: 8} N016 [000557] ADD => $203 {ADD($101, $401)} N018 [000559] LCL_VAR V53 tmp23 u:2 => fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [000560] to VN: $1c5. N019 [000560] ASG => $VN.Void N020 [000561] COMMA => $VN.Void N021 [000568] ARGPLACE => $28f {28f} N022 [000567] ARGPLACE => $290 {290} N023 [000564] LCL_VAR V75 tmp45 u:2 (last use) => $400 {400} N024 [000565] LCL_VAR V73 tmp43 => $3c2 {3c2} N025 [000566] ADDR => $403 {403} N026 [000058] LCL_VAR V41 tmp11 u:2 (last use) => $242 {PhiDef($29, $2, $34b)} N027 [000057] CNS_INT 0 => $40 {IntCns 0} VN of ARGPLACE tree [000568] updated to $40 {IntCns 0} VN of ARGPLACE tree [000567] updated to $242 {PhiDef($29, $2, $34b)} fgCurMemoryVN[GcHeap] assigned for CALL at [000059] to VN: $1c6. N028 [000059] CALL => $VN.Void ***** BB10, STMT00016(after) N028 ( 49, 35) [000059] SACXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger $VN.Void N004 ( 7, 6) [000563] -A------R-L- arg0 SETUP +--* ASG long $400 N003 ( 3, 2) [000562] D------N---- | +--* LCL_VAR long V75 tmp45 d:2 $400 N002 ( 3, 3) [000064] ------------ | \--* ADDR long $400 N001 ( 3, 2) [000063] ----G--N---- | \--* LCL_VAR struct(AX)(P) V11 loc8 | \--* ref V11._bits (offs=0x00) -> V54 tmp24 | \--* int V11._sign (offs=0x08) -> V55 tmp25 $3c0 N020 ( 14, 13) [000561] -A--------L- arg1 SETUP +--* COMMA void $VN.Void N013 ( 8, 7) [000554] -A---------- | +--* COMMA void $VN.Void N008 ( 3, 3) [000549] -A------R--- | | +--* ASG byref $401 N007 ( 1, 1) [000548] D------N---- | | | +--* LCL_VAR byref V74 tmp44 d:2 $401 N006 ( 3, 3) [000546] ------------ | | | \--* ADDR byref $401 N005 ( 3, 2) [000547] -------N---- | | | \--* LCL_VAR struct(AX) V73 tmp43 $3c1 N012 ( 5, 4) [000553] -A---------- | | \--* ASG ref $VN.Void N010 ( 3, 2) [000551] *------N---- | | +--* IND ref N009 ( 1, 1) [000550] ------------ | | | \--* LCL_VAR byref V74 tmp44 u:2 Zero Fseq[Mantissa] $401 N011 ( 1, 1) [000552] -------N---- | | \--* LCL_VAR ref V52 tmp22 u:2 N019 ( 6, 6) [000560] -A---------- | \--* ASG int $VN.Void N017 ( 4, 4) [000558] *------N---- | +--* IND int N016 ( 2, 2) [000557] -------N---- | | \--* ADD byref $203 N014 ( 1, 1) [000555] ------------ | | +--* LCL_VAR byref V74 tmp44 u:2 (last use) $401 N015 ( 1, 1) [000556] ------------ | | \--* CNS_INT long 8 Fseq[Exponent] $101 N018 ( 1, 1) [000559] -------N---- | \--* LCL_VAR int V53 tmp23 u:2 N023 ( 3, 2) [000564] ------------ arg0 in rcx +--* LCL_VAR long V75 tmp45 u:2 (last use) $400 N025 ( 3, 3) [000566] ------------ arg1 in rdx +--* ADDR byref $403 N024 ( 3, 2) [000565] -------N---- | \--* LCL_VAR struct(AX) V73 tmp43 $3c2 N026 ( 1, 1) [000058] ------------ arg3 in r9 +--* LCL_VAR int V41 tmp11 u:2 (last use) $242 N027 ( 1, 1) [000057] ------------ arg2 in r8 \--* CNS_INT int 0 $40 --------- ***** BB10, STMT00017(before) N004 ( 7, 6) [000068] ------------ * JTRUE void N003 ( 5, 4) [000067] N------N---- \--* EQ int N001 ( 3, 2) [000065] ------------ +--* LCL_VAR int V05 loc2 u:2 N002 ( 1, 1) [000066] ------------ \--* CNS_INT int 0 N001 [000065] LCL_VAR V05 loc2 u:2 => $34e {SUB($241, $242)} N002 [000066] CNS_INT 0 => $40 {IntCns 0} N003 [000067] EQ => $351 {EQ($34e, $40)} ***** BB10, STMT00017(after) N004 ( 7, 6) [000068] ------------ * JTRUE void N003 ( 5, 4) [000067] N------N---- \--* EQ int $351 N001 ( 3, 2) [000065] ------------ +--* LCL_VAR int V05 loc2 u:2 $34e N002 ( 1, 1) [000066] ------------ \--* CNS_INT int 0 $40 finish(BB10). Succ(BB11). Not yet completed. All preds complete, adding to allDone. Succ(BB14). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#4) at start of BB11 is $383 {383} The SSA definition for GcHeap (#5) at start of BB11 is $1c6 {1c6} ***** BB11, STMT00083(before) N008 ( 23, 17) [000387] --CXG------- * JTRUE void N007 ( 21, 15) [000386] J-CXG--N---- \--* GE int N004 ( 16, 10) [000385] --CXG------- +--* CAST long <- int N003 ( 15, 8) [000383] --CXG------- | \--* CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent N002 ( 1, 1) [000382] ------------ this in rcx | \--* LCL_VAR ref V01 arg1 u:1 N006 ( 4, 4) [000381] ---------U-- \--* CAST long <- ulong <- uint N005 ( 3, 2) [000380] ------------ \--* LCL_VAR int V05 loc2 u:2 N001 [000569] ARGPLACE => $1c7 {1c7} N002 [000382] LCL_VAR V01 arg1 u:1 => $c0 {InitVal($41)} fgCurMemoryVN[GcHeap] assigned for CALL at [000383] to VN: $1c8. N003 [000383] CALL nullcheck => $291 {291} VNForCastOper(long) is $4b N004 [000385] CAST => $480 {Cast($291, $4b)} N005 [000380] LCL_VAR V05 loc2 u:2 => $34e {SUB($241, $242)} VNForCastOper(ulong, unsignedSrc) is $4c N006 [000381] CAST => $481 {Cast($34e, $4c)} N007 [000386] GE => $352 {GE($480, $481)} ***** BB11, STMT00083(after) N008 ( 23, 17) [000387] --CXG------- * JTRUE void N007 ( 21, 15) [000386] J-CXG--N---- \--* GE int $352 N004 ( 16, 10) [000385] --CXG------- +--* CAST long <- int $480 N003 ( 15, 8) [000383] --CXG------- | \--* CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent $291 N002 ( 1, 1) [000382] ------------ this in rcx | \--* LCL_VAR ref V01 arg1 u:1 $c0 N006 ( 4, 4) [000381] ---------U-- \--* CAST long <- ulong <- uint $481 N005 ( 3, 2) [000380] ------------ \--* LCL_VAR int V05 loc2 u:2 $34e finish(BB11). Succ(BB12). Not yet completed. All preds complete, adding to allDone. Succ(BB13). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#34) at start of BB13 is $384 {384} The SSA definition for GcHeap (#35) at start of BB13 is $1c8 {1c8} ***** BB13, STMT00084(before) N006 ( 20, 12) [000391] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen N004 ( 3, 3) [000389] ------------ arg0 in rcx +--* ADDR long N003 ( 3, 2) [000388] ----G--N---- | \--* LCL_VAR struct(AX)(P) V11 loc8 | \--* ref V11._bits (offs=0x00) -> V54 tmp24 | \--* int V11._sign (offs=0x08) -> V55 tmp25 N005 ( 3, 2) [000390] ------------ arg1 in rdx \--* LCL_VAR int V05 loc2 u:2 (last use) N001 [000571] ARGPLACE => $441 {441} N002 [000572] ARGPLACE => $292 {292} N003 [000388] LCL_VAR V11 loc8 ref V11._bits (offs=0x00) -> V54 tmp24 int V11._sign (offs=0x08) -> V55 tmp25 => $3c3 {3c3} N004 [000389] ADDR => $404 {404} N005 [000390] LCL_VAR V05 loc2 u:2 (last use) => $34e {SUB($241, $242)} VN of ARGPLACE tree [000571] updated to $404 {404} VN of ARGPLACE tree [000572] updated to $34e {SUB($241, $242)} fgCurMemoryVN[GcHeap] assigned for CALL at [000391] to VN: $1c9. N006 [000391] CALL => $VN.Void ***** BB13, STMT00084(after) N006 ( 20, 12) [000391] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen $VN.Void N004 ( 3, 3) [000389] ------------ arg0 in rcx +--* ADDR long $404 N003 ( 3, 2) [000388] ----G--N---- | \--* LCL_VAR struct(AX)(P) V11 loc8 | \--* ref V11._bits (offs=0x00) -> V54 tmp24 | \--* int V11._sign (offs=0x08) -> V55 tmp25 $3c3 N005 ( 3, 2) [000390] ------------ arg1 in rdx \--* LCL_VAR int V05 loc2 u:2 (last use) $34e finish(BB13). Succ(BB14). Not yet completed. All preds complete, adding to allDone. Building phi application: $4d = SSA# 36. Building phi application: $47 = SSA# 4. Building phi application: $302 = phi($47, $4d). The SSA definition for ByrefExposed (#6) at start of BB14 is $303 {PhiMemoryDef($4c0, $302)} Building phi application: $4e = SSA# 37. Building phi application: $4f = SSA# 5. Building phi application: $304 = phi($4f, $4e). The SSA definition for GcHeap (#7) at start of BB14 is $305 {PhiMemoryDef($4c0, $304)} ***** BB14, STMT00019(before) N023 ( 41, 28) [000077] -ACXG---R--- * ASG int N022 ( 1, 1) [000076] D------N---- +--* LCL_VAR int V13 loc10 d:2 N021 ( 41, 28) [000072] -ACXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits N016 ( 18, 15) [000591] -A--G-----L- arg0 SETUP +--* COMMA void N009 ( 10, 8) [000584] -A--G------- | +--* COMMA void N004 ( 3, 3) [000579] -A------R--- | | +--* ASG byref N003 ( 1, 1) [000578] D------N---- | | | +--* LCL_VAR byref V77 tmp47 d:2 N002 ( 3, 3) [000576] ------------ | | | \--* ADDR byref N001 ( 3, 2) [000577] -------N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 N008 ( 7, 5) [000583] -A--G------- | | \--* ASG ref N006 ( 3, 2) [000581] *------N---- | | +--* IND ref N005 ( 1, 1) [000580] ------------ | | | \--* LCL_VAR byref V77 tmp47 u:2 Zero Fseq[_bits] N007 ( 3, 2) [000582] ----G--N---- | | \--* LCL_VAR ref (AX) V54 tmp24 N015 ( 8, 7) [000590] -A--G------- | \--* ASG int N013 ( 4, 4) [000588] *------N---- | +--* IND int N012 ( 2, 2) [000587] -------N---- | | \--* ADD byref N010 ( 1, 1) [000585] ------------ | | +--* LCL_VAR byref V77 tmp47 u:2 (last use) N011 ( 1, 1) [000586] ------------ | | \--* CNS_INT long 8 Fseq[_sign] N014 ( 3, 2) [000589] ----G--N---- | \--* LCL_VAR int (AX) V55 tmp25 N019 ( 3, 3) [000593] ------------ arg0 in rcx +--* ADDR byref N018 ( 3, 2) [000592] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 N020 ( 3, 3) [000071] ------------ arg1 in rdx \--* LCL_VAR_ADDR long V12 loc9 N001 [000577] LCL_VAR V76 tmp46 => $3c4 {3c4} N002 [000576] ADDR => $405 {405} N003 [000578] LCL_VAR V77 tmp47 d:2 => $405 {405} N004 [000579] ASG => $405 {405} N005 [000580] LCL_VAR V77 tmp47 u:2 => $405 {405} N007 [000582] LCL_VAR V54 tmp24 => $181 {ByrefExposedLoad($44, $205, $303)} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [000583] to VN: $1ca. N008 [000583] ASG => $VN.Void N009 [000584] COMMA => $VN.Void N010 [000585] LCL_VAR V77 tmp47 u:2 (last use) => $405 {405} N011 [000586] CNS_INT 8 Fseq[_sign] => $101 {LngCns: 8} N012 [000587] ADD => $206 {ADD($101, $405)} N014 [000589] LCL_VAR V55 tmp25 => $243 {ByrefExposedLoad($45, $207, $386)} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [000590] to VN: $1cb. N015 [000590] ASG => $VN.Void N016 [000591] COMMA => $VN.Void N017 [000594] ARGPLACE => $442 {442} N018 [000592] LCL_VAR V76 tmp46 => $3c5 {3c5} N019 [000593] ADDR => $407 {407} N020 [000071] LCL_VAR_ADDR V12 loc9 => $443 {443} VN of ARGPLACE tree [000594] updated to $443 {443} fgCurMemoryVN[GcHeap] assigned for CALL at [000072] to VN: $1cc. N021 [000072] CALL => $293 {293} N022 [000076] LCL_VAR V13 loc10 d:2 => $293 {293} N023 [000077] ASG => $293 {293} ***** BB14, STMT00019(after) N023 ( 41, 28) [000077] -ACXG---R--- * ASG int $293 N022 ( 1, 1) [000076] D------N---- +--* LCL_VAR int V13 loc10 d:2 $293 N021 ( 41, 28) [000072] -ACXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $293 N016 ( 18, 15) [000591] -A--G-----L- arg0 SETUP +--* COMMA void $VN.Void N009 ( 10, 8) [000584] -A--G------- | +--* COMMA void $VN.Void N004 ( 3, 3) [000579] -A------R--- | | +--* ASG byref $405 N003 ( 1, 1) [000578] D------N---- | | | +--* LCL_VAR byref V77 tmp47 d:2 $405 N002 ( 3, 3) [000576] ------------ | | | \--* ADDR byref $405 N001 ( 3, 2) [000577] -------N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 $3c4 N008 ( 7, 5) [000583] -A--G------- | | \--* ASG ref $VN.Void N006 ( 3, 2) [000581] *------N---- | | +--* IND ref $181 N005 ( 1, 1) [000580] ------------ | | | \--* LCL_VAR byref V77 tmp47 u:2 Zero Fseq[_bits] $405 N007 ( 3, 2) [000582] ----G--N---- | | \--* LCL_VAR ref (AX) V54 tmp24 $181 N015 ( 8, 7) [000590] -A--G------- | \--* ASG int $VN.Void N013 ( 4, 4) [000588] *------N---- | +--* IND int $243 N012 ( 2, 2) [000587] -------N---- | | \--* ADD byref $206 N010 ( 1, 1) [000585] ------------ | | +--* LCL_VAR byref V77 tmp47 u:2 (last use) $405 N011 ( 1, 1) [000586] ------------ | | \--* CNS_INT long 8 Fseq[_sign] $101 N014 ( 3, 2) [000589] ----G--N---- | \--* LCL_VAR int (AX) V55 tmp25 $243 N019 ( 3, 3) [000593] ------------ arg0 in rcx +--* ADDR byref $407 N018 ( 3, 2) [000592] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 $3c5 N020 ( 3, 3) [000071] ------------ arg1 in rdx \--* LCL_VAR_ADDR long V12 loc9 $443 --------- ***** BB14, STMT00020(before) N004 ( 7, 6) [000081] ------------ * JTRUE void N003 ( 5, 4) [000080] N------N-U-- \--* GE int N001 ( 1, 1) [000078] ------------ +--* LCL_VAR int V13 loc10 u:2 N002 ( 3, 2) [000079] ------------ \--* LCL_VAR int V03 loc0 u:2 N001 [000078] LCL_VAR V13 loc10 u:2 => $293 {293} N002 [000079] LCL_VAR V03 loc0 u:2 => $348 {ADD($41, $347)} N003 [000080] GE => $353 {GE_UN($293, $348)} ***** BB14, STMT00020(after) N004 ( 7, 6) [000081] ------------ * JTRUE void N003 ( 5, 4) [000080] N------N-U-- \--* GE int $353 N001 ( 1, 1) [000078] ------------ +--* LCL_VAR int V13 loc10 u:2 $293 N002 ( 3, 2) [000079] ------------ \--* LCL_VAR int V03 loc0 u:2 $348 finish(BB14). Succ(BB15). Not yet completed. All preds complete, adding to allDone. Succ(BB16). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#8) at start of BB15 is $388 {388} The SSA definition for GcHeap (#9) at start of BB15 is $1cc {1cc} ***** BB15, STMT00022(before) N004 ( 5, 5) [000094] ------------ * JTRUE void N003 ( 3, 3) [000093] J------N---- \--* NE int N001 ( 1, 1) [000091] ------------ +--* LCL_VAR int V10 loc7 u:2 N002 ( 1, 1) [000092] ------------ \--* CNS_INT int 0 N001 [000091] LCL_VAR V10 loc7 u:2 => N002 [000092] CNS_INT 0 => $40 {IntCns 0} N003 [000093] NE => ***** BB15, STMT00022(after) N004 ( 5, 5) [000094] ------------ * JTRUE void N003 ( 3, 3) [000093] J------N---- \--* NE int N001 ( 1, 1) [000091] ------------ +--* LCL_VAR int V10 loc7 u:2 N002 ( 1, 1) [000092] ------------ \--* CNS_INT int 0 $40 finish(BB15). Succ(BB16). Not yet completed. All preds complete, adding to allDone. Succ(BB17). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#8) at start of BB17 is $388 {388} The SSA definition for GcHeap (#9) at start of BB17 is $1cc {1cc} ***** BB17, STMT00023(before) N004 ( 5, 5) [000100] ----G------- * JTRUE void N003 ( 3, 3) [000099] J---G--N---- \--* LT int N001 ( 1, 1) [000097] ------------ +--* LCL_VAR int V53 tmp23 u:2 N002 ( 1, 1) [000098] ------------ \--* CNS_INT int 0 N001 [000097] LCL_VAR V53 tmp23 u:2 => N002 [000098] CNS_INT 0 => $40 {IntCns 0} N003 [000099] LT => ***** BB17, STMT00023(after) N004 ( 5, 5) [000100] ----G------- * JTRUE void N003 ( 3, 3) [000099] J---G--N---- \--* LT int N001 ( 1, 1) [000097] ------------ +--* LCL_VAR int V53 tmp23 u:2 N002 ( 1, 1) [000098] ------------ \--* CNS_INT int 0 $40 finish(BB17). Succ(BB18). Not yet completed. All preds complete, adding to allDone. Succ(BB19). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#8) at start of BB19 is $388 {388} The SSA definition for GcHeap (#9) at start of BB19 is $1cc {1cc} ***** BB19, STMT00024(before) N005 ( 7, 6) [000108] -A--G---R--- * ASG int N004 ( 3, 2) [000107] D------N---- +--* LCL_VAR int V32 tmp2 d:3 N003 ( 3, 3) [000106] ----G------- \--* SUB int N001 ( 1, 1) [000101] ------------ +--* LCL_VAR int V10 loc7 u:2 N002 ( 1, 1) [000104] ------------ \--* LCL_VAR int V53 tmp23 u:2 N001 [000101] LCL_VAR V10 loc7 u:2 => N002 [000104] LCL_VAR V53 tmp23 u:2 => N003 [000106] SUB => N004 [000107] LCL_VAR V32 tmp2 d:3 => N005 [000108] ASG => ***** BB19, STMT00024(after) N005 ( 7, 6) [000108] -A--G---R--- * ASG int N004 ( 3, 2) [000107] D------N---- +--* LCL_VAR int V32 tmp2 d:3 N003 ( 3, 3) [000106] ----G------- \--* SUB int N001 ( 1, 1) [000101] ------------ +--* LCL_VAR int V10 loc7 u:2 N002 ( 1, 1) [000104] ------------ \--* LCL_VAR int V53 tmp23 u:2 finish(BB19). Succ(BB20). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#8) at start of BB18 is $388 {388} The SSA definition for GcHeap (#9) at start of BB18 is $1cc {1cc} ***** BB18, STMT00081(before) N003 ( 5, 4) [000378] -A------R--- * ASG int N002 ( 3, 2) [000377] D------N---- +--* LCL_VAR int V32 tmp2 d:4 N001 ( 1, 1) [000376] ------------ \--* LCL_VAR int V10 loc7 u:2 N001 [000376] LCL_VAR V10 loc7 u:2 => N002 [000377] LCL_VAR V32 tmp2 d:4 => N003 [000378] ASG => ***** BB18, STMT00081(after) N003 ( 5, 4) [000378] -A------R--- * ASG int N002 ( 3, 2) [000377] D------N---- +--* LCL_VAR int V32 tmp2 d:4 N001 ( 1, 1) [000376] ------------ \--* LCL_VAR int V10 loc7 u:2 finish(BB18). Succ(BB20). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 32/2 to $244 {PhiDef($20, $2, $34b)} . The SSA definition for ByrefExposed (#8) at start of BB20 is $388 {388} The SSA definition for GcHeap (#9) at start of BB20 is $1cc {1cc} ***** BB20, STMT00025(before) N003 ( 7, 5) [000112] -A------R--- * ASG int N002 ( 3, 2) [000111] D------N---- +--* LCL_VAR int V14 loc11 d:2 N001 ( 3, 2) [000110] ------------ \--* LCL_VAR int V32 tmp2 u:2 (last use) N001 [000110] LCL_VAR V32 tmp2 u:2 (last use) => $244 {PhiDef($20, $2, $34b)} N002 [000111] LCL_VAR V14 loc11 d:2 => $244 {PhiDef($20, $2, $34b)} N003 [000112] ASG => $244 {PhiDef($20, $2, $34b)} ***** BB20, STMT00025(after) N003 ( 7, 5) [000112] -A------R--- * ASG int $244 N002 ( 3, 2) [000111] D------N---- +--* LCL_VAR int V14 loc11 d:2 $244 N001 ( 3, 2) [000110] ------------ \--* LCL_VAR int V32 tmp2 u:2 (last use) $244 --------- ***** BB20, STMT00026(before) N004 ( 5, 5) [000116] ------------ * JTRUE void N003 ( 3, 3) [000115] J------N---- \--* NE int N001 ( 1, 1) [000113] ------------ +--* LCL_VAR int V13 loc10 u:2 N002 ( 1, 1) [000114] ------------ \--* CNS_INT int 0 N001 [000113] LCL_VAR V13 loc10 u:2 => $293 {293} N002 [000114] CNS_INT 0 => $40 {IntCns 0} N003 [000115] NE => $35a {NE($293, $40)} ***** BB20, STMT00026(after) N004 ( 5, 5) [000116] ------------ * JTRUE void N003 ( 3, 3) [000115] J------N---- \--* NE int $35a N001 ( 1, 1) [000113] ------------ +--* LCL_VAR int V13 loc10 u:2 $293 N002 ( 1, 1) [000114] ------------ \--* CNS_INT int 0 $40 finish(BB20). Succ(BB21). Not yet completed. All preds complete, adding to allDone. Succ(BB23). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#8) at start of BB21 is $388 {388} The SSA definition for GcHeap (#9) at start of BB21 is $1cc {1cc} ***** BB21, STMT00077(before) N008 ( 13, 13) [000363] -A-XG---R--- * ASG long N007 ( 3, 2) [000362] D------N---- +--* LCL_VAR long V38 tmp8 d:2 N006 ( 9, 10) [000359] ---XG---R--- \--* SUB long N005 ( 4, 4) [000353] ---------U-- +--* CAST long <- ulong <- uint N004 ( 3, 2) [000352] ------------ | \--* LCL_VAR int V14 loc11 u:2 N003 ( 4, 5) [000358] ---XG------- \--* CAST long <- int N002 ( 3, 3) [000456] ---XG------- \--* ARR_LENGTH int N001 ( 1, 1) [000455] ------------ \--* LCL_VAR ref V52 tmp22 u:2 N001 [000455] LCL_VAR V52 tmp22 u:2 => N002 [000456] ARR_LENGTH => VNForCastOper(long) is $4b N003 [000358] CAST => N004 [000352] LCL_VAR V14 loc11 u:2 => $244 {PhiDef($20, $2, $34b)} VNForCastOper(ulong, unsignedSrc) is $4c N005 [000353] CAST => $486 {Cast($244, $4c)} N006 [000359] SUB => N007 [000362] LCL_VAR V38 tmp8 d:2 => N008 [000363] ASG => ***** BB21, STMT00077(after) N008 ( 13, 13) [000363] -A-XG---R--- * ASG long N007 ( 3, 2) [000362] D------N---- +--* LCL_VAR long V38 tmp8 d:2 N006 ( 9, 10) [000359] ---XG---R--- \--* SUB long N005 ( 4, 4) [000353] ---------U-- +--* CAST long <- ulong <- uint $486 N004 ( 3, 2) [000352] ------------ | \--* LCL_VAR int V14 loc11 u:2 $244 N003 ( 4, 5) [000358] ---XG------- \--* CAST long <- int N002 ( 3, 3) [000456] ---XG------- \--* ARR_LENGTH int N001 ( 1, 1) [000455] ------------ \--* LCL_VAR ref V52 tmp22 u:2 --------- ***** BB21, STMT00078(before) N007 ( 22, 15) [000368] --CXG------- * JTRUE void N006 ( 20, 13) [000367] J-CXG--N---- \--* GE int N004 ( 16, 10) [000366] --CXG------- +--* CAST long <- int N003 ( 15, 8) [000361] --CXG------- | \--* CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent N002 ( 1, 1) [000360] ------------ this in rcx | \--* LCL_VAR ref V01 arg1 u:1 N005 ( 3, 2) [000364] ------------ \--* LCL_VAR long V38 tmp8 u:2 (last use) N001 [000601] ARGPLACE => $1cd {1cd} N002 [000360] LCL_VAR V01 arg1 u:1 => $c0 {InitVal($41)} fgCurMemoryVN[GcHeap] assigned for CALL at [000361] to VN: $1ce. N003 [000361] CALL nullcheck => $298 {298} VNForCastOper(long) is $4b N004 [000366] CAST => $48b {Cast($298, $4b)} N005 [000364] LCL_VAR V38 tmp8 u:2 (last use) => N006 [000367] GE => ***** BB21, STMT00078(after) N007 ( 22, 15) [000368] --CXG------- * JTRUE void N006 ( 20, 13) [000367] J-CXG--N---- \--* GE int N004 ( 16, 10) [000366] --CXG------- +--* CAST long <- int $48b N003 ( 15, 8) [000361] --CXG------- | \--* CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent $298 N002 ( 1, 1) [000360] ------------ this in rcx | \--* LCL_VAR ref V01 arg1 u:1 $c0 N005 ( 3, 2) [000364] ------------ \--* LCL_VAR long V38 tmp8 u:2 (last use) finish(BB21). Succ(BB22). Not yet completed. All preds complete, adding to allDone. Succ(BB23). Not yet completed. All preds complete, adding to allDone. Building phi application: $53 = SSA# 30. Building phi application: $54 = SSA# 8. Building phi application: $306 = phi($54, $53). The SSA definition for ByrefExposed (#12) at start of BB23 is $307 {PhiMemoryDef($4c1, $306)} Building phi application: $55 = SSA# 31. Building phi application: $56 = SSA# 9. Building phi application: $308 = phi($56, $55). The SSA definition for GcHeap (#13) at start of BB23 is $309 {PhiMemoryDef($4c1, $308)} ***** BB23, STMT00028(before) N028 ( 53, 37) [000120] SACXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger N004 ( 7, 6) [000623] -A------R-L- arg0 SETUP +--* ASG long N003 ( 3, 2) [000622] D------N---- | +--* LCL_VAR long V79 tmp49 d:2 N002 ( 3, 3) [000125] ------------ | \--* ADDR long N001 ( 3, 2) [000124] ----G--N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 N020 ( 14, 13) [000621] -A--------L- arg1 SETUP +--* COMMA void N013 ( 8, 7) [000614] -A---------- | +--* COMMA void N008 ( 3, 3) [000609] -A------R--- | | +--* ASG byref N007 ( 1, 1) [000608] D------N---- | | | +--* LCL_VAR byref V78 tmp48 d:2 N006 ( 3, 3) [000606] ------------ | | | \--* ADDR byref N005 ( 3, 2) [000607] ----G--N---- | | | \--* LCL_VAR struct(AX) V73 tmp43 N012 ( 5, 4) [000613] -A---------- | | \--* ASG ref N010 ( 3, 2) [000611] *------N---- | | +--* IND ref N009 ( 1, 1) [000610] ------------ | | | \--* LCL_VAR byref V78 tmp48 u:2 Zero Fseq[Mantissa] N011 ( 1, 1) [000612] -------N---- | | \--* LCL_VAR ref V52 tmp22 u:2 (last use) N019 ( 6, 6) [000620] -A---------- | \--* ASG int N017 ( 4, 4) [000618] *------N---- | +--* IND int N016 ( 2, 2) [000617] -------N---- | | \--* ADD byref N014 ( 1, 1) [000615] ------------ | | +--* LCL_VAR byref V78 tmp48 u:2 (last use) N015 ( 1, 1) [000616] ------------ | | \--* CNS_INT long 8 Fseq[Exponent] N018 ( 1, 1) [000619] -------N---- | \--* LCL_VAR int V53 tmp23 u:2 (last use) N023 ( 3, 2) [000624] ------------ arg0 in rcx +--* LCL_VAR long V79 tmp49 u:2 (last use) N025 ( 3, 3) [000626] ------------ arg1 in rdx +--* ADDR byref N024 ( 3, 2) [000625] -------N---- | \--* LCL_VAR struct(AX) V73 tmp43 N026 ( 3, 2) [000118] ------------ arg2 in r8 +--* LCL_VAR int V08 loc5 u:2 (last use) N027 ( 3, 2) [000119] ------------ arg3 in r9 \--* LCL_VAR int V09 loc6 u:2 (last use) N001 [000124] LCL_VAR V15 loc12 ref V15._bits (offs=0x00) -> V56 tmp26 int V15._sign (offs=0x08) -> V57 tmp27 => $3c6 {3c6} N002 [000125] ADDR => $408 {408} N003 [000622] LCL_VAR V79 tmp49 d:2 => $408 {408} N004 [000623] ASG => $408 {408} N005 [000607] LCL_VAR V73 tmp43 => $3c7 {3c7} N006 [000606] ADDR => $409 {409} N007 [000608] LCL_VAR V78 tmp48 d:2 => $409 {409} N008 [000609] ASG => $409 {409} N009 [000610] LCL_VAR V78 tmp48 u:2 => $409 {409} N011 [000612] LCL_VAR V52 tmp22 u:2 (last use) => fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [000613] to VN: $1cf. N012 [000613] ASG => $VN.Void N013 [000614] COMMA => $VN.Void N014 [000615] LCL_VAR V78 tmp48 u:2 (last use) => $409 {409} N015 [000616] CNS_INT 8 Fseq[Exponent] => $101 {LngCns: 8} N016 [000617] ADD => $209 {ADD($101, $409)} N018 [000619] LCL_VAR V53 tmp23 u:2 (last use) => fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [000620] to VN: $1d0. N019 [000620] ASG => $VN.Void N020 [000621] COMMA => $VN.Void N021 [000627] ARGPLACE => $299 {299} N022 [000628] ARGPLACE => $29a {29a} N023 [000624] LCL_VAR V79 tmp49 u:2 (last use) => $408 {408} N024 [000625] LCL_VAR V73 tmp43 => $3c8 {3c8} N025 [000626] ADDR => $40b {40b} N026 [000118] LCL_VAR V08 loc5 u:2 (last use) => $242 {PhiDef($29, $2, $34b)} N027 [000119] LCL_VAR V09 loc6 u:2 (last use) => VN of ARGPLACE tree [000627] updated to $242 {PhiDef($29, $2, $34b)} VN of ARGPLACE tree [000628] updated to fgCurMemoryVN[GcHeap] assigned for CALL at [000120] to VN: $1d1. N028 [000120] CALL => $VN.Void ***** BB23, STMT00028(after) N028 ( 53, 37) [000120] SACXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger $VN.Void N004 ( 7, 6) [000623] -A------R-L- arg0 SETUP +--* ASG long $408 N003 ( 3, 2) [000622] D------N---- | +--* LCL_VAR long V79 tmp49 d:2 $408 N002 ( 3, 3) [000125] ------------ | \--* ADDR long $408 N001 ( 3, 2) [000124] ----G--N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 $3c6 N020 ( 14, 13) [000621] -A--------L- arg1 SETUP +--* COMMA void $VN.Void N013 ( 8, 7) [000614] -A---------- | +--* COMMA void $VN.Void N008 ( 3, 3) [000609] -A------R--- | | +--* ASG byref $409 N007 ( 1, 1) [000608] D------N---- | | | +--* LCL_VAR byref V78 tmp48 d:2 $409 N006 ( 3, 3) [000606] ------------ | | | \--* ADDR byref $409 N005 ( 3, 2) [000607] ----G--N---- | | | \--* LCL_VAR struct(AX) V73 tmp43 $3c7 N012 ( 5, 4) [000613] -A---------- | | \--* ASG ref $VN.Void N010 ( 3, 2) [000611] *------N---- | | +--* IND ref N009 ( 1, 1) [000610] ------------ | | | \--* LCL_VAR byref V78 tmp48 u:2 Zero Fseq[Mantissa] $409 N011 ( 1, 1) [000612] -------N---- | | \--* LCL_VAR ref V52 tmp22 u:2 (last use) N019 ( 6, 6) [000620] -A---------- | \--* ASG int $VN.Void N017 ( 4, 4) [000618] *------N---- | +--* IND int N016 ( 2, 2) [000617] -------N---- | | \--* ADD byref $209 N014 ( 1, 1) [000615] ------------ | | +--* LCL_VAR byref V78 tmp48 u:2 (last use) $409 N015 ( 1, 1) [000616] ------------ | | \--* CNS_INT long 8 Fseq[Exponent] $101 N018 ( 1, 1) [000619] -------N---- | \--* LCL_VAR int V53 tmp23 u:2 (last use) N023 ( 3, 2) [000624] ------------ arg0 in rcx +--* LCL_VAR long V79 tmp49 u:2 (last use) $408 N025 ( 3, 3) [000626] ------------ arg1 in rdx +--* ADDR byref $40b N024 ( 3, 2) [000625] -------N---- | \--* LCL_VAR struct(AX) V73 tmp43 $3c8 N026 ( 3, 2) [000118] ------------ arg2 in r8 +--* LCL_VAR int V08 loc5 u:2 (last use) $242 N027 ( 3, 2) [000119] ------------ arg3 in r9 \--* LCL_VAR int V09 loc6 u:2 (last use) --------- ***** BB23, STMT00029(before) N005 ( 17, 21) [000133] H-CXG------- * CALL help long HELPER.CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE N003 ( 2, 10) [000131] ------------ arg0 in rcx +--* CNS_INT long 0x7ff815262aa0 N004 ( 1, 4) [000132] ------------ arg1 in rdx \--* CNS_INT int 173 N001 [000629] ARGPLACE => $446 {446} N002 [000630] ARGPLACE => $29b {29b} N003 [000131] CNS_INT 0x7ff815262aa0 => $102 {LngCns: 0x7ff815262aa0} N004 [000132] CNS_INT 173 => $58 {IntCns 173} VN of ARGPLACE tree [000629] updated to $102 {LngCns: 0x7ff815262aa0} VN of ARGPLACE tree [000630] updated to $58 {IntCns 173} N005 [000133] CALL help => $48d {norm=$48c {GetsharedNongcstaticBase($102, $58)}, exc=$30a {HelperMultipleExc()}} ***** BB23, STMT00029(after) N005 ( 17, 21) [000133] H-CXG------- * CALL help long HELPER.CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE $48d N003 ( 2, 10) [000131] ------------ arg0 in rcx +--* CNS_INT long 0x7ff815262aa0 $102 N004 ( 1, 4) [000132] ------------ arg1 in rdx \--* CNS_INT int 173 $58 --------- ***** BB23, STMT00030(before) N018 ( 21, 26) [000649] -A-XG------- * COMMA void N011 ( 13, 19) [000642] -A-XG------- +--* COMMA void N006 ( 6, 14) [000637] -A--G---R--- | +--* ASG byref N005 ( 1, 1) [000636] D------N---- | | +--* LCL_VAR byref V80 tmp50 d:2 N004 ( 6, 14) [000632] ----G------- | | \--* ADD byref N002 ( 4, 12) [000633] n---G------- | | +--* IND ref N001 ( 2, 10) [000634] I----------- | | | \--* CNS_INT(h) long 0xd1ffab1e static Fseq[BigOne] N003 ( 1, 1) [000635] ------------ | | \--* CNS_INT long 8 Fseq[#FirstElem] N010 ( 7, 5) [000641] -A-XG---R--- | \--* ASG ref N009 ( 3, 2) [000638] D---G--N---- | +--* LCL_VAR ref (AX) V58 tmp28 N008 ( 3, 2) [000640] ---X-------- | \--* IND ref N007 ( 1, 1) [000639] ------------ | \--* LCL_VAR byref V80 tmp50 u:2 Zero Fseq[_bits] N017 ( 8, 7) [000648] -A-XG---R--- \--* ASG int N016 ( 3, 2) [000643] D---G--N---- +--* LCL_VAR int (AX) V59 tmp29 N015 ( 4, 4) [000647] ---X-------- \--* IND int N014 ( 2, 2) [000646] -------N---- \--* ADD byref N012 ( 1, 1) [000644] ------------ +--* LCL_VAR byref V80 tmp50 u:2 (last use) N013 ( 1, 1) [000645] ------------ \--* CNS_INT long 8 Fseq[_sign] N001 [000634] CNS_INT(h) 0xd1ffab1e static Fseq[BigOne] => $4c2 {Hnd const: 0x00000000D1FFAB1E} N002 [000633] IND => N003 [000635] CNS_INT 8 Fseq[#FirstElem] => $101 {LngCns: 8} N004 [000632] ADD => N005 [000636] LCL_VAR V80 tmp50 d:2 => N006 [000637] ASG => N007 [000639] LCL_VAR V80 tmp50 u:2 => N008 [000640] IND => fgCurMemoryVN[ByrefExposed] assigned for local assign at [000641] to VN: $38d. N010 [000641] ASG => N011 [000642] COMMA => N012 [000644] LCL_VAR V80 tmp50 u:2 (last use) => N013 [000645] CNS_INT 8 Fseq[_sign] => $101 {LngCns: 8} N014 [000646] ADD => N015 [000647] IND => fgCurMemoryVN[ByrefExposed] assigned for local assign at [000648] to VN: $38e. N017 [000648] ASG => N018 [000649] COMMA => ***** BB23, STMT00030(after) N018 ( 21, 26) [000649] -A-XG------- * COMMA void N011 ( 13, 19) [000642] -A-XG------- +--* COMMA void N006 ( 6, 14) [000637] -A--G---R--- | +--* ASG byref N005 ( 1, 1) [000636] D------N---- | | +--* LCL_VAR byref V80 tmp50 d:2 N004 ( 6, 14) [000632] ----G------- | | \--* ADD byref N002 ( 4, 12) [000633] n---G------- | | +--* IND ref N001 ( 2, 10) [000634] I----------- | | | \--* CNS_INT(h) long 0xd1ffab1e static Fseq[BigOne] $4c2 N003 ( 1, 1) [000635] ------------ | | \--* CNS_INT long 8 Fseq[#FirstElem] $101 N010 ( 7, 5) [000641] -A-XG---R--- | \--* ASG ref N009 ( 3, 2) [000638] D---G--N---- | +--* LCL_VAR ref (AX) V58 tmp28 N008 ( 3, 2) [000640] ---X-------- | \--* IND ref N007 ( 1, 1) [000639] ------------ | \--* LCL_VAR byref V80 tmp50 u:2 Zero Fseq[_bits] N017 ( 8, 7) [000648] -A-XG---R--- \--* ASG int N016 ( 3, 2) [000643] D---G--N---- +--* LCL_VAR int (AX) V59 tmp29 N015 ( 4, 4) [000647] ---X-------- \--* IND int N014 ( 2, 2) [000646] -------N---- \--* ADD byref N012 ( 1, 1) [000644] ------------ +--* LCL_VAR byref V80 tmp50 u:2 (last use) N013 ( 1, 1) [000645] ------------ \--* CNS_INT long 8 Fseq[_sign] $101 --------- ***** BB23, STMT00031(before) N006 ( 20, 12) [000141] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen N004 ( 3, 3) [000139] ------------ arg0 in rcx +--* ADDR long N003 ( 3, 2) [000138] ----G--N---- | \--* LCL_VAR struct(AX)(P) V16 loc13 | \--* ref V16._bits (offs=0x00) -> V58 tmp28 | \--* int V16._sign (offs=0x08) -> V59 tmp29 N005 ( 3, 2) [000140] ------------ arg1 in rdx \--* LCL_VAR int V14 loc11 u:2 (last use) N001 [000650] ARGPLACE => $447 {447} N002 [000651] ARGPLACE => $29d {29d} N003 [000138] LCL_VAR V16 loc13 ref V16._bits (offs=0x00) -> V58 tmp28 int V16._sign (offs=0x08) -> V59 tmp29 => $3c9 {3c9} N004 [000139] ADDR => $40d {40d} N005 [000140] LCL_VAR V14 loc11 u:2 (last use) => $244 {PhiDef($20, $2, $34b)} VN of ARGPLACE tree [000650] updated to $40d {40d} VN of ARGPLACE tree [000651] updated to $244 {PhiDef($20, $2, $34b)} fgCurMemoryVN[GcHeap] assigned for CALL at [000141] to VN: $1d4. N006 [000141] CALL => $VN.Void ***** BB23, STMT00031(after) N006 ( 20, 12) [000141] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen $VN.Void N004 ( 3, 3) [000139] ------------ arg0 in rcx +--* ADDR long $40d N003 ( 3, 2) [000138] ----G--N---- | \--* LCL_VAR struct(AX)(P) V16 loc13 | \--* ref V16._bits (offs=0x00) -> V58 tmp28 | \--* int V16._sign (offs=0x08) -> V59 tmp29 $3c9 N005 ( 3, 2) [000140] ------------ arg1 in rdx \--* LCL_VAR int V14 loc11 u:2 (last use) $244 --------- ***** BB23, STMT00099(before) N007 ( 14, 10) [000658] -A--G------- * COMMA void N003 ( 7, 5) [000654] -A--G---R--- +--* ASG ref N002 ( 3, 2) [000652] D------N---- | +--* LCL_VAR ref V64 tmp34 d:2 N001 ( 3, 2) [000653] ----G--N---- | \--* LCL_VAR ref (AX) V56 tmp26 N006 ( 7, 5) [000657] -A--G---R--- \--* ASG int N005 ( 3, 2) [000655] D------N---- +--* LCL_VAR int V65 tmp35 d:2 N004 ( 3, 2) [000656] ----G--N---- \--* LCL_VAR int (AX) V57 tmp27 N001 [000653] LCL_VAR V56 tmp26 => $184 {ByrefExposedLoad($44, $20f, $38f)} N002 [000652] LCL_VAR V64 tmp34 d:2 => $184 {ByrefExposedLoad($44, $20f, $38f)} N003 [000654] ASG => $184 {ByrefExposedLoad($44, $20f, $38f)} N004 [000656] LCL_VAR V57 tmp27 => $246 {ByrefExposedLoad($45, $210, $38f)} N005 [000655] LCL_VAR V65 tmp35 d:2 => $246 {ByrefExposedLoad($45, $210, $38f)} N006 [000657] ASG => $246 {ByrefExposedLoad($45, $210, $38f)} N007 [000658] COMMA => $246 {ByrefExposedLoad($45, $210, $38f)} ***** BB23, STMT00099(after) N007 ( 14, 10) [000658] -A--G------- * COMMA void $246 N003 ( 7, 5) [000654] -A--G---R--- +--* ASG ref $184 N002 ( 3, 2) [000652] D------N---- | +--* LCL_VAR ref V64 tmp34 d:2 $184 N001 ( 3, 2) [000653] ----G--N---- | \--* LCL_VAR ref (AX) V56 tmp26 $184 N006 ( 7, 5) [000657] -A--G---R--- \--* ASG int $246 N005 ( 3, 2) [000655] D------N---- +--* LCL_VAR int V65 tmp35 d:2 $246 N004 ( 3, 2) [000656] ----G--N---- \--* LCL_VAR int (AX) V57 tmp27 $246 --------- ***** BB23, STMT00098(before) N023 ( 45, 31) [000468] -ACXG---R--- * ASG int N022 ( 3, 2) [000467] D------N---- +--* LCL_VAR int V43 tmp13 d:2 N021 ( 41, 28) [000463] -ACXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits N016 ( 18, 15) [000677] -A--------L- arg0 SETUP +--* COMMA void N009 ( 10, 8) [000670] -A---------- | +--* COMMA void N004 ( 3, 3) [000665] -A------R--- | | +--* ASG byref N003 ( 1, 1) [000664] D------N---- | | | +--* LCL_VAR byref V81 tmp51 d:2 N002 ( 3, 3) [000662] ------------ | | | \--* ADDR byref N001 ( 3, 2) [000663] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 N008 ( 7, 5) [000669] -A---------- | | \--* ASG ref N006 ( 3, 2) [000667] *------N---- | | +--* IND ref N005 ( 1, 1) [000666] ------------ | | | \--* LCL_VAR byref V81 tmp51 u:2 Zero Fseq[_bits] N007 ( 3, 2) [000668] -------N---- | | \--* LCL_VAR ref V64 tmp34 u:2 (last use) N015 ( 8, 7) [000676] -A---------- | \--* ASG int N013 ( 4, 4) [000674] *------N---- | +--* IND int N012 ( 2, 2) [000673] -------N---- | | \--* ADD byref N010 ( 1, 1) [000671] ------------ | | +--* LCL_VAR byref V81 tmp51 u:2 (last use) N011 ( 1, 1) [000672] ------------ | | \--* CNS_INT long 8 Fseq[_sign] N014 ( 3, 2) [000675] -------N---- | \--* LCL_VAR int V65 tmp35 u:2 (last use) N019 ( 3, 3) [000679] ------------ arg0 in rcx +--* ADDR byref N018 ( 3, 2) [000678] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 N020 ( 3, 3) [000462] ------------ arg1 in rdx \--* LCL_VAR_ADDR long V45 tmp15 N001 [000663] LCL_VAR V76 tmp46 => $3ca {3ca} N002 [000662] ADDR => $40e {40e} N003 [000664] LCL_VAR V81 tmp51 d:2 => $40e {40e} N004 [000665] ASG => $40e {40e} N005 [000666] LCL_VAR V81 tmp51 u:2 => $40e {40e} N007 [000668] LCL_VAR V64 tmp34 u:2 (last use) => $184 {ByrefExposedLoad($44, $20f, $38f)} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [000669] to VN: $1d6. N008 [000669] ASG => $VN.Void N009 [000670] COMMA => $VN.Void N010 [000671] LCL_VAR V81 tmp51 u:2 (last use) => $40e {40e} N011 [000672] CNS_INT 8 Fseq[_sign] => $101 {LngCns: 8} N012 [000673] ADD => $211 {ADD($101, $40e)} N014 [000675] LCL_VAR V65 tmp35 u:2 (last use) => $246 {ByrefExposedLoad($45, $210, $38f)} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [000676] to VN: $1d7. N015 [000676] ASG => $VN.Void N016 [000677] COMMA => $VN.Void N017 [000680] ARGPLACE => $448 {448} N018 [000678] LCL_VAR V76 tmp46 => $3cb {3cb} N019 [000679] ADDR => $410 {410} N020 [000462] LCL_VAR_ADDR V45 tmp15 => $449 {449} VN of ARGPLACE tree [000680] updated to $449 {449} fgCurMemoryVN[GcHeap] assigned for CALL at [000463] to VN: $1d8. N021 [000463] CALL => $29f {29f} N022 [000467] LCL_VAR V43 tmp13 d:2 => $29f {29f} N023 [000468] ASG => $29f {29f} ***** BB23, STMT00098(after) N023 ( 45, 31) [000468] -ACXG---R--- * ASG int $29f N022 ( 3, 2) [000467] D------N---- +--* LCL_VAR int V43 tmp13 d:2 $29f N021 ( 41, 28) [000463] -ACXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $29f N016 ( 18, 15) [000677] -A--------L- arg0 SETUP +--* COMMA void $VN.Void N009 ( 10, 8) [000670] -A---------- | +--* COMMA void $VN.Void N004 ( 3, 3) [000665] -A------R--- | | +--* ASG byref $40e N003 ( 1, 1) [000664] D------N---- | | | +--* LCL_VAR byref V81 tmp51 d:2 $40e N002 ( 3, 3) [000662] ------------ | | | \--* ADDR byref $40e N001 ( 3, 2) [000663] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 $3ca N008 ( 7, 5) [000669] -A---------- | | \--* ASG ref $VN.Void N006 ( 3, 2) [000667] *------N---- | | +--* IND ref $184 N005 ( 1, 1) [000666] ------------ | | | \--* LCL_VAR byref V81 tmp51 u:2 Zero Fseq[_bits] $40e N007 ( 3, 2) [000668] -------N---- | | \--* LCL_VAR ref V64 tmp34 u:2 (last use) $184 N015 ( 8, 7) [000676] -A---------- | \--* ASG int $VN.Void N013 ( 4, 4) [000674] *------N---- | +--* IND int $246 N012 ( 2, 2) [000673] -------N---- | | \--* ADD byref $211 N010 ( 1, 1) [000671] ------------ | | +--* LCL_VAR byref V81 tmp51 u:2 (last use) $40e N011 ( 1, 1) [000672] ------------ | | \--* CNS_INT long 8 Fseq[_sign] $101 N014 ( 3, 2) [000675] -------N---- | \--* LCL_VAR int V65 tmp35 u:2 (last use) $246 N019 ( 3, 3) [000679] ------------ arg0 in rcx +--* ADDR byref $410 N018 ( 3, 2) [000678] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 $3cb N020 ( 3, 3) [000462] ------------ arg1 in rdx \--* LCL_VAR_ADDR long V45 tmp15 $449 --------- ***** BB23, STMT00100(before) N003 ( 5, 4) [000475] -A--G---R--- * ASG ref N002 ( 3, 2) [000474] D---G--N---- +--* LCL_VAR ref (AX) V45 tmp15 N001 ( 1, 1) [000473] ------------ \--* CNS_INT ref null N001 [000473] CNS_INT null => $VN.Null fgCurMemoryVN[ByrefExposed] assigned for local assign at [000475] to VN: $393. N003 [000475] ASG => $VN.Null ***** BB23, STMT00100(after) N003 ( 5, 4) [000475] -A--G---R--- * ASG ref $VN.Null N002 ( 3, 2) [000474] D---G--N---- +--* LCL_VAR ref (AX) V45 tmp15 N001 ( 1, 1) [000473] ------------ \--* CNS_INT ref null $VN.Null --------- ***** BB23, STMT00033(before) N003 ( 7, 5) [000148] -A------R--- * ASG int N002 ( 3, 2) [000147] D------N---- +--* LCL_VAR int V17 loc14 d:2 N001 ( 3, 2) [000469] ------------ \--* LCL_VAR int V43 tmp13 u:2 N001 [000469] LCL_VAR V43 tmp13 u:2 => $29f {29f} N002 [000147] LCL_VAR V17 loc14 d:2 => $29f {29f} N003 [000148] ASG => $29f {29f} ***** BB23, STMT00033(after) N003 ( 7, 5) [000148] -A------R--- * ASG int $29f N002 ( 3, 2) [000147] D------N---- +--* LCL_VAR int V17 loc14 d:2 $29f N001 ( 3, 2) [000469] ------------ \--* LCL_VAR int V43 tmp13 u:2 $29f --------- ***** BB23, STMT00103(before) N007 ( 14, 10) [000687] -A--G------- * COMMA void N003 ( 7, 5) [000683] -A--G---R--- +--* ASG ref N002 ( 3, 2) [000681] D------N---- | +--* LCL_VAR ref V66 tmp36 d:2 N001 ( 3, 2) [000682] ----G--N---- | \--* LCL_VAR ref (AX) V58 tmp28 N006 ( 7, 5) [000686] -A--G---R--- \--* ASG int N005 ( 3, 2) [000684] D------N---- +--* LCL_VAR int V67 tmp37 d:2 N004 ( 3, 2) [000685] ----G--N---- \--* LCL_VAR int (AX) V59 tmp29 N001 [000682] LCL_VAR V58 tmp28 => $185 {ByrefExposedLoad($44, $212, $393)} N002 [000681] LCL_VAR V66 tmp36 d:2 => $185 {ByrefExposedLoad($44, $212, $393)} N003 [000683] ASG => $185 {ByrefExposedLoad($44, $212, $393)} N004 [000685] LCL_VAR V59 tmp29 => $247 {ByrefExposedLoad($45, $213, $393)} N005 [000684] LCL_VAR V67 tmp37 d:2 => $247 {ByrefExposedLoad($45, $213, $393)} N006 [000686] ASG => $247 {ByrefExposedLoad($45, $213, $393)} N007 [000687] COMMA => $247 {ByrefExposedLoad($45, $213, $393)} ***** BB23, STMT00103(after) N007 ( 14, 10) [000687] -A--G------- * COMMA void $247 N003 ( 7, 5) [000683] -A--G---R--- +--* ASG ref $185 N002 ( 3, 2) [000681] D------N---- | +--* LCL_VAR ref V66 tmp36 d:2 $185 N001 ( 3, 2) [000682] ----G--N---- | \--* LCL_VAR ref (AX) V58 tmp28 $185 N006 ( 7, 5) [000686] -A--G---R--- \--* ASG int $247 N005 ( 3, 2) [000684] D------N---- +--* LCL_VAR int V67 tmp37 d:2 $247 N004 ( 3, 2) [000685] ----G--N---- \--* LCL_VAR int (AX) V59 tmp29 $247 --------- ***** BB23, STMT00102(before) N023 ( 45, 31) [000486] -ACXG---R--- * ASG int N022 ( 3, 2) [000485] D------N---- +--* LCL_VAR int V46 tmp16 d:2 N021 ( 41, 28) [000481] -ACXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits N016 ( 18, 15) [000706] -A--------L- arg0 SETUP +--* COMMA void N009 ( 10, 8) [000699] -A---------- | +--* COMMA void N004 ( 3, 3) [000694] -A------R--- | | +--* ASG byref N003 ( 1, 1) [000693] D------N---- | | | +--* LCL_VAR byref V82 tmp52 d:2 N002 ( 3, 3) [000691] ------------ | | | \--* ADDR byref N001 ( 3, 2) [000692] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 N008 ( 7, 5) [000698] -A---------- | | \--* ASG ref N006 ( 3, 2) [000696] *------N---- | | +--* IND ref N005 ( 1, 1) [000695] ------------ | | | \--* LCL_VAR byref V82 tmp52 u:2 Zero Fseq[_bits] N007 ( 3, 2) [000697] -------N---- | | \--* LCL_VAR ref V66 tmp36 u:2 (last use) N015 ( 8, 7) [000705] -A---------- | \--* ASG int N013 ( 4, 4) [000703] *------N---- | +--* IND int N012 ( 2, 2) [000702] -------N---- | | \--* ADD byref N010 ( 1, 1) [000700] ------------ | | +--* LCL_VAR byref V82 tmp52 u:2 (last use) N011 ( 1, 1) [000701] ------------ | | \--* CNS_INT long 8 Fseq[_sign] N014 ( 3, 2) [000704] -------N---- | \--* LCL_VAR int V67 tmp37 u:2 (last use) N019 ( 3, 3) [000708] ------------ arg0 in rcx +--* ADDR byref N018 ( 3, 2) [000707] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 N020 ( 3, 3) [000480] ------------ arg1 in rdx \--* LCL_VAR_ADDR long V48 tmp18 N001 [000692] LCL_VAR V76 tmp46 => $3cc {3cc} N002 [000691] ADDR => $411 {411} N003 [000693] LCL_VAR V82 tmp52 d:2 => $411 {411} N004 [000694] ASG => $411 {411} N005 [000695] LCL_VAR V82 tmp52 u:2 => $411 {411} N007 [000697] LCL_VAR V66 tmp36 u:2 (last use) => $185 {ByrefExposedLoad($44, $212, $393)} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [000698] to VN: $1da. N008 [000698] ASG => $VN.Void N009 [000699] COMMA => $VN.Void N010 [000700] LCL_VAR V82 tmp52 u:2 (last use) => $411 {411} N011 [000701] CNS_INT 8 Fseq[_sign] => $101 {LngCns: 8} N012 [000702] ADD => $214 {ADD($101, $411)} N014 [000704] LCL_VAR V67 tmp37 u:2 (last use) => $247 {ByrefExposedLoad($45, $213, $393)} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [000705] to VN: $1db. N015 [000705] ASG => $VN.Void N016 [000706] COMMA => $VN.Void N017 [000709] ARGPLACE => $44a {44a} N018 [000707] LCL_VAR V76 tmp46 => $3cd {3cd} N019 [000708] ADDR => $413 {413} N020 [000480] LCL_VAR_ADDR V48 tmp18 => $44b {44b} VN of ARGPLACE tree [000709] updated to $44b {44b} fgCurMemoryVN[GcHeap] assigned for CALL at [000481] to VN: $1dc. N021 [000481] CALL => $2a3 {2a3} N022 [000485] LCL_VAR V46 tmp16 d:2 => $2a3 {2a3} N023 [000486] ASG => $2a3 {2a3} ***** BB23, STMT00102(after) N023 ( 45, 31) [000486] -ACXG---R--- * ASG int $2a3 N022 ( 3, 2) [000485] D------N---- +--* LCL_VAR int V46 tmp16 d:2 $2a3 N021 ( 41, 28) [000481] -ACXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $2a3 N016 ( 18, 15) [000706] -A--------L- arg0 SETUP +--* COMMA void $VN.Void N009 ( 10, 8) [000699] -A---------- | +--* COMMA void $VN.Void N004 ( 3, 3) [000694] -A------R--- | | +--* ASG byref $411 N003 ( 1, 1) [000693] D------N---- | | | +--* LCL_VAR byref V82 tmp52 d:2 $411 N002 ( 3, 3) [000691] ------------ | | | \--* ADDR byref $411 N001 ( 3, 2) [000692] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 $3cc N008 ( 7, 5) [000698] -A---------- | | \--* ASG ref $VN.Void N006 ( 3, 2) [000696] *------N---- | | +--* IND ref $185 N005 ( 1, 1) [000695] ------------ | | | \--* LCL_VAR byref V82 tmp52 u:2 Zero Fseq[_bits] $411 N007 ( 3, 2) [000697] -------N---- | | \--* LCL_VAR ref V66 tmp36 u:2 (last use) $185 N015 ( 8, 7) [000705] -A---------- | \--* ASG int $VN.Void N013 ( 4, 4) [000703] *------N---- | +--* IND int $247 N012 ( 2, 2) [000702] -------N---- | | \--* ADD byref $214 N010 ( 1, 1) [000700] ------------ | | +--* LCL_VAR byref V82 tmp52 u:2 (last use) $411 N011 ( 1, 1) [000701] ------------ | | \--* CNS_INT long 8 Fseq[_sign] $101 N014 ( 3, 2) [000704] -------N---- | \--* LCL_VAR int V67 tmp37 u:2 (last use) $247 N019 ( 3, 3) [000708] ------------ arg0 in rcx +--* ADDR byref $413 N018 ( 3, 2) [000707] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 $3cd N020 ( 3, 3) [000480] ------------ arg1 in rdx \--* LCL_VAR_ADDR long V48 tmp18 $44b --------- ***** BB23, STMT00104(before) N003 ( 5, 4) [000493] -A--G---R--- * ASG ref N002 ( 3, 2) [000492] D---G--N---- +--* LCL_VAR ref (AX) V48 tmp18 N001 ( 1, 1) [000491] ------------ \--* CNS_INT ref null N001 [000491] CNS_INT null => $VN.Null fgCurMemoryVN[ByrefExposed] assigned for local assign at [000493] to VN: $397. N003 [000493] ASG => $VN.Null ***** BB23, STMT00104(after) N003 ( 5, 4) [000493] -A--G---R--- * ASG ref $VN.Null N002 ( 3, 2) [000492] D---G--N---- +--* LCL_VAR ref (AX) V48 tmp18 N001 ( 1, 1) [000491] ------------ \--* CNS_INT ref null $VN.Null --------- ***** BB23, STMT00035(before) N003 ( 7, 5) [000155] -A------R--- * ASG int N002 ( 3, 2) [000154] D------N---- +--* LCL_VAR int V18 loc15 d:2 N001 ( 3, 2) [000487] ------------ \--* LCL_VAR int V46 tmp16 u:2 N001 [000487] LCL_VAR V46 tmp16 u:2 => $2a3 {2a3} N002 [000154] LCL_VAR V18 loc15 d:2 => $2a3 {2a3} N003 [000155] ASG => $2a3 {2a3} ***** BB23, STMT00035(after) N003 ( 7, 5) [000155] -A------R--- * ASG int $2a3 N002 ( 3, 2) [000154] D------N---- +--* LCL_VAR int V18 loc15 d:2 $2a3 N001 ( 3, 2) [000487] ------------ \--* LCL_VAR int V46 tmp16 u:2 $2a3 --------- ***** BB23, STMT00036(before) N004 ( 9, 7) [000159] ------------ * JTRUE void N003 ( 7, 5) [000158] N------N-U-- \--* GT int N001 ( 3, 2) [000156] ------------ +--* LCL_VAR int V46 tmp16 u:2 (last use) N002 ( 3, 2) [000157] ------------ \--* LCL_VAR int V43 tmp13 u:2 (last use) N001 [000156] LCL_VAR V46 tmp16 u:2 (last use) => $2a3 {2a3} N002 [000157] LCL_VAR V43 tmp13 u:2 (last use) => $29f {29f} N003 [000158] GT => $35f {GT_UN($2a3, $29f)} ***** BB23, STMT00036(after) N004 ( 9, 7) [000159] ------------ * JTRUE void N003 ( 7, 5) [000158] N------N-U-- \--* GT int $35f N001 ( 3, 2) [000156] ------------ +--* LCL_VAR int V46 tmp16 u:2 (last use) $2a3 N002 ( 3, 2) [000157] ------------ \--* LCL_VAR int V43 tmp13 u:2 (last use) $29f finish(BB23). Succ(BB24). Not yet completed. All preds complete, adding to allDone. Succ(BB25). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#14) at start of BB25 is $397 {397} The SSA definition for GcHeap (#15) at start of BB25 is $1dc {1dc} ***** BB25, STMT00037(before) N005 ( 11, 8) [000164] -A------R--- * ASG int N004 ( 3, 2) [000163] D------N---- +--* LCL_VAR int V33 tmp3 d:3 N003 ( 7, 5) [000162] ------------ \--* SUB int N001 ( 3, 2) [000160] ------------ +--* LCL_VAR int V18 loc15 u:2 (last use) N002 ( 3, 2) [000161] ------------ \--* LCL_VAR int V17 loc14 u:2 (last use) N001 [000160] LCL_VAR V18 loc15 u:2 (last use) => $2a3 {2a3} N002 [000161] LCL_VAR V17 loc14 u:2 (last use) => $29f {29f} N003 [000162] SUB => $360 {SUB($2a3, $29f)} N004 [000163] LCL_VAR V33 tmp3 d:3 => $360 {SUB($2a3, $29f)} N005 [000164] ASG => $360 {SUB($2a3, $29f)} ***** BB25, STMT00037(after) N005 ( 11, 8) [000164] -A------R--- * ASG int $360 N004 ( 3, 2) [000163] D------N---- +--* LCL_VAR int V33 tmp3 d:3 $360 N003 ( 7, 5) [000162] ------------ \--* SUB int $360 N001 ( 3, 2) [000160] ------------ +--* LCL_VAR int V18 loc15 u:2 (last use) $2a3 N002 ( 3, 2) [000161] ------------ \--* LCL_VAR int V17 loc14 u:2 (last use) $29f finish(BB25). Succ(BB26). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#14) at start of BB24 is $397 {397} The SSA definition for GcHeap (#15) at start of BB24 is $1dc {1dc} ***** BB24, STMT00074(before) N003 ( 5, 4) [000350] -A------R--- * ASG int N002 ( 3, 2) [000349] D------N---- +--* LCL_VAR int V33 tmp3 d:4 N001 ( 1, 1) [000348] ------------ \--* CNS_INT int 0 N001 [000348] CNS_INT 0 => $40 {IntCns 0} N002 [000349] LCL_VAR V33 tmp3 d:4 => $40 {IntCns 0} N003 [000350] ASG => $40 {IntCns 0} ***** BB24, STMT00074(after) N003 ( 5, 4) [000350] -A------R--- * ASG int $40 N002 ( 3, 2) [000349] D------N---- +--* LCL_VAR int V33 tmp3 d:4 $40 N001 ( 1, 1) [000348] ------------ \--* CNS_INT int 0 $40 finish(BB24). Succ(BB26). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 33/2 to $248 {PhiDef($21, $2, $34b)} . The SSA definition for ByrefExposed (#14) at start of BB26 is $397 {397} The SSA definition for GcHeap (#15) at start of BB26 is $1dc {1dc} ***** BB26, STMT00038(before) N003 ( 3, 3) [000168] -A------R--- * ASG int N002 ( 1, 1) [000167] D------N---- +--* LCL_VAR int V19 loc16 d:2 N001 ( 3, 2) [000166] ------------ \--* LCL_VAR int V33 tmp3 u:2 N001 [000166] LCL_VAR V33 tmp3 u:2 => $248 {PhiDef($21, $2, $34b)} N002 [000167] LCL_VAR V19 loc16 d:2 => $248 {PhiDef($21, $2, $34b)} N003 [000168] ASG => $248 {PhiDef($21, $2, $34b)} ***** BB26, STMT00038(after) N003 ( 3, 3) [000168] -A------R--- * ASG int $248 N002 ( 1, 1) [000167] D------N---- +--* LCL_VAR int V19 loc16 d:2 $248 N001 ( 3, 2) [000166] ------------ \--* LCL_VAR int V33 tmp3 u:2 $248 --------- ***** BB26, STMT00039(before) N004 ( 7, 6) [000172] ------------ * JTRUE void N003 ( 5, 4) [000171] N------N---- \--* EQ int N001 ( 3, 2) [000169] ------------ +--* LCL_VAR int V33 tmp3 u:2 (last use) N002 ( 1, 1) [000170] ------------ \--* CNS_INT int 0 N001 [000169] LCL_VAR V33 tmp3 u:2 (last use) => $248 {PhiDef($21, $2, $34b)} N002 [000170] CNS_INT 0 => $40 {IntCns 0} N003 [000171] EQ => $361 {EQ($248, $40)} ***** BB26, STMT00039(after) N004 ( 7, 6) [000172] ------------ * JTRUE void N003 ( 5, 4) [000171] N------N---- \--* EQ int $361 N001 ( 3, 2) [000169] ------------ +--* LCL_VAR int V33 tmp3 u:2 (last use) $248 N002 ( 1, 1) [000170] ------------ \--* CNS_INT int 0 $40 finish(BB26). Succ(BB27). Not yet completed. All preds complete, adding to allDone. Succ(BB28). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#14) at start of BB27 is $397 {397} The SSA definition for GcHeap (#15) at start of BB27 is $1dc {1dc} ***** BB27, STMT00073(before) N006 ( 18, 11) [000347] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft N004 ( 3, 3) [000345] ------------ arg0 in rcx +--* ADDR long N003 ( 3, 2) [000344] ----G--N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 N005 ( 1, 1) [000346] ------------ arg1 in rdx \--* LCL_VAR int V19 loc16 u:2 N001 [000710] ARGPLACE => $44c {44c} N002 [000711] ARGPLACE => $2a9 {2a9} N003 [000344] LCL_VAR V15 loc12 ref V15._bits (offs=0x00) -> V56 tmp26 int V15._sign (offs=0x08) -> V57 tmp27 => $3ce {3ce} N004 [000345] ADDR => $414 {414} N005 [000346] LCL_VAR V19 loc16 u:2 => $248 {PhiDef($21, $2, $34b)} VN of ARGPLACE tree [000710] updated to $414 {414} VN of ARGPLACE tree [000711] updated to $248 {PhiDef($21, $2, $34b)} fgCurMemoryVN[GcHeap] assigned for CALL at [000347] to VN: $1dd. N006 [000347] CALL => $VN.Void ***** BB27, STMT00073(after) N006 ( 18, 11) [000347] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft $VN.Void N004 ( 3, 3) [000345] ------------ arg0 in rcx +--* ADDR long $414 N003 ( 3, 2) [000344] ----G--N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 $3ce N005 ( 1, 1) [000346] ------------ arg1 in rdx \--* LCL_VAR int V19 loc16 u:2 $248 finish(BB27). Succ(BB28). Not yet completed. All preds complete, adding to allDone. Building phi application: $5e = SSA# 28. Building phi application: $5f = SSA# 14. Building phi application: $30f = phi($5f, $5e). The SSA definition for ByrefExposed (#16) at start of BB28 is $310 {PhiMemoryDef($4c3, $30f)} Building phi application: $60 = SSA# 29. Building phi application: $57 = SSA# 15. Building phi application: $311 = phi($57, $60). The SSA definition for GcHeap (#17) at start of BB28 is $312 {PhiMemoryDef($4c3, $311)} ***** BB28, STMT00040(before) N005 ( 9, 7) [000177] -A------R--- * ASG int N004 ( 3, 2) [000176] D------N---- +--* LCL_VAR int V20 loc17 d:2 N003 ( 5, 4) [000175] ------------ \--* SUB int N001 ( 3, 2) [000173] ------------ +--* LCL_VAR int V03 loc0 u:2 (last use) N002 ( 1, 1) [000174] ------------ \--* LCL_VAR int V13 loc10 u:2 N001 [000173] LCL_VAR V03 loc0 u:2 (last use) => $348 {ADD($41, $347)} N002 [000174] LCL_VAR V13 loc10 u:2 => $293 {293} N003 [000175] SUB => $362 {SUB($348, $293)} N004 [000176] LCL_VAR V20 loc17 d:2 => $362 {SUB($348, $293)} N005 [000177] ASG => $362 {SUB($348, $293)} ***** BB28, STMT00040(after) N005 ( 9, 7) [000177] -A------R--- * ASG int $362 N004 ( 3, 2) [000176] D------N---- +--* LCL_VAR int V20 loc17 d:2 $362 N003 ( 5, 4) [000175] ------------ \--* SUB int $362 N001 ( 3, 2) [000173] ------------ +--* LCL_VAR int V03 loc0 u:2 (last use) $348 N002 ( 1, 1) [000174] ------------ \--* LCL_VAR int V13 loc10 u:2 $293 --------- ***** BB28, STMT00041(before) N003 ( 7, 5) [000180] -A------R--- * ASG int N002 ( 3, 2) [000179] D------N---- +--* LCL_VAR int V21 loc18 d:2 N001 ( 3, 2) [000178] ------------ \--* LCL_VAR int V20 loc17 u:2 N001 [000178] LCL_VAR V20 loc17 u:2 => $362 {SUB($348, $293)} N002 [000179] LCL_VAR V21 loc18 d:2 => $362 {SUB($348, $293)} N003 [000180] ASG => $362 {SUB($348, $293)} ***** BB28, STMT00041(after) N003 ( 7, 5) [000180] -A------R--- * ASG int $362 N002 ( 3, 2) [000179] D------N---- +--* LCL_VAR int V21 loc18 d:2 $362 N001 ( 3, 2) [000178] ------------ \--* LCL_VAR int V20 loc17 u:2 $362 --------- ***** BB28, STMT00042(before) N004 ( 5, 5) [000184] ------------ * JTRUE void N003 ( 3, 3) [000183] N------N---- \--* EQ int N001 ( 1, 1) [000181] ------------ +--* LCL_VAR int V13 loc10 u:2 N002 ( 1, 1) [000182] ------------ \--* CNS_INT int 0 N001 [000181] LCL_VAR V13 loc10 u:2 => $293 {293} N002 [000182] CNS_INT 0 => $40 {IntCns 0} N003 [000183] EQ => $363 {EQ($293, $40)} ***** BB28, STMT00042(after) N004 ( 5, 5) [000184] ------------ * JTRUE void N003 ( 3, 3) [000183] N------N---- \--* EQ int $363 N001 ( 1, 1) [000181] ------------ +--* LCL_VAR int V13 loc10 u:2 $293 N002 ( 1, 1) [000182] ------------ \--* CNS_INT int 0 $40 finish(BB28). Succ(BB29). Not yet completed. All preds complete, adding to allDone. Succ(BB32). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#16) at start of BB29 is $310 {PhiMemoryDef($4c3, $30f)} The SSA definition for GcHeap (#17) at start of BB29 is $312 {PhiMemoryDef($4c3, $311)} ***** BB29, STMT00070(before) N004 ( 7, 6) [000329] ------------ * JTRUE void N003 ( 5, 4) [000328] N------N-U-- \--* LE int N001 ( 1, 1) [000326] ------------ +--* LCL_VAR int V19 loc16 u:2 N002 ( 3, 2) [000327] ------------ \--* LCL_VAR int V21 loc18 u:2 N001 [000326] LCL_VAR V19 loc16 u:2 => $248 {PhiDef($21, $2, $34b)} N002 [000327] LCL_VAR V21 loc18 u:2 => $362 {SUB($348, $293)} N003 [000328] LE => $364 {LE_UN($248, $362)} ***** BB29, STMT00070(after) N004 ( 7, 6) [000329] ------------ * JTRUE void N003 ( 5, 4) [000328] N------N-U-- \--* LE int $364 N001 ( 1, 1) [000326] ------------ +--* LCL_VAR int V19 loc16 u:2 $248 N002 ( 3, 2) [000327] ------------ \--* LCL_VAR int V21 loc18 u:2 $362 finish(BB29). Succ(BB30). Not yet completed. All preds complete, adding to allDone. Succ(BB31). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#16) at start of BB31 is $310 {PhiMemoryDef($4c3, $30f)} The SSA definition for GcHeap (#17) at start of BB31 is $312 {PhiMemoryDef($4c3, $311)} ***** BB31, STMT00071(before) N005 ( 9, 7) [000334] -A------R--- * ASG int N004 ( 3, 2) [000333] D------N---- +--* LCL_VAR int V21 loc18 d:4 N003 ( 5, 4) [000332] ------------ \--* SUB int N001 ( 3, 2) [000330] ------------ +--* LCL_VAR int V21 loc18 u:2 (last use) N002 ( 1, 1) [000331] ------------ \--* LCL_VAR int V19 loc16 u:2 N001 [000330] LCL_VAR V21 loc18 u:2 (last use) => $362 {SUB($348, $293)} N002 [000331] LCL_VAR V19 loc16 u:2 => $248 {PhiDef($21, $2, $34b)} N003 [000332] SUB => $365 {SUB($362, $248)} N004 [000333] LCL_VAR V21 loc18 d:4 => $365 {SUB($362, $248)} N005 [000334] ASG => $365 {SUB($362, $248)} ***** BB31, STMT00071(after) N005 ( 9, 7) [000334] -A------R--- * ASG int $365 N004 ( 3, 2) [000333] D------N---- +--* LCL_VAR int V21 loc18 d:4 $365 N003 ( 5, 4) [000332] ------------ \--* SUB int $365 N001 ( 3, 2) [000330] ------------ +--* LCL_VAR int V21 loc18 u:2 (last use) $362 N002 ( 1, 1) [000331] ------------ \--* LCL_VAR int V19 loc16 u:2 $248 finish(BB31). Succ(BB32). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 21/3 to $249 {PhiDef($15, $3, $366)} . The SSA definition for ByrefExposed (#16) at start of BB32 is $310 {PhiMemoryDef($4c3, $30f)} The SSA definition for GcHeap (#17) at start of BB32 is $312 {PhiMemoryDef($4c3, $311)} ***** BB32, STMT00105(before) N007 ( 14, 10) [000724] -A--G------- * COMMA void N003 ( 7, 5) [000720] -A--G---R--- +--* ASG ref N002 ( 3, 2) [000718] D---G--N---- | +--* LCL_VAR ref (AX) V68 tmp38 N001 ( 3, 2) [000719] ----G--N---- | \--* LCL_VAR ref (AX) V56 tmp26 N006 ( 7, 5) [000723] -A--G---R--- \--* ASG int N005 ( 3, 2) [000721] D---G--N---- +--* LCL_VAR int (AX) V69 tmp39 N004 ( 3, 2) [000722] ----G--N---- \--* LCL_VAR int (AX) V57 tmp27 N001 [000719] LCL_VAR V56 tmp26 => $186 {ByrefExposedLoad($44, $20f, $310)} fgCurMemoryVN[ByrefExposed] assigned for local assign at [000720] to VN: $399. N003 [000720] ASG => $186 {ByrefExposedLoad($44, $20f, $310)} N004 [000722] LCL_VAR V57 tmp27 => $24a {ByrefExposedLoad($45, $210, $399)} fgCurMemoryVN[ByrefExposed] assigned for local assign at [000723] to VN: $39a. N006 [000723] ASG => $24a {ByrefExposedLoad($45, $210, $399)} N007 [000724] COMMA => $24a {ByrefExposedLoad($45, $210, $399)} ***** BB32, STMT00105(after) N007 ( 14, 10) [000724] -A--G------- * COMMA void $24a N003 ( 7, 5) [000720] -A--G---R--- +--* ASG ref $186 N002 ( 3, 2) [000718] D---G--N---- | +--* LCL_VAR ref (AX) V68 tmp38 N001 ( 3, 2) [000719] ----G--N---- | \--* LCL_VAR ref (AX) V56 tmp26 $186 N006 ( 7, 5) [000723] -A--G---R--- \--* ASG int $24a N005 ( 3, 2) [000721] D---G--N---- +--* LCL_VAR int (AX) V69 tmp39 N004 ( 3, 2) [000722] ----G--N---- \--* LCL_VAR int (AX) V57 tmp27 $24a --------- ***** BB32, STMT00106(before) N007 ( 14, 10) [000731] -A--G------- * COMMA void N003 ( 7, 5) [000727] -A--G---R--- +--* ASG ref N002 ( 3, 2) [000725] D------N---- | +--* LCL_VAR ref V70 tmp40 d:2 N001 ( 3, 2) [000726] ----G--N---- | \--* LCL_VAR ref (AX) V58 tmp28 N006 ( 7, 5) [000730] -A--G---R--- \--* ASG int N005 ( 3, 2) [000728] D------N---- +--* LCL_VAR int V71 tmp41 d:2 N004 ( 3, 2) [000729] ----G--N---- \--* LCL_VAR int (AX) V59 tmp29 N001 [000726] LCL_VAR V58 tmp28 => $187 {ByrefExposedLoad($44, $212, $39a)} N002 [000725] LCL_VAR V70 tmp40 d:2 => $187 {ByrefExposedLoad($44, $212, $39a)} N003 [000727] ASG => $187 {ByrefExposedLoad($44, $212, $39a)} N004 [000729] LCL_VAR V59 tmp29 => $24b {ByrefExposedLoad($45, $213, $39a)} N005 [000728] LCL_VAR V71 tmp41 d:2 => $24b {ByrefExposedLoad($45, $213, $39a)} N006 [000730] ASG => $24b {ByrefExposedLoad($45, $213, $39a)} N007 [000731] COMMA => $24b {ByrefExposedLoad($45, $213, $39a)} ***** BB32, STMT00106(after) N007 ( 14, 10) [000731] -A--G------- * COMMA void $24b N003 ( 7, 5) [000727] -A--G---R--- +--* ASG ref $187 N002 ( 3, 2) [000725] D------N---- | +--* LCL_VAR ref V70 tmp40 d:2 $187 N001 ( 3, 2) [000726] ----G--N---- | \--* LCL_VAR ref (AX) V58 tmp28 $187 N006 ( 7, 5) [000730] -A--G---R--- \--* ASG int $24b N005 ( 3, 2) [000728] D------N---- +--* LCL_VAR int V71 tmp41 d:2 $24b N004 ( 3, 2) [000729] ----G--N---- \--* LCL_VAR int (AX) V59 tmp29 $24b --------- ***** BB32, STMT00044(before) N027 ( 52, 38) [000195] -ACXG------- * JTRUE void N026 ( 50, 36) [000503] JACXG--N---- \--* LT int N024 ( 48, 34) [000499] -ACXG------- +--* CALL int System.Numerics.BigInteger.CompareTo N004 ( 7, 6) [000752] -A------R-L- this SETUP | +--* ASG byref N003 ( 3, 2) [000751] D------N---- | | +--* LCL_VAR byref V84 tmp54 d:2 N002 ( 3, 3) [000497] ------------ | | \--* ADDR byref N001 ( 3, 2) [000496] ----G--N---- | | \--* LCL_VAR struct(AX)(P) V49 tmp19 | | \--* ref V49._bits (offs=0x00) -> V68 tmp38 | | \--* int V49._sign (offs=0x08) -> V69 tmp39 N020 ( 18, 15) [000750] -A--------L- arg1 SETUP | +--* COMMA void N013 ( 10, 8) [000743] -A---------- | | +--* COMMA void N008 ( 3, 3) [000738] -A------R--- | | | +--* ASG byref N007 ( 1, 1) [000737] D------N---- | | | | +--* LCL_VAR byref V83 tmp53 d:2 N006 ( 3, 3) [000735] ------------ | | | | \--* ADDR byref N005 ( 3, 2) [000736] ----G--N---- | | | | \--* LCL_VAR struct(AX) V76 tmp46 N012 ( 7, 5) [000742] -A---------- | | | \--* ASG ref N010 ( 3, 2) [000740] *------N---- | | | +--* IND ref N009 ( 1, 1) [000739] ------------ | | | | \--* LCL_VAR byref V83 tmp53 u:2 Zero Fseq[_bits] N011 ( 3, 2) [000741] -------N---- | | | \--* LCL_VAR ref V70 tmp40 u:2 (last use) N019 ( 8, 7) [000749] -A---------- | | \--* ASG int N017 ( 4, 4) [000747] *------N---- | | +--* IND int N016 ( 2, 2) [000746] -------N---- | | | \--* ADD byref N014 ( 1, 1) [000744] ------------ | | | +--* LCL_VAR byref V83 tmp53 u:2 (last use) N015 ( 1, 1) [000745] ------------ | | | \--* CNS_INT long 8 Fseq[_sign] N018 ( 3, 2) [000748] -------N---- | | \--* LCL_VAR int V71 tmp41 u:2 (last use) N021 ( 3, 2) [000753] ------------ this in rcx | +--* LCL_VAR byref V84 tmp54 u:2 (last use) N023 ( 3, 3) [000755] ------------ arg1 in rdx | \--* ADDR byref N022 ( 3, 2) [000754] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 N025 ( 1, 1) [000502] ------------ \--* CNS_INT int 0 N001 [000496] LCL_VAR V49 tmp19 ref V49._bits (offs=0x00) -> V68 tmp38 int V49._sign (offs=0x08) -> V69 tmp39 => $3cf {3cf} N002 [000497] ADDR => $415 {415} N003 [000751] LCL_VAR V84 tmp54 d:2 => $415 {415} N004 [000752] ASG => $415 {415} N005 [000736] LCL_VAR V76 tmp46 => $3d0 {3d0} N006 [000735] ADDR => $417 {417} N007 [000737] LCL_VAR V83 tmp53 d:2 => $417 {417} N008 [000738] ASG => $417 {417} N009 [000739] LCL_VAR V83 tmp53 u:2 => $417 {417} N011 [000741] LCL_VAR V70 tmp40 u:2 (last use) => $187 {ByrefExposedLoad($44, $212, $39a)} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [000742] to VN: $1df. N012 [000742] ASG => $VN.Void N013 [000743] COMMA => $VN.Void N014 [000744] LCL_VAR V83 tmp53 u:2 (last use) => $417 {417} N015 [000745] CNS_INT 8 Fseq[_sign] => $101 {LngCns: 8} N016 [000746] ADD => $216 {ADD($101, $417)} N018 [000748] LCL_VAR V71 tmp41 u:2 (last use) => $24b {ByrefExposedLoad($45, $213, $39a)} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [000749] to VN: $1e0. N019 [000749] ASG => $VN.Void N020 [000750] COMMA => $VN.Void N021 [000753] LCL_VAR V84 tmp54 u:2 (last use) => $415 {415} N022 [000754] LCL_VAR V76 tmp46 => $3d1 {3d1} N023 [000755] ADDR => $419 {419} fgCurMemoryVN[GcHeap] assigned for CALL at [000499] to VN: $1e1. N024 [000499] CALL => $2ae {2ae} N025 [000502] CNS_INT 0 => $40 {IntCns 0} N026 [000503] LT => $367 {LT($2ae, $40)} ***** BB32, STMT00044(after) N027 ( 52, 38) [000195] -ACXG------- * JTRUE void N026 ( 50, 36) [000503] JACXG--N---- \--* LT int $367 N024 ( 48, 34) [000499] -ACXG------- +--* CALL int System.Numerics.BigInteger.CompareTo $2ae N004 ( 7, 6) [000752] -A------R-L- this SETUP | +--* ASG byref $415 N003 ( 3, 2) [000751] D------N---- | | +--* LCL_VAR byref V84 tmp54 d:2 $415 N002 ( 3, 3) [000497] ------------ | | \--* ADDR byref $415 N001 ( 3, 2) [000496] ----G--N---- | | \--* LCL_VAR struct(AX)(P) V49 tmp19 | | \--* ref V49._bits (offs=0x00) -> V68 tmp38 | | \--* int V49._sign (offs=0x08) -> V69 tmp39 $3cf N020 ( 18, 15) [000750] -A--------L- arg1 SETUP | +--* COMMA void $VN.Void N013 ( 10, 8) [000743] -A---------- | | +--* COMMA void $VN.Void N008 ( 3, 3) [000738] -A------R--- | | | +--* ASG byref $417 N007 ( 1, 1) [000737] D------N---- | | | | +--* LCL_VAR byref V83 tmp53 d:2 $417 N006 ( 3, 3) [000735] ------------ | | | | \--* ADDR byref $417 N005 ( 3, 2) [000736] ----G--N---- | | | | \--* LCL_VAR struct(AX) V76 tmp46 $3d0 N012 ( 7, 5) [000742] -A---------- | | | \--* ASG ref $VN.Void N010 ( 3, 2) [000740] *------N---- | | | +--* IND ref $187 N009 ( 1, 1) [000739] ------------ | | | | \--* LCL_VAR byref V83 tmp53 u:2 Zero Fseq[_bits] $417 N011 ( 3, 2) [000741] -------N---- | | | \--* LCL_VAR ref V70 tmp40 u:2 (last use) $187 N019 ( 8, 7) [000749] -A---------- | | \--* ASG int $VN.Void N017 ( 4, 4) [000747] *------N---- | | +--* IND int $24b N016 ( 2, 2) [000746] -------N---- | | | \--* ADD byref $216 N014 ( 1, 1) [000744] ------------ | | | +--* LCL_VAR byref V83 tmp53 u:2 (last use) $417 N015 ( 1, 1) [000745] ------------ | | | \--* CNS_INT long 8 Fseq[_sign] $101 N018 ( 3, 2) [000748] -------N---- | | \--* LCL_VAR int V71 tmp41 u:2 (last use) $24b N021 ( 3, 2) [000753] ------------ this in rcx | +--* LCL_VAR byref V84 tmp54 u:2 (last use) $415 N023 ( 3, 3) [000755] ------------ arg1 in rdx | \--* ADDR byref $419 N022 ( 3, 2) [000754] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 $3d1 N025 ( 1, 1) [000502] ------------ \--* CNS_INT int 0 $40 finish(BB32). Succ(BB33). Not yet completed. All preds complete, adding to allDone. Succ(BB34). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#18) at start of BB34 is $39d {39d} The SSA definition for GcHeap (#19) at start of BB34 is $1e1 {1e1} ***** BB34, STMT00045(before) N005 ( 7, 6) [000200] -A------R--- * ASG int N004 ( 3, 2) [000199] D------N---- +--* LCL_VAR int V34 tmp4 d:3 N003 ( 3, 3) [000198] ------------ \--* ADD int N001 ( 1, 1) [000196] ------------ +--* LCL_VAR int V19 loc16 u:2 (last use) N002 ( 1, 1) [000197] ------------ \--* CNS_INT int 1 N001 [000196] LCL_VAR V19 loc16 u:2 (last use) => $248 {PhiDef($21, $2, $34b)} N002 [000197] CNS_INT 1 => $41 {IntCns 1} N003 [000198] ADD => $368 {ADD($41, $248)} N004 [000199] LCL_VAR V34 tmp4 d:3 => $368 {ADD($41, $248)} N005 [000200] ASG => $368 {ADD($41, $248)} ***** BB34, STMT00045(after) N005 ( 7, 6) [000200] -A------R--- * ASG int $368 N004 ( 3, 2) [000199] D------N---- +--* LCL_VAR int V34 tmp4 d:3 $368 N003 ( 3, 3) [000198] ------------ \--* ADD int $368 N001 ( 1, 1) [000196] ------------ +--* LCL_VAR int V19 loc16 u:2 (last use) $248 N002 ( 1, 1) [000197] ------------ \--* CNS_INT int 1 $41 finish(BB34). Succ(BB35). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#18) at start of BB33 is $39d {39d} The SSA definition for GcHeap (#19) at start of BB33 is $1e1 {1e1} ***** BB33, STMT00069(before) N003 ( 5, 4) [000324] -A------R--- * ASG int N002 ( 3, 2) [000323] D------N---- +--* LCL_VAR int V34 tmp4 d:4 N001 ( 1, 1) [000322] ------------ \--* LCL_VAR int V19 loc16 u:2 (last use) N001 [000322] LCL_VAR V19 loc16 u:2 (last use) => $248 {PhiDef($21, $2, $34b)} N002 [000323] LCL_VAR V34 tmp4 d:4 => $248 {PhiDef($21, $2, $34b)} N003 [000324] ASG => $248 {PhiDef($21, $2, $34b)} ***** BB33, STMT00069(after) N003 ( 5, 4) [000324] -A------R--- * ASG int $248 N002 ( 3, 2) [000323] D------N---- +--* LCL_VAR int V34 tmp4 d:4 $248 N001 ( 1, 1) [000322] ------------ \--* LCL_VAR int V19 loc16 u:2 (last use) $248 finish(BB33). Succ(BB35). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 34/2 to $24c {PhiDef($22, $2, $34b)} . The SSA definition for ByrefExposed (#18) at start of BB35 is $39d {39d} The SSA definition for GcHeap (#19) at start of BB35 is $1e1 {1e1} ***** BB35, STMT00046(before) N003 ( 7, 5) [000204] -A------R--- * ASG int N002 ( 3, 2) [000203] D------N---- +--* LCL_VAR int V22 loc19 d:2 N001 ( 3, 2) [000202] ------------ \--* LCL_VAR int V34 tmp4 u:2 (last use) N001 [000202] LCL_VAR V34 tmp4 u:2 (last use) => $24c {PhiDef($22, $2, $34b)} N002 [000203] LCL_VAR V22 loc19 d:2 => $24c {PhiDef($22, $2, $34b)} N003 [000204] ASG => $24c {PhiDef($22, $2, $34b)} ***** BB35, STMT00046(after) N003 ( 7, 5) [000204] -A------R--- * ASG int $24c N002 ( 3, 2) [000203] D------N---- +--* LCL_VAR int V22 loc19 d:2 $24c N001 ( 3, 2) [000202] ------------ \--* LCL_VAR int V34 tmp4 u:2 (last use) $24c --------- ***** BB35, STMT00047(before) N006 ( 20, 12) [000208] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft N004 ( 3, 3) [000206] ------------ arg0 in rcx +--* ADDR long N003 ( 3, 2) [000205] ----G--N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 N005 ( 3, 2) [000207] ------------ arg1 in rdx \--* LCL_VAR int V21 loc18 u:3 (last use) N001 [000756] ARGPLACE => $44d {44d} N002 [000757] ARGPLACE => $2b2 {2b2} N003 [000205] LCL_VAR V15 loc12 ref V15._bits (offs=0x00) -> V56 tmp26 int V15._sign (offs=0x08) -> V57 tmp27 => $3d2 {3d2} N004 [000206] ADDR => $41a {41a} N005 [000207] LCL_VAR V21 loc18 u:3 (last use) => $249 {PhiDef($15, $3, $366)} VN of ARGPLACE tree [000756] updated to $41a {41a} VN of ARGPLACE tree [000757] updated to $249 {PhiDef($15, $3, $366)} fgCurMemoryVN[GcHeap] assigned for CALL at [000208] to VN: $1e2. N006 [000208] CALL => $VN.Void ***** BB35, STMT00047(after) N006 ( 20, 12) [000208] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft $VN.Void N004 ( 3, 3) [000206] ------------ arg0 in rcx +--* ADDR long $41a N003 ( 3, 2) [000205] ----G--N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 $3d2 N005 ( 3, 2) [000207] ------------ arg1 in rdx \--* LCL_VAR int V21 loc18 u:3 (last use) $249 --------- ***** BB35, STMT00048(before) N045 ( 78, 56) [000213] SACXG------- * CALL void System.Numerics.BigInteger.DivRem N004 ( 7, 6) [000797] -A------R-L- arg0 SETUP +--* ASG long N003 ( 3, 2) [000796] D------N---- | +--* LCL_VAR long V88 tmp58 d:2 N002 ( 3, 3) [000220] ------------ | \--* ADDR long N001 ( 3, 2) [000219] ----G--N---- | \--* LCL_VAR struct(AX)(P) V35 tmp5 | \--* ref V35._bits (offs=0x00) -> V62 tmp32 | \--* int V35._sign (offs=0x08) -> V63 tmp33 N020 ( 18, 15) [000776] -A--G-----L- arg1 SETUP +--* COMMA void N013 ( 10, 8) [000769] -A--G------- | +--* COMMA void N008 ( 3, 3) [000764] -A------R--- | | +--* ASG byref N007 ( 1, 1) [000763] D------N---- | | | +--* LCL_VAR byref V85 tmp55 d:2 N006 ( 3, 3) [000761] ------------ | | | \--* ADDR byref N005 ( 3, 2) [000762] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 N012 ( 7, 5) [000768] -A--G------- | | \--* ASG ref N010 ( 3, 2) [000766] *------N---- | | +--* IND ref N009 ( 1, 1) [000765] ------------ | | | \--* LCL_VAR byref V85 tmp55 u:2 Zero Fseq[_bits] N011 ( 3, 2) [000767] ----G--N---- | | \--* LCL_VAR ref (AX) V56 tmp26 N019 ( 8, 7) [000775] -A--G------- | \--* ASG int N017 ( 4, 4) [000773] *------N---- | +--* IND int N016 ( 2, 2) [000772] -------N---- | | \--* ADD byref N014 ( 1, 1) [000770] ------------ | | +--* LCL_VAR byref V85 tmp55 u:2 (last use) N015 ( 1, 1) [000771] ------------ | | \--* CNS_INT long 8 Fseq[_sign] N018 ( 3, 2) [000774] ----G--N---- | \--* LCL_VAR int (AX) V57 tmp27 N036 ( 18, 15) [000795] -A--G-----L- arg2 SETUP +--* COMMA void N029 ( 10, 8) [000788] -A--G------- | +--* COMMA void N024 ( 3, 3) [000783] -A------R--- | | +--* ASG byref N023 ( 1, 1) [000782] D------N---- | | | +--* LCL_VAR byref V87 tmp57 d:2 N022 ( 3, 3) [000780] ------------ | | | \--* ADDR byref N021 ( 3, 2) [000781] -------N---- | | | \--* LCL_VAR struct(AX) V86 tmp56 N028 ( 7, 5) [000787] -A--G------- | | \--* ASG ref N026 ( 3, 2) [000785] *------N---- | | +--* IND ref N025 ( 1, 1) [000784] ------------ | | | \--* LCL_VAR byref V87 tmp57 u:2 Zero Fseq[_bits] N027 ( 3, 2) [000786] ----G--N---- | | \--* LCL_VAR ref (AX) V58 tmp28 N035 ( 8, 7) [000794] -A--G------- | \--* ASG int N033 ( 4, 4) [000792] *------N---- | +--* IND int N032 ( 2, 2) [000791] -------N---- | | \--* ADD byref N030 ( 1, 1) [000789] ------------ | | +--* LCL_VAR byref V87 tmp57 u:2 (last use) N031 ( 1, 1) [000790] ------------ | | \--* CNS_INT long 8 Fseq[_sign] N034 ( 3, 2) [000793] ----G--N---- | \--* LCL_VAR int (AX) V59 tmp29 N038 ( 3, 2) [000798] ------------ arg0 in rcx +--* LCL_VAR long V88 tmp58 u:2 (last use) N040 ( 3, 3) [000800] ------------ arg1 in rdx +--* ADDR byref N039 ( 3, 2) [000799] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 N042 ( 3, 3) [000802] ------------ arg2 in r8 +--* ADDR byref N041 ( 3, 2) [000801] -------N---- | \--* LCL_VAR struct(AX) V86 tmp56 N044 ( 3, 3) [000212] ------------ arg3 in r9 \--* ADDR long N043 ( 3, 2) [000211] ----G--N---- \--* LCL_VAR struct(AX)(P) V23 loc20 \--* ref V23._bits (offs=0x00) -> V60 tmp30 \--* int V23._sign (offs=0x08) -> V61 tmp31 N001 [000219] LCL_VAR V35 tmp5 ref V35._bits (offs=0x00) -> V62 tmp32 int V35._sign (offs=0x08) -> V63 tmp33 => $3d3 {3d3} N002 [000220] ADDR => $41b {41b} N003 [000796] LCL_VAR V88 tmp58 d:2 => $41b {41b} N004 [000797] ASG => $41b {41b} N005 [000762] LCL_VAR V76 tmp46 => $3d4 {3d4} N006 [000761] ADDR => $41c {41c} N007 [000763] LCL_VAR V85 tmp55 d:2 => $41c {41c} N008 [000764] ASG => $41c {41c} N009 [000765] LCL_VAR V85 tmp55 u:2 => $41c {41c} N011 [000767] LCL_VAR V56 tmp26 => $188 {ByrefExposedLoad($44, $20f, $39e)} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [000768] to VN: $1e3. N012 [000768] ASG => $VN.Void N013 [000769] COMMA => $VN.Void N014 [000770] LCL_VAR V85 tmp55 u:2 (last use) => $41c {41c} N015 [000771] CNS_INT 8 Fseq[_sign] => $101 {LngCns: 8} N016 [000772] ADD => $218 {ADD($101, $41c)} N018 [000774] LCL_VAR V57 tmp27 => $24d {ByrefExposedLoad($45, $210, $39f)} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [000775] to VN: $1e4. N019 [000775] ASG => $VN.Void N020 [000776] COMMA => $VN.Void N021 [000781] LCL_VAR V86 tmp56 => $3d5 {3d5} N022 [000780] ADDR => $41e {41e} N023 [000782] LCL_VAR V87 tmp57 d:2 => $41e {41e} N024 [000783] ASG => $41e {41e} N025 [000784] LCL_VAR V87 tmp57 u:2 => $41e {41e} N027 [000786] LCL_VAR V58 tmp28 => $189 {ByrefExposedLoad($44, $212, $3a0)} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [000787] to VN: $1e5. N028 [000787] ASG => $VN.Void N029 [000788] COMMA => $VN.Void N030 [000789] LCL_VAR V87 tmp57 u:2 (last use) => $41e {41e} N031 [000790] CNS_INT 8 Fseq[_sign] => $101 {LngCns: 8} N032 [000791] ADD => $21a {ADD($101, $41e)} N034 [000793] LCL_VAR V59 tmp29 => $24e {ByrefExposedLoad($45, $213, $3a1)} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [000794] to VN: $1e6. N035 [000794] ASG => $VN.Void N036 [000795] COMMA => $VN.Void N037 [000803] ARGPLACE => $44f {44f} N038 [000798] LCL_VAR V88 tmp58 u:2 (last use) => $41b {41b} N039 [000799] LCL_VAR V76 tmp46 => $3d6 {3d6} N040 [000800] ADDR => $420 {420} N041 [000801] LCL_VAR V86 tmp56 => $3d7 {3d7} N042 [000802] ADDR => $421 {421} N043 [000211] LCL_VAR V23 loc20 ref V23._bits (offs=0x00) -> V60 tmp30 int V23._sign (offs=0x08) -> V61 tmp31 => $3d8 {3d8} N044 [000212] ADDR => $422 {422} VN of ARGPLACE tree [000803] updated to $422 {422} fgCurMemoryVN[GcHeap] assigned for CALL at [000213] to VN: $1e7. N045 [000213] CALL => $VN.Void ***** BB35, STMT00048(after) N045 ( 78, 56) [000213] SACXG------- * CALL void System.Numerics.BigInteger.DivRem $VN.Void N004 ( 7, 6) [000797] -A------R-L- arg0 SETUP +--* ASG long $41b N003 ( 3, 2) [000796] D------N---- | +--* LCL_VAR long V88 tmp58 d:2 $41b N002 ( 3, 3) [000220] ------------ | \--* ADDR long $41b N001 ( 3, 2) [000219] ----G--N---- | \--* LCL_VAR struct(AX)(P) V35 tmp5 | \--* ref V35._bits (offs=0x00) -> V62 tmp32 | \--* int V35._sign (offs=0x08) -> V63 tmp33 $3d3 N020 ( 18, 15) [000776] -A--G-----L- arg1 SETUP +--* COMMA void $VN.Void N013 ( 10, 8) [000769] -A--G------- | +--* COMMA void $VN.Void N008 ( 3, 3) [000764] -A------R--- | | +--* ASG byref $41c N007 ( 1, 1) [000763] D------N---- | | | +--* LCL_VAR byref V85 tmp55 d:2 $41c N006 ( 3, 3) [000761] ------------ | | | \--* ADDR byref $41c N005 ( 3, 2) [000762] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 $3d4 N012 ( 7, 5) [000768] -A--G------- | | \--* ASG ref $VN.Void N010 ( 3, 2) [000766] *------N---- | | +--* IND ref $188 N009 ( 1, 1) [000765] ------------ | | | \--* LCL_VAR byref V85 tmp55 u:2 Zero Fseq[_bits] $41c N011 ( 3, 2) [000767] ----G--N---- | | \--* LCL_VAR ref (AX) V56 tmp26 $188 N019 ( 8, 7) [000775] -A--G------- | \--* ASG int $VN.Void N017 ( 4, 4) [000773] *------N---- | +--* IND int $24d N016 ( 2, 2) [000772] -------N---- | | \--* ADD byref $218 N014 ( 1, 1) [000770] ------------ | | +--* LCL_VAR byref V85 tmp55 u:2 (last use) $41c N015 ( 1, 1) [000771] ------------ | | \--* CNS_INT long 8 Fseq[_sign] $101 N018 ( 3, 2) [000774] ----G--N---- | \--* LCL_VAR int (AX) V57 tmp27 $24d N036 ( 18, 15) [000795] -A--G-----L- arg2 SETUP +--* COMMA void $VN.Void N029 ( 10, 8) [000788] -A--G------- | +--* COMMA void $VN.Void N024 ( 3, 3) [000783] -A------R--- | | +--* ASG byref $41e N023 ( 1, 1) [000782] D------N---- | | | +--* LCL_VAR byref V87 tmp57 d:2 $41e N022 ( 3, 3) [000780] ------------ | | | \--* ADDR byref $41e N021 ( 3, 2) [000781] -------N---- | | | \--* LCL_VAR struct(AX) V86 tmp56 $3d5 N028 ( 7, 5) [000787] -A--G------- | | \--* ASG ref $VN.Void N026 ( 3, 2) [000785] *------N---- | | +--* IND ref $189 N025 ( 1, 1) [000784] ------------ | | | \--* LCL_VAR byref V87 tmp57 u:2 Zero Fseq[_bits] $41e N027 ( 3, 2) [000786] ----G--N---- | | \--* LCL_VAR ref (AX) V58 tmp28 $189 N035 ( 8, 7) [000794] -A--G------- | \--* ASG int $VN.Void N033 ( 4, 4) [000792] *------N---- | +--* IND int $24e N032 ( 2, 2) [000791] -------N---- | | \--* ADD byref $21a N030 ( 1, 1) [000789] ------------ | | +--* LCL_VAR byref V87 tmp57 u:2 (last use) $41e N031 ( 1, 1) [000790] ------------ | | \--* CNS_INT long 8 Fseq[_sign] $101 N034 ( 3, 2) [000793] ----G--N---- | \--* LCL_VAR int (AX) V59 tmp29 $24e N038 ( 3, 2) [000798] ------------ arg0 in rcx +--* LCL_VAR long V88 tmp58 u:2 (last use) $41b N040 ( 3, 3) [000800] ------------ arg1 in rdx +--* ADDR byref $420 N039 ( 3, 2) [000799] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 $3d6 N042 ( 3, 3) [000802] ------------ arg2 in r8 +--* ADDR byref $421 N041 ( 3, 2) [000801] -------N---- | \--* LCL_VAR struct(AX) V86 tmp56 $3d7 N044 ( 3, 3) [000212] ------------ arg3 in r9 \--* ADDR long $422 N043 ( 3, 2) [000211] ----G--N---- \--* LCL_VAR struct(AX)(P) V23 loc20 \--* ref V23._bits (offs=0x00) -> V60 tmp30 \--* int V23._sign (offs=0x08) -> V61 tmp31 $3d8 --------- ***** BB35, STMT00050(before) N021 ( 38, 24) [000226] -ACXG---R--- * ASG long N020 ( 1, 1) [000225] D------N---- +--* LCL_VAR long V24 loc21 d:2 N019 ( 38, 24) [000218] -ACXG------- \--* CALL long System.Numerics.BigInteger.op_Explicit N016 ( 18, 15) [000822] -A--G-----L- arg0 SETUP +--* COMMA void N009 ( 10, 8) [000815] -A--G------- | +--* COMMA void N004 ( 3, 3) [000810] -A------R--- | | +--* ASG byref N003 ( 1, 1) [000809] D------N---- | | | +--* LCL_VAR byref V89 tmp59 d:2 N002 ( 3, 3) [000807] ------------ | | | \--* ADDR byref N001 ( 3, 2) [000808] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 N008 ( 7, 5) [000814] -A--G------- | | \--* ASG ref N006 ( 3, 2) [000812] *------N---- | | +--* IND ref N005 ( 1, 1) [000811] ------------ | | | \--* LCL_VAR byref V89 tmp59 u:2 Zero Fseq[_bits] N007 ( 3, 2) [000813] ----G--N---- | | \--* LCL_VAR ref (AX) V62 tmp32 N015 ( 8, 7) [000821] -A--G------- | \--* ASG int N013 ( 4, 4) [000819] *------N---- | +--* IND int N012 ( 2, 2) [000818] -------N---- | | \--* ADD byref N010 ( 1, 1) [000816] ------------ | | +--* LCL_VAR byref V89 tmp59 u:2 (last use) N011 ( 1, 1) [000817] ------------ | | \--* CNS_INT long 8 Fseq[_sign] N014 ( 3, 2) [000820] ----G--N---- | \--* LCL_VAR int (AX) V63 tmp33 N018 ( 3, 3) [000824] ------------ arg0 in rcx \--* ADDR byref N017 ( 3, 2) [000823] -------N---- \--* LCL_VAR struct(AX) V76 tmp46 N001 [000808] LCL_VAR V76 tmp46 => $3d9 {3d9} N002 [000807] ADDR => $423 {423} N003 [000809] LCL_VAR V89 tmp59 d:2 => $423 {423} N004 [000810] ASG => $423 {423} N005 [000811] LCL_VAR V89 tmp59 u:2 => $423 {423} N007 [000813] LCL_VAR V62 tmp32 => $18a {ByrefExposedLoad($44, $21c, $3a3)} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [000814] to VN: $1e8. N008 [000814] ASG => $VN.Void N009 [000815] COMMA => $VN.Void N010 [000816] LCL_VAR V89 tmp59 u:2 (last use) => $423 {423} N011 [000817] CNS_INT 8 Fseq[_sign] => $101 {LngCns: 8} N012 [000818] ADD => $21d {ADD($101, $423)} N014 [000820] LCL_VAR V63 tmp33 => $24f {ByrefExposedLoad($45, $21e, $3a4)} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [000821] to VN: $1e9. N015 [000821] ASG => $VN.Void N016 [000822] COMMA => $VN.Void N017 [000823] LCL_VAR V76 tmp46 => $3da {3da} N018 [000824] ADDR => $425 {425} fgCurMemoryVN[GcHeap] assigned for CALL at [000218] to VN: $1ea. N019 [000218] CALL => $450 {450} N020 [000225] LCL_VAR V24 loc21 d:2 => $450 {450} N021 [000226] ASG => $450 {450} ***** BB35, STMT00050(after) N021 ( 38, 24) [000226] -ACXG---R--- * ASG long $450 N020 ( 1, 1) [000225] D------N---- +--* LCL_VAR long V24 loc21 d:2 $450 N019 ( 38, 24) [000218] -ACXG------- \--* CALL long System.Numerics.BigInteger.op_Explicit $450 N016 ( 18, 15) [000822] -A--G-----L- arg0 SETUP +--* COMMA void $VN.Void N009 ( 10, 8) [000815] -A--G------- | +--* COMMA void $VN.Void N004 ( 3, 3) [000810] -A------R--- | | +--* ASG byref $423 N003 ( 1, 1) [000809] D------N---- | | | +--* LCL_VAR byref V89 tmp59 d:2 $423 N002 ( 3, 3) [000807] ------------ | | | \--* ADDR byref $423 N001 ( 3, 2) [000808] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 $3d9 N008 ( 7, 5) [000814] -A--G------- | | \--* ASG ref $VN.Void N006 ( 3, 2) [000812] *------N---- | | +--* IND ref $18a N005 ( 1, 1) [000811] ------------ | | | \--* LCL_VAR byref V89 tmp59 u:2 Zero Fseq[_bits] $423 N007 ( 3, 2) [000813] ----G--N---- | | \--* LCL_VAR ref (AX) V62 tmp32 $18a N015 ( 8, 7) [000821] -A--G------- | \--* ASG int $VN.Void N013 ( 4, 4) [000819] *------N---- | +--* IND int $24f N012 ( 2, 2) [000818] -------N---- | | \--* ADD byref $21d N010 ( 1, 1) [000816] ------------ | | +--* LCL_VAR byref V89 tmp59 u:2 (last use) $423 N011 ( 1, 1) [000817] ------------ | | \--* CNS_INT long 8 Fseq[_sign] $101 N014 ( 3, 2) [000820] ----G--N---- | \--* LCL_VAR int (AX) V63 tmp33 $24f N018 ( 3, 3) [000824] ------------ arg0 in rcx \--* ADDR byref $425 N017 ( 3, 2) [000823] -------N---- \--* LCL_VAR struct(AX) V76 tmp46 $3da --------- ***** BB35, STMT00052(before) N005 ( 12, 7) [000232] -A--G---R--- * ASG int N004 ( 3, 2) [000231] D------N---- +--* LCL_VAR int V25 loc22 d:2 N003 ( 8, 4) [000516] ----G------- \--* EQ int N001 ( 3, 2) [000514] ----G------- +--* LCL_VAR int (AX) V61 tmp31 N002 ( 1, 1) [000515] ------------ \--* CNS_INT int 0 N001 [000514] LCL_VAR V61 tmp31 => $250 {ByrefExposedLoad($45, $21f, $3a6)} N002 [000515] CNS_INT 0 => $40 {IntCns 0} N003 [000516] EQ => $369 {EQ($250, $40)} N004 [000231] LCL_VAR V25 loc22 d:2 => $369 {EQ($250, $40)} N005 [000232] ASG => $369 {EQ($250, $40)} ***** BB35, STMT00052(after) N005 ( 12, 7) [000232] -A--G---R--- * ASG int $369 N004 ( 3, 2) [000231] D------N---- +--* LCL_VAR int V25 loc22 d:2 $369 N003 ( 8, 4) [000516] ----G------- \--* EQ int $369 N001 ( 3, 2) [000514] ----G------- +--* LCL_VAR int (AX) V61 tmp31 $250 N002 ( 1, 1) [000515] ------------ \--* CNS_INT int 0 $40 --------- ***** BB35, STMT00054(before) N005 ( 19, 10) [000237] -ACXG---R--- * ASG int N004 ( 3, 2) [000236] D------N---- +--* LCL_VAR int V26 loc23 d:2 N003 ( 15, 7) [000234] --CXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits N002 ( 1, 1) [000233] ------------ arg0 in rcx \--* LCL_VAR long V24 loc21 u:2 N001 [000825] ARGPLACE => $452 {452} N002 [000233] LCL_VAR V24 loc21 u:2 => $450 {450} VN of ARGPLACE tree [000825] updated to $450 {450} fgCurMemoryVN[GcHeap] assigned for CALL at [000234] to VN: $1eb. N003 [000234] CALL => $2b4 {2b4} N004 [000236] LCL_VAR V26 loc23 d:2 => $2b4 {2b4} N005 [000237] ASG => $2b4 {2b4} ***** BB35, STMT00054(after) N005 ( 19, 10) [000237] -ACXG---R--- * ASG int $2b4 N004 ( 3, 2) [000236] D------N---- +--* LCL_VAR int V26 loc23 d:2 $2b4 N003 ( 15, 7) [000234] --CXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $2b4 N002 ( 1, 1) [000233] ------------ arg0 in rcx \--* LCL_VAR long V24 loc21 u:2 $450 --------- ***** BB35, STMT00055(before) N004 ( 9, 7) [000241] ------------ * JTRUE void N003 ( 7, 5) [000240] N------N-U-- \--* LE int N001 ( 3, 2) [000238] ------------ +--* LCL_VAR int V26 loc23 u:2 N002 ( 3, 2) [000239] ------------ \--* LCL_VAR int V20 loc17 u:2 N001 [000238] LCL_VAR V26 loc23 u:2 => $2b4 {2b4} N002 [000239] LCL_VAR V20 loc17 u:2 => $362 {SUB($348, $293)} N003 [000240] LE => $36a {LE_UN($2b4, $362)} ***** BB35, STMT00055(after) N004 ( 9, 7) [000241] ------------ * JTRUE void N003 ( 7, 5) [000240] N------N-U-- \--* LE int $36a N001 ( 3, 2) [000238] ------------ +--* LCL_VAR int V26 loc23 u:2 $2b4 N002 ( 3, 2) [000239] ------------ \--* LCL_VAR int V20 loc17 u:2 $362 finish(BB35). Succ(BB36). Not yet completed. All preds complete, adding to allDone. Succ(BB40). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#20) at start of BB36 is $3a7 {3a7} The SSA definition for GcHeap (#21) at start of BB36 is $1eb {1eb} ***** BB36, STMT00063(before) N005 ( 11, 8) [000286] -A------R--- * ASG int N004 ( 3, 2) [000285] D------N---- +--* LCL_VAR int V29 loc26 d:2 N003 ( 7, 5) [000284] ------------ \--* SUB int N001 ( 3, 2) [000282] ------------ +--* LCL_VAR int V26 loc23 u:2 (last use) N002 ( 3, 2) [000283] ------------ \--* LCL_VAR int V20 loc17 u:2 N001 [000282] LCL_VAR V26 loc23 u:2 (last use) => $2b4 {2b4} N002 [000283] LCL_VAR V20 loc17 u:2 => $362 {SUB($348, $293)} N003 [000284] SUB => $36b {SUB($2b4, $362)} N004 [000285] LCL_VAR V29 loc26 d:2 => $36b {SUB($2b4, $362)} N005 [000286] ASG => $36b {SUB($2b4, $362)} ***** BB36, STMT00063(after) N005 ( 11, 8) [000286] -A------R--- * ASG int $36b N004 ( 3, 2) [000285] D------N---- +--* LCL_VAR int V29 loc26 d:2 $36b N003 ( 7, 5) [000284] ------------ \--* SUB int $36b N001 ( 3, 2) [000282] ------------ +--* LCL_VAR int V26 loc23 u:2 (last use) $2b4 N002 ( 3, 2) [000283] ------------ \--* LCL_VAR int V20 loc17 u:2 $362 --------- ***** BB36, STMT00064(before) N004 ( 7, 6) [000290] ------------ * JTRUE void N003 ( 5, 4) [000289] J------N---- \--* EQ int N001 ( 3, 2) [000287] ------------ +--* LCL_VAR int V25 loc22 u:2 (last use) N002 ( 1, 1) [000288] ------------ \--* CNS_INT int 0 N001 [000287] LCL_VAR V25 loc22 u:2 (last use) => $369 {EQ($250, $40)} N002 [000288] CNS_INT 0 => $40 {IntCns 0} N003 [000289] EQ => $36c {EQ($369, $40)} ***** BB36, STMT00064(after) N004 ( 7, 6) [000290] ------------ * JTRUE void N003 ( 5, 4) [000289] J------N---- \--* EQ int $36c N001 ( 3, 2) [000287] ------------ +--* LCL_VAR int V25 loc22 u:2 (last use) $369 N002 ( 1, 1) [000288] ------------ \--* CNS_INT int 0 $40 finish(BB36). Succ(BB37). Not yet completed. All preds complete, adding to allDone. Succ(BB38). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#20) at start of BB38 is $3a7 {3a7} The SSA definition for GcHeap (#21) at start of BB38 is $1eb {1eb} ***** BB38, STMT00065(before) N003 ( 5, 4) [000293] -A------R--- * ASG int N002 ( 3, 2) [000292] D------N---- +--* LCL_VAR int V37 tmp7 d:3 N001 ( 1, 1) [000291] ------------ \--* CNS_INT int 0 N001 [000291] CNS_INT 0 => $40 {IntCns 0} N002 [000292] LCL_VAR V37 tmp7 d:3 => $40 {IntCns 0} N003 [000293] ASG => $40 {IntCns 0} ***** BB38, STMT00065(after) N003 ( 5, 4) [000293] -A------R--- * ASG int $40 N002 ( 3, 2) [000292] D------N---- +--* LCL_VAR int V37 tmp7 d:3 $40 N001 ( 1, 1) [000291] ------------ \--* CNS_INT int 0 $40 finish(BB38). Succ(BB39). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#20) at start of BB37 is $3a7 {3a7} The SSA definition for GcHeap (#21) at start of BB37 is $1eb {1eb} ***** BB37, STMT00068(before) N013 ( 23, 15) [000320] -A------R--- * ASG int N012 ( 3, 2) [000319] D------N---- +--* LCL_VAR int V37 tmp7 d:4 N011 ( 19, 12) [000318] ------------ \--* EQ int N009 ( 14, 10) [000315] ------------ +--* AND long N001 ( 1, 1) [000305] ------------ | +--* LCL_VAR long V24 loc21 u:2 N008 ( 12, 8) [000314] ------------ | \--* ADD long N006 ( 10, 6) [000311] --------R--- | +--* LSH long N005 ( 1, 1) [000307] ------------ | | +--* CNS_INT long 1 N004 ( 5, 4) [000310] ------------ | | \--* AND int N002 ( 3, 2) [000308] ------------ | | +--* LCL_VAR int V29 loc26 u:2 N003 ( 1, 1) [000309] ------------ | | \--* CNS_INT int 63 N007 ( 1, 1) [000313] ------------ | \--* CNS_INT long -1 N010 ( 1, 1) [000317] ------------ \--* CNS_INT long 0 N001 [000305] LCL_VAR V24 loc21 u:2 => $450 {450} N002 [000308] LCL_VAR V29 loc26 u:2 => $36b {SUB($2b4, $362)} N003 [000309] CNS_INT 63 => $66 {IntCns 63} N004 [000310] AND => $36d {AND($66, $36b)} N005 [000307] CNS_INT 1 => $103 {LngCns: 1} N006 [000311] LSH => $48e {LSH($103, $36d)} N007 [000313] CNS_INT -1 => $104 {LngCns: -1} N008 [000314] ADD => $48f {ADD($104, $48e)} N009 [000315] AND => $490 {AND($450, $48f)} N010 [000317] CNS_INT 0 => $100 {LngCns: 0} N011 [000318] EQ => $36e {EQ($490, $100)} N012 [000319] LCL_VAR V37 tmp7 d:4 => $36e {EQ($490, $100)} N013 [000320] ASG => $36e {EQ($490, $100)} ***** BB37, STMT00068(after) N013 ( 23, 15) [000320] -A------R--- * ASG int $36e N012 ( 3, 2) [000319] D------N---- +--* LCL_VAR int V37 tmp7 d:4 $36e N011 ( 19, 12) [000318] ------------ \--* EQ int $36e N009 ( 14, 10) [000315] ------------ +--* AND long $490 N001 ( 1, 1) [000305] ------------ | +--* LCL_VAR long V24 loc21 u:2 $450 N008 ( 12, 8) [000314] ------------ | \--* ADD long $48f N006 ( 10, 6) [000311] --------R--- | +--* LSH long $48e N005 ( 1, 1) [000307] ------------ | | +--* CNS_INT long 1 $103 N004 ( 5, 4) [000310] ------------ | | \--* AND int $36d N002 ( 3, 2) [000308] ------------ | | +--* LCL_VAR int V29 loc26 u:2 $36b N003 ( 1, 1) [000309] ------------ | | \--* CNS_INT int 63 $66 N007 ( 1, 1) [000313] ------------ | \--* CNS_INT long -1 $104 N010 ( 1, 1) [000317] ------------ \--* CNS_INT long 0 $100 finish(BB37). Succ(BB39). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 37/2 to $251 {PhiDef($25, $2, $34b)} . The SSA definition for ByrefExposed (#20) at start of BB39 is $3a7 {3a7} The SSA definition for GcHeap (#21) at start of BB39 is $1eb {1eb} ***** BB39, STMT00066(before) N004 ( 8, 7) [000297] -A------R--- * ASG int N003 ( 3, 2) [000296] D------N---- +--* LCL_VAR int V25 loc22 d:4 N002 ( 4, 4) [000826] ------------ \--* CAST int <- bool <- int N001 ( 3, 2) [000295] ------------ \--* LCL_VAR int V37 tmp7 u:2 (last use) N001 [000295] LCL_VAR V37 tmp7 u:2 (last use) => $251 {PhiDef($25, $2, $34b)} VNForCastOper(bool) is $47 N002 [000826] CAST => $36f {Cast($251, $47)} N003 [000296] LCL_VAR V25 loc22 d:4 => $36f {Cast($251, $47)} N004 [000297] ASG => $36f {Cast($251, $47)} ***** BB39, STMT00066(after) N004 ( 8, 7) [000297] -A------R--- * ASG int $36f N003 ( 3, 2) [000296] D------N---- +--* LCL_VAR int V25 loc22 d:4 $36f N002 ( 4, 4) [000826] ------------ \--* CAST int <- bool <- int $36f N001 ( 3, 2) [000295] ------------ \--* LCL_VAR int V37 tmp7 u:2 (last use) $251 --------- ***** BB39, STMT00067(before) N007 ( 10, 6) [000304] -A------R--- * ASG long N006 ( 1, 1) [000303] D------N---- +--* LCL_VAR long V24 loc21 d:4 N005 ( 10, 6) [000302] ------------ \--* RSZ long N001 ( 1, 1) [000298] ------------ +--* LCL_VAR long V24 loc21 u:2 (last use) N004 ( 5, 4) [000301] ------------ \--* AND int N002 ( 3, 2) [000299] ------------ +--* LCL_VAR int V29 loc26 u:2 (last use) N003 ( 1, 1) [000300] ------------ \--* CNS_INT int 63 N001 [000298] LCL_VAR V24 loc21 u:2 (last use) => $450 {450} N002 [000299] LCL_VAR V29 loc26 u:2 (last use) => $36b {SUB($2b4, $362)} N003 [000300] CNS_INT 63 => $66 {IntCns 63} N004 [000301] AND => $36d {AND($66, $36b)} N005 [000302] RSZ => $491 {RSZ($450, $36d)} N006 [000303] LCL_VAR V24 loc21 d:4 => $491 {RSZ($450, $36d)} N007 [000304] ASG => $491 {RSZ($450, $36d)} ***** BB39, STMT00067(after) N007 ( 10, 6) [000304] -A------R--- * ASG long $491 N006 ( 1, 1) [000303] D------N---- +--* LCL_VAR long V24 loc21 d:4 $491 N005 ( 10, 6) [000302] ------------ \--* RSZ long $491 N001 ( 1, 1) [000298] ------------ +--* LCL_VAR long V24 loc21 u:2 (last use) $450 N004 ( 5, 4) [000301] ------------ \--* AND int $36d N002 ( 3, 2) [000299] ------------ +--* LCL_VAR int V29 loc26 u:2 (last use) $36b N003 ( 1, 1) [000300] ------------ \--* CNS_INT int 63 $66 finish(BB39). Succ(BB40). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 25/3 to $540 {PhiDef($19, $3, $366)} . SSA PHI definition: set VN of local 24/3 to $580 {PhiDef($18, $3, $366)} . The SSA definition for ByrefExposed (#20) at start of BB40 is $3a7 {3a7} The SSA definition for GcHeap (#21) at start of BB40 is $1eb {1eb} ***** BB40, STMT00057(before) N027 ( 53, 34) [000254] -ACXG---R--- * ASG long N026 ( 3, 2) [000253] D------N---- +--* LCL_VAR long V27 loc24 d:2 N025 ( 49, 31) [000252] -ACXG------- \--* ADD long N023 ( 47, 29) [000250] -ACXG------- +--* LSH long N019 ( 38, 24) [000243] -ACXG------- | +--* CALL long System.Numerics.BigInteger.op_Explicit N016 ( 18, 15) [000845] -A--G-----L- arg0 SETUP | | +--* COMMA void N009 ( 10, 8) [000838] -A--G------- | | | +--* COMMA void N004 ( 3, 3) [000833] -A------R--- | | | | +--* ASG byref N003 ( 1, 1) [000832] D------N---- | | | | | +--* LCL_VAR byref V90 tmp60 d:2 N002 ( 3, 3) [000830] ------------ | | | | | \--* ADDR byref N001 ( 3, 2) [000831] ----G--N---- | | | | | \--* LCL_VAR struct(AX) V76 tmp46 N008 ( 7, 5) [000837] -A--G------- | | | | \--* ASG ref N006 ( 3, 2) [000835] *------N---- | | | | +--* IND ref N005 ( 1, 1) [000834] ------------ | | | | | \--* LCL_VAR byref V90 tmp60 u:2 Zero Fseq[_bits] N007 ( 3, 2) [000836] ----G--N---- | | | | \--* LCL_VAR ref (AX) V54 tmp24 N015 ( 8, 7) [000844] -A--G------- | | | \--* ASG int N013 ( 4, 4) [000842] *------N---- | | | +--* IND int N012 ( 2, 2) [000841] -------N---- | | | | \--* ADD byref N010 ( 1, 1) [000839] ------------ | | | | +--* LCL_VAR byref V90 tmp60 u:2 (last use) N011 ( 1, 1) [000840] ------------ | | | | \--* CNS_INT long 8 Fseq[_sign] N014 ( 3, 2) [000843] ----G--N---- | | | \--* LCL_VAR int (AX) V55 tmp25 N018 ( 3, 3) [000847] ------------ arg0 in rcx | | \--* ADDR byref N017 ( 3, 2) [000846] -------N---- | | \--* LCL_VAR struct(AX) V76 tmp46 N022 ( 5, 4) [000249] ------------ | \--* AND int N020 ( 3, 2) [000247] ------------ | +--* LCL_VAR int V20 loc17 u:2 (last use) N021 ( 1, 1) [000248] ------------ | \--* CNS_INT int 63 N024 ( 1, 1) [000251] ------------ \--* LCL_VAR long V24 loc21 u:3 (last use) N001 [000831] LCL_VAR V76 tmp46 => $3db {3db} N002 [000830] ADDR => $426 {426} N003 [000832] LCL_VAR V90 tmp60 d:2 => $426 {426} N004 [000833] ASG => $426 {426} N005 [000834] LCL_VAR V90 tmp60 u:2 => $426 {426} N007 [000836] LCL_VAR V54 tmp24 => $18b {ByrefExposedLoad($44, $205, $3a7)} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [000837] to VN: $1ec. N008 [000837] ASG => $VN.Void N009 [000838] COMMA => $VN.Void N010 [000839] LCL_VAR V90 tmp60 u:2 (last use) => $426 {426} N011 [000840] CNS_INT 8 Fseq[_sign] => $101 {LngCns: 8} N012 [000841] ADD => $220 {ADD($101, $426)} N014 [000843] LCL_VAR V55 tmp25 => $252 {ByrefExposedLoad($45, $207, $3a8)} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [000844] to VN: $1ed. N015 [000844] ASG => $VN.Void N016 [000845] COMMA => $VN.Void N017 [000846] LCL_VAR V76 tmp46 => $3dc {3dc} N018 [000847] ADDR => $428 {428} fgCurMemoryVN[GcHeap] assigned for CALL at [000243] to VN: $1ee. N019 [000243] CALL => $454 {454} N020 [000247] LCL_VAR V20 loc17 u:2 (last use) => $362 {SUB($348, $293)} N021 [000248] CNS_INT 63 => $66 {IntCns 63} N022 [000249] AND => $370 {AND($66, $362)} N023 [000250] LSH => $492 {LSH($454, $370)} N024 [000251] LCL_VAR V24 loc21 u:3 (last use) => $580 {PhiDef($18, $3, $366)} N025 [000252] ADD => $493 {ADD($492, $580)} N026 [000253] LCL_VAR V27 loc24 d:2 => $493 {ADD($492, $580)} N027 [000254] ASG => $493 {ADD($492, $580)} ***** BB40, STMT00057(after) N027 ( 53, 34) [000254] -ACXG---R--- * ASG long $493 N026 ( 3, 2) [000253] D------N---- +--* LCL_VAR long V27 loc24 d:2 $493 N025 ( 49, 31) [000252] -ACXG------- \--* ADD long $493 N023 ( 47, 29) [000250] -ACXG------- +--* LSH long $492 N019 ( 38, 24) [000243] -ACXG------- | +--* CALL long System.Numerics.BigInteger.op_Explicit $454 N016 ( 18, 15) [000845] -A--G-----L- arg0 SETUP | | +--* COMMA void $VN.Void N009 ( 10, 8) [000838] -A--G------- | | | +--* COMMA void $VN.Void N004 ( 3, 3) [000833] -A------R--- | | | | +--* ASG byref $426 N003 ( 1, 1) [000832] D------N---- | | | | | +--* LCL_VAR byref V90 tmp60 d:2 $426 N002 ( 3, 3) [000830] ------------ | | | | | \--* ADDR byref $426 N001 ( 3, 2) [000831] ----G--N---- | | | | | \--* LCL_VAR struct(AX) V76 tmp46 $3db N008 ( 7, 5) [000837] -A--G------- | | | | \--* ASG ref $VN.Void N006 ( 3, 2) [000835] *------N---- | | | | +--* IND ref $18b N005 ( 1, 1) [000834] ------------ | | | | | \--* LCL_VAR byref V90 tmp60 u:2 Zero Fseq[_bits] $426 N007 ( 3, 2) [000836] ----G--N---- | | | | \--* LCL_VAR ref (AX) V54 tmp24 $18b N015 ( 8, 7) [000844] -A--G------- | | | \--* ASG int $VN.Void N013 ( 4, 4) [000842] *------N---- | | | +--* IND int $252 N012 ( 2, 2) [000841] -------N---- | | | | \--* ADD byref $220 N010 ( 1, 1) [000839] ------------ | | | | +--* LCL_VAR byref V90 tmp60 u:2 (last use) $426 N011 ( 1, 1) [000840] ------------ | | | | \--* CNS_INT long 8 Fseq[_sign] $101 N014 ( 3, 2) [000843] ----G--N---- | | | \--* LCL_VAR int (AX) V55 tmp25 $252 N018 ( 3, 3) [000847] ------------ arg0 in rcx | | \--* ADDR byref $428 N017 ( 3, 2) [000846] -------N---- | | \--* LCL_VAR struct(AX) V76 tmp46 $3dc N022 ( 5, 4) [000249] ------------ | \--* AND int $370 N020 ( 3, 2) [000247] ------------ | +--* LCL_VAR int V20 loc17 u:2 (last use) $362 N021 ( 1, 1) [000248] ------------ | \--* CNS_INT int 63 $66 N024 ( 1, 1) [000251] ------------ \--* LCL_VAR long V24 loc21 u:3 (last use) $580 --------- ***** BB40, STMT00058(before) N004 ( 5, 5) [000258] ------------ * JTRUE void N003 ( 3, 3) [000257] N------N---- \--* NE int N001 ( 1, 1) [000255] ------------ +--* LCL_VAR int V13 loc10 u:2 N002 ( 1, 1) [000256] ------------ \--* CNS_INT int 0 N001 [000255] LCL_VAR V13 loc10 u:2 => $293 {293} N002 [000256] CNS_INT 0 => $40 {IntCns 0} N003 [000257] NE => $35a {NE($293, $40)} ***** BB40, STMT00058(after) N004 ( 5, 5) [000258] ------------ * JTRUE void N003 ( 3, 3) [000257] N------N---- \--* NE int $35a N001 ( 1, 1) [000255] ------------ +--* LCL_VAR int V13 loc10 u:2 $293 N002 ( 1, 1) [000256] ------------ \--* CNS_INT int 0 $40 finish(BB40). Succ(BB41). Not yet completed. All preds complete, adding to allDone. Succ(BB42). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#22) at start of BB42 is $3aa {3aa} The SSA definition for GcHeap (#23) at start of BB42 is $1ee {1ee} ***** BB42, STMT00059(before) N005 ( 7, 6) [000263] -A------R--- * ASG int N004 ( 3, 2) [000262] D------N---- +--* LCL_VAR int V36 tmp6 d:3 N003 ( 3, 3) [000261] ------------ \--* ADD int N001 ( 1, 1) [000259] ------------ +--* LCL_VAR int V13 loc10 u:2 (last use) N002 ( 1, 1) [000260] ------------ \--* CNS_INT int -2 N001 [000259] LCL_VAR V13 loc10 u:2 (last use) => $293 {293} N002 [000260] CNS_INT -2 => $68 {IntCns -2} N003 [000261] ADD => $371 {ADD($68, $293)} N004 [000262] LCL_VAR V36 tmp6 d:3 => $371 {ADD($68, $293)} N005 [000263] ASG => $371 {ADD($68, $293)} ***** BB42, STMT00059(after) N005 ( 7, 6) [000263] -A------R--- * ASG int $371 N004 ( 3, 2) [000262] D------N---- +--* LCL_VAR int V36 tmp6 d:3 $371 N003 ( 3, 3) [000261] ------------ \--* ADD int $371 N001 ( 1, 1) [000259] ------------ +--* LCL_VAR int V13 loc10 u:2 (last use) $293 N002 ( 1, 1) [000260] ------------ \--* CNS_INT int -2 $68 finish(BB42). Succ(BB43). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#22) at start of BB41 is $3aa {3aa} The SSA definition for GcHeap (#23) at start of BB41 is $1ee {1ee} ***** BB41, STMT00062(before) N006 ( 10, 8) [000280] -A------R--- * ASG int N005 ( 3, 2) [000279] D------N---- +--* LCL_VAR int V36 tmp6 d:4 N004 ( 6, 5) [000278] ------------ \--* ADD int N002 ( 4, 3) [000276] ------------ +--* NEG int N001 ( 3, 2) [000275] ------------ | \--* LCL_VAR int V22 loc19 u:2 (last use) N003 ( 1, 1) [000277] ------------ \--* CNS_INT int -1 N001 [000275] LCL_VAR V22 loc19 u:2 (last use) => $24c {PhiDef($22, $2, $34b)} N002 [000276] NEG => $2c2 {NEG($24c)} N003 [000277] CNS_INT -1 => $43 {IntCns -1} N004 [000278] ADD => $372 {ADD($43, $2c2)} N005 [000279] LCL_VAR V36 tmp6 d:4 => $372 {ADD($43, $2c2)} N006 [000280] ASG => $372 {ADD($43, $2c2)} ***** BB41, STMT00062(after) N006 ( 10, 8) [000280] -A------R--- * ASG int $372 N005 ( 3, 2) [000279] D------N---- +--* LCL_VAR int V36 tmp6 d:4 $372 N004 ( 6, 5) [000278] ------------ \--* ADD int $372 N002 ( 4, 3) [000276] ------------ +--* NEG int $2c2 N001 ( 3, 2) [000275] ------------ | \--* LCL_VAR int V22 loc19 u:2 (last use) $24c N003 ( 1, 1) [000277] ------------ \--* CNS_INT int -1 $43 finish(BB41). Succ(BB43). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 36/2 to $253 {PhiDef($24, $2, $34b)} . The SSA definition for ByrefExposed (#22) at start of BB43 is $3aa {3aa} The SSA definition for GcHeap (#23) at start of BB43 is $1ee {1ee} ***** BB43, STMT00061(before) N012 ( 28, 18) [000853] -ACXG---R--- * ASG int N011 ( 1, 1) [000852] D------N---- +--* LCL_VAR int V51 tmp21 d:4 N010 ( 28, 18) [000273] --CXG------- \--* CALL nullcheck int FloatingPointType.AssembleFloatingPointValue N005 ( 1, 1) [000272] ------------ arg4 out+20 +--* LCL_VAR byref V02 arg2 u:1 (last use) N006 ( 1, 1) [000268] ------------ this in rcx +--* LCL_VAR ref V01 arg1 u:1 (last use) N007 ( 3, 2) [000269] ------------ arg1 in rdx +--* LCL_VAR long V27 loc24 u:2 (last use) N008 ( 3, 2) [000270] ------------ arg2 in r8 +--* LCL_VAR int V36 tmp6 u:2 (last use) N009 ( 3, 2) [000271] ------------ arg3 in r9 \--* LCL_VAR int V25 loc22 u:3 (last use) N001 [000848] ARGPLACE => $1ef {1ef} N002 [000849] ARGPLACE => $456 {456} N003 [000850] ARGPLACE => $2bc {2bc} N004 [000851] ARGPLACE => $2bd {2bd} N005 [000272] LCL_VAR V02 arg2 u:1 (last use) => $81 {InitVal($42)} N006 [000268] LCL_VAR V01 arg1 u:1 (last use) => $c0 {InitVal($41)} N007 [000269] LCL_VAR V27 loc24 u:2 (last use) => $493 {ADD($492, $580)} N008 [000270] LCL_VAR V36 tmp6 u:2 (last use) => $253 {PhiDef($24, $2, $34b)} N009 [000271] LCL_VAR V25 loc22 u:3 (last use) => $540 {PhiDef($19, $3, $366)} VN of ARGPLACE tree [000849] updated to $c0 {InitVal($41)} VN of ARGPLACE tree [000850] updated to $493 {ADD($492, $580)} VN of ARGPLACE tree [000851] updated to $253 {PhiDef($24, $2, $34b)} fgCurMemoryVN[GcHeap] assigned for CALL at [000273] to VN: $1f0. N010 [000273] CALL nullcheck => $2be {2be} N011 [000852] LCL_VAR V51 tmp21 d:4 => $2be {2be} N012 [000853] ASG => $2be {2be} ***** BB43, STMT00061(after) N012 ( 28, 18) [000853] -ACXG---R--- * ASG int $2be N011 ( 1, 1) [000852] D------N---- +--* LCL_VAR int V51 tmp21 d:4 $2be N010 ( 28, 18) [000273] --CXG------- \--* CALL nullcheck int FloatingPointType.AssembleFloatingPointValue $2be N005 ( 1, 1) [000272] ------------ arg4 out+20 +--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N006 ( 1, 1) [000268] ------------ this in rcx +--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 N007 ( 3, 2) [000269] ------------ arg1 in rdx +--* LCL_VAR long V27 loc24 u:2 (last use) $493 N008 ( 3, 2) [000270] ------------ arg2 in r8 +--* LCL_VAR int V36 tmp6 u:2 (last use) $253 N009 ( 3, 2) [000271] ------------ arg3 in r9 \--* LCL_VAR int V25 loc22 u:3 (last use) $540 finish(BB43). Succ(BB44). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#16) at start of BB30 is $310 {PhiMemoryDef($4c3, $30f)} The SSA definition for GcHeap (#17) at start of BB30 is $312 {PhiMemoryDef($4c3, $311)} ***** BB30, STMT00072(before) N014 ( 29, 17) [000717] -ACXG---R--- * ASG int N013 ( 1, 1) [000716] D------N---- +--* LCL_VAR int V51 tmp21 d:5 N012 ( 29, 17) [000342] --CXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits N005 ( 1, 1) [000341] ------------ arg4 out+20 +--* LCL_VAR byref V02 arg2 u:1 (last use) N008 ( 6, 3) [000339] N----------- arg2 in r8 +--* NE int N006 ( 1, 1) [000337] ------------ | +--* LCL_VAR int V10 loc7 u:2 (last use) N007 ( 1, 1) [000338] ------------ | \--* CNS_INT int 0 N009 ( 3, 2) [000335] ----G------- arg0 in rcx +--* LCL_VAR ref (AX) V12 loc9 N010 ( 1, 1) [000336] ------------ arg1 in rdx +--* LCL_VAR int V13 loc10 u:2 (last use) N011 ( 1, 1) [000340] ------------ arg3 in r9 \--* LCL_VAR ref V01 arg1 u:1 (last use) N001 [000713] ARGPLACE => $1f1 {1f1} N002 [000714] ARGPLACE => $5c0 {5c0} N003 [000712] ARGPLACE => $5c1 {5c1} N004 [000715] ARGPLACE => $1f2 {1f2} N005 [000341] LCL_VAR V02 arg2 u:1 (last use) => $81 {InitVal($42)} N006 [000337] LCL_VAR V10 loc7 u:2 (last use) => N007 [000338] CNS_INT 0 => $40 {IntCns 0} N008 [000339] NE => N009 [000335] LCL_VAR V12 loc9 => $18c {ByrefExposedLoad($44, $221, $310)} N010 [000336] LCL_VAR V13 loc10 u:2 (last use) => $293 {293} N011 [000340] LCL_VAR V01 arg1 u:1 (last use) => $c0 {InitVal($41)} VN of ARGPLACE tree [000713] updated to $18c {ByrefExposedLoad($44, $221, $310)} VN of ARGPLACE tree [000714] updated to $293 {293} VN of ARGPLACE tree [000712] updated to VN of ARGPLACE tree [000715] updated to $c0 {InitVal($41)} fgCurMemoryVN[GcHeap] assigned for CALL at [000342] to VN: $1f3. N012 [000342] CALL => $5c2 {5c2} N013 [000716] LCL_VAR V51 tmp21 d:5 => $5c2 {5c2} N014 [000717] ASG => $5c2 {5c2} ***** BB30, STMT00072(after) N014 ( 29, 17) [000717] -ACXG---R--- * ASG int $5c2 N013 ( 1, 1) [000716] D------N---- +--* LCL_VAR int V51 tmp21 d:5 $5c2 N012 ( 29, 17) [000342] --CXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits $5c2 N005 ( 1, 1) [000341] ------------ arg4 out+20 +--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N008 ( 6, 3) [000339] N----------- arg2 in r8 +--* NE int N006 ( 1, 1) [000337] ------------ | +--* LCL_VAR int V10 loc7 u:2 (last use) N007 ( 1, 1) [000338] ------------ | \--* CNS_INT int 0 $40 N009 ( 3, 2) [000335] ----G------- arg0 in rcx +--* LCL_VAR ref (AX) V12 loc9 $18c N010 ( 1, 1) [000336] ------------ arg1 in rdx +--* LCL_VAR int V13 loc10 u:2 (last use) $293 N011 ( 1, 1) [000340] ------------ arg3 in r9 \--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 finish(BB30). Succ(BB44). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#30) at start of BB22 is $389 {389} The SSA definition for GcHeap (#31) at start of BB22 is $1ce {1ce} ***** BB22, STMT00079(before) N006 ( 25, 13) [000373] -ACXG---R--- * ASG long N005 ( 3, 2) [000372] *--X---N---- +--* IND long N004 ( 1, 1) [000369] ------------ | \--* LCL_VAR byref V02 arg2 u:1 (last use) N003 ( 21, 10) [000371] --CXG------- \--* CALLV ind long FloatingPointType.get_Zero N002 ( 1, 1) [000370] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 (last use) N001 [000602] ARGPLACE => $1f4 {1f4} N002 [000370] LCL_VAR V01 arg1 u:1 (last use) => $c0 {InitVal($41)} fgCurMemoryVN[GcHeap] assigned for CALL at [000371] to VN: $1f5. N003 [000371] CALLV ind => $457 {457} N004 [000369] LCL_VAR V02 arg2 u:1 (last use) => $81 {InitVal($42)} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [000373] to VN: $1f6. N006 [000373] ASG => $VN.Void ***** BB22, STMT00079(after) N006 ( 25, 13) [000373] -ACXG---R--- * ASG long $VN.Void N005 ( 3, 2) [000372] *--X---N---- +--* IND long $457 N004 ( 1, 1) [000369] ------------ | \--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N003 ( 21, 10) [000371] --CXG------- \--* CALLV ind long FloatingPointType.get_Zero $457 N002 ( 1, 1) [000370] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 --------- ***** BB22, STMT00110(before) N002 ( 2, 2) [000524] ------------ * RETURN int N001 ( 1, 1) [000374] ------------ \--* CNS_INT int 2 N001 [000374] CNS_INT 2 => $42 {IntCns 2} N002 [000524] RETURN => $5c4 {5c4} ***** BB22, STMT00110(after) N002 ( 2, 2) [000524] ------------ * RETURN int $5c4 N001 ( 1, 1) [000374] ------------ \--* CNS_INT int 2 $42 finish(BB22). The SSA definition for ByrefExposed (#8) at start of BB16 is $388 {388} The SSA definition for GcHeap (#9) at start of BB16 is $1cc {1cc} ***** BB16, STMT00021(before) N014 ( 29, 17) [000600] -ACXG---R--- * ASG int N013 ( 1, 1) [000599] D------N---- +--* LCL_VAR int V51 tmp21 d:3 N012 ( 29, 17) [000089] --CXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits N005 ( 1, 1) [000088] ------------ arg4 out+20 +--* LCL_VAR byref V02 arg2 u:1 (last use) N008 ( 6, 3) [000086] N----------- arg2 in r8 +--* NE int N006 ( 1, 1) [000084] ------------ | +--* LCL_VAR int V10 loc7 u:2 (last use) N007 ( 1, 1) [000085] ------------ | \--* CNS_INT int 0 N009 ( 3, 2) [000082] ----G------- arg0 in rcx +--* LCL_VAR ref (AX) V12 loc9 N010 ( 1, 1) [000083] ------------ arg1 in rdx +--* LCL_VAR int V13 loc10 u:2 (last use) N011 ( 1, 1) [000087] ------------ arg3 in r9 \--* LCL_VAR ref V01 arg1 u:1 (last use) N001 [000596] ARGPLACE => $1f7 {1f7} N002 [000597] ARGPLACE => $5c5 {5c5} N003 [000595] ARGPLACE => $5c6 {5c6} N004 [000598] ARGPLACE => $1f8 {1f8} N005 [000088] LCL_VAR V02 arg2 u:1 (last use) => $81 {InitVal($42)} N006 [000084] LCL_VAR V10 loc7 u:2 (last use) => N007 [000085] CNS_INT 0 => $40 {IntCns 0} N008 [000086] NE => N009 [000082] LCL_VAR V12 loc9 => $18d {ByrefExposedLoad($44, $221, $388)} N010 [000083] LCL_VAR V13 loc10 u:2 (last use) => $293 {293} N011 [000087] LCL_VAR V01 arg1 u:1 (last use) => $c0 {InitVal($41)} VN of ARGPLACE tree [000596] updated to $18d {ByrefExposedLoad($44, $221, $388)} VN of ARGPLACE tree [000597] updated to $293 {293} VN of ARGPLACE tree [000595] updated to VN of ARGPLACE tree [000598] updated to $c0 {InitVal($41)} fgCurMemoryVN[GcHeap] assigned for CALL at [000089] to VN: $1f9. N012 [000089] CALL => $5c7 {5c7} N013 [000599] LCL_VAR V51 tmp21 d:3 => $5c7 {5c7} N014 [000600] ASG => $5c7 {5c7} ***** BB16, STMT00021(after) N014 ( 29, 17) [000600] -ACXG---R--- * ASG int $5c7 N013 ( 1, 1) [000599] D------N---- +--* LCL_VAR int V51 tmp21 d:3 $5c7 N012 ( 29, 17) [000089] --CXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits $5c7 N005 ( 1, 1) [000088] ------------ arg4 out+20 +--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N008 ( 6, 3) [000086] N----------- arg2 in r8 +--* NE int N006 ( 1, 1) [000084] ------------ | +--* LCL_VAR int V10 loc7 u:2 (last use) N007 ( 1, 1) [000085] ------------ | \--* CNS_INT int 0 $40 N009 ( 3, 2) [000082] ----G------- arg0 in rcx +--* LCL_VAR ref (AX) V12 loc9 $18d N010 ( 1, 1) [000083] ------------ arg1 in rdx +--* LCL_VAR int V13 loc10 u:2 (last use) $293 N011 ( 1, 1) [000087] ------------ arg3 in r9 \--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 finish(BB16). Succ(BB44). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 51/2 to $254 {PhiDef($33, $2, $374)} . The SSA definition for ByrefExposed (#8) at start of BB44 is $388 {388} The SSA definition for GcHeap (#9) at start of BB44 is $1cc {1cc} ***** BB44, STMT00109(before) N002 ( 2, 2) [000523] ------------ * RETURN int N001 ( 1, 1) [000522] -------N---- \--* LCL_VAR int V51 tmp21 u:2 (last use) N001 [000522] LCL_VAR V51 tmp21 u:2 (last use) => $254 {PhiDef($33, $2, $374)} N002 [000523] RETURN => $5c9 {5c9} ***** BB44, STMT00109(after) N002 ( 2, 2) [000523] ------------ * RETURN int $5c9 N001 ( 1, 1) [000522] -------N---- \--* LCL_VAR int V51 tmp21 u:2 (last use) $254 finish(BB44). The SSA definition for ByrefExposed (#34) at start of BB12 is $384 {384} The SSA definition for GcHeap (#35) at start of BB12 is $1c8 {1c8} ***** BB12, STMT00085(before) N006 ( 25, 13) [000396] -ACXG---R--- * ASG long N005 ( 3, 2) [000395] *--X---N---- +--* IND long N004 ( 1, 1) [000392] ------------ | \--* LCL_VAR byref V02 arg2 u:1 (last use) N003 ( 21, 10) [000394] --CXG------- \--* CALLV ind long FloatingPointType.get_Infinity N002 ( 1, 1) [000393] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 (last use) N001 [000570] ARGPLACE => $1fa {1fa} N002 [000393] LCL_VAR V01 arg1 u:1 (last use) => $c0 {InitVal($41)} fgCurMemoryVN[GcHeap] assigned for CALL at [000394] to VN: $1fb. N003 [000394] CALLV ind => $458 {458} N004 [000392] LCL_VAR V02 arg2 u:1 (last use) => $81 {InitVal($42)} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [000396] to VN: $1fc. N006 [000396] ASG => $VN.Void ***** BB12, STMT00085(after) N006 ( 25, 13) [000396] -ACXG---R--- * ASG long $VN.Void N005 ( 3, 2) [000395] *--X---N---- +--* IND long $458 N004 ( 1, 1) [000392] ------------ | \--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N003 ( 21, 10) [000394] --CXG------- \--* CALLV ind long FloatingPointType.get_Infinity $458 N002 ( 1, 1) [000393] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 --------- ***** BB12, STMT00108(before) N002 ( 2, 2) [000521] ------------ * RETURN int N001 ( 1, 1) [000397] ------------ \--* CNS_INT int 3 N001 [000397] CNS_INT 3 => $48 {IntCns 3} N002 [000521] RETURN => $5ca {5ca} ***** BB12, STMT00108(after) N002 ( 2, 2) [000521] ------------ * RETURN int $5ca N001 ( 1, 1) [000397] ------------ \--* CNS_INT int 3 $48 finish(BB12). The SSA definition for ByrefExposed (#1) at start of BB03 is $c1 {InitVal($43)} The SSA definition for GcHeap (#1) at start of BB03 is $c1 {InitVal($43)} ***** BB03, STMT00087(before) N006 ( 25, 13) [000403] -ACXG---R--- * ASG long N005 ( 3, 2) [000402] *--X---N---- +--* IND long N004 ( 1, 1) [000399] ------------ | \--* LCL_VAR byref V02 arg2 u:1 (last use) N003 ( 21, 10) [000401] --CXG------- \--* CALLV ind long FloatingPointType.get_Zero N002 ( 1, 1) [000400] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 (last use) N001 [000541] ARGPLACE => $1fd {1fd} N002 [000400] LCL_VAR V01 arg1 u:1 (last use) => $c0 {InitVal($41)} fgCurMemoryVN[GcHeap] assigned for CALL at [000401] to VN: $1fe. N003 [000401] CALLV ind => $459 {459} N004 [000399] LCL_VAR V02 arg2 u:1 (last use) => $81 {InitVal($42)} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [000403] to VN: $1ff. N006 [000403] ASG => $VN.Void ***** BB03, STMT00087(after) N006 ( 25, 13) [000403] -ACXG---R--- * ASG long $VN.Void N005 ( 3, 2) [000402] *--X---N---- +--* IND long $459 N004 ( 1, 1) [000399] ------------ | \--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N003 ( 21, 10) [000401] --CXG------- \--* CALLV ind long FloatingPointType.get_Zero $459 N002 ( 1, 1) [000400] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 --------- ***** BB03, STMT00107(before) N002 ( 2, 2) [000520] ------------ * RETURN int N001 ( 1, 1) [000404] ------------ \--* CNS_INT int 1 N001 [000404] CNS_INT 1 => $41 {IntCns 1} N002 [000520] RETURN => $5cb {5cb} ***** BB03, STMT00107(after) N002 ( 2, 2) [000520] ------------ * RETURN int $5cb N001 ( 1, 1) [000404] ------------ \--* CNS_INT int 1 $41 finish(BB03). *************** Finishing PHASE Do value numbering *************** Starting PHASE Hoist loop code *************** Finishing PHASE Hoist loop code *************** Starting PHASE VN based copy prop *************** In optVnCopyProp() Copy Assertion for BB01 curSsaName stack: { } Live vars: {V00 V01 V02} => {V00 V01 V02 V52} Live vars: {V00 V01 V02 V52} => {V01 V02 V52} Live vars: {V01 V02 V52} => {V01 V02 V52 V53} Copy Assertion for BB02 curSsaName stack: { 0-[000531]:V00 52-[000530]:V52 53-[000534]:V53 } Copy Assertion for BB04 curSsaName stack: { 0-[000531]:V00 52-[000530]:V52 53-[000534]:V53 } Live vars: {V01 V02 V52 V53} => {V01 V02 V03 V52 V53} Live vars: {V01 V02 V03 V52 V53} => {V01 V02 V03 V40 V52 V53} VN based copy assertion for [000412] V53 @00000280 by [000423] V40 @00000280. N001 ( 1, 1) [000412] ------------ * LCL_VAR int V53 tmp23 u:2 copy propagated to: N001 ( 1, 1) [000412] ------------ * LCL_VAR int V40 tmp10 u:2 Copy Assertion for BB07 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 3-[000012]:V03 40-[000423]:V40 52-[000530]:V52 53-[000534]:V53 } Live vars: {V01 V02 V03 V39 V52 V53} => {V01 V02 V03 V31 V39 V52 V53} Live vars: {V01 V02 V03 V31 V39 V52 V53} => {V01 V02 V03 V31 V39 V42 V52 V53} Live vars: {V01 V02 V03 V31 V39 V42 V52 V53} => {V01 V02 V03 V31 V42 V52 V53} VN based copy assertion for [000023] V39 @00000241 by [000020] V31 @00000241. N001 ( 3, 2) [000023] ------------ * LCL_VAR int V39 tmp9 u:2 (last use) $241 copy propagated to: N001 ( 3, 2) [000023] ------------ * LCL_VAR int V31 tmp1 u:2 (last use) $241 Copy Assertion for BB10 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 3-[000012]:V03 52-[000530]:V52 53-[000534]:V53 31-[000020]:V31 39-[000884]:V39 40-[000423]:V40 42-[000442]:V42 } Live vars: {V01 V02 V03 V31 V41 V52 V53} => {V01 V02 V03 V41 V52 V53} Live vars: {V01 V02 V03 V41 V52 V53} => {V01 V02 V03 V05 V41 V52 V53} Live vars: {V01 V02 V03 V05 V41 V52 V53} => {V01 V02 V03 V05 V08 V41 V52 V53} Live vars: {V01 V02 V03 V05 V08 V41 V52 V53} => {V01 V02 V03 V05 V08 V09 V41 V52 V53} VN based copy assertion for [000052] V41 @00000242 by [000043] V08 @00000242. N002 ( 1, 1) [000052] ------------ * LCL_VAR int V41 tmp11 u:2 $242 copy propagated to: N002 ( 1, 1) [000052] ------------ * LCL_VAR int V08 loc5 u:2 $242 Live vars: {V01 V02 V03 V05 V08 V09 V41 V52 V53} => {V01 V02 V03 V05 V08 V09 V10 V41 V52 V53} Live vars: {V01 V02 V03 V05 V08 V09 V10 V41 V52 V53} => {V01 V02 V03 V05 V08 V09 V10 V41 V52 V53 V75} Live vars: {V01 V02 V03 V05 V08 V09 V10 V41 V52 V53 V75} => {V01 V02 V03 V05 V08 V09 V10 V41 V52 V53 V74 V75} Live vars: {V01 V02 V03 V05 V08 V09 V10 V41 V52 V53 V74 V75} => {V01 V02 V03 V05 V08 V09 V10 V41 V52 V53 V75} Live vars: {V01 V02 V03 V05 V08 V09 V10 V41 V52 V53 V75} => {V01 V02 V03 V05 V08 V09 V10 V41 V52 V53} Live vars: {V01 V02 V03 V05 V08 V09 V10 V41 V52 V53} => {V01 V02 V03 V05 V08 V09 V10 V52 V53} VN based copy assertion for [000058] V41 @00000242 by [000043] V08 @00000242. N026 ( 1, 1) [000058] ------------ * LCL_VAR int V41 tmp11 u:2 (last use) $242 copy propagated to: N026 ( 1, 1) [000058] ------------ * LCL_VAR int V08 loc5 u:2 (last use) $242 Copy Assertion for BB14 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 3-[000012]:V03 74-[000548]:V74 5-[000034]:V05 75-[000562]:V75 52-[000530]:V52 53-[000534]:V53 8-[000043]:V08 31-[000020]:V31 9-[000049]:V09 10-[000054]:V10 39-[000884]:V39 40-[000423]:V40 41-[000881]:V41 42-[000442]:V42 } Live vars: {V01 V02 V03 V08 V09 V10 V52 V53} => {V01 V02 V03 V08 V09 V10 V52 V53 V77} Live vars: {V01 V02 V03 V08 V09 V10 V52 V53 V77} => {V01 V02 V03 V08 V09 V10 V52 V53} Live vars: {V01 V02 V03 V08 V09 V10 V52 V53} => {V01 V02 V03 V08 V09 V10 V13 V52 V53} Copy Assertion for BB44 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 3-[000012]:V03 5-[000034]:V05 8-[000043]:V08 9-[000049]:V09 10-[000054]:V10 13-[000076]:V13 74-[000548]:V74 75-[000562]:V75 77-[000578]:V77 31-[000020]:V31 39-[000884]:V39 40-[000423]:V40 41-[000881]:V41 42-[000442]:V42 52-[000530]:V52 53-[000534]:V53 } Live vars: {V51} => {} Copy Assertion for BB16 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 3-[000012]:V03 5-[000034]:V05 8-[000043]:V08 9-[000049]:V09 10-[000054]:V10 13-[000076]:V13 74-[000548]:V74 75-[000562]:V75 77-[000578]:V77 31-[000020]:V31 39-[000884]:V39 40-[000423]:V40 41-[000881]:V41 42-[000442]:V42 52-[000530]:V52 53-[000534]:V53 } Live vars: {V01 V02 V10 V13} => {V01 V10 V13} Live vars: {V01 V10 V13} => {V01 V13} Live vars: {V01 V13} => {V01} Live vars: {V01} => {} Live vars: {} => {V51} Copy Assertion for BB15 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 2-[000088]:V02 3-[000012]:V03 5-[000034]:V05 8-[000043]:V08 9-[000049]:V09 10-[000054]:V10 13-[000076]:V13 74-[000548]:V74 75-[000562]:V75 77-[000578]:V77 31-[000020]:V31 39-[000884]:V39 40-[000423]:V40 41-[000881]:V41 42-[000442]:V42 52-[000530]:V52 53-[000534]:V53 } Copy Assertion for BB17 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 2-[000088]:V02 3-[000012]:V03 5-[000034]:V05 8-[000043]:V08 9-[000049]:V09 10-[000054]:V10 13-[000076]:V13 74-[000548]:V74 75-[000562]:V75 77-[000578]:V77 31-[000020]:V31 39-[000884]:V39 40-[000423]:V40 41-[000881]:V41 42-[000442]:V42 52-[000530]:V52 53-[000534]:V53 } Copy Assertion for BB20 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 2-[000088]:V02 3-[000012]:V03 5-[000034]:V05 8-[000043]:V08 9-[000049]:V09 10-[000054]:V10 13-[000076]:V13 74-[000548]:V74 75-[000562]:V75 77-[000578]:V77 31-[000020]:V31 39-[000884]:V39 40-[000423]:V40 41-[000881]:V41 42-[000442]:V42 52-[000530]:V52 53-[000534]:V53 } Live vars: {V01 V02 V03 V08 V09 V10 V13 V32 V52 V53} => {V01 V02 V03 V08 V09 V10 V13 V52 V53} Live vars: {V01 V02 V03 V08 V09 V10 V13 V52 V53} => {V01 V02 V03 V08 V09 V10 V13 V14 V52 V53} Copy Assertion for BB23 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 2-[000088]:V02 3-[000012]:V03 5-[000034]:V05 8-[000043]:V08 9-[000049]:V09 10-[000054]:V10 13-[000076]:V13 14-[000111]:V14 74-[000548]:V74 75-[000562]:V75 77-[000578]:V77 31-[000020]:V31 32-[000878]:V32 39-[000884]:V39 40-[000423]:V40 41-[000881]:V41 42-[000442]:V42 52-[000530]:V52 53-[000534]:V53 } Live vars: {V01 V02 V03 V08 V09 V10 V13 V14 V52 V53} => {V01 V02 V03 V08 V09 V10 V13 V14 V52 V53 V79} Live vars: {V01 V02 V03 V08 V09 V10 V13 V14 V52 V53 V79} => {V01 V02 V03 V08 V09 V10 V13 V14 V52 V53 V78 V79} Live vars: {V01 V02 V03 V08 V09 V10 V13 V14 V52 V53 V78 V79} => {V01 V02 V03 V08 V09 V10 V13 V14 V53 V78 V79} Live vars: {V01 V02 V03 V08 V09 V10 V13 V14 V53 V78 V79} => {V01 V02 V03 V08 V09 V10 V13 V14 V53 V79} Live vars: {V01 V02 V03 V08 V09 V10 V13 V14 V53 V79} => {V01 V02 V03 V08 V09 V10 V13 V14 V79} Live vars: {V01 V02 V03 V08 V09 V10 V13 V14 V79} => {V01 V02 V03 V08 V09 V10 V13 V14} Live vars: {V01 V02 V03 V08 V09 V10 V13 V14} => {V01 V02 V03 V09 V10 V13 V14} Live vars: {V01 V02 V03 V09 V10 V13 V14} => {V01 V02 V03 V10 V13 V14} Live vars: {V01 V02 V03 V10 V13 V14} => {V01 V02 V03 V10 V13 V14 V80} Live vars: {V01 V02 V03 V10 V13 V14 V80} => {V01 V02 V03 V10 V13 V14} Live vars: {V01 V02 V03 V10 V13 V14} => {V01 V02 V03 V10 V13} Live vars: {V01 V02 V03 V10 V13} => {V01 V02 V03 V10 V13 V64} Live vars: {V01 V02 V03 V10 V13 V64} => {V01 V02 V03 V10 V13 V64 V65} Live vars: {V01 V02 V03 V10 V13 V64 V65} => {V01 V02 V03 V10 V13 V64 V65 V81} Live vars: {V01 V02 V03 V10 V13 V64 V65 V81} => {V01 V02 V03 V10 V13 V65 V81} Live vars: {V01 V02 V03 V10 V13 V65 V81} => {V01 V02 V03 V10 V13 V65} Live vars: {V01 V02 V03 V10 V13 V65} => {V01 V02 V03 V10 V13} Live vars: {V01 V02 V03 V10 V13} => {V01 V02 V03 V10 V13 V43} Live vars: {V01 V02 V03 V10 V13 V43} => {V01 V02 V03 V10 V13 V17 V43} Live vars: {V01 V02 V03 V10 V13 V17 V43} => {V01 V02 V03 V10 V13 V17 V43 V66} Live vars: {V01 V02 V03 V10 V13 V17 V43 V66} => {V01 V02 V03 V10 V13 V17 V43 V66 V67} Live vars: {V01 V02 V03 V10 V13 V17 V43 V66 V67} => {V01 V02 V03 V10 V13 V17 V43 V66 V67 V82} Live vars: {V01 V02 V03 V10 V13 V17 V43 V66 V67 V82} => {V01 V02 V03 V10 V13 V17 V43 V67 V82} Live vars: {V01 V02 V03 V10 V13 V17 V43 V67 V82} => {V01 V02 V03 V10 V13 V17 V43 V67} Live vars: {V01 V02 V03 V10 V13 V17 V43 V67} => {V01 V02 V03 V10 V13 V17 V43} Live vars: {V01 V02 V03 V10 V13 V17 V43} => {V01 V02 V03 V10 V13 V17 V43 V46} Live vars: {V01 V02 V03 V10 V13 V17 V43 V46} => {V01 V02 V03 V10 V13 V17 V18 V43 V46} Live vars: {V01 V02 V03 V10 V13 V17 V18 V43 V46} => {V01 V02 V03 V10 V13 V17 V18 V43} VN based copy assertion for [000156] V46 @000002A3 by [000154] V18 @000002A3. N001 ( 3, 2) [000156] ------------ * LCL_VAR int V46 tmp16 u:2 (last use) $2a3 copy propagated to: N001 ( 3, 2) [000156] ------------ * LCL_VAR int V18 loc15 u:2 (last use) $2a3 Live vars: {V01 V02 V03 V10 V13 V17 V18 V43} => {V01 V02 V03 V10 V13 V17 V18} VN based copy assertion for [000157] V43 @0000029F by [000147] V17 @0000029F. N002 ( 3, 2) [000157] ------------ * LCL_VAR int V43 tmp13 u:2 (last use) $29f copy propagated to: N002 ( 3, 2) [000157] ------------ * LCL_VAR int V17 loc14 u:2 (last use) $29f Copy Assertion for BB26 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 2-[000088]:V02 3-[000012]:V03 64-[000652]:V64 5-[000034]:V05 65-[000655]:V65 66-[000681]:V66 67-[000684]:V67 8-[000043]:V08 9-[000049]:V09 10-[000054]:V10 13-[000076]:V13 14-[000111]:V14 74-[000548]:V74 75-[000562]:V75 17-[000147]:V17 18-[000154]:V18 77-[000578]:V77 78-[000608]:V78 79-[000622]:V79 80-[000636]:V80 81-[000664]:V81 82-[000693]:V82 31-[000020]:V31 32-[000878]:V32 39-[000884]:V39 40-[000423]:V40 41-[000881]:V41 42-[000442]:V42 43-[000467]:V43 46-[000485]:V46 52-[000530]:V52 53-[000534]:V53 } Live vars: {V01 V02 V03 V10 V13 V33} => {V01 V02 V03 V10 V13 V19 V33} Live vars: {V01 V02 V03 V10 V13 V19 V33} => {V01 V02 V03 V10 V13 V19} VN based copy assertion for [000169] V33 @00000248 by [000167] V19 @00000248. N001 ( 3, 2) [000169] ------------ * LCL_VAR int V33 tmp3 u:2 (last use) $248 copy propagated to: N001 ( 3, 2) [000169] ------------ * LCL_VAR int V19 loc16 u:2 (last use) $248 Copy Assertion for BB28 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 2-[000088]:V02 3-[000012]:V03 64-[000652]:V64 5-[000034]:V05 65-[000655]:V65 66-[000681]:V66 67-[000684]:V67 8-[000043]:V08 9-[000049]:V09 10-[000054]:V10 13-[000076]:V13 14-[000111]:V14 74-[000548]:V74 75-[000562]:V75 17-[000147]:V17 18-[000154]:V18 77-[000578]:V77 19-[000167]:V19 78-[000608]:V78 79-[000622]:V79 80-[000636]:V80 81-[000664]:V81 82-[000693]:V82 31-[000020]:V31 32-[000878]:V32 33-[000875]:V33 39-[000884]:V39 40-[000423]:V40 41-[000881]:V41 42-[000442]:V42 43-[000467]:V43 46-[000485]:V46 52-[000530]:V52 53-[000534]:V53 } Live vars: {V01 V02 V03 V10 V13 V19} => {V01 V02 V10 V13 V19} Live vars: {V01 V02 V10 V13 V19} => {V01 V02 V10 V13 V19 V20} Live vars: {V01 V02 V10 V13 V19 V20} => {V01 V02 V10 V13 V19 V20 V21} Copy Assertion for BB32 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 2-[000088]:V02 3-[000012]:V03 64-[000652]:V64 5-[000034]:V05 65-[000655]:V65 66-[000681]:V66 67-[000684]:V67 8-[000043]:V08 9-[000049]:V09 10-[000054]:V10 13-[000076]:V13 14-[000111]:V14 74-[000548]:V74 75-[000562]:V75 17-[000147]:V17 18-[000154]:V18 77-[000578]:V77 19-[000167]:V19 78-[000608]:V78 20-[000176]:V20 79-[000622]:V79 21-[000179]:V21 80-[000636]:V80 81-[000664]:V81 82-[000693]:V82 31-[000020]:V31 32-[000878]:V32 33-[000875]:V33 39-[000884]:V39 40-[000423]:V40 41-[000881]:V41 42-[000442]:V42 43-[000467]:V43 46-[000485]:V46 52-[000530]:V52 53-[000534]:V53 } Live vars: {V01 V02 V13 V19 V20 V21} => {V01 V02 V13 V19 V20 V21 V70} Live vars: {V01 V02 V13 V19 V20 V21 V70} => {V01 V02 V13 V19 V20 V21 V70 V71} Live vars: {V01 V02 V13 V19 V20 V21 V70 V71} => {V01 V02 V13 V19 V20 V21 V70 V71 V84} Live vars: {V01 V02 V13 V19 V20 V21 V70 V71 V84} => {V01 V02 V13 V19 V20 V21 V70 V71 V83 V84} Live vars: {V01 V02 V13 V19 V20 V21 V70 V71 V83 V84} => {V01 V02 V13 V19 V20 V21 V71 V83 V84} Live vars: {V01 V02 V13 V19 V20 V21 V71 V83 V84} => {V01 V02 V13 V19 V20 V21 V71 V84} Live vars: {V01 V02 V13 V19 V20 V21 V71 V84} => {V01 V02 V13 V19 V20 V21 V84} Live vars: {V01 V02 V13 V19 V20 V21 V84} => {V01 V02 V13 V19 V20 V21} Copy Assertion for BB35 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 2-[000088]:V02 3-[000012]:V03 64-[000652]:V64 5-[000034]:V05 65-[000655]:V65 66-[000681]:V66 67-[000684]:V67 8-[000043]:V08 9-[000049]:V09 10-[000054]:V10 70-[000725]:V70 71-[000728]:V71 13-[000076]:V13 14-[000111]:V14 74-[000548]:V74 75-[000562]:V75 17-[000147]:V17 18-[000154]:V18 77-[000578]:V77 19-[000167]:V19 78-[000608]:V78 20-[000176]:V20 79-[000622]:V79 21-[000872]:V21 80-[000636]:V80 81-[000664]:V81 82-[000693]:V82 83-[000737]:V83 84-[000751]:V84 31-[000020]:V31 32-[000878]:V32 33-[000875]:V33 39-[000884]:V39 40-[000423]:V40 41-[000881]:V41 42-[000442]:V42 43-[000467]:V43 46-[000485]:V46 52-[000530]:V52 53-[000534]:V53 } Live vars: {V01 V02 V13 V20 V21 V34} => {V01 V02 V13 V20 V21} Live vars: {V01 V02 V13 V20 V21} => {V01 V02 V13 V20 V21 V22} Live vars: {V01 V02 V13 V20 V21 V22} => {V01 V02 V13 V20 V22} Live vars: {V01 V02 V13 V20 V22} => {V01 V02 V13 V20 V22 V88} Live vars: {V01 V02 V13 V20 V22 V88} => {V01 V02 V13 V20 V22 V85 V88} Live vars: {V01 V02 V13 V20 V22 V85 V88} => {V01 V02 V13 V20 V22 V88} Live vars: {V01 V02 V13 V20 V22 V88} => {V01 V02 V13 V20 V22 V87 V88} Live vars: {V01 V02 V13 V20 V22 V87 V88} => {V01 V02 V13 V20 V22 V88} Live vars: {V01 V02 V13 V20 V22 V88} => {V01 V02 V13 V20 V22} Live vars: {V01 V02 V13 V20 V22} => {V01 V02 V13 V20 V22 V89} Live vars: {V01 V02 V13 V20 V22 V89} => {V01 V02 V13 V20 V22} Live vars: {V01 V02 V13 V20 V22} => {V01 V02 V13 V20 V22 V24} Live vars: {V01 V02 V13 V20 V22 V24} => {V01 V02 V13 V20 V22 V24 V25} Live vars: {V01 V02 V13 V20 V22 V24 V25} => {V01 V02 V13 V20 V22 V24 V25 V26} Copy Assertion for BB40 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 2-[000088]:V02 3-[000012]:V03 5-[000034]:V05 8-[000043]:V08 9-[000049]:V09 10-[000054]:V10 13-[000076]:V13 14-[000111]:V14 17-[000147]:V17 18-[000154]:V18 19-[000167]:V19 20-[000176]:V20 21-[000872]:V21 22-[000203]:V22 24-[000225]:V24 25-[000231]:V25 26-[000236]:V26 31-[000020]:V31 32-[000878]:V32 33-[000875]:V33 34-[000869]:V34 39-[000884]:V39 40-[000423]:V40 41-[000881]:V41 42-[000442]:V42 43-[000467]:V43 46-[000485]:V46 52-[000530]:V52 53-[000534]:V53 64-[000652]:V64 65-[000655]:V65 66-[000681]:V66 67-[000684]:V67 70-[000725]:V70 71-[000728]:V71 74-[000548]:V74 75-[000562]:V75 77-[000578]:V77 78-[000608]:V78 79-[000622]:V79 80-[000636]:V80 81-[000664]:V81 82-[000693]:V82 83-[000737]:V83 84-[000751]:V84 85-[000763]:V85 87-[000782]:V87 88-[000796]:V88 89-[000809]:V89 } Live vars: {V01 V02 V13 V20 V22 V24 V25} => {V01 V02 V13 V20 V22 V24 V25 V90} Live vars: {V01 V02 V13 V20 V22 V24 V25 V90} => {V01 V02 V13 V20 V22 V24 V25} Live vars: {V01 V02 V13 V20 V22 V24 V25} => {V01 V02 V13 V22 V24 V25} Live vars: {V01 V02 V13 V22 V24 V25} => {V01 V02 V13 V22 V25} Live vars: {V01 V02 V13 V22 V25} => {V01 V02 V13 V22 V25 V27} Copy Assertion for BB43 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 2-[000088]:V02 3-[000012]:V03 5-[000034]:V05 8-[000043]:V08 9-[000049]:V09 10-[000054]:V10 13-[000076]:V13 14-[000111]:V14 17-[000147]:V17 18-[000154]:V18 19-[000167]:V19 20-[000176]:V20 21-[000872]:V21 22-[000203]:V22 24-[000860]:V24 25-[000863]:V25 26-[000236]:V26 27-[000253]:V27 31-[000020]:V31 32-[000878]:V32 33-[000875]:V33 34-[000869]:V34 39-[000884]:V39 40-[000423]:V40 41-[000881]:V41 42-[000442]:V42 43-[000467]:V43 46-[000485]:V46 52-[000530]:V52 53-[000534]:V53 64-[000652]:V64 65-[000655]:V65 66-[000681]:V66 67-[000684]:V67 70-[000725]:V70 71-[000728]:V71 74-[000548]:V74 75-[000562]:V75 77-[000578]:V77 78-[000608]:V78 79-[000622]:V79 80-[000636]:V80 81-[000664]:V81 82-[000693]:V82 83-[000737]:V83 84-[000751]:V84 85-[000763]:V85 87-[000782]:V87 88-[000796]:V88 89-[000809]:V89 90-[000832]:V90 } Live vars: {V01 V02 V25 V27 V36} => {V01 V25 V27 V36} Live vars: {V01 V25 V27 V36} => {V25 V27 V36} Live vars: {V25 V27 V36} => {V25 V36} Live vars: {V25 V36} => {V25} Live vars: {V25} => {} Live vars: {} => {V51} Copy Assertion for BB42 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 2-[000088]:V02 3-[000012]:V03 5-[000034]:V05 8-[000043]:V08 9-[000049]:V09 10-[000054]:V10 13-[000076]:V13 14-[000111]:V14 17-[000147]:V17 18-[000154]:V18 19-[000167]:V19 20-[000176]:V20 21-[000872]:V21 22-[000203]:V22 24-[000860]:V24 25-[000863]:V25 26-[000236]:V26 27-[000253]:V27 31-[000020]:V31 32-[000878]:V32 33-[000875]:V33 34-[000869]:V34 39-[000884]:V39 40-[000423]:V40 41-[000881]:V41 42-[000442]:V42 43-[000467]:V43 46-[000485]:V46 52-[000530]:V52 53-[000534]:V53 64-[000652]:V64 65-[000655]:V65 66-[000681]:V66 67-[000684]:V67 70-[000725]:V70 71-[000728]:V71 74-[000548]:V74 75-[000562]:V75 77-[000578]:V77 78-[000608]:V78 79-[000622]:V79 80-[000636]:V80 81-[000664]:V81 82-[000693]:V82 83-[000737]:V83 84-[000751]:V84 85-[000763]:V85 87-[000782]:V87 88-[000796]:V88 89-[000809]:V89 90-[000832]:V90 } Live vars: {V01 V02 V13 V25 V27} => {V01 V02 V25 V27} Live vars: {V01 V02 V25 V27} => {V01 V02 V25 V27 V36} Copy Assertion for BB41 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 2-[000088]:V02 3-[000012]:V03 5-[000034]:V05 8-[000043]:V08 9-[000049]:V09 10-[000054]:V10 13-[000076]:V13 14-[000111]:V14 17-[000147]:V17 18-[000154]:V18 19-[000167]:V19 20-[000176]:V20 21-[000872]:V21 22-[000203]:V22 24-[000860]:V24 25-[000863]:V25 26-[000236]:V26 27-[000253]:V27 31-[000020]:V31 32-[000878]:V32 33-[000875]:V33 34-[000869]:V34 39-[000884]:V39 40-[000423]:V40 41-[000881]:V41 42-[000442]:V42 43-[000467]:V43 46-[000485]:V46 52-[000530]:V52 53-[000534]:V53 64-[000652]:V64 65-[000655]:V65 66-[000681]:V66 67-[000684]:V67 70-[000725]:V70 71-[000728]:V71 74-[000548]:V74 75-[000562]:V75 77-[000578]:V77 78-[000608]:V78 79-[000622]:V79 80-[000636]:V80 81-[000664]:V81 82-[000693]:V82 83-[000737]:V83 84-[000751]:V84 85-[000763]:V85 87-[000782]:V87 88-[000796]:V88 89-[000809]:V89 90-[000832]:V90 } Live vars: {V01 V02 V22 V25 V27} => {V01 V02 V25 V27} Live vars: {V01 V02 V25 V27} => {V01 V02 V25 V27 V36} Copy Assertion for BB36 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 2-[000088]:V02 3-[000012]:V03 5-[000034]:V05 8-[000043]:V08 9-[000049]:V09 10-[000054]:V10 13-[000076]:V13 14-[000111]:V14 17-[000147]:V17 18-[000154]:V18 19-[000167]:V19 20-[000176]:V20 21-[000872]:V21 22-[000203]:V22 24-[000225]:V24 25-[000231]:V25 26-[000236]:V26 31-[000020]:V31 32-[000878]:V32 33-[000875]:V33 34-[000869]:V34 39-[000884]:V39 40-[000423]:V40 41-[000881]:V41 42-[000442]:V42 43-[000467]:V43 46-[000485]:V46 52-[000530]:V52 53-[000534]:V53 64-[000652]:V64 65-[000655]:V65 66-[000681]:V66 67-[000684]:V67 70-[000725]:V70 71-[000728]:V71 74-[000548]:V74 75-[000562]:V75 77-[000578]:V77 78-[000608]:V78 79-[000622]:V79 80-[000636]:V80 81-[000664]:V81 82-[000693]:V82 83-[000737]:V83 84-[000751]:V84 85-[000763]:V85 87-[000782]:V87 88-[000796]:V88 89-[000809]:V89 } Live vars: {V01 V02 V13 V20 V22 V24 V25 V26} => {V01 V02 V13 V20 V22 V24 V25} Live vars: {V01 V02 V13 V20 V22 V24 V25} => {V01 V02 V13 V20 V22 V24 V25 V29} Live vars: {V01 V02 V13 V20 V22 V24 V25 V29} => {V01 V02 V13 V20 V22 V24 V29} Copy Assertion for BB39 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 2-[000088]:V02 3-[000012]:V03 5-[000034]:V05 8-[000043]:V08 9-[000049]:V09 10-[000054]:V10 13-[000076]:V13 14-[000111]:V14 17-[000147]:V17 18-[000154]:V18 19-[000167]:V19 20-[000176]:V20 21-[000872]:V21 22-[000203]:V22 24-[000225]:V24 25-[000231]:V25 26-[000236]:V26 29-[000285]:V29 31-[000020]:V31 32-[000878]:V32 33-[000875]:V33 34-[000869]:V34 39-[000884]:V39 40-[000423]:V40 41-[000881]:V41 42-[000442]:V42 43-[000467]:V43 46-[000485]:V46 52-[000530]:V52 53-[000534]:V53 64-[000652]:V64 65-[000655]:V65 66-[000681]:V66 67-[000684]:V67 70-[000725]:V70 71-[000728]:V71 74-[000548]:V74 75-[000562]:V75 77-[000578]:V77 78-[000608]:V78 79-[000622]:V79 80-[000636]:V80 81-[000664]:V81 82-[000693]:V82 83-[000737]:V83 84-[000751]:V84 85-[000763]:V85 87-[000782]:V87 88-[000796]:V88 89-[000809]:V89 } Live vars: {V01 V02 V13 V20 V22 V24 V29 V37} => {V01 V02 V13 V20 V22 V24 V29} Live vars: {V01 V02 V13 V20 V22 V24 V29} => {V01 V02 V13 V20 V22 V24 V25 V29} Live vars: {V01 V02 V13 V20 V22 V24 V25 V29} => {V01 V02 V13 V20 V22 V25 V29} Live vars: {V01 V02 V13 V20 V22 V25 V29} => {V01 V02 V13 V20 V22 V25} Live vars: {V01 V02 V13 V20 V22 V25} => {V01 V02 V13 V20 V22 V24 V25} Copy Assertion for BB38 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 2-[000088]:V02 3-[000012]:V03 5-[000034]:V05 8-[000043]:V08 9-[000049]:V09 10-[000054]:V10 13-[000076]:V13 14-[000111]:V14 17-[000147]:V17 18-[000154]:V18 19-[000167]:V19 20-[000176]:V20 21-[000872]:V21 22-[000203]:V22 24-[000225]:V24 25-[000231]:V25 26-[000236]:V26 29-[000285]:V29 31-[000020]:V31 32-[000878]:V32 33-[000875]:V33 34-[000869]:V34 39-[000884]:V39 40-[000423]:V40 41-[000881]:V41 42-[000442]:V42 43-[000467]:V43 46-[000485]:V46 52-[000530]:V52 53-[000534]:V53 64-[000652]:V64 65-[000655]:V65 66-[000681]:V66 67-[000684]:V67 70-[000725]:V70 71-[000728]:V71 74-[000548]:V74 75-[000562]:V75 77-[000578]:V77 78-[000608]:V78 79-[000622]:V79 80-[000636]:V80 81-[000664]:V81 82-[000693]:V82 83-[000737]:V83 84-[000751]:V84 85-[000763]:V85 87-[000782]:V87 88-[000796]:V88 89-[000809]:V89 } Live vars: {V01 V02 V13 V20 V22 V24 V29} => {V01 V02 V13 V20 V22 V24 V29 V37} Copy Assertion for BB37 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 2-[000088]:V02 3-[000012]:V03 5-[000034]:V05 8-[000043]:V08 9-[000049]:V09 10-[000054]:V10 13-[000076]:V13 14-[000111]:V14 17-[000147]:V17 18-[000154]:V18 19-[000167]:V19 20-[000176]:V20 21-[000872]:V21 22-[000203]:V22 24-[000225]:V24 25-[000231]:V25 26-[000236]:V26 29-[000285]:V29 31-[000020]:V31 32-[000878]:V32 33-[000875]:V33 34-[000869]:V34 39-[000884]:V39 40-[000423]:V40 41-[000881]:V41 42-[000442]:V42 43-[000467]:V43 46-[000485]:V46 52-[000530]:V52 53-[000534]:V53 64-[000652]:V64 65-[000655]:V65 66-[000681]:V66 67-[000684]:V67 70-[000725]:V70 71-[000728]:V71 74-[000548]:V74 75-[000562]:V75 77-[000578]:V77 78-[000608]:V78 79-[000622]:V79 80-[000636]:V80 81-[000664]:V81 82-[000693]:V82 83-[000737]:V83 84-[000751]:V84 85-[000763]:V85 87-[000782]:V87 88-[000796]:V88 89-[000809]:V89 } Live vars: {V01 V02 V13 V20 V22 V24 V29} => {V01 V02 V13 V20 V22 V24 V29 V37} Copy Assertion for BB34 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 2-[000088]:V02 3-[000012]:V03 5-[000034]:V05 8-[000043]:V08 9-[000049]:V09 10-[000054]:V10 13-[000076]:V13 14-[000111]:V14 17-[000147]:V17 18-[000154]:V18 19-[000167]:V19 20-[000176]:V20 21-[000872]:V21 31-[000020]:V31 32-[000878]:V32 33-[000875]:V33 39-[000884]:V39 40-[000423]:V40 41-[000881]:V41 42-[000442]:V42 43-[000467]:V43 46-[000485]:V46 52-[000530]:V52 53-[000534]:V53 64-[000652]:V64 65-[000655]:V65 66-[000681]:V66 67-[000684]:V67 70-[000725]:V70 71-[000728]:V71 74-[000548]:V74 75-[000562]:V75 77-[000578]:V77 78-[000608]:V78 79-[000622]:V79 80-[000636]:V80 81-[000664]:V81 82-[000693]:V82 83-[000737]:V83 84-[000751]:V84 } Live vars: {V01 V02 V13 V19 V20 V21} => {V01 V02 V13 V20 V21} Live vars: {V01 V02 V13 V20 V21} => {V01 V02 V13 V20 V21 V34} Copy Assertion for BB33 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 2-[000088]:V02 3-[000012]:V03 5-[000034]:V05 8-[000043]:V08 9-[000049]:V09 10-[000054]:V10 13-[000076]:V13 14-[000111]:V14 17-[000147]:V17 18-[000154]:V18 19-[000167]:V19 20-[000176]:V20 21-[000872]:V21 31-[000020]:V31 32-[000878]:V32 33-[000875]:V33 39-[000884]:V39 40-[000423]:V40 41-[000881]:V41 42-[000442]:V42 43-[000467]:V43 46-[000485]:V46 52-[000530]:V52 53-[000534]:V53 64-[000652]:V64 65-[000655]:V65 66-[000681]:V66 67-[000684]:V67 70-[000725]:V70 71-[000728]:V71 74-[000548]:V74 75-[000562]:V75 77-[000578]:V77 78-[000608]:V78 79-[000622]:V79 80-[000636]:V80 81-[000664]:V81 82-[000693]:V82 83-[000737]:V83 84-[000751]:V84 } Live vars: {V01 V02 V13 V19 V20 V21} => {V01 V02 V13 V20 V21} Live vars: {V01 V02 V13 V20 V21} => {V01 V02 V13 V20 V21 V34} Copy Assertion for BB29 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 2-[000088]:V02 3-[000012]:V03 5-[000034]:V05 8-[000043]:V08 9-[000049]:V09 10-[000054]:V10 13-[000076]:V13 14-[000111]:V14 17-[000147]:V17 18-[000154]:V18 19-[000167]:V19 20-[000176]:V20 21-[000179]:V21 31-[000020]:V31 32-[000878]:V32 33-[000875]:V33 39-[000884]:V39 40-[000423]:V40 41-[000881]:V41 42-[000442]:V42 43-[000467]:V43 46-[000485]:V46 52-[000530]:V52 53-[000534]:V53 64-[000652]:V64 65-[000655]:V65 66-[000681]:V66 67-[000684]:V67 74-[000548]:V74 75-[000562]:V75 77-[000578]:V77 78-[000608]:V78 79-[000622]:V79 80-[000636]:V80 81-[000664]:V81 82-[000693]:V82 } VN based copy assertion for [000327] V21 @00000362 by [000176] V20 @00000362. N002 ( 3, 2) [000327] ------------ * LCL_VAR int V21 loc18 u:2 $362 copy propagated to: N002 ( 3, 2) [000327] ------------ * LCL_VAR int V20 loc17 u:2 $362 Copy Assertion for BB31 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 2-[000088]:V02 3-[000012]:V03 5-[000034]:V05 8-[000043]:V08 9-[000049]:V09 10-[000054]:V10 13-[000076]:V13 14-[000111]:V14 17-[000147]:V17 18-[000154]:V18 19-[000167]:V19 20-[000176]:V20 21-[000179]:V21 31-[000020]:V31 32-[000878]:V32 33-[000875]:V33 39-[000884]:V39 40-[000423]:V40 41-[000881]:V41 42-[000442]:V42 43-[000467]:V43 46-[000485]:V46 52-[000530]:V52 53-[000534]:V53 64-[000652]:V64 65-[000655]:V65 66-[000681]:V66 67-[000684]:V67 74-[000548]:V74 75-[000562]:V75 77-[000578]:V77 78-[000608]:V78 79-[000622]:V79 80-[000636]:V80 81-[000664]:V81 82-[000693]:V82 } Live vars: {V01 V02 V13 V19 V20 V21} => {V01 V02 V13 V19 V20} VN based copy assertion for [000330] V21 @00000362 by [000176] V20 @00000362. N001 ( 3, 2) [000330] ------------ * LCL_VAR int V21 loc18 u:2 (last use) $362 copy propagated to: N001 ( 3, 2) [000330] ------------ * LCL_VAR int V20 loc17 u:2 (last use) $362 Live vars: {V01 V02 V13 V19 V20} => {V01 V02 V13 V19 V20 V21} Copy Assertion for BB30 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 2-[000088]:V02 3-[000012]:V03 5-[000034]:V05 8-[000043]:V08 9-[000049]:V09 10-[000054]:V10 13-[000076]:V13 14-[000111]:V14 17-[000147]:V17 18-[000154]:V18 19-[000167]:V19 20-[000176]:V20 21-[000179]:V21 31-[000020]:V31 32-[000878]:V32 33-[000875]:V33 39-[000884]:V39 40-[000423]:V40 41-[000881]:V41 42-[000442]:V42 43-[000467]:V43 46-[000485]:V46 52-[000530]:V52 53-[000534]:V53 64-[000652]:V64 65-[000655]:V65 66-[000681]:V66 67-[000684]:V67 74-[000548]:V74 75-[000562]:V75 77-[000578]:V77 78-[000608]:V78 79-[000622]:V79 80-[000636]:V80 81-[000664]:V81 82-[000693]:V82 } Live vars: {V01 V02 V10 V13} => {V01 V10 V13} Live vars: {V01 V10 V13} => {V01 V13} Live vars: {V01 V13} => {V01} Live vars: {V01} => {} Live vars: {} => {V51} Copy Assertion for BB27 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 2-[000088]:V02 3-[000012]:V03 5-[000034]:V05 8-[000043]:V08 9-[000049]:V09 10-[000054]:V10 13-[000076]:V13 14-[000111]:V14 17-[000147]:V17 18-[000154]:V18 19-[000167]:V19 31-[000020]:V31 32-[000878]:V32 33-[000875]:V33 39-[000884]:V39 40-[000423]:V40 41-[000881]:V41 42-[000442]:V42 43-[000467]:V43 46-[000485]:V46 52-[000530]:V52 53-[000534]:V53 64-[000652]:V64 65-[000655]:V65 66-[000681]:V66 67-[000684]:V67 74-[000548]:V74 75-[000562]:V75 77-[000578]:V77 78-[000608]:V78 79-[000622]:V79 80-[000636]:V80 81-[000664]:V81 82-[000693]:V82 } Copy Assertion for BB25 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 2-[000088]:V02 3-[000012]:V03 5-[000034]:V05 8-[000043]:V08 9-[000049]:V09 10-[000054]:V10 13-[000076]:V13 14-[000111]:V14 17-[000147]:V17 18-[000154]:V18 31-[000020]:V31 32-[000878]:V32 39-[000884]:V39 40-[000423]:V40 41-[000881]:V41 42-[000442]:V42 43-[000467]:V43 46-[000485]:V46 52-[000530]:V52 53-[000534]:V53 64-[000652]:V64 65-[000655]:V65 66-[000681]:V66 67-[000684]:V67 74-[000548]:V74 75-[000562]:V75 77-[000578]:V77 78-[000608]:V78 79-[000622]:V79 80-[000636]:V80 81-[000664]:V81 82-[000693]:V82 } Live vars: {V01 V02 V03 V10 V13 V17 V18} => {V01 V02 V03 V10 V13 V17} Live vars: {V01 V02 V03 V10 V13 V17} => {V01 V02 V03 V10 V13} Live vars: {V01 V02 V03 V10 V13} => {V01 V02 V03 V10 V13 V33} Copy Assertion for BB24 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 2-[000088]:V02 3-[000012]:V03 5-[000034]:V05 8-[000043]:V08 9-[000049]:V09 10-[000054]:V10 13-[000076]:V13 14-[000111]:V14 17-[000147]:V17 18-[000154]:V18 31-[000020]:V31 32-[000878]:V32 39-[000884]:V39 40-[000423]:V40 41-[000881]:V41 42-[000442]:V42 43-[000467]:V43 46-[000485]:V46 52-[000530]:V52 53-[000534]:V53 64-[000652]:V64 65-[000655]:V65 66-[000681]:V66 67-[000684]:V67 74-[000548]:V74 75-[000562]:V75 77-[000578]:V77 78-[000608]:V78 79-[000622]:V79 80-[000636]:V80 81-[000664]:V81 82-[000693]:V82 } Live vars: {V01 V02 V03 V10 V13} => {V01 V02 V03 V10 V13 V33} Copy Assertion for BB21 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 2-[000088]:V02 3-[000012]:V03 5-[000034]:V05 8-[000043]:V08 9-[000049]:V09 10-[000054]:V10 13-[000076]:V13 14-[000111]:V14 31-[000020]:V31 32-[000878]:V32 39-[000884]:V39 40-[000423]:V40 41-[000881]:V41 42-[000442]:V42 52-[000530]:V52 53-[000534]:V53 74-[000548]:V74 75-[000562]:V75 77-[000578]:V77 } Live vars: {V01 V02 V03 V08 V09 V10 V13 V14 V52 V53} => {V01 V02 V03 V08 V09 V10 V13 V14 V38 V52 V53} Live vars: {V01 V02 V03 V08 V09 V10 V13 V14 V38 V52 V53} => {V01 V02 V03 V08 V09 V10 V13 V14 V52 V53} Copy Assertion for BB22 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 2-[000088]:V02 3-[000012]:V03 5-[000034]:V05 8-[000043]:V08 9-[000049]:V09 10-[000054]:V10 13-[000076]:V13 14-[000111]:V14 31-[000020]:V31 32-[000878]:V32 38-[000362]:V38 39-[000884]:V39 40-[000423]:V40 41-[000881]:V41 42-[000442]:V42 52-[000530]:V52 53-[000534]:V53 74-[000548]:V74 75-[000562]:V75 77-[000578]:V77 } Live vars: {V01 V02} => {V02} Live vars: {V02} => {} Copy Assertion for BB19 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 2-[000088]:V02 3-[000012]:V03 5-[000034]:V05 8-[000043]:V08 9-[000049]:V09 10-[000054]:V10 13-[000076]:V13 31-[000020]:V31 39-[000884]:V39 40-[000423]:V40 41-[000881]:V41 42-[000442]:V42 52-[000530]:V52 53-[000534]:V53 74-[000548]:V74 75-[000562]:V75 77-[000578]:V77 } Live vars: {V01 V02 V03 V08 V09 V10 V13 V52 V53} => {V01 V02 V03 V08 V09 V10 V13 V32 V52 V53} Copy Assertion for BB18 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 2-[000088]:V02 3-[000012]:V03 5-[000034]:V05 8-[000043]:V08 9-[000049]:V09 10-[000054]:V10 13-[000076]:V13 31-[000020]:V31 39-[000884]:V39 40-[000423]:V40 41-[000881]:V41 42-[000442]:V42 52-[000530]:V52 53-[000534]:V53 74-[000548]:V74 75-[000562]:V75 77-[000578]:V77 } Live vars: {V01 V02 V03 V08 V09 V10 V13 V52 V53} => {V01 V02 V03 V08 V09 V10 V13 V32 V52 V53} Copy Assertion for BB11 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 2-[000088]:V02 3-[000012]:V03 5-[000034]:V05 8-[000043]:V08 9-[000049]:V09 10-[000054]:V10 31-[000020]:V31 39-[000884]:V39 40-[000423]:V40 41-[000881]:V41 42-[000442]:V42 52-[000530]:V52 53-[000534]:V53 74-[000548]:V74 75-[000562]:V75 } Copy Assertion for BB13 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 2-[000088]:V02 3-[000012]:V03 5-[000034]:V05 8-[000043]:V08 9-[000049]:V09 10-[000054]:V10 31-[000020]:V31 39-[000884]:V39 40-[000423]:V40 41-[000881]:V41 42-[000442]:V42 52-[000530]:V52 53-[000534]:V53 74-[000548]:V74 75-[000562]:V75 } Live vars: {V01 V02 V03 V05 V08 V09 V10 V52 V53} => {V01 V02 V03 V08 V09 V10 V52 V53} Copy Assertion for BB12 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 2-[000088]:V02 3-[000012]:V03 5-[000034]:V05 8-[000043]:V08 9-[000049]:V09 10-[000054]:V10 31-[000020]:V31 39-[000884]:V39 40-[000423]:V40 41-[000881]:V41 42-[000442]:V42 52-[000530]:V52 53-[000534]:V53 74-[000548]:V74 75-[000562]:V75 } Live vars: {V01 V02} => {V02} Live vars: {V02} => {} Copy Assertion for BB09 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 2-[000088]:V02 3-[000012]:V03 31-[000020]:V31 39-[000884]:V39 40-[000423]:V40 42-[000442]:V42 52-[000530]:V52 53-[000534]:V53 } Live vars: {V01 V02 V03 V31 V52 V53} => {V01 V02 V03 V31 V41 V52 V53} Copy Assertion for BB08 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 2-[000088]:V02 3-[000012]:V03 31-[000020]:V31 39-[000884]:V39 40-[000423]:V40 42-[000442]:V42 52-[000530]:V52 53-[000534]:V53 } Live vars: {V01 V02 V03 V31 V42 V52 V53} => {V01 V02 V03 V31 V52 V53} Live vars: {V01 V02 V03 V31 V52 V53} => {V01 V02 V03 V31 V41 V52 V53} Copy Assertion for BB06 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 2-[000088]:V02 3-[000012]:V03 40-[000423]:V40 52-[000530]:V52 53-[000534]:V53 } Live vars: {V01 V02 V03 V52 V53} => {V01 V02 V03 V39 V52 V53} Copy Assertion for BB05 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 2-[000088]:V02 3-[000012]:V03 40-[000423]:V40 52-[000530]:V52 53-[000534]:V53 } Live vars: {V01 V02 V03 V40 V52 V53} => {V01 V02 V03 V52 V53} VN based copy assertion for [000419] V40 @00000280 by [000534] V53 @00000280. N001 ( 3, 2) [000419] ------------ * LCL_VAR int V40 tmp10 u:2 (last use) copy propagated to: N001 ( 3, 2) [000419] ------------ * LCL_VAR int V53 tmp23 u:2 (last use) Live vars: {V01 V02 V03 V52 V53} => {V01 V02 V03 V39 V52 V53} Copy Assertion for BB03 curSsaName stack: { 0-[000531]:V00 1-[000007]:V01 2-[000088]:V02 52-[000530]:V52 53-[000534]:V53 } Live vars: {V01 V02} => {V02} Live vars: {V02} => {} *************** Finishing PHASE VN based copy prop *************** Starting PHASE Optimize Valnum CSEs *************** In optOptimizeCSEs() Blocks/Trees at start of optOptimizeCSE phase ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0056] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..00D)-> BB04 ( cond ) i label target idxlen BB03 [0001] 1 BB02 0.50 [00D..017) (return) i hascall gcsafe BB04 [0002] 1 BB02 0.50 [017..065)-> BB06 ( cond ) i label target hascall gcsafe BB05 [0038] 1 BB04 0.50 [020..021)-> BB07 (always) i gcsafe BB06 [0039] 1 BB04 0.50 [020..021) i label target gcsafe BB07 [0040] 2 BB05,BB06 0.50 [000..000)-> BB09 ( cond ) i internal label target gcsafe idxlen BB08 [0043] 1 BB07 0.50 [000..000)-> BB10 (always) i internal gcsafe BB09 [0044] 1 BB07 0.50 [000..000) i internal label target gcsafe BB10 [0045] 2 BB08,BB09 0.50 [???..???)-> BB14 ( cond ) i internal label target hascall gcsafe idxlen BB11 [0003] 1 BB10 0.50 [065..070)-> BB13 ( cond ) i hascall gcsafe BB12 [0004] 1 BB11 0.50 [070..07A) (return) i hascall gcsafe BB13 [0005] 1 BB11 0.50 [07A..082) i label target hascall gcsafe BB14 [0006] 2 BB10,BB13 0.50 [082..092)-> BB16 ( cond ) i label target hascall gcsafe BB15 [0007] 1 BB14 0.50 [092..096)-> BB17 ( cond ) i gcsafe BB16 [0008] 2 BB14,BB15 0.50 [096..0A7)-> BB44 (always) i label target hascall gcsafe BB17 [0009] 1 BB15 0.50 [0A7..0B0)-> BB19 ( cond ) i label target gcsafe BB18 [0010] 1 BB17 0.50 [0B0..0B4)-> BB20 (always) i gcsafe BB19 [0011] 1 BB17 0.50 [0B4..0BE) i label target gcsafe BB20 [0012] 2 BB18,BB19 0.50 [0BE..0C4)-> BB23 ( cond ) i label target gcsafe BB21 [0013] 1 BB20 0.50 [0C4..0D9)-> BB23 ( cond ) i hascall gcsafe idxlen BB22 [0014] 1 BB21 0.50 [0D9..0E3) (return) i hascall gcsafe BB23 [0015] 2 BB20,BB21 0.50 [0E3..117)-> BB25 ( cond ) i label target hascall gcsafe BB24 [0016] 1 BB23 0.50 [117..11A)-> BB26 (always) i gcsafe BB25 [0017] 1 BB23 0.50 [11A..11F) i label target gcsafe BB26 [0018] 2 BB24,BB25 0.50 [11F..126)-> BB28 ( cond ) i label target gcsafe BB27 [0019] 1 BB26 0.50 [126..12F) i hascall gcsafe BB28 [0020] 2 BB26,BB27 0.50 [12F..13E)-> BB32 ( cond ) i label target gcsafe BB29 [0021] 1 BB28 0.50 [13E..144)-> BB31 ( cond ) i gcsafe BB30 [0022] 1 BB29 0.50 [144..155)-> BB44 (always) i hascall gcsafe BB31 [0023] 1 BB29 0.50 [155..15C) i label target gcsafe BB32 [0024] 2 BB28,BB31 0.50 [15C..167)-> BB34 ( cond ) i label target hascall gcsafe BB33 [0025] 1 BB32 0.50 [167..16B)-> BB35 (always) i gcsafe BB34 [0026] 1 BB32 0.50 [16B..16F) i label target gcsafe BB35 [0027] 2 BB33,BB34 0.50 [16F..1A4)-> BB40 ( cond ) i label target hascall gcsafe BB36 [0028] 1 BB35 0.50 [1A4..1AF)-> BB38 ( cond ) i gcsafe BB37 [0029] 1 BB36 0.50 [1AF..1C3)-> BB39 (always) i gcsafe BB38 [0030] 1 BB36 0.50 [1C3..1C4) i label target gcsafe BB39 [0031] 2 BB37,BB38 0.50 [1C4..1D0) i label target gcsafe BB40 [0032] 2 BB35,BB39 0.50 [1D0..1E7)-> BB42 ( cond ) i label target hascall gcsafe BB41 [0033] 1 BB40 0.50 [1E7..1EE)-> BB43 (always) i gcsafe BB42 [0034] 1 BB40 0.50 [1EE..1F2) i label target gcsafe BB43 [0035] 2 BB41,BB42 0.50 [1F2..202) i label target hascall gcsafe BB44 [0054] 3 BB16,BB30,BB43 0.50 [???..???) (return) keep internal target gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} ***** BB01 STMT00111 (IL ???... ???) N011 ( 7, 7) [000540] -A---------- * COMMA void N004 ( 3, 3) [000533] -A------R--- +--* ASG ref N003 ( 1, 1) [000530] D------N---- | +--* LCL_VAR ref V52 tmp22 d:2 N002 ( 3, 2) [000532] n----------- | \--* IND ref N001 ( 1, 1) [000531] ------------ | \--* LCL_VAR byref V00 arg0 u:1 Zero Fseq[Mantissa] $80 N010 ( 4, 4) [000539] -A------R--- \--* ASG int N009 ( 1, 1) [000534] D------N---- +--* LCL_VAR int V53 tmp23 d:2 N008 ( 4, 4) [000538] n----------- \--* IND int N007 ( 2, 2) [000537] -------N---- \--* ADD byref $200 N005 ( 1, 1) [000535] ------------ +--* LCL_VAR byref V00 arg0 u:1 (last use) $80 N006 ( 1, 1) [000536] ------------ \--* CNS_INT long 8 Fseq[Exponent] $101 ------------ BB02 [000..00D) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00000 (IL 0x000...0x00B) N005 ( 7, 7) [000006] ---XG------- * JTRUE void N004 ( 5, 5) [000005] J--XG--N---- \--* NE int N002 ( 3, 3) [000003] ---XG------- +--* ARR_LENGTH int N001 ( 1, 1) [000002] ------------ | \--* LCL_VAR ref V52 tmp22 u:2 N003 ( 1, 1) [000004] ------------ \--* CNS_INT int 0 $40 ------------ BB03 [00D..017) (return), preds={BB02} succs={} ***** BB03 STMT00087 (IL 0x00D...0x014) N006 ( 25, 13) [000403] -ACXG---R--- * ASG long $VN.Void N005 ( 3, 2) [000402] *--X---N---- +--* IND long $459 N004 ( 1, 1) [000399] ------------ | \--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N003 ( 21, 10) [000401] --CXG------- \--* CALLV ind long FloatingPointType.get_Zero $459 N002 ( 1, 1) [000400] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 ***** BB03 STMT00107 (IL ???... ???) N002 ( 2, 2) [000520] ------------ * RETURN int $5cb N001 ( 1, 1) [000404] ------------ \--* CNS_INT int 1 $41 ------------ BB04 [017..065) -> BB06 (cond), preds={BB02} succs={BB05,BB06} ***** BB04 STMT00002 (IL ???... ???) N010 ( 30, 19) [000013] -ACXG---R--- * ASG int $348 N009 ( 3, 2) [000012] D------N---- +--* LCL_VAR int V03 loc0 d:2 $348 N008 ( 26, 16) [000011] --CXG------- \--* ADD int $348 N006 ( 24, 14) [000409] --CXG------- +--* CAST int <- ushort <- int $347 N005 ( 23, 12) [000408] --CXG------- | \--* ADD int $346 N003 ( 21, 10) [000406] --CXG------- | +--* CALLV ind int FloatingPointType.get_DenormalMantissaBits $282 N002 ( 1, 1) [000007] ------------ this in rcx | | \--* LCL_VAR ref V01 arg1 u:1 $c0 N004 ( 1, 1) [000407] ------------ | \--* CNS_INT int 1 $41 N007 ( 1, 1) [000010] ------------ \--* CNS_INT int 1 $41 ***** BB04 STMT00092 (IL 0x020... ???) N003 ( 5, 4) [000424] -A--G---R--- * ASG int N002 ( 3, 2) [000423] D------N---- +--* LCL_VAR int V40 tmp10 d:2 N001 ( 1, 1) [000017] ------------ \--* LCL_VAR int V53 tmp23 u:2 ***** BB04 STMT00089 (IL 0x020... ???) N004 ( 5, 5) [000414] ------------ * JTRUE void N003 ( 3, 3) [000413] J------N---- \--* LE int N001 ( 1, 1) [000412] ------------ +--* LCL_VAR int V40 tmp10 u:2 N002 ( 1, 1) [000411] ------------ \--* CNS_INT int 0 $40 ------------ BB05 [020..021) -> BB07 (always), preds={BB04} succs={BB07} ***** BB05 STMT00091 (IL 0x020... ???) N003 ( 7, 5) [000421] -A------R--- * ASG int N002 ( 3, 2) [000420] D------N---- +--* LCL_VAR int V39 tmp9 d:4 N001 ( 3, 2) [000419] ------------ \--* LCL_VAR int V53 tmp23 u:2 (last use) ------------ BB06 [020..021), preds={BB04} succs={BB07} ***** BB06 STMT00090 (IL 0x020... ???) N003 ( 5, 4) [000417] -A------R--- * ASG int $40 N002 ( 3, 2) [000416] D------N---- +--* LCL_VAR int V39 tmp9 d:3 $40 N001 ( 1, 1) [000415] ------------ \--* CNS_INT int 0 $40 ------------ BB07 [000..000) -> BB09 (cond), preds={BB05,BB06} succs={BB08,BB09} ***** BB07 STMT00122 (IL ???... ???) N005 ( 0, 0) [000886] -A------R--- * ASG int N004 ( 0, 0) [000884] D------N---- +--* LCL_VAR int V39 tmp9 d:2 N003 ( 0, 0) [000885] ------------ \--* PHI int N001 ( 0, 0) [000909] ------------ pred BB05 +--* PHI_ARG int V39 tmp9 u:4 N002 ( 0, 0) [000908] ------------ pred BB06 \--* PHI_ARG int V39 tmp9 u:3 $40 ***** BB07 STMT00004 (IL ???... ???) N003 ( 3, 3) [000021] -A------R--- * ASG int $241 N002 ( 1, 1) [000020] D------N---- +--* LCL_VAR int V31 tmp1 d:2 $241 N001 ( 3, 2) [000422] ------------ \--* LCL_VAR int V39 tmp9 u:2 $241 ***** BB07 STMT00096 (IL ???... ???) N004 ( 3, 3) [000443] -A-XG---R--- * ASG int N003 ( 1, 1) [000442] D------N---- +--* LCL_VAR int V42 tmp12 d:2 N002 ( 3, 3) [000429] ---XG------- \--* ARR_LENGTH int N001 ( 1, 1) [000428] ------------ \--* LCL_VAR ref V52 tmp22 u:2 ***** BB07 STMT00093 (IL ???... ???) N004 ( 7, 6) [000433] ------------ * JTRUE void N003 ( 5, 4) [000432] N------N-U-- \--* LE int N001 ( 3, 2) [000023] ------------ +--* LCL_VAR int V31 tmp1 u:2 (last use) $241 N002 ( 1, 1) [000431] ------------ \--* LCL_VAR int V42 tmp12 u:2 ------------ BB08 [000..000) -> BB10 (always), preds={BB07} succs={BB10} ***** BB08 STMT00095 (IL ???... ???) N003 ( 1, 3) [000440] -A------R--- * ASG int N002 ( 1, 1) [000439] D------N---- +--* LCL_VAR int V41 tmp11 d:4 N001 ( 1, 1) [000438] ------------ \--* LCL_VAR int V42 tmp12 u:2 (last use) ------------ BB09 [000..000), preds={BB07} succs={BB10} ***** BB09 STMT00094 (IL ???... ???) N003 ( 1, 3) [000436] -A------R--- * ASG int $241 N002 ( 1, 1) [000435] D------N---- +--* LCL_VAR int V41 tmp11 d:3 $241 N001 ( 1, 1) [000434] ------------ \--* LCL_VAR int V31 tmp1 u:2 $241 ------------ BB10 [???..???) -> BB14 (cond), preds={BB08,BB09} succs={BB11,BB14} ***** BB10 STMT00121 (IL ???... ???) N005 ( 0, 0) [000883] -A------R--- * ASG int N004 ( 0, 0) [000881] D------N---- +--* LCL_VAR int V41 tmp11 d:2 N003 ( 0, 0) [000882] ------------ \--* PHI int N001 ( 0, 0) [000907] ------------ pred BB08 +--* PHI_ARG int V41 tmp11 u:4 N002 ( 0, 0) [000906] ------------ pred BB09 \--* PHI_ARG int V41 tmp11 u:3 $241 ***** BB10 STMT00008 (IL ???...0x03C) N005 ( 7, 6) [000035] -A------R--- * ASG int $34e N004 ( 3, 2) [000034] D------N---- +--* LCL_VAR int V05 loc2 d:2 $34e N003 ( 3, 3) [000033] ------------ \--* SUB int $34e N001 ( 1, 1) [000022] ------------ +--* LCL_VAR int V31 tmp1 u:2 (last use) $241 N002 ( 1, 1) [000032] ------------ \--* LCL_VAR int V41 tmp11 u:2 $242 ***** BB10 STMT00011 (IL 0x042...0x044) N003 ( 5, 4) [000044] -A------R--- * ASG int $242 N002 ( 3, 2) [000043] D------N---- +--* LCL_VAR int V08 loc5 d:2 $242 N001 ( 1, 1) [000042] ------------ \--* LCL_VAR int V41 tmp11 u:2 $242 ***** BB10 STMT00013 (IL ???... ???) N004 ( 7, 6) [000050] -A-XG---R--- * ASG int N003 ( 3, 2) [000049] D------N---- +--* LCL_VAR int V09 loc6 d:2 N002 ( 3, 3) [000448] ---XG------- \--* ARR_LENGTH int N001 ( 1, 1) [000447] ------------ \--* LCL_VAR ref V52 tmp22 u:2 ***** BB10 STMT00014 (IL 0x04F...0x054) N005 ( 5, 4) [000055] -A------R--- * ASG int N004 ( 1, 1) [000054] D------N---- +--* LCL_VAR int V10 loc7 d:2 N003 ( 5, 4) [000053] ------------ \--* SUB int N001 ( 3, 2) [000051] ------------ +--* LCL_VAR int V09 loc6 u:2 N002 ( 1, 1) [000052] ------------ \--* LCL_VAR int V08 loc5 u:2 $242 ***** BB10 STMT00016 (IL ???... ???) N028 ( 49, 35) [000059] SACXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger $VN.Void N004 ( 7, 6) [000563] -A------R-L- arg0 SETUP +--* ASG long $400 N003 ( 3, 2) [000562] D------N---- | +--* LCL_VAR long V75 tmp45 d:2 $400 N002 ( 3, 3) [000064] ------------ | \--* ADDR long $400 N001 ( 3, 2) [000063] ----G--N---- | \--* LCL_VAR struct(AX)(P) V11 loc8 | \--* ref V11._bits (offs=0x00) -> V54 tmp24 | \--* int V11._sign (offs=0x08) -> V55 tmp25 $3c0 N020 ( 14, 13) [000561] -A--------L- arg1 SETUP +--* COMMA void $VN.Void N013 ( 8, 7) [000554] -A---------- | +--* COMMA void $VN.Void N008 ( 3, 3) [000549] -A------R--- | | +--* ASG byref $401 N007 ( 1, 1) [000548] D------N---- | | | +--* LCL_VAR byref V74 tmp44 d:2 $401 N006 ( 3, 3) [000546] ------------ | | | \--* ADDR byref $401 N005 ( 3, 2) [000547] -------N---- | | | \--* LCL_VAR struct(AX) V73 tmp43 $3c1 N012 ( 5, 4) [000553] -A---------- | | \--* ASG ref $VN.Void N010 ( 3, 2) [000551] *------N---- | | +--* IND ref N009 ( 1, 1) [000550] ------------ | | | \--* LCL_VAR byref V74 tmp44 u:2 Zero Fseq[Mantissa] $401 N011 ( 1, 1) [000552] -------N---- | | \--* LCL_VAR ref V52 tmp22 u:2 N019 ( 6, 6) [000560] -A---------- | \--* ASG int $VN.Void N017 ( 4, 4) [000558] *------N---- | +--* IND int N016 ( 2, 2) [000557] -------N---- | | \--* ADD byref $203 N014 ( 1, 1) [000555] ------------ | | +--* LCL_VAR byref V74 tmp44 u:2 (last use) $401 N015 ( 1, 1) [000556] ------------ | | \--* CNS_INT long 8 Fseq[Exponent] $101 N018 ( 1, 1) [000559] -------N---- | \--* LCL_VAR int V53 tmp23 u:2 N023 ( 3, 2) [000564] ------------ arg0 in rcx +--* LCL_VAR long V75 tmp45 u:2 (last use) $400 N025 ( 3, 3) [000566] ------------ arg1 in rdx +--* ADDR byref $403 N024 ( 3, 2) [000565] -------N---- | \--* LCL_VAR struct(AX) V73 tmp43 $3c2 N026 ( 1, 1) [000058] ------------ arg3 in r9 +--* LCL_VAR int V08 loc5 u:2 (last use) $242 N027 ( 1, 1) [000057] ------------ arg2 in r8 \--* CNS_INT int 0 $40 ***** BB10 STMT00017 (IL 0x061...0x063) N004 ( 7, 6) [000068] ------------ * JTRUE void N003 ( 5, 4) [000067] N------N---- \--* EQ int $351 N001 ( 3, 2) [000065] ------------ +--* LCL_VAR int V05 loc2 u:2 $34e N002 ( 1, 1) [000066] ------------ \--* CNS_INT int 0 $40 ------------ BB11 [065..070) -> BB13 (cond), preds={BB10} succs={BB12,BB13} ***** BB11 STMT00083 (IL ???... ???) N008 ( 23, 17) [000387] --CXG------- * JTRUE void N007 ( 21, 15) [000386] J-CXG--N---- \--* GE int $352 N004 ( 16, 10) [000385] --CXG------- +--* CAST long <- int $480 N003 ( 15, 8) [000383] --CXG------- | \--* CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent $291 N002 ( 1, 1) [000382] ------------ this in rcx | \--* LCL_VAR ref V01 arg1 u:1 $c0 N006 ( 4, 4) [000381] ---------U-- \--* CAST long <- ulong <- uint $481 N005 ( 3, 2) [000380] ------------ \--* LCL_VAR int V05 loc2 u:2 $34e ------------ BB12 [070..07A) (return), preds={BB11} succs={} ***** BB12 STMT00085 (IL 0x070...0x077) N006 ( 25, 13) [000396] -ACXG---R--- * ASG long $VN.Void N005 ( 3, 2) [000395] *--X---N---- +--* IND long $458 N004 ( 1, 1) [000392] ------------ | \--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N003 ( 21, 10) [000394] --CXG------- \--* CALLV ind long FloatingPointType.get_Infinity $458 N002 ( 1, 1) [000393] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 ***** BB12 STMT00108 (IL ???... ???) N002 ( 2, 2) [000521] ------------ * RETURN int $5ca N001 ( 1, 1) [000397] ------------ \--* CNS_INT int 3 $48 ------------ BB13 [07A..082), preds={BB11} succs={BB14} ***** BB13 STMT00084 (IL 0x07A...0x07D) N006 ( 20, 12) [000391] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen $VN.Void N004 ( 3, 3) [000389] ------------ arg0 in rcx +--* ADDR long $404 N003 ( 3, 2) [000388] ----G--N---- | \--* LCL_VAR struct(AX)(P) V11 loc8 | \--* ref V11._bits (offs=0x00) -> V54 tmp24 | \--* int V11._sign (offs=0x08) -> V55 tmp25 $3c3 N005 ( 3, 2) [000390] ------------ arg1 in rdx \--* LCL_VAR int V05 loc2 u:2 (last use) $34e ------------ BB14 [082..092) -> BB16 (cond), preds={BB10,BB13} succs={BB15,BB16} ***** BB14 STMT00019 (IL ???... ???) N023 ( 41, 28) [000077] -ACXG---R--- * ASG int $293 N022 ( 1, 1) [000076] D------N---- +--* LCL_VAR int V13 loc10 d:2 $293 N021 ( 41, 28) [000072] -ACXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $293 N016 ( 18, 15) [000591] -A--G-----L- arg0 SETUP +--* COMMA void $VN.Void N009 ( 10, 8) [000584] -A--G------- | +--* COMMA void $VN.Void N004 ( 3, 3) [000579] -A------R--- | | +--* ASG byref $405 N003 ( 1, 1) [000578] D------N---- | | | +--* LCL_VAR byref V77 tmp47 d:2 $405 N002 ( 3, 3) [000576] ------------ | | | \--* ADDR byref $405 N001 ( 3, 2) [000577] -------N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 $3c4 N008 ( 7, 5) [000583] -A--G------- | | \--* ASG ref $VN.Void N006 ( 3, 2) [000581] *------N---- | | +--* IND ref $181 N005 ( 1, 1) [000580] ------------ | | | \--* LCL_VAR byref V77 tmp47 u:2 Zero Fseq[_bits] $405 N007 ( 3, 2) [000582] ----G--N---- | | \--* LCL_VAR ref (AX) V54 tmp24 $181 N015 ( 8, 7) [000590] -A--G------- | \--* ASG int $VN.Void N013 ( 4, 4) [000588] *------N---- | +--* IND int $243 N012 ( 2, 2) [000587] -------N---- | | \--* ADD byref $206 N010 ( 1, 1) [000585] ------------ | | +--* LCL_VAR byref V77 tmp47 u:2 (last use) $405 N011 ( 1, 1) [000586] ------------ | | \--* CNS_INT long 8 Fseq[_sign] $101 N014 ( 3, 2) [000589] ----G--N---- | \--* LCL_VAR int (AX) V55 tmp25 $243 N019 ( 3, 3) [000593] ------------ arg0 in rcx +--* ADDR byref $407 N018 ( 3, 2) [000592] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 $3c5 N020 ( 3, 3) [000071] ------------ arg1 in rdx \--* LCL_VAR_ADDR long V12 loc9 $443 ***** BB14 STMT00020 (IL 0x08D...0x090) N004 ( 7, 6) [000081] ------------ * JTRUE void N003 ( 5, 4) [000080] N------N-U-- \--* GE int $353 N001 ( 1, 1) [000078] ------------ +--* LCL_VAR int V13 loc10 u:2 $293 N002 ( 3, 2) [000079] ------------ \--* LCL_VAR int V03 loc0 u:2 $348 ------------ BB15 [092..096) -> BB17 (cond), preds={BB14} succs={BB16,BB17} ***** BB15 STMT00022 (IL 0x092...0x094) N004 ( 5, 5) [000094] ------------ * JTRUE void N003 ( 3, 3) [000093] J------N---- \--* NE int N001 ( 1, 1) [000091] ------------ +--* LCL_VAR int V10 loc7 u:2 N002 ( 1, 1) [000092] ------------ \--* CNS_INT int 0 $40 ------------ BB16 [096..0A7) -> BB44 (always), preds={BB14,BB15} succs={BB44} ***** BB16 STMT00021 (IL 0x096...0x0A6) N014 ( 29, 17) [000600] -ACXG---R--- * ASG int $5c7 N013 ( 1, 1) [000599] D------N---- +--* LCL_VAR int V51 tmp21 d:3 $5c7 N012 ( 29, 17) [000089] --CXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits $5c7 N005 ( 1, 1) [000088] ------------ arg4 out+20 +--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N008 ( 6, 3) [000086] N----------- arg2 in r8 +--* NE int N006 ( 1, 1) [000084] ------------ | +--* LCL_VAR int V10 loc7 u:2 (last use) N007 ( 1, 1) [000085] ------------ | \--* CNS_INT int 0 $40 N009 ( 3, 2) [000082] ----G------- arg0 in rcx +--* LCL_VAR ref (AX) V12 loc9 $18d N010 ( 1, 1) [000083] ------------ arg1 in rdx +--* LCL_VAR int V13 loc10 u:2 (last use) $293 N011 ( 1, 1) [000087] ------------ arg3 in r9 \--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 ------------ BB17 [0A7..0B0) -> BB19 (cond), preds={BB15} succs={BB18,BB19} ***** BB17 STMT00023 (IL 0x0A7...0x0AE) N004 ( 5, 5) [000100] ----G------- * JTRUE void N003 ( 3, 3) [000099] J---G--N---- \--* LT int N001 ( 1, 1) [000097] ------------ +--* LCL_VAR int V53 tmp23 u:2 N002 ( 1, 1) [000098] ------------ \--* CNS_INT int 0 $40 ------------ BB18 [0B0..0B4) -> BB20 (always), preds={BB17} succs={BB20} ***** BB18 STMT00081 (IL 0x0B0...0x0B2) N003 ( 5, 4) [000378] -A------R--- * ASG int N002 ( 3, 2) [000377] D------N---- +--* LCL_VAR int V32 tmp2 d:4 N001 ( 1, 1) [000376] ------------ \--* LCL_VAR int V10 loc7 u:2 ------------ BB19 [0B4..0BE), preds={BB17} succs={BB20} ***** BB19 STMT00024 (IL 0x0B4...0x0BD) N005 ( 7, 6) [000108] -A--G---R--- * ASG int N004 ( 3, 2) [000107] D------N---- +--* LCL_VAR int V32 tmp2 d:3 N003 ( 3, 3) [000106] ----G------- \--* SUB int N001 ( 1, 1) [000101] ------------ +--* LCL_VAR int V10 loc7 u:2 N002 ( 1, 1) [000104] ------------ \--* LCL_VAR int V53 tmp23 u:2 ------------ BB20 [0BE..0C4) -> BB23 (cond), preds={BB18,BB19} succs={BB21,BB23} ***** BB20 STMT00120 (IL ???... ???) N005 ( 0, 0) [000880] -A------R--- * ASG int N004 ( 0, 0) [000878] D------N---- +--* LCL_VAR int V32 tmp2 d:2 N003 ( 0, 0) [000879] ------------ \--* PHI int N001 ( 0, 0) [000905] ------------ pred BB18 +--* PHI_ARG int V32 tmp2 u:4 N002 ( 0, 0) [000904] ------------ pred BB19 \--* PHI_ARG int V32 tmp2 u:3 ***** BB20 STMT00025 (IL ???...0x0BE) N003 ( 7, 5) [000112] -A------R--- * ASG int $244 N002 ( 3, 2) [000111] D------N---- +--* LCL_VAR int V14 loc11 d:2 $244 N001 ( 3, 2) [000110] ------------ \--* LCL_VAR int V32 tmp2 u:2 (last use) $244 ***** BB20 STMT00026 (IL 0x0C0...0x0C2) N004 ( 5, 5) [000116] ------------ * JTRUE void N003 ( 3, 3) [000115] J------N---- \--* NE int $35a N001 ( 1, 1) [000113] ------------ +--* LCL_VAR int V13 loc10 u:2 $293 N002 ( 1, 1) [000114] ------------ \--* CNS_INT int 0 $40 ------------ BB21 [0C4..0D9) -> BB23 (cond), preds={BB20} succs={BB22,BB23} ***** BB21 STMT00077 (IL ???... ???) N008 ( 13, 13) [000363] -A-XG---R--- * ASG long N007 ( 3, 2) [000362] D------N---- +--* LCL_VAR long V38 tmp8 d:2 N006 ( 9, 10) [000359] ---XG---R--- \--* SUB long N005 ( 4, 4) [000353] ---------U-- +--* CAST long <- ulong <- uint $486 N004 ( 3, 2) [000352] ------------ | \--* LCL_VAR int V14 loc11 u:2 $244 N003 ( 4, 5) [000358] ---XG------- \--* CAST long <- int N002 ( 3, 3) [000456] ---XG------- \--* ARR_LENGTH int N001 ( 1, 1) [000455] ------------ \--* LCL_VAR ref V52 tmp22 u:2 ***** BB21 STMT00078 (IL ???... ???) N007 ( 22, 15) [000368] --CXG------- * JTRUE void N006 ( 20, 13) [000367] J-CXG--N---- \--* GE int N004 ( 16, 10) [000366] --CXG------- +--* CAST long <- int $48b N003 ( 15, 8) [000361] --CXG------- | \--* CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent $298 N002 ( 1, 1) [000360] ------------ this in rcx | \--* LCL_VAR ref V01 arg1 u:1 $c0 N005 ( 3, 2) [000364] ------------ \--* LCL_VAR long V38 tmp8 u:2 (last use) ------------ BB22 [0D9..0E3) (return), preds={BB21} succs={} ***** BB22 STMT00079 (IL 0x0D9...0x0E0) N006 ( 25, 13) [000373] -ACXG---R--- * ASG long $VN.Void N005 ( 3, 2) [000372] *--X---N---- +--* IND long $457 N004 ( 1, 1) [000369] ------------ | \--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N003 ( 21, 10) [000371] --CXG------- \--* CALLV ind long FloatingPointType.get_Zero $457 N002 ( 1, 1) [000370] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 ***** BB22 STMT00110 (IL ???... ???) N002 ( 2, 2) [000524] ------------ * RETURN int $5c4 N001 ( 1, 1) [000374] ------------ \--* CNS_INT int 2 $42 ------------ BB23 [0E3..117) -> BB25 (cond), preds={BB20,BB21} succs={BB24,BB25} ***** BB23 STMT00028 (IL ???... ???) N028 ( 53, 37) [000120] SACXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger $VN.Void N004 ( 7, 6) [000623] -A------R-L- arg0 SETUP +--* ASG long $408 N003 ( 3, 2) [000622] D------N---- | +--* LCL_VAR long V79 tmp49 d:2 $408 N002 ( 3, 3) [000125] ------------ | \--* ADDR long $408 N001 ( 3, 2) [000124] ----G--N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 $3c6 N020 ( 14, 13) [000621] -A--------L- arg1 SETUP +--* COMMA void $VN.Void N013 ( 8, 7) [000614] -A---------- | +--* COMMA void $VN.Void N008 ( 3, 3) [000609] -A------R--- | | +--* ASG byref $409 N007 ( 1, 1) [000608] D------N---- | | | +--* LCL_VAR byref V78 tmp48 d:2 $409 N006 ( 3, 3) [000606] ------------ | | | \--* ADDR byref $409 N005 ( 3, 2) [000607] ----G--N---- | | | \--* LCL_VAR struct(AX) V73 tmp43 $3c7 N012 ( 5, 4) [000613] -A---------- | | \--* ASG ref $VN.Void N010 ( 3, 2) [000611] *------N---- | | +--* IND ref N009 ( 1, 1) [000610] ------------ | | | \--* LCL_VAR byref V78 tmp48 u:2 Zero Fseq[Mantissa] $409 N011 ( 1, 1) [000612] -------N---- | | \--* LCL_VAR ref V52 tmp22 u:2 (last use) N019 ( 6, 6) [000620] -A---------- | \--* ASG int $VN.Void N017 ( 4, 4) [000618] *------N---- | +--* IND int N016 ( 2, 2) [000617] -------N---- | | \--* ADD byref $209 N014 ( 1, 1) [000615] ------------ | | +--* LCL_VAR byref V78 tmp48 u:2 (last use) $409 N015 ( 1, 1) [000616] ------------ | | \--* CNS_INT long 8 Fseq[Exponent] $101 N018 ( 1, 1) [000619] -------N---- | \--* LCL_VAR int V53 tmp23 u:2 (last use) N023 ( 3, 2) [000624] ------------ arg0 in rcx +--* LCL_VAR long V79 tmp49 u:2 (last use) $408 N025 ( 3, 3) [000626] ------------ arg1 in rdx +--* ADDR byref $40b N024 ( 3, 2) [000625] -------N---- | \--* LCL_VAR struct(AX) V73 tmp43 $3c8 N026 ( 3, 2) [000118] ------------ arg2 in r8 +--* LCL_VAR int V08 loc5 u:2 (last use) $242 N027 ( 3, 2) [000119] ------------ arg3 in r9 \--* LCL_VAR int V09 loc6 u:2 (last use) ***** BB23 STMT00029 (IL 0x0EF...0x0F4) N005 ( 17, 21) [000133] H-CXG------- * CALL help long HELPER.CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE $48d N003 ( 2, 10) [000131] ------------ arg0 in rcx +--* CNS_INT long 0x7ff815262aa0 $102 N004 ( 1, 4) [000132] ------------ arg1 in rdx \--* CNS_INT int 173 $58 ***** BB23 STMT00030 (IL ???... ???) N018 ( 21, 26) [000649] -A-XG------- * COMMA void N011 ( 13, 19) [000642] -A-XG------- +--* COMMA void N006 ( 6, 14) [000637] -A--G---R--- | +--* ASG byref N005 ( 1, 1) [000636] D------N---- | | +--* LCL_VAR byref V80 tmp50 d:2 N004 ( 6, 14) [000632] ----G------- | | \--* ADD byref N002 ( 4, 12) [000633] n---G------- | | +--* IND ref N001 ( 2, 10) [000634] I----------- | | | \--* CNS_INT(h) long 0xd1ffab1e static Fseq[BigOne] $4c2 N003 ( 1, 1) [000635] ------------ | | \--* CNS_INT long 8 Fseq[#FirstElem] $101 N010 ( 7, 5) [000641] -A-XG---R--- | \--* ASG ref N009 ( 3, 2) [000638] D---G--N---- | +--* LCL_VAR ref (AX) V58 tmp28 N008 ( 3, 2) [000640] ---X-------- | \--* IND ref N007 ( 1, 1) [000639] ------------ | \--* LCL_VAR byref V80 tmp50 u:2 Zero Fseq[_bits] N017 ( 8, 7) [000648] -A-XG---R--- \--* ASG int N016 ( 3, 2) [000643] D---G--N---- +--* LCL_VAR int (AX) V59 tmp29 N015 ( 4, 4) [000647] ---X-------- \--* IND int N014 ( 2, 2) [000646] -------N---- \--* ADD byref N012 ( 1, 1) [000644] ------------ +--* LCL_VAR byref V80 tmp50 u:2 (last use) N013 ( 1, 1) [000645] ------------ \--* CNS_INT long 8 Fseq[_sign] $101 ***** BB23 STMT00031 (IL 0x0F6...0x106) N006 ( 20, 12) [000141] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen $VN.Void N004 ( 3, 3) [000139] ------------ arg0 in rcx +--* ADDR long $40d N003 ( 3, 2) [000138] ----G--N---- | \--* LCL_VAR struct(AX)(P) V16 loc13 | \--* ref V16._bits (offs=0x00) -> V58 tmp28 | \--* int V16._sign (offs=0x08) -> V59 tmp29 $3c9 N005 ( 3, 2) [000140] ------------ arg1 in rdx \--* LCL_VAR int V14 loc11 u:2 (last use) $244 ***** BB23 STMT00099 (IL 0x0FF... ???) N007 ( 14, 10) [000658] -A--G------- * COMMA void $246 N003 ( 7, 5) [000654] -A--G---R--- +--* ASG ref $184 N002 ( 3, 2) [000652] D------N---- | +--* LCL_VAR ref V64 tmp34 d:2 $184 N001 ( 3, 2) [000653] ----G--N---- | \--* LCL_VAR ref (AX) V56 tmp26 $184 N006 ( 7, 5) [000657] -A--G---R--- \--* ASG int $246 N005 ( 3, 2) [000655] D------N---- +--* LCL_VAR int V65 tmp35 d:2 $246 N004 ( 3, 2) [000656] ----G--N---- \--* LCL_VAR int (AX) V57 tmp27 $246 ***** BB23 STMT00098 (IL 0x0FF... ???) N023 ( 45, 31) [000468] -ACXG---R--- * ASG int $29f N022 ( 3, 2) [000467] D------N---- +--* LCL_VAR int V43 tmp13 d:2 $29f N021 ( 41, 28) [000463] -ACXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $29f N016 ( 18, 15) [000677] -A--------L- arg0 SETUP +--* COMMA void $VN.Void N009 ( 10, 8) [000670] -A---------- | +--* COMMA void $VN.Void N004 ( 3, 3) [000665] -A------R--- | | +--* ASG byref $40e N003 ( 1, 1) [000664] D------N---- | | | +--* LCL_VAR byref V81 tmp51 d:2 $40e N002 ( 3, 3) [000662] ------------ | | | \--* ADDR byref $40e N001 ( 3, 2) [000663] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 $3ca N008 ( 7, 5) [000669] -A---------- | | \--* ASG ref $VN.Void N006 ( 3, 2) [000667] *------N---- | | +--* IND ref $184 N005 ( 1, 1) [000666] ------------ | | | \--* LCL_VAR byref V81 tmp51 u:2 Zero Fseq[_bits] $40e N007 ( 3, 2) [000668] -------N---- | | \--* LCL_VAR ref V64 tmp34 u:2 (last use) $184 N015 ( 8, 7) [000676] -A---------- | \--* ASG int $VN.Void N013 ( 4, 4) [000674] *------N---- | +--* IND int $246 N012 ( 2, 2) [000673] -------N---- | | \--* ADD byref $211 N010 ( 1, 1) [000671] ------------ | | +--* LCL_VAR byref V81 tmp51 u:2 (last use) $40e N011 ( 1, 1) [000672] ------------ | | \--* CNS_INT long 8 Fseq[_sign] $101 N014 ( 3, 2) [000675] -------N---- | \--* LCL_VAR int V65 tmp35 u:2 (last use) $246 N019 ( 3, 3) [000679] ------------ arg0 in rcx +--* ADDR byref $410 N018 ( 3, 2) [000678] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 $3cb N020 ( 3, 3) [000462] ------------ arg1 in rdx \--* LCL_VAR_ADDR long V45 tmp15 $449 ***** BB23 STMT00100 (IL 0x0FF... ???) N003 ( 5, 4) [000475] -A--G---R--- * ASG ref $VN.Null N002 ( 3, 2) [000474] D---G--N---- +--* LCL_VAR ref (AX) V45 tmp15 N001 ( 1, 1) [000473] ------------ \--* CNS_INT ref null $VN.Null ***** BB23 STMT00033 (IL ???... ???) N003 ( 7, 5) [000148] -A------R--- * ASG int $29f N002 ( 3, 2) [000147] D------N---- +--* LCL_VAR int V17 loc14 d:2 $29f N001 ( 3, 2) [000469] ------------ \--* LCL_VAR int V43 tmp13 u:2 $29f ***** BB23 STMT00103 (IL 0x108... ???) N007 ( 14, 10) [000687] -A--G------- * COMMA void $247 N003 ( 7, 5) [000683] -A--G---R--- +--* ASG ref $185 N002 ( 3, 2) [000681] D------N---- | +--* LCL_VAR ref V66 tmp36 d:2 $185 N001 ( 3, 2) [000682] ----G--N---- | \--* LCL_VAR ref (AX) V58 tmp28 $185 N006 ( 7, 5) [000686] -A--G---R--- \--* ASG int $247 N005 ( 3, 2) [000684] D------N---- +--* LCL_VAR int V67 tmp37 d:2 $247 N004 ( 3, 2) [000685] ----G--N---- \--* LCL_VAR int (AX) V59 tmp29 $247 ***** BB23 STMT00102 (IL 0x108... ???) N023 ( 45, 31) [000486] -ACXG---R--- * ASG int $2a3 N022 ( 3, 2) [000485] D------N---- +--* LCL_VAR int V46 tmp16 d:2 $2a3 N021 ( 41, 28) [000481] -ACXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $2a3 N016 ( 18, 15) [000706] -A--------L- arg0 SETUP +--* COMMA void $VN.Void N009 ( 10, 8) [000699] -A---------- | +--* COMMA void $VN.Void N004 ( 3, 3) [000694] -A------R--- | | +--* ASG byref $411 N003 ( 1, 1) [000693] D------N---- | | | +--* LCL_VAR byref V82 tmp52 d:2 $411 N002 ( 3, 3) [000691] ------------ | | | \--* ADDR byref $411 N001 ( 3, 2) [000692] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 $3cc N008 ( 7, 5) [000698] -A---------- | | \--* ASG ref $VN.Void N006 ( 3, 2) [000696] *------N---- | | +--* IND ref $185 N005 ( 1, 1) [000695] ------------ | | | \--* LCL_VAR byref V82 tmp52 u:2 Zero Fseq[_bits] $411 N007 ( 3, 2) [000697] -------N---- | | \--* LCL_VAR ref V66 tmp36 u:2 (last use) $185 N015 ( 8, 7) [000705] -A---------- | \--* ASG int $VN.Void N013 ( 4, 4) [000703] *------N---- | +--* IND int $247 N012 ( 2, 2) [000702] -------N---- | | \--* ADD byref $214 N010 ( 1, 1) [000700] ------------ | | +--* LCL_VAR byref V82 tmp52 u:2 (last use) $411 N011 ( 1, 1) [000701] ------------ | | \--* CNS_INT long 8 Fseq[_sign] $101 N014 ( 3, 2) [000704] -------N---- | \--* LCL_VAR int V67 tmp37 u:2 (last use) $247 N019 ( 3, 3) [000708] ------------ arg0 in rcx +--* ADDR byref $413 N018 ( 3, 2) [000707] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 $3cd N020 ( 3, 3) [000480] ------------ arg1 in rdx \--* LCL_VAR_ADDR long V48 tmp18 $44b ***** BB23 STMT00104 (IL 0x108... ???) N003 ( 5, 4) [000493] -A--G---R--- * ASG ref $VN.Null N002 ( 3, 2) [000492] D---G--N---- +--* LCL_VAR ref (AX) V48 tmp18 N001 ( 1, 1) [000491] ------------ \--* CNS_INT ref null $VN.Null ***** BB23 STMT00035 (IL ???... ???) N003 ( 7, 5) [000155] -A------R--- * ASG int $2a3 N002 ( 3, 2) [000154] D------N---- +--* LCL_VAR int V18 loc15 d:2 $2a3 N001 ( 3, 2) [000487] ------------ \--* LCL_VAR int V46 tmp16 u:2 $2a3 ***** BB23 STMT00036 (IL 0x111...0x115) N004 ( 9, 7) [000159] ------------ * JTRUE void N003 ( 7, 5) [000158] N------N-U-- \--* GT int $35f N001 ( 3, 2) [000156] ------------ +--* LCL_VAR int V18 loc15 u:2 (last use) $2a3 N002 ( 3, 2) [000157] ------------ \--* LCL_VAR int V17 loc14 u:2 (last use) $29f ------------ BB24 [117..11A) -> BB26 (always), preds={BB23} succs={BB26} ***** BB24 STMT00074 (IL 0x117...0x118) N003 ( 5, 4) [000350] -A------R--- * ASG int $40 N002 ( 3, 2) [000349] D------N---- +--* LCL_VAR int V33 tmp3 d:4 $40 N001 ( 1, 1) [000348] ------------ \--* CNS_INT int 0 $40 ------------ BB25 [11A..11F), preds={BB23} succs={BB26} ***** BB25 STMT00037 (IL 0x11A...0x11E) N005 ( 11, 8) [000164] -A------R--- * ASG int $360 N004 ( 3, 2) [000163] D------N---- +--* LCL_VAR int V33 tmp3 d:3 $360 N003 ( 7, 5) [000162] ------------ \--* SUB int $360 N001 ( 3, 2) [000160] ------------ +--* LCL_VAR int V18 loc15 u:2 (last use) $2a3 N002 ( 3, 2) [000161] ------------ \--* LCL_VAR int V17 loc14 u:2 (last use) $29f ------------ BB26 [11F..126) -> BB28 (cond), preds={BB24,BB25} succs={BB27,BB28} ***** BB26 STMT00119 (IL ???... ???) N005 ( 0, 0) [000877] -A------R--- * ASG int N004 ( 0, 0) [000875] D------N---- +--* LCL_VAR int V33 tmp3 d:2 N003 ( 0, 0) [000876] ------------ \--* PHI int N001 ( 0, 0) [000903] ------------ pred BB24 +--* PHI_ARG int V33 tmp3 u:4 $40 N002 ( 0, 0) [000902] ------------ pred BB25 \--* PHI_ARG int V33 tmp3 u:3 $360 ***** BB26 STMT00038 (IL ???...0x11F) N003 ( 3, 3) [000168] -A------R--- * ASG int $248 N002 ( 1, 1) [000167] D------N---- +--* LCL_VAR int V19 loc16 d:2 $248 N001 ( 3, 2) [000166] ------------ \--* LCL_VAR int V33 tmp3 u:2 $248 ***** BB26 STMT00039 (IL 0x121...0x124) N004 ( 7, 6) [000172] ------------ * JTRUE void N003 ( 5, 4) [000171] N------N---- \--* EQ int $361 N001 ( 3, 2) [000169] ------------ +--* LCL_VAR int V19 loc16 u:2 (last use) $248 N002 ( 1, 1) [000170] ------------ \--* CNS_INT int 0 $40 ------------ BB27 [126..12F), preds={BB26} succs={BB28} ***** BB27 STMT00073 (IL 0x126...0x12A) N006 ( 18, 11) [000347] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft $VN.Void N004 ( 3, 3) [000345] ------------ arg0 in rcx +--* ADDR long $414 N003 ( 3, 2) [000344] ----G--N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 $3ce N005 ( 1, 1) [000346] ------------ arg1 in rdx \--* LCL_VAR int V19 loc16 u:2 $248 ------------ BB28 [12F..13E) -> BB32 (cond), preds={BB26,BB27} succs={BB29,BB32} ***** BB28 STMT00040 (IL 0x12F...0x133) N005 ( 9, 7) [000177] -A------R--- * ASG int $362 N004 ( 3, 2) [000176] D------N---- +--* LCL_VAR int V20 loc17 d:2 $362 N003 ( 5, 4) [000175] ------------ \--* SUB int $362 N001 ( 3, 2) [000173] ------------ +--* LCL_VAR int V03 loc0 u:2 (last use) $348 N002 ( 1, 1) [000174] ------------ \--* LCL_VAR int V13 loc10 u:2 $293 ***** BB28 STMT00041 (IL 0x135...0x137) N003 ( 7, 5) [000180] -A------R--- * ASG int $362 N002 ( 3, 2) [000179] D------N---- +--* LCL_VAR int V21 loc18 d:2 $362 N001 ( 3, 2) [000178] ------------ \--* LCL_VAR int V20 loc17 u:2 $362 ***** BB28 STMT00042 (IL 0x139...0x13C) N004 ( 5, 5) [000184] ------------ * JTRUE void N003 ( 3, 3) [000183] N------N---- \--* EQ int $363 N001 ( 1, 1) [000181] ------------ +--* LCL_VAR int V13 loc10 u:2 $293 N002 ( 1, 1) [000182] ------------ \--* CNS_INT int 0 $40 ------------ BB29 [13E..144) -> BB31 (cond), preds={BB28} succs={BB30,BB31} ***** BB29 STMT00070 (IL 0x13E...0x142) N004 ( 7, 6) [000329] ------------ * JTRUE void N003 ( 5, 4) [000328] N------N-U-- \--* LE int $364 N001 ( 1, 1) [000326] ------------ +--* LCL_VAR int V19 loc16 u:2 $248 N002 ( 3, 2) [000327] ------------ \--* LCL_VAR int V20 loc17 u:2 $362 ------------ BB30 [144..155) -> BB44 (always), preds={BB29} succs={BB44} ***** BB30 STMT00072 (IL 0x144...0x154) N014 ( 29, 17) [000717] -ACXG---R--- * ASG int $5c2 N013 ( 1, 1) [000716] D------N---- +--* LCL_VAR int V51 tmp21 d:5 $5c2 N012 ( 29, 17) [000342] --CXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits $5c2 N005 ( 1, 1) [000341] ------------ arg4 out+20 +--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N008 ( 6, 3) [000339] N----------- arg2 in r8 +--* NE int N006 ( 1, 1) [000337] ------------ | +--* LCL_VAR int V10 loc7 u:2 (last use) N007 ( 1, 1) [000338] ------------ | \--* CNS_INT int 0 $40 N009 ( 3, 2) [000335] ----G------- arg0 in rcx +--* LCL_VAR ref (AX) V12 loc9 $18c N010 ( 1, 1) [000336] ------------ arg1 in rdx +--* LCL_VAR int V13 loc10 u:2 (last use) $293 N011 ( 1, 1) [000340] ------------ arg3 in r9 \--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 ------------ BB31 [155..15C), preds={BB29} succs={BB32} ***** BB31 STMT00071 (IL 0x155...0x15A) N005 ( 9, 7) [000334] -A------R--- * ASG int $365 N004 ( 3, 2) [000333] D------N---- +--* LCL_VAR int V21 loc18 d:4 $365 N003 ( 5, 4) [000332] ------------ \--* SUB int $365 N001 ( 3, 2) [000330] ------------ +--* LCL_VAR int V20 loc17 u:2 (last use) $362 N002 ( 1, 1) [000331] ------------ \--* LCL_VAR int V19 loc16 u:2 $248 ------------ BB32 [15C..167) -> BB34 (cond), preds={BB28,BB31} succs={BB33,BB34} ***** BB32 STMT00118 (IL ???... ???) N005 ( 0, 0) [000874] -A------R--- * ASG int N004 ( 0, 0) [000872] D------N---- +--* LCL_VAR int V21 loc18 d:3 N003 ( 0, 0) [000873] ------------ \--* PHI int N001 ( 0, 0) [000900] ------------ pred BB31 +--* PHI_ARG int V21 loc18 u:4 $365 N002 ( 0, 0) [000888] ------------ pred BB28 \--* PHI_ARG int V21 loc18 u:2 $362 ***** BB32 STMT00105 (IL 0x15C... ???) N007 ( 14, 10) [000724] -A--G------- * COMMA void $24a N003 ( 7, 5) [000720] -A--G---R--- +--* ASG ref $186 N002 ( 3, 2) [000718] D---G--N---- | +--* LCL_VAR ref (AX) V68 tmp38 N001 ( 3, 2) [000719] ----G--N---- | \--* LCL_VAR ref (AX) V56 tmp26 $186 N006 ( 7, 5) [000723] -A--G---R--- \--* ASG int $24a N005 ( 3, 2) [000721] D---G--N---- +--* LCL_VAR int (AX) V69 tmp39 N004 ( 3, 2) [000722] ----G--N---- \--* LCL_VAR int (AX) V57 tmp27 $24a ***** BB32 STMT00106 (IL 0x15C... ???) N007 ( 14, 10) [000731] -A--G------- * COMMA void $24b N003 ( 7, 5) [000727] -A--G---R--- +--* ASG ref $187 N002 ( 3, 2) [000725] D------N---- | +--* LCL_VAR ref V70 tmp40 d:2 $187 N001 ( 3, 2) [000726] ----G--N---- | \--* LCL_VAR ref (AX) V58 tmp28 $187 N006 ( 7, 5) [000730] -A--G---R--- \--* ASG int $24b N005 ( 3, 2) [000728] D------N---- +--* LCL_VAR int V71 tmp41 d:2 $24b N004 ( 3, 2) [000729] ----G--N---- \--* LCL_VAR int (AX) V59 tmp29 $24b ***** BB32 STMT00044 (IL ???... ???) N027 ( 52, 38) [000195] -ACXG------- * JTRUE void N026 ( 50, 36) [000503] JACXG--N---- \--* LT int $367 N024 ( 48, 34) [000499] -ACXG------- +--* CALL int System.Numerics.BigInteger.CompareTo $2ae N004 ( 7, 6) [000752] -A------R-L- this SETUP | +--* ASG byref $415 N003 ( 3, 2) [000751] D------N---- | | +--* LCL_VAR byref V84 tmp54 d:2 $415 N002 ( 3, 3) [000497] ------------ | | \--* ADDR byref $415 N001 ( 3, 2) [000496] ----G--N---- | | \--* LCL_VAR struct(AX)(P) V49 tmp19 | | \--* ref V49._bits (offs=0x00) -> V68 tmp38 | | \--* int V49._sign (offs=0x08) -> V69 tmp39 $3cf N020 ( 18, 15) [000750] -A--------L- arg1 SETUP | +--* COMMA void $VN.Void N013 ( 10, 8) [000743] -A---------- | | +--* COMMA void $VN.Void N008 ( 3, 3) [000738] -A------R--- | | | +--* ASG byref $417 N007 ( 1, 1) [000737] D------N---- | | | | +--* LCL_VAR byref V83 tmp53 d:2 $417 N006 ( 3, 3) [000735] ------------ | | | | \--* ADDR byref $417 N005 ( 3, 2) [000736] ----G--N---- | | | | \--* LCL_VAR struct(AX) V76 tmp46 $3d0 N012 ( 7, 5) [000742] -A---------- | | | \--* ASG ref $VN.Void N010 ( 3, 2) [000740] *------N---- | | | +--* IND ref $187 N009 ( 1, 1) [000739] ------------ | | | | \--* LCL_VAR byref V83 tmp53 u:2 Zero Fseq[_bits] $417 N011 ( 3, 2) [000741] -------N---- | | | \--* LCL_VAR ref V70 tmp40 u:2 (last use) $187 N019 ( 8, 7) [000749] -A---------- | | \--* ASG int $VN.Void N017 ( 4, 4) [000747] *------N---- | | +--* IND int $24b N016 ( 2, 2) [000746] -------N---- | | | \--* ADD byref $216 N014 ( 1, 1) [000744] ------------ | | | +--* LCL_VAR byref V83 tmp53 u:2 (last use) $417 N015 ( 1, 1) [000745] ------------ | | | \--* CNS_INT long 8 Fseq[_sign] $101 N018 ( 3, 2) [000748] -------N---- | | \--* LCL_VAR int V71 tmp41 u:2 (last use) $24b N021 ( 3, 2) [000753] ------------ this in rcx | +--* LCL_VAR byref V84 tmp54 u:2 (last use) $415 N023 ( 3, 3) [000755] ------------ arg1 in rdx | \--* ADDR byref $419 N022 ( 3, 2) [000754] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 $3d1 N025 ( 1, 1) [000502] ------------ \--* CNS_INT int 0 $40 ------------ BB33 [167..16B) -> BB35 (always), preds={BB32} succs={BB35} ***** BB33 STMT00069 (IL 0x167...0x169) N003 ( 5, 4) [000324] -A------R--- * ASG int $248 N002 ( 3, 2) [000323] D------N---- +--* LCL_VAR int V34 tmp4 d:4 $248 N001 ( 1, 1) [000322] ------------ \--* LCL_VAR int V19 loc16 u:2 (last use) $248 ------------ BB34 [16B..16F), preds={BB32} succs={BB35} ***** BB34 STMT00045 (IL 0x16B...0x16E) N005 ( 7, 6) [000200] -A------R--- * ASG int $368 N004 ( 3, 2) [000199] D------N---- +--* LCL_VAR int V34 tmp4 d:3 $368 N003 ( 3, 3) [000198] ------------ \--* ADD int $368 N001 ( 1, 1) [000196] ------------ +--* LCL_VAR int V19 loc16 u:2 (last use) $248 N002 ( 1, 1) [000197] ------------ \--* CNS_INT int 1 $41 ------------ BB35 [16F..1A4) -> BB40 (cond), preds={BB33,BB34} succs={BB36,BB40} ***** BB35 STMT00117 (IL ???... ???) N005 ( 0, 0) [000871] -A------R--- * ASG int N004 ( 0, 0) [000869] D------N---- +--* LCL_VAR int V34 tmp4 d:2 N003 ( 0, 0) [000870] ------------ \--* PHI int N001 ( 0, 0) [000899] ------------ pred BB33 +--* PHI_ARG int V34 tmp4 u:4 $248 N002 ( 0, 0) [000898] ------------ pred BB34 \--* PHI_ARG int V34 tmp4 u:3 $368 ***** BB35 STMT00046 (IL ???...0x16F) N003 ( 7, 5) [000204] -A------R--- * ASG int $24c N002 ( 3, 2) [000203] D------N---- +--* LCL_VAR int V22 loc19 d:2 $24c N001 ( 3, 2) [000202] ------------ \--* LCL_VAR int V34 tmp4 u:2 (last use) $24c ***** BB35 STMT00047 (IL 0x171...0x18A) N006 ( 20, 12) [000208] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft $VN.Void N004 ( 3, 3) [000206] ------------ arg0 in rcx +--* ADDR long $41a N003 ( 3, 2) [000205] ----G--N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 $3d2 N005 ( 3, 2) [000207] ------------ arg1 in rdx \--* LCL_VAR int V21 loc18 u:3 (last use) $249 ***** BB35 STMT00048 (IL 0x17A... ???) N045 ( 78, 56) [000213] SACXG------- * CALL void System.Numerics.BigInteger.DivRem $VN.Void N004 ( 7, 6) [000797] -A------R-L- arg0 SETUP +--* ASG long $41b N003 ( 3, 2) [000796] D------N---- | +--* LCL_VAR long V88 tmp58 d:2 $41b N002 ( 3, 3) [000220] ------------ | \--* ADDR long $41b N001 ( 3, 2) [000219] ----G--N---- | \--* LCL_VAR struct(AX)(P) V35 tmp5 | \--* ref V35._bits (offs=0x00) -> V62 tmp32 | \--* int V35._sign (offs=0x08) -> V63 tmp33 $3d3 N020 ( 18, 15) [000776] -A--G-----L- arg1 SETUP +--* COMMA void $VN.Void N013 ( 10, 8) [000769] -A--G------- | +--* COMMA void $VN.Void N008 ( 3, 3) [000764] -A------R--- | | +--* ASG byref $41c N007 ( 1, 1) [000763] D------N---- | | | +--* LCL_VAR byref V85 tmp55 d:2 $41c N006 ( 3, 3) [000761] ------------ | | | \--* ADDR byref $41c N005 ( 3, 2) [000762] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 $3d4 N012 ( 7, 5) [000768] -A--G------- | | \--* ASG ref $VN.Void N010 ( 3, 2) [000766] *------N---- | | +--* IND ref $188 N009 ( 1, 1) [000765] ------------ | | | \--* LCL_VAR byref V85 tmp55 u:2 Zero Fseq[_bits] $41c N011 ( 3, 2) [000767] ----G--N---- | | \--* LCL_VAR ref (AX) V56 tmp26 $188 N019 ( 8, 7) [000775] -A--G------- | \--* ASG int $VN.Void N017 ( 4, 4) [000773] *------N---- | +--* IND int $24d N016 ( 2, 2) [000772] -------N---- | | \--* ADD byref $218 N014 ( 1, 1) [000770] ------------ | | +--* LCL_VAR byref V85 tmp55 u:2 (last use) $41c N015 ( 1, 1) [000771] ------------ | | \--* CNS_INT long 8 Fseq[_sign] $101 N018 ( 3, 2) [000774] ----G--N---- | \--* LCL_VAR int (AX) V57 tmp27 $24d N036 ( 18, 15) [000795] -A--G-----L- arg2 SETUP +--* COMMA void $VN.Void N029 ( 10, 8) [000788] -A--G------- | +--* COMMA void $VN.Void N024 ( 3, 3) [000783] -A------R--- | | +--* ASG byref $41e N023 ( 1, 1) [000782] D------N---- | | | +--* LCL_VAR byref V87 tmp57 d:2 $41e N022 ( 3, 3) [000780] ------------ | | | \--* ADDR byref $41e N021 ( 3, 2) [000781] -------N---- | | | \--* LCL_VAR struct(AX) V86 tmp56 $3d5 N028 ( 7, 5) [000787] -A--G------- | | \--* ASG ref $VN.Void N026 ( 3, 2) [000785] *------N---- | | +--* IND ref $189 N025 ( 1, 1) [000784] ------------ | | | \--* LCL_VAR byref V87 tmp57 u:2 Zero Fseq[_bits] $41e N027 ( 3, 2) [000786] ----G--N---- | | \--* LCL_VAR ref (AX) V58 tmp28 $189 N035 ( 8, 7) [000794] -A--G------- | \--* ASG int $VN.Void N033 ( 4, 4) [000792] *------N---- | +--* IND int $24e N032 ( 2, 2) [000791] -------N---- | | \--* ADD byref $21a N030 ( 1, 1) [000789] ------------ | | +--* LCL_VAR byref V87 tmp57 u:2 (last use) $41e N031 ( 1, 1) [000790] ------------ | | \--* CNS_INT long 8 Fseq[_sign] $101 N034 ( 3, 2) [000793] ----G--N---- | \--* LCL_VAR int (AX) V59 tmp29 $24e N038 ( 3, 2) [000798] ------------ arg0 in rcx +--* LCL_VAR long V88 tmp58 u:2 (last use) $41b N040 ( 3, 3) [000800] ------------ arg1 in rdx +--* ADDR byref $420 N039 ( 3, 2) [000799] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 $3d6 N042 ( 3, 3) [000802] ------------ arg2 in r8 +--* ADDR byref $421 N041 ( 3, 2) [000801] -------N---- | \--* LCL_VAR struct(AX) V86 tmp56 $3d7 N044 ( 3, 3) [000212] ------------ arg3 in r9 \--* ADDR long $422 N043 ( 3, 2) [000211] ----G--N---- \--* LCL_VAR struct(AX)(P) V23 loc20 \--* ref V23._bits (offs=0x00) -> V60 tmp30 \--* int V23._sign (offs=0x08) -> V61 tmp31 $3d8 ***** BB35 STMT00050 (IL ???... ???) N021 ( 38, 24) [000226] -ACXG---R--- * ASG long $450 N020 ( 1, 1) [000225] D------N---- +--* LCL_VAR long V24 loc21 d:2 $450 N019 ( 38, 24) [000218] -ACXG------- \--* CALL long System.Numerics.BigInteger.op_Explicit $450 N016 ( 18, 15) [000822] -A--G-----L- arg0 SETUP +--* COMMA void $VN.Void N009 ( 10, 8) [000815] -A--G------- | +--* COMMA void $VN.Void N004 ( 3, 3) [000810] -A------R--- | | +--* ASG byref $423 N003 ( 1, 1) [000809] D------N---- | | | +--* LCL_VAR byref V89 tmp59 d:2 $423 N002 ( 3, 3) [000807] ------------ | | | \--* ADDR byref $423 N001 ( 3, 2) [000808] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 $3d9 N008 ( 7, 5) [000814] -A--G------- | | \--* ASG ref $VN.Void N006 ( 3, 2) [000812] *------N---- | | +--* IND ref $18a N005 ( 1, 1) [000811] ------------ | | | \--* LCL_VAR byref V89 tmp59 u:2 Zero Fseq[_bits] $423 N007 ( 3, 2) [000813] ----G--N---- | | \--* LCL_VAR ref (AX) V62 tmp32 $18a N015 ( 8, 7) [000821] -A--G------- | \--* ASG int $VN.Void N013 ( 4, 4) [000819] *------N---- | +--* IND int $24f N012 ( 2, 2) [000818] -------N---- | | \--* ADD byref $21d N010 ( 1, 1) [000816] ------------ | | +--* LCL_VAR byref V89 tmp59 u:2 (last use) $423 N011 ( 1, 1) [000817] ------------ | | \--* CNS_INT long 8 Fseq[_sign] $101 N014 ( 3, 2) [000820] ----G--N---- | \--* LCL_VAR int (AX) V63 tmp33 $24f N018 ( 3, 3) [000824] ------------ arg0 in rcx \--* ADDR byref $425 N017 ( 3, 2) [000823] -------N---- \--* LCL_VAR struct(AX) V76 tmp46 $3da ***** BB35 STMT00052 (IL ???... ???) N005 ( 12, 7) [000232] -A--G---R--- * ASG int $369 N004 ( 3, 2) [000231] D------N---- +--* LCL_VAR int V25 loc22 d:2 $369 N003 ( 8, 4) [000516] ----G------- \--* EQ int $369 N001 ( 3, 2) [000514] ----G------- +--* LCL_VAR int (AX) V61 tmp31 $250 N002 ( 1, 1) [000515] ------------ \--* CNS_INT int 0 $40 ***** BB35 STMT00054 (IL ???... ???) N005 ( 19, 10) [000237] -ACXG---R--- * ASG int $2b4 N004 ( 3, 2) [000236] D------N---- +--* LCL_VAR int V26 loc23 d:2 $2b4 N003 ( 15, 7) [000234] --CXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $2b4 N002 ( 1, 1) [000233] ------------ arg0 in rcx \--* LCL_VAR long V24 loc21 u:2 $450 ***** BB35 STMT00055 (IL 0x19E...0x1A2) N004 ( 9, 7) [000241] ------------ * JTRUE void N003 ( 7, 5) [000240] N------N-U-- \--* LE int $36a N001 ( 3, 2) [000238] ------------ +--* LCL_VAR int V26 loc23 u:2 $2b4 N002 ( 3, 2) [000239] ------------ \--* LCL_VAR int V20 loc17 u:2 $362 ------------ BB36 [1A4..1AF) -> BB38 (cond), preds={BB35} succs={BB37,BB38} ***** BB36 STMT00063 (IL 0x1A4...0x1A9) N005 ( 11, 8) [000286] -A------R--- * ASG int $36b N004 ( 3, 2) [000285] D------N---- +--* LCL_VAR int V29 loc26 d:2 $36b N003 ( 7, 5) [000284] ------------ \--* SUB int $36b N001 ( 3, 2) [000282] ------------ +--* LCL_VAR int V26 loc23 u:2 (last use) $2b4 N002 ( 3, 2) [000283] ------------ \--* LCL_VAR int V20 loc17 u:2 $362 ***** BB36 STMT00064 (IL 0x1AB...0x1AD) N004 ( 7, 6) [000290] ------------ * JTRUE void N003 ( 5, 4) [000289] J------N---- \--* EQ int $36c N001 ( 3, 2) [000287] ------------ +--* LCL_VAR int V25 loc22 u:2 (last use) $369 N002 ( 1, 1) [000288] ------------ \--* CNS_INT int 0 $40 ------------ BB37 [1AF..1C3) -> BB39 (always), preds={BB36} succs={BB39} ***** BB37 STMT00068 (IL 0x1AF...0x1C1) N013 ( 23, 15) [000320] -A------R--- * ASG int $36e N012 ( 3, 2) [000319] D------N---- +--* LCL_VAR int V37 tmp7 d:4 $36e N011 ( 19, 12) [000318] ------------ \--* EQ int $36e N009 ( 14, 10) [000315] ------------ +--* AND long $490 N001 ( 1, 1) [000305] ------------ | +--* LCL_VAR long V24 loc21 u:2 $450 N008 ( 12, 8) [000314] ------------ | \--* ADD long $48f N006 ( 10, 6) [000311] --------R--- | +--* LSH long $48e N005 ( 1, 1) [000307] ------------ | | +--* CNS_INT long 1 $103 N004 ( 5, 4) [000310] ------------ | | \--* AND int $36d N002 ( 3, 2) [000308] ------------ | | +--* LCL_VAR int V29 loc26 u:2 $36b N003 ( 1, 1) [000309] ------------ | | \--* CNS_INT int 63 $66 N007 ( 1, 1) [000313] ------------ | \--* CNS_INT long -1 $104 N010 ( 1, 1) [000317] ------------ \--* CNS_INT long 0 $100 ------------ BB38 [1C3..1C4), preds={BB36} succs={BB39} ***** BB38 STMT00065 (IL 0x1C3...0x1C3) N003 ( 5, 4) [000293] -A------R--- * ASG int $40 N002 ( 3, 2) [000292] D------N---- +--* LCL_VAR int V37 tmp7 d:3 $40 N001 ( 1, 1) [000291] ------------ \--* CNS_INT int 0 $40 ------------ BB39 [1C4..1D0), preds={BB37,BB38} succs={BB40} ***** BB39 STMT00116 (IL ???... ???) N005 ( 0, 0) [000868] -A------R--- * ASG int N004 ( 0, 0) [000866] D------N---- +--* LCL_VAR int V37 tmp7 d:2 N003 ( 0, 0) [000867] ------------ \--* PHI int N001 ( 0, 0) [000897] ------------ pred BB37 +--* PHI_ARG int V37 tmp7 u:4 $36e N002 ( 0, 0) [000896] ------------ pred BB38 \--* PHI_ARG int V37 tmp7 u:3 $40 ***** BB39 STMT00066 (IL ???...0x1C4) N004 ( 8, 7) [000297] -A------R--- * ASG int $36f N003 ( 3, 2) [000296] D------N---- +--* LCL_VAR int V25 loc22 d:4 $36f N002 ( 4, 4) [000826] ------------ \--* CAST int <- bool <- int $36f N001 ( 3, 2) [000295] ------------ \--* LCL_VAR int V37 tmp7 u:2 (last use) $251 ***** BB39 STMT00067 (IL 0x1C6...0x1CE) N007 ( 10, 6) [000304] -A------R--- * ASG long $491 N006 ( 1, 1) [000303] D------N---- +--* LCL_VAR long V24 loc21 d:4 $491 N005 ( 10, 6) [000302] ------------ \--* RSZ long $491 N001 ( 1, 1) [000298] ------------ +--* LCL_VAR long V24 loc21 u:2 (last use) $450 N004 ( 5, 4) [000301] ------------ \--* AND int $36d N002 ( 3, 2) [000299] ------------ +--* LCL_VAR int V29 loc26 u:2 (last use) $36b N003 ( 1, 1) [000300] ------------ \--* CNS_INT int 63 $66 ------------ BB40 [1D0..1E7) -> BB42 (cond), preds={BB35,BB39} succs={BB41,BB42} ***** BB40 STMT00115 (IL ???... ???) N005 ( 0, 0) [000865] -A------R--- * ASG bool N004 ( 0, 0) [000863] D------N---- +--* LCL_VAR bool V25 loc22 d:3 N003 ( 0, 0) [000864] ------------ \--* PHI bool N001 ( 0, 0) [000894] ------------ pred BB39 +--* PHI_ARG bool V25 loc22 u:4 $36f N002 ( 0, 0) [000889] ------------ pred BB35 \--* PHI_ARG bool V25 loc22 u:2 $369 ***** BB40 STMT00114 (IL ???... ???) N005 ( 0, 0) [000862] -A------R--- * ASG long N004 ( 0, 0) [000860] D------N---- +--* LCL_VAR long V24 loc21 d:3 N003 ( 0, 0) [000861] ------------ \--* PHI long N001 ( 0, 0) [000895] ------------ pred BB39 +--* PHI_ARG long V24 loc21 u:4 $491 N002 ( 0, 0) [000890] ------------ pred BB35 \--* PHI_ARG long V24 loc21 u:2 $450 ***** BB40 STMT00057 (IL ???... ???) N027 ( 53, 34) [000254] -ACXG---R--- * ASG long $493 N026 ( 3, 2) [000253] D------N---- +--* LCL_VAR long V27 loc24 d:2 $493 N025 ( 49, 31) [000252] -ACXG------- \--* ADD long $493 N023 ( 47, 29) [000250] -ACXG------- +--* LSH long $492 N019 ( 38, 24) [000243] -ACXG------- | +--* CALL long System.Numerics.BigInteger.op_Explicit $454 N016 ( 18, 15) [000845] -A--G-----L- arg0 SETUP | | +--* COMMA void $VN.Void N009 ( 10, 8) [000838] -A--G------- | | | +--* COMMA void $VN.Void N004 ( 3, 3) [000833] -A------R--- | | | | +--* ASG byref $426 N003 ( 1, 1) [000832] D------N---- | | | | | +--* LCL_VAR byref V90 tmp60 d:2 $426 N002 ( 3, 3) [000830] ------------ | | | | | \--* ADDR byref $426 N001 ( 3, 2) [000831] ----G--N---- | | | | | \--* LCL_VAR struct(AX) V76 tmp46 $3db N008 ( 7, 5) [000837] -A--G------- | | | | \--* ASG ref $VN.Void N006 ( 3, 2) [000835] *------N---- | | | | +--* IND ref $18b N005 ( 1, 1) [000834] ------------ | | | | | \--* LCL_VAR byref V90 tmp60 u:2 Zero Fseq[_bits] $426 N007 ( 3, 2) [000836] ----G--N---- | | | | \--* LCL_VAR ref (AX) V54 tmp24 $18b N015 ( 8, 7) [000844] -A--G------- | | | \--* ASG int $VN.Void N013 ( 4, 4) [000842] *------N---- | | | +--* IND int $252 N012 ( 2, 2) [000841] -------N---- | | | | \--* ADD byref $220 N010 ( 1, 1) [000839] ------------ | | | | +--* LCL_VAR byref V90 tmp60 u:2 (last use) $426 N011 ( 1, 1) [000840] ------------ | | | | \--* CNS_INT long 8 Fseq[_sign] $101 N014 ( 3, 2) [000843] ----G--N---- | | | \--* LCL_VAR int (AX) V55 tmp25 $252 N018 ( 3, 3) [000847] ------------ arg0 in rcx | | \--* ADDR byref $428 N017 ( 3, 2) [000846] -------N---- | | \--* LCL_VAR struct(AX) V76 tmp46 $3dc N022 ( 5, 4) [000249] ------------ | \--* AND int $370 N020 ( 3, 2) [000247] ------------ | +--* LCL_VAR int V20 loc17 u:2 (last use) $362 N021 ( 1, 1) [000248] ------------ | \--* CNS_INT int 63 $66 N024 ( 1, 1) [000251] ------------ \--* LCL_VAR long V24 loc21 u:3 (last use) $580 ***** BB40 STMT00058 (IL 0x1E2...0x1E5) N004 ( 5, 5) [000258] ------------ * JTRUE void N003 ( 3, 3) [000257] N------N---- \--* NE int $35a N001 ( 1, 1) [000255] ------------ +--* LCL_VAR int V13 loc10 u:2 $293 N002 ( 1, 1) [000256] ------------ \--* CNS_INT int 0 $40 ------------ BB41 [1E7..1EE) -> BB43 (always), preds={BB40} succs={BB43} ***** BB41 STMT00062 (IL 0x1E7...0x1EC) N006 ( 10, 8) [000280] -A------R--- * ASG int $372 N005 ( 3, 2) [000279] D------N---- +--* LCL_VAR int V36 tmp6 d:4 $372 N004 ( 6, 5) [000278] ------------ \--* ADD int $372 N002 ( 4, 3) [000276] ------------ +--* NEG int $2c2 N001 ( 3, 2) [000275] ------------ | \--* LCL_VAR int V22 loc19 u:2 (last use) $24c N003 ( 1, 1) [000277] ------------ \--* CNS_INT int -1 $43 ------------ BB42 [1EE..1F2), preds={BB40} succs={BB43} ***** BB42 STMT00059 (IL 0x1EE...0x1F1) N005 ( 7, 6) [000263] -A------R--- * ASG int $371 N004 ( 3, 2) [000262] D------N---- +--* LCL_VAR int V36 tmp6 d:3 $371 N003 ( 3, 3) [000261] ------------ \--* ADD int $371 N001 ( 1, 1) [000259] ------------ +--* LCL_VAR int V13 loc10 u:2 (last use) $293 N002 ( 1, 1) [000260] ------------ \--* CNS_INT int -2 $68 ------------ BB43 [1F2..202), preds={BB41,BB42} succs={BB44} ***** BB43 STMT00113 (IL ???... ???) N005 ( 0, 0) [000859] -A------R--- * ASG int N004 ( 0, 0) [000857] D------N---- +--* LCL_VAR int V36 tmp6 d:2 N003 ( 0, 0) [000858] ------------ \--* PHI int N001 ( 0, 0) [000893] ------------ pred BB41 +--* PHI_ARG int V36 tmp6 u:4 $372 N002 ( 0, 0) [000892] ------------ pred BB42 \--* PHI_ARG int V36 tmp6 u:3 $371 ***** BB43 STMT00061 (IL 0x1F4...0x201) N012 ( 28, 18) [000853] -ACXG---R--- * ASG int $2be N011 ( 1, 1) [000852] D------N---- +--* LCL_VAR int V51 tmp21 d:4 $2be N010 ( 28, 18) [000273] --CXG------- \--* CALL nullcheck int FloatingPointType.AssembleFloatingPointValue $2be N005 ( 1, 1) [000272] ------------ arg4 out+20 +--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N006 ( 1, 1) [000268] ------------ this in rcx +--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 N007 ( 3, 2) [000269] ------------ arg1 in rdx +--* LCL_VAR long V27 loc24 u:2 (last use) $493 N008 ( 3, 2) [000270] ------------ arg2 in r8 +--* LCL_VAR int V36 tmp6 u:2 (last use) $253 N009 ( 3, 2) [000271] ------------ arg3 in r9 \--* LCL_VAR int V25 loc22 u:3 (last use) $540 ------------ BB44 [???..???) (return), preds={BB16,BB30,BB43} succs={} ***** BB44 STMT00112 (IL ???... ???) N006 ( 0, 0) [000856] -A------R--- * ASG int N005 ( 0, 0) [000854] D------N---- +--* LCL_VAR int V51 tmp21 d:2 N004 ( 0, 0) [000855] ------------ \--* PHI int N001 ( 0, 0) [000901] ------------ pred BB30 +--* PHI_ARG int V51 tmp21 u:5 $5c2 N002 ( 0, 0) [000891] ------------ pred BB43 +--* PHI_ARG int V51 tmp21 u:4 $2be N003 ( 0, 0) [000887] ------------ pred BB16 \--* PHI_ARG int V51 tmp21 u:3 $5c7 ***** BB44 STMT00109 (IL ???... ???) N002 ( 2, 2) [000523] ------------ * RETURN int $5c9 N001 ( 1, 1) [000522] -------N---- \--* LCL_VAR int V51 tmp21 u:2 (last use) $254 ------------------------------------------------------------------------------------------------------------------- *************** In optOptimizeValnumCSEs() CSE candidate #01, key=$2c1 in BB07, [cost= 3, size= 3]: N002 ( 3, 3) CSE #01 (use)[000429] ---XG------- * ARR_LENGTH int N001 ( 1, 1) [000428] ------------ \--* LCL_VAR ref V52 tmp22 u:2 CSE candidate #02, key=$355 in BB30, [cost= 6, size= 3]: N008 ( 6, 3) CSE #02 (use)[000339] N----------- * NE int N006 ( 1, 1) [000337] ------------ +--* LCL_VAR int V10 loc7 u:2 (last use) N007 ( 1, 1) [000338] ------------ \--* CNS_INT int 0 $40 CSE candidate #03, key=$36d in BB39, [cost= 5, size= 4]: N004 ( 5, 4) CSE #03 (use)[000301] ------------ * AND int $36d N002 ( 3, 2) [000299] ------------ +--* LCL_VAR int V29 loc26 u:2 (last use) $36b N003 ( 1, 1) [000300] ------------ \--* CNS_INT int 63 $66 Blocks that generate CSE def/uses BB02 cseGen = 0000000000000003 BB07 cseGen = 0000000000000003 BB10 cseGen = 0000000000000001 BB16 cseGen = 0000000000000004 BB21 cseGen = 0000000000000001 BB30 cseGen = 0000000000000004 BB37 cseGen = 0000000000000030 BB39 cseGen = 0000000000000030 Performing DataFlow for ValnumCSE's StartMerge BB01 :: cseOut = 000000000000007F EndMerge BB01 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 000000000000007F, => true StartMerge BB02 :: cseOut = 000000000000007F Merge BB02 and BB01 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000000 EndMerge BB02 :: cseIn = 0000000000000000 :: cseGen = 0000000000000003 => cseOut = 0000000000000003 != preMerge = 000000000000007F, => true StartMerge BB03 :: cseOut = 000000000000007F Merge BB03 and BB02 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000003 EndMerge BB03 :: cseIn = 0000000000000003 -- cseKill = 0000000000000015 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 000000000000007F, => true StartMerge BB04 :: cseOut = 000000000000007F Merge BB04 and BB02 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000003 EndMerge BB04 :: cseIn = 0000000000000003 -- cseKill = 0000000000000015 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 000000000000007F, => true StartMerge BB05 :: cseOut = 000000000000007F Merge BB05 and BB04 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000001 EndMerge BB05 :: cseIn = 0000000000000001 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 000000000000007F, => true StartMerge BB06 :: cseOut = 000000000000007F Merge BB06 and BB04 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000001 EndMerge BB06 :: cseIn = 0000000000000001 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 000000000000007F, => true StartMerge BB07 :: cseOut = 000000000000007F Merge BB07 and BB05 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000001 Merge BB07 and BB06 :: cseIn = 0000000000000001 :: cseOut = 000000000000007F => cseIn = 0000000000000001 EndMerge BB07 :: cseIn = 0000000000000001 :: cseGen = 0000000000000003 => cseOut = 0000000000000003 != preMerge = 000000000000007F, => true StartMerge BB07 :: cseOut = 0000000000000003 Merge BB07 and BB05 :: cseIn = 0000000000000001 :: cseOut = 0000000000000003 => cseIn = 0000000000000001 Merge BB07 and BB06 :: cseIn = 0000000000000001 :: cseOut = 0000000000000003 => cseIn = 0000000000000001 EndMerge BB07 :: cseIn = 0000000000000001 :: cseGen = 0000000000000003 => cseOut = 0000000000000003 != preMerge = 0000000000000003, => false StartMerge BB08 :: cseOut = 000000000000007F Merge BB08 and BB07 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000003 EndMerge BB08 :: cseIn = 0000000000000003 :: cseGen = 0000000000000000 => cseOut = 0000000000000003 != preMerge = 000000000000007F, => true StartMerge BB09 :: cseOut = 000000000000007F Merge BB09 and BB07 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000003 EndMerge BB09 :: cseIn = 0000000000000003 :: cseGen = 0000000000000000 => cseOut = 0000000000000003 != preMerge = 000000000000007F, => true StartMerge BB10 :: cseOut = 000000000000007F Merge BB10 and BB08 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000003 Merge BB10 and BB09 :: cseIn = 0000000000000003 :: cseOut = 000000000000007F => cseIn = 0000000000000003 EndMerge BB10 :: cseIn = 0000000000000003 -- cseKill = 0000000000000015 :: cseGen = 0000000000000001 => cseOut = 0000000000000001 != preMerge = 000000000000007F, => true StartMerge BB10 :: cseOut = 0000000000000001 Merge BB10 and BB08 :: cseIn = 0000000000000003 :: cseOut = 0000000000000001 => cseIn = 0000000000000003 Merge BB10 and BB09 :: cseIn = 0000000000000003 :: cseOut = 0000000000000001 => cseIn = 0000000000000003 EndMerge BB10 :: cseIn = 0000000000000003 -- cseKill = 0000000000000015 :: cseGen = 0000000000000001 => cseOut = 0000000000000001 != preMerge = 0000000000000001, => false StartMerge BB11 :: cseOut = 000000000000007F Merge BB11 and BB10 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000001 EndMerge BB11 :: cseIn = 0000000000000001 -- cseKill = 0000000000000015 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 000000000000007F, => true StartMerge BB14 :: cseOut = 000000000000007F Merge BB14 and BB10 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000001 Merge BB14 and BB13 :: cseIn = 0000000000000001 :: cseOut = 000000000000007F => cseIn = 0000000000000001 EndMerge BB14 :: cseIn = 0000000000000001 -- cseKill = 0000000000000015 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 000000000000007F, => true StartMerge BB12 :: cseOut = 000000000000007F Merge BB12 and BB11 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000001 EndMerge BB12 :: cseIn = 0000000000000001 -- cseKill = 0000000000000015 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 000000000000007F, => true StartMerge BB13 :: cseOut = 000000000000007F Merge BB13 and BB11 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000001 EndMerge BB13 :: cseIn = 0000000000000001 -- cseKill = 0000000000000015 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 000000000000007F, => true StartMerge BB15 :: cseOut = 000000000000007F Merge BB15 and BB14 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000001 EndMerge BB15 :: cseIn = 0000000000000001 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 000000000000007F, => true StartMerge BB16 :: cseOut = 000000000000007F Merge BB16 and BB14 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000001 Merge BB16 and BB15 :: cseIn = 0000000000000001 :: cseOut = 000000000000007F => cseIn = 0000000000000001 EndMerge BB16 :: cseIn = 0000000000000001 -- cseKill = 0000000000000015 :: cseGen = 0000000000000004 => cseOut = 0000000000000005 != preMerge = 000000000000007F, => true StartMerge BB14 :: cseOut = 0000000000000001 Merge BB14 and BB10 :: cseIn = 0000000000000001 :: cseOut = 0000000000000001 => cseIn = 0000000000000001 Merge BB14 and BB13 :: cseIn = 0000000000000001 :: cseOut = 0000000000000001 => cseIn = 0000000000000001 EndMerge BB14 :: cseIn = 0000000000000001 -- cseKill = 0000000000000015 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 0000000000000001, => false StartMerge BB16 :: cseOut = 0000000000000005 Merge BB16 and BB14 :: cseIn = 0000000000000001 :: cseOut = 0000000000000005 => cseIn = 0000000000000001 Merge BB16 and BB15 :: cseIn = 0000000000000001 :: cseOut = 0000000000000005 => cseIn = 0000000000000001 EndMerge BB16 :: cseIn = 0000000000000001 -- cseKill = 0000000000000015 :: cseGen = 0000000000000004 => cseOut = 0000000000000005 != preMerge = 0000000000000005, => false StartMerge BB17 :: cseOut = 000000000000007F Merge BB17 and BB15 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000001 EndMerge BB17 :: cseIn = 0000000000000001 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 000000000000007F, => true StartMerge BB44 :: cseOut = 000000000000007F Merge BB44 and BB16 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000005 Merge BB44 and BB30 :: cseIn = 0000000000000005 :: cseOut = 000000000000007F => cseIn = 0000000000000005 Merge BB44 and BB43 :: cseIn = 0000000000000005 :: cseOut = 000000000000007F => cseIn = 0000000000000005 EndMerge BB44 :: cseIn = 0000000000000005 :: cseGen = 0000000000000000 => cseOut = 0000000000000005 != preMerge = 000000000000007F, => true StartMerge BB18 :: cseOut = 000000000000007F Merge BB18 and BB17 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000001 EndMerge BB18 :: cseIn = 0000000000000001 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 000000000000007F, => true StartMerge BB19 :: cseOut = 000000000000007F Merge BB19 and BB17 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000001 EndMerge BB19 :: cseIn = 0000000000000001 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 000000000000007F, => true StartMerge BB20 :: cseOut = 000000000000007F Merge BB20 and BB18 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000001 Merge BB20 and BB19 :: cseIn = 0000000000000001 :: cseOut = 000000000000007F => cseIn = 0000000000000001 EndMerge BB20 :: cseIn = 0000000000000001 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 000000000000007F, => true StartMerge BB20 :: cseOut = 0000000000000001 Merge BB20 and BB18 :: cseIn = 0000000000000001 :: cseOut = 0000000000000001 => cseIn = 0000000000000001 Merge BB20 and BB19 :: cseIn = 0000000000000001 :: cseOut = 0000000000000001 => cseIn = 0000000000000001 EndMerge BB20 :: cseIn = 0000000000000001 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 0000000000000001, => false StartMerge BB21 :: cseOut = 000000000000007F Merge BB21 and BB20 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000001 EndMerge BB21 :: cseIn = 0000000000000001 -- cseKill = 0000000000000015 :: cseGen = 0000000000000001 => cseOut = 0000000000000001 != preMerge = 000000000000007F, => true StartMerge BB23 :: cseOut = 000000000000007F Merge BB23 and BB20 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000001 Merge BB23 and BB21 :: cseIn = 0000000000000001 :: cseOut = 000000000000007F => cseIn = 0000000000000001 EndMerge BB23 :: cseIn = 0000000000000001 -- cseKill = 0000000000000015 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 000000000000007F, => true StartMerge BB22 :: cseOut = 000000000000007F Merge BB22 and BB21 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000001 EndMerge BB22 :: cseIn = 0000000000000001 -- cseKill = 0000000000000015 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 000000000000007F, => true StartMerge BB23 :: cseOut = 0000000000000001 Merge BB23 and BB20 :: cseIn = 0000000000000001 :: cseOut = 0000000000000001 => cseIn = 0000000000000001 Merge BB23 and BB21 :: cseIn = 0000000000000001 :: cseOut = 0000000000000001 => cseIn = 0000000000000001 EndMerge BB23 :: cseIn = 0000000000000001 -- cseKill = 0000000000000015 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 0000000000000001, => false StartMerge BB24 :: cseOut = 000000000000007F Merge BB24 and BB23 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000001 EndMerge BB24 :: cseIn = 0000000000000001 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 000000000000007F, => true StartMerge BB25 :: cseOut = 000000000000007F Merge BB25 and BB23 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000001 EndMerge BB25 :: cseIn = 0000000000000001 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 000000000000007F, => true StartMerge BB26 :: cseOut = 000000000000007F Merge BB26 and BB24 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000001 Merge BB26 and BB25 :: cseIn = 0000000000000001 :: cseOut = 000000000000007F => cseIn = 0000000000000001 EndMerge BB26 :: cseIn = 0000000000000001 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 000000000000007F, => true StartMerge BB26 :: cseOut = 0000000000000001 Merge BB26 and BB24 :: cseIn = 0000000000000001 :: cseOut = 0000000000000001 => cseIn = 0000000000000001 Merge BB26 and BB25 :: cseIn = 0000000000000001 :: cseOut = 0000000000000001 => cseIn = 0000000000000001 EndMerge BB26 :: cseIn = 0000000000000001 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 0000000000000001, => false StartMerge BB27 :: cseOut = 000000000000007F Merge BB27 and BB26 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000001 EndMerge BB27 :: cseIn = 0000000000000001 -- cseKill = 0000000000000015 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 000000000000007F, => true StartMerge BB28 :: cseOut = 000000000000007F Merge BB28 and BB26 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000001 Merge BB28 and BB27 :: cseIn = 0000000000000001 :: cseOut = 000000000000007F => cseIn = 0000000000000001 EndMerge BB28 :: cseIn = 0000000000000001 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 000000000000007F, => true StartMerge BB28 :: cseOut = 0000000000000001 Merge BB28 and BB26 :: cseIn = 0000000000000001 :: cseOut = 0000000000000001 => cseIn = 0000000000000001 Merge BB28 and BB27 :: cseIn = 0000000000000001 :: cseOut = 0000000000000001 => cseIn = 0000000000000001 EndMerge BB28 :: cseIn = 0000000000000001 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 0000000000000001, => false StartMerge BB29 :: cseOut = 000000000000007F Merge BB29 and BB28 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000001 EndMerge BB29 :: cseIn = 0000000000000001 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 000000000000007F, => true StartMerge BB32 :: cseOut = 000000000000007F Merge BB32 and BB28 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000001 Merge BB32 and BB31 :: cseIn = 0000000000000001 :: cseOut = 000000000000007F => cseIn = 0000000000000001 EndMerge BB32 :: cseIn = 0000000000000001 -- cseKill = 0000000000000015 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 000000000000007F, => true StartMerge BB30 :: cseOut = 000000000000007F Merge BB30 and BB29 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000001 EndMerge BB30 :: cseIn = 0000000000000001 -- cseKill = 0000000000000015 :: cseGen = 0000000000000004 => cseOut = 0000000000000005 != preMerge = 000000000000007F, => true StartMerge BB31 :: cseOut = 000000000000007F Merge BB31 and BB29 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000001 EndMerge BB31 :: cseIn = 0000000000000001 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 000000000000007F, => true StartMerge BB33 :: cseOut = 000000000000007F Merge BB33 and BB32 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000001 EndMerge BB33 :: cseIn = 0000000000000001 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 000000000000007F, => true StartMerge BB34 :: cseOut = 000000000000007F Merge BB34 and BB32 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000001 EndMerge BB34 :: cseIn = 0000000000000001 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 000000000000007F, => true StartMerge BB44 :: cseOut = 0000000000000005 Merge BB44 and BB16 :: cseIn = 0000000000000005 :: cseOut = 0000000000000005 => cseIn = 0000000000000005 Merge BB44 and BB30 :: cseIn = 0000000000000005 :: cseOut = 0000000000000005 => cseIn = 0000000000000005 Merge BB44 and BB43 :: cseIn = 0000000000000005 :: cseOut = 0000000000000005 => cseIn = 0000000000000005 EndMerge BB44 :: cseIn = 0000000000000005 :: cseGen = 0000000000000000 => cseOut = 0000000000000005 != preMerge = 0000000000000005, => false StartMerge BB32 :: cseOut = 0000000000000001 Merge BB32 and BB28 :: cseIn = 0000000000000001 :: cseOut = 0000000000000001 => cseIn = 0000000000000001 Merge BB32 and BB31 :: cseIn = 0000000000000001 :: cseOut = 0000000000000001 => cseIn = 0000000000000001 EndMerge BB32 :: cseIn = 0000000000000001 -- cseKill = 0000000000000015 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 0000000000000001, => false StartMerge BB35 :: cseOut = 000000000000007F Merge BB35 and BB33 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000001 Merge BB35 and BB34 :: cseIn = 0000000000000001 :: cseOut = 000000000000007F => cseIn = 0000000000000001 EndMerge BB35 :: cseIn = 0000000000000001 -- cseKill = 0000000000000015 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 000000000000007F, => true StartMerge BB35 :: cseOut = 0000000000000001 Merge BB35 and BB33 :: cseIn = 0000000000000001 :: cseOut = 0000000000000001 => cseIn = 0000000000000001 Merge BB35 and BB34 :: cseIn = 0000000000000001 :: cseOut = 0000000000000001 => cseIn = 0000000000000001 EndMerge BB35 :: cseIn = 0000000000000001 -- cseKill = 0000000000000015 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 0000000000000001, => false StartMerge BB36 :: cseOut = 000000000000007F Merge BB36 and BB35 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000001 EndMerge BB36 :: cseIn = 0000000000000001 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 000000000000007F, => true StartMerge BB40 :: cseOut = 000000000000007F Merge BB40 and BB35 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000001 Merge BB40 and BB39 :: cseIn = 0000000000000001 :: cseOut = 000000000000007F => cseIn = 0000000000000001 EndMerge BB40 :: cseIn = 0000000000000001 -- cseKill = 0000000000000015 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 000000000000007F, => true StartMerge BB37 :: cseOut = 000000000000007F Merge BB37 and BB36 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000001 EndMerge BB37 :: cseIn = 0000000000000001 :: cseGen = 0000000000000030 => cseOut = 0000000000000031 != preMerge = 000000000000007F, => true StartMerge BB38 :: cseOut = 000000000000007F Merge BB38 and BB36 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000001 EndMerge BB38 :: cseIn = 0000000000000001 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 000000000000007F, => true StartMerge BB41 :: cseOut = 000000000000007F Merge BB41 and BB40 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000001 EndMerge BB41 :: cseIn = 0000000000000001 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 000000000000007F, => true StartMerge BB42 :: cseOut = 000000000000007F Merge BB42 and BB40 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000001 EndMerge BB42 :: cseIn = 0000000000000001 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 000000000000007F, => true StartMerge BB39 :: cseOut = 000000000000007F Merge BB39 and BB37 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000031 Merge BB39 and BB38 :: cseIn = 0000000000000031 :: cseOut = 000000000000007F => cseIn = 0000000000000001 EndMerge BB39 :: cseIn = 0000000000000001 :: cseGen = 0000000000000030 => cseOut = 0000000000000031 != preMerge = 000000000000007F, => true StartMerge BB39 :: cseOut = 0000000000000031 Merge BB39 and BB37 :: cseIn = 0000000000000001 :: cseOut = 0000000000000031 => cseIn = 0000000000000001 Merge BB39 and BB38 :: cseIn = 0000000000000001 :: cseOut = 0000000000000031 => cseIn = 0000000000000001 EndMerge BB39 :: cseIn = 0000000000000001 :: cseGen = 0000000000000030 => cseOut = 0000000000000031 != preMerge = 0000000000000031, => false StartMerge BB43 :: cseOut = 000000000000007F Merge BB43 and BB41 :: cseIn = 000000000000007F :: cseOut = 000000000000007F => cseIn = 0000000000000001 Merge BB43 and BB42 :: cseIn = 0000000000000001 :: cseOut = 000000000000007F => cseIn = 0000000000000001 EndMerge BB43 :: cseIn = 0000000000000001 -- cseKill = 0000000000000015 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 000000000000007F, => true StartMerge BB43 :: cseOut = 0000000000000001 Merge BB43 and BB41 :: cseIn = 0000000000000001 :: cseOut = 0000000000000001 => cseIn = 0000000000000001 Merge BB43 and BB42 :: cseIn = 0000000000000001 :: cseOut = 0000000000000001 => cseIn = 0000000000000001 EndMerge BB43 :: cseIn = 0000000000000001 -- cseKill = 0000000000000015 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 0000000000000001, => false StartMerge BB40 :: cseOut = 0000000000000001 Merge BB40 and BB35 :: cseIn = 0000000000000001 :: cseOut = 0000000000000001 => cseIn = 0000000000000001 Merge BB40 and BB39 :: cseIn = 0000000000000001 :: cseOut = 0000000000000001 => cseIn = 0000000000000001 EndMerge BB40 :: cseIn = 0000000000000001 -- cseKill = 0000000000000015 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 0000000000000001, => false StartMerge BB44 :: cseOut = 0000000000000005 Merge BB44 and BB16 :: cseIn = 0000000000000005 :: cseOut = 0000000000000005 => cseIn = 0000000000000005 Merge BB44 and BB30 :: cseIn = 0000000000000005 :: cseOut = 0000000000000005 => cseIn = 0000000000000005 Merge BB44 and BB43 :: cseIn = 0000000000000005 :: cseOut = 0000000000000005 => cseIn = 0000000000000001 EndMerge BB44 :: cseIn = 0000000000000001 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 0000000000000005, => true After performing DataFlow for ValnumCSE's BB01 cseIn = 0000000000000000, cseGen = 0000000000000000, cseOut = 0000000000000000 BB02 cseIn = 0000000000000000, cseGen = 0000000000000003, cseOut = 0000000000000003 BB03 cseIn = 0000000000000003, cseGen = 0000000000000000, cseOut = 0000000000000001 BB04 cseIn = 0000000000000003, cseGen = 0000000000000000, cseOut = 0000000000000001 BB05 cseIn = 0000000000000001, cseGen = 0000000000000000, cseOut = 0000000000000001 BB06 cseIn = 0000000000000001, cseGen = 0000000000000000, cseOut = 0000000000000001 BB07 cseIn = 0000000000000001, cseGen = 0000000000000003, cseOut = 0000000000000003 BB08 cseIn = 0000000000000003, cseGen = 0000000000000000, cseOut = 0000000000000003 BB09 cseIn = 0000000000000003, cseGen = 0000000000000000, cseOut = 0000000000000003 BB10 cseIn = 0000000000000003, cseGen = 0000000000000001, cseOut = 0000000000000001 BB11 cseIn = 0000000000000001, cseGen = 0000000000000000, cseOut = 0000000000000001 BB12 cseIn = 0000000000000001, cseGen = 0000000000000000, cseOut = 0000000000000001 BB13 cseIn = 0000000000000001, cseGen = 0000000000000000, cseOut = 0000000000000001 BB14 cseIn = 0000000000000001, cseGen = 0000000000000000, cseOut = 0000000000000001 BB15 cseIn = 0000000000000001, cseGen = 0000000000000000, cseOut = 0000000000000001 BB16 cseIn = 0000000000000001, cseGen = 0000000000000004, cseOut = 0000000000000005 BB17 cseIn = 0000000000000001, cseGen = 0000000000000000, cseOut = 0000000000000001 BB18 cseIn = 0000000000000001, cseGen = 0000000000000000, cseOut = 0000000000000001 BB19 cseIn = 0000000000000001, cseGen = 0000000000000000, cseOut = 0000000000000001 BB20 cseIn = 0000000000000001, cseGen = 0000000000000000, cseOut = 0000000000000001 BB21 cseIn = 0000000000000001, cseGen = 0000000000000001, cseOut = 0000000000000001 BB22 cseIn = 0000000000000001, cseGen = 0000000000000000, cseOut = 0000000000000001 BB23 cseIn = 0000000000000001, cseGen = 0000000000000000, cseOut = 0000000000000001 BB24 cseIn = 0000000000000001, cseGen = 0000000000000000, cseOut = 0000000000000001 BB25 cseIn = 0000000000000001, cseGen = 0000000000000000, cseOut = 0000000000000001 BB26 cseIn = 0000000000000001, cseGen = 0000000000000000, cseOut = 0000000000000001 BB27 cseIn = 0000000000000001, cseGen = 0000000000000000, cseOut = 0000000000000001 BB28 cseIn = 0000000000000001, cseGen = 0000000000000000, cseOut = 0000000000000001 BB29 cseIn = 0000000000000001, cseGen = 0000000000000000, cseOut = 0000000000000001 BB30 cseIn = 0000000000000001, cseGen = 0000000000000004, cseOut = 0000000000000005 BB31 cseIn = 0000000000000001, cseGen = 0000000000000000, cseOut = 0000000000000001 BB32 cseIn = 0000000000000001, cseGen = 0000000000000000, cseOut = 0000000000000001 BB33 cseIn = 0000000000000001, cseGen = 0000000000000000, cseOut = 0000000000000001 BB34 cseIn = 0000000000000001, cseGen = 0000000000000000, cseOut = 0000000000000001 BB35 cseIn = 0000000000000001, cseGen = 0000000000000000, cseOut = 0000000000000001 BB36 cseIn = 0000000000000001, cseGen = 0000000000000000, cseOut = 0000000000000001 BB37 cseIn = 0000000000000001, cseGen = 0000000000000030, cseOut = 0000000000000031 BB38 cseIn = 0000000000000001, cseGen = 0000000000000000, cseOut = 0000000000000001 BB39 cseIn = 0000000000000001, cseGen = 0000000000000030, cseOut = 0000000000000031 BB40 cseIn = 0000000000000001, cseGen = 0000000000000000, cseOut = 0000000000000001 BB41 cseIn = 0000000000000001, cseGen = 0000000000000000, cseOut = 0000000000000001 BB42 cseIn = 0000000000000001, cseGen = 0000000000000000, cseOut = 0000000000000001 BB43 cseIn = 0000000000000001, cseGen = 0000000000000000, cseOut = 0000000000000001 BB44 cseIn = 0000000000000001, cseGen = 0000000000000000, cseOut = 0000000000000001 Labeling the CSEs with Use/Def information BB02 [000003] Def of CSE #01 [weight=1 ] BB07 [000429] Use of CSE #01 [weight=0.50] *** Now Live Across Call *** BB10 [000448] Use of CSE #01 [weight=0.50] BB16 [000086] Def of CSE #02 [weight=0.50] BB21 [000456] Use of CSE #01 [weight=0.50] BB30 [000339] Def of CSE #02 [weight=0.50] BB37 [000310] Def of CSE #03 [weight=0.50] BB39 [000301] Def of CSE #03 [weight=0.50] ************ Trees at start of optValnumCSE_Heuristic() ------------ BB01 [???..???), preds={} succs={BB02} ***** BB01 STMT00111 (IL ???... ???) N011 ( 7, 7) [000540] -A---------- * COMMA void N004 ( 3, 3) [000533] -A------R--- +--* ASG ref N003 ( 1, 1) [000530] D------N---- | +--* LCL_VAR ref V52 tmp22 d:2 N002 ( 3, 2) [000532] n----------- | \--* IND ref N001 ( 1, 1) [000531] ------------ | \--* LCL_VAR byref V00 arg0 u:1 Zero Fseq[Mantissa] $80 N010 ( 4, 4) [000539] -A------R--- \--* ASG int N009 ( 1, 1) [000534] D------N---- +--* LCL_VAR int V53 tmp23 d:2 N008 ( 4, 4) [000538] n----------- \--* IND int N007 ( 2, 2) [000537] -------N---- \--* ADD byref $200 N005 ( 1, 1) [000535] ------------ +--* LCL_VAR byref V00 arg0 u:1 (last use) $80 N006 ( 1, 1) [000536] ------------ \--* CNS_INT long 8 Fseq[Exponent] $101 ------------ BB02 [000..00D) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00000 (IL 0x000...0x00B) N005 ( 7, 7) [000006] ---XG------- * JTRUE void N004 ( 5, 5) [000005] J--XG--N---- \--* NE int N002 ( 3, 3) CSE #01 (def)[000003] ---XG------- +--* ARR_LENGTH int N001 ( 1, 1) [000002] ------------ | \--* LCL_VAR ref V52 tmp22 u:2 N003 ( 1, 1) [000004] ------------ \--* CNS_INT int 0 $40 ------------ BB03 [00D..017) (return), preds={BB02} succs={} ***** BB03 STMT00087 (IL 0x00D...0x014) N006 ( 25, 13) [000403] -ACXG---R--- * ASG long $VN.Void N005 ( 3, 2) [000402] *--X---N---- +--* IND long $459 N004 ( 1, 1) [000399] ------------ | \--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N003 ( 21, 10) [000401] --CXG------- \--* CALLV ind long FloatingPointType.get_Zero $459 N002 ( 1, 1) [000400] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 ***** BB03 STMT00107 (IL ???... ???) N002 ( 2, 2) [000520] ------------ * RETURN int $5cb N001 ( 1, 1) [000404] ------------ \--* CNS_INT int 1 $41 ------------ BB04 [017..065) -> BB06 (cond), preds={BB02} succs={BB05,BB06} ***** BB04 STMT00002 (IL ???... ???) N010 ( 30, 19) [000013] -ACXG---R--- * ASG int $348 N009 ( 3, 2) [000012] D------N---- +--* LCL_VAR int V03 loc0 d:2 $348 N008 ( 26, 16) [000011] --CXG------- \--* ADD int $348 N006 ( 24, 14) [000409] --CXG------- +--* CAST int <- ushort <- int $347 N005 ( 23, 12) [000408] --CXG------- | \--* ADD int $346 N003 ( 21, 10) [000406] --CXG------- | +--* CALLV ind int FloatingPointType.get_DenormalMantissaBits $282 N002 ( 1, 1) [000007] ------------ this in rcx | | \--* LCL_VAR ref V01 arg1 u:1 $c0 N004 ( 1, 1) [000407] ------------ | \--* CNS_INT int 1 $41 N007 ( 1, 1) [000010] ------------ \--* CNS_INT int 1 $41 ***** BB04 STMT00092 (IL 0x020... ???) N003 ( 5, 4) [000424] -A--G---R--- * ASG int N002 ( 3, 2) [000423] D------N---- +--* LCL_VAR int V40 tmp10 d:2 N001 ( 1, 1) [000017] ------------ \--* LCL_VAR int V53 tmp23 u:2 ***** BB04 STMT00089 (IL 0x020... ???) N004 ( 5, 5) [000414] ------------ * JTRUE void N003 ( 3, 3) [000413] J------N---- \--* LE int N001 ( 1, 1) [000412] ------------ +--* LCL_VAR int V40 tmp10 u:2 N002 ( 1, 1) [000411] ------------ \--* CNS_INT int 0 $40 ------------ BB05 [020..021) -> BB07 (always), preds={BB04} succs={BB07} ***** BB05 STMT00091 (IL 0x020... ???) N003 ( 7, 5) [000421] -A------R--- * ASG int N002 ( 3, 2) [000420] D------N---- +--* LCL_VAR int V39 tmp9 d:4 N001 ( 3, 2) [000419] ------------ \--* LCL_VAR int V53 tmp23 u:2 (last use) ------------ BB06 [020..021), preds={BB04} succs={BB07} ***** BB06 STMT00090 (IL 0x020... ???) N003 ( 5, 4) [000417] -A------R--- * ASG int $40 N002 ( 3, 2) [000416] D------N---- +--* LCL_VAR int V39 tmp9 d:3 $40 N001 ( 1, 1) [000415] ------------ \--* CNS_INT int 0 $40 ------------ BB07 [000..000) -> BB09 (cond), preds={BB05,BB06} succs={BB08,BB09} ***** BB07 STMT00122 (IL ???... ???) N005 ( 0, 0) [000886] -A------R--- * ASG int N004 ( 0, 0) [000884] D------N---- +--* LCL_VAR int V39 tmp9 d:2 N003 ( 0, 0) [000885] ------------ \--* PHI int N001 ( 0, 0) [000909] ------------ pred BB05 +--* PHI_ARG int V39 tmp9 u:4 N002 ( 0, 0) [000908] ------------ pred BB06 \--* PHI_ARG int V39 tmp9 u:3 $40 ***** BB07 STMT00004 (IL ???... ???) N003 ( 3, 3) [000021] -A------R--- * ASG int $241 N002 ( 1, 1) [000020] D------N---- +--* LCL_VAR int V31 tmp1 d:2 $241 N001 ( 3, 2) [000422] ------------ \--* LCL_VAR int V39 tmp9 u:2 $241 ***** BB07 STMT00096 (IL ???... ???) N004 ( 3, 3) [000443] -A-XG---R--- * ASG int N003 ( 1, 1) [000442] D------N---- +--* LCL_VAR int V42 tmp12 d:2 N002 ( 3, 3) CSE #01 (use)[000429] ---XG------- \--* ARR_LENGTH int N001 ( 1, 1) [000428] ------------ \--* LCL_VAR ref V52 tmp22 u:2 ***** BB07 STMT00093 (IL ???... ???) N004 ( 7, 6) [000433] ------------ * JTRUE void N003 ( 5, 4) [000432] N------N-U-- \--* LE int N001 ( 3, 2) [000023] ------------ +--* LCL_VAR int V31 tmp1 u:2 (last use) $241 N002 ( 1, 1) [000431] ------------ \--* LCL_VAR int V42 tmp12 u:2 ------------ BB08 [000..000) -> BB10 (always), preds={BB07} succs={BB10} ***** BB08 STMT00095 (IL ???... ???) N003 ( 1, 3) [000440] -A------R--- * ASG int N002 ( 1, 1) [000439] D------N---- +--* LCL_VAR int V41 tmp11 d:4 N001 ( 1, 1) [000438] ------------ \--* LCL_VAR int V42 tmp12 u:2 (last use) ------------ BB09 [000..000), preds={BB07} succs={BB10} ***** BB09 STMT00094 (IL ???... ???) N003 ( 1, 3) [000436] -A------R--- * ASG int $241 N002 ( 1, 1) [000435] D------N---- +--* LCL_VAR int V41 tmp11 d:3 $241 N001 ( 1, 1) [000434] ------------ \--* LCL_VAR int V31 tmp1 u:2 $241 ------------ BB10 [???..???) -> BB14 (cond), preds={BB08,BB09} succs={BB11,BB14} ***** BB10 STMT00121 (IL ???... ???) N005 ( 0, 0) [000883] -A------R--- * ASG int N004 ( 0, 0) [000881] D------N---- +--* LCL_VAR int V41 tmp11 d:2 N003 ( 0, 0) [000882] ------------ \--* PHI int N001 ( 0, 0) [000907] ------------ pred BB08 +--* PHI_ARG int V41 tmp11 u:4 N002 ( 0, 0) [000906] ------------ pred BB09 \--* PHI_ARG int V41 tmp11 u:3 $241 ***** BB10 STMT00008 (IL ???...0x03C) N005 ( 7, 6) [000035] -A------R--- * ASG int $34e N004 ( 3, 2) [000034] D------N---- +--* LCL_VAR int V05 loc2 d:2 $34e N003 ( 3, 3) [000033] ------------ \--* SUB int $34e N001 ( 1, 1) [000022] ------------ +--* LCL_VAR int V31 tmp1 u:2 (last use) $241 N002 ( 1, 1) [000032] ------------ \--* LCL_VAR int V41 tmp11 u:2 $242 ***** BB10 STMT00011 (IL 0x042...0x044) N003 ( 5, 4) [000044] -A------R--- * ASG int $242 N002 ( 3, 2) [000043] D------N---- +--* LCL_VAR int V08 loc5 d:2 $242 N001 ( 1, 1) [000042] ------------ \--* LCL_VAR int V41 tmp11 u:2 $242 ***** BB10 STMT00013 (IL ???... ???) N004 ( 7, 6) [000050] -A-XG---R--- * ASG int N003 ( 3, 2) [000049] D------N---- +--* LCL_VAR int V09 loc6 d:2 N002 ( 3, 3) CSE #01 (use)[000448] ---XG------- \--* ARR_LENGTH int N001 ( 1, 1) [000447] ------------ \--* LCL_VAR ref V52 tmp22 u:2 ***** BB10 STMT00014 (IL 0x04F...0x054) N005 ( 5, 4) [000055] -A------R--- * ASG int N004 ( 1, 1) [000054] D------N---- +--* LCL_VAR int V10 loc7 d:2 N003 ( 5, 4) [000053] ------------ \--* SUB int N001 ( 3, 2) [000051] ------------ +--* LCL_VAR int V09 loc6 u:2 N002 ( 1, 1) [000052] ------------ \--* LCL_VAR int V08 loc5 u:2 $242 ***** BB10 STMT00016 (IL ???... ???) N028 ( 49, 35) [000059] SACXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger $VN.Void N004 ( 7, 6) [000563] -A------R-L- arg0 SETUP +--* ASG long $400 N003 ( 3, 2) [000562] D------N---- | +--* LCL_VAR long V75 tmp45 d:2 $400 N002 ( 3, 3) [000064] ------------ | \--* ADDR long $400 N001 ( 3, 2) [000063] ----G--N---- | \--* LCL_VAR struct(AX)(P) V11 loc8 | \--* ref V11._bits (offs=0x00) -> V54 tmp24 | \--* int V11._sign (offs=0x08) -> V55 tmp25 $3c0 N020 ( 14, 13) [000561] -A--------L- arg1 SETUP +--* COMMA void $VN.Void N013 ( 8, 7) [000554] -A---------- | +--* COMMA void $VN.Void N008 ( 3, 3) [000549] -A------R--- | | +--* ASG byref $401 N007 ( 1, 1) [000548] D------N---- | | | +--* LCL_VAR byref V74 tmp44 d:2 $401 N006 ( 3, 3) [000546] ------------ | | | \--* ADDR byref $401 N005 ( 3, 2) [000547] -------N---- | | | \--* LCL_VAR struct(AX) V73 tmp43 $3c1 N012 ( 5, 4) [000553] -A---------- | | \--* ASG ref $VN.Void N010 ( 3, 2) [000551] *------N---- | | +--* IND ref N009 ( 1, 1) [000550] ------------ | | | \--* LCL_VAR byref V74 tmp44 u:2 Zero Fseq[Mantissa] $401 N011 ( 1, 1) [000552] -------N---- | | \--* LCL_VAR ref V52 tmp22 u:2 N019 ( 6, 6) [000560] -A---------- | \--* ASG int $VN.Void N017 ( 4, 4) [000558] *------N---- | +--* IND int N016 ( 2, 2) [000557] -------N---- | | \--* ADD byref $203 N014 ( 1, 1) [000555] ------------ | | +--* LCL_VAR byref V74 tmp44 u:2 (last use) $401 N015 ( 1, 1) [000556] ------------ | | \--* CNS_INT long 8 Fseq[Exponent] $101 N018 ( 1, 1) [000559] -------N---- | \--* LCL_VAR int V53 tmp23 u:2 N023 ( 3, 2) [000564] ------------ arg0 in rcx +--* LCL_VAR long V75 tmp45 u:2 (last use) $400 N025 ( 3, 3) [000566] ------------ arg1 in rdx +--* ADDR byref $403 N024 ( 3, 2) [000565] -------N---- | \--* LCL_VAR struct(AX) V73 tmp43 $3c2 N026 ( 1, 1) [000058] ------------ arg3 in r9 +--* LCL_VAR int V08 loc5 u:2 (last use) $242 N027 ( 1, 1) [000057] ------------ arg2 in r8 \--* CNS_INT int 0 $40 ***** BB10 STMT00017 (IL 0x061...0x063) N004 ( 7, 6) [000068] ------------ * JTRUE void N003 ( 5, 4) [000067] N------N---- \--* EQ int $351 N001 ( 3, 2) [000065] ------------ +--* LCL_VAR int V05 loc2 u:2 $34e N002 ( 1, 1) [000066] ------------ \--* CNS_INT int 0 $40 ------------ BB11 [065..070) -> BB13 (cond), preds={BB10} succs={BB12,BB13} ***** BB11 STMT00083 (IL ???... ???) N008 ( 23, 17) [000387] --CXG------- * JTRUE void N007 ( 21, 15) [000386] J-CXG--N---- \--* GE int $352 N004 ( 16, 10) [000385] --CXG------- +--* CAST long <- int $480 N003 ( 15, 8) [000383] --CXG------- | \--* CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent $291 N002 ( 1, 1) [000382] ------------ this in rcx | \--* LCL_VAR ref V01 arg1 u:1 $c0 N006 ( 4, 4) [000381] ---------U-- \--* CAST long <- ulong <- uint $481 N005 ( 3, 2) [000380] ------------ \--* LCL_VAR int V05 loc2 u:2 $34e ------------ BB12 [070..07A) (return), preds={BB11} succs={} ***** BB12 STMT00085 (IL 0x070...0x077) N006 ( 25, 13) [000396] -ACXG---R--- * ASG long $VN.Void N005 ( 3, 2) [000395] *--X---N---- +--* IND long $458 N004 ( 1, 1) [000392] ------------ | \--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N003 ( 21, 10) [000394] --CXG------- \--* CALLV ind long FloatingPointType.get_Infinity $458 N002 ( 1, 1) [000393] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 ***** BB12 STMT00108 (IL ???... ???) N002 ( 2, 2) [000521] ------------ * RETURN int $5ca N001 ( 1, 1) [000397] ------------ \--* CNS_INT int 3 $48 ------------ BB13 [07A..082), preds={BB11} succs={BB14} ***** BB13 STMT00084 (IL 0x07A...0x07D) N006 ( 20, 12) [000391] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen $VN.Void N004 ( 3, 3) [000389] ------------ arg0 in rcx +--* ADDR long $404 N003 ( 3, 2) [000388] ----G--N---- | \--* LCL_VAR struct(AX)(P) V11 loc8 | \--* ref V11._bits (offs=0x00) -> V54 tmp24 | \--* int V11._sign (offs=0x08) -> V55 tmp25 $3c3 N005 ( 3, 2) [000390] ------------ arg1 in rdx \--* LCL_VAR int V05 loc2 u:2 (last use) $34e ------------ BB14 [082..092) -> BB16 (cond), preds={BB10,BB13} succs={BB15,BB16} ***** BB14 STMT00019 (IL ???... ???) N023 ( 41, 28) [000077] -ACXG---R--- * ASG int $293 N022 ( 1, 1) [000076] D------N---- +--* LCL_VAR int V13 loc10 d:2 $293 N021 ( 41, 28) [000072] -ACXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $293 N016 ( 18, 15) [000591] -A--G-----L- arg0 SETUP +--* COMMA void $VN.Void N009 ( 10, 8) [000584] -A--G------- | +--* COMMA void $VN.Void N004 ( 3, 3) [000579] -A------R--- | | +--* ASG byref $405 N003 ( 1, 1) [000578] D------N---- | | | +--* LCL_VAR byref V77 tmp47 d:2 $405 N002 ( 3, 3) [000576] ------------ | | | \--* ADDR byref $405 N001 ( 3, 2) [000577] -------N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 $3c4 N008 ( 7, 5) [000583] -A--G------- | | \--* ASG ref $VN.Void N006 ( 3, 2) [000581] *------N---- | | +--* IND ref $181 N005 ( 1, 1) [000580] ------------ | | | \--* LCL_VAR byref V77 tmp47 u:2 Zero Fseq[_bits] $405 N007 ( 3, 2) [000582] ----G--N---- | | \--* LCL_VAR ref (AX) V54 tmp24 $181 N015 ( 8, 7) [000590] -A--G------- | \--* ASG int $VN.Void N013 ( 4, 4) [000588] *------N---- | +--* IND int $243 N012 ( 2, 2) [000587] -------N---- | | \--* ADD byref $206 N010 ( 1, 1) [000585] ------------ | | +--* LCL_VAR byref V77 tmp47 u:2 (last use) $405 N011 ( 1, 1) [000586] ------------ | | \--* CNS_INT long 8 Fseq[_sign] $101 N014 ( 3, 2) [000589] ----G--N---- | \--* LCL_VAR int (AX) V55 tmp25 $243 N019 ( 3, 3) [000593] ------------ arg0 in rcx +--* ADDR byref $407 N018 ( 3, 2) [000592] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 $3c5 N020 ( 3, 3) [000071] ------------ arg1 in rdx \--* LCL_VAR_ADDR long V12 loc9 $443 ***** BB14 STMT00020 (IL 0x08D...0x090) N004 ( 7, 6) [000081] ------------ * JTRUE void N003 ( 5, 4) [000080] N------N-U-- \--* GE int $353 N001 ( 1, 1) [000078] ------------ +--* LCL_VAR int V13 loc10 u:2 $293 N002 ( 3, 2) [000079] ------------ \--* LCL_VAR int V03 loc0 u:2 $348 ------------ BB15 [092..096) -> BB17 (cond), preds={BB14} succs={BB16,BB17} ***** BB15 STMT00022 (IL 0x092...0x094) N004 ( 5, 5) [000094] ------------ * JTRUE void N003 ( 3, 3) [000093] J------N---- \--* NE int N001 ( 1, 1) [000091] ------------ +--* LCL_VAR int V10 loc7 u:2 N002 ( 1, 1) [000092] ------------ \--* CNS_INT int 0 $40 ------------ BB16 [096..0A7) -> BB44 (always), preds={BB14,BB15} succs={BB44} ***** BB16 STMT00021 (IL 0x096...0x0A6) N014 ( 29, 17) [000600] -ACXG---R--- * ASG int $5c7 N013 ( 1, 1) [000599] D------N---- +--* LCL_VAR int V51 tmp21 d:3 $5c7 N012 ( 29, 17) [000089] --CXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits $5c7 N005 ( 1, 1) [000088] ------------ arg4 out+20 +--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N008 ( 6, 3) CSE #02 (def)[000086] N----------- arg2 in r8 +--* NE int N006 ( 1, 1) [000084] ------------ | +--* LCL_VAR int V10 loc7 u:2 (last use) N007 ( 1, 1) [000085] ------------ | \--* CNS_INT int 0 $40 N009 ( 3, 2) [000082] ----G------- arg0 in rcx +--* LCL_VAR ref (AX) V12 loc9 $18d N010 ( 1, 1) [000083] ------------ arg1 in rdx +--* LCL_VAR int V13 loc10 u:2 (last use) $293 N011 ( 1, 1) [000087] ------------ arg3 in r9 \--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 ------------ BB17 [0A7..0B0) -> BB19 (cond), preds={BB15} succs={BB18,BB19} ***** BB17 STMT00023 (IL 0x0A7...0x0AE) N004 ( 5, 5) [000100] ----G------- * JTRUE void N003 ( 3, 3) [000099] J---G--N---- \--* LT int N001 ( 1, 1) [000097] ------------ +--* LCL_VAR int V53 tmp23 u:2 N002 ( 1, 1) [000098] ------------ \--* CNS_INT int 0 $40 ------------ BB18 [0B0..0B4) -> BB20 (always), preds={BB17} succs={BB20} ***** BB18 STMT00081 (IL 0x0B0...0x0B2) N003 ( 5, 4) [000378] -A------R--- * ASG int N002 ( 3, 2) [000377] D------N---- +--* LCL_VAR int V32 tmp2 d:4 N001 ( 1, 1) [000376] ------------ \--* LCL_VAR int V10 loc7 u:2 ------------ BB19 [0B4..0BE), preds={BB17} succs={BB20} ***** BB19 STMT00024 (IL 0x0B4...0x0BD) N005 ( 7, 6) [000108] -A--G---R--- * ASG int N004 ( 3, 2) [000107] D------N---- +--* LCL_VAR int V32 tmp2 d:3 N003 ( 3, 3) [000106] ----G------- \--* SUB int N001 ( 1, 1) [000101] ------------ +--* LCL_VAR int V10 loc7 u:2 N002 ( 1, 1) [000104] ------------ \--* LCL_VAR int V53 tmp23 u:2 ------------ BB20 [0BE..0C4) -> BB23 (cond), preds={BB18,BB19} succs={BB21,BB23} ***** BB20 STMT00120 (IL ???... ???) N005 ( 0, 0) [000880] -A------R--- * ASG int N004 ( 0, 0) [000878] D------N---- +--* LCL_VAR int V32 tmp2 d:2 N003 ( 0, 0) [000879] ------------ \--* PHI int N001 ( 0, 0) [000905] ------------ pred BB18 +--* PHI_ARG int V32 tmp2 u:4 N002 ( 0, 0) [000904] ------------ pred BB19 \--* PHI_ARG int V32 tmp2 u:3 ***** BB20 STMT00025 (IL ???...0x0BE) N003 ( 7, 5) [000112] -A------R--- * ASG int $244 N002 ( 3, 2) [000111] D------N---- +--* LCL_VAR int V14 loc11 d:2 $244 N001 ( 3, 2) [000110] ------------ \--* LCL_VAR int V32 tmp2 u:2 (last use) $244 ***** BB20 STMT00026 (IL 0x0C0...0x0C2) N004 ( 5, 5) [000116] ------------ * JTRUE void N003 ( 3, 3) [000115] J------N---- \--* NE int $35a N001 ( 1, 1) [000113] ------------ +--* LCL_VAR int V13 loc10 u:2 $293 N002 ( 1, 1) [000114] ------------ \--* CNS_INT int 0 $40 ------------ BB21 [0C4..0D9) -> BB23 (cond), preds={BB20} succs={BB22,BB23} ***** BB21 STMT00077 (IL ???... ???) N008 ( 13, 13) [000363] -A-XG---R--- * ASG long N007 ( 3, 2) [000362] D------N---- +--* LCL_VAR long V38 tmp8 d:2 N006 ( 9, 10) [000359] ---XG---R--- \--* SUB long N005 ( 4, 4) [000353] ---------U-- +--* CAST long <- ulong <- uint $486 N004 ( 3, 2) [000352] ------------ | \--* LCL_VAR int V14 loc11 u:2 $244 N003 ( 4, 5) [000358] ---XG------- \--* CAST long <- int N002 ( 3, 3) CSE #01 (use)[000456] ---XG------- \--* ARR_LENGTH int N001 ( 1, 1) [000455] ------------ \--* LCL_VAR ref V52 tmp22 u:2 ***** BB21 STMT00078 (IL ???... ???) N007 ( 22, 15) [000368] --CXG------- * JTRUE void N006 ( 20, 13) [000367] J-CXG--N---- \--* GE int N004 ( 16, 10) [000366] --CXG------- +--* CAST long <- int $48b N003 ( 15, 8) [000361] --CXG------- | \--* CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent $298 N002 ( 1, 1) [000360] ------------ this in rcx | \--* LCL_VAR ref V01 arg1 u:1 $c0 N005 ( 3, 2) [000364] ------------ \--* LCL_VAR long V38 tmp8 u:2 (last use) ------------ BB22 [0D9..0E3) (return), preds={BB21} succs={} ***** BB22 STMT00079 (IL 0x0D9...0x0E0) N006 ( 25, 13) [000373] -ACXG---R--- * ASG long $VN.Void N005 ( 3, 2) [000372] *--X---N---- +--* IND long $457 N004 ( 1, 1) [000369] ------------ | \--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N003 ( 21, 10) [000371] --CXG------- \--* CALLV ind long FloatingPointType.get_Zero $457 N002 ( 1, 1) [000370] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 ***** BB22 STMT00110 (IL ???... ???) N002 ( 2, 2) [000524] ------------ * RETURN int $5c4 N001 ( 1, 1) [000374] ------------ \--* CNS_INT int 2 $42 ------------ BB23 [0E3..117) -> BB25 (cond), preds={BB20,BB21} succs={BB24,BB25} ***** BB23 STMT00028 (IL ???... ???) N028 ( 53, 37) [000120] SACXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger $VN.Void N004 ( 7, 6) [000623] -A------R-L- arg0 SETUP +--* ASG long $408 N003 ( 3, 2) [000622] D------N---- | +--* LCL_VAR long V79 tmp49 d:2 $408 N002 ( 3, 3) [000125] ------------ | \--* ADDR long $408 N001 ( 3, 2) [000124] ----G--N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 $3c6 N020 ( 14, 13) [000621] -A--------L- arg1 SETUP +--* COMMA void $VN.Void N013 ( 8, 7) [000614] -A---------- | +--* COMMA void $VN.Void N008 ( 3, 3) [000609] -A------R--- | | +--* ASG byref $409 N007 ( 1, 1) [000608] D------N---- | | | +--* LCL_VAR byref V78 tmp48 d:2 $409 N006 ( 3, 3) [000606] ------------ | | | \--* ADDR byref $409 N005 ( 3, 2) [000607] ----G--N---- | | | \--* LCL_VAR struct(AX) V73 tmp43 $3c7 N012 ( 5, 4) [000613] -A---------- | | \--* ASG ref $VN.Void N010 ( 3, 2) [000611] *------N---- | | +--* IND ref N009 ( 1, 1) [000610] ------------ | | | \--* LCL_VAR byref V78 tmp48 u:2 Zero Fseq[Mantissa] $409 N011 ( 1, 1) [000612] -------N---- | | \--* LCL_VAR ref V52 tmp22 u:2 (last use) N019 ( 6, 6) [000620] -A---------- | \--* ASG int $VN.Void N017 ( 4, 4) [000618] *------N---- | +--* IND int N016 ( 2, 2) [000617] -------N---- | | \--* ADD byref $209 N014 ( 1, 1) [000615] ------------ | | +--* LCL_VAR byref V78 tmp48 u:2 (last use) $409 N015 ( 1, 1) [000616] ------------ | | \--* CNS_INT long 8 Fseq[Exponent] $101 N018 ( 1, 1) [000619] -------N---- | \--* LCL_VAR int V53 tmp23 u:2 (last use) N023 ( 3, 2) [000624] ------------ arg0 in rcx +--* LCL_VAR long V79 tmp49 u:2 (last use) $408 N025 ( 3, 3) [000626] ------------ arg1 in rdx +--* ADDR byref $40b N024 ( 3, 2) [000625] -------N---- | \--* LCL_VAR struct(AX) V73 tmp43 $3c8 N026 ( 3, 2) [000118] ------------ arg2 in r8 +--* LCL_VAR int V08 loc5 u:2 (last use) $242 N027 ( 3, 2) [000119] ------------ arg3 in r9 \--* LCL_VAR int V09 loc6 u:2 (last use) ***** BB23 STMT00029 (IL 0x0EF...0x0F4) N005 ( 17, 21) [000133] H-CXG------- * CALL help long HELPER.CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE $48d N003 ( 2, 10) [000131] ------------ arg0 in rcx +--* CNS_INT long 0x7ff815262aa0 $102 N004 ( 1, 4) [000132] ------------ arg1 in rdx \--* CNS_INT int 173 $58 ***** BB23 STMT00030 (IL ???... ???) N018 ( 21, 26) [000649] -A-XG------- * COMMA void N011 ( 13, 19) [000642] -A-XG------- +--* COMMA void N006 ( 6, 14) [000637] -A--G---R--- | +--* ASG byref N005 ( 1, 1) [000636] D------N---- | | +--* LCL_VAR byref V80 tmp50 d:2 N004 ( 6, 14) [000632] ----G------- | | \--* ADD byref N002 ( 4, 12) [000633] n---G------- | | +--* IND ref N001 ( 2, 10) [000634] I----------- | | | \--* CNS_INT(h) long 0xd1ffab1e static Fseq[BigOne] $4c2 N003 ( 1, 1) [000635] ------------ | | \--* CNS_INT long 8 Fseq[#FirstElem] $101 N010 ( 7, 5) [000641] -A-XG---R--- | \--* ASG ref N009 ( 3, 2) [000638] D---G--N---- | +--* LCL_VAR ref (AX) V58 tmp28 N008 ( 3, 2) [000640] ---X-------- | \--* IND ref N007 ( 1, 1) [000639] ------------ | \--* LCL_VAR byref V80 tmp50 u:2 Zero Fseq[_bits] N017 ( 8, 7) [000648] -A-XG---R--- \--* ASG int N016 ( 3, 2) [000643] D---G--N---- +--* LCL_VAR int (AX) V59 tmp29 N015 ( 4, 4) [000647] ---X-------- \--* IND int N014 ( 2, 2) [000646] -------N---- \--* ADD byref N012 ( 1, 1) [000644] ------------ +--* LCL_VAR byref V80 tmp50 u:2 (last use) N013 ( 1, 1) [000645] ------------ \--* CNS_INT long 8 Fseq[_sign] $101 ***** BB23 STMT00031 (IL 0x0F6...0x106) N006 ( 20, 12) [000141] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen $VN.Void N004 ( 3, 3) [000139] ------------ arg0 in rcx +--* ADDR long $40d N003 ( 3, 2) [000138] ----G--N---- | \--* LCL_VAR struct(AX)(P) V16 loc13 | \--* ref V16._bits (offs=0x00) -> V58 tmp28 | \--* int V16._sign (offs=0x08) -> V59 tmp29 $3c9 N005 ( 3, 2) [000140] ------------ arg1 in rdx \--* LCL_VAR int V14 loc11 u:2 (last use) $244 ***** BB23 STMT00099 (IL 0x0FF... ???) N007 ( 14, 10) [000658] -A--G------- * COMMA void $246 N003 ( 7, 5) [000654] -A--G---R--- +--* ASG ref $184 N002 ( 3, 2) [000652] D------N---- | +--* LCL_VAR ref V64 tmp34 d:2 $184 N001 ( 3, 2) [000653] ----G--N---- | \--* LCL_VAR ref (AX) V56 tmp26 $184 N006 ( 7, 5) [000657] -A--G---R--- \--* ASG int $246 N005 ( 3, 2) [000655] D------N---- +--* LCL_VAR int V65 tmp35 d:2 $246 N004 ( 3, 2) [000656] ----G--N---- \--* LCL_VAR int (AX) V57 tmp27 $246 ***** BB23 STMT00098 (IL 0x0FF... ???) N023 ( 45, 31) [000468] -ACXG---R--- * ASG int $29f N022 ( 3, 2) [000467] D------N---- +--* LCL_VAR int V43 tmp13 d:2 $29f N021 ( 41, 28) [000463] -ACXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $29f N016 ( 18, 15) [000677] -A--------L- arg0 SETUP +--* COMMA void $VN.Void N009 ( 10, 8) [000670] -A---------- | +--* COMMA void $VN.Void N004 ( 3, 3) [000665] -A------R--- | | +--* ASG byref $40e N003 ( 1, 1) [000664] D------N---- | | | +--* LCL_VAR byref V81 tmp51 d:2 $40e N002 ( 3, 3) [000662] ------------ | | | \--* ADDR byref $40e N001 ( 3, 2) [000663] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 $3ca N008 ( 7, 5) [000669] -A---------- | | \--* ASG ref $VN.Void N006 ( 3, 2) [000667] *------N---- | | +--* IND ref $184 N005 ( 1, 1) [000666] ------------ | | | \--* LCL_VAR byref V81 tmp51 u:2 Zero Fseq[_bits] $40e N007 ( 3, 2) [000668] -------N---- | | \--* LCL_VAR ref V64 tmp34 u:2 (last use) $184 N015 ( 8, 7) [000676] -A---------- | \--* ASG int $VN.Void N013 ( 4, 4) [000674] *------N---- | +--* IND int $246 N012 ( 2, 2) [000673] -------N---- | | \--* ADD byref $211 N010 ( 1, 1) [000671] ------------ | | +--* LCL_VAR byref V81 tmp51 u:2 (last use) $40e N011 ( 1, 1) [000672] ------------ | | \--* CNS_INT long 8 Fseq[_sign] $101 N014 ( 3, 2) [000675] -------N---- | \--* LCL_VAR int V65 tmp35 u:2 (last use) $246 N019 ( 3, 3) [000679] ------------ arg0 in rcx +--* ADDR byref $410 N018 ( 3, 2) [000678] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 $3cb N020 ( 3, 3) [000462] ------------ arg1 in rdx \--* LCL_VAR_ADDR long V45 tmp15 $449 ***** BB23 STMT00100 (IL 0x0FF... ???) N003 ( 5, 4) [000475] -A--G---R--- * ASG ref $VN.Null N002 ( 3, 2) [000474] D---G--N---- +--* LCL_VAR ref (AX) V45 tmp15 N001 ( 1, 1) [000473] ------------ \--* CNS_INT ref null $VN.Null ***** BB23 STMT00033 (IL ???... ???) N003 ( 7, 5) [000148] -A------R--- * ASG int $29f N002 ( 3, 2) [000147] D------N---- +--* LCL_VAR int V17 loc14 d:2 $29f N001 ( 3, 2) [000469] ------------ \--* LCL_VAR int V43 tmp13 u:2 $29f ***** BB23 STMT00103 (IL 0x108... ???) N007 ( 14, 10) [000687] -A--G------- * COMMA void $247 N003 ( 7, 5) [000683] -A--G---R--- +--* ASG ref $185 N002 ( 3, 2) [000681] D------N---- | +--* LCL_VAR ref V66 tmp36 d:2 $185 N001 ( 3, 2) [000682] ----G--N---- | \--* LCL_VAR ref (AX) V58 tmp28 $185 N006 ( 7, 5) [000686] -A--G---R--- \--* ASG int $247 N005 ( 3, 2) [000684] D------N---- +--* LCL_VAR int V67 tmp37 d:2 $247 N004 ( 3, 2) [000685] ----G--N---- \--* LCL_VAR int (AX) V59 tmp29 $247 ***** BB23 STMT00102 (IL 0x108... ???) N023 ( 45, 31) [000486] -ACXG---R--- * ASG int $2a3 N022 ( 3, 2) [000485] D------N---- +--* LCL_VAR int V46 tmp16 d:2 $2a3 N021 ( 41, 28) [000481] -ACXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $2a3 N016 ( 18, 15) [000706] -A--------L- arg0 SETUP +--* COMMA void $VN.Void N009 ( 10, 8) [000699] -A---------- | +--* COMMA void $VN.Void N004 ( 3, 3) [000694] -A------R--- | | +--* ASG byref $411 N003 ( 1, 1) [000693] D------N---- | | | +--* LCL_VAR byref V82 tmp52 d:2 $411 N002 ( 3, 3) [000691] ------------ | | | \--* ADDR byref $411 N001 ( 3, 2) [000692] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 $3cc N008 ( 7, 5) [000698] -A---------- | | \--* ASG ref $VN.Void N006 ( 3, 2) [000696] *------N---- | | +--* IND ref $185 N005 ( 1, 1) [000695] ------------ | | | \--* LCL_VAR byref V82 tmp52 u:2 Zero Fseq[_bits] $411 N007 ( 3, 2) [000697] -------N---- | | \--* LCL_VAR ref V66 tmp36 u:2 (last use) $185 N015 ( 8, 7) [000705] -A---------- | \--* ASG int $VN.Void N013 ( 4, 4) [000703] *------N---- | +--* IND int $247 N012 ( 2, 2) [000702] -------N---- | | \--* ADD byref $214 N010 ( 1, 1) [000700] ------------ | | +--* LCL_VAR byref V82 tmp52 u:2 (last use) $411 N011 ( 1, 1) [000701] ------------ | | \--* CNS_INT long 8 Fseq[_sign] $101 N014 ( 3, 2) [000704] -------N---- | \--* LCL_VAR int V67 tmp37 u:2 (last use) $247 N019 ( 3, 3) [000708] ------------ arg0 in rcx +--* ADDR byref $413 N018 ( 3, 2) [000707] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 $3cd N020 ( 3, 3) [000480] ------------ arg1 in rdx \--* LCL_VAR_ADDR long V48 tmp18 $44b ***** BB23 STMT00104 (IL 0x108... ???) N003 ( 5, 4) [000493] -A--G---R--- * ASG ref $VN.Null N002 ( 3, 2) [000492] D---G--N---- +--* LCL_VAR ref (AX) V48 tmp18 N001 ( 1, 1) [000491] ------------ \--* CNS_INT ref null $VN.Null ***** BB23 STMT00035 (IL ???... ???) N003 ( 7, 5) [000155] -A------R--- * ASG int $2a3 N002 ( 3, 2) [000154] D------N---- +--* LCL_VAR int V18 loc15 d:2 $2a3 N001 ( 3, 2) [000487] ------------ \--* LCL_VAR int V46 tmp16 u:2 $2a3 ***** BB23 STMT00036 (IL 0x111...0x115) N004 ( 9, 7) [000159] ------------ * JTRUE void N003 ( 7, 5) [000158] N------N-U-- \--* GT int $35f N001 ( 3, 2) [000156] ------------ +--* LCL_VAR int V18 loc15 u:2 (last use) $2a3 N002 ( 3, 2) [000157] ------------ \--* LCL_VAR int V17 loc14 u:2 (last use) $29f ------------ BB24 [117..11A) -> BB26 (always), preds={BB23} succs={BB26} ***** BB24 STMT00074 (IL 0x117...0x118) N003 ( 5, 4) [000350] -A------R--- * ASG int $40 N002 ( 3, 2) [000349] D------N---- +--* LCL_VAR int V33 tmp3 d:4 $40 N001 ( 1, 1) [000348] ------------ \--* CNS_INT int 0 $40 ------------ BB25 [11A..11F), preds={BB23} succs={BB26} ***** BB25 STMT00037 (IL 0x11A...0x11E) N005 ( 11, 8) [000164] -A------R--- * ASG int $360 N004 ( 3, 2) [000163] D------N---- +--* LCL_VAR int V33 tmp3 d:3 $360 N003 ( 7, 5) [000162] ------------ \--* SUB int $360 N001 ( 3, 2) [000160] ------------ +--* LCL_VAR int V18 loc15 u:2 (last use) $2a3 N002 ( 3, 2) [000161] ------------ \--* LCL_VAR int V17 loc14 u:2 (last use) $29f ------------ BB26 [11F..126) -> BB28 (cond), preds={BB24,BB25} succs={BB27,BB28} ***** BB26 STMT00119 (IL ???... ???) N005 ( 0, 0) [000877] -A------R--- * ASG int N004 ( 0, 0) [000875] D------N---- +--* LCL_VAR int V33 tmp3 d:2 N003 ( 0, 0) [000876] ------------ \--* PHI int N001 ( 0, 0) [000903] ------------ pred BB24 +--* PHI_ARG int V33 tmp3 u:4 $40 N002 ( 0, 0) [000902] ------------ pred BB25 \--* PHI_ARG int V33 tmp3 u:3 $360 ***** BB26 STMT00038 (IL ???...0x11F) N003 ( 3, 3) [000168] -A------R--- * ASG int $248 N002 ( 1, 1) [000167] D------N---- +--* LCL_VAR int V19 loc16 d:2 $248 N001 ( 3, 2) [000166] ------------ \--* LCL_VAR int V33 tmp3 u:2 $248 ***** BB26 STMT00039 (IL 0x121...0x124) N004 ( 7, 6) [000172] ------------ * JTRUE void N003 ( 5, 4) [000171] N------N---- \--* EQ int $361 N001 ( 3, 2) [000169] ------------ +--* LCL_VAR int V19 loc16 u:2 (last use) $248 N002 ( 1, 1) [000170] ------------ \--* CNS_INT int 0 $40 ------------ BB27 [126..12F), preds={BB26} succs={BB28} ***** BB27 STMT00073 (IL 0x126...0x12A) N006 ( 18, 11) [000347] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft $VN.Void N004 ( 3, 3) [000345] ------------ arg0 in rcx +--* ADDR long $414 N003 ( 3, 2) [000344] ----G--N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 $3ce N005 ( 1, 1) [000346] ------------ arg1 in rdx \--* LCL_VAR int V19 loc16 u:2 $248 ------------ BB28 [12F..13E) -> BB32 (cond), preds={BB26,BB27} succs={BB29,BB32} ***** BB28 STMT00040 (IL 0x12F...0x133) N005 ( 9, 7) [000177] -A------R--- * ASG int $362 N004 ( 3, 2) [000176] D------N---- +--* LCL_VAR int V20 loc17 d:2 $362 N003 ( 5, 4) [000175] ------------ \--* SUB int $362 N001 ( 3, 2) [000173] ------------ +--* LCL_VAR int V03 loc0 u:2 (last use) $348 N002 ( 1, 1) [000174] ------------ \--* LCL_VAR int V13 loc10 u:2 $293 ***** BB28 STMT00041 (IL 0x135...0x137) N003 ( 7, 5) [000180] -A------R--- * ASG int $362 N002 ( 3, 2) [000179] D------N---- +--* LCL_VAR int V21 loc18 d:2 $362 N001 ( 3, 2) [000178] ------------ \--* LCL_VAR int V20 loc17 u:2 $362 ***** BB28 STMT00042 (IL 0x139...0x13C) N004 ( 5, 5) [000184] ------------ * JTRUE void N003 ( 3, 3) [000183] N------N---- \--* EQ int $363 N001 ( 1, 1) [000181] ------------ +--* LCL_VAR int V13 loc10 u:2 $293 N002 ( 1, 1) [000182] ------------ \--* CNS_INT int 0 $40 ------------ BB29 [13E..144) -> BB31 (cond), preds={BB28} succs={BB30,BB31} ***** BB29 STMT00070 (IL 0x13E...0x142) N004 ( 7, 6) [000329] ------------ * JTRUE void N003 ( 5, 4) [000328] N------N-U-- \--* LE int $364 N001 ( 1, 1) [000326] ------------ +--* LCL_VAR int V19 loc16 u:2 $248 N002 ( 3, 2) [000327] ------------ \--* LCL_VAR int V20 loc17 u:2 $362 ------------ BB30 [144..155) -> BB44 (always), preds={BB29} succs={BB44} ***** BB30 STMT00072 (IL 0x144...0x154) N014 ( 29, 17) [000717] -ACXG---R--- * ASG int $5c2 N013 ( 1, 1) [000716] D------N---- +--* LCL_VAR int V51 tmp21 d:5 $5c2 N012 ( 29, 17) [000342] --CXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits $5c2 N005 ( 1, 1) [000341] ------------ arg4 out+20 +--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N008 ( 6, 3) CSE #02 (def)[000339] N----------- arg2 in r8 +--* NE int N006 ( 1, 1) [000337] ------------ | +--* LCL_VAR int V10 loc7 u:2 (last use) N007 ( 1, 1) [000338] ------------ | \--* CNS_INT int 0 $40 N009 ( 3, 2) [000335] ----G------- arg0 in rcx +--* LCL_VAR ref (AX) V12 loc9 $18c N010 ( 1, 1) [000336] ------------ arg1 in rdx +--* LCL_VAR int V13 loc10 u:2 (last use) $293 N011 ( 1, 1) [000340] ------------ arg3 in r9 \--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 ------------ BB31 [155..15C), preds={BB29} succs={BB32} ***** BB31 STMT00071 (IL 0x155...0x15A) N005 ( 9, 7) [000334] -A------R--- * ASG int $365 N004 ( 3, 2) [000333] D------N---- +--* LCL_VAR int V21 loc18 d:4 $365 N003 ( 5, 4) [000332] ------------ \--* SUB int $365 N001 ( 3, 2) [000330] ------------ +--* LCL_VAR int V20 loc17 u:2 (last use) $362 N002 ( 1, 1) [000331] ------------ \--* LCL_VAR int V19 loc16 u:2 $248 ------------ BB32 [15C..167) -> BB34 (cond), preds={BB28,BB31} succs={BB33,BB34} ***** BB32 STMT00118 (IL ???... ???) N005 ( 0, 0) [000874] -A------R--- * ASG int N004 ( 0, 0) [000872] D------N---- +--* LCL_VAR int V21 loc18 d:3 N003 ( 0, 0) [000873] ------------ \--* PHI int N001 ( 0, 0) [000900] ------------ pred BB31 +--* PHI_ARG int V21 loc18 u:4 $365 N002 ( 0, 0) [000888] ------------ pred BB28 \--* PHI_ARG int V21 loc18 u:2 $362 ***** BB32 STMT00105 (IL 0x15C... ???) N007 ( 14, 10) [000724] -A--G------- * COMMA void $24a N003 ( 7, 5) [000720] -A--G---R--- +--* ASG ref $186 N002 ( 3, 2) [000718] D---G--N---- | +--* LCL_VAR ref (AX) V68 tmp38 N001 ( 3, 2) [000719] ----G--N---- | \--* LCL_VAR ref (AX) V56 tmp26 $186 N006 ( 7, 5) [000723] -A--G---R--- \--* ASG int $24a N005 ( 3, 2) [000721] D---G--N---- +--* LCL_VAR int (AX) V69 tmp39 N004 ( 3, 2) [000722] ----G--N---- \--* LCL_VAR int (AX) V57 tmp27 $24a ***** BB32 STMT00106 (IL 0x15C... ???) N007 ( 14, 10) [000731] -A--G------- * COMMA void $24b N003 ( 7, 5) [000727] -A--G---R--- +--* ASG ref $187 N002 ( 3, 2) [000725] D------N---- | +--* LCL_VAR ref V70 tmp40 d:2 $187 N001 ( 3, 2) [000726] ----G--N---- | \--* LCL_VAR ref (AX) V58 tmp28 $187 N006 ( 7, 5) [000730] -A--G---R--- \--* ASG int $24b N005 ( 3, 2) [000728] D------N---- +--* LCL_VAR int V71 tmp41 d:2 $24b N004 ( 3, 2) [000729] ----G--N---- \--* LCL_VAR int (AX) V59 tmp29 $24b ***** BB32 STMT00044 (IL ???... ???) N027 ( 52, 38) [000195] -ACXG------- * JTRUE void N026 ( 50, 36) [000503] JACXG--N---- \--* LT int $367 N024 ( 48, 34) [000499] -ACXG------- +--* CALL int System.Numerics.BigInteger.CompareTo $2ae N004 ( 7, 6) [000752] -A------R-L- this SETUP | +--* ASG byref $415 N003 ( 3, 2) [000751] D------N---- | | +--* LCL_VAR byref V84 tmp54 d:2 $415 N002 ( 3, 3) [000497] ------------ | | \--* ADDR byref $415 N001 ( 3, 2) [000496] ----G--N---- | | \--* LCL_VAR struct(AX)(P) V49 tmp19 | | \--* ref V49._bits (offs=0x00) -> V68 tmp38 | | \--* int V49._sign (offs=0x08) -> V69 tmp39 $3cf N020 ( 18, 15) [000750] -A--------L- arg1 SETUP | +--* COMMA void $VN.Void N013 ( 10, 8) [000743] -A---------- | | +--* COMMA void $VN.Void N008 ( 3, 3) [000738] -A------R--- | | | +--* ASG byref $417 N007 ( 1, 1) [000737] D------N---- | | | | +--* LCL_VAR byref V83 tmp53 d:2 $417 N006 ( 3, 3) [000735] ------------ | | | | \--* ADDR byref $417 N005 ( 3, 2) [000736] ----G--N---- | | | | \--* LCL_VAR struct(AX) V76 tmp46 $3d0 N012 ( 7, 5) [000742] -A---------- | | | \--* ASG ref $VN.Void N010 ( 3, 2) [000740] *------N---- | | | +--* IND ref $187 N009 ( 1, 1) [000739] ------------ | | | | \--* LCL_VAR byref V83 tmp53 u:2 Zero Fseq[_bits] $417 N011 ( 3, 2) [000741] -------N---- | | | \--* LCL_VAR ref V70 tmp40 u:2 (last use) $187 N019 ( 8, 7) [000749] -A---------- | | \--* ASG int $VN.Void N017 ( 4, 4) [000747] *------N---- | | +--* IND int $24b N016 ( 2, 2) [000746] -------N---- | | | \--* ADD byref $216 N014 ( 1, 1) [000744] ------------ | | | +--* LCL_VAR byref V83 tmp53 u:2 (last use) $417 N015 ( 1, 1) [000745] ------------ | | | \--* CNS_INT long 8 Fseq[_sign] $101 N018 ( 3, 2) [000748] -------N---- | | \--* LCL_VAR int V71 tmp41 u:2 (last use) $24b N021 ( 3, 2) [000753] ------------ this in rcx | +--* LCL_VAR byref V84 tmp54 u:2 (last use) $415 N023 ( 3, 3) [000755] ------------ arg1 in rdx | \--* ADDR byref $419 N022 ( 3, 2) [000754] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 $3d1 N025 ( 1, 1) [000502] ------------ \--* CNS_INT int 0 $40 ------------ BB33 [167..16B) -> BB35 (always), preds={BB32} succs={BB35} ***** BB33 STMT00069 (IL 0x167...0x169) N003 ( 5, 4) [000324] -A------R--- * ASG int $248 N002 ( 3, 2) [000323] D------N---- +--* LCL_VAR int V34 tmp4 d:4 $248 N001 ( 1, 1) [000322] ------------ \--* LCL_VAR int V19 loc16 u:2 (last use) $248 ------------ BB34 [16B..16F), preds={BB32} succs={BB35} ***** BB34 STMT00045 (IL 0x16B...0x16E) N005 ( 7, 6) [000200] -A------R--- * ASG int $368 N004 ( 3, 2) [000199] D------N---- +--* LCL_VAR int V34 tmp4 d:3 $368 N003 ( 3, 3) [000198] ------------ \--* ADD int $368 N001 ( 1, 1) [000196] ------------ +--* LCL_VAR int V19 loc16 u:2 (last use) $248 N002 ( 1, 1) [000197] ------------ \--* CNS_INT int 1 $41 ------------ BB35 [16F..1A4) -> BB40 (cond), preds={BB33,BB34} succs={BB36,BB40} ***** BB35 STMT00117 (IL ???... ???) N005 ( 0, 0) [000871] -A------R--- * ASG int N004 ( 0, 0) [000869] D------N---- +--* LCL_VAR int V34 tmp4 d:2 N003 ( 0, 0) [000870] ------------ \--* PHI int N001 ( 0, 0) [000899] ------------ pred BB33 +--* PHI_ARG int V34 tmp4 u:4 $248 N002 ( 0, 0) [000898] ------------ pred BB34 \--* PHI_ARG int V34 tmp4 u:3 $368 ***** BB35 STMT00046 (IL ???...0x16F) N003 ( 7, 5) [000204] -A------R--- * ASG int $24c N002 ( 3, 2) [000203] D------N---- +--* LCL_VAR int V22 loc19 d:2 $24c N001 ( 3, 2) [000202] ------------ \--* LCL_VAR int V34 tmp4 u:2 (last use) $24c ***** BB35 STMT00047 (IL 0x171...0x18A) N006 ( 20, 12) [000208] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft $VN.Void N004 ( 3, 3) [000206] ------------ arg0 in rcx +--* ADDR long $41a N003 ( 3, 2) [000205] ----G--N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 $3d2 N005 ( 3, 2) [000207] ------------ arg1 in rdx \--* LCL_VAR int V21 loc18 u:3 (last use) $249 ***** BB35 STMT00048 (IL 0x17A... ???) N045 ( 78, 56) [000213] SACXG------- * CALL void System.Numerics.BigInteger.DivRem $VN.Void N004 ( 7, 6) [000797] -A------R-L- arg0 SETUP +--* ASG long $41b N003 ( 3, 2) [000796] D------N---- | +--* LCL_VAR long V88 tmp58 d:2 $41b N002 ( 3, 3) [000220] ------------ | \--* ADDR long $41b N001 ( 3, 2) [000219] ----G--N---- | \--* LCL_VAR struct(AX)(P) V35 tmp5 | \--* ref V35._bits (offs=0x00) -> V62 tmp32 | \--* int V35._sign (offs=0x08) -> V63 tmp33 $3d3 N020 ( 18, 15) [000776] -A--G-----L- arg1 SETUP +--* COMMA void $VN.Void N013 ( 10, 8) [000769] -A--G------- | +--* COMMA void $VN.Void N008 ( 3, 3) [000764] -A------R--- | | +--* ASG byref $41c N007 ( 1, 1) [000763] D------N---- | | | +--* LCL_VAR byref V85 tmp55 d:2 $41c N006 ( 3, 3) [000761] ------------ | | | \--* ADDR byref $41c N005 ( 3, 2) [000762] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 $3d4 N012 ( 7, 5) [000768] -A--G------- | | \--* ASG ref $VN.Void N010 ( 3, 2) [000766] *------N---- | | +--* IND ref $188 N009 ( 1, 1) [000765] ------------ | | | \--* LCL_VAR byref V85 tmp55 u:2 Zero Fseq[_bits] $41c N011 ( 3, 2) [000767] ----G--N---- | | \--* LCL_VAR ref (AX) V56 tmp26 $188 N019 ( 8, 7) [000775] -A--G------- | \--* ASG int $VN.Void N017 ( 4, 4) [000773] *------N---- | +--* IND int $24d N016 ( 2, 2) [000772] -------N---- | | \--* ADD byref $218 N014 ( 1, 1) [000770] ------------ | | +--* LCL_VAR byref V85 tmp55 u:2 (last use) $41c N015 ( 1, 1) [000771] ------------ | | \--* CNS_INT long 8 Fseq[_sign] $101 N018 ( 3, 2) [000774] ----G--N---- | \--* LCL_VAR int (AX) V57 tmp27 $24d N036 ( 18, 15) [000795] -A--G-----L- arg2 SETUP +--* COMMA void $VN.Void N029 ( 10, 8) [000788] -A--G------- | +--* COMMA void $VN.Void N024 ( 3, 3) [000783] -A------R--- | | +--* ASG byref $41e N023 ( 1, 1) [000782] D------N---- | | | +--* LCL_VAR byref V87 tmp57 d:2 $41e N022 ( 3, 3) [000780] ------------ | | | \--* ADDR byref $41e N021 ( 3, 2) [000781] -------N---- | | | \--* LCL_VAR struct(AX) V86 tmp56 $3d5 N028 ( 7, 5) [000787] -A--G------- | | \--* ASG ref $VN.Void N026 ( 3, 2) [000785] *------N---- | | +--* IND ref $189 N025 ( 1, 1) [000784] ------------ | | | \--* LCL_VAR byref V87 tmp57 u:2 Zero Fseq[_bits] $41e N027 ( 3, 2) [000786] ----G--N---- | | \--* LCL_VAR ref (AX) V58 tmp28 $189 N035 ( 8, 7) [000794] -A--G------- | \--* ASG int $VN.Void N033 ( 4, 4) [000792] *------N---- | +--* IND int $24e N032 ( 2, 2) [000791] -------N---- | | \--* ADD byref $21a N030 ( 1, 1) [000789] ------------ | | +--* LCL_VAR byref V87 tmp57 u:2 (last use) $41e N031 ( 1, 1) [000790] ------------ | | \--* CNS_INT long 8 Fseq[_sign] $101 N034 ( 3, 2) [000793] ----G--N---- | \--* LCL_VAR int (AX) V59 tmp29 $24e N038 ( 3, 2) [000798] ------------ arg0 in rcx +--* LCL_VAR long V88 tmp58 u:2 (last use) $41b N040 ( 3, 3) [000800] ------------ arg1 in rdx +--* ADDR byref $420 N039 ( 3, 2) [000799] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 $3d6 N042 ( 3, 3) [000802] ------------ arg2 in r8 +--* ADDR byref $421 N041 ( 3, 2) [000801] -------N---- | \--* LCL_VAR struct(AX) V86 tmp56 $3d7 N044 ( 3, 3) [000212] ------------ arg3 in r9 \--* ADDR long $422 N043 ( 3, 2) [000211] ----G--N---- \--* LCL_VAR struct(AX)(P) V23 loc20 \--* ref V23._bits (offs=0x00) -> V60 tmp30 \--* int V23._sign (offs=0x08) -> V61 tmp31 $3d8 ***** BB35 STMT00050 (IL ???... ???) N021 ( 38, 24) [000226] -ACXG---R--- * ASG long $450 N020 ( 1, 1) [000225] D------N---- +--* LCL_VAR long V24 loc21 d:2 $450 N019 ( 38, 24) [000218] -ACXG------- \--* CALL long System.Numerics.BigInteger.op_Explicit $450 N016 ( 18, 15) [000822] -A--G-----L- arg0 SETUP +--* COMMA void $VN.Void N009 ( 10, 8) [000815] -A--G------- | +--* COMMA void $VN.Void N004 ( 3, 3) [000810] -A------R--- | | +--* ASG byref $423 N003 ( 1, 1) [000809] D------N---- | | | +--* LCL_VAR byref V89 tmp59 d:2 $423 N002 ( 3, 3) [000807] ------------ | | | \--* ADDR byref $423 N001 ( 3, 2) [000808] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 $3d9 N008 ( 7, 5) [000814] -A--G------- | | \--* ASG ref $VN.Void N006 ( 3, 2) [000812] *------N---- | | +--* IND ref $18a N005 ( 1, 1) [000811] ------------ | | | \--* LCL_VAR byref V89 tmp59 u:2 Zero Fseq[_bits] $423 N007 ( 3, 2) [000813] ----G--N---- | | \--* LCL_VAR ref (AX) V62 tmp32 $18a N015 ( 8, 7) [000821] -A--G------- | \--* ASG int $VN.Void N013 ( 4, 4) [000819] *------N---- | +--* IND int $24f N012 ( 2, 2) [000818] -------N---- | | \--* ADD byref $21d N010 ( 1, 1) [000816] ------------ | | +--* LCL_VAR byref V89 tmp59 u:2 (last use) $423 N011 ( 1, 1) [000817] ------------ | | \--* CNS_INT long 8 Fseq[_sign] $101 N014 ( 3, 2) [000820] ----G--N---- | \--* LCL_VAR int (AX) V63 tmp33 $24f N018 ( 3, 3) [000824] ------------ arg0 in rcx \--* ADDR byref $425 N017 ( 3, 2) [000823] -------N---- \--* LCL_VAR struct(AX) V76 tmp46 $3da ***** BB35 STMT00052 (IL ???... ???) N005 ( 12, 7) [000232] -A--G---R--- * ASG int $369 N004 ( 3, 2) [000231] D------N---- +--* LCL_VAR int V25 loc22 d:2 $369 N003 ( 8, 4) [000516] ----G------- \--* EQ int $369 N001 ( 3, 2) [000514] ----G------- +--* LCL_VAR int (AX) V61 tmp31 $250 N002 ( 1, 1) [000515] ------------ \--* CNS_INT int 0 $40 ***** BB35 STMT00054 (IL ???... ???) N005 ( 19, 10) [000237] -ACXG---R--- * ASG int $2b4 N004 ( 3, 2) [000236] D------N---- +--* LCL_VAR int V26 loc23 d:2 $2b4 N003 ( 15, 7) [000234] --CXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $2b4 N002 ( 1, 1) [000233] ------------ arg0 in rcx \--* LCL_VAR long V24 loc21 u:2 $450 ***** BB35 STMT00055 (IL 0x19E...0x1A2) N004 ( 9, 7) [000241] ------------ * JTRUE void N003 ( 7, 5) [000240] N------N-U-- \--* LE int $36a N001 ( 3, 2) [000238] ------------ +--* LCL_VAR int V26 loc23 u:2 $2b4 N002 ( 3, 2) [000239] ------------ \--* LCL_VAR int V20 loc17 u:2 $362 ------------ BB36 [1A4..1AF) -> BB38 (cond), preds={BB35} succs={BB37,BB38} ***** BB36 STMT00063 (IL 0x1A4...0x1A9) N005 ( 11, 8) [000286] -A------R--- * ASG int $36b N004 ( 3, 2) [000285] D------N---- +--* LCL_VAR int V29 loc26 d:2 $36b N003 ( 7, 5) [000284] ------------ \--* SUB int $36b N001 ( 3, 2) [000282] ------------ +--* LCL_VAR int V26 loc23 u:2 (last use) $2b4 N002 ( 3, 2) [000283] ------------ \--* LCL_VAR int V20 loc17 u:2 $362 ***** BB36 STMT00064 (IL 0x1AB...0x1AD) N004 ( 7, 6) [000290] ------------ * JTRUE void N003 ( 5, 4) [000289] J------N---- \--* EQ int $36c N001 ( 3, 2) [000287] ------------ +--* LCL_VAR int V25 loc22 u:2 (last use) $369 N002 ( 1, 1) [000288] ------------ \--* CNS_INT int 0 $40 ------------ BB37 [1AF..1C3) -> BB39 (always), preds={BB36} succs={BB39} ***** BB37 STMT00068 (IL 0x1AF...0x1C1) N013 ( 23, 15) [000320] -A------R--- * ASG int $36e N012 ( 3, 2) [000319] D------N---- +--* LCL_VAR int V37 tmp7 d:4 $36e N011 ( 19, 12) [000318] ------------ \--* EQ int $36e N009 ( 14, 10) [000315] ------------ +--* AND long $490 N001 ( 1, 1) [000305] ------------ | +--* LCL_VAR long V24 loc21 u:2 $450 N008 ( 12, 8) [000314] ------------ | \--* ADD long $48f N006 ( 10, 6) [000311] --------R--- | +--* LSH long $48e N005 ( 1, 1) [000307] ------------ | | +--* CNS_INT long 1 $103 N004 ( 5, 4) CSE #03 (def)[000310] ------------ | | \--* AND int $36d N002 ( 3, 2) [000308] ------------ | | +--* LCL_VAR int V29 loc26 u:2 $36b N003 ( 1, 1) [000309] ------------ | | \--* CNS_INT int 63 $66 N007 ( 1, 1) [000313] ------------ | \--* CNS_INT long -1 $104 N010 ( 1, 1) [000317] ------------ \--* CNS_INT long 0 $100 ------------ BB38 [1C3..1C4), preds={BB36} succs={BB39} ***** BB38 STMT00065 (IL 0x1C3...0x1C3) N003 ( 5, 4) [000293] -A------R--- * ASG int $40 N002 ( 3, 2) [000292] D------N---- +--* LCL_VAR int V37 tmp7 d:3 $40 N001 ( 1, 1) [000291] ------------ \--* CNS_INT int 0 $40 ------------ BB39 [1C4..1D0), preds={BB37,BB38} succs={BB40} ***** BB39 STMT00116 (IL ???... ???) N005 ( 0, 0) [000868] -A------R--- * ASG int N004 ( 0, 0) [000866] D------N---- +--* LCL_VAR int V37 tmp7 d:2 N003 ( 0, 0) [000867] ------------ \--* PHI int N001 ( 0, 0) [000897] ------------ pred BB37 +--* PHI_ARG int V37 tmp7 u:4 $36e N002 ( 0, 0) [000896] ------------ pred BB38 \--* PHI_ARG int V37 tmp7 u:3 $40 ***** BB39 STMT00066 (IL ???...0x1C4) N004 ( 8, 7) [000297] -A------R--- * ASG int $36f N003 ( 3, 2) [000296] D------N---- +--* LCL_VAR int V25 loc22 d:4 $36f N002 ( 4, 4) [000826] ------------ \--* CAST int <- bool <- int $36f N001 ( 3, 2) [000295] ------------ \--* LCL_VAR int V37 tmp7 u:2 (last use) $251 ***** BB39 STMT00067 (IL 0x1C6...0x1CE) N007 ( 10, 6) [000304] -A------R--- * ASG long $491 N006 ( 1, 1) [000303] D------N---- +--* LCL_VAR long V24 loc21 d:4 $491 N005 ( 10, 6) [000302] ------------ \--* RSZ long $491 N001 ( 1, 1) [000298] ------------ +--* LCL_VAR long V24 loc21 u:2 (last use) $450 N004 ( 5, 4) CSE #03 (def)[000301] ------------ \--* AND int $36d N002 ( 3, 2) [000299] ------------ +--* LCL_VAR int V29 loc26 u:2 (last use) $36b N003 ( 1, 1) [000300] ------------ \--* CNS_INT int 63 $66 ------------ BB40 [1D0..1E7) -> BB42 (cond), preds={BB35,BB39} succs={BB41,BB42} ***** BB40 STMT00115 (IL ???... ???) N005 ( 0, 0) [000865] -A------R--- * ASG bool N004 ( 0, 0) [000863] D------N---- +--* LCL_VAR bool V25 loc22 d:3 N003 ( 0, 0) [000864] ------------ \--* PHI bool N001 ( 0, 0) [000894] ------------ pred BB39 +--* PHI_ARG bool V25 loc22 u:4 $36f N002 ( 0, 0) [000889] ------------ pred BB35 \--* PHI_ARG bool V25 loc22 u:2 $369 ***** BB40 STMT00114 (IL ???... ???) N005 ( 0, 0) [000862] -A------R--- * ASG long N004 ( 0, 0) [000860] D------N---- +--* LCL_VAR long V24 loc21 d:3 N003 ( 0, 0) [000861] ------------ \--* PHI long N001 ( 0, 0) [000895] ------------ pred BB39 +--* PHI_ARG long V24 loc21 u:4 $491 N002 ( 0, 0) [000890] ------------ pred BB35 \--* PHI_ARG long V24 loc21 u:2 $450 ***** BB40 STMT00057 (IL ???... ???) N027 ( 53, 34) [000254] -ACXG---R--- * ASG long $493 N026 ( 3, 2) [000253] D------N---- +--* LCL_VAR long V27 loc24 d:2 $493 N025 ( 49, 31) [000252] -ACXG------- \--* ADD long $493 N023 ( 47, 29) [000250] -ACXG------- +--* LSH long $492 N019 ( 38, 24) [000243] -ACXG------- | +--* CALL long System.Numerics.BigInteger.op_Explicit $454 N016 ( 18, 15) [000845] -A--G-----L- arg0 SETUP | | +--* COMMA void $VN.Void N009 ( 10, 8) [000838] -A--G------- | | | +--* COMMA void $VN.Void N004 ( 3, 3) [000833] -A------R--- | | | | +--* ASG byref $426 N003 ( 1, 1) [000832] D------N---- | | | | | +--* LCL_VAR byref V90 tmp60 d:2 $426 N002 ( 3, 3) [000830] ------------ | | | | | \--* ADDR byref $426 N001 ( 3, 2) [000831] ----G--N---- | | | | | \--* LCL_VAR struct(AX) V76 tmp46 $3db N008 ( 7, 5) [000837] -A--G------- | | | | \--* ASG ref $VN.Void N006 ( 3, 2) [000835] *------N---- | | | | +--* IND ref $18b N005 ( 1, 1) [000834] ------------ | | | | | \--* LCL_VAR byref V90 tmp60 u:2 Zero Fseq[_bits] $426 N007 ( 3, 2) [000836] ----G--N---- | | | | \--* LCL_VAR ref (AX) V54 tmp24 $18b N015 ( 8, 7) [000844] -A--G------- | | | \--* ASG int $VN.Void N013 ( 4, 4) [000842] *------N---- | | | +--* IND int $252 N012 ( 2, 2) [000841] -------N---- | | | | \--* ADD byref $220 N010 ( 1, 1) [000839] ------------ | | | | +--* LCL_VAR byref V90 tmp60 u:2 (last use) $426 N011 ( 1, 1) [000840] ------------ | | | | \--* CNS_INT long 8 Fseq[_sign] $101 N014 ( 3, 2) [000843] ----G--N---- | | | \--* LCL_VAR int (AX) V55 tmp25 $252 N018 ( 3, 3) [000847] ------------ arg0 in rcx | | \--* ADDR byref $428 N017 ( 3, 2) [000846] -------N---- | | \--* LCL_VAR struct(AX) V76 tmp46 $3dc N022 ( 5, 4) [000249] ------------ | \--* AND int $370 N020 ( 3, 2) [000247] ------------ | +--* LCL_VAR int V20 loc17 u:2 (last use) $362 N021 ( 1, 1) [000248] ------------ | \--* CNS_INT int 63 $66 N024 ( 1, 1) [000251] ------------ \--* LCL_VAR long V24 loc21 u:3 (last use) $580 ***** BB40 STMT00058 (IL 0x1E2...0x1E5) N004 ( 5, 5) [000258] ------------ * JTRUE void N003 ( 3, 3) [000257] N------N---- \--* NE int $35a N001 ( 1, 1) [000255] ------------ +--* LCL_VAR int V13 loc10 u:2 $293 N002 ( 1, 1) [000256] ------------ \--* CNS_INT int 0 $40 ------------ BB41 [1E7..1EE) -> BB43 (always), preds={BB40} succs={BB43} ***** BB41 STMT00062 (IL 0x1E7...0x1EC) N006 ( 10, 8) [000280] -A------R--- * ASG int $372 N005 ( 3, 2) [000279] D------N---- +--* LCL_VAR int V36 tmp6 d:4 $372 N004 ( 6, 5) [000278] ------------ \--* ADD int $372 N002 ( 4, 3) [000276] ------------ +--* NEG int $2c2 N001 ( 3, 2) [000275] ------------ | \--* LCL_VAR int V22 loc19 u:2 (last use) $24c N003 ( 1, 1) [000277] ------------ \--* CNS_INT int -1 $43 ------------ BB42 [1EE..1F2), preds={BB40} succs={BB43} ***** BB42 STMT00059 (IL 0x1EE...0x1F1) N005 ( 7, 6) [000263] -A------R--- * ASG int $371 N004 ( 3, 2) [000262] D------N---- +--* LCL_VAR int V36 tmp6 d:3 $371 N003 ( 3, 3) [000261] ------------ \--* ADD int $371 N001 ( 1, 1) [000259] ------------ +--* LCL_VAR int V13 loc10 u:2 (last use) $293 N002 ( 1, 1) [000260] ------------ \--* CNS_INT int -2 $68 ------------ BB43 [1F2..202), preds={BB41,BB42} succs={BB44} ***** BB43 STMT00113 (IL ???... ???) N005 ( 0, 0) [000859] -A------R--- * ASG int N004 ( 0, 0) [000857] D------N---- +--* LCL_VAR int V36 tmp6 d:2 N003 ( 0, 0) [000858] ------------ \--* PHI int N001 ( 0, 0) [000893] ------------ pred BB41 +--* PHI_ARG int V36 tmp6 u:4 $372 N002 ( 0, 0) [000892] ------------ pred BB42 \--* PHI_ARG int V36 tmp6 u:3 $371 ***** BB43 STMT00061 (IL 0x1F4...0x201) N012 ( 28, 18) [000853] -ACXG---R--- * ASG int $2be N011 ( 1, 1) [000852] D------N---- +--* LCL_VAR int V51 tmp21 d:4 $2be N010 ( 28, 18) [000273] --CXG------- \--* CALL nullcheck int FloatingPointType.AssembleFloatingPointValue $2be N005 ( 1, 1) [000272] ------------ arg4 out+20 +--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N006 ( 1, 1) [000268] ------------ this in rcx +--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 N007 ( 3, 2) [000269] ------------ arg1 in rdx +--* LCL_VAR long V27 loc24 u:2 (last use) $493 N008 ( 3, 2) [000270] ------------ arg2 in r8 +--* LCL_VAR int V36 tmp6 u:2 (last use) $253 N009 ( 3, 2) [000271] ------------ arg3 in r9 \--* LCL_VAR int V25 loc22 u:3 (last use) $540 ------------ BB44 [???..???) (return), preds={BB16,BB30,BB43} succs={} ***** BB44 STMT00112 (IL ???... ???) N006 ( 0, 0) [000856] -A------R--- * ASG int N005 ( 0, 0) [000854] D------N---- +--* LCL_VAR int V51 tmp21 d:2 N004 ( 0, 0) [000855] ------------ \--* PHI int N001 ( 0, 0) [000901] ------------ pred BB30 +--* PHI_ARG int V51 tmp21 u:5 $5c2 N002 ( 0, 0) [000891] ------------ pred BB43 +--* PHI_ARG int V51 tmp21 u:4 $2be N003 ( 0, 0) [000887] ------------ pred BB16 \--* PHI_ARG int V51 tmp21 u:3 $5c7 ***** BB44 STMT00109 (IL ???... ???) N002 ( 2, 2) [000523] ------------ * RETURN int $5c9 N001 ( 1, 1) [000522] -------N---- \--* LCL_VAR int V51 tmp21 u:2 (last use) $254 ------------------------------------------------------------------------------------------------------------------- Aggressive CSE Promotion cutoff is 400 Moderate CSE Promotion cutoff is 200 enregCount is 62 Framesize estimate is 0x0084 We have a large frame Sorted CSE candidates: CSE #02, {$355, $4 } useCnt=0: [def=100, use= 0, cost= 6 ] :: N008 ( 6, 3) CSE #02 (def)[000086] N----------- * NE int CSE #03, {$36d, $4 } useCnt=0: [def=100, use= 0, cost= 5 ] :: N004 ( 5, 4) CSE #03 (def)[000310] ------------ * AND int $36d CSE #01, {$2c1, $301} useCnt=3: [def=100, use=150, cost= 3, call] :: N002 ( 3, 3) CSE #01 (def)[000003] ---XG------- * ARR_LENGTH int Skipped CSE #02 because use count is 0 Skipped CSE #03 because use count is 0 Considering CSE #01 {$2c1, $301} [def=100, use=150, cost= 3, call] CSE Expression : N002 ( 3, 3) CSE #01 (def)[000003] ---XG------- * ARR_LENGTH int N001 ( 1, 1) [000002] ------------ \--* LCL_VAR ref V52 tmp22 u:2 Moderate CSE Promotion (CSE is live across a call) (350 >= 200) cseRefCnt=350, aggressiveRefCnt=400, moderateRefCnt=200 defCnt=100, useCnt=150, cost=3, size=3, LiveAcrossCall def_cost=2, use_cost=2, extra_no_cost=6, extra_yes_cost=0 CSE cost savings check (456 >= 500) fails Did Not promote this CSE *************** Finishing PHASE Optimize Valnum CSEs *************** Starting PHASE Assertion prop *************** In optAssertionPropMain() Blocks/Trees at start of phase ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0056] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..00D)-> BB04 ( cond ) i label target idxlen BB03 [0001] 1 BB02 0.50 [00D..017) (return) i hascall gcsafe BB04 [0002] 1 BB02 0.50 [017..065)-> BB06 ( cond ) i label target hascall gcsafe BB05 [0038] 1 BB04 0.50 [020..021)-> BB07 (always) i gcsafe BB06 [0039] 1 BB04 0.50 [020..021) i label target gcsafe BB07 [0040] 2 BB05,BB06 0.50 [000..000)-> BB09 ( cond ) i internal label target gcsafe idxlen BB08 [0043] 1 BB07 0.50 [000..000)-> BB10 (always) i internal gcsafe BB09 [0044] 1 BB07 0.50 [000..000) i internal label target gcsafe BB10 [0045] 2 BB08,BB09 0.50 [???..???)-> BB14 ( cond ) i internal label target hascall gcsafe idxlen BB11 [0003] 1 BB10 0.50 [065..070)-> BB13 ( cond ) i hascall gcsafe BB12 [0004] 1 BB11 0.50 [070..07A) (return) i hascall gcsafe BB13 [0005] 1 BB11 0.50 [07A..082) i label target hascall gcsafe BB14 [0006] 2 BB10,BB13 0.50 [082..092)-> BB16 ( cond ) i label target hascall gcsafe BB15 [0007] 1 BB14 0.50 [092..096)-> BB17 ( cond ) i gcsafe BB16 [0008] 2 BB14,BB15 0.50 [096..0A7)-> BB44 (always) i label target hascall gcsafe BB17 [0009] 1 BB15 0.50 [0A7..0B0)-> BB19 ( cond ) i label target gcsafe BB18 [0010] 1 BB17 0.50 [0B0..0B4)-> BB20 (always) i gcsafe BB19 [0011] 1 BB17 0.50 [0B4..0BE) i label target gcsafe BB20 [0012] 2 BB18,BB19 0.50 [0BE..0C4)-> BB23 ( cond ) i label target gcsafe BB21 [0013] 1 BB20 0.50 [0C4..0D9)-> BB23 ( cond ) i hascall gcsafe idxlen BB22 [0014] 1 BB21 0.50 [0D9..0E3) (return) i hascall gcsafe BB23 [0015] 2 BB20,BB21 0.50 [0E3..117)-> BB25 ( cond ) i label target hascall gcsafe BB24 [0016] 1 BB23 0.50 [117..11A)-> BB26 (always) i gcsafe BB25 [0017] 1 BB23 0.50 [11A..11F) i label target gcsafe BB26 [0018] 2 BB24,BB25 0.50 [11F..126)-> BB28 ( cond ) i label target gcsafe BB27 [0019] 1 BB26 0.50 [126..12F) i hascall gcsafe BB28 [0020] 2 BB26,BB27 0.50 [12F..13E)-> BB32 ( cond ) i label target gcsafe BB29 [0021] 1 BB28 0.50 [13E..144)-> BB31 ( cond ) i gcsafe BB30 [0022] 1 BB29 0.50 [144..155)-> BB44 (always) i hascall gcsafe BB31 [0023] 1 BB29 0.50 [155..15C) i label target gcsafe BB32 [0024] 2 BB28,BB31 0.50 [15C..167)-> BB34 ( cond ) i label target hascall gcsafe BB33 [0025] 1 BB32 0.50 [167..16B)-> BB35 (always) i gcsafe BB34 [0026] 1 BB32 0.50 [16B..16F) i label target gcsafe BB35 [0027] 2 BB33,BB34 0.50 [16F..1A4)-> BB40 ( cond ) i label target hascall gcsafe BB36 [0028] 1 BB35 0.50 [1A4..1AF)-> BB38 ( cond ) i gcsafe BB37 [0029] 1 BB36 0.50 [1AF..1C3)-> BB39 (always) i gcsafe BB38 [0030] 1 BB36 0.50 [1C3..1C4) i label target gcsafe BB39 [0031] 2 BB37,BB38 0.50 [1C4..1D0) i label target gcsafe BB40 [0032] 2 BB35,BB39 0.50 [1D0..1E7)-> BB42 ( cond ) i label target hascall gcsafe BB41 [0033] 1 BB40 0.50 [1E7..1EE)-> BB43 (always) i gcsafe BB42 [0034] 1 BB40 0.50 [1EE..1F2) i label target gcsafe BB43 [0035] 2 BB41,BB42 0.50 [1F2..202) i label target hascall gcsafe BB44 [0054] 3 BB16,BB30,BB43 0.50 [???..???) (return) keep internal target gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} ***** BB01 STMT00111 (IL ???... ???) N011 ( 7, 7) [000540] -A---------- * COMMA void N004 ( 3, 3) [000533] -A------R--- +--* ASG ref N003 ( 1, 1) [000530] D------N---- | +--* LCL_VAR ref V52 tmp22 d:2 N002 ( 3, 2) [000532] n----------- | \--* IND ref N001 ( 1, 1) [000531] ------------ | \--* LCL_VAR byref V00 arg0 u:1 Zero Fseq[Mantissa] $80 N010 ( 4, 4) [000539] -A------R--- \--* ASG int N009 ( 1, 1) [000534] D------N---- +--* LCL_VAR int V53 tmp23 d:2 N008 ( 4, 4) [000538] n----------- \--* IND int N007 ( 2, 2) [000537] -------N---- \--* ADD byref $200 N005 ( 1, 1) [000535] ------------ +--* LCL_VAR byref V00 arg0 u:1 (last use) $80 N006 ( 1, 1) [000536] ------------ \--* CNS_INT long 8 Fseq[Exponent] $101 ------------ BB02 [000..00D) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00000 (IL 0x000...0x00B) N005 ( 7, 7) [000006] ---XG------- * JTRUE void N004 ( 5, 5) [000005] J--XG--N---- \--* NE int N002 ( 3, 3) [000003] ---XG------- +--* ARR_LENGTH int N001 ( 1, 1) [000002] ------------ | \--* LCL_VAR ref V52 tmp22 u:2 N003 ( 1, 1) [000004] ------------ \--* CNS_INT int 0 $40 ------------ BB03 [00D..017) (return), preds={BB02} succs={} ***** BB03 STMT00087 (IL 0x00D...0x014) N006 ( 25, 13) [000403] -ACXG---R--- * ASG long $VN.Void N005 ( 3, 2) [000402] *--X---N---- +--* IND long $459 N004 ( 1, 1) [000399] ------------ | \--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N003 ( 21, 10) [000401] --CXG------- \--* CALLV ind long FloatingPointType.get_Zero $459 N002 ( 1, 1) [000400] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 ***** BB03 STMT00107 (IL ???... ???) N002 ( 2, 2) [000520] ------------ * RETURN int $5cb N001 ( 1, 1) [000404] ------------ \--* CNS_INT int 1 $41 ------------ BB04 [017..065) -> BB06 (cond), preds={BB02} succs={BB05,BB06} ***** BB04 STMT00002 (IL ???... ???) N010 ( 30, 19) [000013] -ACXG---R--- * ASG int $348 N009 ( 3, 2) [000012] D------N---- +--* LCL_VAR int V03 loc0 d:2 $348 N008 ( 26, 16) [000011] --CXG------- \--* ADD int $348 N006 ( 24, 14) [000409] --CXG------- +--* CAST int <- ushort <- int $347 N005 ( 23, 12) [000408] --CXG------- | \--* ADD int $346 N003 ( 21, 10) [000406] --CXG------- | +--* CALLV ind int FloatingPointType.get_DenormalMantissaBits $282 N002 ( 1, 1) [000007] ------------ this in rcx | | \--* LCL_VAR ref V01 arg1 u:1 $c0 N004 ( 1, 1) [000407] ------------ | \--* CNS_INT int 1 $41 N007 ( 1, 1) [000010] ------------ \--* CNS_INT int 1 $41 ***** BB04 STMT00092 (IL 0x020... ???) N003 ( 5, 4) [000424] -A--G---R--- * ASG int N002 ( 3, 2) [000423] D------N---- +--* LCL_VAR int V40 tmp10 d:2 N001 ( 1, 1) [000017] ------------ \--* LCL_VAR int V53 tmp23 u:2 ***** BB04 STMT00089 (IL 0x020... ???) N004 ( 5, 5) [000414] ------------ * JTRUE void N003 ( 3, 3) [000413] J------N---- \--* LE int N001 ( 1, 1) [000412] ------------ +--* LCL_VAR int V40 tmp10 u:2 N002 ( 1, 1) [000411] ------------ \--* CNS_INT int 0 $40 ------------ BB05 [020..021) -> BB07 (always), preds={BB04} succs={BB07} ***** BB05 STMT00091 (IL 0x020... ???) N003 ( 7, 5) [000421] -A------R--- * ASG int N002 ( 3, 2) [000420] D------N---- +--* LCL_VAR int V39 tmp9 d:4 N001 ( 3, 2) [000419] ------------ \--* LCL_VAR int V53 tmp23 u:2 (last use) ------------ BB06 [020..021), preds={BB04} succs={BB07} ***** BB06 STMT00090 (IL 0x020... ???) N003 ( 5, 4) [000417] -A------R--- * ASG int $40 N002 ( 3, 2) [000416] D------N---- +--* LCL_VAR int V39 tmp9 d:3 $40 N001 ( 1, 1) [000415] ------------ \--* CNS_INT int 0 $40 ------------ BB07 [000..000) -> BB09 (cond), preds={BB05,BB06} succs={BB08,BB09} ***** BB07 STMT00122 (IL ???... ???) N005 ( 0, 0) [000886] -A------R--- * ASG int N004 ( 0, 0) [000884] D------N---- +--* LCL_VAR int V39 tmp9 d:2 N003 ( 0, 0) [000885] ------------ \--* PHI int N001 ( 0, 0) [000909] ------------ pred BB05 +--* PHI_ARG int V39 tmp9 u:4 N002 ( 0, 0) [000908] ------------ pred BB06 \--* PHI_ARG int V39 tmp9 u:3 $40 ***** BB07 STMT00004 (IL ???... ???) N003 ( 3, 3) [000021] -A------R--- * ASG int $241 N002 ( 1, 1) [000020] D------N---- +--* LCL_VAR int V31 tmp1 d:2 $241 N001 ( 3, 2) [000422] ------------ \--* LCL_VAR int V39 tmp9 u:2 $241 ***** BB07 STMT00096 (IL ???... ???) N004 ( 3, 3) [000443] -A-XG---R--- * ASG int N003 ( 1, 1) [000442] D------N---- +--* LCL_VAR int V42 tmp12 d:2 N002 ( 3, 3) [000429] ---XG------- \--* ARR_LENGTH int N001 ( 1, 1) [000428] ------------ \--* LCL_VAR ref V52 tmp22 u:2 ***** BB07 STMT00093 (IL ???... ???) N004 ( 7, 6) [000433] ------------ * JTRUE void N003 ( 5, 4) [000432] N------N-U-- \--* LE int N001 ( 3, 2) [000023] ------------ +--* LCL_VAR int V31 tmp1 u:2 (last use) $241 N002 ( 1, 1) [000431] ------------ \--* LCL_VAR int V42 tmp12 u:2 ------------ BB08 [000..000) -> BB10 (always), preds={BB07} succs={BB10} ***** BB08 STMT00095 (IL ???... ???) N003 ( 1, 3) [000440] -A------R--- * ASG int N002 ( 1, 1) [000439] D------N---- +--* LCL_VAR int V41 tmp11 d:4 N001 ( 1, 1) [000438] ------------ \--* LCL_VAR int V42 tmp12 u:2 (last use) ------------ BB09 [000..000), preds={BB07} succs={BB10} ***** BB09 STMT00094 (IL ???... ???) N003 ( 1, 3) [000436] -A------R--- * ASG int $241 N002 ( 1, 1) [000435] D------N---- +--* LCL_VAR int V41 tmp11 d:3 $241 N001 ( 1, 1) [000434] ------------ \--* LCL_VAR int V31 tmp1 u:2 $241 ------------ BB10 [???..???) -> BB14 (cond), preds={BB08,BB09} succs={BB11,BB14} ***** BB10 STMT00121 (IL ???... ???) N005 ( 0, 0) [000883] -A------R--- * ASG int N004 ( 0, 0) [000881] D------N---- +--* LCL_VAR int V41 tmp11 d:2 N003 ( 0, 0) [000882] ------------ \--* PHI int N001 ( 0, 0) [000907] ------------ pred BB08 +--* PHI_ARG int V41 tmp11 u:4 N002 ( 0, 0) [000906] ------------ pred BB09 \--* PHI_ARG int V41 tmp11 u:3 $241 ***** BB10 STMT00008 (IL ???...0x03C) N005 ( 7, 6) [000035] -A------R--- * ASG int $34e N004 ( 3, 2) [000034] D------N---- +--* LCL_VAR int V05 loc2 d:2 $34e N003 ( 3, 3) [000033] ------------ \--* SUB int $34e N001 ( 1, 1) [000022] ------------ +--* LCL_VAR int V31 tmp1 u:2 (last use) $241 N002 ( 1, 1) [000032] ------------ \--* LCL_VAR int V41 tmp11 u:2 $242 ***** BB10 STMT00011 (IL 0x042...0x044) N003 ( 5, 4) [000044] -A------R--- * ASG int $242 N002 ( 3, 2) [000043] D------N---- +--* LCL_VAR int V08 loc5 d:2 $242 N001 ( 1, 1) [000042] ------------ \--* LCL_VAR int V41 tmp11 u:2 $242 ***** BB10 STMT00013 (IL ???... ???) N004 ( 7, 6) [000050] -A-XG---R--- * ASG int N003 ( 3, 2) [000049] D------N---- +--* LCL_VAR int V09 loc6 d:2 N002 ( 3, 3) [000448] ---XG------- \--* ARR_LENGTH int N001 ( 1, 1) [000447] ------------ \--* LCL_VAR ref V52 tmp22 u:2 ***** BB10 STMT00014 (IL 0x04F...0x054) N005 ( 5, 4) [000055] -A------R--- * ASG int N004 ( 1, 1) [000054] D------N---- +--* LCL_VAR int V10 loc7 d:2 N003 ( 5, 4) [000053] ------------ \--* SUB int N001 ( 3, 2) [000051] ------------ +--* LCL_VAR int V09 loc6 u:2 N002 ( 1, 1) [000052] ------------ \--* LCL_VAR int V08 loc5 u:2 $242 ***** BB10 STMT00016 (IL ???... ???) N028 ( 49, 35) [000059] SACXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger $VN.Void N004 ( 7, 6) [000563] -A------R-L- arg0 SETUP +--* ASG long $400 N003 ( 3, 2) [000562] D------N---- | +--* LCL_VAR long V75 tmp45 d:2 $400 N002 ( 3, 3) [000064] ------------ | \--* ADDR long $400 N001 ( 3, 2) [000063] ----G--N---- | \--* LCL_VAR struct(AX)(P) V11 loc8 | \--* ref V11._bits (offs=0x00) -> V54 tmp24 | \--* int V11._sign (offs=0x08) -> V55 tmp25 $3c0 N020 ( 14, 13) [000561] -A--------L- arg1 SETUP +--* COMMA void $VN.Void N013 ( 8, 7) [000554] -A---------- | +--* COMMA void $VN.Void N008 ( 3, 3) [000549] -A------R--- | | +--* ASG byref $401 N007 ( 1, 1) [000548] D------N---- | | | +--* LCL_VAR byref V74 tmp44 d:2 $401 N006 ( 3, 3) [000546] ------------ | | | \--* ADDR byref $401 N005 ( 3, 2) [000547] -------N---- | | | \--* LCL_VAR struct(AX) V73 tmp43 $3c1 N012 ( 5, 4) [000553] -A---------- | | \--* ASG ref $VN.Void N010 ( 3, 2) [000551] *------N---- | | +--* IND ref N009 ( 1, 1) [000550] ------------ | | | \--* LCL_VAR byref V74 tmp44 u:2 Zero Fseq[Mantissa] $401 N011 ( 1, 1) [000552] -------N---- | | \--* LCL_VAR ref V52 tmp22 u:2 N019 ( 6, 6) [000560] -A---------- | \--* ASG int $VN.Void N017 ( 4, 4) [000558] *------N---- | +--* IND int N016 ( 2, 2) [000557] -------N---- | | \--* ADD byref $203 N014 ( 1, 1) [000555] ------------ | | +--* LCL_VAR byref V74 tmp44 u:2 (last use) $401 N015 ( 1, 1) [000556] ------------ | | \--* CNS_INT long 8 Fseq[Exponent] $101 N018 ( 1, 1) [000559] -------N---- | \--* LCL_VAR int V53 tmp23 u:2 N023 ( 3, 2) [000564] ------------ arg0 in rcx +--* LCL_VAR long V75 tmp45 u:2 (last use) $400 N025 ( 3, 3) [000566] ------------ arg1 in rdx +--* ADDR byref $403 N024 ( 3, 2) [000565] -------N---- | \--* LCL_VAR struct(AX) V73 tmp43 $3c2 N026 ( 1, 1) [000058] ------------ arg3 in r9 +--* LCL_VAR int V08 loc5 u:2 (last use) $242 N027 ( 1, 1) [000057] ------------ arg2 in r8 \--* CNS_INT int 0 $40 ***** BB10 STMT00017 (IL 0x061...0x063) N004 ( 7, 6) [000068] ------------ * JTRUE void N003 ( 5, 4) [000067] N------N---- \--* EQ int $351 N001 ( 3, 2) [000065] ------------ +--* LCL_VAR int V05 loc2 u:2 $34e N002 ( 1, 1) [000066] ------------ \--* CNS_INT int 0 $40 ------------ BB11 [065..070) -> BB13 (cond), preds={BB10} succs={BB12,BB13} ***** BB11 STMT00083 (IL ???... ???) N008 ( 23, 17) [000387] --CXG------- * JTRUE void N007 ( 21, 15) [000386] J-CXG--N---- \--* GE int $352 N004 ( 16, 10) [000385] --CXG------- +--* CAST long <- int $480 N003 ( 15, 8) [000383] --CXG------- | \--* CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent $291 N002 ( 1, 1) [000382] ------------ this in rcx | \--* LCL_VAR ref V01 arg1 u:1 $c0 N006 ( 4, 4) [000381] ---------U-- \--* CAST long <- ulong <- uint $481 N005 ( 3, 2) [000380] ------------ \--* LCL_VAR int V05 loc2 u:2 $34e ------------ BB12 [070..07A) (return), preds={BB11} succs={} ***** BB12 STMT00085 (IL 0x070...0x077) N006 ( 25, 13) [000396] -ACXG---R--- * ASG long $VN.Void N005 ( 3, 2) [000395] *--X---N---- +--* IND long $458 N004 ( 1, 1) [000392] ------------ | \--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N003 ( 21, 10) [000394] --CXG------- \--* CALLV ind long FloatingPointType.get_Infinity $458 N002 ( 1, 1) [000393] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 ***** BB12 STMT00108 (IL ???... ???) N002 ( 2, 2) [000521] ------------ * RETURN int $5ca N001 ( 1, 1) [000397] ------------ \--* CNS_INT int 3 $48 ------------ BB13 [07A..082), preds={BB11} succs={BB14} ***** BB13 STMT00084 (IL 0x07A...0x07D) N006 ( 20, 12) [000391] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen $VN.Void N004 ( 3, 3) [000389] ------------ arg0 in rcx +--* ADDR long $404 N003 ( 3, 2) [000388] ----G--N---- | \--* LCL_VAR struct(AX)(P) V11 loc8 | \--* ref V11._bits (offs=0x00) -> V54 tmp24 | \--* int V11._sign (offs=0x08) -> V55 tmp25 $3c3 N005 ( 3, 2) [000390] ------------ arg1 in rdx \--* LCL_VAR int V05 loc2 u:2 (last use) $34e ------------ BB14 [082..092) -> BB16 (cond), preds={BB10,BB13} succs={BB15,BB16} ***** BB14 STMT00019 (IL ???... ???) N023 ( 41, 28) [000077] -ACXG---R--- * ASG int $293 N022 ( 1, 1) [000076] D------N---- +--* LCL_VAR int V13 loc10 d:2 $293 N021 ( 41, 28) [000072] -ACXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $293 N016 ( 18, 15) [000591] -A--G-----L- arg0 SETUP +--* COMMA void $VN.Void N009 ( 10, 8) [000584] -A--G------- | +--* COMMA void $VN.Void N004 ( 3, 3) [000579] -A------R--- | | +--* ASG byref $405 N003 ( 1, 1) [000578] D------N---- | | | +--* LCL_VAR byref V77 tmp47 d:2 $405 N002 ( 3, 3) [000576] ------------ | | | \--* ADDR byref $405 N001 ( 3, 2) [000577] -------N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 $3c4 N008 ( 7, 5) [000583] -A--G------- | | \--* ASG ref $VN.Void N006 ( 3, 2) [000581] *------N---- | | +--* IND ref $181 N005 ( 1, 1) [000580] ------------ | | | \--* LCL_VAR byref V77 tmp47 u:2 Zero Fseq[_bits] $405 N007 ( 3, 2) [000582] ----G--N---- | | \--* LCL_VAR ref (AX) V54 tmp24 $181 N015 ( 8, 7) [000590] -A--G------- | \--* ASG int $VN.Void N013 ( 4, 4) [000588] *------N---- | +--* IND int $243 N012 ( 2, 2) [000587] -------N---- | | \--* ADD byref $206 N010 ( 1, 1) [000585] ------------ | | +--* LCL_VAR byref V77 tmp47 u:2 (last use) $405 N011 ( 1, 1) [000586] ------------ | | \--* CNS_INT long 8 Fseq[_sign] $101 N014 ( 3, 2) [000589] ----G--N---- | \--* LCL_VAR int (AX) V55 tmp25 $243 N019 ( 3, 3) [000593] ------------ arg0 in rcx +--* ADDR byref $407 N018 ( 3, 2) [000592] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 $3c5 N020 ( 3, 3) [000071] ------------ arg1 in rdx \--* LCL_VAR_ADDR long V12 loc9 $443 ***** BB14 STMT00020 (IL 0x08D...0x090) N004 ( 7, 6) [000081] ------------ * JTRUE void N003 ( 5, 4) [000080] N------N-U-- \--* GE int $353 N001 ( 1, 1) [000078] ------------ +--* LCL_VAR int V13 loc10 u:2 $293 N002 ( 3, 2) [000079] ------------ \--* LCL_VAR int V03 loc0 u:2 $348 ------------ BB15 [092..096) -> BB17 (cond), preds={BB14} succs={BB16,BB17} ***** BB15 STMT00022 (IL 0x092...0x094) N004 ( 5, 5) [000094] ------------ * JTRUE void N003 ( 3, 3) [000093] J------N---- \--* NE int N001 ( 1, 1) [000091] ------------ +--* LCL_VAR int V10 loc7 u:2 N002 ( 1, 1) [000092] ------------ \--* CNS_INT int 0 $40 ------------ BB16 [096..0A7) -> BB44 (always), preds={BB14,BB15} succs={BB44} ***** BB16 STMT00021 (IL 0x096...0x0A6) N014 ( 29, 17) [000600] -ACXG---R--- * ASG int $5c7 N013 ( 1, 1) [000599] D------N---- +--* LCL_VAR int V51 tmp21 d:3 $5c7 N012 ( 29, 17) [000089] --CXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits $5c7 N005 ( 1, 1) [000088] ------------ arg4 out+20 +--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N008 ( 6, 3) [000086] N----------- arg2 in r8 +--* NE int N006 ( 1, 1) [000084] ------------ | +--* LCL_VAR int V10 loc7 u:2 (last use) N007 ( 1, 1) [000085] ------------ | \--* CNS_INT int 0 $40 N009 ( 3, 2) [000082] ----G------- arg0 in rcx +--* LCL_VAR ref (AX) V12 loc9 $18d N010 ( 1, 1) [000083] ------------ arg1 in rdx +--* LCL_VAR int V13 loc10 u:2 (last use) $293 N011 ( 1, 1) [000087] ------------ arg3 in r9 \--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 ------------ BB17 [0A7..0B0) -> BB19 (cond), preds={BB15} succs={BB18,BB19} ***** BB17 STMT00023 (IL 0x0A7...0x0AE) N004 ( 5, 5) [000100] ----G------- * JTRUE void N003 ( 3, 3) [000099] J---G--N---- \--* LT int N001 ( 1, 1) [000097] ------------ +--* LCL_VAR int V53 tmp23 u:2 N002 ( 1, 1) [000098] ------------ \--* CNS_INT int 0 $40 ------------ BB18 [0B0..0B4) -> BB20 (always), preds={BB17} succs={BB20} ***** BB18 STMT00081 (IL 0x0B0...0x0B2) N003 ( 5, 4) [000378] -A------R--- * ASG int N002 ( 3, 2) [000377] D------N---- +--* LCL_VAR int V32 tmp2 d:4 N001 ( 1, 1) [000376] ------------ \--* LCL_VAR int V10 loc7 u:2 ------------ BB19 [0B4..0BE), preds={BB17} succs={BB20} ***** BB19 STMT00024 (IL 0x0B4...0x0BD) N005 ( 7, 6) [000108] -A--G---R--- * ASG int N004 ( 3, 2) [000107] D------N---- +--* LCL_VAR int V32 tmp2 d:3 N003 ( 3, 3) [000106] ----G------- \--* SUB int N001 ( 1, 1) [000101] ------------ +--* LCL_VAR int V10 loc7 u:2 N002 ( 1, 1) [000104] ------------ \--* LCL_VAR int V53 tmp23 u:2 ------------ BB20 [0BE..0C4) -> BB23 (cond), preds={BB18,BB19} succs={BB21,BB23} ***** BB20 STMT00120 (IL ???... ???) N005 ( 0, 0) [000880] -A------R--- * ASG int N004 ( 0, 0) [000878] D------N---- +--* LCL_VAR int V32 tmp2 d:2 N003 ( 0, 0) [000879] ------------ \--* PHI int N001 ( 0, 0) [000905] ------------ pred BB18 +--* PHI_ARG int V32 tmp2 u:4 N002 ( 0, 0) [000904] ------------ pred BB19 \--* PHI_ARG int V32 tmp2 u:3 ***** BB20 STMT00025 (IL ???...0x0BE) N003 ( 7, 5) [000112] -A------R--- * ASG int $244 N002 ( 3, 2) [000111] D------N---- +--* LCL_VAR int V14 loc11 d:2 $244 N001 ( 3, 2) [000110] ------------ \--* LCL_VAR int V32 tmp2 u:2 (last use) $244 ***** BB20 STMT00026 (IL 0x0C0...0x0C2) N004 ( 5, 5) [000116] ------------ * JTRUE void N003 ( 3, 3) [000115] J------N---- \--* NE int $35a N001 ( 1, 1) [000113] ------------ +--* LCL_VAR int V13 loc10 u:2 $293 N002 ( 1, 1) [000114] ------------ \--* CNS_INT int 0 $40 ------------ BB21 [0C4..0D9) -> BB23 (cond), preds={BB20} succs={BB22,BB23} ***** BB21 STMT00077 (IL ???... ???) N008 ( 13, 13) [000363] -A-XG---R--- * ASG long N007 ( 3, 2) [000362] D------N---- +--* LCL_VAR long V38 tmp8 d:2 N006 ( 9, 10) [000359] ---XG---R--- \--* SUB long N005 ( 4, 4) [000353] ---------U-- +--* CAST long <- ulong <- uint $486 N004 ( 3, 2) [000352] ------------ | \--* LCL_VAR int V14 loc11 u:2 $244 N003 ( 4, 5) [000358] ---XG------- \--* CAST long <- int N002 ( 3, 3) [000456] ---XG------- \--* ARR_LENGTH int N001 ( 1, 1) [000455] ------------ \--* LCL_VAR ref V52 tmp22 u:2 ***** BB21 STMT00078 (IL ???... ???) N007 ( 22, 15) [000368] --CXG------- * JTRUE void N006 ( 20, 13) [000367] J-CXG--N---- \--* GE int N004 ( 16, 10) [000366] --CXG------- +--* CAST long <- int $48b N003 ( 15, 8) [000361] --CXG------- | \--* CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent $298 N002 ( 1, 1) [000360] ------------ this in rcx | \--* LCL_VAR ref V01 arg1 u:1 $c0 N005 ( 3, 2) [000364] ------------ \--* LCL_VAR long V38 tmp8 u:2 (last use) ------------ BB22 [0D9..0E3) (return), preds={BB21} succs={} ***** BB22 STMT00079 (IL 0x0D9...0x0E0) N006 ( 25, 13) [000373] -ACXG---R--- * ASG long $VN.Void N005 ( 3, 2) [000372] *--X---N---- +--* IND long $457 N004 ( 1, 1) [000369] ------------ | \--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N003 ( 21, 10) [000371] --CXG------- \--* CALLV ind long FloatingPointType.get_Zero $457 N002 ( 1, 1) [000370] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 ***** BB22 STMT00110 (IL ???... ???) N002 ( 2, 2) [000524] ------------ * RETURN int $5c4 N001 ( 1, 1) [000374] ------------ \--* CNS_INT int 2 $42 ------------ BB23 [0E3..117) -> BB25 (cond), preds={BB20,BB21} succs={BB24,BB25} ***** BB23 STMT00028 (IL ???... ???) N028 ( 53, 37) [000120] SACXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger $VN.Void N004 ( 7, 6) [000623] -A------R-L- arg0 SETUP +--* ASG long $408 N003 ( 3, 2) [000622] D------N---- | +--* LCL_VAR long V79 tmp49 d:2 $408 N002 ( 3, 3) [000125] ------------ | \--* ADDR long $408 N001 ( 3, 2) [000124] ----G--N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 $3c6 N020 ( 14, 13) [000621] -A--------L- arg1 SETUP +--* COMMA void $VN.Void N013 ( 8, 7) [000614] -A---------- | +--* COMMA void $VN.Void N008 ( 3, 3) [000609] -A------R--- | | +--* ASG byref $409 N007 ( 1, 1) [000608] D------N---- | | | +--* LCL_VAR byref V78 tmp48 d:2 $409 N006 ( 3, 3) [000606] ------------ | | | \--* ADDR byref $409 N005 ( 3, 2) [000607] ----G--N---- | | | \--* LCL_VAR struct(AX) V73 tmp43 $3c7 N012 ( 5, 4) [000613] -A---------- | | \--* ASG ref $VN.Void N010 ( 3, 2) [000611] *------N---- | | +--* IND ref N009 ( 1, 1) [000610] ------------ | | | \--* LCL_VAR byref V78 tmp48 u:2 Zero Fseq[Mantissa] $409 N011 ( 1, 1) [000612] -------N---- | | \--* LCL_VAR ref V52 tmp22 u:2 (last use) N019 ( 6, 6) [000620] -A---------- | \--* ASG int $VN.Void N017 ( 4, 4) [000618] *------N---- | +--* IND int N016 ( 2, 2) [000617] -------N---- | | \--* ADD byref $209 N014 ( 1, 1) [000615] ------------ | | +--* LCL_VAR byref V78 tmp48 u:2 (last use) $409 N015 ( 1, 1) [000616] ------------ | | \--* CNS_INT long 8 Fseq[Exponent] $101 N018 ( 1, 1) [000619] -------N---- | \--* LCL_VAR int V53 tmp23 u:2 (last use) N023 ( 3, 2) [000624] ------------ arg0 in rcx +--* LCL_VAR long V79 tmp49 u:2 (last use) $408 N025 ( 3, 3) [000626] ------------ arg1 in rdx +--* ADDR byref $40b N024 ( 3, 2) [000625] -------N---- | \--* LCL_VAR struct(AX) V73 tmp43 $3c8 N026 ( 3, 2) [000118] ------------ arg2 in r8 +--* LCL_VAR int V08 loc5 u:2 (last use) $242 N027 ( 3, 2) [000119] ------------ arg3 in r9 \--* LCL_VAR int V09 loc6 u:2 (last use) ***** BB23 STMT00029 (IL 0x0EF...0x0F4) N005 ( 17, 21) [000133] H-CXG------- * CALL help long HELPER.CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE $48d N003 ( 2, 10) [000131] ------------ arg0 in rcx +--* CNS_INT long 0x7ff815262aa0 $102 N004 ( 1, 4) [000132] ------------ arg1 in rdx \--* CNS_INT int 173 $58 ***** BB23 STMT00030 (IL ???... ???) N018 ( 21, 26) [000649] -A-XG------- * COMMA void N011 ( 13, 19) [000642] -A-XG------- +--* COMMA void N006 ( 6, 14) [000637] -A--G---R--- | +--* ASG byref N005 ( 1, 1) [000636] D------N---- | | +--* LCL_VAR byref V80 tmp50 d:2 N004 ( 6, 14) [000632] ----G------- | | \--* ADD byref N002 ( 4, 12) [000633] n---G------- | | +--* IND ref N001 ( 2, 10) [000634] I----------- | | | \--* CNS_INT(h) long 0xd1ffab1e static Fseq[BigOne] $4c2 N003 ( 1, 1) [000635] ------------ | | \--* CNS_INT long 8 Fseq[#FirstElem] $101 N010 ( 7, 5) [000641] -A-XG---R--- | \--* ASG ref N009 ( 3, 2) [000638] D---G--N---- | +--* LCL_VAR ref (AX) V58 tmp28 N008 ( 3, 2) [000640] ---X-------- | \--* IND ref N007 ( 1, 1) [000639] ------------ | \--* LCL_VAR byref V80 tmp50 u:2 Zero Fseq[_bits] N017 ( 8, 7) [000648] -A-XG---R--- \--* ASG int N016 ( 3, 2) [000643] D---G--N---- +--* LCL_VAR int (AX) V59 tmp29 N015 ( 4, 4) [000647] ---X-------- \--* IND int N014 ( 2, 2) [000646] -------N---- \--* ADD byref N012 ( 1, 1) [000644] ------------ +--* LCL_VAR byref V80 tmp50 u:2 (last use) N013 ( 1, 1) [000645] ------------ \--* CNS_INT long 8 Fseq[_sign] $101 ***** BB23 STMT00031 (IL 0x0F6...0x106) N006 ( 20, 12) [000141] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen $VN.Void N004 ( 3, 3) [000139] ------------ arg0 in rcx +--* ADDR long $40d N003 ( 3, 2) [000138] ----G--N---- | \--* LCL_VAR struct(AX)(P) V16 loc13 | \--* ref V16._bits (offs=0x00) -> V58 tmp28 | \--* int V16._sign (offs=0x08) -> V59 tmp29 $3c9 N005 ( 3, 2) [000140] ------------ arg1 in rdx \--* LCL_VAR int V14 loc11 u:2 (last use) $244 ***** BB23 STMT00099 (IL 0x0FF... ???) N007 ( 14, 10) [000658] -A--G------- * COMMA void $246 N003 ( 7, 5) [000654] -A--G---R--- +--* ASG ref $184 N002 ( 3, 2) [000652] D------N---- | +--* LCL_VAR ref V64 tmp34 d:2 $184 N001 ( 3, 2) [000653] ----G--N---- | \--* LCL_VAR ref (AX) V56 tmp26 $184 N006 ( 7, 5) [000657] -A--G---R--- \--* ASG int $246 N005 ( 3, 2) [000655] D------N---- +--* LCL_VAR int V65 tmp35 d:2 $246 N004 ( 3, 2) [000656] ----G--N---- \--* LCL_VAR int (AX) V57 tmp27 $246 ***** BB23 STMT00098 (IL 0x0FF... ???) N023 ( 45, 31) [000468] -ACXG---R--- * ASG int $29f N022 ( 3, 2) [000467] D------N---- +--* LCL_VAR int V43 tmp13 d:2 $29f N021 ( 41, 28) [000463] -ACXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $29f N016 ( 18, 15) [000677] -A--------L- arg0 SETUP +--* COMMA void $VN.Void N009 ( 10, 8) [000670] -A---------- | +--* COMMA void $VN.Void N004 ( 3, 3) [000665] -A------R--- | | +--* ASG byref $40e N003 ( 1, 1) [000664] D------N---- | | | +--* LCL_VAR byref V81 tmp51 d:2 $40e N002 ( 3, 3) [000662] ------------ | | | \--* ADDR byref $40e N001 ( 3, 2) [000663] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 $3ca N008 ( 7, 5) [000669] -A---------- | | \--* ASG ref $VN.Void N006 ( 3, 2) [000667] *------N---- | | +--* IND ref $184 N005 ( 1, 1) [000666] ------------ | | | \--* LCL_VAR byref V81 tmp51 u:2 Zero Fseq[_bits] $40e N007 ( 3, 2) [000668] -------N---- | | \--* LCL_VAR ref V64 tmp34 u:2 (last use) $184 N015 ( 8, 7) [000676] -A---------- | \--* ASG int $VN.Void N013 ( 4, 4) [000674] *------N---- | +--* IND int $246 N012 ( 2, 2) [000673] -------N---- | | \--* ADD byref $211 N010 ( 1, 1) [000671] ------------ | | +--* LCL_VAR byref V81 tmp51 u:2 (last use) $40e N011 ( 1, 1) [000672] ------------ | | \--* CNS_INT long 8 Fseq[_sign] $101 N014 ( 3, 2) [000675] -------N---- | \--* LCL_VAR int V65 tmp35 u:2 (last use) $246 N019 ( 3, 3) [000679] ------------ arg0 in rcx +--* ADDR byref $410 N018 ( 3, 2) [000678] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 $3cb N020 ( 3, 3) [000462] ------------ arg1 in rdx \--* LCL_VAR_ADDR long V45 tmp15 $449 ***** BB23 STMT00100 (IL 0x0FF... ???) N003 ( 5, 4) [000475] -A--G---R--- * ASG ref $VN.Null N002 ( 3, 2) [000474] D---G--N---- +--* LCL_VAR ref (AX) V45 tmp15 N001 ( 1, 1) [000473] ------------ \--* CNS_INT ref null $VN.Null ***** BB23 STMT00033 (IL ???... ???) N003 ( 7, 5) [000148] -A------R--- * ASG int $29f N002 ( 3, 2) [000147] D------N---- +--* LCL_VAR int V17 loc14 d:2 $29f N001 ( 3, 2) [000469] ------------ \--* LCL_VAR int V43 tmp13 u:2 $29f ***** BB23 STMT00103 (IL 0x108... ???) N007 ( 14, 10) [000687] -A--G------- * COMMA void $247 N003 ( 7, 5) [000683] -A--G---R--- +--* ASG ref $185 N002 ( 3, 2) [000681] D------N---- | +--* LCL_VAR ref V66 tmp36 d:2 $185 N001 ( 3, 2) [000682] ----G--N---- | \--* LCL_VAR ref (AX) V58 tmp28 $185 N006 ( 7, 5) [000686] -A--G---R--- \--* ASG int $247 N005 ( 3, 2) [000684] D------N---- +--* LCL_VAR int V67 tmp37 d:2 $247 N004 ( 3, 2) [000685] ----G--N---- \--* LCL_VAR int (AX) V59 tmp29 $247 ***** BB23 STMT00102 (IL 0x108... ???) N023 ( 45, 31) [000486] -ACXG---R--- * ASG int $2a3 N022 ( 3, 2) [000485] D------N---- +--* LCL_VAR int V46 tmp16 d:2 $2a3 N021 ( 41, 28) [000481] -ACXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $2a3 N016 ( 18, 15) [000706] -A--------L- arg0 SETUP +--* COMMA void $VN.Void N009 ( 10, 8) [000699] -A---------- | +--* COMMA void $VN.Void N004 ( 3, 3) [000694] -A------R--- | | +--* ASG byref $411 N003 ( 1, 1) [000693] D------N---- | | | +--* LCL_VAR byref V82 tmp52 d:2 $411 N002 ( 3, 3) [000691] ------------ | | | \--* ADDR byref $411 N001 ( 3, 2) [000692] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 $3cc N008 ( 7, 5) [000698] -A---------- | | \--* ASG ref $VN.Void N006 ( 3, 2) [000696] *------N---- | | +--* IND ref $185 N005 ( 1, 1) [000695] ------------ | | | \--* LCL_VAR byref V82 tmp52 u:2 Zero Fseq[_bits] $411 N007 ( 3, 2) [000697] -------N---- | | \--* LCL_VAR ref V66 tmp36 u:2 (last use) $185 N015 ( 8, 7) [000705] -A---------- | \--* ASG int $VN.Void N013 ( 4, 4) [000703] *------N---- | +--* IND int $247 N012 ( 2, 2) [000702] -------N---- | | \--* ADD byref $214 N010 ( 1, 1) [000700] ------------ | | +--* LCL_VAR byref V82 tmp52 u:2 (last use) $411 N011 ( 1, 1) [000701] ------------ | | \--* CNS_INT long 8 Fseq[_sign] $101 N014 ( 3, 2) [000704] -------N---- | \--* LCL_VAR int V67 tmp37 u:2 (last use) $247 N019 ( 3, 3) [000708] ------------ arg0 in rcx +--* ADDR byref $413 N018 ( 3, 2) [000707] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 $3cd N020 ( 3, 3) [000480] ------------ arg1 in rdx \--* LCL_VAR_ADDR long V48 tmp18 $44b ***** BB23 STMT00104 (IL 0x108... ???) N003 ( 5, 4) [000493] -A--G---R--- * ASG ref $VN.Null N002 ( 3, 2) [000492] D---G--N---- +--* LCL_VAR ref (AX) V48 tmp18 N001 ( 1, 1) [000491] ------------ \--* CNS_INT ref null $VN.Null ***** BB23 STMT00035 (IL ???... ???) N003 ( 7, 5) [000155] -A------R--- * ASG int $2a3 N002 ( 3, 2) [000154] D------N---- +--* LCL_VAR int V18 loc15 d:2 $2a3 N001 ( 3, 2) [000487] ------------ \--* LCL_VAR int V46 tmp16 u:2 $2a3 ***** BB23 STMT00036 (IL 0x111...0x115) N004 ( 9, 7) [000159] ------------ * JTRUE void N003 ( 7, 5) [000158] N------N-U-- \--* GT int $35f N001 ( 3, 2) [000156] ------------ +--* LCL_VAR int V18 loc15 u:2 (last use) $2a3 N002 ( 3, 2) [000157] ------------ \--* LCL_VAR int V17 loc14 u:2 (last use) $29f ------------ BB24 [117..11A) -> BB26 (always), preds={BB23} succs={BB26} ***** BB24 STMT00074 (IL 0x117...0x118) N003 ( 5, 4) [000350] -A------R--- * ASG int $40 N002 ( 3, 2) [000349] D------N---- +--* LCL_VAR int V33 tmp3 d:4 $40 N001 ( 1, 1) [000348] ------------ \--* CNS_INT int 0 $40 ------------ BB25 [11A..11F), preds={BB23} succs={BB26} ***** BB25 STMT00037 (IL 0x11A...0x11E) N005 ( 11, 8) [000164] -A------R--- * ASG int $360 N004 ( 3, 2) [000163] D------N---- +--* LCL_VAR int V33 tmp3 d:3 $360 N003 ( 7, 5) [000162] ------------ \--* SUB int $360 N001 ( 3, 2) [000160] ------------ +--* LCL_VAR int V18 loc15 u:2 (last use) $2a3 N002 ( 3, 2) [000161] ------------ \--* LCL_VAR int V17 loc14 u:2 (last use) $29f ------------ BB26 [11F..126) -> BB28 (cond), preds={BB24,BB25} succs={BB27,BB28} ***** BB26 STMT00119 (IL ???... ???) N005 ( 0, 0) [000877] -A------R--- * ASG int N004 ( 0, 0) [000875] D------N---- +--* LCL_VAR int V33 tmp3 d:2 N003 ( 0, 0) [000876] ------------ \--* PHI int N001 ( 0, 0) [000903] ------------ pred BB24 +--* PHI_ARG int V33 tmp3 u:4 $40 N002 ( 0, 0) [000902] ------------ pred BB25 \--* PHI_ARG int V33 tmp3 u:3 $360 ***** BB26 STMT00038 (IL ???...0x11F) N003 ( 3, 3) [000168] -A------R--- * ASG int $248 N002 ( 1, 1) [000167] D------N---- +--* LCL_VAR int V19 loc16 d:2 $248 N001 ( 3, 2) [000166] ------------ \--* LCL_VAR int V33 tmp3 u:2 $248 ***** BB26 STMT00039 (IL 0x121...0x124) N004 ( 7, 6) [000172] ------------ * JTRUE void N003 ( 5, 4) [000171] N------N---- \--* EQ int $361 N001 ( 3, 2) [000169] ------------ +--* LCL_VAR int V19 loc16 u:2 (last use) $248 N002 ( 1, 1) [000170] ------------ \--* CNS_INT int 0 $40 ------------ BB27 [126..12F), preds={BB26} succs={BB28} ***** BB27 STMT00073 (IL 0x126...0x12A) N006 ( 18, 11) [000347] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft $VN.Void N004 ( 3, 3) [000345] ------------ arg0 in rcx +--* ADDR long $414 N003 ( 3, 2) [000344] ----G--N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 $3ce N005 ( 1, 1) [000346] ------------ arg1 in rdx \--* LCL_VAR int V19 loc16 u:2 $248 ------------ BB28 [12F..13E) -> BB32 (cond), preds={BB26,BB27} succs={BB29,BB32} ***** BB28 STMT00040 (IL 0x12F...0x133) N005 ( 9, 7) [000177] -A------R--- * ASG int $362 N004 ( 3, 2) [000176] D------N---- +--* LCL_VAR int V20 loc17 d:2 $362 N003 ( 5, 4) [000175] ------------ \--* SUB int $362 N001 ( 3, 2) [000173] ------------ +--* LCL_VAR int V03 loc0 u:2 (last use) $348 N002 ( 1, 1) [000174] ------------ \--* LCL_VAR int V13 loc10 u:2 $293 ***** BB28 STMT00041 (IL 0x135...0x137) N003 ( 7, 5) [000180] -A------R--- * ASG int $362 N002 ( 3, 2) [000179] D------N---- +--* LCL_VAR int V21 loc18 d:2 $362 N001 ( 3, 2) [000178] ------------ \--* LCL_VAR int V20 loc17 u:2 $362 ***** BB28 STMT00042 (IL 0x139...0x13C) N004 ( 5, 5) [000184] ------------ * JTRUE void N003 ( 3, 3) [000183] N------N---- \--* EQ int $363 N001 ( 1, 1) [000181] ------------ +--* LCL_VAR int V13 loc10 u:2 $293 N002 ( 1, 1) [000182] ------------ \--* CNS_INT int 0 $40 ------------ BB29 [13E..144) -> BB31 (cond), preds={BB28} succs={BB30,BB31} ***** BB29 STMT00070 (IL 0x13E...0x142) N004 ( 7, 6) [000329] ------------ * JTRUE void N003 ( 5, 4) [000328] N------N-U-- \--* LE int $364 N001 ( 1, 1) [000326] ------------ +--* LCL_VAR int V19 loc16 u:2 $248 N002 ( 3, 2) [000327] ------------ \--* LCL_VAR int V20 loc17 u:2 $362 ------------ BB30 [144..155) -> BB44 (always), preds={BB29} succs={BB44} ***** BB30 STMT00072 (IL 0x144...0x154) N014 ( 29, 17) [000717] -ACXG---R--- * ASG int $5c2 N013 ( 1, 1) [000716] D------N---- +--* LCL_VAR int V51 tmp21 d:5 $5c2 N012 ( 29, 17) [000342] --CXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits $5c2 N005 ( 1, 1) [000341] ------------ arg4 out+20 +--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N008 ( 6, 3) [000339] N----------- arg2 in r8 +--* NE int N006 ( 1, 1) [000337] ------------ | +--* LCL_VAR int V10 loc7 u:2 (last use) N007 ( 1, 1) [000338] ------------ | \--* CNS_INT int 0 $40 N009 ( 3, 2) [000335] ----G------- arg0 in rcx +--* LCL_VAR ref (AX) V12 loc9 $18c N010 ( 1, 1) [000336] ------------ arg1 in rdx +--* LCL_VAR int V13 loc10 u:2 (last use) $293 N011 ( 1, 1) [000340] ------------ arg3 in r9 \--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 ------------ BB31 [155..15C), preds={BB29} succs={BB32} ***** BB31 STMT00071 (IL 0x155...0x15A) N005 ( 9, 7) [000334] -A------R--- * ASG int $365 N004 ( 3, 2) [000333] D------N---- +--* LCL_VAR int V21 loc18 d:4 $365 N003 ( 5, 4) [000332] ------------ \--* SUB int $365 N001 ( 3, 2) [000330] ------------ +--* LCL_VAR int V20 loc17 u:2 (last use) $362 N002 ( 1, 1) [000331] ------------ \--* LCL_VAR int V19 loc16 u:2 $248 ------------ BB32 [15C..167) -> BB34 (cond), preds={BB28,BB31} succs={BB33,BB34} ***** BB32 STMT00118 (IL ???... ???) N005 ( 0, 0) [000874] -A------R--- * ASG int N004 ( 0, 0) [000872] D------N---- +--* LCL_VAR int V21 loc18 d:3 N003 ( 0, 0) [000873] ------------ \--* PHI int N001 ( 0, 0) [000900] ------------ pred BB31 +--* PHI_ARG int V21 loc18 u:4 $365 N002 ( 0, 0) [000888] ------------ pred BB28 \--* PHI_ARG int V21 loc18 u:2 $362 ***** BB32 STMT00105 (IL 0x15C... ???) N007 ( 14, 10) [000724] -A--G------- * COMMA void $24a N003 ( 7, 5) [000720] -A--G---R--- +--* ASG ref $186 N002 ( 3, 2) [000718] D---G--N---- | +--* LCL_VAR ref (AX) V68 tmp38 N001 ( 3, 2) [000719] ----G--N---- | \--* LCL_VAR ref (AX) V56 tmp26 $186 N006 ( 7, 5) [000723] -A--G---R--- \--* ASG int $24a N005 ( 3, 2) [000721] D---G--N---- +--* LCL_VAR int (AX) V69 tmp39 N004 ( 3, 2) [000722] ----G--N---- \--* LCL_VAR int (AX) V57 tmp27 $24a ***** BB32 STMT00106 (IL 0x15C... ???) N007 ( 14, 10) [000731] -A--G------- * COMMA void $24b N003 ( 7, 5) [000727] -A--G---R--- +--* ASG ref $187 N002 ( 3, 2) [000725] D------N---- | +--* LCL_VAR ref V70 tmp40 d:2 $187 N001 ( 3, 2) [000726] ----G--N---- | \--* LCL_VAR ref (AX) V58 tmp28 $187 N006 ( 7, 5) [000730] -A--G---R--- \--* ASG int $24b N005 ( 3, 2) [000728] D------N---- +--* LCL_VAR int V71 tmp41 d:2 $24b N004 ( 3, 2) [000729] ----G--N---- \--* LCL_VAR int (AX) V59 tmp29 $24b ***** BB32 STMT00044 (IL ???... ???) N027 ( 52, 38) [000195] -ACXG------- * JTRUE void N026 ( 50, 36) [000503] JACXG--N---- \--* LT int $367 N024 ( 48, 34) [000499] -ACXG------- +--* CALL int System.Numerics.BigInteger.CompareTo $2ae N004 ( 7, 6) [000752] -A------R-L- this SETUP | +--* ASG byref $415 N003 ( 3, 2) [000751] D------N---- | | +--* LCL_VAR byref V84 tmp54 d:2 $415 N002 ( 3, 3) [000497] ------------ | | \--* ADDR byref $415 N001 ( 3, 2) [000496] ----G--N---- | | \--* LCL_VAR struct(AX)(P) V49 tmp19 | | \--* ref V49._bits (offs=0x00) -> V68 tmp38 | | \--* int V49._sign (offs=0x08) -> V69 tmp39 $3cf N020 ( 18, 15) [000750] -A--------L- arg1 SETUP | +--* COMMA void $VN.Void N013 ( 10, 8) [000743] -A---------- | | +--* COMMA void $VN.Void N008 ( 3, 3) [000738] -A------R--- | | | +--* ASG byref $417 N007 ( 1, 1) [000737] D------N---- | | | | +--* LCL_VAR byref V83 tmp53 d:2 $417 N006 ( 3, 3) [000735] ------------ | | | | \--* ADDR byref $417 N005 ( 3, 2) [000736] ----G--N---- | | | | \--* LCL_VAR struct(AX) V76 tmp46 $3d0 N012 ( 7, 5) [000742] -A---------- | | | \--* ASG ref $VN.Void N010 ( 3, 2) [000740] *------N---- | | | +--* IND ref $187 N009 ( 1, 1) [000739] ------------ | | | | \--* LCL_VAR byref V83 tmp53 u:2 Zero Fseq[_bits] $417 N011 ( 3, 2) [000741] -------N---- | | | \--* LCL_VAR ref V70 tmp40 u:2 (last use) $187 N019 ( 8, 7) [000749] -A---------- | | \--* ASG int $VN.Void N017 ( 4, 4) [000747] *------N---- | | +--* IND int $24b N016 ( 2, 2) [000746] -------N---- | | | \--* ADD byref $216 N014 ( 1, 1) [000744] ------------ | | | +--* LCL_VAR byref V83 tmp53 u:2 (last use) $417 N015 ( 1, 1) [000745] ------------ | | | \--* CNS_INT long 8 Fseq[_sign] $101 N018 ( 3, 2) [000748] -------N---- | | \--* LCL_VAR int V71 tmp41 u:2 (last use) $24b N021 ( 3, 2) [000753] ------------ this in rcx | +--* LCL_VAR byref V84 tmp54 u:2 (last use) $415 N023 ( 3, 3) [000755] ------------ arg1 in rdx | \--* ADDR byref $419 N022 ( 3, 2) [000754] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 $3d1 N025 ( 1, 1) [000502] ------------ \--* CNS_INT int 0 $40 ------------ BB33 [167..16B) -> BB35 (always), preds={BB32} succs={BB35} ***** BB33 STMT00069 (IL 0x167...0x169) N003 ( 5, 4) [000324] -A------R--- * ASG int $248 N002 ( 3, 2) [000323] D------N---- +--* LCL_VAR int V34 tmp4 d:4 $248 N001 ( 1, 1) [000322] ------------ \--* LCL_VAR int V19 loc16 u:2 (last use) $248 ------------ BB34 [16B..16F), preds={BB32} succs={BB35} ***** BB34 STMT00045 (IL 0x16B...0x16E) N005 ( 7, 6) [000200] -A------R--- * ASG int $368 N004 ( 3, 2) [000199] D------N---- +--* LCL_VAR int V34 tmp4 d:3 $368 N003 ( 3, 3) [000198] ------------ \--* ADD int $368 N001 ( 1, 1) [000196] ------------ +--* LCL_VAR int V19 loc16 u:2 (last use) $248 N002 ( 1, 1) [000197] ------------ \--* CNS_INT int 1 $41 ------------ BB35 [16F..1A4) -> BB40 (cond), preds={BB33,BB34} succs={BB36,BB40} ***** BB35 STMT00117 (IL ???... ???) N005 ( 0, 0) [000871] -A------R--- * ASG int N004 ( 0, 0) [000869] D------N---- +--* LCL_VAR int V34 tmp4 d:2 N003 ( 0, 0) [000870] ------------ \--* PHI int N001 ( 0, 0) [000899] ------------ pred BB33 +--* PHI_ARG int V34 tmp4 u:4 $248 N002 ( 0, 0) [000898] ------------ pred BB34 \--* PHI_ARG int V34 tmp4 u:3 $368 ***** BB35 STMT00046 (IL ???...0x16F) N003 ( 7, 5) [000204] -A------R--- * ASG int $24c N002 ( 3, 2) [000203] D------N---- +--* LCL_VAR int V22 loc19 d:2 $24c N001 ( 3, 2) [000202] ------------ \--* LCL_VAR int V34 tmp4 u:2 (last use) $24c ***** BB35 STMT00047 (IL 0x171...0x18A) N006 ( 20, 12) [000208] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft $VN.Void N004 ( 3, 3) [000206] ------------ arg0 in rcx +--* ADDR long $41a N003 ( 3, 2) [000205] ----G--N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 $3d2 N005 ( 3, 2) [000207] ------------ arg1 in rdx \--* LCL_VAR int V21 loc18 u:3 (last use) $249 ***** BB35 STMT00048 (IL 0x17A... ???) N045 ( 78, 56) [000213] SACXG------- * CALL void System.Numerics.BigInteger.DivRem $VN.Void N004 ( 7, 6) [000797] -A------R-L- arg0 SETUP +--* ASG long $41b N003 ( 3, 2) [000796] D------N---- | +--* LCL_VAR long V88 tmp58 d:2 $41b N002 ( 3, 3) [000220] ------------ | \--* ADDR long $41b N001 ( 3, 2) [000219] ----G--N---- | \--* LCL_VAR struct(AX)(P) V35 tmp5 | \--* ref V35._bits (offs=0x00) -> V62 tmp32 | \--* int V35._sign (offs=0x08) -> V63 tmp33 $3d3 N020 ( 18, 15) [000776] -A--G-----L- arg1 SETUP +--* COMMA void $VN.Void N013 ( 10, 8) [000769] -A--G------- | +--* COMMA void $VN.Void N008 ( 3, 3) [000764] -A------R--- | | +--* ASG byref $41c N007 ( 1, 1) [000763] D------N---- | | | +--* LCL_VAR byref V85 tmp55 d:2 $41c N006 ( 3, 3) [000761] ------------ | | | \--* ADDR byref $41c N005 ( 3, 2) [000762] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 $3d4 N012 ( 7, 5) [000768] -A--G------- | | \--* ASG ref $VN.Void N010 ( 3, 2) [000766] *------N---- | | +--* IND ref $188 N009 ( 1, 1) [000765] ------------ | | | \--* LCL_VAR byref V85 tmp55 u:2 Zero Fseq[_bits] $41c N011 ( 3, 2) [000767] ----G--N---- | | \--* LCL_VAR ref (AX) V56 tmp26 $188 N019 ( 8, 7) [000775] -A--G------- | \--* ASG int $VN.Void N017 ( 4, 4) [000773] *------N---- | +--* IND int $24d N016 ( 2, 2) [000772] -------N---- | | \--* ADD byref $218 N014 ( 1, 1) [000770] ------------ | | +--* LCL_VAR byref V85 tmp55 u:2 (last use) $41c N015 ( 1, 1) [000771] ------------ | | \--* CNS_INT long 8 Fseq[_sign] $101 N018 ( 3, 2) [000774] ----G--N---- | \--* LCL_VAR int (AX) V57 tmp27 $24d N036 ( 18, 15) [000795] -A--G-----L- arg2 SETUP +--* COMMA void $VN.Void N029 ( 10, 8) [000788] -A--G------- | +--* COMMA void $VN.Void N024 ( 3, 3) [000783] -A------R--- | | +--* ASG byref $41e N023 ( 1, 1) [000782] D------N---- | | | +--* LCL_VAR byref V87 tmp57 d:2 $41e N022 ( 3, 3) [000780] ------------ | | | \--* ADDR byref $41e N021 ( 3, 2) [000781] -------N---- | | | \--* LCL_VAR struct(AX) V86 tmp56 $3d5 N028 ( 7, 5) [000787] -A--G------- | | \--* ASG ref $VN.Void N026 ( 3, 2) [000785] *------N---- | | +--* IND ref $189 N025 ( 1, 1) [000784] ------------ | | | \--* LCL_VAR byref V87 tmp57 u:2 Zero Fseq[_bits] $41e N027 ( 3, 2) [000786] ----G--N---- | | \--* LCL_VAR ref (AX) V58 tmp28 $189 N035 ( 8, 7) [000794] -A--G------- | \--* ASG int $VN.Void N033 ( 4, 4) [000792] *------N---- | +--* IND int $24e N032 ( 2, 2) [000791] -------N---- | | \--* ADD byref $21a N030 ( 1, 1) [000789] ------------ | | +--* LCL_VAR byref V87 tmp57 u:2 (last use) $41e N031 ( 1, 1) [000790] ------------ | | \--* CNS_INT long 8 Fseq[_sign] $101 N034 ( 3, 2) [000793] ----G--N---- | \--* LCL_VAR int (AX) V59 tmp29 $24e N038 ( 3, 2) [000798] ------------ arg0 in rcx +--* LCL_VAR long V88 tmp58 u:2 (last use) $41b N040 ( 3, 3) [000800] ------------ arg1 in rdx +--* ADDR byref $420 N039 ( 3, 2) [000799] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 $3d6 N042 ( 3, 3) [000802] ------------ arg2 in r8 +--* ADDR byref $421 N041 ( 3, 2) [000801] -------N---- | \--* LCL_VAR struct(AX) V86 tmp56 $3d7 N044 ( 3, 3) [000212] ------------ arg3 in r9 \--* ADDR long $422 N043 ( 3, 2) [000211] ----G--N---- \--* LCL_VAR struct(AX)(P) V23 loc20 \--* ref V23._bits (offs=0x00) -> V60 tmp30 \--* int V23._sign (offs=0x08) -> V61 tmp31 $3d8 ***** BB35 STMT00050 (IL ???... ???) N021 ( 38, 24) [000226] -ACXG---R--- * ASG long $450 N020 ( 1, 1) [000225] D------N---- +--* LCL_VAR long V24 loc21 d:2 $450 N019 ( 38, 24) [000218] -ACXG------- \--* CALL long System.Numerics.BigInteger.op_Explicit $450 N016 ( 18, 15) [000822] -A--G-----L- arg0 SETUP +--* COMMA void $VN.Void N009 ( 10, 8) [000815] -A--G------- | +--* COMMA void $VN.Void N004 ( 3, 3) [000810] -A------R--- | | +--* ASG byref $423 N003 ( 1, 1) [000809] D------N---- | | | +--* LCL_VAR byref V89 tmp59 d:2 $423 N002 ( 3, 3) [000807] ------------ | | | \--* ADDR byref $423 N001 ( 3, 2) [000808] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 $3d9 N008 ( 7, 5) [000814] -A--G------- | | \--* ASG ref $VN.Void N006 ( 3, 2) [000812] *------N---- | | +--* IND ref $18a N005 ( 1, 1) [000811] ------------ | | | \--* LCL_VAR byref V89 tmp59 u:2 Zero Fseq[_bits] $423 N007 ( 3, 2) [000813] ----G--N---- | | \--* LCL_VAR ref (AX) V62 tmp32 $18a N015 ( 8, 7) [000821] -A--G------- | \--* ASG int $VN.Void N013 ( 4, 4) [000819] *------N---- | +--* IND int $24f N012 ( 2, 2) [000818] -------N---- | | \--* ADD byref $21d N010 ( 1, 1) [000816] ------------ | | +--* LCL_VAR byref V89 tmp59 u:2 (last use) $423 N011 ( 1, 1) [000817] ------------ | | \--* CNS_INT long 8 Fseq[_sign] $101 N014 ( 3, 2) [000820] ----G--N---- | \--* LCL_VAR int (AX) V63 tmp33 $24f N018 ( 3, 3) [000824] ------------ arg0 in rcx \--* ADDR byref $425 N017 ( 3, 2) [000823] -------N---- \--* LCL_VAR struct(AX) V76 tmp46 $3da ***** BB35 STMT00052 (IL ???... ???) N005 ( 12, 7) [000232] -A--G---R--- * ASG int $369 N004 ( 3, 2) [000231] D------N---- +--* LCL_VAR int V25 loc22 d:2 $369 N003 ( 8, 4) [000516] ----G------- \--* EQ int $369 N001 ( 3, 2) [000514] ----G------- +--* LCL_VAR int (AX) V61 tmp31 $250 N002 ( 1, 1) [000515] ------------ \--* CNS_INT int 0 $40 ***** BB35 STMT00054 (IL ???... ???) N005 ( 19, 10) [000237] -ACXG---R--- * ASG int $2b4 N004 ( 3, 2) [000236] D------N---- +--* LCL_VAR int V26 loc23 d:2 $2b4 N003 ( 15, 7) [000234] --CXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $2b4 N002 ( 1, 1) [000233] ------------ arg0 in rcx \--* LCL_VAR long V24 loc21 u:2 $450 ***** BB35 STMT00055 (IL 0x19E...0x1A2) N004 ( 9, 7) [000241] ------------ * JTRUE void N003 ( 7, 5) [000240] N------N-U-- \--* LE int $36a N001 ( 3, 2) [000238] ------------ +--* LCL_VAR int V26 loc23 u:2 $2b4 N002 ( 3, 2) [000239] ------------ \--* LCL_VAR int V20 loc17 u:2 $362 ------------ BB36 [1A4..1AF) -> BB38 (cond), preds={BB35} succs={BB37,BB38} ***** BB36 STMT00063 (IL 0x1A4...0x1A9) N005 ( 11, 8) [000286] -A------R--- * ASG int $36b N004 ( 3, 2) [000285] D------N---- +--* LCL_VAR int V29 loc26 d:2 $36b N003 ( 7, 5) [000284] ------------ \--* SUB int $36b N001 ( 3, 2) [000282] ------------ +--* LCL_VAR int V26 loc23 u:2 (last use) $2b4 N002 ( 3, 2) [000283] ------------ \--* LCL_VAR int V20 loc17 u:2 $362 ***** BB36 STMT00064 (IL 0x1AB...0x1AD) N004 ( 7, 6) [000290] ------------ * JTRUE void N003 ( 5, 4) [000289] J------N---- \--* EQ int $36c N001 ( 3, 2) [000287] ------------ +--* LCL_VAR int V25 loc22 u:2 (last use) $369 N002 ( 1, 1) [000288] ------------ \--* CNS_INT int 0 $40 ------------ BB37 [1AF..1C3) -> BB39 (always), preds={BB36} succs={BB39} ***** BB37 STMT00068 (IL 0x1AF...0x1C1) N013 ( 23, 15) [000320] -A------R--- * ASG int $36e N012 ( 3, 2) [000319] D------N---- +--* LCL_VAR int V37 tmp7 d:4 $36e N011 ( 19, 12) [000318] ------------ \--* EQ int $36e N009 ( 14, 10) [000315] ------------ +--* AND long $490 N001 ( 1, 1) [000305] ------------ | +--* LCL_VAR long V24 loc21 u:2 $450 N008 ( 12, 8) [000314] ------------ | \--* ADD long $48f N006 ( 10, 6) [000311] --------R--- | +--* LSH long $48e N005 ( 1, 1) [000307] ------------ | | +--* CNS_INT long 1 $103 N004 ( 5, 4) [000310] ------------ | | \--* AND int $36d N002 ( 3, 2) [000308] ------------ | | +--* LCL_VAR int V29 loc26 u:2 $36b N003 ( 1, 1) [000309] ------------ | | \--* CNS_INT int 63 $66 N007 ( 1, 1) [000313] ------------ | \--* CNS_INT long -1 $104 N010 ( 1, 1) [000317] ------------ \--* CNS_INT long 0 $100 ------------ BB38 [1C3..1C4), preds={BB36} succs={BB39} ***** BB38 STMT00065 (IL 0x1C3...0x1C3) N003 ( 5, 4) [000293] -A------R--- * ASG int $40 N002 ( 3, 2) [000292] D------N---- +--* LCL_VAR int V37 tmp7 d:3 $40 N001 ( 1, 1) [000291] ------------ \--* CNS_INT int 0 $40 ------------ BB39 [1C4..1D0), preds={BB37,BB38} succs={BB40} ***** BB39 STMT00116 (IL ???... ???) N005 ( 0, 0) [000868] -A------R--- * ASG int N004 ( 0, 0) [000866] D------N---- +--* LCL_VAR int V37 tmp7 d:2 N003 ( 0, 0) [000867] ------------ \--* PHI int N001 ( 0, 0) [000897] ------------ pred BB37 +--* PHI_ARG int V37 tmp7 u:4 $36e N002 ( 0, 0) [000896] ------------ pred BB38 \--* PHI_ARG int V37 tmp7 u:3 $40 ***** BB39 STMT00066 (IL ???...0x1C4) N004 ( 8, 7) [000297] -A------R--- * ASG int $36f N003 ( 3, 2) [000296] D------N---- +--* LCL_VAR int V25 loc22 d:4 $36f N002 ( 4, 4) [000826] ------------ \--* CAST int <- bool <- int $36f N001 ( 3, 2) [000295] ------------ \--* LCL_VAR int V37 tmp7 u:2 (last use) $251 ***** BB39 STMT00067 (IL 0x1C6...0x1CE) N007 ( 10, 6) [000304] -A------R--- * ASG long $491 N006 ( 1, 1) [000303] D------N---- +--* LCL_VAR long V24 loc21 d:4 $491 N005 ( 10, 6) [000302] ------------ \--* RSZ long $491 N001 ( 1, 1) [000298] ------------ +--* LCL_VAR long V24 loc21 u:2 (last use) $450 N004 ( 5, 4) [000301] ------------ \--* AND int $36d N002 ( 3, 2) [000299] ------------ +--* LCL_VAR int V29 loc26 u:2 (last use) $36b N003 ( 1, 1) [000300] ------------ \--* CNS_INT int 63 $66 ------------ BB40 [1D0..1E7) -> BB42 (cond), preds={BB35,BB39} succs={BB41,BB42} ***** BB40 STMT00115 (IL ???... ???) N005 ( 0, 0) [000865] -A------R--- * ASG bool N004 ( 0, 0) [000863] D------N---- +--* LCL_VAR bool V25 loc22 d:3 N003 ( 0, 0) [000864] ------------ \--* PHI bool N001 ( 0, 0) [000894] ------------ pred BB39 +--* PHI_ARG bool V25 loc22 u:4 $36f N002 ( 0, 0) [000889] ------------ pred BB35 \--* PHI_ARG bool V25 loc22 u:2 $369 ***** BB40 STMT00114 (IL ???... ???) N005 ( 0, 0) [000862] -A------R--- * ASG long N004 ( 0, 0) [000860] D------N---- +--* LCL_VAR long V24 loc21 d:3 N003 ( 0, 0) [000861] ------------ \--* PHI long N001 ( 0, 0) [000895] ------------ pred BB39 +--* PHI_ARG long V24 loc21 u:4 $491 N002 ( 0, 0) [000890] ------------ pred BB35 \--* PHI_ARG long V24 loc21 u:2 $450 ***** BB40 STMT00057 (IL ???... ???) N027 ( 53, 34) [000254] -ACXG---R--- * ASG long $493 N026 ( 3, 2) [000253] D------N---- +--* LCL_VAR long V27 loc24 d:2 $493 N025 ( 49, 31) [000252] -ACXG------- \--* ADD long $493 N023 ( 47, 29) [000250] -ACXG------- +--* LSH long $492 N019 ( 38, 24) [000243] -ACXG------- | +--* CALL long System.Numerics.BigInteger.op_Explicit $454 N016 ( 18, 15) [000845] -A--G-----L- arg0 SETUP | | +--* COMMA void $VN.Void N009 ( 10, 8) [000838] -A--G------- | | | +--* COMMA void $VN.Void N004 ( 3, 3) [000833] -A------R--- | | | | +--* ASG byref $426 N003 ( 1, 1) [000832] D------N---- | | | | | +--* LCL_VAR byref V90 tmp60 d:2 $426 N002 ( 3, 3) [000830] ------------ | | | | | \--* ADDR byref $426 N001 ( 3, 2) [000831] ----G--N---- | | | | | \--* LCL_VAR struct(AX) V76 tmp46 $3db N008 ( 7, 5) [000837] -A--G------- | | | | \--* ASG ref $VN.Void N006 ( 3, 2) [000835] *------N---- | | | | +--* IND ref $18b N005 ( 1, 1) [000834] ------------ | | | | | \--* LCL_VAR byref V90 tmp60 u:2 Zero Fseq[_bits] $426 N007 ( 3, 2) [000836] ----G--N---- | | | | \--* LCL_VAR ref (AX) V54 tmp24 $18b N015 ( 8, 7) [000844] -A--G------- | | | \--* ASG int $VN.Void N013 ( 4, 4) [000842] *------N---- | | | +--* IND int $252 N012 ( 2, 2) [000841] -------N---- | | | | \--* ADD byref $220 N010 ( 1, 1) [000839] ------------ | | | | +--* LCL_VAR byref V90 tmp60 u:2 (last use) $426 N011 ( 1, 1) [000840] ------------ | | | | \--* CNS_INT long 8 Fseq[_sign] $101 N014 ( 3, 2) [000843] ----G--N---- | | | \--* LCL_VAR int (AX) V55 tmp25 $252 N018 ( 3, 3) [000847] ------------ arg0 in rcx | | \--* ADDR byref $428 N017 ( 3, 2) [000846] -------N---- | | \--* LCL_VAR struct(AX) V76 tmp46 $3dc N022 ( 5, 4) [000249] ------------ | \--* AND int $370 N020 ( 3, 2) [000247] ------------ | +--* LCL_VAR int V20 loc17 u:2 (last use) $362 N021 ( 1, 1) [000248] ------------ | \--* CNS_INT int 63 $66 N024 ( 1, 1) [000251] ------------ \--* LCL_VAR long V24 loc21 u:3 (last use) $580 ***** BB40 STMT00058 (IL 0x1E2...0x1E5) N004 ( 5, 5) [000258] ------------ * JTRUE void N003 ( 3, 3) [000257] N------N---- \--* NE int $35a N001 ( 1, 1) [000255] ------------ +--* LCL_VAR int V13 loc10 u:2 $293 N002 ( 1, 1) [000256] ------------ \--* CNS_INT int 0 $40 ------------ BB41 [1E7..1EE) -> BB43 (always), preds={BB40} succs={BB43} ***** BB41 STMT00062 (IL 0x1E7...0x1EC) N006 ( 10, 8) [000280] -A------R--- * ASG int $372 N005 ( 3, 2) [000279] D------N---- +--* LCL_VAR int V36 tmp6 d:4 $372 N004 ( 6, 5) [000278] ------------ \--* ADD int $372 N002 ( 4, 3) [000276] ------------ +--* NEG int $2c2 N001 ( 3, 2) [000275] ------------ | \--* LCL_VAR int V22 loc19 u:2 (last use) $24c N003 ( 1, 1) [000277] ------------ \--* CNS_INT int -1 $43 ------------ BB42 [1EE..1F2), preds={BB40} succs={BB43} ***** BB42 STMT00059 (IL 0x1EE...0x1F1) N005 ( 7, 6) [000263] -A------R--- * ASG int $371 N004 ( 3, 2) [000262] D------N---- +--* LCL_VAR int V36 tmp6 d:3 $371 N003 ( 3, 3) [000261] ------------ \--* ADD int $371 N001 ( 1, 1) [000259] ------------ +--* LCL_VAR int V13 loc10 u:2 (last use) $293 N002 ( 1, 1) [000260] ------------ \--* CNS_INT int -2 $68 ------------ BB43 [1F2..202), preds={BB41,BB42} succs={BB44} ***** BB43 STMT00113 (IL ???... ???) N005 ( 0, 0) [000859] -A------R--- * ASG int N004 ( 0, 0) [000857] D------N---- +--* LCL_VAR int V36 tmp6 d:2 N003 ( 0, 0) [000858] ------------ \--* PHI int N001 ( 0, 0) [000893] ------------ pred BB41 +--* PHI_ARG int V36 tmp6 u:4 $372 N002 ( 0, 0) [000892] ------------ pred BB42 \--* PHI_ARG int V36 tmp6 u:3 $371 ***** BB43 STMT00061 (IL 0x1F4...0x201) N012 ( 28, 18) [000853] -ACXG---R--- * ASG int $2be N011 ( 1, 1) [000852] D------N---- +--* LCL_VAR int V51 tmp21 d:4 $2be N010 ( 28, 18) [000273] --CXG------- \--* CALL nullcheck int FloatingPointType.AssembleFloatingPointValue $2be N005 ( 1, 1) [000272] ------------ arg4 out+20 +--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N006 ( 1, 1) [000268] ------------ this in rcx +--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 N007 ( 3, 2) [000269] ------------ arg1 in rdx +--* LCL_VAR long V27 loc24 u:2 (last use) $493 N008 ( 3, 2) [000270] ------------ arg2 in r8 +--* LCL_VAR int V36 tmp6 u:2 (last use) $253 N009 ( 3, 2) [000271] ------------ arg3 in r9 \--* LCL_VAR int V25 loc22 u:3 (last use) $540 ------------ BB44 [???..???) (return), preds={BB16,BB30,BB43} succs={} ***** BB44 STMT00112 (IL ???... ???) N006 ( 0, 0) [000856] -A------R--- * ASG int N005 ( 0, 0) [000854] D------N---- +--* LCL_VAR int V51 tmp21 d:2 N004 ( 0, 0) [000855] ------------ \--* PHI int N001 ( 0, 0) [000901] ------------ pred BB30 +--* PHI_ARG int V51 tmp21 u:5 $5c2 N002 ( 0, 0) [000891] ------------ pred BB43 +--* PHI_ARG int V51 tmp21 u:4 $2be N003 ( 0, 0) [000887] ------------ pred BB16 \--* PHI_ARG int V51 tmp21 u:3 $5c7 ***** BB44 STMT00109 (IL ???... ???) N002 ( 2, 2) [000523] ------------ * RETURN int $5c9 N001 ( 1, 1) [000522] -------N---- \--* LCL_VAR int V51 tmp21 u:2 (last use) $254 ------------------------------------------------------------------------------------------------------------------- GenTreeNode creates assertion: N002 ( 3, 2) [000532] n----------- * IND ref In BB01 New Global Constant Assertion: (128, 0) ($80,$0) Value_Number {InitVal($40)} is not 0 index=#01, mask=0000000000000001 GenTreeNode creates assertion: N002 ( 3, 3) [000003] ---XG------- * ARR_LENGTH int In BB02 New Global Constant Assertion: (448, 0) ($1c0,$0) V52.02 != null index=#02, mask=0000000000000002 GenTreeNode creates assertion: N005 ( 7, 7) [000006] ---XG------- * JTRUE void In BB02 New Global ArrBnds Assertion: (704, 64) ($2c0,$40) [idx: {IntCns 0};len: {ARR_LENGTH($1c0)}] is not index=#03, mask=0000000000000004 GenTreeNode creates assertion: N003 ( 21, 10) [000401] --CXG------- * CALLV ind long FloatingPointType.get_Zero $459 In BB03 New Global Constant Assertion: (192, 0) ($c0,$0) V01.01 != null index=#04, mask=0000000000000008 GenTreeNode creates assertion: N005 ( 3, 2) [000402] *--X---N---- * IND long $459 In BB03 New Global Constant Assertion: (129, 0) ($81,$0) Value_Number {InitVal($42)} is not 0 index=#05, mask=0000000000000010 GenTreeNode creates assertion: N004 ( 5, 5) [000414] ------------ * JTRUE void In BB04 New Global Constant Assertion: (841, 64) ($349,$40) Const_Loop_Bnd {LE($280, $40)} is not {IntCns 0} index=#06, mask=0000000000000020 GenTreeNode creates assertion: N004 ( 5, 5) [000414] ------------ * JTRUE void In BB04 New Global Constant Assertion: (841, 64) ($349,$40) Const_Loop_Bnd {LE($280, $40)} is {IntCns 0} index=#07, mask=0000000000000040 GenTreeNode creates assertion: N010 ( 3, 2) [000551] *------N---- * IND ref In BB10 New Global Constant Assertion: (1025, 0) ($401,$0) Value_Number {401} is not 0 index=#08, mask=0000000000000080 GenTreeNode creates assertion: N004 ( 7, 6) [000068] ------------ * JTRUE void In BB10 New Global Constant Assertion: (846, 64) ($34e,$40) V05.02 == 0 index=#09, mask=0000000000000100 GenTreeNode creates assertion: N004 ( 7, 6) [000068] ------------ * JTRUE void In BB10 New Global Constant Assertion: (846, 64) ($34e,$40) V05.02 != 0 index=#10, mask=0000000000000200 GenTreeNode creates assertion: N006 ( 3, 2) [000581] *------N---- * IND ref $181 In BB14 New Global Constant Assertion: (1029, 0) ($405,$0) Value_Number {405} is not 0 index=#11, mask=0000000000000400 GenTreeNode creates assertion: N004 ( 5, 5) [000094] ------------ * JTRUE void In BB15 New Global Constant Assertion: (847, 64) ($34f,$40) V10.02 != 0 index=#12, mask=0000000000000800 GenTreeNode creates assertion: N004 ( 5, 5) [000094] ------------ * JTRUE void In BB15 New Global Constant Assertion: (847, 64) ($34f,$40) V10.02 == 0 index=#13, mask=0000000000001000 GenTreeNode creates assertion: N004 ( 5, 5) [000100] ----G------- * JTRUE void In BB17 New Global Constant Assertion: (854, 64) ($356,$40) Const_Loop_Bnd {LT($280, $40)} is not {IntCns 0} index=#14, mask=0000000000002000 GenTreeNode creates assertion: N004 ( 5, 5) [000100] ----G------- * JTRUE void In BB17 New Global Constant Assertion: (854, 64) ($356,$40) Const_Loop_Bnd {LT($280, $40)} is {IntCns 0} index=#15, mask=0000000000004000 GenTreeNode creates assertion: N004 ( 5, 5) [000116] ------------ * JTRUE void In BB20 New Global Constant Assertion: (659, 64) ($293,$40) V13.02 != 0 index=#16, mask=0000000000008000 GenTreeNode creates assertion: N004 ( 5, 5) [000116] ------------ * JTRUE void In BB20 New Global Constant Assertion: (659, 64) ($293,$40) V13.02 == 0 index=#17, mask=0000000000010000 GenTreeNode creates assertion: N010 ( 3, 2) [000611] *------N---- * IND ref In BB23 New Global Constant Assertion: (1033, 0) ($409,$0) Value_Number {409} is not 0 index=#18, mask=0000000000020000 GenTreeNode creates assertion: N008 ( 3, 2) [000640] ---X-------- * IND ref In BB23 New Global Constant Assertion: (466, 0) ($1d2,$0) Value_Number {1d2} is not null index=#19, mask=0000000000040000 GenTreeNode creates assertion: N006 ( 3, 2) [000667] *------N---- * IND ref $184 In BB23 New Global Constant Assertion: (1038, 0) ($40e,$0) Value_Number {40e} is not 0 index=#20, mask=0000000000080000 GenTreeNode creates assertion: N006 ( 3, 2) [000696] *------N---- * IND ref $185 In BB23 New Global Constant Assertion: (1041, 0) ($411,$0) Value_Number {411} is not 0 index=#21, mask=0000000000100000 GenTreeNode creates assertion: N004 ( 7, 6) [000172] ------------ * JTRUE void In BB26 New Global Constant Assertion: (584, 64) ($248,$40) V19.02 == 0 index=#22, mask=0000000000200000 GenTreeNode creates assertion: N004 ( 7, 6) [000172] ------------ * JTRUE void In BB26 New Global Constant Assertion: (584, 64) ($248,$40) V19.02 != 0 index=#23, mask=0000000000400000 GenTreeNode creates assertion: N010 ( 3, 2) [000740] *------N---- * IND ref $187 In BB32 New Global Constant Assertion: (1047, 0) ($417,$0) Value_Number {417} is not 0 index=#24, mask=0000000000800000 GenTreeNode creates assertion: N027 ( 52, 38) [000195] -ACXG------- * JTRUE void In BB32 New Global Constant Assertion: (871, 64) ($367,$40) Const_Loop_Bnd {LT($2ae, $40)} is not {IntCns 0} index=#25, mask=0000000001000000 GenTreeNode creates assertion: N027 ( 52, 38) [000195] -ACXG------- * JTRUE void In BB32 New Global Constant Assertion: (871, 64) ($367,$40) Const_Loop_Bnd {LT($2ae, $40)} is {IntCns 0} index=#26, mask=0000000002000000 GenTreeNode creates assertion: N010 ( 3, 2) [000766] *------N---- * IND ref $188 In BB35 New Global Constant Assertion: (1052, 0) ($41c,$0) Value_Number {41c} is not 0 index=#27, mask=0000000004000000 GenTreeNode creates assertion: N026 ( 3, 2) [000785] *------N---- * IND ref $189 In BB35 New Global Constant Assertion: (1054, 0) ($41e,$0) Value_Number {41e} is not 0 index=#28, mask=0000000008000000 GenTreeNode creates assertion: N006 ( 3, 2) [000812] *------N---- * IND ref $18a In BB35 New Global Constant Assertion: (1059, 0) ($423,$0) Value_Number {423} is not 0 index=#29, mask=0000000010000000 GenTreeNode creates assertion: N004 ( 7, 6) [000290] ------------ * JTRUE void In BB36 New Global Constant Assertion: (873, 64) ($369,$40) V25.02 == 0 index=#30, mask=0000000020000000 GenTreeNode creates assertion: N004 ( 7, 6) [000290] ------------ * JTRUE void In BB36 New Global Constant Assertion: (873, 64) ($369,$40) V25.02 != 0 index=#31, mask=0000000040000000 GenTreeNode creates assertion: N002 ( 4, 4) [000826] ------------ * CAST int <- bool <- int $36f In BB39 New Global Subrange Assertion: (593, 0) ($251,$0) V37.02 in [0..1] index=#32, mask=0000000080000000 GenTreeNode creates assertion: N006 ( 3, 2) [000835] *------N---- * IND ref $18b In BB40 New Global Constant Assertion: (1062, 0) ($426,$0) Value_Number {426} is not 0 index=#33, mask=0000000000000000 BB01 valueGen = 0000000000000001 BB02 valueGen = 0000000000000002 => BB04 valueGen = 0000000000000006, BB03 valueGen = 0000000000000018 BB04 valueGen = 0000000000000048 => BB06 valueGen = 0000000000000028, BB05 valueGen = 0000000000000000 BB06 valueGen = 0000000000000000 BB07 valueGen = 0000000000000002 => BB09 valueGen = 0000000000000002, BB08 valueGen = 0000000000000000 BB09 valueGen = 0000000000000000 BB10 valueGen = 0000000000000282 => BB14 valueGen = 0000000000000182, BB11 valueGen = 0000000000000008 => BB13 valueGen = 0000000000000008, BB12 valueGen = 0000000000000018 BB13 valueGen = 0000000000000000 BB14 valueGen = 0000000000000400 => BB16 valueGen = 0000000000000400, BB15 valueGen = 0000000000001000 => BB17 valueGen = 0000000000000800, BB16 valueGen = 0000000000000000 BB17 valueGen = 0000000000004000 => BB19 valueGen = 0000000000002000, BB18 valueGen = 0000000000000000 BB19 valueGen = 0000000000000000 BB20 valueGen = 0000000000010000 => BB23 valueGen = 0000000000008000, BB21 valueGen = 000000000000000A => BB23 valueGen = 000000000000000A, BB22 valueGen = 0000000000000018 BB23 valueGen = 00000000001E0000 => BB25 valueGen = 00000000001E0000, BB24 valueGen = 0000000000000000 BB25 valueGen = 0000000000000000 BB26 valueGen = 0000000000400000 => BB28 valueGen = 0000000000200000, BB27 valueGen = 0000000000000000 BB28 valueGen = 0000000000008000 => BB32 valueGen = 0000000000010000, BB29 valueGen = 0000000000000000 => BB31 valueGen = 0000000000000000, BB30 valueGen = 0000000000000000 BB31 valueGen = 0000000000000000 BB32 valueGen = 0000000002800000 => BB34 valueGen = 0000000001800000, BB33 valueGen = 0000000000000000 BB34 valueGen = 0000000000000000 BB35 valueGen = 000000001C000000 => BB40 valueGen = 000000001C000000, BB36 valueGen = 0000000040000000 => BB38 valueGen = 0000000020000000, BB37 valueGen = 0000000000000000 BB38 valueGen = 0000000000000000 BB39 valueGen = 0000000000000000 BB40 valueGen = 0000000000010000 => BB42 valueGen = 0000000000008000, BB41 valueGen = 0000000000000000 BB42 valueGen = 0000000000000000 BB43 valueGen = 0000000000000008 BB44 valueGen = 0000000000000000 AssertionPropCallback::StartMerge: BB01 in -> 0000000000000000 AssertionPropCallback::EndMerge : BB01 in -> 0000000000000000 AssertionPropCallback::Changed : BB01 before out -> 00000000FFFFFFFF; after out -> 0000000000000001; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 0000000000000000; AssertionPropCallback::StartMerge: BB02 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB02 in -> 00000000FFFFFFFF, predBlock BB01 out -> 0000000000000001 AssertionPropCallback::EndMerge : BB02 in -> 0000000000000001 AssertionPropCallback::Changed : BB02 before out -> 00000000FFFFFFFF; after out -> 0000000000000003; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 0000000000000007; AssertionPropCallback::StartMerge: BB03 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB03 in -> 00000000FFFFFFFF, predBlock BB02 out -> 0000000000000003 AssertionPropCallback::EndMerge : BB03 in -> 0000000000000003 AssertionPropCallback::Changed : BB03 before out -> 00000000FFFFFFFF; after out -> 000000000000001B; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 0000000000000003; AssertionPropCallback::StartMerge: BB04 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB04 in -> 00000000FFFFFFFF, predBlock BB02 out -> 0000000000000003 AssertionPropCallback::EndMerge : BB04 in -> 0000000000000007 AssertionPropCallback::Changed : BB04 before out -> 00000000FFFFFFFF; after out -> 000000000000004F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 000000000000002F; AssertionPropCallback::StartMerge: BB05 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB05 in -> 00000000FFFFFFFF, predBlock BB04 out -> 000000000000004F AssertionPropCallback::EndMerge : BB05 in -> 000000000000004F AssertionPropCallback::Changed : BB05 before out -> 00000000FFFFFFFF; after out -> 000000000000004F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 000000000000004F; AssertionPropCallback::StartMerge: BB06 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB06 in -> 00000000FFFFFFFF, predBlock BB04 out -> 000000000000004F AssertionPropCallback::EndMerge : BB06 in -> 000000000000002F AssertionPropCallback::Changed : BB06 before out -> 00000000FFFFFFFF; after out -> 000000000000002F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 000000000000002F; AssertionPropCallback::StartMerge: BB07 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB07 in -> 00000000FFFFFFFF, predBlock BB05 out -> 000000000000004F AssertionPropCallback::Merge : BB07 in -> 000000000000004F, predBlock BB06 out -> 000000000000002F AssertionPropCallback::EndMerge : BB07 in -> 000000000000000F AssertionPropCallback::Changed : BB07 before out -> 00000000FFFFFFFF; after out -> 000000000000000F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 000000000000000F; AssertionPropCallback::StartMerge: BB07 in -> 000000000000000F AssertionPropCallback::Merge : BB07 in -> 000000000000000F, predBlock BB05 out -> 000000000000004F AssertionPropCallback::Merge : BB07 in -> 000000000000000F, predBlock BB06 out -> 000000000000002F AssertionPropCallback::EndMerge : BB07 in -> 000000000000000F AssertionPropCallback::Unchanged : BB07 out -> 000000000000000F; jumpDest out -> 000000000000000F AssertionPropCallback::StartMerge: BB08 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB08 in -> 00000000FFFFFFFF, predBlock BB07 out -> 000000000000000F AssertionPropCallback::EndMerge : BB08 in -> 000000000000000F AssertionPropCallback::Changed : BB08 before out -> 00000000FFFFFFFF; after out -> 000000000000000F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 000000000000000F; AssertionPropCallback::StartMerge: BB09 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB09 in -> 00000000FFFFFFFF, predBlock BB07 out -> 000000000000000F AssertionPropCallback::EndMerge : BB09 in -> 000000000000000F AssertionPropCallback::Changed : BB09 before out -> 00000000FFFFFFFF; after out -> 000000000000000F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 000000000000000F; AssertionPropCallback::StartMerge: BB10 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB10 in -> 00000000FFFFFFFF, predBlock BB08 out -> 000000000000000F AssertionPropCallback::Merge : BB10 in -> 000000000000000F, predBlock BB09 out -> 000000000000000F AssertionPropCallback::EndMerge : BB10 in -> 000000000000000F AssertionPropCallback::Changed : BB10 before out -> 00000000FFFFFFFF; after out -> 000000000000028F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 000000000000018F; AssertionPropCallback::StartMerge: BB10 in -> 000000000000000F AssertionPropCallback::Merge : BB10 in -> 000000000000000F, predBlock BB08 out -> 000000000000000F AssertionPropCallback::Merge : BB10 in -> 000000000000000F, predBlock BB09 out -> 000000000000000F AssertionPropCallback::EndMerge : BB10 in -> 000000000000000F AssertionPropCallback::Unchanged : BB10 out -> 000000000000028F; jumpDest out -> 000000000000018F AssertionPropCallback::StartMerge: BB11 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB11 in -> 00000000FFFFFFFF, predBlock BB10 out -> 000000000000028F AssertionPropCallback::EndMerge : BB11 in -> 000000000000028F AssertionPropCallback::Changed : BB11 before out -> 00000000FFFFFFFF; after out -> 000000000000028F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 000000000000028F; AssertionPropCallback::StartMerge: BB14 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB14 in -> 00000000FFFFFFFF, predBlock BB10 out -> 000000000000028F AssertionPropCallback::Merge : BB14 in -> 000000000000018F, predBlock BB13 out -> 00000000FFFFFFFF AssertionPropCallback::EndMerge : BB14 in -> 000000000000018F AssertionPropCallback::Changed : BB14 before out -> 00000000FFFFFFFF; after out -> 000000000000058F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 000000000000058F; AssertionPropCallback::StartMerge: BB12 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB12 in -> 00000000FFFFFFFF, predBlock BB11 out -> 000000000000028F AssertionPropCallback::EndMerge : BB12 in -> 000000000000028F AssertionPropCallback::Changed : BB12 before out -> 00000000FFFFFFFF; after out -> 000000000000029F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 000000000000028F; AssertionPropCallback::StartMerge: BB13 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB13 in -> 00000000FFFFFFFF, predBlock BB11 out -> 000000000000028F AssertionPropCallback::EndMerge : BB13 in -> 000000000000028F AssertionPropCallback::Changed : BB13 before out -> 00000000FFFFFFFF; after out -> 000000000000028F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 000000000000028F; AssertionPropCallback::StartMerge: BB15 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB15 in -> 00000000FFFFFFFF, predBlock BB14 out -> 000000000000058F AssertionPropCallback::EndMerge : BB15 in -> 000000000000058F AssertionPropCallback::Changed : BB15 before out -> 00000000FFFFFFFF; after out -> 000000000000158F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 0000000000000D8F; AssertionPropCallback::StartMerge: BB16 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB16 in -> 00000000FFFFFFFF, predBlock BB14 out -> 000000000000058F AssertionPropCallback::Merge : BB16 in -> 000000000000058F, predBlock BB15 out -> 000000000000158F AssertionPropCallback::EndMerge : BB16 in -> 000000000000058F AssertionPropCallback::Changed : BB16 before out -> 00000000FFFFFFFF; after out -> 000000000000058F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 000000000000058F; AssertionPropCallback::StartMerge: BB14 in -> 000000000000018F AssertionPropCallback::Merge : BB14 in -> 000000000000018F, predBlock BB10 out -> 000000000000028F AssertionPropCallback::Merge : BB14 in -> 000000000000018F, predBlock BB13 out -> 000000000000028F AssertionPropCallback::EndMerge : BB14 in -> 000000000000008F AssertionPropCallback::Changed : BB14 before out -> 000000000000058F; after out -> 000000000000048F; jumpDest before out -> 000000000000058F; jumpDest after out -> 000000000000048F; AssertionPropCallback::StartMerge: BB16 in -> 000000000000058F AssertionPropCallback::Merge : BB16 in -> 000000000000058F, predBlock BB14 out -> 000000000000048F AssertionPropCallback::Merge : BB16 in -> 000000000000048F, predBlock BB15 out -> 000000000000158F AssertionPropCallback::EndMerge : BB16 in -> 000000000000048F AssertionPropCallback::Changed : BB16 before out -> 000000000000058F; after out -> 000000000000048F; jumpDest before out -> 000000000000058F; jumpDest after out -> 000000000000048F; AssertionPropCallback::StartMerge: BB17 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB17 in -> 00000000FFFFFFFF, predBlock BB15 out -> 000000000000158F AssertionPropCallback::EndMerge : BB17 in -> 0000000000000D8F AssertionPropCallback::Changed : BB17 before out -> 00000000FFFFFFFF; after out -> 0000000000004D8F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 0000000000002D8F; AssertionPropCallback::StartMerge: BB44 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB44 in -> 00000000FFFFFFFF, predBlock BB16 out -> 000000000000048F AssertionPropCallback::Merge : BB44 in -> 000000000000048F, predBlock BB30 out -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB44 in -> 000000000000048F, predBlock BB43 out -> 00000000FFFFFFFF AssertionPropCallback::EndMerge : BB44 in -> 000000000000048F AssertionPropCallback::Changed : BB44 before out -> 00000000FFFFFFFF; after out -> 000000000000048F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 000000000000048F; AssertionPropCallback::StartMerge: BB15 in -> 000000000000058F AssertionPropCallback::Merge : BB15 in -> 000000000000058F, predBlock BB14 out -> 000000000000048F AssertionPropCallback::EndMerge : BB15 in -> 000000000000048F AssertionPropCallback::Changed : BB15 before out -> 000000000000158F; after out -> 000000000000148F; jumpDest before out -> 0000000000000D8F; jumpDest after out -> 0000000000000C8F; AssertionPropCallback::StartMerge: BB16 in -> 000000000000048F AssertionPropCallback::Merge : BB16 in -> 000000000000048F, predBlock BB14 out -> 000000000000048F AssertionPropCallback::Merge : BB16 in -> 000000000000048F, predBlock BB15 out -> 000000000000148F AssertionPropCallback::EndMerge : BB16 in -> 000000000000048F AssertionPropCallback::Unchanged : BB16 out -> 000000000000048F; jumpDest out -> 000000000000048F AssertionPropCallback::StartMerge: BB44 in -> 000000000000048F AssertionPropCallback::Merge : BB44 in -> 000000000000048F, predBlock BB16 out -> 000000000000048F AssertionPropCallback::Merge : BB44 in -> 000000000000048F, predBlock BB30 out -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB44 in -> 000000000000048F, predBlock BB43 out -> 00000000FFFFFFFF AssertionPropCallback::EndMerge : BB44 in -> 000000000000048F AssertionPropCallback::Unchanged : BB44 out -> 000000000000048F; jumpDest out -> 000000000000048F AssertionPropCallback::StartMerge: BB18 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB18 in -> 00000000FFFFFFFF, predBlock BB17 out -> 0000000000004D8F AssertionPropCallback::EndMerge : BB18 in -> 0000000000004D8F AssertionPropCallback::Changed : BB18 before out -> 00000000FFFFFFFF; after out -> 0000000000004D8F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 0000000000004D8F; AssertionPropCallback::StartMerge: BB19 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB19 in -> 00000000FFFFFFFF, predBlock BB17 out -> 0000000000004D8F AssertionPropCallback::EndMerge : BB19 in -> 0000000000002D8F AssertionPropCallback::Changed : BB19 before out -> 00000000FFFFFFFF; after out -> 0000000000002D8F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 0000000000002D8F; AssertionPropCallback::StartMerge: BB16 in -> 000000000000048F AssertionPropCallback::Merge : BB16 in -> 000000000000048F, predBlock BB14 out -> 000000000000048F AssertionPropCallback::Merge : BB16 in -> 000000000000048F, predBlock BB15 out -> 000000000000148F AssertionPropCallback::EndMerge : BB16 in -> 000000000000048F AssertionPropCallback::Unchanged : BB16 out -> 000000000000048F; jumpDest out -> 000000000000048F AssertionPropCallback::StartMerge: BB17 in -> 0000000000000D8F AssertionPropCallback::Merge : BB17 in -> 0000000000000D8F, predBlock BB15 out -> 000000000000148F AssertionPropCallback::EndMerge : BB17 in -> 0000000000000C8F AssertionPropCallback::Changed : BB17 before out -> 0000000000004D8F; after out -> 0000000000004C8F; jumpDest before out -> 0000000000002D8F; jumpDest after out -> 0000000000002C8F; AssertionPropCallback::StartMerge: BB20 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB20 in -> 00000000FFFFFFFF, predBlock BB18 out -> 0000000000004D8F AssertionPropCallback::Merge : BB20 in -> 0000000000004D8F, predBlock BB19 out -> 0000000000002D8F AssertionPropCallback::EndMerge : BB20 in -> 0000000000000D8F AssertionPropCallback::Changed : BB20 before out -> 00000000FFFFFFFF; after out -> 0000000000010D8F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 0000000000008D8F; AssertionPropCallback::StartMerge: BB20 in -> 0000000000000D8F AssertionPropCallback::Merge : BB20 in -> 0000000000000D8F, predBlock BB18 out -> 0000000000004D8F AssertionPropCallback::Merge : BB20 in -> 0000000000000D8F, predBlock BB19 out -> 0000000000002D8F AssertionPropCallback::EndMerge : BB20 in -> 0000000000000D8F AssertionPropCallback::Unchanged : BB20 out -> 0000000000010D8F; jumpDest out -> 0000000000008D8F AssertionPropCallback::StartMerge: BB18 in -> 0000000000004D8F AssertionPropCallback::Merge : BB18 in -> 0000000000004D8F, predBlock BB17 out -> 0000000000004C8F AssertionPropCallback::EndMerge : BB18 in -> 0000000000004C8F AssertionPropCallback::Changed : BB18 before out -> 0000000000004D8F; after out -> 0000000000004C8F; jumpDest before out -> 0000000000004D8F; jumpDest after out -> 0000000000004C8F; AssertionPropCallback::StartMerge: BB19 in -> 0000000000002D8F AssertionPropCallback::Merge : BB19 in -> 0000000000002D8F, predBlock BB17 out -> 0000000000004C8F AssertionPropCallback::EndMerge : BB19 in -> 0000000000002C8F AssertionPropCallback::Changed : BB19 before out -> 0000000000002D8F; after out -> 0000000000002C8F; jumpDest before out -> 0000000000002D8F; jumpDest after out -> 0000000000002C8F; AssertionPropCallback::StartMerge: BB21 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB21 in -> 00000000FFFFFFFF, predBlock BB20 out -> 0000000000010D8F AssertionPropCallback::EndMerge : BB21 in -> 0000000000010D8F AssertionPropCallback::Changed : BB21 before out -> 00000000FFFFFFFF; after out -> 0000000000010D8F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 0000000000010D8F; AssertionPropCallback::StartMerge: BB23 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB23 in -> 00000000FFFFFFFF, predBlock BB20 out -> 0000000000010D8F AssertionPropCallback::Merge : BB23 in -> 0000000000008D8F, predBlock BB21 out -> 0000000000010D8F AssertionPropCallback::EndMerge : BB23 in -> 0000000000000D8F AssertionPropCallback::Changed : BB23 before out -> 00000000FFFFFFFF; after out -> 00000000001E0D8F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 00000000001E0D8F; AssertionPropCallback::StartMerge: BB20 in -> 0000000000000D8F AssertionPropCallback::Merge : BB20 in -> 0000000000000D8F, predBlock BB18 out -> 0000000000004C8F AssertionPropCallback::Merge : BB20 in -> 0000000000000C8F, predBlock BB19 out -> 0000000000002C8F AssertionPropCallback::EndMerge : BB20 in -> 0000000000000C8F AssertionPropCallback::Changed : BB20 before out -> 0000000000010D8F; after out -> 0000000000010C8F; jumpDest before out -> 0000000000008D8F; jumpDest after out -> 0000000000008C8F; AssertionPropCallback::StartMerge: BB20 in -> 0000000000000C8F AssertionPropCallback::Merge : BB20 in -> 0000000000000C8F, predBlock BB18 out -> 0000000000004C8F AssertionPropCallback::Merge : BB20 in -> 0000000000000C8F, predBlock BB19 out -> 0000000000002C8F AssertionPropCallback::EndMerge : BB20 in -> 0000000000000C8F AssertionPropCallback::Unchanged : BB20 out -> 0000000000010C8F; jumpDest out -> 0000000000008C8F AssertionPropCallback::StartMerge: BB22 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB22 in -> 00000000FFFFFFFF, predBlock BB21 out -> 0000000000010D8F AssertionPropCallback::EndMerge : BB22 in -> 0000000000010D8F AssertionPropCallback::Changed : BB22 before out -> 00000000FFFFFFFF; after out -> 0000000000010D9F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 0000000000010D8F; AssertionPropCallback::StartMerge: BB23 in -> 0000000000000D8F AssertionPropCallback::Merge : BB23 in -> 0000000000000D8F, predBlock BB20 out -> 0000000000010C8F AssertionPropCallback::Merge : BB23 in -> 0000000000000C8F, predBlock BB21 out -> 0000000000010D8F AssertionPropCallback::EndMerge : BB23 in -> 0000000000000C8F AssertionPropCallback::Changed : BB23 before out -> 00000000001E0D8F; after out -> 00000000001E0C8F; jumpDest before out -> 00000000001E0D8F; jumpDest after out -> 00000000001E0C8F; AssertionPropCallback::StartMerge: BB24 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB24 in -> 00000000FFFFFFFF, predBlock BB23 out -> 00000000001E0C8F AssertionPropCallback::EndMerge : BB24 in -> 00000000001E0C8F AssertionPropCallback::Changed : BB24 before out -> 00000000FFFFFFFF; after out -> 00000000001E0C8F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 00000000001E0C8F; AssertionPropCallback::StartMerge: BB25 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB25 in -> 00000000FFFFFFFF, predBlock BB23 out -> 00000000001E0C8F AssertionPropCallback::EndMerge : BB25 in -> 00000000001E0C8F AssertionPropCallback::Changed : BB25 before out -> 00000000FFFFFFFF; after out -> 00000000001E0C8F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 00000000001E0C8F; AssertionPropCallback::StartMerge: BB21 in -> 0000000000010D8F AssertionPropCallback::Merge : BB21 in -> 0000000000010D8F, predBlock BB20 out -> 0000000000010C8F AssertionPropCallback::EndMerge : BB21 in -> 0000000000010C8F AssertionPropCallback::Changed : BB21 before out -> 0000000000010D8F; after out -> 0000000000010C8F; jumpDest before out -> 0000000000010D8F; jumpDest after out -> 0000000000010C8F; AssertionPropCallback::StartMerge: BB23 in -> 0000000000000C8F AssertionPropCallback::Merge : BB23 in -> 0000000000000C8F, predBlock BB20 out -> 0000000000010C8F AssertionPropCallback::Merge : BB23 in -> 0000000000000C8F, predBlock BB21 out -> 0000000000010C8F AssertionPropCallback::EndMerge : BB23 in -> 0000000000000C8F AssertionPropCallback::Unchanged : BB23 out -> 00000000001E0C8F; jumpDest out -> 00000000001E0C8F AssertionPropCallback::StartMerge: BB24 in -> 00000000001E0C8F AssertionPropCallback::Merge : BB24 in -> 00000000001E0C8F, predBlock BB23 out -> 00000000001E0C8F AssertionPropCallback::EndMerge : BB24 in -> 00000000001E0C8F AssertionPropCallback::Unchanged : BB24 out -> 00000000001E0C8F; jumpDest out -> 00000000001E0C8F AssertionPropCallback::StartMerge: BB25 in -> 00000000001E0C8F AssertionPropCallback::Merge : BB25 in -> 00000000001E0C8F, predBlock BB23 out -> 00000000001E0C8F AssertionPropCallback::EndMerge : BB25 in -> 00000000001E0C8F AssertionPropCallback::Unchanged : BB25 out -> 00000000001E0C8F; jumpDest out -> 00000000001E0C8F AssertionPropCallback::StartMerge: BB26 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB26 in -> 00000000FFFFFFFF, predBlock BB24 out -> 00000000001E0C8F AssertionPropCallback::Merge : BB26 in -> 00000000001E0C8F, predBlock BB25 out -> 00000000001E0C8F AssertionPropCallback::EndMerge : BB26 in -> 00000000001E0C8F AssertionPropCallback::Changed : BB26 before out -> 00000000FFFFFFFF; after out -> 00000000005E0C8F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 00000000003E0C8F; AssertionPropCallback::StartMerge: BB26 in -> 00000000001E0C8F AssertionPropCallback::Merge : BB26 in -> 00000000001E0C8F, predBlock BB24 out -> 00000000001E0C8F AssertionPropCallback::Merge : BB26 in -> 00000000001E0C8F, predBlock BB25 out -> 00000000001E0C8F AssertionPropCallback::EndMerge : BB26 in -> 00000000001E0C8F AssertionPropCallback::Unchanged : BB26 out -> 00000000005E0C8F; jumpDest out -> 00000000003E0C8F AssertionPropCallback::StartMerge: BB22 in -> 0000000000010D8F AssertionPropCallback::Merge : BB22 in -> 0000000000010D8F, predBlock BB21 out -> 0000000000010C8F AssertionPropCallback::EndMerge : BB22 in -> 0000000000010C8F AssertionPropCallback::Changed : BB22 before out -> 0000000000010D9F; after out -> 0000000000010C9F; jumpDest before out -> 0000000000010D8F; jumpDest after out -> 0000000000010C8F; AssertionPropCallback::StartMerge: BB23 in -> 0000000000000C8F AssertionPropCallback::Merge : BB23 in -> 0000000000000C8F, predBlock BB20 out -> 0000000000010C8F AssertionPropCallback::Merge : BB23 in -> 0000000000000C8F, predBlock BB21 out -> 0000000000010C8F AssertionPropCallback::EndMerge : BB23 in -> 0000000000000C8F AssertionPropCallback::Unchanged : BB23 out -> 00000000001E0C8F; jumpDest out -> 00000000001E0C8F AssertionPropCallback::StartMerge: BB27 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB27 in -> 00000000FFFFFFFF, predBlock BB26 out -> 00000000005E0C8F AssertionPropCallback::EndMerge : BB27 in -> 00000000005E0C8F AssertionPropCallback::Changed : BB27 before out -> 00000000FFFFFFFF; after out -> 00000000005E0C8F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 00000000005E0C8F; AssertionPropCallback::StartMerge: BB28 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB28 in -> 00000000FFFFFFFF, predBlock BB26 out -> 00000000005E0C8F AssertionPropCallback::Merge : BB28 in -> 00000000003E0C8F, predBlock BB27 out -> 00000000005E0C8F AssertionPropCallback::EndMerge : BB28 in -> 00000000001E0C8F AssertionPropCallback::Changed : BB28 before out -> 00000000FFFFFFFF; after out -> 00000000001E8C8F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 00000000001F0C8F; AssertionPropCallback::StartMerge: BB28 in -> 00000000001E0C8F AssertionPropCallback::Merge : BB28 in -> 00000000001E0C8F, predBlock BB26 out -> 00000000005E0C8F AssertionPropCallback::Merge : BB28 in -> 00000000001E0C8F, predBlock BB27 out -> 00000000005E0C8F AssertionPropCallback::EndMerge : BB28 in -> 00000000001E0C8F AssertionPropCallback::Unchanged : BB28 out -> 00000000001E8C8F; jumpDest out -> 00000000001F0C8F AssertionPropCallback::StartMerge: BB29 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB29 in -> 00000000FFFFFFFF, predBlock BB28 out -> 00000000001E8C8F AssertionPropCallback::EndMerge : BB29 in -> 00000000001E8C8F AssertionPropCallback::Changed : BB29 before out -> 00000000FFFFFFFF; after out -> 00000000001E8C8F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 00000000001E8C8F; AssertionPropCallback::StartMerge: BB32 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB32 in -> 00000000FFFFFFFF, predBlock BB28 out -> 00000000001E8C8F AssertionPropCallback::Merge : BB32 in -> 00000000001F0C8F, predBlock BB31 out -> 00000000FFFFFFFF AssertionPropCallback::EndMerge : BB32 in -> 00000000001F0C8F AssertionPropCallback::Changed : BB32 before out -> 00000000FFFFFFFF; after out -> 00000000029F0C8F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 00000000019F0C8F; AssertionPropCallback::StartMerge: BB30 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB30 in -> 00000000FFFFFFFF, predBlock BB29 out -> 00000000001E8C8F AssertionPropCallback::EndMerge : BB30 in -> 00000000001E8C8F AssertionPropCallback::Changed : BB30 before out -> 00000000FFFFFFFF; after out -> 00000000001E8C8F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 00000000001E8C8F; AssertionPropCallback::StartMerge: BB31 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB31 in -> 00000000FFFFFFFF, predBlock BB29 out -> 00000000001E8C8F AssertionPropCallback::EndMerge : BB31 in -> 00000000001E8C8F AssertionPropCallback::Changed : BB31 before out -> 00000000FFFFFFFF; after out -> 00000000001E8C8F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 00000000001E8C8F; AssertionPropCallback::StartMerge: BB33 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB33 in -> 00000000FFFFFFFF, predBlock BB32 out -> 00000000029F0C8F AssertionPropCallback::EndMerge : BB33 in -> 00000000029F0C8F AssertionPropCallback::Changed : BB33 before out -> 00000000FFFFFFFF; after out -> 00000000029F0C8F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 00000000029F0C8F; AssertionPropCallback::StartMerge: BB34 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB34 in -> 00000000FFFFFFFF, predBlock BB32 out -> 00000000029F0C8F AssertionPropCallback::EndMerge : BB34 in -> 00000000019F0C8F AssertionPropCallback::Changed : BB34 before out -> 00000000FFFFFFFF; after out -> 00000000019F0C8F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 00000000019F0C8F; AssertionPropCallback::StartMerge: BB44 in -> 000000000000048F AssertionPropCallback::Merge : BB44 in -> 000000000000048F, predBlock BB16 out -> 000000000000048F AssertionPropCallback::Merge : BB44 in -> 000000000000048F, predBlock BB30 out -> 00000000001E8C8F AssertionPropCallback::Merge : BB44 in -> 000000000000048F, predBlock BB43 out -> 00000000FFFFFFFF AssertionPropCallback::EndMerge : BB44 in -> 000000000000048F AssertionPropCallback::Unchanged : BB44 out -> 000000000000048F; jumpDest out -> 000000000000048F AssertionPropCallback::StartMerge: BB32 in -> 00000000001F0C8F AssertionPropCallback::Merge : BB32 in -> 00000000001F0C8F, predBlock BB28 out -> 00000000001E8C8F AssertionPropCallback::Merge : BB32 in -> 00000000001F0C8F, predBlock BB31 out -> 00000000001E8C8F AssertionPropCallback::EndMerge : BB32 in -> 00000000001E0C8F AssertionPropCallback::Changed : BB32 before out -> 00000000029F0C8F; after out -> 00000000029E0C8F; jumpDest before out -> 00000000019F0C8F; jumpDest after out -> 00000000019E0C8F; AssertionPropCallback::StartMerge: BB35 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB35 in -> 00000000FFFFFFFF, predBlock BB33 out -> 00000000029F0C8F AssertionPropCallback::Merge : BB35 in -> 00000000029F0C8F, predBlock BB34 out -> 00000000019F0C8F AssertionPropCallback::EndMerge : BB35 in -> 00000000009F0C8F AssertionPropCallback::Changed : BB35 before out -> 00000000FFFFFFFF; after out -> 000000001C9F0C8F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 000000001C9F0C8F; AssertionPropCallback::StartMerge: BB35 in -> 00000000009F0C8F AssertionPropCallback::Merge : BB35 in -> 00000000009F0C8F, predBlock BB33 out -> 00000000029F0C8F AssertionPropCallback::Merge : BB35 in -> 00000000009F0C8F, predBlock BB34 out -> 00000000019F0C8F AssertionPropCallback::EndMerge : BB35 in -> 00000000009F0C8F AssertionPropCallback::Unchanged : BB35 out -> 000000001C9F0C8F; jumpDest out -> 000000001C9F0C8F AssertionPropCallback::StartMerge: BB33 in -> 00000000029F0C8F AssertionPropCallback::Merge : BB33 in -> 00000000029F0C8F, predBlock BB32 out -> 00000000029E0C8F AssertionPropCallback::EndMerge : BB33 in -> 00000000029E0C8F AssertionPropCallback::Changed : BB33 before out -> 00000000029F0C8F; after out -> 00000000029E0C8F; jumpDest before out -> 00000000029F0C8F; jumpDest after out -> 00000000029E0C8F; AssertionPropCallback::StartMerge: BB34 in -> 00000000019F0C8F AssertionPropCallback::Merge : BB34 in -> 00000000019F0C8F, predBlock BB32 out -> 00000000029E0C8F AssertionPropCallback::EndMerge : BB34 in -> 00000000019E0C8F AssertionPropCallback::Changed : BB34 before out -> 00000000019F0C8F; after out -> 00000000019E0C8F; jumpDest before out -> 00000000019F0C8F; jumpDest after out -> 00000000019E0C8F; AssertionPropCallback::StartMerge: BB36 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB36 in -> 00000000FFFFFFFF, predBlock BB35 out -> 000000001C9F0C8F AssertionPropCallback::EndMerge : BB36 in -> 000000001C9F0C8F AssertionPropCallback::Changed : BB36 before out -> 00000000FFFFFFFF; after out -> 000000005C9F0C8F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 000000003C9F0C8F; AssertionPropCallback::StartMerge: BB40 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB40 in -> 00000000FFFFFFFF, predBlock BB35 out -> 000000001C9F0C8F AssertionPropCallback::Merge : BB40 in -> 000000001C9F0C8F, predBlock BB39 out -> 00000000FFFFFFFF AssertionPropCallback::EndMerge : BB40 in -> 000000001C9F0C8F AssertionPropCallback::Changed : BB40 before out -> 00000000FFFFFFFF; after out -> 000000001C9F0C8F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 000000001C9F8C8F; AssertionPropCallback::StartMerge: BB35 in -> 00000000009F0C8F AssertionPropCallback::Merge : BB35 in -> 00000000009F0C8F, predBlock BB33 out -> 00000000029E0C8F AssertionPropCallback::Merge : BB35 in -> 00000000009E0C8F, predBlock BB34 out -> 00000000019E0C8F AssertionPropCallback::EndMerge : BB35 in -> 00000000009E0C8F AssertionPropCallback::Changed : BB35 before out -> 000000001C9F0C8F; after out -> 000000001C9E0C8F; jumpDest before out -> 000000001C9F0C8F; jumpDest after out -> 000000001C9E0C8F; AssertionPropCallback::StartMerge: BB35 in -> 00000000009E0C8F AssertionPropCallback::Merge : BB35 in -> 00000000009E0C8F, predBlock BB33 out -> 00000000029E0C8F AssertionPropCallback::Merge : BB35 in -> 00000000009E0C8F, predBlock BB34 out -> 00000000019E0C8F AssertionPropCallback::EndMerge : BB35 in -> 00000000009E0C8F AssertionPropCallback::Unchanged : BB35 out -> 000000001C9E0C8F; jumpDest out -> 000000001C9E0C8F AssertionPropCallback::StartMerge: BB37 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB37 in -> 00000000FFFFFFFF, predBlock BB36 out -> 000000005C9F0C8F AssertionPropCallback::EndMerge : BB37 in -> 000000005C9F0C8F AssertionPropCallback::Changed : BB37 before out -> 00000000FFFFFFFF; after out -> 000000005C9F0C8F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 000000005C9F0C8F; AssertionPropCallback::StartMerge: BB38 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB38 in -> 00000000FFFFFFFF, predBlock BB36 out -> 000000005C9F0C8F AssertionPropCallback::EndMerge : BB38 in -> 000000003C9F0C8F AssertionPropCallback::Changed : BB38 before out -> 00000000FFFFFFFF; after out -> 000000003C9F0C8F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 000000003C9F0C8F; AssertionPropCallback::StartMerge: BB41 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB41 in -> 00000000FFFFFFFF, predBlock BB40 out -> 000000001C9F0C8F AssertionPropCallback::EndMerge : BB41 in -> 000000001C9F0C8F AssertionPropCallback::Changed : BB41 before out -> 00000000FFFFFFFF; after out -> 000000001C9F0C8F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 000000001C9F0C8F; AssertionPropCallback::StartMerge: BB42 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB42 in -> 00000000FFFFFFFF, predBlock BB40 out -> 000000001C9F0C8F AssertionPropCallback::EndMerge : BB42 in -> 000000001C9F8C8F AssertionPropCallback::Changed : BB42 before out -> 00000000FFFFFFFF; after out -> 000000001C9F8C8F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 000000001C9F8C8F; AssertionPropCallback::StartMerge: BB36 in -> 000000001C9F0C8F AssertionPropCallback::Merge : BB36 in -> 000000001C9F0C8F, predBlock BB35 out -> 000000001C9E0C8F AssertionPropCallback::EndMerge : BB36 in -> 000000001C9E0C8F AssertionPropCallback::Changed : BB36 before out -> 000000005C9F0C8F; after out -> 000000005C9E0C8F; jumpDest before out -> 000000003C9F0C8F; jumpDest after out -> 000000003C9E0C8F; AssertionPropCallback::StartMerge: BB40 in -> 000000001C9F0C8F AssertionPropCallback::Merge : BB40 in -> 000000001C9F0C8F, predBlock BB35 out -> 000000001C9E0C8F AssertionPropCallback::Merge : BB40 in -> 000000001C9E0C8F, predBlock BB39 out -> 00000000FFFFFFFF AssertionPropCallback::EndMerge : BB40 in -> 000000001C9E0C8F AssertionPropCallback::Changed : BB40 before out -> 000000001C9F0C8F; after out -> 000000001C9F0C8F; jumpDest before out -> 000000001C9F8C8F; jumpDest after out -> 000000001C9E8C8F; AssertionPropCallback::StartMerge: BB39 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB39 in -> 00000000FFFFFFFF, predBlock BB37 out -> 000000005C9F0C8F AssertionPropCallback::Merge : BB39 in -> 000000005C9F0C8F, predBlock BB38 out -> 000000003C9F0C8F AssertionPropCallback::EndMerge : BB39 in -> 000000001C9F0C8F AssertionPropCallback::Changed : BB39 before out -> 00000000FFFFFFFF; after out -> 000000001C9F0C8F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 000000001C9F0C8F; AssertionPropCallback::StartMerge: BB39 in -> 000000001C9F0C8F AssertionPropCallback::Merge : BB39 in -> 000000001C9F0C8F, predBlock BB37 out -> 000000005C9F0C8F AssertionPropCallback::Merge : BB39 in -> 000000001C9F0C8F, predBlock BB38 out -> 000000003C9F0C8F AssertionPropCallback::EndMerge : BB39 in -> 000000001C9F0C8F AssertionPropCallback::Unchanged : BB39 out -> 000000001C9F0C8F; jumpDest out -> 000000001C9F0C8F AssertionPropCallback::StartMerge: BB43 in -> 00000000FFFFFFFF AssertionPropCallback::Merge : BB43 in -> 00000000FFFFFFFF, predBlock BB41 out -> 000000001C9F0C8F AssertionPropCallback::Merge : BB43 in -> 000000001C9F0C8F, predBlock BB42 out -> 000000001C9F8C8F AssertionPropCallback::EndMerge : BB43 in -> 000000001C9F0C8F AssertionPropCallback::Changed : BB43 before out -> 00000000FFFFFFFF; after out -> 000000001C9F0C8F; jumpDest before out -> 00000000FFFFFFFF; jumpDest after out -> 000000001C9F0C8F; AssertionPropCallback::StartMerge: BB43 in -> 000000001C9F0C8F AssertionPropCallback::Merge : BB43 in -> 000000001C9F0C8F, predBlock BB41 out -> 000000001C9F0C8F AssertionPropCallback::Merge : BB43 in -> 000000001C9F0C8F, predBlock BB42 out -> 000000001C9F8C8F AssertionPropCallback::EndMerge : BB43 in -> 000000001C9F0C8F AssertionPropCallback::Unchanged : BB43 out -> 000000001C9F0C8F; jumpDest out -> 000000001C9F0C8F AssertionPropCallback::StartMerge: BB37 in -> 000000005C9F0C8F AssertionPropCallback::Merge : BB37 in -> 000000005C9F0C8F, predBlock BB36 out -> 000000005C9E0C8F AssertionPropCallback::EndMerge : BB37 in -> 000000005C9E0C8F AssertionPropCallback::Changed : BB37 before out -> 000000005C9F0C8F; after out -> 000000005C9E0C8F; jumpDest before out -> 000000005C9F0C8F; jumpDest after out -> 000000005C9E0C8F; AssertionPropCallback::StartMerge: BB38 in -> 000000003C9F0C8F AssertionPropCallback::Merge : BB38 in -> 000000003C9F0C8F, predBlock BB36 out -> 000000005C9E0C8F AssertionPropCallback::EndMerge : BB38 in -> 000000003C9E0C8F AssertionPropCallback::Changed : BB38 before out -> 000000003C9F0C8F; after out -> 000000003C9E0C8F; jumpDest before out -> 000000003C9F0C8F; jumpDest after out -> 000000003C9E0C8F; AssertionPropCallback::StartMerge: BB41 in -> 000000001C9F0C8F AssertionPropCallback::Merge : BB41 in -> 000000001C9F0C8F, predBlock BB40 out -> 000000001C9F0C8F AssertionPropCallback::EndMerge : BB41 in -> 000000001C9F0C8F AssertionPropCallback::Unchanged : BB41 out -> 000000001C9F0C8F; jumpDest out -> 000000001C9F0C8F AssertionPropCallback::StartMerge: BB42 in -> 000000001C9F8C8F AssertionPropCallback::Merge : BB42 in -> 000000001C9F8C8F, predBlock BB40 out -> 000000001C9F0C8F AssertionPropCallback::EndMerge : BB42 in -> 000000001C9E8C8F AssertionPropCallback::Changed : BB42 before out -> 000000001C9F8C8F; after out -> 000000001C9E8C8F; jumpDest before out -> 000000001C9F8C8F; jumpDest after out -> 000000001C9E8C8F; AssertionPropCallback::StartMerge: BB40 in -> 000000001C9E0C8F AssertionPropCallback::Merge : BB40 in -> 000000001C9E0C8F, predBlock BB35 out -> 000000001C9E0C8F AssertionPropCallback::Merge : BB40 in -> 000000001C9E0C8F, predBlock BB39 out -> 000000001C9F0C8F AssertionPropCallback::EndMerge : BB40 in -> 000000001C9E0C8F AssertionPropCallback::Unchanged : BB40 out -> 000000001C9F0C8F; jumpDest out -> 000000001C9E8C8F AssertionPropCallback::StartMerge: BB44 in -> 000000000000048F AssertionPropCallback::Merge : BB44 in -> 000000000000048F, predBlock BB16 out -> 000000000000048F AssertionPropCallback::Merge : BB44 in -> 000000000000048F, predBlock BB30 out -> 00000000001E8C8F AssertionPropCallback::Merge : BB44 in -> 000000000000048F, predBlock BB43 out -> 000000001C9F0C8F AssertionPropCallback::EndMerge : BB44 in -> 000000000000048F AssertionPropCallback::Unchanged : BB44 out -> 000000000000048F; jumpDest out -> 000000000000048F AssertionPropCallback::StartMerge: BB39 in -> 000000001C9F0C8F AssertionPropCallback::Merge : BB39 in -> 000000001C9F0C8F, predBlock BB37 out -> 000000005C9E0C8F AssertionPropCallback::Merge : BB39 in -> 000000001C9E0C8F, predBlock BB38 out -> 000000003C9E0C8F AssertionPropCallback::EndMerge : BB39 in -> 000000001C9E0C8F AssertionPropCallback::Changed : BB39 before out -> 000000001C9F0C8F; after out -> 000000001C9E0C8F; jumpDest before out -> 000000001C9F0C8F; jumpDest after out -> 000000001C9E0C8F; AssertionPropCallback::StartMerge: BB39 in -> 000000001C9E0C8F AssertionPropCallback::Merge : BB39 in -> 000000001C9E0C8F, predBlock BB37 out -> 000000005C9E0C8F AssertionPropCallback::Merge : BB39 in -> 000000001C9E0C8F, predBlock BB38 out -> 000000003C9E0C8F AssertionPropCallback::EndMerge : BB39 in -> 000000001C9E0C8F AssertionPropCallback::Unchanged : BB39 out -> 000000001C9E0C8F; jumpDest out -> 000000001C9E0C8F AssertionPropCallback::StartMerge: BB43 in -> 000000001C9F0C8F AssertionPropCallback::Merge : BB43 in -> 000000001C9F0C8F, predBlock BB41 out -> 000000001C9F0C8F AssertionPropCallback::Merge : BB43 in -> 000000001C9F0C8F, predBlock BB42 out -> 000000001C9E8C8F AssertionPropCallback::EndMerge : BB43 in -> 000000001C9E0C8F AssertionPropCallback::Changed : BB43 before out -> 000000001C9F0C8F; after out -> 000000001C9E0C8F; jumpDest before out -> 000000001C9F0C8F; jumpDest after out -> 000000001C9E0C8F; AssertionPropCallback::StartMerge: BB40 in -> 000000001C9E0C8F AssertionPropCallback::Merge : BB40 in -> 000000001C9E0C8F, predBlock BB35 out -> 000000001C9E0C8F AssertionPropCallback::Merge : BB40 in -> 000000001C9E0C8F, predBlock BB39 out -> 000000001C9E0C8F AssertionPropCallback::EndMerge : BB40 in -> 000000001C9E0C8F AssertionPropCallback::Unchanged : BB40 out -> 000000001C9F0C8F; jumpDest out -> 000000001C9E8C8F AssertionPropCallback::StartMerge: BB44 in -> 000000000000048F AssertionPropCallback::Merge : BB44 in -> 000000000000048F, predBlock BB16 out -> 000000000000048F AssertionPropCallback::Merge : BB44 in -> 000000000000048F, predBlock BB30 out -> 00000000001E8C8F AssertionPropCallback::Merge : BB44 in -> 000000000000048F, predBlock BB43 out -> 000000001C9E0C8F AssertionPropCallback::EndMerge : BB44 in -> 000000000000048F AssertionPropCallback::Unchanged : BB44 out -> 000000000000048F; jumpDest out -> 000000000000048F BB01 valueIn = 0000000000000000 valueOut = 0000000000000001 BB02 valueIn = 0000000000000001 valueOut = 0000000000000003 => BB04 valueOut= 0000000000000007 BB03 valueIn = 0000000000000003 valueOut = 000000000000001B BB04 valueIn = 0000000000000007 valueOut = 000000000000004F => BB06 valueOut= 000000000000002F BB05 valueIn = 000000000000004F valueOut = 000000000000004F BB06 valueIn = 000000000000002F valueOut = 000000000000002F BB07 valueIn = 000000000000000F valueOut = 000000000000000F => BB09 valueOut= 000000000000000F BB08 valueIn = 000000000000000F valueOut = 000000000000000F BB09 valueIn = 000000000000000F valueOut = 000000000000000F BB10 valueIn = 000000000000000F valueOut = 000000000000028F => BB14 valueOut= 000000000000018F BB11 valueIn = 000000000000028F valueOut = 000000000000028F => BB13 valueOut= 000000000000028F BB12 valueIn = 000000000000028F valueOut = 000000000000029F BB13 valueIn = 000000000000028F valueOut = 000000000000028F BB14 valueIn = 000000000000008F valueOut = 000000000000048F => BB16 valueOut= 000000000000048F BB15 valueIn = 000000000000048F valueOut = 000000000000148F => BB17 valueOut= 0000000000000C8F BB16 valueIn = 000000000000048F valueOut = 000000000000048F BB17 valueIn = 0000000000000C8F valueOut = 0000000000004C8F => BB19 valueOut= 0000000000002C8F BB18 valueIn = 0000000000004C8F valueOut = 0000000000004C8F BB19 valueIn = 0000000000002C8F valueOut = 0000000000002C8F BB20 valueIn = 0000000000000C8F valueOut = 0000000000010C8F => BB23 valueOut= 0000000000008C8F BB21 valueIn = 0000000000010C8F valueOut = 0000000000010C8F => BB23 valueOut= 0000000000010C8F BB22 valueIn = 0000000000010C8F valueOut = 0000000000010C9F BB23 valueIn = 0000000000000C8F valueOut = 00000000001E0C8F => BB25 valueOut= 00000000001E0C8F BB24 valueIn = 00000000001E0C8F valueOut = 00000000001E0C8F BB25 valueIn = 00000000001E0C8F valueOut = 00000000001E0C8F BB26 valueIn = 00000000001E0C8F valueOut = 00000000005E0C8F => BB28 valueOut= 00000000003E0C8F BB27 valueIn = 00000000005E0C8F valueOut = 00000000005E0C8F BB28 valueIn = 00000000001E0C8F valueOut = 00000000001E8C8F => BB32 valueOut= 00000000001F0C8F BB29 valueIn = 00000000001E8C8F valueOut = 00000000001E8C8F => BB31 valueOut= 00000000001E8C8F BB30 valueIn = 00000000001E8C8F valueOut = 00000000001E8C8F BB31 valueIn = 00000000001E8C8F valueOut = 00000000001E8C8F BB32 valueIn = 00000000001E0C8F valueOut = 00000000029E0C8F => BB34 valueOut= 00000000019E0C8F BB33 valueIn = 00000000029E0C8F valueOut = 00000000029E0C8F BB34 valueIn = 00000000019E0C8F valueOut = 00000000019E0C8F BB35 valueIn = 00000000009E0C8F valueOut = 000000001C9E0C8F => BB40 valueOut= 000000001C9E0C8F BB36 valueIn = 000000001C9E0C8F valueOut = 000000005C9E0C8F => BB38 valueOut= 000000003C9E0C8F BB37 valueIn = 000000005C9E0C8F valueOut = 000000005C9E0C8F BB38 valueIn = 000000003C9E0C8F valueOut = 000000003C9E0C8F BB39 valueIn = 000000001C9E0C8F valueOut = 000000001C9E0C8F BB40 valueIn = 000000001C9E0C8F valueOut = 000000001C9F0C8F => BB42 valueOut= 000000001C9E8C8F BB41 valueIn = 000000001C9F0C8F valueOut = 000000001C9F0C8F BB42 valueIn = 000000001C9E8C8F valueOut = 000000001C9E8C8F BB43 valueIn = 000000001C9E0C8F valueOut = 000000001C9E0C8F BB44 valueIn = 000000000000048F valueOut = 000000000000048F Propagating 0000000000000000 assertions for BB01, stmt STMT00111, tree [000531], tree -> 0 Propagating 0000000000000000 assertions for BB01, stmt STMT00111, tree [000532], tree -> 1 Propagating 0000000000000001 assertions for BB01, stmt STMT00111, tree [000530], tree -> 0 Propagating 0000000000000001 assertions for BB01, stmt STMT00111, tree [000533], tree -> 0 Propagating 0000000000000001 assertions for BB01, stmt STMT00111, tree [000535], tree -> 0 Propagating 0000000000000001 assertions for BB01, stmt STMT00111, tree [000536], tree -> 0 Propagating 0000000000000001 assertions for BB01, stmt STMT00111, tree [000537], tree -> 0 Propagating 0000000000000001 assertions for BB01, stmt STMT00111, tree [000538], tree -> 1 Propagating 0000000000000001 assertions for BB01, stmt STMT00111, tree [000534], tree -> 0 Propagating 0000000000000001 assertions for BB01, stmt STMT00111, tree [000539], tree -> 0 Propagating 0000000000000001 assertions for BB01, stmt STMT00111, tree [000540], tree -> 0 Propagating 0000000000000001 assertions for BB02, stmt STMT00000, tree [000002], tree -> 0 Propagating 0000000000000001 assertions for BB02, stmt STMT00000, tree [000003], tree -> 2 Propagating 0000000000000003 assertions for BB02, stmt STMT00000, tree [000004], tree -> 0 Propagating 0000000000000003 assertions for BB02, stmt STMT00000, tree [000005], tree -> 0 Propagating 0000000000000003 assertions for BB02, stmt STMT00000, tree [000006], tree -> 3 Propagating 0000000000000003 assertions for BB03, stmt STMT00087, tree [000541], tree -> 0 Propagating 0000000000000003 assertions for BB03, stmt STMT00087, tree [000400], tree -> 0 Propagating 0000000000000003 assertions for BB03, stmt STMT00087, tree [000401], tree -> 4 Propagating 000000000000000B assertions for BB03, stmt STMT00087, tree [000399], tree -> 0 Propagating 000000000000000B assertions for BB03, stmt STMT00087, tree [000402], tree -> 5 Propagating 000000000000001B assertions for BB03, stmt STMT00087, tree [000403], tree -> 0 Propagating 000000000000001B assertions for BB03, stmt STMT00107, tree [000404], tree -> 0 Propagating 000000000000001B assertions for BB03, stmt STMT00107, tree [000520], tree -> 0 Propagating 0000000000000007 assertions for BB04, stmt STMT00002, tree [000542], tree -> 0 Propagating 0000000000000007 assertions for BB04, stmt STMT00002, tree [000007], tree -> 0 Propagating 0000000000000007 assertions for BB04, stmt STMT00002, tree [000406], tree -> 4 Propagating 000000000000000F assertions for BB04, stmt STMT00002, tree [000407], tree -> 0 Propagating 000000000000000F assertions for BB04, stmt STMT00002, tree [000408], tree -> 0 Propagating 000000000000000F assertions for BB04, stmt STMT00002, tree [000409], tree -> 0 Propagating 000000000000000F assertions for BB04, stmt STMT00002, tree [000010], tree -> 0 Propagating 000000000000000F assertions for BB04, stmt STMT00002, tree [000011], tree -> 0 Propagating 000000000000000F assertions for BB04, stmt STMT00002, tree [000012], tree -> 0 Propagating 000000000000000F assertions for BB04, stmt STMT00002, tree [000013], tree -> 0 Propagating 000000000000000F assertions for BB04, stmt STMT00092, tree [000017], tree -> 0 Propagating 000000000000000F assertions for BB04, stmt STMT00092, tree [000423], tree -> 0 Propagating 000000000000000F assertions for BB04, stmt STMT00092, tree [000424], tree -> 0 Propagating 000000000000000F assertions for BB04, stmt STMT00089, tree [000412], tree -> 0 Propagating 000000000000000F assertions for BB04, stmt STMT00089, tree [000411], tree -> 0 Propagating 000000000000000F assertions for BB04, stmt STMT00089, tree [000413], tree -> 0 Propagating 000000000000000F assertions for BB04, stmt STMT00089, tree [000414], tree -> 6 Propagating 000000000000004F assertions for BB05, stmt STMT00091, tree [000419], tree -> 0 Propagating 000000000000004F assertions for BB05, stmt STMT00091, tree [000420], tree -> 0 Propagating 000000000000004F assertions for BB05, stmt STMT00091, tree [000421], tree -> 0 Propagating 000000000000002F assertions for BB06, stmt STMT00090, tree [000415], tree -> 0 Propagating 000000000000002F assertions for BB06, stmt STMT00090, tree [000416], tree -> 0 Propagating 000000000000002F assertions for BB06, stmt STMT00090, tree [000417], tree -> 0 Propagating 000000000000000F assertions for BB07, stmt STMT00004, tree [000422], tree -> 0 Propagating 000000000000000F assertions for BB07, stmt STMT00004, tree [000020], tree -> 0 Propagating 000000000000000F assertions for BB07, stmt STMT00004, tree [000021], tree -> 0 Propagating 000000000000000F assertions for BB07, stmt STMT00096, tree [000428], tree -> 0 Propagating 000000000000000F assertions for BB07, stmt STMT00096, tree [000429], tree -> 2 Propagating 000000000000000F assertions for BB07, stmt STMT00096, tree [000442], tree -> 0 Propagating 000000000000000F assertions for BB07, stmt STMT00096, tree [000443], tree -> 0 Propagating 000000000000000F assertions for BB07, stmt STMT00093, tree [000023], tree -> 0 Propagating 000000000000000F assertions for BB07, stmt STMT00093, tree [000431], tree -> 0 Propagating 000000000000000F assertions for BB07, stmt STMT00093, tree [000432], tree -> 0 Propagating 000000000000000F assertions for BB07, stmt STMT00093, tree [000433], tree -> 0 Propagating 000000000000000F assertions for BB08, stmt STMT00095, tree [000438], tree -> 0 Propagating 000000000000000F assertions for BB08, stmt STMT00095, tree [000439], tree -> 0 Propagating 000000000000000F assertions for BB08, stmt STMT00095, tree [000440], tree -> 0 Propagating 000000000000000F assertions for BB09, stmt STMT00094, tree [000434], tree -> 0 Propagating 000000000000000F assertions for BB09, stmt STMT00094, tree [000435], tree -> 0 Propagating 000000000000000F assertions for BB09, stmt STMT00094, tree [000436], tree -> 0 Propagating 000000000000000F assertions for BB10, stmt STMT00008, tree [000022], tree -> 0 Propagating 000000000000000F assertions for BB10, stmt STMT00008, tree [000032], tree -> 0 Propagating 000000000000000F assertions for BB10, stmt STMT00008, tree [000033], tree -> 0 Propagating 000000000000000F assertions for BB10, stmt STMT00008, tree [000034], tree -> 0 Propagating 000000000000000F assertions for BB10, stmt STMT00008, tree [000035], tree -> 0 Propagating 000000000000000F assertions for BB10, stmt STMT00011, tree [000042], tree -> 0 Propagating 000000000000000F assertions for BB10, stmt STMT00011, tree [000043], tree -> 0 Propagating 000000000000000F assertions for BB10, stmt STMT00011, tree [000044], tree -> 0 Propagating 000000000000000F assertions for BB10, stmt STMT00013, tree [000447], tree -> 0 Propagating 000000000000000F assertions for BB10, stmt STMT00013, tree [000448], tree -> 2 Propagating 000000000000000F assertions for BB10, stmt STMT00013, tree [000049], tree -> 0 Propagating 000000000000000F assertions for BB10, stmt STMT00013, tree [000050], tree -> 0 Propagating 000000000000000F assertions for BB10, stmt STMT00014, tree [000051], tree -> 0 Propagating 000000000000000F assertions for BB10, stmt STMT00014, tree [000052], tree -> 0 Propagating 000000000000000F assertions for BB10, stmt STMT00014, tree [000053], tree -> 0 Propagating 000000000000000F assertions for BB10, stmt STMT00014, tree [000054], tree -> 0 Propagating 000000000000000F assertions for BB10, stmt STMT00014, tree [000055], tree -> 0 Propagating 000000000000000F assertions for BB10, stmt STMT00016, tree [000063], tree -> 0 Propagating 000000000000000F assertions for BB10, stmt STMT00016, tree [000064], tree -> 0 Propagating 000000000000000F assertions for BB10, stmt STMT00016, tree [000562], tree -> 0 Propagating 000000000000000F assertions for BB10, stmt STMT00016, tree [000563], tree -> 0 Propagating 000000000000000F assertions for BB10, stmt STMT00016, tree [000547], tree -> 0 Propagating 000000000000000F assertions for BB10, stmt STMT00016, tree [000546], tree -> 0 Propagating 000000000000000F assertions for BB10, stmt STMT00016, tree [000548], tree -> 0 Propagating 000000000000000F assertions for BB10, stmt STMT00016, tree [000549], tree -> 0 Propagating 000000000000000F assertions for BB10, stmt STMT00016, tree [000550], tree -> 0 Propagating 000000000000000F assertions for BB10, stmt STMT00016, tree [000551], tree -> 8 Propagating 000000000000008F assertions for BB10, stmt STMT00016, tree [000552], tree -> 0 Propagating 000000000000008F assertions for BB10, stmt STMT00016, tree [000553], tree -> 0 Propagating 000000000000008F assertions for BB10, stmt STMT00016, tree [000554], tree -> 0 Propagating 000000000000008F assertions for BB10, stmt STMT00016, tree [000555], tree -> 0 Propagating 000000000000008F assertions for BB10, stmt STMT00016, tree [000556], tree -> 0 Propagating 000000000000008F assertions for BB10, stmt STMT00016, tree [000557], tree -> 0 Propagating 000000000000008F assertions for BB10, stmt STMT00016, tree [000558], tree -> 8 Propagating 000000000000008F assertions for BB10, stmt STMT00016, tree [000559], tree -> 0 Propagating 000000000000008F assertions for BB10, stmt STMT00016, tree [000560], tree -> 0 Propagating 000000000000008F assertions for BB10, stmt STMT00016, tree [000561], tree -> 0 Propagating 000000000000008F assertions for BB10, stmt STMT00016, tree [000568], tree -> 0 Propagating 000000000000008F assertions for BB10, stmt STMT00016, tree [000567], tree -> 0 Propagating 000000000000008F assertions for BB10, stmt STMT00016, tree [000564], tree -> 0 Propagating 000000000000008F assertions for BB10, stmt STMT00016, tree [000565], tree -> 0 Propagating 000000000000008F assertions for BB10, stmt STMT00016, tree [000566], tree -> 0 Propagating 000000000000008F assertions for BB10, stmt STMT00016, tree [000058], tree -> 0 Propagating 000000000000008F assertions for BB10, stmt STMT00016, tree [000057], tree -> 0 Propagating 000000000000008F assertions for BB10, stmt STMT00016, tree [000059], tree -> 0 Propagating 000000000000008F assertions for BB10, stmt STMT00017, tree [000065], tree -> 0 Propagating 000000000000008F assertions for BB10, stmt STMT00017, tree [000066], tree -> 0 Propagating 000000000000008F assertions for BB10, stmt STMT00017, tree [000067], tree -> 0 Propagating 000000000000008F assertions for BB10, stmt STMT00017, tree [000068], tree -> 9 Propagating 000000000000028F assertions for BB11, stmt STMT00083, tree [000569], tree -> 0 Propagating 000000000000028F assertions for BB11, stmt STMT00083, tree [000382], tree -> 0 Propagating 000000000000028F assertions for BB11, stmt STMT00083, tree [000383], tree -> 4 Non-null prop for index #04 in BB11: N003 ( 15, 8) [000383] --CXG------- * CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent $291 Propagating 000000000000028F assertions for BB11, stmt STMT00083, tree [000385], tree -> 0 Propagating 000000000000028F assertions for BB11, stmt STMT00083, tree [000380], tree -> 0 Propagating 000000000000028F assertions for BB11, stmt STMT00083, tree [000381], tree -> 0 Propagating 000000000000028F assertions for BB11, stmt STMT00083, tree [000386], tree -> 0 Propagating 000000000000028F assertions for BB11, stmt STMT00083, tree [000387], tree -> 0 Re-morphing this stmt: STMT00083 (IL ???... ???) N008 ( 23, 17) [000387] --CXG------- * JTRUE void N007 ( 21, 15) [000386] J-CXG--N---- \--* GE int $352 N004 ( 16, 10) [000385] --CXG------- +--* CAST long <- int $480 N003 ( 15, 8) [000383] --C-G------- | \--* CALL int FloatingPointType.get_OverflowDecimalExponent $291 N002 ( 1, 1) [000382] ------------ this in rcx | \--* LCL_VAR ref V01 arg1 u:1 $c0 N006 ( 4, 4) [000381] ---------U-- \--* CAST long <- ulong <- uint $481 N005 ( 3, 2) [000380] ------------ \--* LCL_VAR int V05 loc2 u:2 $34e ReMorphing args for 383.CALL: argSlots=1, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 ArgTable for 383.CALL after fgMorphArgs: fgArgTabEntry[arg 0 382.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed] optAssertionPropMain morphed tree: N008 ( 23, 17) [000387] --CXG------- * JTRUE void N007 ( 21, 15) [000386] J-CXG--N---- \--* GE int $352 N004 ( 16, 10) [000385] --CXG------- +--* CAST long <- int $480 N003 ( 15, 8) [000383] --CXG------- | \--* CALL int FloatingPointType.get_OverflowDecimalExponent $291 N002 ( 1, 1) [000382] ------------ this in rcx | \--* LCL_VAR ref V01 arg1 u:1 $c0 N006 ( 4, 4) [000381] ---------U-- \--* CAST long <- ulong <- uint $481 N005 ( 3, 2) [000380] ------------ \--* LCL_VAR int V05 loc2 u:2 $34e Propagating 000000000000028F assertions for BB12, stmt STMT00085, tree [000570], tree -> 0 Propagating 000000000000028F assertions for BB12, stmt STMT00085, tree [000393], tree -> 0 Propagating 000000000000028F assertions for BB12, stmt STMT00085, tree [000394], tree -> 4 Propagating 000000000000028F assertions for BB12, stmt STMT00085, tree [000392], tree -> 0 Propagating 000000000000028F assertions for BB12, stmt STMT00085, tree [000395], tree -> 5 Propagating 000000000000029F assertions for BB12, stmt STMT00085, tree [000396], tree -> 0 Propagating 000000000000029F assertions for BB12, stmt STMT00108, tree [000397], tree -> 0 Propagating 000000000000029F assertions for BB12, stmt STMT00108, tree [000521], tree -> 0 Propagating 000000000000028F assertions for BB13, stmt STMT00084, tree [000571], tree -> 0 Propagating 000000000000028F assertions for BB13, stmt STMT00084, tree [000572], tree -> 0 Propagating 000000000000028F assertions for BB13, stmt STMT00084, tree [000388], tree -> 0 Propagating 000000000000028F assertions for BB13, stmt STMT00084, tree [000389], tree -> 0 Propagating 000000000000028F assertions for BB13, stmt STMT00084, tree [000390], tree -> 0 Propagating 000000000000028F assertions for BB13, stmt STMT00084, tree [000391], tree -> 0 Propagating 000000000000008F assertions for BB14, stmt STMT00019, tree [000577], tree -> 0 Propagating 000000000000008F assertions for BB14, stmt STMT00019, tree [000576], tree -> 0 Propagating 000000000000008F assertions for BB14, stmt STMT00019, tree [000578], tree -> 0 Propagating 000000000000008F assertions for BB14, stmt STMT00019, tree [000579], tree -> 0 Propagating 000000000000008F assertions for BB14, stmt STMT00019, tree [000580], tree -> 0 Propagating 000000000000008F assertions for BB14, stmt STMT00019, tree [000581], tree -> 11 Propagating 000000000000048F assertions for BB14, stmt STMT00019, tree [000582], tree -> 0 Propagating 000000000000048F assertions for BB14, stmt STMT00019, tree [000583], tree -> 0 Propagating 000000000000048F assertions for BB14, stmt STMT00019, tree [000584], tree -> 0 Propagating 000000000000048F assertions for BB14, stmt STMT00019, tree [000585], tree -> 0 Propagating 000000000000048F assertions for BB14, stmt STMT00019, tree [000586], tree -> 0 Propagating 000000000000048F assertions for BB14, stmt STMT00019, tree [000587], tree -> 0 Propagating 000000000000048F assertions for BB14, stmt STMT00019, tree [000588], tree -> 11 Propagating 000000000000048F assertions for BB14, stmt STMT00019, tree [000589], tree -> 0 Propagating 000000000000048F assertions for BB14, stmt STMT00019, tree [000590], tree -> 0 Propagating 000000000000048F assertions for BB14, stmt STMT00019, tree [000591], tree -> 0 Propagating 000000000000048F assertions for BB14, stmt STMT00019, tree [000594], tree -> 0 Propagating 000000000000048F assertions for BB14, stmt STMT00019, tree [000592], tree -> 0 Propagating 000000000000048F assertions for BB14, stmt STMT00019, tree [000593], tree -> 0 Propagating 000000000000048F assertions for BB14, stmt STMT00019, tree [000071], tree -> 0 Propagating 000000000000048F assertions for BB14, stmt STMT00019, tree [000072], tree -> 0 Propagating 000000000000048F assertions for BB14, stmt STMT00019, tree [000076], tree -> 0 Propagating 000000000000048F assertions for BB14, stmt STMT00019, tree [000077], tree -> 0 Propagating 000000000000048F assertions for BB14, stmt STMT00020, tree [000078], tree -> 0 Propagating 000000000000048F assertions for BB14, stmt STMT00020, tree [000079], tree -> 0 Propagating 000000000000048F assertions for BB14, stmt STMT00020, tree [000080], tree -> 0 Propagating 000000000000048F assertions for BB14, stmt STMT00020, tree [000081], tree -> 0 Propagating 000000000000048F assertions for BB15, stmt STMT00022, tree [000091], tree -> 0 Propagating 000000000000048F assertions for BB15, stmt STMT00022, tree [000092], tree -> 0 Propagating 000000000000048F assertions for BB15, stmt STMT00022, tree [000093], tree -> 0 Propagating 000000000000048F assertions for BB15, stmt STMT00022, tree [000094], tree -> 12 Propagating 000000000000048F assertions for BB16, stmt STMT00021, tree [000596], tree -> 0 Propagating 000000000000048F assertions for BB16, stmt STMT00021, tree [000597], tree -> 0 Propagating 000000000000048F assertions for BB16, stmt STMT00021, tree [000595], tree -> 0 Propagating 000000000000048F assertions for BB16, stmt STMT00021, tree [000598], tree -> 0 Propagating 000000000000048F assertions for BB16, stmt STMT00021, tree [000088], tree -> 0 Propagating 000000000000048F assertions for BB16, stmt STMT00021, tree [000084], tree -> 0 Propagating 000000000000048F assertions for BB16, stmt STMT00021, tree [000085], tree -> 0 Propagating 000000000000048F assertions for BB16, stmt STMT00021, tree [000086], tree -> 0 Propagating 000000000000048F assertions for BB16, stmt STMT00021, tree [000082], tree -> 0 Propagating 000000000000048F assertions for BB16, stmt STMT00021, tree [000083], tree -> 0 Propagating 000000000000048F assertions for BB16, stmt STMT00021, tree [000087], tree -> 0 Propagating 000000000000048F assertions for BB16, stmt STMT00021, tree [000089], tree -> 0 Propagating 000000000000048F assertions for BB16, stmt STMT00021, tree [000599], tree -> 0 Propagating 000000000000048F assertions for BB16, stmt STMT00021, tree [000600], tree -> 0 Propagating 0000000000000C8F assertions for BB17, stmt STMT00023, tree [000097], tree -> 0 Propagating 0000000000000C8F assertions for BB17, stmt STMT00023, tree [000098], tree -> 0 Propagating 0000000000000C8F assertions for BB17, stmt STMT00023, tree [000099], tree -> 0 Propagating 0000000000000C8F assertions for BB17, stmt STMT00023, tree [000100], tree -> 14 Propagating 0000000000004C8F assertions for BB18, stmt STMT00081, tree [000376], tree -> 0 Propagating 0000000000004C8F assertions for BB18, stmt STMT00081, tree [000377], tree -> 0 Propagating 0000000000004C8F assertions for BB18, stmt STMT00081, tree [000378], tree -> 0 Propagating 0000000000002C8F assertions for BB19, stmt STMT00024, tree [000101], tree -> 0 Propagating 0000000000002C8F assertions for BB19, stmt STMT00024, tree [000104], tree -> 0 Propagating 0000000000002C8F assertions for BB19, stmt STMT00024, tree [000106], tree -> 0 Propagating 0000000000002C8F assertions for BB19, stmt STMT00024, tree [000107], tree -> 0 Propagating 0000000000002C8F assertions for BB19, stmt STMT00024, tree [000108], tree -> 0 Propagating 0000000000000C8F assertions for BB20, stmt STMT00025, tree [000110], tree -> 0 Propagating 0000000000000C8F assertions for BB20, stmt STMT00025, tree [000111], tree -> 0 Propagating 0000000000000C8F assertions for BB20, stmt STMT00025, tree [000112], tree -> 0 Propagating 0000000000000C8F assertions for BB20, stmt STMT00026, tree [000113], tree -> 0 Propagating 0000000000000C8F assertions for BB20, stmt STMT00026, tree [000114], tree -> 0 Propagating 0000000000000C8F assertions for BB20, stmt STMT00026, tree [000115], tree -> 0 Propagating 0000000000000C8F assertions for BB20, stmt STMT00026, tree [000116], tree -> 16 Propagating 0000000000010C8F assertions for BB21, stmt STMT00077, tree [000455], tree -> 0 Propagating 0000000000010C8F assertions for BB21, stmt STMT00077, tree [000456], tree -> 2 Propagating 0000000000010C8F assertions for BB21, stmt STMT00077, tree [000358], tree -> 0 Propagating 0000000000010C8F assertions for BB21, stmt STMT00077, tree [000352], tree -> 0 Propagating 0000000000010C8F assertions for BB21, stmt STMT00077, tree [000353], tree -> 0 Propagating 0000000000010C8F assertions for BB21, stmt STMT00077, tree [000359], tree -> 0 Propagating 0000000000010C8F assertions for BB21, stmt STMT00077, tree [000362], tree -> 0 Propagating 0000000000010C8F assertions for BB21, stmt STMT00077, tree [000363], tree -> 0 Propagating 0000000000010C8F assertions for BB21, stmt STMT00078, tree [000601], tree -> 0 Propagating 0000000000010C8F assertions for BB21, stmt STMT00078, tree [000360], tree -> 0 Propagating 0000000000010C8F assertions for BB21, stmt STMT00078, tree [000361], tree -> 4 Non-null prop for index #04 in BB21: N003 ( 15, 8) [000361] --CXG------- * CALL nullcheck int FloatingPointType.get_OverflowDecimalExponent $298 Propagating 0000000000010C8F assertions for BB21, stmt STMT00078, tree [000366], tree -> 0 Propagating 0000000000010C8F assertions for BB21, stmt STMT00078, tree [000364], tree -> 0 Propagating 0000000000010C8F assertions for BB21, stmt STMT00078, tree [000367], tree -> 0 Propagating 0000000000010C8F assertions for BB21, stmt STMT00078, tree [000368], tree -> 0 Re-morphing this stmt: STMT00078 (IL ???... ???) N007 ( 22, 15) [000368] --CXG------- * JTRUE void N006 ( 20, 13) [000367] J-CXG--N---- \--* GE int N004 ( 16, 10) [000366] --CXG------- +--* CAST long <- int $48b N003 ( 15, 8) [000361] --C-G------- | \--* CALL int FloatingPointType.get_OverflowDecimalExponent $298 N002 ( 1, 1) [000360] ------------ this in rcx | \--* LCL_VAR ref V01 arg1 u:1 $c0 N005 ( 3, 2) [000364] ------------ \--* LCL_VAR long V38 tmp8 u:2 (last use) ReMorphing args for 361.CALL: argSlots=1, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 ArgTable for 361.CALL after fgMorphArgs: fgArgTabEntry[arg 0 360.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed] optAssertionPropMain morphed tree: N007 ( 22, 15) [000368] --CXG------- * JTRUE void N006 ( 20, 13) [000367] J-CXG--N---- \--* GE int N004 ( 16, 10) [000366] --CXG------- +--* CAST long <- int $48b N003 ( 15, 8) [000361] --CXG------- | \--* CALL int FloatingPointType.get_OverflowDecimalExponent $298 N002 ( 1, 1) [000360] ------------ this in rcx | \--* LCL_VAR ref V01 arg1 u:1 $c0 N005 ( 3, 2) [000364] ------------ \--* LCL_VAR long V38 tmp8 u:2 (last use) Propagating 0000000000010C8F assertions for BB22, stmt STMT00079, tree [000602], tree -> 0 Propagating 0000000000010C8F assertions for BB22, stmt STMT00079, tree [000370], tree -> 0 Propagating 0000000000010C8F assertions for BB22, stmt STMT00079, tree [000371], tree -> 4 Propagating 0000000000010C8F assertions for BB22, stmt STMT00079, tree [000369], tree -> 0 Propagating 0000000000010C8F assertions for BB22, stmt STMT00079, tree [000372], tree -> 5 Propagating 0000000000010C9F assertions for BB22, stmt STMT00079, tree [000373], tree -> 0 Propagating 0000000000010C9F assertions for BB22, stmt STMT00110, tree [000374], tree -> 0 Propagating 0000000000010C9F assertions for BB22, stmt STMT00110, tree [000524], tree -> 0 Propagating 0000000000000C8F assertions for BB23, stmt STMT00028, tree [000124], tree -> 0 Propagating 0000000000000C8F assertions for BB23, stmt STMT00028, tree [000125], tree -> 0 Propagating 0000000000000C8F assertions for BB23, stmt STMT00028, tree [000622], tree -> 0 Propagating 0000000000000C8F assertions for BB23, stmt STMT00028, tree [000623], tree -> 0 Propagating 0000000000000C8F assertions for BB23, stmt STMT00028, tree [000607], tree -> 0 Propagating 0000000000000C8F assertions for BB23, stmt STMT00028, tree [000606], tree -> 0 Propagating 0000000000000C8F assertions for BB23, stmt STMT00028, tree [000608], tree -> 0 Propagating 0000000000000C8F assertions for BB23, stmt STMT00028, tree [000609], tree -> 0 Propagating 0000000000000C8F assertions for BB23, stmt STMT00028, tree [000610], tree -> 0 Propagating 0000000000000C8F assertions for BB23, stmt STMT00028, tree [000611], tree -> 18 Propagating 0000000000020C8F assertions for BB23, stmt STMT00028, tree [000612], tree -> 0 Propagating 0000000000020C8F assertions for BB23, stmt STMT00028, tree [000613], tree -> 0 Propagating 0000000000020C8F assertions for BB23, stmt STMT00028, tree [000614], tree -> 0 Propagating 0000000000020C8F assertions for BB23, stmt STMT00028, tree [000615], tree -> 0 Propagating 0000000000020C8F assertions for BB23, stmt STMT00028, tree [000616], tree -> 0 Propagating 0000000000020C8F assertions for BB23, stmt STMT00028, tree [000617], tree -> 0 Propagating 0000000000020C8F assertions for BB23, stmt STMT00028, tree [000618], tree -> 18 Propagating 0000000000020C8F assertions for BB23, stmt STMT00028, tree [000619], tree -> 0 Propagating 0000000000020C8F assertions for BB23, stmt STMT00028, tree [000620], tree -> 0 Propagating 0000000000020C8F assertions for BB23, stmt STMT00028, tree [000621], tree -> 0 Propagating 0000000000020C8F assertions for BB23, stmt STMT00028, tree [000627], tree -> 0 Propagating 0000000000020C8F assertions for BB23, stmt STMT00028, tree [000628], tree -> 0 Propagating 0000000000020C8F assertions for BB23, stmt STMT00028, tree [000624], tree -> 0 Propagating 0000000000020C8F assertions for BB23, stmt STMT00028, tree [000625], tree -> 0 Propagating 0000000000020C8F assertions for BB23, stmt STMT00028, tree [000626], tree -> 0 Propagating 0000000000020C8F assertions for BB23, stmt STMT00028, tree [000118], tree -> 0 Propagating 0000000000020C8F assertions for BB23, stmt STMT00028, tree [000119], tree -> 0 Propagating 0000000000020C8F assertions for BB23, stmt STMT00028, tree [000120], tree -> 0 Propagating 0000000000020C8F assertions for BB23, stmt STMT00029, tree [000629], tree -> 0 Propagating 0000000000020C8F assertions for BB23, stmt STMT00029, tree [000630], tree -> 0 Propagating 0000000000020C8F assertions for BB23, stmt STMT00029, tree [000131], tree -> 0 Propagating 0000000000020C8F assertions for BB23, stmt STMT00029, tree [000132], tree -> 0 Propagating 0000000000020C8F assertions for BB23, stmt STMT00029, tree [000133], tree -> 0 Propagating 0000000000020C8F assertions for BB23, stmt STMT00030, tree [000634], tree -> 0 Propagating 0000000000020C8F assertions for BB23, stmt STMT00030, tree [000633], tree -> 0 Propagating 0000000000020C8F assertions for BB23, stmt STMT00030, tree [000635], tree -> 0 Propagating 0000000000020C8F assertions for BB23, stmt STMT00030, tree [000632], tree -> 0 Propagating 0000000000020C8F assertions for BB23, stmt STMT00030, tree [000636], tree -> 0 Propagating 0000000000020C8F assertions for BB23, stmt STMT00030, tree [000637], tree -> 0 Propagating 0000000000020C8F assertions for BB23, stmt STMT00030, tree [000639], tree -> 0 Propagating 0000000000020C8F assertions for BB23, stmt STMT00030, tree [000640], tree -> 19 Propagating 0000000000060C8F assertions for BB23, stmt STMT00030, tree [000638], tree -> 0 Propagating 0000000000060C8F assertions for BB23, stmt STMT00030, tree [000641], tree -> 0 Propagating 0000000000060C8F assertions for BB23, stmt STMT00030, tree [000642], tree -> 0 Propagating 0000000000060C8F assertions for BB23, stmt STMT00030, tree [000644], tree -> 0 Propagating 0000000000060C8F assertions for BB23, stmt STMT00030, tree [000645], tree -> 0 Propagating 0000000000060C8F assertions for BB23, stmt STMT00030, tree [000646], tree -> 0 Propagating 0000000000060C8F assertions for BB23, stmt STMT00030, tree [000647], tree -> 19 Propagating 0000000000060C8F assertions for BB23, stmt STMT00030, tree [000643], tree -> 0 Propagating 0000000000060C8F assertions for BB23, stmt STMT00030, tree [000648], tree -> 0 Propagating 0000000000060C8F assertions for BB23, stmt STMT00030, tree [000649], tree -> 0 Propagating 0000000000060C8F assertions for BB23, stmt STMT00031, tree [000650], tree -> 0 Propagating 0000000000060C8F assertions for BB23, stmt STMT00031, tree [000651], tree -> 0 Propagating 0000000000060C8F assertions for BB23, stmt STMT00031, tree [000138], tree -> 0 Propagating 0000000000060C8F assertions for BB23, stmt STMT00031, tree [000139], tree -> 0 Propagating 0000000000060C8F assertions for BB23, stmt STMT00031, tree [000140], tree -> 0 Propagating 0000000000060C8F assertions for BB23, stmt STMT00031, tree [000141], tree -> 0 Propagating 0000000000060C8F assertions for BB23, stmt STMT00099, tree [000653], tree -> 0 Propagating 0000000000060C8F assertions for BB23, stmt STMT00099, tree [000652], tree -> 0 Propagating 0000000000060C8F assertions for BB23, stmt STMT00099, tree [000654], tree -> 0 Propagating 0000000000060C8F assertions for BB23, stmt STMT00099, tree [000656], tree -> 0 Propagating 0000000000060C8F assertions for BB23, stmt STMT00099, tree [000655], tree -> 0 Propagating 0000000000060C8F assertions for BB23, stmt STMT00099, tree [000657], tree -> 0 Propagating 0000000000060C8F assertions for BB23, stmt STMT00099, tree [000658], tree -> 0 Propagating 0000000000060C8F assertions for BB23, stmt STMT00098, tree [000663], tree -> 0 Propagating 0000000000060C8F assertions for BB23, stmt STMT00098, tree [000662], tree -> 0 Propagating 0000000000060C8F assertions for BB23, stmt STMT00098, tree [000664], tree -> 0 Propagating 0000000000060C8F assertions for BB23, stmt STMT00098, tree [000665], tree -> 0 Propagating 0000000000060C8F assertions for BB23, stmt STMT00098, tree [000666], tree -> 0 Propagating 0000000000060C8F assertions for BB23, stmt STMT00098, tree [000667], tree -> 20 Propagating 00000000000E0C8F assertions for BB23, stmt STMT00098, tree [000668], tree -> 0 Propagating 00000000000E0C8F assertions for BB23, stmt STMT00098, tree [000669], tree -> 0 Propagating 00000000000E0C8F assertions for BB23, stmt STMT00098, tree [000670], tree -> 0 Propagating 00000000000E0C8F assertions for BB23, stmt STMT00098, tree [000671], tree -> 0 Propagating 00000000000E0C8F assertions for BB23, stmt STMT00098, tree [000672], tree -> 0 Propagating 00000000000E0C8F assertions for BB23, stmt STMT00098, tree [000673], tree -> 0 Propagating 00000000000E0C8F assertions for BB23, stmt STMT00098, tree [000674], tree -> 20 Propagating 00000000000E0C8F assertions for BB23, stmt STMT00098, tree [000675], tree -> 0 Propagating 00000000000E0C8F assertions for BB23, stmt STMT00098, tree [000676], tree -> 0 Propagating 00000000000E0C8F assertions for BB23, stmt STMT00098, tree [000677], tree -> 0 Propagating 00000000000E0C8F assertions for BB23, stmt STMT00098, tree [000680], tree -> 0 Propagating 00000000000E0C8F assertions for BB23, stmt STMT00098, tree [000678], tree -> 0 Propagating 00000000000E0C8F assertions for BB23, stmt STMT00098, tree [000679], tree -> 0 Propagating 00000000000E0C8F assertions for BB23, stmt STMT00098, tree [000462], tree -> 0 Propagating 00000000000E0C8F assertions for BB23, stmt STMT00098, tree [000463], tree -> 0 Propagating 00000000000E0C8F assertions for BB23, stmt STMT00098, tree [000467], tree -> 0 Propagating 00000000000E0C8F assertions for BB23, stmt STMT00098, tree [000468], tree -> 0 Propagating 00000000000E0C8F assertions for BB23, stmt STMT00100, tree [000473], tree -> 0 Propagating 00000000000E0C8F assertions for BB23, stmt STMT00100, tree [000474], tree -> 0 Propagating 00000000000E0C8F assertions for BB23, stmt STMT00100, tree [000475], tree -> 0 Propagating 00000000000E0C8F assertions for BB23, stmt STMT00033, tree [000469], tree -> 0 Propagating 00000000000E0C8F assertions for BB23, stmt STMT00033, tree [000147], tree -> 0 Propagating 00000000000E0C8F assertions for BB23, stmt STMT00033, tree [000148], tree -> 0 Propagating 00000000000E0C8F assertions for BB23, stmt STMT00103, tree [000682], tree -> 0 Propagating 00000000000E0C8F assertions for BB23, stmt STMT00103, tree [000681], tree -> 0 Propagating 00000000000E0C8F assertions for BB23, stmt STMT00103, tree [000683], tree -> 0 Propagating 00000000000E0C8F assertions for BB23, stmt STMT00103, tree [000685], tree -> 0 Propagating 00000000000E0C8F assertions for BB23, stmt STMT00103, tree [000684], tree -> 0 Propagating 00000000000E0C8F assertions for BB23, stmt STMT00103, tree [000686], tree -> 0 Propagating 00000000000E0C8F assertions for BB23, stmt STMT00103, tree [000687], tree -> 0 Propagating 00000000000E0C8F assertions for BB23, stmt STMT00102, tree [000692], tree -> 0 Propagating 00000000000E0C8F assertions for BB23, stmt STMT00102, tree [000691], tree -> 0 Propagating 00000000000E0C8F assertions for BB23, stmt STMT00102, tree [000693], tree -> 0 Propagating 00000000000E0C8F assertions for BB23, stmt STMT00102, tree [000694], tree -> 0 Propagating 00000000000E0C8F assertions for BB23, stmt STMT00102, tree [000695], tree -> 0 Propagating 00000000000E0C8F assertions for BB23, stmt STMT00102, tree [000696], tree -> 21 Propagating 00000000001E0C8F assertions for BB23, stmt STMT00102, tree [000697], tree -> 0 Propagating 00000000001E0C8F assertions for BB23, stmt STMT00102, tree [000698], tree -> 0 Propagating 00000000001E0C8F assertions for BB23, stmt STMT00102, tree [000699], tree -> 0 Propagating 00000000001E0C8F assertions for BB23, stmt STMT00102, tree [000700], tree -> 0 Propagating 00000000001E0C8F assertions for BB23, stmt STMT00102, tree [000701], tree -> 0 Propagating 00000000001E0C8F assertions for BB23, stmt STMT00102, tree [000702], tree -> 0 Propagating 00000000001E0C8F assertions for BB23, stmt STMT00102, tree [000703], tree -> 21 Propagating 00000000001E0C8F assertions for BB23, stmt STMT00102, tree [000704], tree -> 0 Propagating 00000000001E0C8F assertions for BB23, stmt STMT00102, tree [000705], tree -> 0 Propagating 00000000001E0C8F assertions for BB23, stmt STMT00102, tree [000706], tree -> 0 Propagating 00000000001E0C8F assertions for BB23, stmt STMT00102, tree [000709], tree -> 0 Propagating 00000000001E0C8F assertions for BB23, stmt STMT00102, tree [000707], tree -> 0 Propagating 00000000001E0C8F assertions for BB23, stmt STMT00102, tree [000708], tree -> 0 Propagating 00000000001E0C8F assertions for BB23, stmt STMT00102, tree [000480], tree -> 0 Propagating 00000000001E0C8F assertions for BB23, stmt STMT00102, tree [000481], tree -> 0 Propagating 00000000001E0C8F assertions for BB23, stmt STMT00102, tree [000485], tree -> 0 Propagating 00000000001E0C8F assertions for BB23, stmt STMT00102, tree [000486], tree -> 0 Propagating 00000000001E0C8F assertions for BB23, stmt STMT00104, tree [000491], tree -> 0 Propagating 00000000001E0C8F assertions for BB23, stmt STMT00104, tree [000492], tree -> 0 Propagating 00000000001E0C8F assertions for BB23, stmt STMT00104, tree [000493], tree -> 0 Propagating 00000000001E0C8F assertions for BB23, stmt STMT00035, tree [000487], tree -> 0 Propagating 00000000001E0C8F assertions for BB23, stmt STMT00035, tree [000154], tree -> 0 Propagating 00000000001E0C8F assertions for BB23, stmt STMT00035, tree [000155], tree -> 0 Propagating 00000000001E0C8F assertions for BB23, stmt STMT00036, tree [000156], tree -> 0 Propagating 00000000001E0C8F assertions for BB23, stmt STMT00036, tree [000157], tree -> 0 Propagating 00000000001E0C8F assertions for BB23, stmt STMT00036, tree [000158], tree -> 0 Propagating 00000000001E0C8F assertions for BB23, stmt STMT00036, tree [000159], tree -> 0 Propagating 00000000001E0C8F assertions for BB24, stmt STMT00074, tree [000348], tree -> 0 Propagating 00000000001E0C8F assertions for BB24, stmt STMT00074, tree [000349], tree -> 0 Propagating 00000000001E0C8F assertions for BB24, stmt STMT00074, tree [000350], tree -> 0 Propagating 00000000001E0C8F assertions for BB25, stmt STMT00037, tree [000160], tree -> 0 Propagating 00000000001E0C8F assertions for BB25, stmt STMT00037, tree [000161], tree -> 0 Propagating 00000000001E0C8F assertions for BB25, stmt STMT00037, tree [000162], tree -> 0 Propagating 00000000001E0C8F assertions for BB25, stmt STMT00037, tree [000163], tree -> 0 Propagating 00000000001E0C8F assertions for BB25, stmt STMT00037, tree [000164], tree -> 0 Propagating 00000000001E0C8F assertions for BB26, stmt STMT00038, tree [000166], tree -> 0 Propagating 00000000001E0C8F assertions for BB26, stmt STMT00038, tree [000167], tree -> 0 Propagating 00000000001E0C8F assertions for BB26, stmt STMT00038, tree [000168], tree -> 0 Propagating 00000000001E0C8F assertions for BB26, stmt STMT00039, tree [000169], tree -> 0 Propagating 00000000001E0C8F assertions for BB26, stmt STMT00039, tree [000170], tree -> 0 Propagating 00000000001E0C8F assertions for BB26, stmt STMT00039, tree [000171], tree -> 0 Propagating 00000000001E0C8F assertions for BB26, stmt STMT00039, tree [000172], tree -> 22 Propagating 00000000005E0C8F assertions for BB27, stmt STMT00073, tree [000710], tree -> 0 Propagating 00000000005E0C8F assertions for BB27, stmt STMT00073, tree [000711], tree -> 0 Propagating 00000000005E0C8F assertions for BB27, stmt STMT00073, tree [000344], tree -> 0 Propagating 00000000005E0C8F assertions for BB27, stmt STMT00073, tree [000345], tree -> 0 Propagating 00000000005E0C8F assertions for BB27, stmt STMT00073, tree [000346], tree -> 0 Propagating 00000000005E0C8F assertions for BB27, stmt STMT00073, tree [000347], tree -> 0 Propagating 00000000001E0C8F assertions for BB28, stmt STMT00040, tree [000173], tree -> 0 Propagating 00000000001E0C8F assertions for BB28, stmt STMT00040, tree [000174], tree -> 0 Propagating 00000000001E0C8F assertions for BB28, stmt STMT00040, tree [000175], tree -> 0 Propagating 00000000001E0C8F assertions for BB28, stmt STMT00040, tree [000176], tree -> 0 Propagating 00000000001E0C8F assertions for BB28, stmt STMT00040, tree [000177], tree -> 0 Propagating 00000000001E0C8F assertions for BB28, stmt STMT00041, tree [000178], tree -> 0 Propagating 00000000001E0C8F assertions for BB28, stmt STMT00041, tree [000179], tree -> 0 Propagating 00000000001E0C8F assertions for BB28, stmt STMT00041, tree [000180], tree -> 0 Propagating 00000000001E0C8F assertions for BB28, stmt STMT00042, tree [000181], tree -> 0 Propagating 00000000001E0C8F assertions for BB28, stmt STMT00042, tree [000182], tree -> 0 Propagating 00000000001E0C8F assertions for BB28, stmt STMT00042, tree [000183], tree -> 0 Propagating 00000000001E0C8F assertions for BB28, stmt STMT00042, tree [000184], tree -> 17 Propagating 00000000001E8C8F assertions for BB29, stmt STMT00070, tree [000326], tree -> 0 Propagating 00000000001E8C8F assertions for BB29, stmt STMT00070, tree [000327], tree -> 0 Propagating 00000000001E8C8F assertions for BB29, stmt STMT00070, tree [000328], tree -> 0 Propagating 00000000001E8C8F assertions for BB29, stmt STMT00070, tree [000329], tree -> 0 Propagating 00000000001E8C8F assertions for BB30, stmt STMT00072, tree [000713], tree -> 0 Propagating 00000000001E8C8F assertions for BB30, stmt STMT00072, tree [000714], tree -> 0 Propagating 00000000001E8C8F assertions for BB30, stmt STMT00072, tree [000712], tree -> 0 Propagating 00000000001E8C8F assertions for BB30, stmt STMT00072, tree [000715], tree -> 0 Propagating 00000000001E8C8F assertions for BB30, stmt STMT00072, tree [000341], tree -> 0 Propagating 00000000001E8C8F assertions for BB30, stmt STMT00072, tree [000337], tree -> 0 Propagating 00000000001E8C8F assertions for BB30, stmt STMT00072, tree [000338], tree -> 0 Propagating 00000000001E8C8F assertions for BB30, stmt STMT00072, tree [000339], tree -> 0 VN relop based constant assertion prop in BB30: Assertion index=#12: [000337] != 0 N008 ( 6, 3) [000339] N----------- * NE int Folding operator with constant nodes into a constant: N008 ( 6, 3) [000339] N----------- * EQ int N006 ( 1, 1) [000337] ------------ +--* CNS_INT int 0 $40 N007 ( 1, 1) [000338] ------------ \--* CNS_INT int 0 $40 Bashed to int constant: N008 ( 6, 3) [000339] ------------ * CNS_INT int 1 $41 N008 ( 6, 3) [000339] ------------ * CNS_INT int 1 $41 Propagating 00000000001E8C8F assertions for BB30, stmt STMT00072, tree [000335], tree -> 0 Propagating 00000000001E8C8F assertions for BB30, stmt STMT00072, tree [000336], tree -> 0 Propagating 00000000001E8C8F assertions for BB30, stmt STMT00072, tree [000340], tree -> 0 Propagating 00000000001E8C8F assertions for BB30, stmt STMT00072, tree [000342], tree -> 0 Propagating 00000000001E8C8F assertions for BB30, stmt STMT00072, tree [000716], tree -> 0 Propagating 00000000001E8C8F assertions for BB30, stmt STMT00072, tree [000717], tree -> 0 Re-morphing this stmt: STMT00072 (IL 0x144...0x154) N014 ( 29, 17) [000717] -ACXG---R--- * ASG int $5c2 N013 ( 1, 1) [000716] D------N---- +--* LCL_VAR int V51 tmp21 d:5 $5c2 N012 ( 29, 17) [000342] --CXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits $5c2 N005 ( 1, 1) [000341] ------------ arg4 out+20 +--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N008 ( 6, 3) [000339] ------------ arg2 in r8 +--* CNS_INT int 1 $41 N009 ( 3, 2) [000335] ----G------- arg0 in rcx +--* LCL_VAR ref (AX) V12 loc9 $18c N010 ( 1, 1) [000336] ------------ arg1 in rdx +--* LCL_VAR int V13 loc10 u:2 (last use) $293 N011 ( 1, 1) [000340] ------------ arg3 in r9 \--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 ReMorphing args for 342.CALL: argSlots=5, preallocatedArgCount=5, nextSlotNum=5, nextSlotByteOffset=40, outgoingArgSpaceSize=40 ArgTable for 342.CALL after fgMorphArgs: fgArgTabEntry[arg 2 339.CNS_INT int (By ref), 1 reg: r8, byteAlignment=8, lateArgInx=0, processed] fgArgTabEntry[arg 0 335.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=1, processed] fgArgTabEntry[arg 1 336.LCL_VAR int (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=2, processed] fgArgTabEntry[arg 3 340.LCL_VAR ref (By ref), 1 reg: r9, byteAlignment=8, lateArgInx=3, processed] fgArgTabEntry[arg 4 341.LCL_VAR byref (By ref), numSlots=1, slotNum=4, byteSize=8, byteOffset=32, byteAlignment=8, processed] optAssertionPropMain morphed tree: N012 ( 24, 15) [000717] -ACXG---R--- * ASG int $5c2 N011 ( 1, 1) [000716] D------N---- +--* LCL_VAR int V51 tmp21 d:5 $5c2 N010 ( 24, 15) [000342] --CXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits $5c2 N005 ( 1, 1) [000341] ------------ arg4 out+20 +--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N006 ( 1, 1) [000339] ------------ arg2 in r8 +--* CNS_INT int 1 $41 N007 ( 3, 2) [000335] ----G------- arg0 in rcx +--* LCL_VAR ref (AX) V12 loc9 $18c N008 ( 1, 1) [000336] ------------ arg1 in rdx +--* LCL_VAR int V13 loc10 u:2 (last use) $293 N009 ( 1, 1) [000340] ------------ arg3 in r9 \--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 Propagating 00000000001E8C8F assertions for BB31, stmt STMT00071, tree [000330], tree -> 0 Propagating 00000000001E8C8F assertions for BB31, stmt STMT00071, tree [000331], tree -> 0 Propagating 00000000001E8C8F assertions for BB31, stmt STMT00071, tree [000332], tree -> 0 Propagating 00000000001E8C8F assertions for BB31, stmt STMT00071, tree [000333], tree -> 0 Propagating 00000000001E8C8F assertions for BB31, stmt STMT00071, tree [000334], tree -> 0 Propagating 00000000001E0C8F assertions for BB32, stmt STMT00105, tree [000719], tree -> 0 Propagating 00000000001E0C8F assertions for BB32, stmt STMT00105, tree [000718], tree -> 0 Propagating 00000000001E0C8F assertions for BB32, stmt STMT00105, tree [000720], tree -> 0 Propagating 00000000001E0C8F assertions for BB32, stmt STMT00105, tree [000722], tree -> 0 Propagating 00000000001E0C8F assertions for BB32, stmt STMT00105, tree [000721], tree -> 0 Propagating 00000000001E0C8F assertions for BB32, stmt STMT00105, tree [000723], tree -> 0 Propagating 00000000001E0C8F assertions for BB32, stmt STMT00105, tree [000724], tree -> 0 Propagating 00000000001E0C8F assertions for BB32, stmt STMT00106, tree [000726], tree -> 0 Propagating 00000000001E0C8F assertions for BB32, stmt STMT00106, tree [000725], tree -> 0 Propagating 00000000001E0C8F assertions for BB32, stmt STMT00106, tree [000727], tree -> 0 Propagating 00000000001E0C8F assertions for BB32, stmt STMT00106, tree [000729], tree -> 0 Propagating 00000000001E0C8F assertions for BB32, stmt STMT00106, tree [000728], tree -> 0 Propagating 00000000001E0C8F assertions for BB32, stmt STMT00106, tree [000730], tree -> 0 Propagating 00000000001E0C8F assertions for BB32, stmt STMT00106, tree [000731], tree -> 0 Propagating 00000000001E0C8F assertions for BB32, stmt STMT00044, tree [000496], tree -> 0 Propagating 00000000001E0C8F assertions for BB32, stmt STMT00044, tree [000497], tree -> 0 Propagating 00000000001E0C8F assertions for BB32, stmt STMT00044, tree [000751], tree -> 0 Propagating 00000000001E0C8F assertions for BB32, stmt STMT00044, tree [000752], tree -> 0 Propagating 00000000001E0C8F assertions for BB32, stmt STMT00044, tree [000736], tree -> 0 Propagating 00000000001E0C8F assertions for BB32, stmt STMT00044, tree [000735], tree -> 0 Propagating 00000000001E0C8F assertions for BB32, stmt STMT00044, tree [000737], tree -> 0 Propagating 00000000001E0C8F assertions for BB32, stmt STMT00044, tree [000738], tree -> 0 Propagating 00000000001E0C8F assertions for BB32, stmt STMT00044, tree [000739], tree -> 0 Propagating 00000000001E0C8F assertions for BB32, stmt STMT00044, tree [000740], tree -> 24 Propagating 00000000009E0C8F assertions for BB32, stmt STMT00044, tree [000741], tree -> 0 Propagating 00000000009E0C8F assertions for BB32, stmt STMT00044, tree [000742], tree -> 0 Propagating 00000000009E0C8F assertions for BB32, stmt STMT00044, tree [000743], tree -> 0 Propagating 00000000009E0C8F assertions for BB32, stmt STMT00044, tree [000744], tree -> 0 Propagating 00000000009E0C8F assertions for BB32, stmt STMT00044, tree [000745], tree -> 0 Propagating 00000000009E0C8F assertions for BB32, stmt STMT00044, tree [000746], tree -> 0 Propagating 00000000009E0C8F assertions for BB32, stmt STMT00044, tree [000747], tree -> 24 Propagating 00000000009E0C8F assertions for BB32, stmt STMT00044, tree [000748], tree -> 0 Propagating 00000000009E0C8F assertions for BB32, stmt STMT00044, tree [000749], tree -> 0 Propagating 00000000009E0C8F assertions for BB32, stmt STMT00044, tree [000750], tree -> 0 Propagating 00000000009E0C8F assertions for BB32, stmt STMT00044, tree [000753], tree -> 0 Propagating 00000000009E0C8F assertions for BB32, stmt STMT00044, tree [000754], tree -> 0 Propagating 00000000009E0C8F assertions for BB32, stmt STMT00044, tree [000755], tree -> 0 Propagating 00000000009E0C8F assertions for BB32, stmt STMT00044, tree [000499], tree -> 0 Propagating 00000000009E0C8F assertions for BB32, stmt STMT00044, tree [000502], tree -> 0 Propagating 00000000009E0C8F assertions for BB32, stmt STMT00044, tree [000503], tree -> 0 Propagating 00000000009E0C8F assertions for BB32, stmt STMT00044, tree [000195], tree -> 25 Propagating 00000000029E0C8F assertions for BB33, stmt STMT00069, tree [000322], tree -> 0 Propagating 00000000029E0C8F assertions for BB33, stmt STMT00069, tree [000323], tree -> 0 Propagating 00000000029E0C8F assertions for BB33, stmt STMT00069, tree [000324], tree -> 0 Propagating 00000000019E0C8F assertions for BB34, stmt STMT00045, tree [000196], tree -> 0 Propagating 00000000019E0C8F assertions for BB34, stmt STMT00045, tree [000197], tree -> 0 Propagating 00000000019E0C8F assertions for BB34, stmt STMT00045, tree [000198], tree -> 0 Propagating 00000000019E0C8F assertions for BB34, stmt STMT00045, tree [000199], tree -> 0 Propagating 00000000019E0C8F assertions for BB34, stmt STMT00045, tree [000200], tree -> 0 Propagating 00000000009E0C8F assertions for BB35, stmt STMT00046, tree [000202], tree -> 0 Propagating 00000000009E0C8F assertions for BB35, stmt STMT00046, tree [000203], tree -> 0 Propagating 00000000009E0C8F assertions for BB35, stmt STMT00046, tree [000204], tree -> 0 Propagating 00000000009E0C8F assertions for BB35, stmt STMT00047, tree [000756], tree -> 0 Propagating 00000000009E0C8F assertions for BB35, stmt STMT00047, tree [000757], tree -> 0 Propagating 00000000009E0C8F assertions for BB35, stmt STMT00047, tree [000205], tree -> 0 Propagating 00000000009E0C8F assertions for BB35, stmt STMT00047, tree [000206], tree -> 0 Propagating 00000000009E0C8F assertions for BB35, stmt STMT00047, tree [000207], tree -> 0 Propagating 00000000009E0C8F assertions for BB35, stmt STMT00047, tree [000208], tree -> 0 Propagating 00000000009E0C8F assertions for BB35, stmt STMT00048, tree [000219], tree -> 0 Propagating 00000000009E0C8F assertions for BB35, stmt STMT00048, tree [000220], tree -> 0 Propagating 00000000009E0C8F assertions for BB35, stmt STMT00048, tree [000796], tree -> 0 Propagating 00000000009E0C8F assertions for BB35, stmt STMT00048, tree [000797], tree -> 0 Propagating 00000000009E0C8F assertions for BB35, stmt STMT00048, tree [000762], tree -> 0 Propagating 00000000009E0C8F assertions for BB35, stmt STMT00048, tree [000761], tree -> 0 Propagating 00000000009E0C8F assertions for BB35, stmt STMT00048, tree [000763], tree -> 0 Propagating 00000000009E0C8F assertions for BB35, stmt STMT00048, tree [000764], tree -> 0 Propagating 00000000009E0C8F assertions for BB35, stmt STMT00048, tree [000765], tree -> 0 Propagating 00000000009E0C8F assertions for BB35, stmt STMT00048, tree [000766], tree -> 27 Propagating 00000000049E0C8F assertions for BB35, stmt STMT00048, tree [000767], tree -> 0 Propagating 00000000049E0C8F assertions for BB35, stmt STMT00048, tree [000768], tree -> 0 Propagating 00000000049E0C8F assertions for BB35, stmt STMT00048, tree [000769], tree -> 0 Propagating 00000000049E0C8F assertions for BB35, stmt STMT00048, tree [000770], tree -> 0 Propagating 00000000049E0C8F assertions for BB35, stmt STMT00048, tree [000771], tree -> 0 Propagating 00000000049E0C8F assertions for BB35, stmt STMT00048, tree [000772], tree -> 0 Propagating 00000000049E0C8F assertions for BB35, stmt STMT00048, tree [000773], tree -> 27 Propagating 00000000049E0C8F assertions for BB35, stmt STMT00048, tree [000774], tree -> 0 Propagating 00000000049E0C8F assertions for BB35, stmt STMT00048, tree [000775], tree -> 0 Propagating 00000000049E0C8F assertions for BB35, stmt STMT00048, tree [000776], tree -> 0 Propagating 00000000049E0C8F assertions for BB35, stmt STMT00048, tree [000781], tree -> 0 Propagating 00000000049E0C8F assertions for BB35, stmt STMT00048, tree [000780], tree -> 0 Propagating 00000000049E0C8F assertions for BB35, stmt STMT00048, tree [000782], tree -> 0 Propagating 00000000049E0C8F assertions for BB35, stmt STMT00048, tree [000783], tree -> 0 Propagating 00000000049E0C8F assertions for BB35, stmt STMT00048, tree [000784], tree -> 0 Propagating 00000000049E0C8F assertions for BB35, stmt STMT00048, tree [000785], tree -> 28 Propagating 000000000C9E0C8F assertions for BB35, stmt STMT00048, tree [000786], tree -> 0 Propagating 000000000C9E0C8F assertions for BB35, stmt STMT00048, tree [000787], tree -> 0 Propagating 000000000C9E0C8F assertions for BB35, stmt STMT00048, tree [000788], tree -> 0 Propagating 000000000C9E0C8F assertions for BB35, stmt STMT00048, tree [000789], tree -> 0 Propagating 000000000C9E0C8F assertions for BB35, stmt STMT00048, tree [000790], tree -> 0 Propagating 000000000C9E0C8F assertions for BB35, stmt STMT00048, tree [000791], tree -> 0 Propagating 000000000C9E0C8F assertions for BB35, stmt STMT00048, tree [000792], tree -> 28 Propagating 000000000C9E0C8F assertions for BB35, stmt STMT00048, tree [000793], tree -> 0 Propagating 000000000C9E0C8F assertions for BB35, stmt STMT00048, tree [000794], tree -> 0 Propagating 000000000C9E0C8F assertions for BB35, stmt STMT00048, tree [000795], tree -> 0 Propagating 000000000C9E0C8F assertions for BB35, stmt STMT00048, tree [000803], tree -> 0 Propagating 000000000C9E0C8F assertions for BB35, stmt STMT00048, tree [000798], tree -> 0 Propagating 000000000C9E0C8F assertions for BB35, stmt STMT00048, tree [000799], tree -> 0 Propagating 000000000C9E0C8F assertions for BB35, stmt STMT00048, tree [000800], tree -> 0 Propagating 000000000C9E0C8F assertions for BB35, stmt STMT00048, tree [000801], tree -> 0 Propagating 000000000C9E0C8F assertions for BB35, stmt STMT00048, tree [000802], tree -> 0 Propagating 000000000C9E0C8F assertions for BB35, stmt STMT00048, tree [000211], tree -> 0 Propagating 000000000C9E0C8F assertions for BB35, stmt STMT00048, tree [000212], tree -> 0 Propagating 000000000C9E0C8F assertions for BB35, stmt STMT00048, tree [000213], tree -> 0 Propagating 000000000C9E0C8F assertions for BB35, stmt STMT00050, tree [000808], tree -> 0 Propagating 000000000C9E0C8F assertions for BB35, stmt STMT00050, tree [000807], tree -> 0 Propagating 000000000C9E0C8F assertions for BB35, stmt STMT00050, tree [000809], tree -> 0 Propagating 000000000C9E0C8F assertions for BB35, stmt STMT00050, tree [000810], tree -> 0 Propagating 000000000C9E0C8F assertions for BB35, stmt STMT00050, tree [000811], tree -> 0 Propagating 000000000C9E0C8F assertions for BB35, stmt STMT00050, tree [000812], tree -> 29 Propagating 000000001C9E0C8F assertions for BB35, stmt STMT00050, tree [000813], tree -> 0 Propagating 000000001C9E0C8F assertions for BB35, stmt STMT00050, tree [000814], tree -> 0 Propagating 000000001C9E0C8F assertions for BB35, stmt STMT00050, tree [000815], tree -> 0 Propagating 000000001C9E0C8F assertions for BB35, stmt STMT00050, tree [000816], tree -> 0 Propagating 000000001C9E0C8F assertions for BB35, stmt STMT00050, tree [000817], tree -> 0 Propagating 000000001C9E0C8F assertions for BB35, stmt STMT00050, tree [000818], tree -> 0 Propagating 000000001C9E0C8F assertions for BB35, stmt STMT00050, tree [000819], tree -> 29 Propagating 000000001C9E0C8F assertions for BB35, stmt STMT00050, tree [000820], tree -> 0 Propagating 000000001C9E0C8F assertions for BB35, stmt STMT00050, tree [000821], tree -> 0 Propagating 000000001C9E0C8F assertions for BB35, stmt STMT00050, tree [000822], tree -> 0 Propagating 000000001C9E0C8F assertions for BB35, stmt STMT00050, tree [000823], tree -> 0 Propagating 000000001C9E0C8F assertions for BB35, stmt STMT00050, tree [000824], tree -> 0 Propagating 000000001C9E0C8F assertions for BB35, stmt STMT00050, tree [000218], tree -> 0 Propagating 000000001C9E0C8F assertions for BB35, stmt STMT00050, tree [000225], tree -> 0 Propagating 000000001C9E0C8F assertions for BB35, stmt STMT00050, tree [000226], tree -> 0 Propagating 000000001C9E0C8F assertions for BB35, stmt STMT00052, tree [000514], tree -> 0 Propagating 000000001C9E0C8F assertions for BB35, stmt STMT00052, tree [000515], tree -> 0 Propagating 000000001C9E0C8F assertions for BB35, stmt STMT00052, tree [000516], tree -> 0 Propagating 000000001C9E0C8F assertions for BB35, stmt STMT00052, tree [000231], tree -> 0 Propagating 000000001C9E0C8F assertions for BB35, stmt STMT00052, tree [000232], tree -> 0 Propagating 000000001C9E0C8F assertions for BB35, stmt STMT00054, tree [000825], tree -> 0 Propagating 000000001C9E0C8F assertions for BB35, stmt STMT00054, tree [000233], tree -> 0 Propagating 000000001C9E0C8F assertions for BB35, stmt STMT00054, tree [000234], tree -> 0 Propagating 000000001C9E0C8F assertions for BB35, stmt STMT00054, tree [000236], tree -> 0 Propagating 000000001C9E0C8F assertions for BB35, stmt STMT00054, tree [000237], tree -> 0 Propagating 000000001C9E0C8F assertions for BB35, stmt STMT00055, tree [000238], tree -> 0 Propagating 000000001C9E0C8F assertions for BB35, stmt STMT00055, tree [000239], tree -> 0 Propagating 000000001C9E0C8F assertions for BB35, stmt STMT00055, tree [000240], tree -> 0 Propagating 000000001C9E0C8F assertions for BB35, stmt STMT00055, tree [000241], tree -> 0 Propagating 000000001C9E0C8F assertions for BB36, stmt STMT00063, tree [000282], tree -> 0 Propagating 000000001C9E0C8F assertions for BB36, stmt STMT00063, tree [000283], tree -> 0 Propagating 000000001C9E0C8F assertions for BB36, stmt STMT00063, tree [000284], tree -> 0 Propagating 000000001C9E0C8F assertions for BB36, stmt STMT00063, tree [000285], tree -> 0 Propagating 000000001C9E0C8F assertions for BB36, stmt STMT00063, tree [000286], tree -> 0 Propagating 000000001C9E0C8F assertions for BB36, stmt STMT00064, tree [000287], tree -> 0 Propagating 000000001C9E0C8F assertions for BB36, stmt STMT00064, tree [000288], tree -> 0 Propagating 000000001C9E0C8F assertions for BB36, stmt STMT00064, tree [000289], tree -> 0 Propagating 000000001C9E0C8F assertions for BB36, stmt STMT00064, tree [000290], tree -> 30 Propagating 000000005C9E0C8F assertions for BB37, stmt STMT00068, tree [000305], tree -> 0 Propagating 000000005C9E0C8F assertions for BB37, stmt STMT00068, tree [000308], tree -> 0 Propagating 000000005C9E0C8F assertions for BB37, stmt STMT00068, tree [000309], tree -> 0 Propagating 000000005C9E0C8F assertions for BB37, stmt STMT00068, tree [000310], tree -> 0 Propagating 000000005C9E0C8F assertions for BB37, stmt STMT00068, tree [000307], tree -> 0 Propagating 000000005C9E0C8F assertions for BB37, stmt STMT00068, tree [000311], tree -> 0 Propagating 000000005C9E0C8F assertions for BB37, stmt STMT00068, tree [000313], tree -> 0 Propagating 000000005C9E0C8F assertions for BB37, stmt STMT00068, tree [000314], tree -> 0 Propagating 000000005C9E0C8F assertions for BB37, stmt STMT00068, tree [000315], tree -> 0 Propagating 000000005C9E0C8F assertions for BB37, stmt STMT00068, tree [000317], tree -> 0 Propagating 000000005C9E0C8F assertions for BB37, stmt STMT00068, tree [000318], tree -> 0 Propagating 000000005C9E0C8F assertions for BB37, stmt STMT00068, tree [000319], tree -> 0 Propagating 000000005C9E0C8F assertions for BB37, stmt STMT00068, tree [000320], tree -> 0 Propagating 000000003C9E0C8F assertions for BB38, stmt STMT00065, tree [000291], tree -> 0 Propagating 000000003C9E0C8F assertions for BB38, stmt STMT00065, tree [000292], tree -> 0 Propagating 000000003C9E0C8F assertions for BB38, stmt STMT00065, tree [000293], tree -> 0 Propagating 000000001C9E0C8F assertions for BB39, stmt STMT00066, tree [000295], tree -> 0 Propagating 000000001C9E0C8F assertions for BB39, stmt STMT00066, tree [000826], tree -> 0 Propagating 000000001C9E0C8F assertions for BB39, stmt STMT00066, tree [000296], tree -> 0 Propagating 000000001C9E0C8F assertions for BB39, stmt STMT00066, tree [000297], tree -> 0 Propagating 000000001C9E0C8F assertions for BB39, stmt STMT00067, tree [000298], tree -> 0 Propagating 000000001C9E0C8F assertions for BB39, stmt STMT00067, tree [000299], tree -> 0 Propagating 000000001C9E0C8F assertions for BB39, stmt STMT00067, tree [000300], tree -> 0 Propagating 000000001C9E0C8F assertions for BB39, stmt STMT00067, tree [000301], tree -> 0 Propagating 000000001C9E0C8F assertions for BB39, stmt STMT00067, tree [000302], tree -> 0 Propagating 000000001C9E0C8F assertions for BB39, stmt STMT00067, tree [000303], tree -> 0 Propagating 000000001C9E0C8F assertions for BB39, stmt STMT00067, tree [000304], tree -> 0 Propagating 000000001C9E0C8F assertions for BB40, stmt STMT00057, tree [000831], tree -> 0 Propagating 000000001C9E0C8F assertions for BB40, stmt STMT00057, tree [000830], tree -> 0 Propagating 000000001C9E0C8F assertions for BB40, stmt STMT00057, tree [000832], tree -> 0 Propagating 000000001C9E0C8F assertions for BB40, stmt STMT00057, tree [000833], tree -> 0 Propagating 000000001C9E0C8F assertions for BB40, stmt STMT00057, tree [000834], tree -> 0 Propagating 000000001C9E0C8F assertions for BB40, stmt STMT00057, tree [000835], tree -> 33 Propagating 000000001C9E0C8F assertions for BB40, stmt STMT00057, tree [000836], tree -> 0 Propagating 000000001C9E0C8F assertions for BB40, stmt STMT00057, tree [000837], tree -> 0 Propagating 000000001C9E0C8F assertions for BB40, stmt STMT00057, tree [000838], tree -> 0 Propagating 000000001C9E0C8F assertions for BB40, stmt STMT00057, tree [000839], tree -> 0 Propagating 000000001C9E0C8F assertions for BB40, stmt STMT00057, tree [000840], tree -> 0 Propagating 000000001C9E0C8F assertions for BB40, stmt STMT00057, tree [000841], tree -> 0 Propagating 000000001C9E0C8F assertions for BB40, stmt STMT00057, tree [000842], tree -> 33 Propagating 000000001C9E0C8F assertions for BB40, stmt STMT00057, tree [000843], tree -> 0 Propagating 000000001C9E0C8F assertions for BB40, stmt STMT00057, tree [000844], tree -> 0 Propagating 000000001C9E0C8F assertions for BB40, stmt STMT00057, tree [000845], tree -> 0 Propagating 000000001C9E0C8F assertions for BB40, stmt STMT00057, tree [000846], tree -> 0 Propagating 000000001C9E0C8F assertions for BB40, stmt STMT00057, tree [000847], tree -> 0 Propagating 000000001C9E0C8F assertions for BB40, stmt STMT00057, tree [000243], tree -> 0 Propagating 000000001C9E0C8F assertions for BB40, stmt STMT00057, tree [000247], tree -> 0 Propagating 000000001C9E0C8F assertions for BB40, stmt STMT00057, tree [000248], tree -> 0 Propagating 000000001C9E0C8F assertions for BB40, stmt STMT00057, tree [000249], tree -> 0 Propagating 000000001C9E0C8F assertions for BB40, stmt STMT00057, tree [000250], tree -> 0 Propagating 000000001C9E0C8F assertions for BB40, stmt STMT00057, tree [000251], tree -> 0 Propagating 000000001C9E0C8F assertions for BB40, stmt STMT00057, tree [000252], tree -> 0 Propagating 000000001C9E0C8F assertions for BB40, stmt STMT00057, tree [000253], tree -> 0 Propagating 000000001C9E0C8F assertions for BB40, stmt STMT00057, tree [000254], tree -> 0 Propagating 000000001C9E0C8F assertions for BB40, stmt STMT00058, tree [000255], tree -> 0 Propagating 000000001C9E0C8F assertions for BB40, stmt STMT00058, tree [000256], tree -> 0 Propagating 000000001C9E0C8F assertions for BB40, stmt STMT00058, tree [000257], tree -> 0 Propagating 000000001C9E0C8F assertions for BB40, stmt STMT00058, tree [000258], tree -> 16 Propagating 000000001C9F0C8F assertions for BB41, stmt STMT00062, tree [000275], tree -> 0 Propagating 000000001C9F0C8F assertions for BB41, stmt STMT00062, tree [000276], tree -> 0 Propagating 000000001C9F0C8F assertions for BB41, stmt STMT00062, tree [000277], tree -> 0 Propagating 000000001C9F0C8F assertions for BB41, stmt STMT00062, tree [000278], tree -> 0 Propagating 000000001C9F0C8F assertions for BB41, stmt STMT00062, tree [000279], tree -> 0 Propagating 000000001C9F0C8F assertions for BB41, stmt STMT00062, tree [000280], tree -> 0 Propagating 000000001C9E8C8F assertions for BB42, stmt STMT00059, tree [000259], tree -> 0 Propagating 000000001C9E8C8F assertions for BB42, stmt STMT00059, tree [000260], tree -> 0 Propagating 000000001C9E8C8F assertions for BB42, stmt STMT00059, tree [000261], tree -> 0 Propagating 000000001C9E8C8F assertions for BB42, stmt STMT00059, tree [000262], tree -> 0 Propagating 000000001C9E8C8F assertions for BB42, stmt STMT00059, tree [000263], tree -> 0 Propagating 000000001C9E0C8F assertions for BB43, stmt STMT00061, tree [000848], tree -> 0 Propagating 000000001C9E0C8F assertions for BB43, stmt STMT00061, tree [000849], tree -> 0 Propagating 000000001C9E0C8F assertions for BB43, stmt STMT00061, tree [000850], tree -> 0 Propagating 000000001C9E0C8F assertions for BB43, stmt STMT00061, tree [000851], tree -> 0 Propagating 000000001C9E0C8F assertions for BB43, stmt STMT00061, tree [000272], tree -> 0 Propagating 000000001C9E0C8F assertions for BB43, stmt STMT00061, tree [000268], tree -> 0 Propagating 000000001C9E0C8F assertions for BB43, stmt STMT00061, tree [000269], tree -> 0 Propagating 000000001C9E0C8F assertions for BB43, stmt STMT00061, tree [000270], tree -> 0 Propagating 000000001C9E0C8F assertions for BB43, stmt STMT00061, tree [000271], tree -> 0 Propagating 000000001C9E0C8F assertions for BB43, stmt STMT00061, tree [000273], tree -> 4 Non-null prop for index #04 in BB43: N010 ( 28, 18) [000273] --CXG------- * CALL nullcheck int FloatingPointType.AssembleFloatingPointValue $2be Propagating 000000001C9E0C8F assertions for BB43, stmt STMT00061, tree [000852], tree -> 0 Propagating 000000001C9E0C8F assertions for BB43, stmt STMT00061, tree [000853], tree -> 0 Re-morphing this stmt: STMT00061 (IL 0x1F4...0x201) N012 ( 28, 18) [000853] -ACXG---R--- * ASG int $2be N011 ( 1, 1) [000852] D------N---- +--* LCL_VAR int V51 tmp21 d:4 $2be N010 ( 28, 18) [000273] --C-G------- \--* CALL int FloatingPointType.AssembleFloatingPointValue $2be N005 ( 1, 1) [000272] ------------ arg4 out+20 +--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N006 ( 1, 1) [000268] ------------ this in rcx +--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 N007 ( 3, 2) [000269] ------------ arg1 in rdx +--* LCL_VAR long V27 loc24 u:2 (last use) $493 N008 ( 3, 2) [000270] ------------ arg2 in r8 +--* LCL_VAR int V36 tmp6 u:2 (last use) $253 N009 ( 3, 2) [000271] ------------ arg3 in r9 \--* LCL_VAR int V25 loc22 u:3 (last use) $540 ReMorphing args for 273.CALL: argSlots=5, preallocatedArgCount=5, nextSlotNum=5, nextSlotByteOffset=40, outgoingArgSpaceSize=40 ArgTable for 273.CALL after fgMorphArgs: fgArgTabEntry[arg 0 268.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed] fgArgTabEntry[arg 1 269.LCL_VAR long (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=1, processed] fgArgTabEntry[arg 2 270.LCL_VAR int (By ref), 1 reg: r8, byteAlignment=8, lateArgInx=2, processed] fgArgTabEntry[arg 3 271.LCL_VAR int (By ref), 1 reg: r9, byteAlignment=8, lateArgInx=3, processed] fgArgTabEntry[arg 4 272.LCL_VAR byref (By ref), numSlots=1, slotNum=4, byteSize=8, byteOffset=32, byteAlignment=8, processed] optAssertionPropMain morphed tree: N012 ( 28, 18) [000853] -ACXG---R--- * ASG int $2be N011 ( 1, 1) [000852] D------N---- +--* LCL_VAR int V51 tmp21 d:4 $2be N010 ( 28, 18) [000273] --CXG------- \--* CALL int FloatingPointType.AssembleFloatingPointValue $2be N005 ( 1, 1) [000272] ------------ arg4 out+20 +--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N006 ( 1, 1) [000268] ------------ this in rcx +--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 N007 ( 3, 2) [000269] ------------ arg1 in rdx +--* LCL_VAR long V27 loc24 u:2 (last use) $493 N008 ( 3, 2) [000270] ------------ arg2 in r8 +--* LCL_VAR int V36 tmp6 u:2 (last use) $253 N009 ( 3, 2) [000271] ------------ arg3 in r9 \--* LCL_VAR int V25 loc22 u:3 (last use) $540 Propagating 000000000000048F assertions for BB44, stmt STMT00109, tree [000522], tree -> 0 Propagating 000000000000048F assertions for BB44, stmt STMT00109, tree [000523], tree -> 0 *************** In fgDebugCheckBBlist *************** Finishing PHASE Assertion prop *************** Starting PHASE Optimize index checks *************** In OptimizeRangeChecks() Blocks/trees before phase ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0056] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..00D)-> BB04 ( cond ) i label target idxlen BB03 [0001] 1 BB02 0.50 [00D..017) (return) i hascall gcsafe BB04 [0002] 1 BB02 0.50 [017..065)-> BB06 ( cond ) i label target hascall gcsafe BB05 [0038] 1 BB04 0.50 [020..021)-> BB07 (always) i gcsafe BB06 [0039] 1 BB04 0.50 [020..021) i label target gcsafe BB07 [0040] 2 BB05,BB06 0.50 [000..000)-> BB09 ( cond ) i internal label target gcsafe idxlen BB08 [0043] 1 BB07 0.50 [000..000)-> BB10 (always) i internal gcsafe BB09 [0044] 1 BB07 0.50 [000..000) i internal label target gcsafe BB10 [0045] 2 BB08,BB09 0.50 [???..???)-> BB14 ( cond ) i internal label target hascall gcsafe idxlen BB11 [0003] 1 BB10 0.50 [065..070)-> BB13 ( cond ) i hascall gcsafe BB12 [0004] 1 BB11 0.50 [070..07A) (return) i hascall gcsafe BB13 [0005] 1 BB11 0.50 [07A..082) i label target hascall gcsafe BB14 [0006] 2 BB10,BB13 0.50 [082..092)-> BB16 ( cond ) i label target hascall gcsafe BB15 [0007] 1 BB14 0.50 [092..096)-> BB17 ( cond ) i gcsafe BB16 [0008] 2 BB14,BB15 0.50 [096..0A7)-> BB44 (always) i label target hascall gcsafe BB17 [0009] 1 BB15 0.50 [0A7..0B0)-> BB19 ( cond ) i label target gcsafe BB18 [0010] 1 BB17 0.50 [0B0..0B4)-> BB20 (always) i gcsafe BB19 [0011] 1 BB17 0.50 [0B4..0BE) i label target gcsafe BB20 [0012] 2 BB18,BB19 0.50 [0BE..0C4)-> BB23 ( cond ) i label target gcsafe BB21 [0013] 1 BB20 0.50 [0C4..0D9)-> BB23 ( cond ) i hascall gcsafe idxlen BB22 [0014] 1 BB21 0.50 [0D9..0E3) (return) i hascall gcsafe BB23 [0015] 2 BB20,BB21 0.50 [0E3..117)-> BB25 ( cond ) i label target hascall gcsafe BB24 [0016] 1 BB23 0.50 [117..11A)-> BB26 (always) i gcsafe BB25 [0017] 1 BB23 0.50 [11A..11F) i label target gcsafe BB26 [0018] 2 BB24,BB25 0.50 [11F..126)-> BB28 ( cond ) i label target gcsafe BB27 [0019] 1 BB26 0.50 [126..12F) i hascall gcsafe BB28 [0020] 2 BB26,BB27 0.50 [12F..13E)-> BB32 ( cond ) i label target gcsafe BB29 [0021] 1 BB28 0.50 [13E..144)-> BB31 ( cond ) i gcsafe BB30 [0022] 1 BB29 0.50 [144..155)-> BB44 (always) i hascall gcsafe BB31 [0023] 1 BB29 0.50 [155..15C) i label target gcsafe BB32 [0024] 2 BB28,BB31 0.50 [15C..167)-> BB34 ( cond ) i label target hascall gcsafe BB33 [0025] 1 BB32 0.50 [167..16B)-> BB35 (always) i gcsafe BB34 [0026] 1 BB32 0.50 [16B..16F) i label target gcsafe BB35 [0027] 2 BB33,BB34 0.50 [16F..1A4)-> BB40 ( cond ) i label target hascall gcsafe BB36 [0028] 1 BB35 0.50 [1A4..1AF)-> BB38 ( cond ) i gcsafe BB37 [0029] 1 BB36 0.50 [1AF..1C3)-> BB39 (always) i gcsafe BB38 [0030] 1 BB36 0.50 [1C3..1C4) i label target gcsafe BB39 [0031] 2 BB37,BB38 0.50 [1C4..1D0) i label target gcsafe BB40 [0032] 2 BB35,BB39 0.50 [1D0..1E7)-> BB42 ( cond ) i label target hascall gcsafe BB41 [0033] 1 BB40 0.50 [1E7..1EE)-> BB43 (always) i gcsafe BB42 [0034] 1 BB40 0.50 [1EE..1F2) i label target gcsafe BB43 [0035] 2 BB41,BB42 0.50 [1F2..202) i label target hascall gcsafe BB44 [0054] 3 BB16,BB30,BB43 0.50 [???..???) (return) keep internal target gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} ***** BB01 STMT00111 (IL ???... ???) N011 ( 7, 7) [000540] -A---------- * COMMA void N004 ( 3, 3) [000533] -A------R--- +--* ASG ref N003 ( 1, 1) [000530] D------N---- | +--* LCL_VAR ref V52 tmp22 d:2 N002 ( 3, 2) [000532] n----------- | \--* IND ref N001 ( 1, 1) [000531] ------------ | \--* LCL_VAR byref V00 arg0 u:1 Zero Fseq[Mantissa] $80 N010 ( 4, 4) [000539] -A------R--- \--* ASG int N009 ( 1, 1) [000534] D------N---- +--* LCL_VAR int V53 tmp23 d:2 N008 ( 4, 4) [000538] n----------- \--* IND int N007 ( 2, 2) [000537] -------N---- \--* ADD byref $200 N005 ( 1, 1) [000535] ------------ +--* LCL_VAR byref V00 arg0 u:1 (last use) $80 N006 ( 1, 1) [000536] ------------ \--* CNS_INT long 8 Fseq[Exponent] $101 ------------ BB02 [000..00D) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00000 (IL 0x000...0x00B) N005 ( 7, 7) [000006] ---XG------- * JTRUE void N004 ( 5, 5) [000005] J--XG--N---- \--* NE int N002 ( 3, 3) [000003] ---XG------- +--* ARR_LENGTH int N001 ( 1, 1) [000002] ------------ | \--* LCL_VAR ref V52 tmp22 u:2 N003 ( 1, 1) [000004] ------------ \--* CNS_INT int 0 $40 ------------ BB03 [00D..017) (return), preds={BB02} succs={} ***** BB03 STMT00087 (IL 0x00D...0x014) N006 ( 25, 13) [000403] -ACXG---R--- * ASG long $VN.Void N005 ( 3, 2) [000402] *--X---N---- +--* IND long $459 N004 ( 1, 1) [000399] ------------ | \--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N003 ( 21, 10) [000401] --CXG------- \--* CALLV ind long FloatingPointType.get_Zero $459 N002 ( 1, 1) [000400] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 ***** BB03 STMT00107 (IL ???... ???) N002 ( 2, 2) [000520] ------------ * RETURN int $5cb N001 ( 1, 1) [000404] ------------ \--* CNS_INT int 1 $41 ------------ BB04 [017..065) -> BB06 (cond), preds={BB02} succs={BB05,BB06} ***** BB04 STMT00002 (IL ???... ???) N010 ( 30, 19) [000013] -ACXG---R--- * ASG int $348 N009 ( 3, 2) [000012] D------N---- +--* LCL_VAR int V03 loc0 d:2 $348 N008 ( 26, 16) [000011] --CXG------- \--* ADD int $348 N006 ( 24, 14) [000409] --CXG------- +--* CAST int <- ushort <- int $347 N005 ( 23, 12) [000408] --CXG------- | \--* ADD int $346 N003 ( 21, 10) [000406] --CXG------- | +--* CALLV ind int FloatingPointType.get_DenormalMantissaBits $282 N002 ( 1, 1) [000007] ------------ this in rcx | | \--* LCL_VAR ref V01 arg1 u:1 $c0 N004 ( 1, 1) [000407] ------------ | \--* CNS_INT int 1 $41 N007 ( 1, 1) [000010] ------------ \--* CNS_INT int 1 $41 ***** BB04 STMT00092 (IL 0x020... ???) N003 ( 5, 4) [000424] -A--G---R--- * ASG int N002 ( 3, 2) [000423] D------N---- +--* LCL_VAR int V40 tmp10 d:2 N001 ( 1, 1) [000017] ------------ \--* LCL_VAR int V53 tmp23 u:2 ***** BB04 STMT00089 (IL 0x020... ???) N004 ( 5, 5) [000414] ------------ * JTRUE void N003 ( 3, 3) [000413] J------N---- \--* LE int N001 ( 1, 1) [000412] ------------ +--* LCL_VAR int V40 tmp10 u:2 N002 ( 1, 1) [000411] ------------ \--* CNS_INT int 0 $40 ------------ BB05 [020..021) -> BB07 (always), preds={BB04} succs={BB07} ***** BB05 STMT00091 (IL 0x020... ???) N003 ( 7, 5) [000421] -A------R--- * ASG int N002 ( 3, 2) [000420] D------N---- +--* LCL_VAR int V39 tmp9 d:4 N001 ( 3, 2) [000419] ------------ \--* LCL_VAR int V53 tmp23 u:2 (last use) ------------ BB06 [020..021), preds={BB04} succs={BB07} ***** BB06 STMT00090 (IL 0x020... ???) N003 ( 5, 4) [000417] -A------R--- * ASG int $40 N002 ( 3, 2) [000416] D------N---- +--* LCL_VAR int V39 tmp9 d:3 $40 N001 ( 1, 1) [000415] ------------ \--* CNS_INT int 0 $40 ------------ BB07 [000..000) -> BB09 (cond), preds={BB05,BB06} succs={BB08,BB09} ***** BB07 STMT00122 (IL ???... ???) N005 ( 0, 0) [000886] -A------R--- * ASG int N004 ( 0, 0) [000884] D------N---- +--* LCL_VAR int V39 tmp9 d:2 N003 ( 0, 0) [000885] ------------ \--* PHI int N001 ( 0, 0) [000909] ------------ pred BB05 +--* PHI_ARG int V39 tmp9 u:4 N002 ( 0, 0) [000908] ------------ pred BB06 \--* PHI_ARG int V39 tmp9 u:3 $40 ***** BB07 STMT00004 (IL ???... ???) N003 ( 3, 3) [000021] -A------R--- * ASG int $241 N002 ( 1, 1) [000020] D------N---- +--* LCL_VAR int V31 tmp1 d:2 $241 N001 ( 3, 2) [000422] ------------ \--* LCL_VAR int V39 tmp9 u:2 $241 ***** BB07 STMT00096 (IL ???... ???) N004 ( 3, 3) [000443] -A-XG---R--- * ASG int N003 ( 1, 1) [000442] D------N---- +--* LCL_VAR int V42 tmp12 d:2 N002 ( 3, 3) [000429] ---XG------- \--* ARR_LENGTH int N001 ( 1, 1) [000428] ------------ \--* LCL_VAR ref V52 tmp22 u:2 ***** BB07 STMT00093 (IL ???... ???) N004 ( 7, 6) [000433] ------------ * JTRUE void N003 ( 5, 4) [000432] N------N-U-- \--* LE int N001 ( 3, 2) [000023] ------------ +--* LCL_VAR int V31 tmp1 u:2 (last use) $241 N002 ( 1, 1) [000431] ------------ \--* LCL_VAR int V42 tmp12 u:2 ------------ BB08 [000..000) -> BB10 (always), preds={BB07} succs={BB10} ***** BB08 STMT00095 (IL ???... ???) N003 ( 1, 3) [000440] -A------R--- * ASG int N002 ( 1, 1) [000439] D------N---- +--* LCL_VAR int V41 tmp11 d:4 N001 ( 1, 1) [000438] ------------ \--* LCL_VAR int V42 tmp12 u:2 (last use) ------------ BB09 [000..000), preds={BB07} succs={BB10} ***** BB09 STMT00094 (IL ???... ???) N003 ( 1, 3) [000436] -A------R--- * ASG int $241 N002 ( 1, 1) [000435] D------N---- +--* LCL_VAR int V41 tmp11 d:3 $241 N001 ( 1, 1) [000434] ------------ \--* LCL_VAR int V31 tmp1 u:2 $241 ------------ BB10 [???..???) -> BB14 (cond), preds={BB08,BB09} succs={BB11,BB14} ***** BB10 STMT00121 (IL ???... ???) N005 ( 0, 0) [000883] -A------R--- * ASG int N004 ( 0, 0) [000881] D------N---- +--* LCL_VAR int V41 tmp11 d:2 N003 ( 0, 0) [000882] ------------ \--* PHI int N001 ( 0, 0) [000907] ------------ pred BB08 +--* PHI_ARG int V41 tmp11 u:4 N002 ( 0, 0) [000906] ------------ pred BB09 \--* PHI_ARG int V41 tmp11 u:3 $241 ***** BB10 STMT00008 (IL ???...0x03C) N005 ( 7, 6) [000035] -A------R--- * ASG int $34e N004 ( 3, 2) [000034] D------N---- +--* LCL_VAR int V05 loc2 d:2 $34e N003 ( 3, 3) [000033] ------------ \--* SUB int $34e N001 ( 1, 1) [000022] ------------ +--* LCL_VAR int V31 tmp1 u:2 (last use) $241 N002 ( 1, 1) [000032] ------------ \--* LCL_VAR int V41 tmp11 u:2 $242 ***** BB10 STMT00011 (IL 0x042...0x044) N003 ( 5, 4) [000044] -A------R--- * ASG int $242 N002 ( 3, 2) [000043] D------N---- +--* LCL_VAR int V08 loc5 d:2 $242 N001 ( 1, 1) [000042] ------------ \--* LCL_VAR int V41 tmp11 u:2 $242 ***** BB10 STMT00013 (IL ???... ???) N004 ( 7, 6) [000050] -A-XG---R--- * ASG int N003 ( 3, 2) [000049] D------N---- +--* LCL_VAR int V09 loc6 d:2 N002 ( 3, 3) [000448] ---XG------- \--* ARR_LENGTH int N001 ( 1, 1) [000447] ------------ \--* LCL_VAR ref V52 tmp22 u:2 ***** BB10 STMT00014 (IL 0x04F...0x054) N005 ( 5, 4) [000055] -A------R--- * ASG int N004 ( 1, 1) [000054] D------N---- +--* LCL_VAR int V10 loc7 d:2 N003 ( 5, 4) [000053] ------------ \--* SUB int N001 ( 3, 2) [000051] ------------ +--* LCL_VAR int V09 loc6 u:2 N002 ( 1, 1) [000052] ------------ \--* LCL_VAR int V08 loc5 u:2 $242 ***** BB10 STMT00016 (IL ???... ???) N028 ( 49, 35) [000059] SACXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger $VN.Void N004 ( 7, 6) [000563] -A------R-L- arg0 SETUP +--* ASG long $400 N003 ( 3, 2) [000562] D------N---- | +--* LCL_VAR long V75 tmp45 d:2 $400 N002 ( 3, 3) [000064] ------------ | \--* ADDR long $400 N001 ( 3, 2) [000063] ----G--N---- | \--* LCL_VAR struct(AX)(P) V11 loc8 | \--* ref V11._bits (offs=0x00) -> V54 tmp24 | \--* int V11._sign (offs=0x08) -> V55 tmp25 $3c0 N020 ( 14, 13) [000561] -A--------L- arg1 SETUP +--* COMMA void $VN.Void N013 ( 8, 7) [000554] -A---------- | +--* COMMA void $VN.Void N008 ( 3, 3) [000549] -A------R--- | | +--* ASG byref $401 N007 ( 1, 1) [000548] D------N---- | | | +--* LCL_VAR byref V74 tmp44 d:2 $401 N006 ( 3, 3) [000546] ------------ | | | \--* ADDR byref $401 N005 ( 3, 2) [000547] -------N---- | | | \--* LCL_VAR struct(AX) V73 tmp43 $3c1 N012 ( 5, 4) [000553] -A---------- | | \--* ASG ref $VN.Void N010 ( 3, 2) [000551] *------N---- | | +--* IND ref N009 ( 1, 1) [000550] ------------ | | | \--* LCL_VAR byref V74 tmp44 u:2 Zero Fseq[Mantissa] $401 N011 ( 1, 1) [000552] -------N---- | | \--* LCL_VAR ref V52 tmp22 u:2 N019 ( 6, 6) [000560] -A---------- | \--* ASG int $VN.Void N017 ( 4, 4) [000558] *------N---- | +--* IND int N016 ( 2, 2) [000557] -------N---- | | \--* ADD byref $203 N014 ( 1, 1) [000555] ------------ | | +--* LCL_VAR byref V74 tmp44 u:2 (last use) $401 N015 ( 1, 1) [000556] ------------ | | \--* CNS_INT long 8 Fseq[Exponent] $101 N018 ( 1, 1) [000559] -------N---- | \--* LCL_VAR int V53 tmp23 u:2 N023 ( 3, 2) [000564] ------------ arg0 in rcx +--* LCL_VAR long V75 tmp45 u:2 (last use) $400 N025 ( 3, 3) [000566] ------------ arg1 in rdx +--* ADDR byref $403 N024 ( 3, 2) [000565] -------N---- | \--* LCL_VAR struct(AX) V73 tmp43 $3c2 N026 ( 1, 1) [000058] ------------ arg3 in r9 +--* LCL_VAR int V08 loc5 u:2 (last use) $242 N027 ( 1, 1) [000057] ------------ arg2 in r8 \--* CNS_INT int 0 $40 ***** BB10 STMT00017 (IL 0x061...0x063) N004 ( 7, 6) [000068] ------------ * JTRUE void N003 ( 5, 4) [000067] N------N---- \--* EQ int $351 N001 ( 3, 2) [000065] ------------ +--* LCL_VAR int V05 loc2 u:2 $34e N002 ( 1, 1) [000066] ------------ \--* CNS_INT int 0 $40 ------------ BB11 [065..070) -> BB13 (cond), preds={BB10} succs={BB12,BB13} ***** BB11 STMT00083 (IL ???... ???) N008 ( 23, 17) [000387] --CXG------- * JTRUE void N007 ( 21, 15) [000386] J-CXG--N---- \--* GE int $352 N004 ( 16, 10) [000385] --CXG------- +--* CAST long <- int $480 N003 ( 15, 8) [000383] --CXG------- | \--* CALL int FloatingPointType.get_OverflowDecimalExponent $291 N002 ( 1, 1) [000382] ------------ this in rcx | \--* LCL_VAR ref V01 arg1 u:1 $c0 N006 ( 4, 4) [000381] ---------U-- \--* CAST long <- ulong <- uint $481 N005 ( 3, 2) [000380] ------------ \--* LCL_VAR int V05 loc2 u:2 $34e ------------ BB12 [070..07A) (return), preds={BB11} succs={} ***** BB12 STMT00085 (IL 0x070...0x077) N006 ( 25, 13) [000396] -ACXG---R--- * ASG long $VN.Void N005 ( 3, 2) [000395] *--X---N---- +--* IND long $458 N004 ( 1, 1) [000392] ------------ | \--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N003 ( 21, 10) [000394] --CXG------- \--* CALLV ind long FloatingPointType.get_Infinity $458 N002 ( 1, 1) [000393] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 ***** BB12 STMT00108 (IL ???... ???) N002 ( 2, 2) [000521] ------------ * RETURN int $5ca N001 ( 1, 1) [000397] ------------ \--* CNS_INT int 3 $48 ------------ BB13 [07A..082), preds={BB11} succs={BB14} ***** BB13 STMT00084 (IL 0x07A...0x07D) N006 ( 20, 12) [000391] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen $VN.Void N004 ( 3, 3) [000389] ------------ arg0 in rcx +--* ADDR long $404 N003 ( 3, 2) [000388] ----G--N---- | \--* LCL_VAR struct(AX)(P) V11 loc8 | \--* ref V11._bits (offs=0x00) -> V54 tmp24 | \--* int V11._sign (offs=0x08) -> V55 tmp25 $3c3 N005 ( 3, 2) [000390] ------------ arg1 in rdx \--* LCL_VAR int V05 loc2 u:2 (last use) $34e ------------ BB14 [082..092) -> BB16 (cond), preds={BB10,BB13} succs={BB15,BB16} ***** BB14 STMT00019 (IL ???... ???) N023 ( 41, 28) [000077] -ACXG---R--- * ASG int $293 N022 ( 1, 1) [000076] D------N---- +--* LCL_VAR int V13 loc10 d:2 $293 N021 ( 41, 28) [000072] -ACXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $293 N016 ( 18, 15) [000591] -A--G-----L- arg0 SETUP +--* COMMA void $VN.Void N009 ( 10, 8) [000584] -A--G------- | +--* COMMA void $VN.Void N004 ( 3, 3) [000579] -A------R--- | | +--* ASG byref $405 N003 ( 1, 1) [000578] D------N---- | | | +--* LCL_VAR byref V77 tmp47 d:2 $405 N002 ( 3, 3) [000576] ------------ | | | \--* ADDR byref $405 N001 ( 3, 2) [000577] -------N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 $3c4 N008 ( 7, 5) [000583] -A--G------- | | \--* ASG ref $VN.Void N006 ( 3, 2) [000581] *------N---- | | +--* IND ref $181 N005 ( 1, 1) [000580] ------------ | | | \--* LCL_VAR byref V77 tmp47 u:2 Zero Fseq[_bits] $405 N007 ( 3, 2) [000582] ----G--N---- | | \--* LCL_VAR ref (AX) V54 tmp24 $181 N015 ( 8, 7) [000590] -A--G------- | \--* ASG int $VN.Void N013 ( 4, 4) [000588] *------N---- | +--* IND int $243 N012 ( 2, 2) [000587] -------N---- | | \--* ADD byref $206 N010 ( 1, 1) [000585] ------------ | | +--* LCL_VAR byref V77 tmp47 u:2 (last use) $405 N011 ( 1, 1) [000586] ------------ | | \--* CNS_INT long 8 Fseq[_sign] $101 N014 ( 3, 2) [000589] ----G--N---- | \--* LCL_VAR int (AX) V55 tmp25 $243 N019 ( 3, 3) [000593] ------------ arg0 in rcx +--* ADDR byref $407 N018 ( 3, 2) [000592] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 $3c5 N020 ( 3, 3) [000071] ------------ arg1 in rdx \--* LCL_VAR_ADDR long V12 loc9 $443 ***** BB14 STMT00020 (IL 0x08D...0x090) N004 ( 7, 6) [000081] ------------ * JTRUE void N003 ( 5, 4) [000080] N------N-U-- \--* GE int $353 N001 ( 1, 1) [000078] ------------ +--* LCL_VAR int V13 loc10 u:2 $293 N002 ( 3, 2) [000079] ------------ \--* LCL_VAR int V03 loc0 u:2 $348 ------------ BB15 [092..096) -> BB17 (cond), preds={BB14} succs={BB16,BB17} ***** BB15 STMT00022 (IL 0x092...0x094) N004 ( 5, 5) [000094] ------------ * JTRUE void N003 ( 3, 3) [000093] J------N---- \--* NE int N001 ( 1, 1) [000091] ------------ +--* LCL_VAR int V10 loc7 u:2 N002 ( 1, 1) [000092] ------------ \--* CNS_INT int 0 $40 ------------ BB16 [096..0A7) -> BB44 (always), preds={BB14,BB15} succs={BB44} ***** BB16 STMT00021 (IL 0x096...0x0A6) N014 ( 29, 17) [000600] -ACXG---R--- * ASG int $5c7 N013 ( 1, 1) [000599] D------N---- +--* LCL_VAR int V51 tmp21 d:3 $5c7 N012 ( 29, 17) [000089] --CXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits $5c7 N005 ( 1, 1) [000088] ------------ arg4 out+20 +--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N008 ( 6, 3) [000086] N----------- arg2 in r8 +--* NE int N006 ( 1, 1) [000084] ------------ | +--* LCL_VAR int V10 loc7 u:2 (last use) N007 ( 1, 1) [000085] ------------ | \--* CNS_INT int 0 $40 N009 ( 3, 2) [000082] ----G------- arg0 in rcx +--* LCL_VAR ref (AX) V12 loc9 $18d N010 ( 1, 1) [000083] ------------ arg1 in rdx +--* LCL_VAR int V13 loc10 u:2 (last use) $293 N011 ( 1, 1) [000087] ------------ arg3 in r9 \--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 ------------ BB17 [0A7..0B0) -> BB19 (cond), preds={BB15} succs={BB18,BB19} ***** BB17 STMT00023 (IL 0x0A7...0x0AE) N004 ( 5, 5) [000100] ----G------- * JTRUE void N003 ( 3, 3) [000099] J---G--N---- \--* LT int N001 ( 1, 1) [000097] ------------ +--* LCL_VAR int V53 tmp23 u:2 N002 ( 1, 1) [000098] ------------ \--* CNS_INT int 0 $40 ------------ BB18 [0B0..0B4) -> BB20 (always), preds={BB17} succs={BB20} ***** BB18 STMT00081 (IL 0x0B0...0x0B2) N003 ( 5, 4) [000378] -A------R--- * ASG int N002 ( 3, 2) [000377] D------N---- +--* LCL_VAR int V32 tmp2 d:4 N001 ( 1, 1) [000376] ------------ \--* LCL_VAR int V10 loc7 u:2 ------------ BB19 [0B4..0BE), preds={BB17} succs={BB20} ***** BB19 STMT00024 (IL 0x0B4...0x0BD) N005 ( 7, 6) [000108] -A--G---R--- * ASG int N004 ( 3, 2) [000107] D------N---- +--* LCL_VAR int V32 tmp2 d:3 N003 ( 3, 3) [000106] ----G------- \--* SUB int N001 ( 1, 1) [000101] ------------ +--* LCL_VAR int V10 loc7 u:2 N002 ( 1, 1) [000104] ------------ \--* LCL_VAR int V53 tmp23 u:2 ------------ BB20 [0BE..0C4) -> BB23 (cond), preds={BB18,BB19} succs={BB21,BB23} ***** BB20 STMT00120 (IL ???... ???) N005 ( 0, 0) [000880] -A------R--- * ASG int N004 ( 0, 0) [000878] D------N---- +--* LCL_VAR int V32 tmp2 d:2 N003 ( 0, 0) [000879] ------------ \--* PHI int N001 ( 0, 0) [000905] ------------ pred BB18 +--* PHI_ARG int V32 tmp2 u:4 N002 ( 0, 0) [000904] ------------ pred BB19 \--* PHI_ARG int V32 tmp2 u:3 ***** BB20 STMT00025 (IL ???...0x0BE) N003 ( 7, 5) [000112] -A------R--- * ASG int $244 N002 ( 3, 2) [000111] D------N---- +--* LCL_VAR int V14 loc11 d:2 $244 N001 ( 3, 2) [000110] ------------ \--* LCL_VAR int V32 tmp2 u:2 (last use) $244 ***** BB20 STMT00026 (IL 0x0C0...0x0C2) N004 ( 5, 5) [000116] ------------ * JTRUE void N003 ( 3, 3) [000115] J------N---- \--* NE int $35a N001 ( 1, 1) [000113] ------------ +--* LCL_VAR int V13 loc10 u:2 $293 N002 ( 1, 1) [000114] ------------ \--* CNS_INT int 0 $40 ------------ BB21 [0C4..0D9) -> BB23 (cond), preds={BB20} succs={BB22,BB23} ***** BB21 STMT00077 (IL ???... ???) N008 ( 13, 13) [000363] -A-XG---R--- * ASG long N007 ( 3, 2) [000362] D------N---- +--* LCL_VAR long V38 tmp8 d:2 N006 ( 9, 10) [000359] ---XG---R--- \--* SUB long N005 ( 4, 4) [000353] ---------U-- +--* CAST long <- ulong <- uint $486 N004 ( 3, 2) [000352] ------------ | \--* LCL_VAR int V14 loc11 u:2 $244 N003 ( 4, 5) [000358] ---XG------- \--* CAST long <- int N002 ( 3, 3) [000456] ---XG------- \--* ARR_LENGTH int N001 ( 1, 1) [000455] ------------ \--* LCL_VAR ref V52 tmp22 u:2 ***** BB21 STMT00078 (IL ???... ???) N007 ( 22, 15) [000368] --CXG------- * JTRUE void N006 ( 20, 13) [000367] J-CXG--N---- \--* GE int N004 ( 16, 10) [000366] --CXG------- +--* CAST long <- int $48b N003 ( 15, 8) [000361] --CXG------- | \--* CALL int FloatingPointType.get_OverflowDecimalExponent $298 N002 ( 1, 1) [000360] ------------ this in rcx | \--* LCL_VAR ref V01 arg1 u:1 $c0 N005 ( 3, 2) [000364] ------------ \--* LCL_VAR long V38 tmp8 u:2 (last use) ------------ BB22 [0D9..0E3) (return), preds={BB21} succs={} ***** BB22 STMT00079 (IL 0x0D9...0x0E0) N006 ( 25, 13) [000373] -ACXG---R--- * ASG long $VN.Void N005 ( 3, 2) [000372] *--X---N---- +--* IND long $457 N004 ( 1, 1) [000369] ------------ | \--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N003 ( 21, 10) [000371] --CXG------- \--* CALLV ind long FloatingPointType.get_Zero $457 N002 ( 1, 1) [000370] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 ***** BB22 STMT00110 (IL ???... ???) N002 ( 2, 2) [000524] ------------ * RETURN int $5c4 N001 ( 1, 1) [000374] ------------ \--* CNS_INT int 2 $42 ------------ BB23 [0E3..117) -> BB25 (cond), preds={BB20,BB21} succs={BB24,BB25} ***** BB23 STMT00028 (IL ???... ???) N028 ( 53, 37) [000120] SACXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger $VN.Void N004 ( 7, 6) [000623] -A------R-L- arg0 SETUP +--* ASG long $408 N003 ( 3, 2) [000622] D------N---- | +--* LCL_VAR long V79 tmp49 d:2 $408 N002 ( 3, 3) [000125] ------------ | \--* ADDR long $408 N001 ( 3, 2) [000124] ----G--N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 $3c6 N020 ( 14, 13) [000621] -A--------L- arg1 SETUP +--* COMMA void $VN.Void N013 ( 8, 7) [000614] -A---------- | +--* COMMA void $VN.Void N008 ( 3, 3) [000609] -A------R--- | | +--* ASG byref $409 N007 ( 1, 1) [000608] D------N---- | | | +--* LCL_VAR byref V78 tmp48 d:2 $409 N006 ( 3, 3) [000606] ------------ | | | \--* ADDR byref $409 N005 ( 3, 2) [000607] ----G--N---- | | | \--* LCL_VAR struct(AX) V73 tmp43 $3c7 N012 ( 5, 4) [000613] -A---------- | | \--* ASG ref $VN.Void N010 ( 3, 2) [000611] *------N---- | | +--* IND ref N009 ( 1, 1) [000610] ------------ | | | \--* LCL_VAR byref V78 tmp48 u:2 Zero Fseq[Mantissa] $409 N011 ( 1, 1) [000612] -------N---- | | \--* LCL_VAR ref V52 tmp22 u:2 (last use) N019 ( 6, 6) [000620] -A---------- | \--* ASG int $VN.Void N017 ( 4, 4) [000618] *------N---- | +--* IND int N016 ( 2, 2) [000617] -------N---- | | \--* ADD byref $209 N014 ( 1, 1) [000615] ------------ | | +--* LCL_VAR byref V78 tmp48 u:2 (last use) $409 N015 ( 1, 1) [000616] ------------ | | \--* CNS_INT long 8 Fseq[Exponent] $101 N018 ( 1, 1) [000619] -------N---- | \--* LCL_VAR int V53 tmp23 u:2 (last use) N023 ( 3, 2) [000624] ------------ arg0 in rcx +--* LCL_VAR long V79 tmp49 u:2 (last use) $408 N025 ( 3, 3) [000626] ------------ arg1 in rdx +--* ADDR byref $40b N024 ( 3, 2) [000625] -------N---- | \--* LCL_VAR struct(AX) V73 tmp43 $3c8 N026 ( 3, 2) [000118] ------------ arg2 in r8 +--* LCL_VAR int V08 loc5 u:2 (last use) $242 N027 ( 3, 2) [000119] ------------ arg3 in r9 \--* LCL_VAR int V09 loc6 u:2 (last use) ***** BB23 STMT00029 (IL 0x0EF...0x0F4) N005 ( 17, 21) [000133] H-CXG------- * CALL help long HELPER.CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE $48d N003 ( 2, 10) [000131] ------------ arg0 in rcx +--* CNS_INT long 0x7ff815262aa0 $102 N004 ( 1, 4) [000132] ------------ arg1 in rdx \--* CNS_INT int 173 $58 ***** BB23 STMT00030 (IL ???... ???) N018 ( 21, 26) [000649] -A-XG------- * COMMA void N011 ( 13, 19) [000642] -A-XG------- +--* COMMA void N006 ( 6, 14) [000637] -A--G---R--- | +--* ASG byref N005 ( 1, 1) [000636] D------N---- | | +--* LCL_VAR byref V80 tmp50 d:2 N004 ( 6, 14) [000632] ----G------- | | \--* ADD byref N002 ( 4, 12) [000633] n---G------- | | +--* IND ref N001 ( 2, 10) [000634] I----------- | | | \--* CNS_INT(h) long 0xd1ffab1e static Fseq[BigOne] $4c2 N003 ( 1, 1) [000635] ------------ | | \--* CNS_INT long 8 Fseq[#FirstElem] $101 N010 ( 7, 5) [000641] -A-XG---R--- | \--* ASG ref N009 ( 3, 2) [000638] D---G--N---- | +--* LCL_VAR ref (AX) V58 tmp28 N008 ( 3, 2) [000640] ---X-------- | \--* IND ref N007 ( 1, 1) [000639] ------------ | \--* LCL_VAR byref V80 tmp50 u:2 Zero Fseq[_bits] N017 ( 8, 7) [000648] -A-XG---R--- \--* ASG int N016 ( 3, 2) [000643] D---G--N---- +--* LCL_VAR int (AX) V59 tmp29 N015 ( 4, 4) [000647] ---X-------- \--* IND int N014 ( 2, 2) [000646] -------N---- \--* ADD byref N012 ( 1, 1) [000644] ------------ +--* LCL_VAR byref V80 tmp50 u:2 (last use) N013 ( 1, 1) [000645] ------------ \--* CNS_INT long 8 Fseq[_sign] $101 ***** BB23 STMT00031 (IL 0x0F6...0x106) N006 ( 20, 12) [000141] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen $VN.Void N004 ( 3, 3) [000139] ------------ arg0 in rcx +--* ADDR long $40d N003 ( 3, 2) [000138] ----G--N---- | \--* LCL_VAR struct(AX)(P) V16 loc13 | \--* ref V16._bits (offs=0x00) -> V58 tmp28 | \--* int V16._sign (offs=0x08) -> V59 tmp29 $3c9 N005 ( 3, 2) [000140] ------------ arg1 in rdx \--* LCL_VAR int V14 loc11 u:2 (last use) $244 ***** BB23 STMT00099 (IL 0x0FF... ???) N007 ( 14, 10) [000658] -A--G------- * COMMA void $246 N003 ( 7, 5) [000654] -A--G---R--- +--* ASG ref $184 N002 ( 3, 2) [000652] D------N---- | +--* LCL_VAR ref V64 tmp34 d:2 $184 N001 ( 3, 2) [000653] ----G--N---- | \--* LCL_VAR ref (AX) V56 tmp26 $184 N006 ( 7, 5) [000657] -A--G---R--- \--* ASG int $246 N005 ( 3, 2) [000655] D------N---- +--* LCL_VAR int V65 tmp35 d:2 $246 N004 ( 3, 2) [000656] ----G--N---- \--* LCL_VAR int (AX) V57 tmp27 $246 ***** BB23 STMT00098 (IL 0x0FF... ???) N023 ( 45, 31) [000468] -ACXG---R--- * ASG int $29f N022 ( 3, 2) [000467] D------N---- +--* LCL_VAR int V43 tmp13 d:2 $29f N021 ( 41, 28) [000463] -ACXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $29f N016 ( 18, 15) [000677] -A--------L- arg0 SETUP +--* COMMA void $VN.Void N009 ( 10, 8) [000670] -A---------- | +--* COMMA void $VN.Void N004 ( 3, 3) [000665] -A------R--- | | +--* ASG byref $40e N003 ( 1, 1) [000664] D------N---- | | | +--* LCL_VAR byref V81 tmp51 d:2 $40e N002 ( 3, 3) [000662] ------------ | | | \--* ADDR byref $40e N001 ( 3, 2) [000663] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 $3ca N008 ( 7, 5) [000669] -A---------- | | \--* ASG ref $VN.Void N006 ( 3, 2) [000667] *------N---- | | +--* IND ref $184 N005 ( 1, 1) [000666] ------------ | | | \--* LCL_VAR byref V81 tmp51 u:2 Zero Fseq[_bits] $40e N007 ( 3, 2) [000668] -------N---- | | \--* LCL_VAR ref V64 tmp34 u:2 (last use) $184 N015 ( 8, 7) [000676] -A---------- | \--* ASG int $VN.Void N013 ( 4, 4) [000674] *------N---- | +--* IND int $246 N012 ( 2, 2) [000673] -------N---- | | \--* ADD byref $211 N010 ( 1, 1) [000671] ------------ | | +--* LCL_VAR byref V81 tmp51 u:2 (last use) $40e N011 ( 1, 1) [000672] ------------ | | \--* CNS_INT long 8 Fseq[_sign] $101 N014 ( 3, 2) [000675] -------N---- | \--* LCL_VAR int V65 tmp35 u:2 (last use) $246 N019 ( 3, 3) [000679] ------------ arg0 in rcx +--* ADDR byref $410 N018 ( 3, 2) [000678] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 $3cb N020 ( 3, 3) [000462] ------------ arg1 in rdx \--* LCL_VAR_ADDR long V45 tmp15 $449 ***** BB23 STMT00100 (IL 0x0FF... ???) N003 ( 5, 4) [000475] -A--G---R--- * ASG ref $VN.Null N002 ( 3, 2) [000474] D---G--N---- +--* LCL_VAR ref (AX) V45 tmp15 N001 ( 1, 1) [000473] ------------ \--* CNS_INT ref null $VN.Null ***** BB23 STMT00033 (IL ???... ???) N003 ( 7, 5) [000148] -A------R--- * ASG int $29f N002 ( 3, 2) [000147] D------N---- +--* LCL_VAR int V17 loc14 d:2 $29f N001 ( 3, 2) [000469] ------------ \--* LCL_VAR int V43 tmp13 u:2 $29f ***** BB23 STMT00103 (IL 0x108... ???) N007 ( 14, 10) [000687] -A--G------- * COMMA void $247 N003 ( 7, 5) [000683] -A--G---R--- +--* ASG ref $185 N002 ( 3, 2) [000681] D------N---- | +--* LCL_VAR ref V66 tmp36 d:2 $185 N001 ( 3, 2) [000682] ----G--N---- | \--* LCL_VAR ref (AX) V58 tmp28 $185 N006 ( 7, 5) [000686] -A--G---R--- \--* ASG int $247 N005 ( 3, 2) [000684] D------N---- +--* LCL_VAR int V67 tmp37 d:2 $247 N004 ( 3, 2) [000685] ----G--N---- \--* LCL_VAR int (AX) V59 tmp29 $247 ***** BB23 STMT00102 (IL 0x108... ???) N023 ( 45, 31) [000486] -ACXG---R--- * ASG int $2a3 N022 ( 3, 2) [000485] D------N---- +--* LCL_VAR int V46 tmp16 d:2 $2a3 N021 ( 41, 28) [000481] -ACXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $2a3 N016 ( 18, 15) [000706] -A--------L- arg0 SETUP +--* COMMA void $VN.Void N009 ( 10, 8) [000699] -A---------- | +--* COMMA void $VN.Void N004 ( 3, 3) [000694] -A------R--- | | +--* ASG byref $411 N003 ( 1, 1) [000693] D------N---- | | | +--* LCL_VAR byref V82 tmp52 d:2 $411 N002 ( 3, 3) [000691] ------------ | | | \--* ADDR byref $411 N001 ( 3, 2) [000692] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 $3cc N008 ( 7, 5) [000698] -A---------- | | \--* ASG ref $VN.Void N006 ( 3, 2) [000696] *------N---- | | +--* IND ref $185 N005 ( 1, 1) [000695] ------------ | | | \--* LCL_VAR byref V82 tmp52 u:2 Zero Fseq[_bits] $411 N007 ( 3, 2) [000697] -------N---- | | \--* LCL_VAR ref V66 tmp36 u:2 (last use) $185 N015 ( 8, 7) [000705] -A---------- | \--* ASG int $VN.Void N013 ( 4, 4) [000703] *------N---- | +--* IND int $247 N012 ( 2, 2) [000702] -------N---- | | \--* ADD byref $214 N010 ( 1, 1) [000700] ------------ | | +--* LCL_VAR byref V82 tmp52 u:2 (last use) $411 N011 ( 1, 1) [000701] ------------ | | \--* CNS_INT long 8 Fseq[_sign] $101 N014 ( 3, 2) [000704] -------N---- | \--* LCL_VAR int V67 tmp37 u:2 (last use) $247 N019 ( 3, 3) [000708] ------------ arg0 in rcx +--* ADDR byref $413 N018 ( 3, 2) [000707] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 $3cd N020 ( 3, 3) [000480] ------------ arg1 in rdx \--* LCL_VAR_ADDR long V48 tmp18 $44b ***** BB23 STMT00104 (IL 0x108... ???) N003 ( 5, 4) [000493] -A--G---R--- * ASG ref $VN.Null N002 ( 3, 2) [000492] D---G--N---- +--* LCL_VAR ref (AX) V48 tmp18 N001 ( 1, 1) [000491] ------------ \--* CNS_INT ref null $VN.Null ***** BB23 STMT00035 (IL ???... ???) N003 ( 7, 5) [000155] -A------R--- * ASG int $2a3 N002 ( 3, 2) [000154] D------N---- +--* LCL_VAR int V18 loc15 d:2 $2a3 N001 ( 3, 2) [000487] ------------ \--* LCL_VAR int V46 tmp16 u:2 $2a3 ***** BB23 STMT00036 (IL 0x111...0x115) N004 ( 9, 7) [000159] ------------ * JTRUE void N003 ( 7, 5) [000158] N------N-U-- \--* GT int $35f N001 ( 3, 2) [000156] ------------ +--* LCL_VAR int V18 loc15 u:2 (last use) $2a3 N002 ( 3, 2) [000157] ------------ \--* LCL_VAR int V17 loc14 u:2 (last use) $29f ------------ BB24 [117..11A) -> BB26 (always), preds={BB23} succs={BB26} ***** BB24 STMT00074 (IL 0x117...0x118) N003 ( 5, 4) [000350] -A------R--- * ASG int $40 N002 ( 3, 2) [000349] D------N---- +--* LCL_VAR int V33 tmp3 d:4 $40 N001 ( 1, 1) [000348] ------------ \--* CNS_INT int 0 $40 ------------ BB25 [11A..11F), preds={BB23} succs={BB26} ***** BB25 STMT00037 (IL 0x11A...0x11E) N005 ( 11, 8) [000164] -A------R--- * ASG int $360 N004 ( 3, 2) [000163] D------N---- +--* LCL_VAR int V33 tmp3 d:3 $360 N003 ( 7, 5) [000162] ------------ \--* SUB int $360 N001 ( 3, 2) [000160] ------------ +--* LCL_VAR int V18 loc15 u:2 (last use) $2a3 N002 ( 3, 2) [000161] ------------ \--* LCL_VAR int V17 loc14 u:2 (last use) $29f ------------ BB26 [11F..126) -> BB28 (cond), preds={BB24,BB25} succs={BB27,BB28} ***** BB26 STMT00119 (IL ???... ???) N005 ( 0, 0) [000877] -A------R--- * ASG int N004 ( 0, 0) [000875] D------N---- +--* LCL_VAR int V33 tmp3 d:2 N003 ( 0, 0) [000876] ------------ \--* PHI int N001 ( 0, 0) [000903] ------------ pred BB24 +--* PHI_ARG int V33 tmp3 u:4 $40 N002 ( 0, 0) [000902] ------------ pred BB25 \--* PHI_ARG int V33 tmp3 u:3 $360 ***** BB26 STMT00038 (IL ???...0x11F) N003 ( 3, 3) [000168] -A------R--- * ASG int $248 N002 ( 1, 1) [000167] D------N---- +--* LCL_VAR int V19 loc16 d:2 $248 N001 ( 3, 2) [000166] ------------ \--* LCL_VAR int V33 tmp3 u:2 $248 ***** BB26 STMT00039 (IL 0x121...0x124) N004 ( 7, 6) [000172] ------------ * JTRUE void N003 ( 5, 4) [000171] N------N---- \--* EQ int $361 N001 ( 3, 2) [000169] ------------ +--* LCL_VAR int V19 loc16 u:2 (last use) $248 N002 ( 1, 1) [000170] ------------ \--* CNS_INT int 0 $40 ------------ BB27 [126..12F), preds={BB26} succs={BB28} ***** BB27 STMT00073 (IL 0x126...0x12A) N006 ( 18, 11) [000347] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft $VN.Void N004 ( 3, 3) [000345] ------------ arg0 in rcx +--* ADDR long $414 N003 ( 3, 2) [000344] ----G--N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 $3ce N005 ( 1, 1) [000346] ------------ arg1 in rdx \--* LCL_VAR int V19 loc16 u:2 $248 ------------ BB28 [12F..13E) -> BB32 (cond), preds={BB26,BB27} succs={BB29,BB32} ***** BB28 STMT00040 (IL 0x12F...0x133) N005 ( 9, 7) [000177] -A------R--- * ASG int $362 N004 ( 3, 2) [000176] D------N---- +--* LCL_VAR int V20 loc17 d:2 $362 N003 ( 5, 4) [000175] ------------ \--* SUB int $362 N001 ( 3, 2) [000173] ------------ +--* LCL_VAR int V03 loc0 u:2 (last use) $348 N002 ( 1, 1) [000174] ------------ \--* LCL_VAR int V13 loc10 u:2 $293 ***** BB28 STMT00041 (IL 0x135...0x137) N003 ( 7, 5) [000180] -A------R--- * ASG int $362 N002 ( 3, 2) [000179] D------N---- +--* LCL_VAR int V21 loc18 d:2 $362 N001 ( 3, 2) [000178] ------------ \--* LCL_VAR int V20 loc17 u:2 $362 ***** BB28 STMT00042 (IL 0x139...0x13C) N004 ( 5, 5) [000184] ------------ * JTRUE void N003 ( 3, 3) [000183] N------N---- \--* EQ int $363 N001 ( 1, 1) [000181] ------------ +--* LCL_VAR int V13 loc10 u:2 $293 N002 ( 1, 1) [000182] ------------ \--* CNS_INT int 0 $40 ------------ BB29 [13E..144) -> BB31 (cond), preds={BB28} succs={BB30,BB31} ***** BB29 STMT00070 (IL 0x13E...0x142) N004 ( 7, 6) [000329] ------------ * JTRUE void N003 ( 5, 4) [000328] N------N-U-- \--* LE int $364 N001 ( 1, 1) [000326] ------------ +--* LCL_VAR int V19 loc16 u:2 $248 N002 ( 3, 2) [000327] ------------ \--* LCL_VAR int V20 loc17 u:2 $362 ------------ BB30 [144..155) -> BB44 (always), preds={BB29} succs={BB44} ***** BB30 STMT00072 (IL 0x144...0x154) N012 ( 24, 15) [000717] -ACXG---R--- * ASG int $5c2 N011 ( 1, 1) [000716] D------N---- +--* LCL_VAR int V51 tmp21 d:5 $5c2 N010 ( 24, 15) [000342] --CXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits $5c2 N005 ( 1, 1) [000341] ------------ arg4 out+20 +--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N006 ( 1, 1) [000339] ------------ arg2 in r8 +--* CNS_INT int 1 $41 N007 ( 3, 2) [000335] ----G------- arg0 in rcx +--* LCL_VAR ref (AX) V12 loc9 $18c N008 ( 1, 1) [000336] ------------ arg1 in rdx +--* LCL_VAR int V13 loc10 u:2 (last use) $293 N009 ( 1, 1) [000340] ------------ arg3 in r9 \--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 ------------ BB31 [155..15C), preds={BB29} succs={BB32} ***** BB31 STMT00071 (IL 0x155...0x15A) N005 ( 9, 7) [000334] -A------R--- * ASG int $365 N004 ( 3, 2) [000333] D------N---- +--* LCL_VAR int V21 loc18 d:4 $365 N003 ( 5, 4) [000332] ------------ \--* SUB int $365 N001 ( 3, 2) [000330] ------------ +--* LCL_VAR int V20 loc17 u:2 (last use) $362 N002 ( 1, 1) [000331] ------------ \--* LCL_VAR int V19 loc16 u:2 $248 ------------ BB32 [15C..167) -> BB34 (cond), preds={BB28,BB31} succs={BB33,BB34} ***** BB32 STMT00118 (IL ???... ???) N005 ( 0, 0) [000874] -A------R--- * ASG int N004 ( 0, 0) [000872] D------N---- +--* LCL_VAR int V21 loc18 d:3 N003 ( 0, 0) [000873] ------------ \--* PHI int N001 ( 0, 0) [000900] ------------ pred BB31 +--* PHI_ARG int V21 loc18 u:4 $365 N002 ( 0, 0) [000888] ------------ pred BB28 \--* PHI_ARG int V21 loc18 u:2 $362 ***** BB32 STMT00105 (IL 0x15C... ???) N007 ( 14, 10) [000724] -A--G------- * COMMA void $24a N003 ( 7, 5) [000720] -A--G---R--- +--* ASG ref $186 N002 ( 3, 2) [000718] D---G--N---- | +--* LCL_VAR ref (AX) V68 tmp38 N001 ( 3, 2) [000719] ----G--N---- | \--* LCL_VAR ref (AX) V56 tmp26 $186 N006 ( 7, 5) [000723] -A--G---R--- \--* ASG int $24a N005 ( 3, 2) [000721] D---G--N---- +--* LCL_VAR int (AX) V69 tmp39 N004 ( 3, 2) [000722] ----G--N---- \--* LCL_VAR int (AX) V57 tmp27 $24a ***** BB32 STMT00106 (IL 0x15C... ???) N007 ( 14, 10) [000731] -A--G------- * COMMA void $24b N003 ( 7, 5) [000727] -A--G---R--- +--* ASG ref $187 N002 ( 3, 2) [000725] D------N---- | +--* LCL_VAR ref V70 tmp40 d:2 $187 N001 ( 3, 2) [000726] ----G--N---- | \--* LCL_VAR ref (AX) V58 tmp28 $187 N006 ( 7, 5) [000730] -A--G---R--- \--* ASG int $24b N005 ( 3, 2) [000728] D------N---- +--* LCL_VAR int V71 tmp41 d:2 $24b N004 ( 3, 2) [000729] ----G--N---- \--* LCL_VAR int (AX) V59 tmp29 $24b ***** BB32 STMT00044 (IL ???... ???) N027 ( 52, 38) [000195] -ACXG------- * JTRUE void N026 ( 50, 36) [000503] JACXG--N---- \--* LT int $367 N024 ( 48, 34) [000499] -ACXG------- +--* CALL int System.Numerics.BigInteger.CompareTo $2ae N004 ( 7, 6) [000752] -A------R-L- this SETUP | +--* ASG byref $415 N003 ( 3, 2) [000751] D------N---- | | +--* LCL_VAR byref V84 tmp54 d:2 $415 N002 ( 3, 3) [000497] ------------ | | \--* ADDR byref $415 N001 ( 3, 2) [000496] ----G--N---- | | \--* LCL_VAR struct(AX)(P) V49 tmp19 | | \--* ref V49._bits (offs=0x00) -> V68 tmp38 | | \--* int V49._sign (offs=0x08) -> V69 tmp39 $3cf N020 ( 18, 15) [000750] -A--------L- arg1 SETUP | +--* COMMA void $VN.Void N013 ( 10, 8) [000743] -A---------- | | +--* COMMA void $VN.Void N008 ( 3, 3) [000738] -A------R--- | | | +--* ASG byref $417 N007 ( 1, 1) [000737] D------N---- | | | | +--* LCL_VAR byref V83 tmp53 d:2 $417 N006 ( 3, 3) [000735] ------------ | | | | \--* ADDR byref $417 N005 ( 3, 2) [000736] ----G--N---- | | | | \--* LCL_VAR struct(AX) V76 tmp46 $3d0 N012 ( 7, 5) [000742] -A---------- | | | \--* ASG ref $VN.Void N010 ( 3, 2) [000740] *------N---- | | | +--* IND ref $187 N009 ( 1, 1) [000739] ------------ | | | | \--* LCL_VAR byref V83 tmp53 u:2 Zero Fseq[_bits] $417 N011 ( 3, 2) [000741] -------N---- | | | \--* LCL_VAR ref V70 tmp40 u:2 (last use) $187 N019 ( 8, 7) [000749] -A---------- | | \--* ASG int $VN.Void N017 ( 4, 4) [000747] *------N---- | | +--* IND int $24b N016 ( 2, 2) [000746] -------N---- | | | \--* ADD byref $216 N014 ( 1, 1) [000744] ------------ | | | +--* LCL_VAR byref V83 tmp53 u:2 (last use) $417 N015 ( 1, 1) [000745] ------------ | | | \--* CNS_INT long 8 Fseq[_sign] $101 N018 ( 3, 2) [000748] -------N---- | | \--* LCL_VAR int V71 tmp41 u:2 (last use) $24b N021 ( 3, 2) [000753] ------------ this in rcx | +--* LCL_VAR byref V84 tmp54 u:2 (last use) $415 N023 ( 3, 3) [000755] ------------ arg1 in rdx | \--* ADDR byref $419 N022 ( 3, 2) [000754] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 $3d1 N025 ( 1, 1) [000502] ------------ \--* CNS_INT int 0 $40 ------------ BB33 [167..16B) -> BB35 (always), preds={BB32} succs={BB35} ***** BB33 STMT00069 (IL 0x167...0x169) N003 ( 5, 4) [000324] -A------R--- * ASG int $248 N002 ( 3, 2) [000323] D------N---- +--* LCL_VAR int V34 tmp4 d:4 $248 N001 ( 1, 1) [000322] ------------ \--* LCL_VAR int V19 loc16 u:2 (last use) $248 ------------ BB34 [16B..16F), preds={BB32} succs={BB35} ***** BB34 STMT00045 (IL 0x16B...0x16E) N005 ( 7, 6) [000200] -A------R--- * ASG int $368 N004 ( 3, 2) [000199] D------N---- +--* LCL_VAR int V34 tmp4 d:3 $368 N003 ( 3, 3) [000198] ------------ \--* ADD int $368 N001 ( 1, 1) [000196] ------------ +--* LCL_VAR int V19 loc16 u:2 (last use) $248 N002 ( 1, 1) [000197] ------------ \--* CNS_INT int 1 $41 ------------ BB35 [16F..1A4) -> BB40 (cond), preds={BB33,BB34} succs={BB36,BB40} ***** BB35 STMT00117 (IL ???... ???) N005 ( 0, 0) [000871] -A------R--- * ASG int N004 ( 0, 0) [000869] D------N---- +--* LCL_VAR int V34 tmp4 d:2 N003 ( 0, 0) [000870] ------------ \--* PHI int N001 ( 0, 0) [000899] ------------ pred BB33 +--* PHI_ARG int V34 tmp4 u:4 $248 N002 ( 0, 0) [000898] ------------ pred BB34 \--* PHI_ARG int V34 tmp4 u:3 $368 ***** BB35 STMT00046 (IL ???...0x16F) N003 ( 7, 5) [000204] -A------R--- * ASG int $24c N002 ( 3, 2) [000203] D------N---- +--* LCL_VAR int V22 loc19 d:2 $24c N001 ( 3, 2) [000202] ------------ \--* LCL_VAR int V34 tmp4 u:2 (last use) $24c ***** BB35 STMT00047 (IL 0x171...0x18A) N006 ( 20, 12) [000208] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft $VN.Void N004 ( 3, 3) [000206] ------------ arg0 in rcx +--* ADDR long $41a N003 ( 3, 2) [000205] ----G--N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 $3d2 N005 ( 3, 2) [000207] ------------ arg1 in rdx \--* LCL_VAR int V21 loc18 u:3 (last use) $249 ***** BB35 STMT00048 (IL 0x17A... ???) N045 ( 78, 56) [000213] SACXG------- * CALL void System.Numerics.BigInteger.DivRem $VN.Void N004 ( 7, 6) [000797] -A------R-L- arg0 SETUP +--* ASG long $41b N003 ( 3, 2) [000796] D------N---- | +--* LCL_VAR long V88 tmp58 d:2 $41b N002 ( 3, 3) [000220] ------------ | \--* ADDR long $41b N001 ( 3, 2) [000219] ----G--N---- | \--* LCL_VAR struct(AX)(P) V35 tmp5 | \--* ref V35._bits (offs=0x00) -> V62 tmp32 | \--* int V35._sign (offs=0x08) -> V63 tmp33 $3d3 N020 ( 18, 15) [000776] -A--G-----L- arg1 SETUP +--* COMMA void $VN.Void N013 ( 10, 8) [000769] -A--G------- | +--* COMMA void $VN.Void N008 ( 3, 3) [000764] -A------R--- | | +--* ASG byref $41c N007 ( 1, 1) [000763] D------N---- | | | +--* LCL_VAR byref V85 tmp55 d:2 $41c N006 ( 3, 3) [000761] ------------ | | | \--* ADDR byref $41c N005 ( 3, 2) [000762] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 $3d4 N012 ( 7, 5) [000768] -A--G------- | | \--* ASG ref $VN.Void N010 ( 3, 2) [000766] *------N---- | | +--* IND ref $188 N009 ( 1, 1) [000765] ------------ | | | \--* LCL_VAR byref V85 tmp55 u:2 Zero Fseq[_bits] $41c N011 ( 3, 2) [000767] ----G--N---- | | \--* LCL_VAR ref (AX) V56 tmp26 $188 N019 ( 8, 7) [000775] -A--G------- | \--* ASG int $VN.Void N017 ( 4, 4) [000773] *------N---- | +--* IND int $24d N016 ( 2, 2) [000772] -------N---- | | \--* ADD byref $218 N014 ( 1, 1) [000770] ------------ | | +--* LCL_VAR byref V85 tmp55 u:2 (last use) $41c N015 ( 1, 1) [000771] ------------ | | \--* CNS_INT long 8 Fseq[_sign] $101 N018 ( 3, 2) [000774] ----G--N---- | \--* LCL_VAR int (AX) V57 tmp27 $24d N036 ( 18, 15) [000795] -A--G-----L- arg2 SETUP +--* COMMA void $VN.Void N029 ( 10, 8) [000788] -A--G------- | +--* COMMA void $VN.Void N024 ( 3, 3) [000783] -A------R--- | | +--* ASG byref $41e N023 ( 1, 1) [000782] D------N---- | | | +--* LCL_VAR byref V87 tmp57 d:2 $41e N022 ( 3, 3) [000780] ------------ | | | \--* ADDR byref $41e N021 ( 3, 2) [000781] -------N---- | | | \--* LCL_VAR struct(AX) V86 tmp56 $3d5 N028 ( 7, 5) [000787] -A--G------- | | \--* ASG ref $VN.Void N026 ( 3, 2) [000785] *------N---- | | +--* IND ref $189 N025 ( 1, 1) [000784] ------------ | | | \--* LCL_VAR byref V87 tmp57 u:2 Zero Fseq[_bits] $41e N027 ( 3, 2) [000786] ----G--N---- | | \--* LCL_VAR ref (AX) V58 tmp28 $189 N035 ( 8, 7) [000794] -A--G------- | \--* ASG int $VN.Void N033 ( 4, 4) [000792] *------N---- | +--* IND int $24e N032 ( 2, 2) [000791] -------N---- | | \--* ADD byref $21a N030 ( 1, 1) [000789] ------------ | | +--* LCL_VAR byref V87 tmp57 u:2 (last use) $41e N031 ( 1, 1) [000790] ------------ | | \--* CNS_INT long 8 Fseq[_sign] $101 N034 ( 3, 2) [000793] ----G--N---- | \--* LCL_VAR int (AX) V59 tmp29 $24e N038 ( 3, 2) [000798] ------------ arg0 in rcx +--* LCL_VAR long V88 tmp58 u:2 (last use) $41b N040 ( 3, 3) [000800] ------------ arg1 in rdx +--* ADDR byref $420 N039 ( 3, 2) [000799] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 $3d6 N042 ( 3, 3) [000802] ------------ arg2 in r8 +--* ADDR byref $421 N041 ( 3, 2) [000801] -------N---- | \--* LCL_VAR struct(AX) V86 tmp56 $3d7 N044 ( 3, 3) [000212] ------------ arg3 in r9 \--* ADDR long $422 N043 ( 3, 2) [000211] ----G--N---- \--* LCL_VAR struct(AX)(P) V23 loc20 \--* ref V23._bits (offs=0x00) -> V60 tmp30 \--* int V23._sign (offs=0x08) -> V61 tmp31 $3d8 ***** BB35 STMT00050 (IL ???... ???) N021 ( 38, 24) [000226] -ACXG---R--- * ASG long $450 N020 ( 1, 1) [000225] D------N---- +--* LCL_VAR long V24 loc21 d:2 $450 N019 ( 38, 24) [000218] -ACXG------- \--* CALL long System.Numerics.BigInteger.op_Explicit $450 N016 ( 18, 15) [000822] -A--G-----L- arg0 SETUP +--* COMMA void $VN.Void N009 ( 10, 8) [000815] -A--G------- | +--* COMMA void $VN.Void N004 ( 3, 3) [000810] -A------R--- | | +--* ASG byref $423 N003 ( 1, 1) [000809] D------N---- | | | +--* LCL_VAR byref V89 tmp59 d:2 $423 N002 ( 3, 3) [000807] ------------ | | | \--* ADDR byref $423 N001 ( 3, 2) [000808] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 $3d9 N008 ( 7, 5) [000814] -A--G------- | | \--* ASG ref $VN.Void N006 ( 3, 2) [000812] *------N---- | | +--* IND ref $18a N005 ( 1, 1) [000811] ------------ | | | \--* LCL_VAR byref V89 tmp59 u:2 Zero Fseq[_bits] $423 N007 ( 3, 2) [000813] ----G--N---- | | \--* LCL_VAR ref (AX) V62 tmp32 $18a N015 ( 8, 7) [000821] -A--G------- | \--* ASG int $VN.Void N013 ( 4, 4) [000819] *------N---- | +--* IND int $24f N012 ( 2, 2) [000818] -------N---- | | \--* ADD byref $21d N010 ( 1, 1) [000816] ------------ | | +--* LCL_VAR byref V89 tmp59 u:2 (last use) $423 N011 ( 1, 1) [000817] ------------ | | \--* CNS_INT long 8 Fseq[_sign] $101 N014 ( 3, 2) [000820] ----G--N---- | \--* LCL_VAR int (AX) V63 tmp33 $24f N018 ( 3, 3) [000824] ------------ arg0 in rcx \--* ADDR byref $425 N017 ( 3, 2) [000823] -------N---- \--* LCL_VAR struct(AX) V76 tmp46 $3da ***** BB35 STMT00052 (IL ???... ???) N005 ( 12, 7) [000232] -A--G---R--- * ASG int $369 N004 ( 3, 2) [000231] D------N---- +--* LCL_VAR int V25 loc22 d:2 $369 N003 ( 8, 4) [000516] ----G------- \--* EQ int $369 N001 ( 3, 2) [000514] ----G------- +--* LCL_VAR int (AX) V61 tmp31 $250 N002 ( 1, 1) [000515] ------------ \--* CNS_INT int 0 $40 ***** BB35 STMT00054 (IL ???... ???) N005 ( 19, 10) [000237] -ACXG---R--- * ASG int $2b4 N004 ( 3, 2) [000236] D------N---- +--* LCL_VAR int V26 loc23 d:2 $2b4 N003 ( 15, 7) [000234] --CXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $2b4 N002 ( 1, 1) [000233] ------------ arg0 in rcx \--* LCL_VAR long V24 loc21 u:2 $450 ***** BB35 STMT00055 (IL 0x19E...0x1A2) N004 ( 9, 7) [000241] ------------ * JTRUE void N003 ( 7, 5) [000240] N------N-U-- \--* LE int $36a N001 ( 3, 2) [000238] ------------ +--* LCL_VAR int V26 loc23 u:2 $2b4 N002 ( 3, 2) [000239] ------------ \--* LCL_VAR int V20 loc17 u:2 $362 ------------ BB36 [1A4..1AF) -> BB38 (cond), preds={BB35} succs={BB37,BB38} ***** BB36 STMT00063 (IL 0x1A4...0x1A9) N005 ( 11, 8) [000286] -A------R--- * ASG int $36b N004 ( 3, 2) [000285] D------N---- +--* LCL_VAR int V29 loc26 d:2 $36b N003 ( 7, 5) [000284] ------------ \--* SUB int $36b N001 ( 3, 2) [000282] ------------ +--* LCL_VAR int V26 loc23 u:2 (last use) $2b4 N002 ( 3, 2) [000283] ------------ \--* LCL_VAR int V20 loc17 u:2 $362 ***** BB36 STMT00064 (IL 0x1AB...0x1AD) N004 ( 7, 6) [000290] ------------ * JTRUE void N003 ( 5, 4) [000289] J------N---- \--* EQ int $36c N001 ( 3, 2) [000287] ------------ +--* LCL_VAR int V25 loc22 u:2 (last use) $369 N002 ( 1, 1) [000288] ------------ \--* CNS_INT int 0 $40 ------------ BB37 [1AF..1C3) -> BB39 (always), preds={BB36} succs={BB39} ***** BB37 STMT00068 (IL 0x1AF...0x1C1) N013 ( 23, 15) [000320] -A------R--- * ASG int $36e N012 ( 3, 2) [000319] D------N---- +--* LCL_VAR int V37 tmp7 d:4 $36e N011 ( 19, 12) [000318] ------------ \--* EQ int $36e N009 ( 14, 10) [000315] ------------ +--* AND long $490 N001 ( 1, 1) [000305] ------------ | +--* LCL_VAR long V24 loc21 u:2 $450 N008 ( 12, 8) [000314] ------------ | \--* ADD long $48f N006 ( 10, 6) [000311] --------R--- | +--* LSH long $48e N005 ( 1, 1) [000307] ------------ | | +--* CNS_INT long 1 $103 N004 ( 5, 4) [000310] ------------ | | \--* AND int $36d N002 ( 3, 2) [000308] ------------ | | +--* LCL_VAR int V29 loc26 u:2 $36b N003 ( 1, 1) [000309] ------------ | | \--* CNS_INT int 63 $66 N007 ( 1, 1) [000313] ------------ | \--* CNS_INT long -1 $104 N010 ( 1, 1) [000317] ------------ \--* CNS_INT long 0 $100 ------------ BB38 [1C3..1C4), preds={BB36} succs={BB39} ***** BB38 STMT00065 (IL 0x1C3...0x1C3) N003 ( 5, 4) [000293] -A------R--- * ASG int $40 N002 ( 3, 2) [000292] D------N---- +--* LCL_VAR int V37 tmp7 d:3 $40 N001 ( 1, 1) [000291] ------------ \--* CNS_INT int 0 $40 ------------ BB39 [1C4..1D0), preds={BB37,BB38} succs={BB40} ***** BB39 STMT00116 (IL ???... ???) N005 ( 0, 0) [000868] -A------R--- * ASG int N004 ( 0, 0) [000866] D------N---- +--* LCL_VAR int V37 tmp7 d:2 N003 ( 0, 0) [000867] ------------ \--* PHI int N001 ( 0, 0) [000897] ------------ pred BB37 +--* PHI_ARG int V37 tmp7 u:4 $36e N002 ( 0, 0) [000896] ------------ pred BB38 \--* PHI_ARG int V37 tmp7 u:3 $40 ***** BB39 STMT00066 (IL ???...0x1C4) N004 ( 8, 7) [000297] -A------R--- * ASG int $36f N003 ( 3, 2) [000296] D------N---- +--* LCL_VAR int V25 loc22 d:4 $36f N002 ( 4, 4) [000826] ------------ \--* CAST int <- bool <- int $36f N001 ( 3, 2) [000295] ------------ \--* LCL_VAR int V37 tmp7 u:2 (last use) $251 ***** BB39 STMT00067 (IL 0x1C6...0x1CE) N007 ( 10, 6) [000304] -A------R--- * ASG long $491 N006 ( 1, 1) [000303] D------N---- +--* LCL_VAR long V24 loc21 d:4 $491 N005 ( 10, 6) [000302] ------------ \--* RSZ long $491 N001 ( 1, 1) [000298] ------------ +--* LCL_VAR long V24 loc21 u:2 (last use) $450 N004 ( 5, 4) [000301] ------------ \--* AND int $36d N002 ( 3, 2) [000299] ------------ +--* LCL_VAR int V29 loc26 u:2 (last use) $36b N003 ( 1, 1) [000300] ------------ \--* CNS_INT int 63 $66 ------------ BB40 [1D0..1E7) -> BB42 (cond), preds={BB35,BB39} succs={BB41,BB42} ***** BB40 STMT00115 (IL ???... ???) N005 ( 0, 0) [000865] -A------R--- * ASG bool N004 ( 0, 0) [000863] D------N---- +--* LCL_VAR bool V25 loc22 d:3 N003 ( 0, 0) [000864] ------------ \--* PHI bool N001 ( 0, 0) [000894] ------------ pred BB39 +--* PHI_ARG bool V25 loc22 u:4 $36f N002 ( 0, 0) [000889] ------------ pred BB35 \--* PHI_ARG bool V25 loc22 u:2 $369 ***** BB40 STMT00114 (IL ???... ???) N005 ( 0, 0) [000862] -A------R--- * ASG long N004 ( 0, 0) [000860] D------N---- +--* LCL_VAR long V24 loc21 d:3 N003 ( 0, 0) [000861] ------------ \--* PHI long N001 ( 0, 0) [000895] ------------ pred BB39 +--* PHI_ARG long V24 loc21 u:4 $491 N002 ( 0, 0) [000890] ------------ pred BB35 \--* PHI_ARG long V24 loc21 u:2 $450 ***** BB40 STMT00057 (IL ???... ???) N027 ( 53, 34) [000254] -ACXG---R--- * ASG long $493 N026 ( 3, 2) [000253] D------N---- +--* LCL_VAR long V27 loc24 d:2 $493 N025 ( 49, 31) [000252] -ACXG------- \--* ADD long $493 N023 ( 47, 29) [000250] -ACXG------- +--* LSH long $492 N019 ( 38, 24) [000243] -ACXG------- | +--* CALL long System.Numerics.BigInteger.op_Explicit $454 N016 ( 18, 15) [000845] -A--G-----L- arg0 SETUP | | +--* COMMA void $VN.Void N009 ( 10, 8) [000838] -A--G------- | | | +--* COMMA void $VN.Void N004 ( 3, 3) [000833] -A------R--- | | | | +--* ASG byref $426 N003 ( 1, 1) [000832] D------N---- | | | | | +--* LCL_VAR byref V90 tmp60 d:2 $426 N002 ( 3, 3) [000830] ------------ | | | | | \--* ADDR byref $426 N001 ( 3, 2) [000831] ----G--N---- | | | | | \--* LCL_VAR struct(AX) V76 tmp46 $3db N008 ( 7, 5) [000837] -A--G------- | | | | \--* ASG ref $VN.Void N006 ( 3, 2) [000835] *------N---- | | | | +--* IND ref $18b N005 ( 1, 1) [000834] ------------ | | | | | \--* LCL_VAR byref V90 tmp60 u:2 Zero Fseq[_bits] $426 N007 ( 3, 2) [000836] ----G--N---- | | | | \--* LCL_VAR ref (AX) V54 tmp24 $18b N015 ( 8, 7) [000844] -A--G------- | | | \--* ASG int $VN.Void N013 ( 4, 4) [000842] *------N---- | | | +--* IND int $252 N012 ( 2, 2) [000841] -------N---- | | | | \--* ADD byref $220 N010 ( 1, 1) [000839] ------------ | | | | +--* LCL_VAR byref V90 tmp60 u:2 (last use) $426 N011 ( 1, 1) [000840] ------------ | | | | \--* CNS_INT long 8 Fseq[_sign] $101 N014 ( 3, 2) [000843] ----G--N---- | | | \--* LCL_VAR int (AX) V55 tmp25 $252 N018 ( 3, 3) [000847] ------------ arg0 in rcx | | \--* ADDR byref $428 N017 ( 3, 2) [000846] -------N---- | | \--* LCL_VAR struct(AX) V76 tmp46 $3dc N022 ( 5, 4) [000249] ------------ | \--* AND int $370 N020 ( 3, 2) [000247] ------------ | +--* LCL_VAR int V20 loc17 u:2 (last use) $362 N021 ( 1, 1) [000248] ------------ | \--* CNS_INT int 63 $66 N024 ( 1, 1) [000251] ------------ \--* LCL_VAR long V24 loc21 u:3 (last use) $580 ***** BB40 STMT00058 (IL 0x1E2...0x1E5) N004 ( 5, 5) [000258] ------------ * JTRUE void N003 ( 3, 3) [000257] N------N---- \--* NE int $35a N001 ( 1, 1) [000255] ------------ +--* LCL_VAR int V13 loc10 u:2 $293 N002 ( 1, 1) [000256] ------------ \--* CNS_INT int 0 $40 ------------ BB41 [1E7..1EE) -> BB43 (always), preds={BB40} succs={BB43} ***** BB41 STMT00062 (IL 0x1E7...0x1EC) N006 ( 10, 8) [000280] -A------R--- * ASG int $372 N005 ( 3, 2) [000279] D------N---- +--* LCL_VAR int V36 tmp6 d:4 $372 N004 ( 6, 5) [000278] ------------ \--* ADD int $372 N002 ( 4, 3) [000276] ------------ +--* NEG int $2c2 N001 ( 3, 2) [000275] ------------ | \--* LCL_VAR int V22 loc19 u:2 (last use) $24c N003 ( 1, 1) [000277] ------------ \--* CNS_INT int -1 $43 ------------ BB42 [1EE..1F2), preds={BB40} succs={BB43} ***** BB42 STMT00059 (IL 0x1EE...0x1F1) N005 ( 7, 6) [000263] -A------R--- * ASG int $371 N004 ( 3, 2) [000262] D------N---- +--* LCL_VAR int V36 tmp6 d:3 $371 N003 ( 3, 3) [000261] ------------ \--* ADD int $371 N001 ( 1, 1) [000259] ------------ +--* LCL_VAR int V13 loc10 u:2 (last use) $293 N002 ( 1, 1) [000260] ------------ \--* CNS_INT int -2 $68 ------------ BB43 [1F2..202), preds={BB41,BB42} succs={BB44} ***** BB43 STMT00113 (IL ???... ???) N005 ( 0, 0) [000859] -A------R--- * ASG int N004 ( 0, 0) [000857] D------N---- +--* LCL_VAR int V36 tmp6 d:2 N003 ( 0, 0) [000858] ------------ \--* PHI int N001 ( 0, 0) [000893] ------------ pred BB41 +--* PHI_ARG int V36 tmp6 u:4 $372 N002 ( 0, 0) [000892] ------------ pred BB42 \--* PHI_ARG int V36 tmp6 u:3 $371 ***** BB43 STMT00061 (IL 0x1F4...0x201) N012 ( 28, 18) [000853] -ACXG---R--- * ASG int $2be N011 ( 1, 1) [000852] D------N---- +--* LCL_VAR int V51 tmp21 d:4 $2be N010 ( 28, 18) [000273] --CXG------- \--* CALL int FloatingPointType.AssembleFloatingPointValue $2be N005 ( 1, 1) [000272] ------------ arg4 out+20 +--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N006 ( 1, 1) [000268] ------------ this in rcx +--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 N007 ( 3, 2) [000269] ------------ arg1 in rdx +--* LCL_VAR long V27 loc24 u:2 (last use) $493 N008 ( 3, 2) [000270] ------------ arg2 in r8 +--* LCL_VAR int V36 tmp6 u:2 (last use) $253 N009 ( 3, 2) [000271] ------------ arg3 in r9 \--* LCL_VAR int V25 loc22 u:3 (last use) $540 ------------ BB44 [???..???) (return), preds={BB16,BB30,BB43} succs={} ***** BB44 STMT00112 (IL ???... ???) N006 ( 0, 0) [000856] -A------R--- * ASG int N005 ( 0, 0) [000854] D------N---- +--* LCL_VAR int V51 tmp21 d:2 N004 ( 0, 0) [000855] ------------ \--* PHI int N001 ( 0, 0) [000901] ------------ pred BB30 +--* PHI_ARG int V51 tmp21 u:5 $5c2 N002 ( 0, 0) [000891] ------------ pred BB43 +--* PHI_ARG int V51 tmp21 u:4 $2be N003 ( 0, 0) [000887] ------------ pred BB16 \--* PHI_ARG int V51 tmp21 u:3 $5c7 ***** BB44 STMT00109 (IL ???... ???) N002 ( 2, 2) [000523] ------------ * RETURN int $5c9 N001 ( 1, 1) [000522] -------N---- \--* LCL_VAR int V51 tmp21 u:2 (last use) $254 ------------------------------------------------------------------------------------------------------------------- *************** Finishing PHASE Optimize index checks *************** Starting PHASE Insert GC Polls *************** Finishing PHASE Insert GC Polls [no changes] *************** Starting PHASE Determine first cold block *************** In fgDetermineFirstColdBlock() No procedure splitting will be done for this method *************** Finishing PHASE Determine first cold block Trees before Rationalize IR ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0056] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..00D)-> BB04 ( cond ) i label target idxlen BB03 [0001] 1 BB02 0.50 [00D..017) (return) i hascall gcsafe BB04 [0002] 1 BB02 0.50 [017..065)-> BB06 ( cond ) i label target hascall gcsafe BB05 [0038] 1 BB04 0.50 [020..021)-> BB07 (always) i gcsafe BB06 [0039] 1 BB04 0.50 [020..021) i label target gcsafe BB07 [0040] 2 BB05,BB06 0.50 [000..000)-> BB09 ( cond ) i internal label target gcsafe idxlen BB08 [0043] 1 BB07 0.50 [000..000)-> BB10 (always) i internal gcsafe BB09 [0044] 1 BB07 0.50 [000..000) i internal label target gcsafe BB10 [0045] 2 BB08,BB09 0.50 [???..???)-> BB14 ( cond ) i internal label target hascall gcsafe idxlen BB11 [0003] 1 BB10 0.50 [065..070)-> BB13 ( cond ) i hascall gcsafe BB12 [0004] 1 BB11 0.50 [070..07A) (return) i hascall gcsafe BB13 [0005] 1 BB11 0.50 [07A..082) i label target hascall gcsafe BB14 [0006] 2 BB10,BB13 0.50 [082..092)-> BB16 ( cond ) i label target hascall gcsafe BB15 [0007] 1 BB14 0.50 [092..096)-> BB17 ( cond ) i gcsafe BB16 [0008] 2 BB14,BB15 0.50 [096..0A7)-> BB44 (always) i label target hascall gcsafe BB17 [0009] 1 BB15 0.50 [0A7..0B0)-> BB19 ( cond ) i label target gcsafe BB18 [0010] 1 BB17 0.50 [0B0..0B4)-> BB20 (always) i gcsafe BB19 [0011] 1 BB17 0.50 [0B4..0BE) i label target gcsafe BB20 [0012] 2 BB18,BB19 0.50 [0BE..0C4)-> BB23 ( cond ) i label target gcsafe BB21 [0013] 1 BB20 0.50 [0C4..0D9)-> BB23 ( cond ) i hascall gcsafe idxlen BB22 [0014] 1 BB21 0.50 [0D9..0E3) (return) i hascall gcsafe BB23 [0015] 2 BB20,BB21 0.50 [0E3..117)-> BB25 ( cond ) i label target hascall gcsafe BB24 [0016] 1 BB23 0.50 [117..11A)-> BB26 (always) i gcsafe BB25 [0017] 1 BB23 0.50 [11A..11F) i label target gcsafe BB26 [0018] 2 BB24,BB25 0.50 [11F..126)-> BB28 ( cond ) i label target gcsafe BB27 [0019] 1 BB26 0.50 [126..12F) i hascall gcsafe BB28 [0020] 2 BB26,BB27 0.50 [12F..13E)-> BB32 ( cond ) i label target gcsafe BB29 [0021] 1 BB28 0.50 [13E..144)-> BB31 ( cond ) i gcsafe BB30 [0022] 1 BB29 0.50 [144..155)-> BB44 (always) i hascall gcsafe BB31 [0023] 1 BB29 0.50 [155..15C) i label target gcsafe BB32 [0024] 2 BB28,BB31 0.50 [15C..167)-> BB34 ( cond ) i label target hascall gcsafe BB33 [0025] 1 BB32 0.50 [167..16B)-> BB35 (always) i gcsafe BB34 [0026] 1 BB32 0.50 [16B..16F) i label target gcsafe BB35 [0027] 2 BB33,BB34 0.50 [16F..1A4)-> BB40 ( cond ) i label target hascall gcsafe BB36 [0028] 1 BB35 0.50 [1A4..1AF)-> BB38 ( cond ) i gcsafe BB37 [0029] 1 BB36 0.50 [1AF..1C3)-> BB39 (always) i gcsafe BB38 [0030] 1 BB36 0.50 [1C3..1C4) i label target gcsafe BB39 [0031] 2 BB37,BB38 0.50 [1C4..1D0) i label target gcsafe BB40 [0032] 2 BB35,BB39 0.50 [1D0..1E7)-> BB42 ( cond ) i label target hascall gcsafe BB41 [0033] 1 BB40 0.50 [1E7..1EE)-> BB43 (always) i gcsafe BB42 [0034] 1 BB40 0.50 [1EE..1F2) i label target gcsafe BB43 [0035] 2 BB41,BB42 0.50 [1F2..202) i label target hascall gcsafe BB44 [0054] 3 BB16,BB30,BB43 0.50 [???..???) (return) keep internal target gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} ***** BB01 STMT00111 (IL ???... ???) N011 ( 7, 7) [000540] -A---------- * COMMA void N004 ( 3, 3) [000533] -A------R--- +--* ASG ref N003 ( 1, 1) [000530] D------N---- | +--* LCL_VAR ref V52 tmp22 d:2 N002 ( 3, 2) [000532] n----------- | \--* IND ref N001 ( 1, 1) [000531] ------------ | \--* LCL_VAR byref V00 arg0 u:1 Zero Fseq[Mantissa] $80 N010 ( 4, 4) [000539] -A------R--- \--* ASG int N009 ( 1, 1) [000534] D------N---- +--* LCL_VAR int V53 tmp23 d:2 N008 ( 4, 4) [000538] n----------- \--* IND int N007 ( 2, 2) [000537] -------N---- \--* ADD byref $200 N005 ( 1, 1) [000535] ------------ +--* LCL_VAR byref V00 arg0 u:1 (last use) $80 N006 ( 1, 1) [000536] ------------ \--* CNS_INT long 8 Fseq[Exponent] $101 ------------ BB02 [000..00D) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00000 (IL 0x000...0x00B) N005 ( 7, 7) [000006] ---XG------- * JTRUE void N004 ( 5, 5) [000005] J--XG--N---- \--* NE int N002 ( 3, 3) [000003] ---XG------- +--* ARR_LENGTH int N001 ( 1, 1) [000002] ------------ | \--* LCL_VAR ref V52 tmp22 u:2 N003 ( 1, 1) [000004] ------------ \--* CNS_INT int 0 $40 ------------ BB03 [00D..017) (return), preds={BB02} succs={} ***** BB03 STMT00087 (IL 0x00D...0x014) N006 ( 25, 13) [000403] -ACXG---R--- * ASG long $VN.Void N005 ( 3, 2) [000402] *--X---N---- +--* IND long $459 N004 ( 1, 1) [000399] ------------ | \--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N003 ( 21, 10) [000401] --CXG------- \--* CALLV ind long FloatingPointType.get_Zero $459 N002 ( 1, 1) [000400] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 ***** BB03 STMT00107 (IL ???... ???) N002 ( 2, 2) [000520] ------------ * RETURN int $5cb N001 ( 1, 1) [000404] ------------ \--* CNS_INT int 1 $41 ------------ BB04 [017..065) -> BB06 (cond), preds={BB02} succs={BB05,BB06} ***** BB04 STMT00002 (IL ???... ???) N010 ( 30, 19) [000013] -ACXG---R--- * ASG int $348 N009 ( 3, 2) [000012] D------N---- +--* LCL_VAR int V03 loc0 d:2 $348 N008 ( 26, 16) [000011] --CXG------- \--* ADD int $348 N006 ( 24, 14) [000409] --CXG------- +--* CAST int <- ushort <- int $347 N005 ( 23, 12) [000408] --CXG------- | \--* ADD int $346 N003 ( 21, 10) [000406] --CXG------- | +--* CALLV ind int FloatingPointType.get_DenormalMantissaBits $282 N002 ( 1, 1) [000007] ------------ this in rcx | | \--* LCL_VAR ref V01 arg1 u:1 $c0 N004 ( 1, 1) [000407] ------------ | \--* CNS_INT int 1 $41 N007 ( 1, 1) [000010] ------------ \--* CNS_INT int 1 $41 ***** BB04 STMT00092 (IL 0x020... ???) N003 ( 5, 4) [000424] -A--G---R--- * ASG int N002 ( 3, 2) [000423] D------N---- +--* LCL_VAR int V40 tmp10 d:2 N001 ( 1, 1) [000017] ------------ \--* LCL_VAR int V53 tmp23 u:2 ***** BB04 STMT00089 (IL 0x020... ???) N004 ( 5, 5) [000414] ------------ * JTRUE void N003 ( 3, 3) [000413] J------N---- \--* LE int N001 ( 1, 1) [000412] ------------ +--* LCL_VAR int V40 tmp10 u:2 N002 ( 1, 1) [000411] ------------ \--* CNS_INT int 0 $40 ------------ BB05 [020..021) -> BB07 (always), preds={BB04} succs={BB07} ***** BB05 STMT00091 (IL 0x020... ???) N003 ( 7, 5) [000421] -A------R--- * ASG int N002 ( 3, 2) [000420] D------N---- +--* LCL_VAR int V39 tmp9 d:4 N001 ( 3, 2) [000419] ------------ \--* LCL_VAR int V53 tmp23 u:2 (last use) ------------ BB06 [020..021), preds={BB04} succs={BB07} ***** BB06 STMT00090 (IL 0x020... ???) N003 ( 5, 4) [000417] -A------R--- * ASG int $40 N002 ( 3, 2) [000416] D------N---- +--* LCL_VAR int V39 tmp9 d:3 $40 N001 ( 1, 1) [000415] ------------ \--* CNS_INT int 0 $40 ------------ BB07 [000..000) -> BB09 (cond), preds={BB05,BB06} succs={BB08,BB09} ***** BB07 STMT00122 (IL ???... ???) N005 ( 0, 0) [000886] -A------R--- * ASG int N004 ( 0, 0) [000884] D------N---- +--* LCL_VAR int V39 tmp9 d:2 N003 ( 0, 0) [000885] ------------ \--* PHI int N001 ( 0, 0) [000909] ------------ pred BB05 +--* PHI_ARG int V39 tmp9 u:4 N002 ( 0, 0) [000908] ------------ pred BB06 \--* PHI_ARG int V39 tmp9 u:3 $40 ***** BB07 STMT00004 (IL ???... ???) N003 ( 3, 3) [000021] -A------R--- * ASG int $241 N002 ( 1, 1) [000020] D------N---- +--* LCL_VAR int V31 tmp1 d:2 $241 N001 ( 3, 2) [000422] ------------ \--* LCL_VAR int V39 tmp9 u:2 $241 ***** BB07 STMT00096 (IL ???... ???) N004 ( 3, 3) [000443] -A-XG---R--- * ASG int N003 ( 1, 1) [000442] D------N---- +--* LCL_VAR int V42 tmp12 d:2 N002 ( 3, 3) [000429] ---XG------- \--* ARR_LENGTH int N001 ( 1, 1) [000428] ------------ \--* LCL_VAR ref V52 tmp22 u:2 ***** BB07 STMT00093 (IL ???... ???) N004 ( 7, 6) [000433] ------------ * JTRUE void N003 ( 5, 4) [000432] N------N-U-- \--* LE int N001 ( 3, 2) [000023] ------------ +--* LCL_VAR int V31 tmp1 u:2 (last use) $241 N002 ( 1, 1) [000431] ------------ \--* LCL_VAR int V42 tmp12 u:2 ------------ BB08 [000..000) -> BB10 (always), preds={BB07} succs={BB10} ***** BB08 STMT00095 (IL ???... ???) N003 ( 1, 3) [000440] -A------R--- * ASG int N002 ( 1, 1) [000439] D------N---- +--* LCL_VAR int V41 tmp11 d:4 N001 ( 1, 1) [000438] ------------ \--* LCL_VAR int V42 tmp12 u:2 (last use) ------------ BB09 [000..000), preds={BB07} succs={BB10} ***** BB09 STMT00094 (IL ???... ???) N003 ( 1, 3) [000436] -A------R--- * ASG int $241 N002 ( 1, 1) [000435] D------N---- +--* LCL_VAR int V41 tmp11 d:3 $241 N001 ( 1, 1) [000434] ------------ \--* LCL_VAR int V31 tmp1 u:2 $241 ------------ BB10 [???..???) -> BB14 (cond), preds={BB08,BB09} succs={BB11,BB14} ***** BB10 STMT00121 (IL ???... ???) N005 ( 0, 0) [000883] -A------R--- * ASG int N004 ( 0, 0) [000881] D------N---- +--* LCL_VAR int V41 tmp11 d:2 N003 ( 0, 0) [000882] ------------ \--* PHI int N001 ( 0, 0) [000907] ------------ pred BB08 +--* PHI_ARG int V41 tmp11 u:4 N002 ( 0, 0) [000906] ------------ pred BB09 \--* PHI_ARG int V41 tmp11 u:3 $241 ***** BB10 STMT00008 (IL ???...0x03C) N005 ( 7, 6) [000035] -A------R--- * ASG int $34e N004 ( 3, 2) [000034] D------N---- +--* LCL_VAR int V05 loc2 d:2 $34e N003 ( 3, 3) [000033] ------------ \--* SUB int $34e N001 ( 1, 1) [000022] ------------ +--* LCL_VAR int V31 tmp1 u:2 (last use) $241 N002 ( 1, 1) [000032] ------------ \--* LCL_VAR int V41 tmp11 u:2 $242 ***** BB10 STMT00011 (IL 0x042...0x044) N003 ( 5, 4) [000044] -A------R--- * ASG int $242 N002 ( 3, 2) [000043] D------N---- +--* LCL_VAR int V08 loc5 d:2 $242 N001 ( 1, 1) [000042] ------------ \--* LCL_VAR int V41 tmp11 u:2 $242 ***** BB10 STMT00013 (IL ???... ???) N004 ( 7, 6) [000050] -A-XG---R--- * ASG int N003 ( 3, 2) [000049] D------N---- +--* LCL_VAR int V09 loc6 d:2 N002 ( 3, 3) [000448] ---XG------- \--* ARR_LENGTH int N001 ( 1, 1) [000447] ------------ \--* LCL_VAR ref V52 tmp22 u:2 ***** BB10 STMT00014 (IL 0x04F...0x054) N005 ( 5, 4) [000055] -A------R--- * ASG int N004 ( 1, 1) [000054] D------N---- +--* LCL_VAR int V10 loc7 d:2 N003 ( 5, 4) [000053] ------------ \--* SUB int N001 ( 3, 2) [000051] ------------ +--* LCL_VAR int V09 loc6 u:2 N002 ( 1, 1) [000052] ------------ \--* LCL_VAR int V08 loc5 u:2 $242 ***** BB10 STMT00016 (IL ???... ???) N028 ( 49, 35) [000059] SACXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger $VN.Void N004 ( 7, 6) [000563] -A------R-L- arg0 SETUP +--* ASG long $400 N003 ( 3, 2) [000562] D------N---- | +--* LCL_VAR long V75 tmp45 d:2 $400 N002 ( 3, 3) [000064] ------------ | \--* ADDR long $400 N001 ( 3, 2) [000063] ----G--N---- | \--* LCL_VAR struct(AX)(P) V11 loc8 | \--* ref V11._bits (offs=0x00) -> V54 tmp24 | \--* int V11._sign (offs=0x08) -> V55 tmp25 $3c0 N020 ( 14, 13) [000561] -A--------L- arg1 SETUP +--* COMMA void $VN.Void N013 ( 8, 7) [000554] -A---------- | +--* COMMA void $VN.Void N008 ( 3, 3) [000549] -A------R--- | | +--* ASG byref $401 N007 ( 1, 1) [000548] D------N---- | | | +--* LCL_VAR byref V74 tmp44 d:2 $401 N006 ( 3, 3) [000546] ------------ | | | \--* ADDR byref $401 N005 ( 3, 2) [000547] -------N---- | | | \--* LCL_VAR struct(AX) V73 tmp43 $3c1 N012 ( 5, 4) [000553] -A---------- | | \--* ASG ref $VN.Void N010 ( 3, 2) [000551] *------N---- | | +--* IND ref N009 ( 1, 1) [000550] ------------ | | | \--* LCL_VAR byref V74 tmp44 u:2 Zero Fseq[Mantissa] $401 N011 ( 1, 1) [000552] -------N---- | | \--* LCL_VAR ref V52 tmp22 u:2 N019 ( 6, 6) [000560] -A---------- | \--* ASG int $VN.Void N017 ( 4, 4) [000558] *------N---- | +--* IND int N016 ( 2, 2) [000557] -------N---- | | \--* ADD byref $203 N014 ( 1, 1) [000555] ------------ | | +--* LCL_VAR byref V74 tmp44 u:2 (last use) $401 N015 ( 1, 1) [000556] ------------ | | \--* CNS_INT long 8 Fseq[Exponent] $101 N018 ( 1, 1) [000559] -------N---- | \--* LCL_VAR int V53 tmp23 u:2 N023 ( 3, 2) [000564] ------------ arg0 in rcx +--* LCL_VAR long V75 tmp45 u:2 (last use) $400 N025 ( 3, 3) [000566] ------------ arg1 in rdx +--* ADDR byref $403 N024 ( 3, 2) [000565] -------N---- | \--* LCL_VAR struct(AX) V73 tmp43 $3c2 N026 ( 1, 1) [000058] ------------ arg3 in r9 +--* LCL_VAR int V08 loc5 u:2 (last use) $242 N027 ( 1, 1) [000057] ------------ arg2 in r8 \--* CNS_INT int 0 $40 ***** BB10 STMT00017 (IL 0x061...0x063) N004 ( 7, 6) [000068] ------------ * JTRUE void N003 ( 5, 4) [000067] N------N---- \--* EQ int $351 N001 ( 3, 2) [000065] ------------ +--* LCL_VAR int V05 loc2 u:2 $34e N002 ( 1, 1) [000066] ------------ \--* CNS_INT int 0 $40 ------------ BB11 [065..070) -> BB13 (cond), preds={BB10} succs={BB12,BB13} ***** BB11 STMT00083 (IL ???... ???) N008 ( 23, 17) [000387] --CXG------- * JTRUE void N007 ( 21, 15) [000386] J-CXG--N---- \--* GE int $352 N004 ( 16, 10) [000385] --CXG------- +--* CAST long <- int $480 N003 ( 15, 8) [000383] --CXG------- | \--* CALL int FloatingPointType.get_OverflowDecimalExponent $291 N002 ( 1, 1) [000382] ------------ this in rcx | \--* LCL_VAR ref V01 arg1 u:1 $c0 N006 ( 4, 4) [000381] ---------U-- \--* CAST long <- ulong <- uint $481 N005 ( 3, 2) [000380] ------------ \--* LCL_VAR int V05 loc2 u:2 $34e ------------ BB12 [070..07A) (return), preds={BB11} succs={} ***** BB12 STMT00085 (IL 0x070...0x077) N006 ( 25, 13) [000396] -ACXG---R--- * ASG long $VN.Void N005 ( 3, 2) [000395] *--X---N---- +--* IND long $458 N004 ( 1, 1) [000392] ------------ | \--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N003 ( 21, 10) [000394] --CXG------- \--* CALLV ind long FloatingPointType.get_Infinity $458 N002 ( 1, 1) [000393] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 ***** BB12 STMT00108 (IL ???... ???) N002 ( 2, 2) [000521] ------------ * RETURN int $5ca N001 ( 1, 1) [000397] ------------ \--* CNS_INT int 3 $48 ------------ BB13 [07A..082), preds={BB11} succs={BB14} ***** BB13 STMT00084 (IL 0x07A...0x07D) N006 ( 20, 12) [000391] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen $VN.Void N004 ( 3, 3) [000389] ------------ arg0 in rcx +--* ADDR long $404 N003 ( 3, 2) [000388] ----G--N---- | \--* LCL_VAR struct(AX)(P) V11 loc8 | \--* ref V11._bits (offs=0x00) -> V54 tmp24 | \--* int V11._sign (offs=0x08) -> V55 tmp25 $3c3 N005 ( 3, 2) [000390] ------------ arg1 in rdx \--* LCL_VAR int V05 loc2 u:2 (last use) $34e ------------ BB14 [082..092) -> BB16 (cond), preds={BB10,BB13} succs={BB15,BB16} ***** BB14 STMT00019 (IL ???... ???) N023 ( 41, 28) [000077] -ACXG---R--- * ASG int $293 N022 ( 1, 1) [000076] D------N---- +--* LCL_VAR int V13 loc10 d:2 $293 N021 ( 41, 28) [000072] -ACXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $293 N016 ( 18, 15) [000591] -A--G-----L- arg0 SETUP +--* COMMA void $VN.Void N009 ( 10, 8) [000584] -A--G------- | +--* COMMA void $VN.Void N004 ( 3, 3) [000579] -A------R--- | | +--* ASG byref $405 N003 ( 1, 1) [000578] D------N---- | | | +--* LCL_VAR byref V77 tmp47 d:2 $405 N002 ( 3, 3) [000576] ------------ | | | \--* ADDR byref $405 N001 ( 3, 2) [000577] -------N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 $3c4 N008 ( 7, 5) [000583] -A--G------- | | \--* ASG ref $VN.Void N006 ( 3, 2) [000581] *------N---- | | +--* IND ref $181 N005 ( 1, 1) [000580] ------------ | | | \--* LCL_VAR byref V77 tmp47 u:2 Zero Fseq[_bits] $405 N007 ( 3, 2) [000582] ----G--N---- | | \--* LCL_VAR ref (AX) V54 tmp24 $181 N015 ( 8, 7) [000590] -A--G------- | \--* ASG int $VN.Void N013 ( 4, 4) [000588] *------N---- | +--* IND int $243 N012 ( 2, 2) [000587] -------N---- | | \--* ADD byref $206 N010 ( 1, 1) [000585] ------------ | | +--* LCL_VAR byref V77 tmp47 u:2 (last use) $405 N011 ( 1, 1) [000586] ------------ | | \--* CNS_INT long 8 Fseq[_sign] $101 N014 ( 3, 2) [000589] ----G--N---- | \--* LCL_VAR int (AX) V55 tmp25 $243 N019 ( 3, 3) [000593] ------------ arg0 in rcx +--* ADDR byref $407 N018 ( 3, 2) [000592] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 $3c5 N020 ( 3, 3) [000071] ------------ arg1 in rdx \--* LCL_VAR_ADDR long V12 loc9 $443 ***** BB14 STMT00020 (IL 0x08D...0x090) N004 ( 7, 6) [000081] ------------ * JTRUE void N003 ( 5, 4) [000080] N------N-U-- \--* GE int $353 N001 ( 1, 1) [000078] ------------ +--* LCL_VAR int V13 loc10 u:2 $293 N002 ( 3, 2) [000079] ------------ \--* LCL_VAR int V03 loc0 u:2 $348 ------------ BB15 [092..096) -> BB17 (cond), preds={BB14} succs={BB16,BB17} ***** BB15 STMT00022 (IL 0x092...0x094) N004 ( 5, 5) [000094] ------------ * JTRUE void N003 ( 3, 3) [000093] J------N---- \--* NE int N001 ( 1, 1) [000091] ------------ +--* LCL_VAR int V10 loc7 u:2 N002 ( 1, 1) [000092] ------------ \--* CNS_INT int 0 $40 ------------ BB16 [096..0A7) -> BB44 (always), preds={BB14,BB15} succs={BB44} ***** BB16 STMT00021 (IL 0x096...0x0A6) N014 ( 29, 17) [000600] -ACXG---R--- * ASG int $5c7 N013 ( 1, 1) [000599] D------N---- +--* LCL_VAR int V51 tmp21 d:3 $5c7 N012 ( 29, 17) [000089] --CXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits $5c7 N005 ( 1, 1) [000088] ------------ arg4 out+20 +--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N008 ( 6, 3) [000086] N----------- arg2 in r8 +--* NE int N006 ( 1, 1) [000084] ------------ | +--* LCL_VAR int V10 loc7 u:2 (last use) N007 ( 1, 1) [000085] ------------ | \--* CNS_INT int 0 $40 N009 ( 3, 2) [000082] ----G------- arg0 in rcx +--* LCL_VAR ref (AX) V12 loc9 $18d N010 ( 1, 1) [000083] ------------ arg1 in rdx +--* LCL_VAR int V13 loc10 u:2 (last use) $293 N011 ( 1, 1) [000087] ------------ arg3 in r9 \--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 ------------ BB17 [0A7..0B0) -> BB19 (cond), preds={BB15} succs={BB18,BB19} ***** BB17 STMT00023 (IL 0x0A7...0x0AE) N004 ( 5, 5) [000100] ----G------- * JTRUE void N003 ( 3, 3) [000099] J---G--N---- \--* LT int N001 ( 1, 1) [000097] ------------ +--* LCL_VAR int V53 tmp23 u:2 N002 ( 1, 1) [000098] ------------ \--* CNS_INT int 0 $40 ------------ BB18 [0B0..0B4) -> BB20 (always), preds={BB17} succs={BB20} ***** BB18 STMT00081 (IL 0x0B0...0x0B2) N003 ( 5, 4) [000378] -A------R--- * ASG int N002 ( 3, 2) [000377] D------N---- +--* LCL_VAR int V32 tmp2 d:4 N001 ( 1, 1) [000376] ------------ \--* LCL_VAR int V10 loc7 u:2 ------------ BB19 [0B4..0BE), preds={BB17} succs={BB20} ***** BB19 STMT00024 (IL 0x0B4...0x0BD) N005 ( 7, 6) [000108] -A--G---R--- * ASG int N004 ( 3, 2) [000107] D------N---- +--* LCL_VAR int V32 tmp2 d:3 N003 ( 3, 3) [000106] ----G------- \--* SUB int N001 ( 1, 1) [000101] ------------ +--* LCL_VAR int V10 loc7 u:2 N002 ( 1, 1) [000104] ------------ \--* LCL_VAR int V53 tmp23 u:2 ------------ BB20 [0BE..0C4) -> BB23 (cond), preds={BB18,BB19} succs={BB21,BB23} ***** BB20 STMT00120 (IL ???... ???) N005 ( 0, 0) [000880] -A------R--- * ASG int N004 ( 0, 0) [000878] D------N---- +--* LCL_VAR int V32 tmp2 d:2 N003 ( 0, 0) [000879] ------------ \--* PHI int N001 ( 0, 0) [000905] ------------ pred BB18 +--* PHI_ARG int V32 tmp2 u:4 N002 ( 0, 0) [000904] ------------ pred BB19 \--* PHI_ARG int V32 tmp2 u:3 ***** BB20 STMT00025 (IL ???...0x0BE) N003 ( 7, 5) [000112] -A------R--- * ASG int $244 N002 ( 3, 2) [000111] D------N---- +--* LCL_VAR int V14 loc11 d:2 $244 N001 ( 3, 2) [000110] ------------ \--* LCL_VAR int V32 tmp2 u:2 (last use) $244 ***** BB20 STMT00026 (IL 0x0C0...0x0C2) N004 ( 5, 5) [000116] ------------ * JTRUE void N003 ( 3, 3) [000115] J------N---- \--* NE int $35a N001 ( 1, 1) [000113] ------------ +--* LCL_VAR int V13 loc10 u:2 $293 N002 ( 1, 1) [000114] ------------ \--* CNS_INT int 0 $40 ------------ BB21 [0C4..0D9) -> BB23 (cond), preds={BB20} succs={BB22,BB23} ***** BB21 STMT00077 (IL ???... ???) N008 ( 13, 13) [000363] -A-XG---R--- * ASG long N007 ( 3, 2) [000362] D------N---- +--* LCL_VAR long V38 tmp8 d:2 N006 ( 9, 10) [000359] ---XG---R--- \--* SUB long N005 ( 4, 4) [000353] ---------U-- +--* CAST long <- ulong <- uint $486 N004 ( 3, 2) [000352] ------------ | \--* LCL_VAR int V14 loc11 u:2 $244 N003 ( 4, 5) [000358] ---XG------- \--* CAST long <- int N002 ( 3, 3) [000456] ---XG------- \--* ARR_LENGTH int N001 ( 1, 1) [000455] ------------ \--* LCL_VAR ref V52 tmp22 u:2 ***** BB21 STMT00078 (IL ???... ???) N007 ( 22, 15) [000368] --CXG------- * JTRUE void N006 ( 20, 13) [000367] J-CXG--N---- \--* GE int N004 ( 16, 10) [000366] --CXG------- +--* CAST long <- int $48b N003 ( 15, 8) [000361] --CXG------- | \--* CALL int FloatingPointType.get_OverflowDecimalExponent $298 N002 ( 1, 1) [000360] ------------ this in rcx | \--* LCL_VAR ref V01 arg1 u:1 $c0 N005 ( 3, 2) [000364] ------------ \--* LCL_VAR long V38 tmp8 u:2 (last use) ------------ BB22 [0D9..0E3) (return), preds={BB21} succs={} ***** BB22 STMT00079 (IL 0x0D9...0x0E0) N006 ( 25, 13) [000373] -ACXG---R--- * ASG long $VN.Void N005 ( 3, 2) [000372] *--X---N---- +--* IND long $457 N004 ( 1, 1) [000369] ------------ | \--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N003 ( 21, 10) [000371] --CXG------- \--* CALLV ind long FloatingPointType.get_Zero $457 N002 ( 1, 1) [000370] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 ***** BB22 STMT00110 (IL ???... ???) N002 ( 2, 2) [000524] ------------ * RETURN int $5c4 N001 ( 1, 1) [000374] ------------ \--* CNS_INT int 2 $42 ------------ BB23 [0E3..117) -> BB25 (cond), preds={BB20,BB21} succs={BB24,BB25} ***** BB23 STMT00028 (IL ???... ???) N028 ( 53, 37) [000120] SACXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger $VN.Void N004 ( 7, 6) [000623] -A------R-L- arg0 SETUP +--* ASG long $408 N003 ( 3, 2) [000622] D------N---- | +--* LCL_VAR long V79 tmp49 d:2 $408 N002 ( 3, 3) [000125] ------------ | \--* ADDR long $408 N001 ( 3, 2) [000124] ----G--N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 $3c6 N020 ( 14, 13) [000621] -A--------L- arg1 SETUP +--* COMMA void $VN.Void N013 ( 8, 7) [000614] -A---------- | +--* COMMA void $VN.Void N008 ( 3, 3) [000609] -A------R--- | | +--* ASG byref $409 N007 ( 1, 1) [000608] D------N---- | | | +--* LCL_VAR byref V78 tmp48 d:2 $409 N006 ( 3, 3) [000606] ------------ | | | \--* ADDR byref $409 N005 ( 3, 2) [000607] ----G--N---- | | | \--* LCL_VAR struct(AX) V73 tmp43 $3c7 N012 ( 5, 4) [000613] -A---------- | | \--* ASG ref $VN.Void N010 ( 3, 2) [000611] *------N---- | | +--* IND ref N009 ( 1, 1) [000610] ------------ | | | \--* LCL_VAR byref V78 tmp48 u:2 Zero Fseq[Mantissa] $409 N011 ( 1, 1) [000612] -------N---- | | \--* LCL_VAR ref V52 tmp22 u:2 (last use) N019 ( 6, 6) [000620] -A---------- | \--* ASG int $VN.Void N017 ( 4, 4) [000618] *------N---- | +--* IND int N016 ( 2, 2) [000617] -------N---- | | \--* ADD byref $209 N014 ( 1, 1) [000615] ------------ | | +--* LCL_VAR byref V78 tmp48 u:2 (last use) $409 N015 ( 1, 1) [000616] ------------ | | \--* CNS_INT long 8 Fseq[Exponent] $101 N018 ( 1, 1) [000619] -------N---- | \--* LCL_VAR int V53 tmp23 u:2 (last use) N023 ( 3, 2) [000624] ------------ arg0 in rcx +--* LCL_VAR long V79 tmp49 u:2 (last use) $408 N025 ( 3, 3) [000626] ------------ arg1 in rdx +--* ADDR byref $40b N024 ( 3, 2) [000625] -------N---- | \--* LCL_VAR struct(AX) V73 tmp43 $3c8 N026 ( 3, 2) [000118] ------------ arg2 in r8 +--* LCL_VAR int V08 loc5 u:2 (last use) $242 N027 ( 3, 2) [000119] ------------ arg3 in r9 \--* LCL_VAR int V09 loc6 u:2 (last use) ***** BB23 STMT00029 (IL 0x0EF...0x0F4) N005 ( 17, 21) [000133] H-CXG------- * CALL help long HELPER.CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE $48d N003 ( 2, 10) [000131] ------------ arg0 in rcx +--* CNS_INT long 0x7ff815262aa0 $102 N004 ( 1, 4) [000132] ------------ arg1 in rdx \--* CNS_INT int 173 $58 ***** BB23 STMT00030 (IL ???... ???) N018 ( 21, 26) [000649] -A-XG------- * COMMA void N011 ( 13, 19) [000642] -A-XG------- +--* COMMA void N006 ( 6, 14) [000637] -A--G---R--- | +--* ASG byref N005 ( 1, 1) [000636] D------N---- | | +--* LCL_VAR byref V80 tmp50 d:2 N004 ( 6, 14) [000632] ----G------- | | \--* ADD byref N002 ( 4, 12) [000633] n---G------- | | +--* IND ref N001 ( 2, 10) [000634] I----------- | | | \--* CNS_INT(h) long 0xd1ffab1e static Fseq[BigOne] $4c2 N003 ( 1, 1) [000635] ------------ | | \--* CNS_INT long 8 Fseq[#FirstElem] $101 N010 ( 7, 5) [000641] -A-XG---R--- | \--* ASG ref N009 ( 3, 2) [000638] D---G--N---- | +--* LCL_VAR ref (AX) V58 tmp28 N008 ( 3, 2) [000640] ---X-------- | \--* IND ref N007 ( 1, 1) [000639] ------------ | \--* LCL_VAR byref V80 tmp50 u:2 Zero Fseq[_bits] N017 ( 8, 7) [000648] -A-XG---R--- \--* ASG int N016 ( 3, 2) [000643] D---G--N---- +--* LCL_VAR int (AX) V59 tmp29 N015 ( 4, 4) [000647] ---X-------- \--* IND int N014 ( 2, 2) [000646] -------N---- \--* ADD byref N012 ( 1, 1) [000644] ------------ +--* LCL_VAR byref V80 tmp50 u:2 (last use) N013 ( 1, 1) [000645] ------------ \--* CNS_INT long 8 Fseq[_sign] $101 ***** BB23 STMT00031 (IL 0x0F6...0x106) N006 ( 20, 12) [000141] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen $VN.Void N004 ( 3, 3) [000139] ------------ arg0 in rcx +--* ADDR long $40d N003 ( 3, 2) [000138] ----G--N---- | \--* LCL_VAR struct(AX)(P) V16 loc13 | \--* ref V16._bits (offs=0x00) -> V58 tmp28 | \--* int V16._sign (offs=0x08) -> V59 tmp29 $3c9 N005 ( 3, 2) [000140] ------------ arg1 in rdx \--* LCL_VAR int V14 loc11 u:2 (last use) $244 ***** BB23 STMT00099 (IL 0x0FF... ???) N007 ( 14, 10) [000658] -A--G------- * COMMA void $246 N003 ( 7, 5) [000654] -A--G---R--- +--* ASG ref $184 N002 ( 3, 2) [000652] D------N---- | +--* LCL_VAR ref V64 tmp34 d:2 $184 N001 ( 3, 2) [000653] ----G--N---- | \--* LCL_VAR ref (AX) V56 tmp26 $184 N006 ( 7, 5) [000657] -A--G---R--- \--* ASG int $246 N005 ( 3, 2) [000655] D------N---- +--* LCL_VAR int V65 tmp35 d:2 $246 N004 ( 3, 2) [000656] ----G--N---- \--* LCL_VAR int (AX) V57 tmp27 $246 ***** BB23 STMT00098 (IL 0x0FF... ???) N023 ( 45, 31) [000468] -ACXG---R--- * ASG int $29f N022 ( 3, 2) [000467] D------N---- +--* LCL_VAR int V43 tmp13 d:2 $29f N021 ( 41, 28) [000463] -ACXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $29f N016 ( 18, 15) [000677] -A--------L- arg0 SETUP +--* COMMA void $VN.Void N009 ( 10, 8) [000670] -A---------- | +--* COMMA void $VN.Void N004 ( 3, 3) [000665] -A------R--- | | +--* ASG byref $40e N003 ( 1, 1) [000664] D------N---- | | | +--* LCL_VAR byref V81 tmp51 d:2 $40e N002 ( 3, 3) [000662] ------------ | | | \--* ADDR byref $40e N001 ( 3, 2) [000663] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 $3ca N008 ( 7, 5) [000669] -A---------- | | \--* ASG ref $VN.Void N006 ( 3, 2) [000667] *------N---- | | +--* IND ref $184 N005 ( 1, 1) [000666] ------------ | | | \--* LCL_VAR byref V81 tmp51 u:2 Zero Fseq[_bits] $40e N007 ( 3, 2) [000668] -------N---- | | \--* LCL_VAR ref V64 tmp34 u:2 (last use) $184 N015 ( 8, 7) [000676] -A---------- | \--* ASG int $VN.Void N013 ( 4, 4) [000674] *------N---- | +--* IND int $246 N012 ( 2, 2) [000673] -------N---- | | \--* ADD byref $211 N010 ( 1, 1) [000671] ------------ | | +--* LCL_VAR byref V81 tmp51 u:2 (last use) $40e N011 ( 1, 1) [000672] ------------ | | \--* CNS_INT long 8 Fseq[_sign] $101 N014 ( 3, 2) [000675] -------N---- | \--* LCL_VAR int V65 tmp35 u:2 (last use) $246 N019 ( 3, 3) [000679] ------------ arg0 in rcx +--* ADDR byref $410 N018 ( 3, 2) [000678] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 $3cb N020 ( 3, 3) [000462] ------------ arg1 in rdx \--* LCL_VAR_ADDR long V45 tmp15 $449 ***** BB23 STMT00100 (IL 0x0FF... ???) N003 ( 5, 4) [000475] -A--G---R--- * ASG ref $VN.Null N002 ( 3, 2) [000474] D---G--N---- +--* LCL_VAR ref (AX) V45 tmp15 N001 ( 1, 1) [000473] ------------ \--* CNS_INT ref null $VN.Null ***** BB23 STMT00033 (IL ???... ???) N003 ( 7, 5) [000148] -A------R--- * ASG int $29f N002 ( 3, 2) [000147] D------N---- +--* LCL_VAR int V17 loc14 d:2 $29f N001 ( 3, 2) [000469] ------------ \--* LCL_VAR int V43 tmp13 u:2 $29f ***** BB23 STMT00103 (IL 0x108... ???) N007 ( 14, 10) [000687] -A--G------- * COMMA void $247 N003 ( 7, 5) [000683] -A--G---R--- +--* ASG ref $185 N002 ( 3, 2) [000681] D------N---- | +--* LCL_VAR ref V66 tmp36 d:2 $185 N001 ( 3, 2) [000682] ----G--N---- | \--* LCL_VAR ref (AX) V58 tmp28 $185 N006 ( 7, 5) [000686] -A--G---R--- \--* ASG int $247 N005 ( 3, 2) [000684] D------N---- +--* LCL_VAR int V67 tmp37 d:2 $247 N004 ( 3, 2) [000685] ----G--N---- \--* LCL_VAR int (AX) V59 tmp29 $247 ***** BB23 STMT00102 (IL 0x108... ???) N023 ( 45, 31) [000486] -ACXG---R--- * ASG int $2a3 N022 ( 3, 2) [000485] D------N---- +--* LCL_VAR int V46 tmp16 d:2 $2a3 N021 ( 41, 28) [000481] -ACXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $2a3 N016 ( 18, 15) [000706] -A--------L- arg0 SETUP +--* COMMA void $VN.Void N009 ( 10, 8) [000699] -A---------- | +--* COMMA void $VN.Void N004 ( 3, 3) [000694] -A------R--- | | +--* ASG byref $411 N003 ( 1, 1) [000693] D------N---- | | | +--* LCL_VAR byref V82 tmp52 d:2 $411 N002 ( 3, 3) [000691] ------------ | | | \--* ADDR byref $411 N001 ( 3, 2) [000692] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 $3cc N008 ( 7, 5) [000698] -A---------- | | \--* ASG ref $VN.Void N006 ( 3, 2) [000696] *------N---- | | +--* IND ref $185 N005 ( 1, 1) [000695] ------------ | | | \--* LCL_VAR byref V82 tmp52 u:2 Zero Fseq[_bits] $411 N007 ( 3, 2) [000697] -------N---- | | \--* LCL_VAR ref V66 tmp36 u:2 (last use) $185 N015 ( 8, 7) [000705] -A---------- | \--* ASG int $VN.Void N013 ( 4, 4) [000703] *------N---- | +--* IND int $247 N012 ( 2, 2) [000702] -------N---- | | \--* ADD byref $214 N010 ( 1, 1) [000700] ------------ | | +--* LCL_VAR byref V82 tmp52 u:2 (last use) $411 N011 ( 1, 1) [000701] ------------ | | \--* CNS_INT long 8 Fseq[_sign] $101 N014 ( 3, 2) [000704] -------N---- | \--* LCL_VAR int V67 tmp37 u:2 (last use) $247 N019 ( 3, 3) [000708] ------------ arg0 in rcx +--* ADDR byref $413 N018 ( 3, 2) [000707] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 $3cd N020 ( 3, 3) [000480] ------------ arg1 in rdx \--* LCL_VAR_ADDR long V48 tmp18 $44b ***** BB23 STMT00104 (IL 0x108... ???) N003 ( 5, 4) [000493] -A--G---R--- * ASG ref $VN.Null N002 ( 3, 2) [000492] D---G--N---- +--* LCL_VAR ref (AX) V48 tmp18 N001 ( 1, 1) [000491] ------------ \--* CNS_INT ref null $VN.Null ***** BB23 STMT00035 (IL ???... ???) N003 ( 7, 5) [000155] -A------R--- * ASG int $2a3 N002 ( 3, 2) [000154] D------N---- +--* LCL_VAR int V18 loc15 d:2 $2a3 N001 ( 3, 2) [000487] ------------ \--* LCL_VAR int V46 tmp16 u:2 $2a3 ***** BB23 STMT00036 (IL 0x111...0x115) N004 ( 9, 7) [000159] ------------ * JTRUE void N003 ( 7, 5) [000158] N------N-U-- \--* GT int $35f N001 ( 3, 2) [000156] ------------ +--* LCL_VAR int V18 loc15 u:2 (last use) $2a3 N002 ( 3, 2) [000157] ------------ \--* LCL_VAR int V17 loc14 u:2 (last use) $29f ------------ BB24 [117..11A) -> BB26 (always), preds={BB23} succs={BB26} ***** BB24 STMT00074 (IL 0x117...0x118) N003 ( 5, 4) [000350] -A------R--- * ASG int $40 N002 ( 3, 2) [000349] D------N---- +--* LCL_VAR int V33 tmp3 d:4 $40 N001 ( 1, 1) [000348] ------------ \--* CNS_INT int 0 $40 ------------ BB25 [11A..11F), preds={BB23} succs={BB26} ***** BB25 STMT00037 (IL 0x11A...0x11E) N005 ( 11, 8) [000164] -A------R--- * ASG int $360 N004 ( 3, 2) [000163] D------N---- +--* LCL_VAR int V33 tmp3 d:3 $360 N003 ( 7, 5) [000162] ------------ \--* SUB int $360 N001 ( 3, 2) [000160] ------------ +--* LCL_VAR int V18 loc15 u:2 (last use) $2a3 N002 ( 3, 2) [000161] ------------ \--* LCL_VAR int V17 loc14 u:2 (last use) $29f ------------ BB26 [11F..126) -> BB28 (cond), preds={BB24,BB25} succs={BB27,BB28} ***** BB26 STMT00119 (IL ???... ???) N005 ( 0, 0) [000877] -A------R--- * ASG int N004 ( 0, 0) [000875] D------N---- +--* LCL_VAR int V33 tmp3 d:2 N003 ( 0, 0) [000876] ------------ \--* PHI int N001 ( 0, 0) [000903] ------------ pred BB24 +--* PHI_ARG int V33 tmp3 u:4 $40 N002 ( 0, 0) [000902] ------------ pred BB25 \--* PHI_ARG int V33 tmp3 u:3 $360 ***** BB26 STMT00038 (IL ???...0x11F) N003 ( 3, 3) [000168] -A------R--- * ASG int $248 N002 ( 1, 1) [000167] D------N---- +--* LCL_VAR int V19 loc16 d:2 $248 N001 ( 3, 2) [000166] ------------ \--* LCL_VAR int V33 tmp3 u:2 $248 ***** BB26 STMT00039 (IL 0x121...0x124) N004 ( 7, 6) [000172] ------------ * JTRUE void N003 ( 5, 4) [000171] N------N---- \--* EQ int $361 N001 ( 3, 2) [000169] ------------ +--* LCL_VAR int V19 loc16 u:2 (last use) $248 N002 ( 1, 1) [000170] ------------ \--* CNS_INT int 0 $40 ------------ BB27 [126..12F), preds={BB26} succs={BB28} ***** BB27 STMT00073 (IL 0x126...0x12A) N006 ( 18, 11) [000347] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft $VN.Void N004 ( 3, 3) [000345] ------------ arg0 in rcx +--* ADDR long $414 N003 ( 3, 2) [000344] ----G--N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 $3ce N005 ( 1, 1) [000346] ------------ arg1 in rdx \--* LCL_VAR int V19 loc16 u:2 $248 ------------ BB28 [12F..13E) -> BB32 (cond), preds={BB26,BB27} succs={BB29,BB32} ***** BB28 STMT00040 (IL 0x12F...0x133) N005 ( 9, 7) [000177] -A------R--- * ASG int $362 N004 ( 3, 2) [000176] D------N---- +--* LCL_VAR int V20 loc17 d:2 $362 N003 ( 5, 4) [000175] ------------ \--* SUB int $362 N001 ( 3, 2) [000173] ------------ +--* LCL_VAR int V03 loc0 u:2 (last use) $348 N002 ( 1, 1) [000174] ------------ \--* LCL_VAR int V13 loc10 u:2 $293 ***** BB28 STMT00041 (IL 0x135...0x137) N003 ( 7, 5) [000180] -A------R--- * ASG int $362 N002 ( 3, 2) [000179] D------N---- +--* LCL_VAR int V21 loc18 d:2 $362 N001 ( 3, 2) [000178] ------------ \--* LCL_VAR int V20 loc17 u:2 $362 ***** BB28 STMT00042 (IL 0x139...0x13C) N004 ( 5, 5) [000184] ------------ * JTRUE void N003 ( 3, 3) [000183] N------N---- \--* EQ int $363 N001 ( 1, 1) [000181] ------------ +--* LCL_VAR int V13 loc10 u:2 $293 N002 ( 1, 1) [000182] ------------ \--* CNS_INT int 0 $40 ------------ BB29 [13E..144) -> BB31 (cond), preds={BB28} succs={BB30,BB31} ***** BB29 STMT00070 (IL 0x13E...0x142) N004 ( 7, 6) [000329] ------------ * JTRUE void N003 ( 5, 4) [000328] N------N-U-- \--* LE int $364 N001 ( 1, 1) [000326] ------------ +--* LCL_VAR int V19 loc16 u:2 $248 N002 ( 3, 2) [000327] ------------ \--* LCL_VAR int V20 loc17 u:2 $362 ------------ BB30 [144..155) -> BB44 (always), preds={BB29} succs={BB44} ***** BB30 STMT00072 (IL 0x144...0x154) N012 ( 24, 15) [000717] -ACXG---R--- * ASG int $5c2 N011 ( 1, 1) [000716] D------N---- +--* LCL_VAR int V51 tmp21 d:5 $5c2 N010 ( 24, 15) [000342] --CXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits $5c2 N005 ( 1, 1) [000341] ------------ arg4 out+20 +--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N006 ( 1, 1) [000339] ------------ arg2 in r8 +--* CNS_INT int 1 $41 N007 ( 3, 2) [000335] ----G------- arg0 in rcx +--* LCL_VAR ref (AX) V12 loc9 $18c N008 ( 1, 1) [000336] ------------ arg1 in rdx +--* LCL_VAR int V13 loc10 u:2 (last use) $293 N009 ( 1, 1) [000340] ------------ arg3 in r9 \--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 ------------ BB31 [155..15C), preds={BB29} succs={BB32} ***** BB31 STMT00071 (IL 0x155...0x15A) N005 ( 9, 7) [000334] -A------R--- * ASG int $365 N004 ( 3, 2) [000333] D------N---- +--* LCL_VAR int V21 loc18 d:4 $365 N003 ( 5, 4) [000332] ------------ \--* SUB int $365 N001 ( 3, 2) [000330] ------------ +--* LCL_VAR int V20 loc17 u:2 (last use) $362 N002 ( 1, 1) [000331] ------------ \--* LCL_VAR int V19 loc16 u:2 $248 ------------ BB32 [15C..167) -> BB34 (cond), preds={BB28,BB31} succs={BB33,BB34} ***** BB32 STMT00118 (IL ???... ???) N005 ( 0, 0) [000874] -A------R--- * ASG int N004 ( 0, 0) [000872] D------N---- +--* LCL_VAR int V21 loc18 d:3 N003 ( 0, 0) [000873] ------------ \--* PHI int N001 ( 0, 0) [000900] ------------ pred BB31 +--* PHI_ARG int V21 loc18 u:4 $365 N002 ( 0, 0) [000888] ------------ pred BB28 \--* PHI_ARG int V21 loc18 u:2 $362 ***** BB32 STMT00105 (IL 0x15C... ???) N007 ( 14, 10) [000724] -A--G------- * COMMA void $24a N003 ( 7, 5) [000720] -A--G---R--- +--* ASG ref $186 N002 ( 3, 2) [000718] D---G--N---- | +--* LCL_VAR ref (AX) V68 tmp38 N001 ( 3, 2) [000719] ----G--N---- | \--* LCL_VAR ref (AX) V56 tmp26 $186 N006 ( 7, 5) [000723] -A--G---R--- \--* ASG int $24a N005 ( 3, 2) [000721] D---G--N---- +--* LCL_VAR int (AX) V69 tmp39 N004 ( 3, 2) [000722] ----G--N---- \--* LCL_VAR int (AX) V57 tmp27 $24a ***** BB32 STMT00106 (IL 0x15C... ???) N007 ( 14, 10) [000731] -A--G------- * COMMA void $24b N003 ( 7, 5) [000727] -A--G---R--- +--* ASG ref $187 N002 ( 3, 2) [000725] D------N---- | +--* LCL_VAR ref V70 tmp40 d:2 $187 N001 ( 3, 2) [000726] ----G--N---- | \--* LCL_VAR ref (AX) V58 tmp28 $187 N006 ( 7, 5) [000730] -A--G---R--- \--* ASG int $24b N005 ( 3, 2) [000728] D------N---- +--* LCL_VAR int V71 tmp41 d:2 $24b N004 ( 3, 2) [000729] ----G--N---- \--* LCL_VAR int (AX) V59 tmp29 $24b ***** BB32 STMT00044 (IL ???... ???) N027 ( 52, 38) [000195] -ACXG------- * JTRUE void N026 ( 50, 36) [000503] JACXG--N---- \--* LT int $367 N024 ( 48, 34) [000499] -ACXG------- +--* CALL int System.Numerics.BigInteger.CompareTo $2ae N004 ( 7, 6) [000752] -A------R-L- this SETUP | +--* ASG byref $415 N003 ( 3, 2) [000751] D------N---- | | +--* LCL_VAR byref V84 tmp54 d:2 $415 N002 ( 3, 3) [000497] ------------ | | \--* ADDR byref $415 N001 ( 3, 2) [000496] ----G--N---- | | \--* LCL_VAR struct(AX)(P) V49 tmp19 | | \--* ref V49._bits (offs=0x00) -> V68 tmp38 | | \--* int V49._sign (offs=0x08) -> V69 tmp39 $3cf N020 ( 18, 15) [000750] -A--------L- arg1 SETUP | +--* COMMA void $VN.Void N013 ( 10, 8) [000743] -A---------- | | +--* COMMA void $VN.Void N008 ( 3, 3) [000738] -A------R--- | | | +--* ASG byref $417 N007 ( 1, 1) [000737] D------N---- | | | | +--* LCL_VAR byref V83 tmp53 d:2 $417 N006 ( 3, 3) [000735] ------------ | | | | \--* ADDR byref $417 N005 ( 3, 2) [000736] ----G--N---- | | | | \--* LCL_VAR struct(AX) V76 tmp46 $3d0 N012 ( 7, 5) [000742] -A---------- | | | \--* ASG ref $VN.Void N010 ( 3, 2) [000740] *------N---- | | | +--* IND ref $187 N009 ( 1, 1) [000739] ------------ | | | | \--* LCL_VAR byref V83 tmp53 u:2 Zero Fseq[_bits] $417 N011 ( 3, 2) [000741] -------N---- | | | \--* LCL_VAR ref V70 tmp40 u:2 (last use) $187 N019 ( 8, 7) [000749] -A---------- | | \--* ASG int $VN.Void N017 ( 4, 4) [000747] *------N---- | | +--* IND int $24b N016 ( 2, 2) [000746] -------N---- | | | \--* ADD byref $216 N014 ( 1, 1) [000744] ------------ | | | +--* LCL_VAR byref V83 tmp53 u:2 (last use) $417 N015 ( 1, 1) [000745] ------------ | | | \--* CNS_INT long 8 Fseq[_sign] $101 N018 ( 3, 2) [000748] -------N---- | | \--* LCL_VAR int V71 tmp41 u:2 (last use) $24b N021 ( 3, 2) [000753] ------------ this in rcx | +--* LCL_VAR byref V84 tmp54 u:2 (last use) $415 N023 ( 3, 3) [000755] ------------ arg1 in rdx | \--* ADDR byref $419 N022 ( 3, 2) [000754] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 $3d1 N025 ( 1, 1) [000502] ------------ \--* CNS_INT int 0 $40 ------------ BB33 [167..16B) -> BB35 (always), preds={BB32} succs={BB35} ***** BB33 STMT00069 (IL 0x167...0x169) N003 ( 5, 4) [000324] -A------R--- * ASG int $248 N002 ( 3, 2) [000323] D------N---- +--* LCL_VAR int V34 tmp4 d:4 $248 N001 ( 1, 1) [000322] ------------ \--* LCL_VAR int V19 loc16 u:2 (last use) $248 ------------ BB34 [16B..16F), preds={BB32} succs={BB35} ***** BB34 STMT00045 (IL 0x16B...0x16E) N005 ( 7, 6) [000200] -A------R--- * ASG int $368 N004 ( 3, 2) [000199] D------N---- +--* LCL_VAR int V34 tmp4 d:3 $368 N003 ( 3, 3) [000198] ------------ \--* ADD int $368 N001 ( 1, 1) [000196] ------------ +--* LCL_VAR int V19 loc16 u:2 (last use) $248 N002 ( 1, 1) [000197] ------------ \--* CNS_INT int 1 $41 ------------ BB35 [16F..1A4) -> BB40 (cond), preds={BB33,BB34} succs={BB36,BB40} ***** BB35 STMT00117 (IL ???... ???) N005 ( 0, 0) [000871] -A------R--- * ASG int N004 ( 0, 0) [000869] D------N---- +--* LCL_VAR int V34 tmp4 d:2 N003 ( 0, 0) [000870] ------------ \--* PHI int N001 ( 0, 0) [000899] ------------ pred BB33 +--* PHI_ARG int V34 tmp4 u:4 $248 N002 ( 0, 0) [000898] ------------ pred BB34 \--* PHI_ARG int V34 tmp4 u:3 $368 ***** BB35 STMT00046 (IL ???...0x16F) N003 ( 7, 5) [000204] -A------R--- * ASG int $24c N002 ( 3, 2) [000203] D------N---- +--* LCL_VAR int V22 loc19 d:2 $24c N001 ( 3, 2) [000202] ------------ \--* LCL_VAR int V34 tmp4 u:2 (last use) $24c ***** BB35 STMT00047 (IL 0x171...0x18A) N006 ( 20, 12) [000208] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft $VN.Void N004 ( 3, 3) [000206] ------------ arg0 in rcx +--* ADDR long $41a N003 ( 3, 2) [000205] ----G--N---- | \--* LCL_VAR struct(AX)(P) V15 loc12 | \--* ref V15._bits (offs=0x00) -> V56 tmp26 | \--* int V15._sign (offs=0x08) -> V57 tmp27 $3d2 N005 ( 3, 2) [000207] ------------ arg1 in rdx \--* LCL_VAR int V21 loc18 u:3 (last use) $249 ***** BB35 STMT00048 (IL 0x17A... ???) N045 ( 78, 56) [000213] SACXG------- * CALL void System.Numerics.BigInteger.DivRem $VN.Void N004 ( 7, 6) [000797] -A------R-L- arg0 SETUP +--* ASG long $41b N003 ( 3, 2) [000796] D------N---- | +--* LCL_VAR long V88 tmp58 d:2 $41b N002 ( 3, 3) [000220] ------------ | \--* ADDR long $41b N001 ( 3, 2) [000219] ----G--N---- | \--* LCL_VAR struct(AX)(P) V35 tmp5 | \--* ref V35._bits (offs=0x00) -> V62 tmp32 | \--* int V35._sign (offs=0x08) -> V63 tmp33 $3d3 N020 ( 18, 15) [000776] -A--G-----L- arg1 SETUP +--* COMMA void $VN.Void N013 ( 10, 8) [000769] -A--G------- | +--* COMMA void $VN.Void N008 ( 3, 3) [000764] -A------R--- | | +--* ASG byref $41c N007 ( 1, 1) [000763] D------N---- | | | +--* LCL_VAR byref V85 tmp55 d:2 $41c N006 ( 3, 3) [000761] ------------ | | | \--* ADDR byref $41c N005 ( 3, 2) [000762] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 $3d4 N012 ( 7, 5) [000768] -A--G------- | | \--* ASG ref $VN.Void N010 ( 3, 2) [000766] *------N---- | | +--* IND ref $188 N009 ( 1, 1) [000765] ------------ | | | \--* LCL_VAR byref V85 tmp55 u:2 Zero Fseq[_bits] $41c N011 ( 3, 2) [000767] ----G--N---- | | \--* LCL_VAR ref (AX) V56 tmp26 $188 N019 ( 8, 7) [000775] -A--G------- | \--* ASG int $VN.Void N017 ( 4, 4) [000773] *------N---- | +--* IND int $24d N016 ( 2, 2) [000772] -------N---- | | \--* ADD byref $218 N014 ( 1, 1) [000770] ------------ | | +--* LCL_VAR byref V85 tmp55 u:2 (last use) $41c N015 ( 1, 1) [000771] ------------ | | \--* CNS_INT long 8 Fseq[_sign] $101 N018 ( 3, 2) [000774] ----G--N---- | \--* LCL_VAR int (AX) V57 tmp27 $24d N036 ( 18, 15) [000795] -A--G-----L- arg2 SETUP +--* COMMA void $VN.Void N029 ( 10, 8) [000788] -A--G------- | +--* COMMA void $VN.Void N024 ( 3, 3) [000783] -A------R--- | | +--* ASG byref $41e N023 ( 1, 1) [000782] D------N---- | | | +--* LCL_VAR byref V87 tmp57 d:2 $41e N022 ( 3, 3) [000780] ------------ | | | \--* ADDR byref $41e N021 ( 3, 2) [000781] -------N---- | | | \--* LCL_VAR struct(AX) V86 tmp56 $3d5 N028 ( 7, 5) [000787] -A--G------- | | \--* ASG ref $VN.Void N026 ( 3, 2) [000785] *------N---- | | +--* IND ref $189 N025 ( 1, 1) [000784] ------------ | | | \--* LCL_VAR byref V87 tmp57 u:2 Zero Fseq[_bits] $41e N027 ( 3, 2) [000786] ----G--N---- | | \--* LCL_VAR ref (AX) V58 tmp28 $189 N035 ( 8, 7) [000794] -A--G------- | \--* ASG int $VN.Void N033 ( 4, 4) [000792] *------N---- | +--* IND int $24e N032 ( 2, 2) [000791] -------N---- | | \--* ADD byref $21a N030 ( 1, 1) [000789] ------------ | | +--* LCL_VAR byref V87 tmp57 u:2 (last use) $41e N031 ( 1, 1) [000790] ------------ | | \--* CNS_INT long 8 Fseq[_sign] $101 N034 ( 3, 2) [000793] ----G--N---- | \--* LCL_VAR int (AX) V59 tmp29 $24e N038 ( 3, 2) [000798] ------------ arg0 in rcx +--* LCL_VAR long V88 tmp58 u:2 (last use) $41b N040 ( 3, 3) [000800] ------------ arg1 in rdx +--* ADDR byref $420 N039 ( 3, 2) [000799] -------N---- | \--* LCL_VAR struct(AX) V76 tmp46 $3d6 N042 ( 3, 3) [000802] ------------ arg2 in r8 +--* ADDR byref $421 N041 ( 3, 2) [000801] -------N---- | \--* LCL_VAR struct(AX) V86 tmp56 $3d7 N044 ( 3, 3) [000212] ------------ arg3 in r9 \--* ADDR long $422 N043 ( 3, 2) [000211] ----G--N---- \--* LCL_VAR struct(AX)(P) V23 loc20 \--* ref V23._bits (offs=0x00) -> V60 tmp30 \--* int V23._sign (offs=0x08) -> V61 tmp31 $3d8 ***** BB35 STMT00050 (IL ???... ???) N021 ( 38, 24) [000226] -ACXG---R--- * ASG long $450 N020 ( 1, 1) [000225] D------N---- +--* LCL_VAR long V24 loc21 d:2 $450 N019 ( 38, 24) [000218] -ACXG------- \--* CALL long System.Numerics.BigInteger.op_Explicit $450 N016 ( 18, 15) [000822] -A--G-----L- arg0 SETUP +--* COMMA void $VN.Void N009 ( 10, 8) [000815] -A--G------- | +--* COMMA void $VN.Void N004 ( 3, 3) [000810] -A------R--- | | +--* ASG byref $423 N003 ( 1, 1) [000809] D------N---- | | | +--* LCL_VAR byref V89 tmp59 d:2 $423 N002 ( 3, 3) [000807] ------------ | | | \--* ADDR byref $423 N001 ( 3, 2) [000808] ----G--N---- | | | \--* LCL_VAR struct(AX) V76 tmp46 $3d9 N008 ( 7, 5) [000814] -A--G------- | | \--* ASG ref $VN.Void N006 ( 3, 2) [000812] *------N---- | | +--* IND ref $18a N005 ( 1, 1) [000811] ------------ | | | \--* LCL_VAR byref V89 tmp59 u:2 Zero Fseq[_bits] $423 N007 ( 3, 2) [000813] ----G--N---- | | \--* LCL_VAR ref (AX) V62 tmp32 $18a N015 ( 8, 7) [000821] -A--G------- | \--* ASG int $VN.Void N013 ( 4, 4) [000819] *------N---- | +--* IND int $24f N012 ( 2, 2) [000818] -------N---- | | \--* ADD byref $21d N010 ( 1, 1) [000816] ------------ | | +--* LCL_VAR byref V89 tmp59 u:2 (last use) $423 N011 ( 1, 1) [000817] ------------ | | \--* CNS_INT long 8 Fseq[_sign] $101 N014 ( 3, 2) [000820] ----G--N---- | \--* LCL_VAR int (AX) V63 tmp33 $24f N018 ( 3, 3) [000824] ------------ arg0 in rcx \--* ADDR byref $425 N017 ( 3, 2) [000823] -------N---- \--* LCL_VAR struct(AX) V76 tmp46 $3da ***** BB35 STMT00052 (IL ???... ???) N005 ( 12, 7) [000232] -A--G---R--- * ASG int $369 N004 ( 3, 2) [000231] D------N---- +--* LCL_VAR int V25 loc22 d:2 $369 N003 ( 8, 4) [000516] ----G------- \--* EQ int $369 N001 ( 3, 2) [000514] ----G------- +--* LCL_VAR int (AX) V61 tmp31 $250 N002 ( 1, 1) [000515] ------------ \--* CNS_INT int 0 $40 ***** BB35 STMT00054 (IL ???... ???) N005 ( 19, 10) [000237] -ACXG---R--- * ASG int $2b4 N004 ( 3, 2) [000236] D------N---- +--* LCL_VAR int V26 loc23 d:2 $2b4 N003 ( 15, 7) [000234] --CXG------- \--* CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $2b4 N002 ( 1, 1) [000233] ------------ arg0 in rcx \--* LCL_VAR long V24 loc21 u:2 $450 ***** BB35 STMT00055 (IL 0x19E...0x1A2) N004 ( 9, 7) [000241] ------------ * JTRUE void N003 ( 7, 5) [000240] N------N-U-- \--* LE int $36a N001 ( 3, 2) [000238] ------------ +--* LCL_VAR int V26 loc23 u:2 $2b4 N002 ( 3, 2) [000239] ------------ \--* LCL_VAR int V20 loc17 u:2 $362 ------------ BB36 [1A4..1AF) -> BB38 (cond), preds={BB35} succs={BB37,BB38} ***** BB36 STMT00063 (IL 0x1A4...0x1A9) N005 ( 11, 8) [000286] -A------R--- * ASG int $36b N004 ( 3, 2) [000285] D------N---- +--* LCL_VAR int V29 loc26 d:2 $36b N003 ( 7, 5) [000284] ------------ \--* SUB int $36b N001 ( 3, 2) [000282] ------------ +--* LCL_VAR int V26 loc23 u:2 (last use) $2b4 N002 ( 3, 2) [000283] ------------ \--* LCL_VAR int V20 loc17 u:2 $362 ***** BB36 STMT00064 (IL 0x1AB...0x1AD) N004 ( 7, 6) [000290] ------------ * JTRUE void N003 ( 5, 4) [000289] J------N---- \--* EQ int $36c N001 ( 3, 2) [000287] ------------ +--* LCL_VAR int V25 loc22 u:2 (last use) $369 N002 ( 1, 1) [000288] ------------ \--* CNS_INT int 0 $40 ------------ BB37 [1AF..1C3) -> BB39 (always), preds={BB36} succs={BB39} ***** BB37 STMT00068 (IL 0x1AF...0x1C1) N013 ( 23, 15) [000320] -A------R--- * ASG int $36e N012 ( 3, 2) [000319] D------N---- +--* LCL_VAR int V37 tmp7 d:4 $36e N011 ( 19, 12) [000318] ------------ \--* EQ int $36e N009 ( 14, 10) [000315] ------------ +--* AND long $490 N001 ( 1, 1) [000305] ------------ | +--* LCL_VAR long V24 loc21 u:2 $450 N008 ( 12, 8) [000314] ------------ | \--* ADD long $48f N006 ( 10, 6) [000311] --------R--- | +--* LSH long $48e N005 ( 1, 1) [000307] ------------ | | +--* CNS_INT long 1 $103 N004 ( 5, 4) [000310] ------------ | | \--* AND int $36d N002 ( 3, 2) [000308] ------------ | | +--* LCL_VAR int V29 loc26 u:2 $36b N003 ( 1, 1) [000309] ------------ | | \--* CNS_INT int 63 $66 N007 ( 1, 1) [000313] ------------ | \--* CNS_INT long -1 $104 N010 ( 1, 1) [000317] ------------ \--* CNS_INT long 0 $100 ------------ BB38 [1C3..1C4), preds={BB36} succs={BB39} ***** BB38 STMT00065 (IL 0x1C3...0x1C3) N003 ( 5, 4) [000293] -A------R--- * ASG int $40 N002 ( 3, 2) [000292] D------N---- +--* LCL_VAR int V37 tmp7 d:3 $40 N001 ( 1, 1) [000291] ------------ \--* CNS_INT int 0 $40 ------------ BB39 [1C4..1D0), preds={BB37,BB38} succs={BB40} ***** BB39 STMT00116 (IL ???... ???) N005 ( 0, 0) [000868] -A------R--- * ASG int N004 ( 0, 0) [000866] D------N---- +--* LCL_VAR int V37 tmp7 d:2 N003 ( 0, 0) [000867] ------------ \--* PHI int N001 ( 0, 0) [000897] ------------ pred BB37 +--* PHI_ARG int V37 tmp7 u:4 $36e N002 ( 0, 0) [000896] ------------ pred BB38 \--* PHI_ARG int V37 tmp7 u:3 $40 ***** BB39 STMT00066 (IL ???...0x1C4) N004 ( 8, 7) [000297] -A------R--- * ASG int $36f N003 ( 3, 2) [000296] D------N---- +--* LCL_VAR int V25 loc22 d:4 $36f N002 ( 4, 4) [000826] ------------ \--* CAST int <- bool <- int $36f N001 ( 3, 2) [000295] ------------ \--* LCL_VAR int V37 tmp7 u:2 (last use) $251 ***** BB39 STMT00067 (IL 0x1C6...0x1CE) N007 ( 10, 6) [000304] -A------R--- * ASG long $491 N006 ( 1, 1) [000303] D------N---- +--* LCL_VAR long V24 loc21 d:4 $491 N005 ( 10, 6) [000302] ------------ \--* RSZ long $491 N001 ( 1, 1) [000298] ------------ +--* LCL_VAR long V24 loc21 u:2 (last use) $450 N004 ( 5, 4) [000301] ------------ \--* AND int $36d N002 ( 3, 2) [000299] ------------ +--* LCL_VAR int V29 loc26 u:2 (last use) $36b N003 ( 1, 1) [000300] ------------ \--* CNS_INT int 63 $66 ------------ BB40 [1D0..1E7) -> BB42 (cond), preds={BB35,BB39} succs={BB41,BB42} ***** BB40 STMT00115 (IL ???... ???) N005 ( 0, 0) [000865] -A------R--- * ASG bool N004 ( 0, 0) [000863] D------N---- +--* LCL_VAR bool V25 loc22 d:3 N003 ( 0, 0) [000864] ------------ \--* PHI bool N001 ( 0, 0) [000894] ------------ pred BB39 +--* PHI_ARG bool V25 loc22 u:4 $36f N002 ( 0, 0) [000889] ------------ pred BB35 \--* PHI_ARG bool V25 loc22 u:2 $369 ***** BB40 STMT00114 (IL ???... ???) N005 ( 0, 0) [000862] -A------R--- * ASG long N004 ( 0, 0) [000860] D------N---- +--* LCL_VAR long V24 loc21 d:3 N003 ( 0, 0) [000861] ------------ \--* PHI long N001 ( 0, 0) [000895] ------------ pred BB39 +--* PHI_ARG long V24 loc21 u:4 $491 N002 ( 0, 0) [000890] ------------ pred BB35 \--* PHI_ARG long V24 loc21 u:2 $450 ***** BB40 STMT00057 (IL ???... ???) N027 ( 53, 34) [000254] -ACXG---R--- * ASG long $493 N026 ( 3, 2) [000253] D------N---- +--* LCL_VAR long V27 loc24 d:2 $493 N025 ( 49, 31) [000252] -ACXG------- \--* ADD long $493 N023 ( 47, 29) [000250] -ACXG------- +--* LSH long $492 N019 ( 38, 24) [000243] -ACXG------- | +--* CALL long System.Numerics.BigInteger.op_Explicit $454 N016 ( 18, 15) [000845] -A--G-----L- arg0 SETUP | | +--* COMMA void $VN.Void N009 ( 10, 8) [000838] -A--G------- | | | +--* COMMA void $VN.Void N004 ( 3, 3) [000833] -A------R--- | | | | +--* ASG byref $426 N003 ( 1, 1) [000832] D------N---- | | | | | +--* LCL_VAR byref V90 tmp60 d:2 $426 N002 ( 3, 3) [000830] ------------ | | | | | \--* ADDR byref $426 N001 ( 3, 2) [000831] ----G--N---- | | | | | \--* LCL_VAR struct(AX) V76 tmp46 $3db N008 ( 7, 5) [000837] -A--G------- | | | | \--* ASG ref $VN.Void N006 ( 3, 2) [000835] *------N---- | | | | +--* IND ref $18b N005 ( 1, 1) [000834] ------------ | | | | | \--* LCL_VAR byref V90 tmp60 u:2 Zero Fseq[_bits] $426 N007 ( 3, 2) [000836] ----G--N---- | | | | \--* LCL_VAR ref (AX) V54 tmp24 $18b N015 ( 8, 7) [000844] -A--G------- | | | \--* ASG int $VN.Void N013 ( 4, 4) [000842] *------N---- | | | +--* IND int $252 N012 ( 2, 2) [000841] -------N---- | | | | \--* ADD byref $220 N010 ( 1, 1) [000839] ------------ | | | | +--* LCL_VAR byref V90 tmp60 u:2 (last use) $426 N011 ( 1, 1) [000840] ------------ | | | | \--* CNS_INT long 8 Fseq[_sign] $101 N014 ( 3, 2) [000843] ----G--N---- | | | \--* LCL_VAR int (AX) V55 tmp25 $252 N018 ( 3, 3) [000847] ------------ arg0 in rcx | | \--* ADDR byref $428 N017 ( 3, 2) [000846] -------N---- | | \--* LCL_VAR struct(AX) V76 tmp46 $3dc N022 ( 5, 4) [000249] ------------ | \--* AND int $370 N020 ( 3, 2) [000247] ------------ | +--* LCL_VAR int V20 loc17 u:2 (last use) $362 N021 ( 1, 1) [000248] ------------ | \--* CNS_INT int 63 $66 N024 ( 1, 1) [000251] ------------ \--* LCL_VAR long V24 loc21 u:3 (last use) $580 ***** BB40 STMT00058 (IL 0x1E2...0x1E5) N004 ( 5, 5) [000258] ------------ * JTRUE void N003 ( 3, 3) [000257] N------N---- \--* NE int $35a N001 ( 1, 1) [000255] ------------ +--* LCL_VAR int V13 loc10 u:2 $293 N002 ( 1, 1) [000256] ------------ \--* CNS_INT int 0 $40 ------------ BB41 [1E7..1EE) -> BB43 (always), preds={BB40} succs={BB43} ***** BB41 STMT00062 (IL 0x1E7...0x1EC) N006 ( 10, 8) [000280] -A------R--- * ASG int $372 N005 ( 3, 2) [000279] D------N---- +--* LCL_VAR int V36 tmp6 d:4 $372 N004 ( 6, 5) [000278] ------------ \--* ADD int $372 N002 ( 4, 3) [000276] ------------ +--* NEG int $2c2 N001 ( 3, 2) [000275] ------------ | \--* LCL_VAR int V22 loc19 u:2 (last use) $24c N003 ( 1, 1) [000277] ------------ \--* CNS_INT int -1 $43 ------------ BB42 [1EE..1F2), preds={BB40} succs={BB43} ***** BB42 STMT00059 (IL 0x1EE...0x1F1) N005 ( 7, 6) [000263] -A------R--- * ASG int $371 N004 ( 3, 2) [000262] D------N---- +--* LCL_VAR int V36 tmp6 d:3 $371 N003 ( 3, 3) [000261] ------------ \--* ADD int $371 N001 ( 1, 1) [000259] ------------ +--* LCL_VAR int V13 loc10 u:2 (last use) $293 N002 ( 1, 1) [000260] ------------ \--* CNS_INT int -2 $68 ------------ BB43 [1F2..202), preds={BB41,BB42} succs={BB44} ***** BB43 STMT00113 (IL ???... ???) N005 ( 0, 0) [000859] -A------R--- * ASG int N004 ( 0, 0) [000857] D------N---- +--* LCL_VAR int V36 tmp6 d:2 N003 ( 0, 0) [000858] ------------ \--* PHI int N001 ( 0, 0) [000893] ------------ pred BB41 +--* PHI_ARG int V36 tmp6 u:4 $372 N002 ( 0, 0) [000892] ------------ pred BB42 \--* PHI_ARG int V36 tmp6 u:3 $371 ***** BB43 STMT00061 (IL 0x1F4...0x201) N012 ( 28, 18) [000853] -ACXG---R--- * ASG int $2be N011 ( 1, 1) [000852] D------N---- +--* LCL_VAR int V51 tmp21 d:4 $2be N010 ( 28, 18) [000273] --CXG------- \--* CALL int FloatingPointType.AssembleFloatingPointValue $2be N005 ( 1, 1) [000272] ------------ arg4 out+20 +--* LCL_VAR byref V02 arg2 u:1 (last use) $81 N006 ( 1, 1) [000268] ------------ this in rcx +--* LCL_VAR ref V01 arg1 u:1 (last use) $c0 N007 ( 3, 2) [000269] ------------ arg1 in rdx +--* LCL_VAR long V27 loc24 u:2 (last use) $493 N008 ( 3, 2) [000270] ------------ arg2 in r8 +--* LCL_VAR int V36 tmp6 u:2 (last use) $253 N009 ( 3, 2) [000271] ------------ arg3 in r9 \--* LCL_VAR int V25 loc22 u:3 (last use) $540 ------------ BB44 [???..???) (return), preds={BB16,BB30,BB43} succs={} ***** BB44 STMT00112 (IL ???... ???) N006 ( 0, 0) [000856] -A------R--- * ASG int N005 ( 0, 0) [000854] D------N---- +--* LCL_VAR int V51 tmp21 d:2 N004 ( 0, 0) [000855] ------------ \--* PHI int N001 ( 0, 0) [000901] ------------ pred BB30 +--* PHI_ARG int V51 tmp21 u:5 $5c2 N002 ( 0, 0) [000891] ------------ pred BB43 +--* PHI_ARG int V51 tmp21 u:4 $2be N003 ( 0, 0) [000887] ------------ pred BB16 \--* PHI_ARG int V51 tmp21 u:3 $5c7 ***** BB44 STMT00109 (IL ???... ???) N002 ( 2, 2) [000523] ------------ * RETURN int $5c9 N001 ( 1, 1) [000522] -------N---- \--* LCL_VAR int V51 tmp21 u:2 (last use) $254 ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Rationalize IR rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 3, 3) [000533] DA---------- * STORE_LCL_VAR ref V52 tmp22 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N010 ( 4, 4) [000539] DA---------- * STORE_LCL_VAR int V53 tmp23 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N010 ( 30, 19) [000013] DACXG------- * STORE_LCL_VAR int V03 loc0 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000424] DA--G------- * STORE_LCL_VAR int V40 tmp10 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 7, 5) [000421] DA---------- * STORE_LCL_VAR int V39 tmp9 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000417] DA---------- * STORE_LCL_VAR int V39 tmp9 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [000886] DA---------- * STORE_LCL_VAR int V39 tmp9 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 3, 3) [000021] DA---------- * STORE_LCL_VAR int V31 tmp1 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 3, 3) [000443] DA-XG------- * STORE_LCL_VAR int V42 tmp12 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000440] DA---------- * STORE_LCL_VAR int V41 tmp11 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000436] DA---------- * STORE_LCL_VAR int V41 tmp11 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [000883] DA---------- * STORE_LCL_VAR int V41 tmp11 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 7, 6) [000035] DA---------- * STORE_LCL_VAR int V05 loc2 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000044] DA---------- * STORE_LCL_VAR int V08 loc5 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 7, 6) [000050] DA-XG------- * STORE_LCL_VAR int V09 loc6 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 5, 4) [000055] DA---------- * STORE_LCL_VAR int V10 loc7 d:2 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N001 ( 3, 2) [000063] -------N---- t63 = LCL_VAR_ADDR byref V11 loc8 * ref V11._bits (offs=0x00) -> V54 tmp24 * int V11._sign (offs=0x08) -> V55 tmp25 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 7, 6) [000563] DA--------L- * STORE_LCL_VAR long V75 tmp45 d:2 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N005 ( 3, 2) [000547] -------N---- t547 = LCL_VAR_ADDR byref V73 tmp43 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N008 ( 3, 3) [000549] DA---------- * STORE_LCL_VAR byref V74 tmp44 d:2 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N024 ( 3, 2) [000565] -------N---- t565 = LCL_VAR_ADDR byref V73 tmp43 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N003 ( 3, 2) [000388] -------N---- t388 = LCL_VAR_ADDR byref V11 loc8 * ref V11._bits (offs=0x00) -> V54 tmp24 * int V11._sign (offs=0x08) -> V55 tmp25 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N001 ( 3, 2) [000577] -------N---- t577 = LCL_VAR_ADDR byref V76 tmp46 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 3, 3) [000579] DA---------- * STORE_LCL_VAR byref V77 tmp47 d:2 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N018 ( 3, 2) [000592] -------N---- t592 = LCL_VAR_ADDR byref V76 tmp46 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N023 ( 41, 28) [000077] DACXG------- * STORE_LCL_VAR int V13 loc10 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N014 ( 29, 17) [000600] DACXG------- * STORE_LCL_VAR int V51 tmp21 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000378] DA---------- * STORE_LCL_VAR int V32 tmp2 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 7, 6) [000108] DA--G------- * STORE_LCL_VAR int V32 tmp2 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [000880] DA---------- * STORE_LCL_VAR int V32 tmp2 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 7, 5) [000112] DA---------- * STORE_LCL_VAR int V14 loc11 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N008 ( 13, 13) [000363] DA-XG------- * STORE_LCL_VAR long V38 tmp8 d:2 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N001 ( 3, 2) [000124] -------N---- t124 = LCL_VAR_ADDR byref V15 loc12 * ref V15._bits (offs=0x00) -> V56 tmp26 * int V15._sign (offs=0x08) -> V57 tmp27 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 7, 6) [000623] DA--------L- * STORE_LCL_VAR long V79 tmp49 d:2 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N005 ( 3, 2) [000607] -------N---- t607 = LCL_VAR_ADDR byref V73 tmp43 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N008 ( 3, 3) [000609] DA---------- * STORE_LCL_VAR byref V78 tmp48 d:2 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N024 ( 3, 2) [000625] -------N---- t625 = LCL_VAR_ADDR byref V73 tmp43 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 6, 14) [000637] DA--G------- * STORE_LCL_VAR byref V80 tmp50 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N010 ( 7, 5) [000641] DA-XG------- * STORE_LCL_VAR ref (AX) V58 tmp28 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N017 ( 8, 7) [000648] DA-XG------- * STORE_LCL_VAR int (AX) V59 tmp29 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N003 ( 3, 2) [000138] -------N---- t138 = LCL_VAR_ADDR byref V16 loc13 * ref V16._bits (offs=0x00) -> V58 tmp28 * int V16._sign (offs=0x08) -> V59 tmp29 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 7, 5) [000654] DA--G------- * STORE_LCL_VAR ref V64 tmp34 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 7, 5) [000657] DA--G------- * STORE_LCL_VAR int V65 tmp35 d:2 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N001 ( 3, 2) [000663] -------N---- t663 = LCL_VAR_ADDR byref V76 tmp46 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 3, 3) [000665] DA---------- * STORE_LCL_VAR byref V81 tmp51 d:2 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N018 ( 3, 2) [000678] -------N---- t678 = LCL_VAR_ADDR byref V76 tmp46 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N023 ( 45, 31) [000468] DACXG------- * STORE_LCL_VAR int V43 tmp13 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000475] DA--G------- * STORE_LCL_VAR ref (AX) V45 tmp15 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 7, 5) [000148] DA---------- * STORE_LCL_VAR int V17 loc14 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 7, 5) [000683] DA--G------- * STORE_LCL_VAR ref V66 tmp36 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 7, 5) [000686] DA--G------- * STORE_LCL_VAR int V67 tmp37 d:2 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N001 ( 3, 2) [000692] -------N---- t692 = LCL_VAR_ADDR byref V76 tmp46 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 3, 3) [000694] DA---------- * STORE_LCL_VAR byref V82 tmp52 d:2 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N018 ( 3, 2) [000707] -------N---- t707 = LCL_VAR_ADDR byref V76 tmp46 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N023 ( 45, 31) [000486] DACXG------- * STORE_LCL_VAR int V46 tmp16 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000493] DA--G------- * STORE_LCL_VAR ref (AX) V48 tmp18 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 7, 5) [000155] DA---------- * STORE_LCL_VAR int V18 loc15 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000350] DA---------- * STORE_LCL_VAR int V33 tmp3 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 11, 8) [000164] DA---------- * STORE_LCL_VAR int V33 tmp3 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [000877] DA---------- * STORE_LCL_VAR int V33 tmp3 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 3, 3) [000168] DA---------- * STORE_LCL_VAR int V19 loc16 d:2 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N003 ( 3, 2) [000344] -------N---- t344 = LCL_VAR_ADDR byref V15 loc12 * ref V15._bits (offs=0x00) -> V56 tmp26 * int V15._sign (offs=0x08) -> V57 tmp27 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 9, 7) [000177] DA---------- * STORE_LCL_VAR int V20 loc17 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 7, 5) [000180] DA---------- * STORE_LCL_VAR int V21 loc18 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N012 ( 24, 15) [000717] DACXG------- * STORE_LCL_VAR int V51 tmp21 d:5 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 9, 7) [000334] DA---------- * STORE_LCL_VAR int V21 loc18 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [000874] DA---------- * STORE_LCL_VAR int V21 loc18 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 7, 5) [000720] DA--G------- * STORE_LCL_VAR ref (AX) V68 tmp38 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 7, 5) [000723] DA--G------- * STORE_LCL_VAR int (AX) V69 tmp39 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 7, 5) [000727] DA--G------- * STORE_LCL_VAR ref V70 tmp40 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 7, 5) [000730] DA--G------- * STORE_LCL_VAR int V71 tmp41 d:2 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N001 ( 3, 2) [000496] -------N---- t496 = LCL_VAR_ADDR byref V49 tmp19 * ref V49._bits (offs=0x00) -> V68 tmp38 * int V49._sign (offs=0x08) -> V69 tmp39 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 7, 6) [000752] DA--------L- * STORE_LCL_VAR byref V84 tmp54 d:2 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N005 ( 3, 2) [000736] -------N---- t736 = LCL_VAR_ADDR byref V76 tmp46 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N008 ( 3, 3) [000738] DA---------- * STORE_LCL_VAR byref V83 tmp53 d:2 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N022 ( 3, 2) [000754] -------N---- t754 = LCL_VAR_ADDR byref V76 tmp46 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000324] DA---------- * STORE_LCL_VAR int V34 tmp4 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 7, 6) [000200] DA---------- * STORE_LCL_VAR int V34 tmp4 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [000871] DA---------- * STORE_LCL_VAR int V34 tmp4 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 7, 5) [000204] DA---------- * STORE_LCL_VAR int V22 loc19 d:2 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N003 ( 3, 2) [000205] -------N---- t205 = LCL_VAR_ADDR byref V15 loc12 * ref V15._bits (offs=0x00) -> V56 tmp26 * int V15._sign (offs=0x08) -> V57 tmp27 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N001 ( 3, 2) [000219] -------N---- t219 = LCL_VAR_ADDR byref V35 tmp5 * ref V35._bits (offs=0x00) -> V62 tmp32 * int V35._sign (offs=0x08) -> V63 tmp33 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 7, 6) [000797] DA--------L- * STORE_LCL_VAR long V88 tmp58 d:2 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N005 ( 3, 2) [000762] -------N---- t762 = LCL_VAR_ADDR byref V76 tmp46 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N008 ( 3, 3) [000764] DA---------- * STORE_LCL_VAR byref V85 tmp55 d:2 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N021 ( 3, 2) [000781] -------N---- t781 = LCL_VAR_ADDR byref V86 tmp56 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N024 ( 3, 3) [000783] DA---------- * STORE_LCL_VAR byref V87 tmp57 d:2 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N039 ( 3, 2) [000799] -------N---- t799 = LCL_VAR_ADDR byref V76 tmp46 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N041 ( 3, 2) [000801] -------N---- t801 = LCL_VAR_ADDR byref V86 tmp56 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N043 ( 3, 2) [000211] -------N---- t211 = LCL_VAR_ADDR byref V23 loc20 * ref V23._bits (offs=0x00) -> V60 tmp30 * int V23._sign (offs=0x08) -> V61 tmp31 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N001 ( 3, 2) [000808] -------N---- t808 = LCL_VAR_ADDR byref V76 tmp46 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 3, 3) [000810] DA---------- * STORE_LCL_VAR byref V89 tmp59 d:2 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N017 ( 3, 2) [000823] -------N---- t823 = LCL_VAR_ADDR byref V76 tmp46 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N021 ( 38, 24) [000226] DACXG------- * STORE_LCL_VAR long V24 loc21 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 12, 7) [000232] DA--G------- * STORE_LCL_VAR int V25 loc22 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 19, 10) [000237] DACXG------- * STORE_LCL_VAR int V26 loc23 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 11, 8) [000286] DA---------- * STORE_LCL_VAR int V29 loc26 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N013 ( 23, 15) [000320] DA---------- * STORE_LCL_VAR int V37 tmp7 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000293] DA---------- * STORE_LCL_VAR int V37 tmp7 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [000868] DA---------- * STORE_LCL_VAR int V37 tmp7 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 8, 7) [000297] DA---------- * STORE_LCL_VAR int V25 loc22 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N007 ( 10, 6) [000304] DA---------- * STORE_LCL_VAR long V24 loc21 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [000865] DA---------- * STORE_LCL_VAR bool V25 loc22 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [000862] DA---------- * STORE_LCL_VAR long V24 loc21 d:3 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N001 ( 3, 2) [000831] -------N---- t831 = LCL_VAR_ADDR byref V76 tmp46 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 3, 3) [000833] DA---------- * STORE_LCL_VAR byref V90 tmp60 d:2 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N017 ( 3, 2) [000846] -------N---- t846 = LCL_VAR_ADDR byref V76 tmp46 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N027 ( 53, 34) [000254] DACXG------- * STORE_LCL_VAR long V27 loc24 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 10, 8) [000280] DA---------- * STORE_LCL_VAR int V36 tmp6 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 7, 6) [000263] DA---------- * STORE_LCL_VAR int V36 tmp6 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [000859] DA---------- * STORE_LCL_VAR int V36 tmp6 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N012 ( 28, 18) [000853] DACXG------- * STORE_LCL_VAR int V51 tmp21 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 0, 0) [000856] DA---------- * STORE_LCL_VAR int V51 tmp21 d:2 *************** Finishing PHASE Rationalize IR Trees after Rationalize IR ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0056] 1 1 [???..???) i internal label target LIR BB02 [0000] 1 BB01 1 [000..00D)-> BB04 ( cond ) i label target idxlen LIR BB03 [0001] 1 BB02 0.50 [00D..017) (return) i hascall gcsafe LIR BB04 [0002] 1 BB02 0.50 [017..065)-> BB06 ( cond ) i label target hascall gcsafe LIR BB05 [0038] 1 BB04 0.50 [020..021)-> BB07 (always) i gcsafe LIR BB06 [0039] 1 BB04 0.50 [020..021) i label target gcsafe LIR BB07 [0040] 2 BB05,BB06 0.50 [000..000)-> BB09 ( cond ) i internal label target gcsafe idxlen LIR BB08 [0043] 1 BB07 0.50 [000..000)-> BB10 (always) i internal gcsafe LIR BB09 [0044] 1 BB07 0.50 [000..000) i internal label target gcsafe LIR BB10 [0045] 2 BB08,BB09 0.50 [???..???)-> BB14 ( cond ) i internal label target hascall gcsafe idxlen LIR BB11 [0003] 1 BB10 0.50 [065..070)-> BB13 ( cond ) i hascall gcsafe LIR BB12 [0004] 1 BB11 0.50 [070..07A) (return) i hascall gcsafe LIR BB13 [0005] 1 BB11 0.50 [07A..082) i label target hascall gcsafe LIR BB14 [0006] 2 BB10,BB13 0.50 [082..092)-> BB16 ( cond ) i label target hascall gcsafe LIR BB15 [0007] 1 BB14 0.50 [092..096)-> BB17 ( cond ) i gcsafe LIR BB16 [0008] 2 BB14,BB15 0.50 [096..0A7)-> BB44 (always) i label target hascall gcsafe LIR BB17 [0009] 1 BB15 0.50 [0A7..0B0)-> BB19 ( cond ) i label target gcsafe LIR BB18 [0010] 1 BB17 0.50 [0B0..0B4)-> BB20 (always) i gcsafe LIR BB19 [0011] 1 BB17 0.50 [0B4..0BE) i label target gcsafe LIR BB20 [0012] 2 BB18,BB19 0.50 [0BE..0C4)-> BB23 ( cond ) i label target gcsafe LIR BB21 [0013] 1 BB20 0.50 [0C4..0D9)-> BB23 ( cond ) i hascall gcsafe idxlen LIR BB22 [0014] 1 BB21 0.50 [0D9..0E3) (return) i hascall gcsafe LIR BB23 [0015] 2 BB20,BB21 0.50 [0E3..117)-> BB25 ( cond ) i label target hascall gcsafe LIR BB24 [0016] 1 BB23 0.50 [117..11A)-> BB26 (always) i gcsafe LIR BB25 [0017] 1 BB23 0.50 [11A..11F) i label target gcsafe LIR BB26 [0018] 2 BB24,BB25 0.50 [11F..126)-> BB28 ( cond ) i label target gcsafe LIR BB27 [0019] 1 BB26 0.50 [126..12F) i hascall gcsafe LIR BB28 [0020] 2 BB26,BB27 0.50 [12F..13E)-> BB32 ( cond ) i label target gcsafe LIR BB29 [0021] 1 BB28 0.50 [13E..144)-> BB31 ( cond ) i gcsafe LIR BB30 [0022] 1 BB29 0.50 [144..155)-> BB44 (always) i hascall gcsafe LIR BB31 [0023] 1 BB29 0.50 [155..15C) i label target gcsafe LIR BB32 [0024] 2 BB28,BB31 0.50 [15C..167)-> BB34 ( cond ) i label target hascall gcsafe LIR BB33 [0025] 1 BB32 0.50 [167..16B)-> BB35 (always) i gcsafe LIR BB34 [0026] 1 BB32 0.50 [16B..16F) i label target gcsafe LIR BB35 [0027] 2 BB33,BB34 0.50 [16F..1A4)-> BB40 ( cond ) i label target hascall gcsafe LIR BB36 [0028] 1 BB35 0.50 [1A4..1AF)-> BB38 ( cond ) i gcsafe LIR BB37 [0029] 1 BB36 0.50 [1AF..1C3)-> BB39 (always) i gcsafe LIR BB38 [0030] 1 BB36 0.50 [1C3..1C4) i label target gcsafe LIR BB39 [0031] 2 BB37,BB38 0.50 [1C4..1D0) i label target gcsafe LIR BB40 [0032] 2 BB35,BB39 0.50 [1D0..1E7)-> BB42 ( cond ) i label target hascall gcsafe LIR BB41 [0033] 1 BB40 0.50 [1E7..1EE)-> BB43 (always) i gcsafe LIR BB42 [0034] 1 BB40 0.50 [1EE..1F2) i label target gcsafe LIR BB43 [0035] 2 BB41,BB42 0.50 [1F2..202) i label target hascall gcsafe LIR BB44 [0054] 3 BB16,BB30,BB43 0.50 [???..???) (return) keep internal target gcsafe LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} N001 ( 1, 1) [000531] ------------ t531 = LCL_VAR byref V00 arg0 u:1 Zero Fseq[Mantissa] $80 /--* t531 byref N002 ( 3, 2) [000532] n----------- t532 = * IND ref /--* t532 ref N004 ( 3, 3) [000533] DA---------- * STORE_LCL_VAR ref V52 tmp22 d:2 N005 ( 1, 1) [000535] ------------ t535 = LCL_VAR byref V00 arg0 u:1 (last use) $80 N006 ( 1, 1) [000536] ------------ t536 = CNS_INT long 8 Fseq[Exponent] $101 /--* t535 byref +--* t536 long N007 ( 2, 2) [000537] -------N---- t537 = * ADD byref $200 /--* t537 byref N008 ( 4, 4) [000538] n----------- t538 = * IND int /--* t538 int N010 ( 4, 4) [000539] DA---------- * STORE_LCL_VAR int V53 tmp23 d:2 ------------ BB02 [000..00D) -> BB04 (cond), preds={BB01} succs={BB03,BB04} [000910] ------------ IL_OFFSET void IL offset: 0x0 N001 ( 1, 1) [000002] ------------ t2 = LCL_VAR ref V52 tmp22 u:2 /--* t2 ref N002 ( 3, 3) [000003] ---XG------- t3 = * ARR_LENGTH int N003 ( 1, 1) [000004] ------------ t4 = CNS_INT int 0 $40 /--* t3 int +--* t4 int N004 ( 5, 5) [000005] J--XG--N---- t5 = * NE int /--* t5 int N005 ( 7, 7) [000006] ---XG------- * JTRUE void ------------ BB03 [00D..017) (return), preds={BB02} succs={} [000911] ------------ IL_OFFSET void IL offset: 0xd N002 ( 1, 1) [000400] ------------ t400 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t400 ref this in rcx N003 ( 21, 10) [000401] --CXG------- t401 = * CALLV ind long FloatingPointType.get_Zero $459 N004 ( 1, 1) [000399] ------------ t399 = LCL_VAR byref V02 arg2 u:1 (last use) $81 /--* t399 byref +--* t401 long [000912] -ACXG------- * STOREIND long N001 ( 1, 1) [000404] ------------ t404 = CNS_INT int 1 $41 /--* t404 int N002 ( 2, 2) [000520] ------------ * RETURN int $5cb ------------ BB04 [017..065) -> BB06 (cond), preds={BB02} succs={BB05,BB06} N002 ( 1, 1) [000007] ------------ t7 = LCL_VAR ref V01 arg1 u:1 $c0 /--* t7 ref this in rcx N003 ( 21, 10) [000406] --CXG------- t406 = * CALLV ind int FloatingPointType.get_DenormalMantissaBits $282 N004 ( 1, 1) [000407] ------------ t407 = CNS_INT int 1 $41 /--* t406 int +--* t407 int N005 ( 23, 12) [000408] ---XG------- t408 = * ADD int $346 /--* t408 int N006 ( 24, 14) [000409] ---XG------- t409 = * CAST int <- ushort <- int $347 N007 ( 1, 1) [000010] ------------ t10 = CNS_INT int 1 $41 /--* t409 int +--* t10 int N008 ( 26, 16) [000011] ---XG------- t11 = * ADD int $348 /--* t11 int N010 ( 30, 19) [000013] DA-XG------- * STORE_LCL_VAR int V03 loc0 d:2 [000913] ------------ IL_OFFSET void IL offset: 0x20 N001 ( 1, 1) [000017] ------------ t17 = LCL_VAR int V53 tmp23 u:2 /--* t17 int N003 ( 5, 4) [000424] DA--G------- * STORE_LCL_VAR int V40 tmp10 d:2 [000914] ------------ IL_OFFSET void IL offset: 0x20 N001 ( 1, 1) [000412] ------------ t412 = LCL_VAR int V40 tmp10 u:2 N002 ( 1, 1) [000411] ------------ t411 = CNS_INT int 0 $40 /--* t412 int +--* t411 int N003 ( 3, 3) [000413] J------N---- t413 = * LE int /--* t413 int N004 ( 5, 5) [000414] ------------ * JTRUE void ------------ BB05 [020..021) -> BB07 (always), preds={BB04} succs={BB07} [000915] ------------ IL_OFFSET void IL offset: 0x20 N001 ( 3, 2) [000419] ------------ t419 = LCL_VAR int V53 tmp23 u:2 (last use) /--* t419 int N003 ( 7, 5) [000421] DA---------- * STORE_LCL_VAR int V39 tmp9 d:4 ------------ BB06 [020..021), preds={BB04} succs={BB07} [000916] ------------ IL_OFFSET void IL offset: 0x20 N001 ( 1, 1) [000415] ------------ t415 = CNS_INT int 0 $40 /--* t415 int N003 ( 5, 4) [000417] DA---------- * STORE_LCL_VAR int V39 tmp9 d:3 ------------ BB07 [000..000) -> BB09 (cond), preds={BB05,BB06} succs={BB08,BB09} N001 ( 0, 0) [000909] ------------ t909 = PHI_ARG int V39 tmp9 u:4 N002 ( 0, 0) [000908] ------------ t908 = PHI_ARG int V39 tmp9 u:3 $40 /--* t909 int +--* t908 int N003 ( 0, 0) [000885] ------------ t885 = * PHI int /--* t885 int N005 ( 0, 0) [000886] DA---------- * STORE_LCL_VAR int V39 tmp9 d:2 N001 ( 3, 2) [000422] ------------ t422 = LCL_VAR int V39 tmp9 u:2 $241 /--* t422 int N003 ( 3, 3) [000021] DA---------- * STORE_LCL_VAR int V31 tmp1 d:2 N001 ( 1, 1) [000428] ------------ t428 = LCL_VAR ref V52 tmp22 u:2 /--* t428 ref N002 ( 3, 3) [000429] ---XG------- t429 = * ARR_LENGTH int /--* t429 int N004 ( 3, 3) [000443] DA-XG------- * STORE_LCL_VAR int V42 tmp12 d:2 N001 ( 3, 2) [000023] ------------ t23 = LCL_VAR int V31 tmp1 u:2 (last use) $241 N002 ( 1, 1) [000431] ------------ t431 = LCL_VAR int V42 tmp12 u:2 /--* t23 int +--* t431 int N003 ( 5, 4) [000432] N------N-U-- t432 = * LE int /--* t432 int N004 ( 7, 6) [000433] ------------ * JTRUE void ------------ BB08 [000..000) -> BB10 (always), preds={BB07} succs={BB10} N001 ( 1, 1) [000438] ------------ t438 = LCL_VAR int V42 tmp12 u:2 (last use) /--* t438 int N003 ( 1, 3) [000440] DA---------- * STORE_LCL_VAR int V41 tmp11 d:4 ------------ BB09 [000..000), preds={BB07} succs={BB10} N001 ( 1, 1) [000434] ------------ t434 = LCL_VAR int V31 tmp1 u:2 $241 /--* t434 int N003 ( 1, 3) [000436] DA---------- * STORE_LCL_VAR int V41 tmp11 d:3 ------------ BB10 [???..???) -> BB14 (cond), preds={BB08,BB09} succs={BB11,BB14} N001 ( 0, 0) [000907] ------------ t907 = PHI_ARG int V41 tmp11 u:4 N002 ( 0, 0) [000906] ------------ t906 = PHI_ARG int V41 tmp11 u:3 $241 /--* t907 int +--* t906 int N003 ( 0, 0) [000882] ------------ t882 = * PHI int /--* t882 int N005 ( 0, 0) [000883] DA---------- * STORE_LCL_VAR int V41 tmp11 d:2 N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR int V31 tmp1 u:2 (last use) $241 N002 ( 1, 1) [000032] ------------ t32 = LCL_VAR int V41 tmp11 u:2 $242 /--* t22 int +--* t32 int N003 ( 3, 3) [000033] ------------ t33 = * SUB int $34e /--* t33 int N005 ( 7, 6) [000035] DA---------- * STORE_LCL_VAR int V05 loc2 d:2 [000917] ------------ IL_OFFSET void IL offset: 0x42 N001 ( 1, 1) [000042] ------------ t42 = LCL_VAR int V41 tmp11 u:2 $242 /--* t42 int N003 ( 5, 4) [000044] DA---------- * STORE_LCL_VAR int V08 loc5 d:2 N001 ( 1, 1) [000447] ------------ t447 = LCL_VAR ref V52 tmp22 u:2 /--* t447 ref N002 ( 3, 3) [000448] ---XG------- t448 = * ARR_LENGTH int /--* t448 int N004 ( 7, 6) [000050] DA-XG------- * STORE_LCL_VAR int V09 loc6 d:2 [000918] ------------ IL_OFFSET void IL offset: 0x4f N001 ( 3, 2) [000051] ------------ t51 = LCL_VAR int V09 loc6 u:2 N002 ( 1, 1) [000052] ------------ t52 = LCL_VAR int V08 loc5 u:2 $242 /--* t51 int +--* t52 int N003 ( 5, 4) [000053] ------------ t53 = * SUB int /--* t53 int N005 ( 5, 4) [000055] DA---------- * STORE_LCL_VAR int V10 loc7 d:2 N001 ( 3, 2) [000063] -------N---- t63 = LCL_VAR_ADDR byref V11 loc8 * ref V11._bits (offs=0x00) -> V54 tmp24 * int V11._sign (offs=0x08) -> V55 tmp25 /--* t63 byref N004 ( 7, 6) [000563] DA--------L- * STORE_LCL_VAR long V75 tmp45 d:2 N005 ( 3, 2) [000547] -------N---- t547 = LCL_VAR_ADDR byref V73 tmp43 /--* t547 byref N008 ( 3, 3) [000549] DA---------- * STORE_LCL_VAR byref V74 tmp44 d:2 N009 ( 1, 1) [000550] ------------ t550 = LCL_VAR byref V74 tmp44 u:2 Zero Fseq[Mantissa] $401 N011 ( 1, 1) [000552] -------N---- t552 = LCL_VAR ref V52 tmp22 u:2 /--* t550 byref +--* t552 ref [000919] -A---------- * STOREIND ref N014 ( 1, 1) [000555] ------------ t555 = LCL_VAR byref V74 tmp44 u:2 (last use) $401 N015 ( 1, 1) [000556] ------------ t556 = CNS_INT long 8 Fseq[Exponent] $101 /--* t555 byref +--* t556 long N016 ( 2, 2) [000557] -------N---- t557 = * ADD byref $203 N018 ( 1, 1) [000559] -------N---- t559 = LCL_VAR int V53 tmp23 u:2 /--* t557 byref +--* t559 int [000920] -A--------L- * STOREIND int N023 ( 3, 2) [000564] ------------ t564 = LCL_VAR long V75 tmp45 u:2 (last use) $400 N024 ( 3, 2) [000565] -------N---- t565 = LCL_VAR_ADDR byref V73 tmp43 N026 ( 1, 1) [000058] ------------ t58 = LCL_VAR int V08 loc5 u:2 (last use) $242 N027 ( 1, 1) [000057] ------------ t57 = CNS_INT int 0 $40 /--* t564 long arg0 in rcx +--* t565 byref arg1 in rdx +--* t58 int arg3 in r9 +--* t57 int arg2 in r8 N028 ( 49, 35) [000059] S-CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger $VN.Void [000921] ------------ IL_OFFSET void IL offset: 0x61 N001 ( 3, 2) [000065] ------------ t65 = LCL_VAR int V05 loc2 u:2 $34e N002 ( 1, 1) [000066] ------------ t66 = CNS_INT int 0 $40 /--* t65 int +--* t66 int N003 ( 5, 4) [000067] N------N---- t67 = * EQ int $351 /--* t67 int N004 ( 7, 6) [000068] ------------ * JTRUE void ------------ BB11 [065..070) -> BB13 (cond), preds={BB10} succs={BB12,BB13} N002 ( 1, 1) [000382] ------------ t382 = LCL_VAR ref V01 arg1 u:1 $c0 /--* t382 ref this in rcx N003 ( 15, 8) [000383] --CXG------- t383 = * CALL int FloatingPointType.get_OverflowDecimalExponent $291 /--* t383 int N004 ( 16, 10) [000385] ---XG------- t385 = * CAST long <- int $480 N005 ( 3, 2) [000380] ------------ t380 = LCL_VAR int V05 loc2 u:2 $34e /--* t380 int N006 ( 4, 4) [000381] ---------U-- t381 = * CAST long <- ulong <- uint $481 /--* t385 long +--* t381 long N007 ( 21, 15) [000386] J--XG--N---- t386 = * GE int $352 /--* t386 int N008 ( 23, 17) [000387] ---XG------- * JTRUE void ------------ BB12 [070..07A) (return), preds={BB11} succs={} [000922] ------------ IL_OFFSET void IL offset: 0x70 N002 ( 1, 1) [000393] ------------ t393 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t393 ref this in rcx N003 ( 21, 10) [000394] --CXG------- t394 = * CALLV ind long FloatingPointType.get_Infinity $458 N004 ( 1, 1) [000392] ------------ t392 = LCL_VAR byref V02 arg2 u:1 (last use) $81 /--* t392 byref +--* t394 long [000923] -ACXG------- * STOREIND long N001 ( 1, 1) [000397] ------------ t397 = CNS_INT int 3 $48 /--* t397 int N002 ( 2, 2) [000521] ------------ * RETURN int $5ca ------------ BB13 [07A..082), preds={BB11} succs={BB14} [000924] ------------ IL_OFFSET void IL offset: 0x7a N003 ( 3, 2) [000388] -------N---- t388 = LCL_VAR_ADDR byref V11 loc8 * ref V11._bits (offs=0x00) -> V54 tmp24 * int V11._sign (offs=0x08) -> V55 tmp25 N005 ( 3, 2) [000390] ------------ t390 = LCL_VAR int V05 loc2 u:2 (last use) $34e /--* t388 byref arg0 in rcx +--* t390 int arg1 in rdx N006 ( 20, 12) [000391] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen $VN.Void ------------ BB14 [082..092) -> BB16 (cond), preds={BB10,BB13} succs={BB15,BB16} N001 ( 3, 2) [000577] -------N---- t577 = LCL_VAR_ADDR byref V76 tmp46 /--* t577 byref N004 ( 3, 3) [000579] DA---------- * STORE_LCL_VAR byref V77 tmp47 d:2 N005 ( 1, 1) [000580] ------------ t580 = LCL_VAR byref V77 tmp47 u:2 Zero Fseq[_bits] $405 N007 ( 3, 2) [000582] -------N---- t582 = LCL_VAR ref (AX) V54 tmp24 $181 /--* t580 byref +--* t582 ref [000925] -A--G------- * STOREIND ref N010 ( 1, 1) [000585] ------------ t585 = LCL_VAR byref V77 tmp47 u:2 (last use) $405 N011 ( 1, 1) [000586] ------------ t586 = CNS_INT long 8 Fseq[_sign] $101 /--* t585 byref +--* t586 long N012 ( 2, 2) [000587] -------N---- t587 = * ADD byref $206 N014 ( 3, 2) [000589] -------N---- t589 = LCL_VAR int (AX) V55 tmp25 $243 /--* t587 byref +--* t589 int [000926] -A--G-----L- * STOREIND int N018 ( 3, 2) [000592] -------N---- t592 = LCL_VAR_ADDR byref V76 tmp46 N020 ( 3, 3) [000071] ------------ t71 = LCL_VAR_ADDR long V12 loc9 $443 /--* t592 byref arg0 in rcx +--* t71 long arg1 in rdx N021 ( 41, 28) [000072] --CXG------- t72 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $293 /--* t72 int N023 ( 41, 28) [000077] DA-XG------- * STORE_LCL_VAR int V13 loc10 d:2 [000927] ------------ IL_OFFSET void IL offset: 0x8d N001 ( 1, 1) [000078] ------------ t78 = LCL_VAR int V13 loc10 u:2 $293 N002 ( 3, 2) [000079] ------------ t79 = LCL_VAR int V03 loc0 u:2 $348 /--* t78 int +--* t79 int N003 ( 5, 4) [000080] N------N-U-- t80 = * GE int $353 /--* t80 int N004 ( 7, 6) [000081] ------------ * JTRUE void ------------ BB15 [092..096) -> BB17 (cond), preds={BB14} succs={BB16,BB17} [000928] ------------ IL_OFFSET void IL offset: 0x92 N001 ( 1, 1) [000091] ------------ t91 = LCL_VAR int V10 loc7 u:2 N002 ( 1, 1) [000092] ------------ t92 = CNS_INT int 0 $40 /--* t91 int +--* t92 int N003 ( 3, 3) [000093] J------N---- t93 = * NE int /--* t93 int N004 ( 5, 5) [000094] ------------ * JTRUE void ------------ BB16 [096..0A7) -> BB44 (always), preds={BB14,BB15} succs={BB44} [000929] ------------ IL_OFFSET void IL offset: 0x96 N005 ( 1, 1) [000088] ------------ t88 = LCL_VAR byref V02 arg2 u:1 (last use) $81 N006 ( 1, 1) [000084] ------------ t84 = LCL_VAR int V10 loc7 u:2 (last use) N007 ( 1, 1) [000085] ------------ t85 = CNS_INT int 0 $40 /--* t84 int +--* t85 int N008 ( 6, 3) [000086] N----------- t86 = * NE int N009 ( 3, 2) [000082] ------------ t82 = LCL_VAR ref (AX) V12 loc9 $18d N010 ( 1, 1) [000083] ------------ t83 = LCL_VAR int V13 loc10 u:2 (last use) $293 N011 ( 1, 1) [000087] ------------ t87 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t88 byref arg4 out+20 +--* t86 int arg2 in r8 +--* t82 ref arg0 in rcx +--* t83 int arg1 in rdx +--* t87 ref arg3 in r9 N012 ( 29, 17) [000089] --CXG------- t89 = * CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits $5c7 /--* t89 int N014 ( 29, 17) [000600] DA-XG------- * STORE_LCL_VAR int V51 tmp21 d:3 ------------ BB17 [0A7..0B0) -> BB19 (cond), preds={BB15} succs={BB18,BB19} [000930] ------------ IL_OFFSET void IL offset: 0xa7 N001 ( 1, 1) [000097] ------------ t97 = LCL_VAR int V53 tmp23 u:2 N002 ( 1, 1) [000098] ------------ t98 = CNS_INT int 0 $40 /--* t97 int +--* t98 int N003 ( 3, 3) [000099] J---G--N---- t99 = * LT int /--* t99 int N004 ( 5, 5) [000100] ----G------- * JTRUE void ------------ BB18 [0B0..0B4) -> BB20 (always), preds={BB17} succs={BB20} [000931] ------------ IL_OFFSET void IL offset: 0xb0 N001 ( 1, 1) [000376] ------------ t376 = LCL_VAR int V10 loc7 u:2 /--* t376 int N003 ( 5, 4) [000378] DA---------- * STORE_LCL_VAR int V32 tmp2 d:4 ------------ BB19 [0B4..0BE), preds={BB17} succs={BB20} [000932] ------------ IL_OFFSET void IL offset: 0xb4 N001 ( 1, 1) [000101] ------------ t101 = LCL_VAR int V10 loc7 u:2 N002 ( 1, 1) [000104] ------------ t104 = LCL_VAR int V53 tmp23 u:2 /--* t101 int +--* t104 int N003 ( 3, 3) [000106] ----G------- t106 = * SUB int /--* t106 int N005 ( 7, 6) [000108] DA--G------- * STORE_LCL_VAR int V32 tmp2 d:3 ------------ BB20 [0BE..0C4) -> BB23 (cond), preds={BB18,BB19} succs={BB21,BB23} N001 ( 0, 0) [000905] ------------ t905 = PHI_ARG int V32 tmp2 u:4 N002 ( 0, 0) [000904] ------------ t904 = PHI_ARG int V32 tmp2 u:3 /--* t905 int +--* t904 int N003 ( 0, 0) [000879] ------------ t879 = * PHI int /--* t879 int N005 ( 0, 0) [000880] DA---------- * STORE_LCL_VAR int V32 tmp2 d:2 N001 ( 3, 2) [000110] ------------ t110 = LCL_VAR int V32 tmp2 u:2 (last use) $244 /--* t110 int N003 ( 7, 5) [000112] DA---------- * STORE_LCL_VAR int V14 loc11 d:2 [000933] ------------ IL_OFFSET void IL offset: 0xc0 N001 ( 1, 1) [000113] ------------ t113 = LCL_VAR int V13 loc10 u:2 $293 N002 ( 1, 1) [000114] ------------ t114 = CNS_INT int 0 $40 /--* t113 int +--* t114 int N003 ( 3, 3) [000115] J------N---- t115 = * NE int $35a /--* t115 int N004 ( 5, 5) [000116] ------------ * JTRUE void ------------ BB21 [0C4..0D9) -> BB23 (cond), preds={BB20} succs={BB22,BB23} N001 ( 1, 1) [000455] ------------ t455 = LCL_VAR ref V52 tmp22 u:2 /--* t455 ref N002 ( 3, 3) [000456] ---XG------- t456 = * ARR_LENGTH int /--* t456 int N003 ( 4, 5) [000358] ---XG------- t358 = * CAST long <- int N004 ( 3, 2) [000352] ------------ t352 = LCL_VAR int V14 loc11 u:2 $244 /--* t352 int N005 ( 4, 4) [000353] ---------U-- t353 = * CAST long <- ulong <- uint $486 /--* t353 long +--* t358 long N006 ( 9, 10) [000359] ---XG------- t359 = * SUB long /--* t359 long N008 ( 13, 13) [000363] DA-XG------- * STORE_LCL_VAR long V38 tmp8 d:2 N002 ( 1, 1) [000360] ------------ t360 = LCL_VAR ref V01 arg1 u:1 $c0 /--* t360 ref this in rcx N003 ( 15, 8) [000361] --CXG------- t361 = * CALL int FloatingPointType.get_OverflowDecimalExponent $298 /--* t361 int N004 ( 16, 10) [000366] ---XG------- t366 = * CAST long <- int $48b N005 ( 3, 2) [000364] ------------ t364 = LCL_VAR long V38 tmp8 u:2 (last use) /--* t366 long +--* t364 long N006 ( 20, 13) [000367] J--XG--N---- t367 = * GE int /--* t367 int N007 ( 22, 15) [000368] ---XG------- * JTRUE void ------------ BB22 [0D9..0E3) (return), preds={BB21} succs={} [000934] ------------ IL_OFFSET void IL offset: 0xd9 N002 ( 1, 1) [000370] ------------ t370 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t370 ref this in rcx N003 ( 21, 10) [000371] --CXG------- t371 = * CALLV ind long FloatingPointType.get_Zero $457 N004 ( 1, 1) [000369] ------------ t369 = LCL_VAR byref V02 arg2 u:1 (last use) $81 /--* t369 byref +--* t371 long [000935] -ACXG------- * STOREIND long N001 ( 1, 1) [000374] ------------ t374 = CNS_INT int 2 $42 /--* t374 int N002 ( 2, 2) [000524] ------------ * RETURN int $5c4 ------------ BB23 [0E3..117) -> BB25 (cond), preds={BB20,BB21} succs={BB24,BB25} N001 ( 3, 2) [000124] -------N---- t124 = LCL_VAR_ADDR byref V15 loc12 * ref V15._bits (offs=0x00) -> V56 tmp26 * int V15._sign (offs=0x08) -> V57 tmp27 /--* t124 byref N004 ( 7, 6) [000623] DA--------L- * STORE_LCL_VAR long V79 tmp49 d:2 N005 ( 3, 2) [000607] -------N---- t607 = LCL_VAR_ADDR byref V73 tmp43 /--* t607 byref N008 ( 3, 3) [000609] DA---------- * STORE_LCL_VAR byref V78 tmp48 d:2 N009 ( 1, 1) [000610] ------------ t610 = LCL_VAR byref V78 tmp48 u:2 Zero Fseq[Mantissa] $409 N011 ( 1, 1) [000612] -------N---- t612 = LCL_VAR ref V52 tmp22 u:2 (last use) /--* t610 byref +--* t612 ref [000936] -A---------- * STOREIND ref N014 ( 1, 1) [000615] ------------ t615 = LCL_VAR byref V78 tmp48 u:2 (last use) $409 N015 ( 1, 1) [000616] ------------ t616 = CNS_INT long 8 Fseq[Exponent] $101 /--* t615 byref +--* t616 long N016 ( 2, 2) [000617] -------N---- t617 = * ADD byref $209 N018 ( 1, 1) [000619] -------N---- t619 = LCL_VAR int V53 tmp23 u:2 (last use) /--* t617 byref +--* t619 int [000937] -A--------L- * STOREIND int N023 ( 3, 2) [000624] ------------ t624 = LCL_VAR long V79 tmp49 u:2 (last use) $408 N024 ( 3, 2) [000625] -------N---- t625 = LCL_VAR_ADDR byref V73 tmp43 N026 ( 3, 2) [000118] ------------ t118 = LCL_VAR int V08 loc5 u:2 (last use) $242 N027 ( 3, 2) [000119] ------------ t119 = LCL_VAR int V09 loc6 u:2 (last use) /--* t624 long arg0 in rcx +--* t625 byref arg1 in rdx +--* t118 int arg2 in r8 +--* t119 int arg3 in r9 N028 ( 53, 37) [000120] S-CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger $VN.Void [000938] ------------ IL_OFFSET void IL offset: 0xef N003 ( 2, 10) [000131] ------------ t131 = CNS_INT long 0x7ff815262aa0 $102 N004 ( 1, 4) [000132] ------------ t132 = CNS_INT int 173 $58 /--* t131 long arg0 in rcx +--* t132 int arg1 in rdx N005 ( 17, 21) [000133] H-CXG------- t133 = * CALL help long HELPER.CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE $48d N001 ( 2, 10) [000634] I----------- t634 = CNS_INT(h) long 0xd1ffab1e static Fseq[BigOne] $4c2 /--* t634 long N002 ( 4, 12) [000633] n---G------- t633 = * IND ref N003 ( 1, 1) [000635] ------------ t635 = CNS_INT long 8 Fseq[#FirstElem] $101 /--* t633 ref +--* t635 long N004 ( 6, 14) [000632] ----G------- t632 = * ADD byref /--* t632 byref N006 ( 6, 14) [000637] DA--G------- * STORE_LCL_VAR byref V80 tmp50 d:2 N007 ( 1, 1) [000639] ------------ t639 = LCL_VAR byref V80 tmp50 u:2 Zero Fseq[_bits] /--* t639 byref N008 ( 3, 2) [000640] ---X-------- t640 = * IND ref /--* t640 ref N010 ( 7, 5) [000641] DA-XG------- * STORE_LCL_VAR ref (AX) V58 tmp28 N012 ( 1, 1) [000644] ------------ t644 = LCL_VAR byref V80 tmp50 u:2 (last use) N013 ( 1, 1) [000645] ------------ t645 = CNS_INT long 8 Fseq[_sign] $101 /--* t644 byref +--* t645 long N014 ( 2, 2) [000646] -------N---- t646 = * ADD byref /--* t646 byref N015 ( 4, 4) [000647] ---X-------- t647 = * IND int /--* t647 int N017 ( 8, 7) [000648] DA-XG------- * STORE_LCL_VAR int (AX) V59 tmp29 [000939] ------------ IL_OFFSET void IL offset: 0xf6 N003 ( 3, 2) [000138] -------N---- t138 = LCL_VAR_ADDR byref V16 loc13 * ref V16._bits (offs=0x00) -> V58 tmp28 * int V16._sign (offs=0x08) -> V59 tmp29 N005 ( 3, 2) [000140] ------------ t140 = LCL_VAR int V14 loc11 u:2 (last use) $244 /--* t138 byref arg0 in rcx +--* t140 int arg1 in rdx N006 ( 20, 12) [000141] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen $VN.Void [000940] ------------ IL_OFFSET void IL offset: 0xff N001 ( 3, 2) [000653] -------N---- t653 = LCL_VAR ref (AX) V56 tmp26 $184 /--* t653 ref N003 ( 7, 5) [000654] DA--G------- * STORE_LCL_VAR ref V64 tmp34 d:2 N004 ( 3, 2) [000656] -------N---- t656 = LCL_VAR int (AX) V57 tmp27 $246 /--* t656 int N006 ( 7, 5) [000657] DA--G------- * STORE_LCL_VAR int V65 tmp35 d:2 [000941] ------------ IL_OFFSET void IL offset: 0xff N001 ( 3, 2) [000663] -------N---- t663 = LCL_VAR_ADDR byref V76 tmp46 /--* t663 byref N004 ( 3, 3) [000665] DA---------- * STORE_LCL_VAR byref V81 tmp51 d:2 N005 ( 1, 1) [000666] ------------ t666 = LCL_VAR byref V81 tmp51 u:2 Zero Fseq[_bits] $40e N007 ( 3, 2) [000668] -------N---- t668 = LCL_VAR ref V64 tmp34 u:2 (last use) $184 /--* t666 byref +--* t668 ref [000942] -A---------- * STOREIND ref N010 ( 1, 1) [000671] ------------ t671 = LCL_VAR byref V81 tmp51 u:2 (last use) $40e N011 ( 1, 1) [000672] ------------ t672 = CNS_INT long 8 Fseq[_sign] $101 /--* t671 byref +--* t672 long N012 ( 2, 2) [000673] -------N---- t673 = * ADD byref $211 N014 ( 3, 2) [000675] -------N---- t675 = LCL_VAR int V65 tmp35 u:2 (last use) $246 /--* t673 byref +--* t675 int [000943] -A--------L- * STOREIND int N018 ( 3, 2) [000678] -------N---- t678 = LCL_VAR_ADDR byref V76 tmp46 N020 ( 3, 3) [000462] ------------ t462 = LCL_VAR_ADDR long V45 tmp15 $449 /--* t678 byref arg0 in rcx +--* t462 long arg1 in rdx N021 ( 41, 28) [000463] --CXG------- t463 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $29f /--* t463 int N023 ( 45, 31) [000468] DA-XG------- * STORE_LCL_VAR int V43 tmp13 d:2 [000944] ------------ IL_OFFSET void IL offset: 0xff N001 ( 1, 1) [000473] ------------ t473 = CNS_INT ref null $VN.Null /--* t473 ref N003 ( 5, 4) [000475] DA--G------- * STORE_LCL_VAR ref (AX) V45 tmp15 N001 ( 3, 2) [000469] ------------ t469 = LCL_VAR int V43 tmp13 u:2 $29f /--* t469 int N003 ( 7, 5) [000148] DA---------- * STORE_LCL_VAR int V17 loc14 d:2 [000945] ------------ IL_OFFSET void IL offset: 0x108 N001 ( 3, 2) [000682] -------N---- t682 = LCL_VAR ref (AX) V58 tmp28 $185 /--* t682 ref N003 ( 7, 5) [000683] DA--G------- * STORE_LCL_VAR ref V66 tmp36 d:2 N004 ( 3, 2) [000685] -------N---- t685 = LCL_VAR int (AX) V59 tmp29 $247 /--* t685 int N006 ( 7, 5) [000686] DA--G------- * STORE_LCL_VAR int V67 tmp37 d:2 [000946] ------------ IL_OFFSET void IL offset: 0x108 N001 ( 3, 2) [000692] -------N---- t692 = LCL_VAR_ADDR byref V76 tmp46 /--* t692 byref N004 ( 3, 3) [000694] DA---------- * STORE_LCL_VAR byref V82 tmp52 d:2 N005 ( 1, 1) [000695] ------------ t695 = LCL_VAR byref V82 tmp52 u:2 Zero Fseq[_bits] $411 N007 ( 3, 2) [000697] -------N---- t697 = LCL_VAR ref V66 tmp36 u:2 (last use) $185 /--* t695 byref +--* t697 ref [000947] -A---------- * STOREIND ref N010 ( 1, 1) [000700] ------------ t700 = LCL_VAR byref V82 tmp52 u:2 (last use) $411 N011 ( 1, 1) [000701] ------------ t701 = CNS_INT long 8 Fseq[_sign] $101 /--* t700 byref +--* t701 long N012 ( 2, 2) [000702] -------N---- t702 = * ADD byref $214 N014 ( 3, 2) [000704] -------N---- t704 = LCL_VAR int V67 tmp37 u:2 (last use) $247 /--* t702 byref +--* t704 int [000948] -A--------L- * STOREIND int N018 ( 3, 2) [000707] -------N---- t707 = LCL_VAR_ADDR byref V76 tmp46 N020 ( 3, 3) [000480] ------------ t480 = LCL_VAR_ADDR long V48 tmp18 $44b /--* t707 byref arg0 in rcx +--* t480 long arg1 in rdx N021 ( 41, 28) [000481] --CXG------- t481 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $2a3 /--* t481 int N023 ( 45, 31) [000486] DA-XG------- * STORE_LCL_VAR int V46 tmp16 d:2 [000949] ------------ IL_OFFSET void IL offset: 0x108 N001 ( 1, 1) [000491] ------------ t491 = CNS_INT ref null $VN.Null /--* t491 ref N003 ( 5, 4) [000493] DA--G------- * STORE_LCL_VAR ref (AX) V48 tmp18 N001 ( 3, 2) [000487] ------------ t487 = LCL_VAR int V46 tmp16 u:2 $2a3 /--* t487 int N003 ( 7, 5) [000155] DA---------- * STORE_LCL_VAR int V18 loc15 d:2 [000950] ------------ IL_OFFSET void IL offset: 0x111 N001 ( 3, 2) [000156] ------------ t156 = LCL_VAR int V18 loc15 u:2 (last use) $2a3 N002 ( 3, 2) [000157] ------------ t157 = LCL_VAR int V17 loc14 u:2 (last use) $29f /--* t156 int +--* t157 int N003 ( 7, 5) [000158] N------N-U-- t158 = * GT int $35f /--* t158 int N004 ( 9, 7) [000159] ------------ * JTRUE void ------------ BB24 [117..11A) -> BB26 (always), preds={BB23} succs={BB26} [000951] ------------ IL_OFFSET void IL offset: 0x117 N001 ( 1, 1) [000348] ------------ t348 = CNS_INT int 0 $40 /--* t348 int N003 ( 5, 4) [000350] DA---------- * STORE_LCL_VAR int V33 tmp3 d:4 ------------ BB25 [11A..11F), preds={BB23} succs={BB26} [000952] ------------ IL_OFFSET void IL offset: 0x11a N001 ( 3, 2) [000160] ------------ t160 = LCL_VAR int V18 loc15 u:2 (last use) $2a3 N002 ( 3, 2) [000161] ------------ t161 = LCL_VAR int V17 loc14 u:2 (last use) $29f /--* t160 int +--* t161 int N003 ( 7, 5) [000162] ------------ t162 = * SUB int $360 /--* t162 int N005 ( 11, 8) [000164] DA---------- * STORE_LCL_VAR int V33 tmp3 d:3 ------------ BB26 [11F..126) -> BB28 (cond), preds={BB24,BB25} succs={BB27,BB28} N001 ( 0, 0) [000903] ------------ t903 = PHI_ARG int V33 tmp3 u:4 $40 N002 ( 0, 0) [000902] ------------ t902 = PHI_ARG int V33 tmp3 u:3 $360 /--* t903 int +--* t902 int N003 ( 0, 0) [000876] ------------ t876 = * PHI int /--* t876 int N005 ( 0, 0) [000877] DA---------- * STORE_LCL_VAR int V33 tmp3 d:2 N001 ( 3, 2) [000166] ------------ t166 = LCL_VAR int V33 tmp3 u:2 $248 /--* t166 int N003 ( 3, 3) [000168] DA---------- * STORE_LCL_VAR int V19 loc16 d:2 [000953] ------------ IL_OFFSET void IL offset: 0x121 N001 ( 3, 2) [000169] ------------ t169 = LCL_VAR int V19 loc16 u:2 (last use) $248 N002 ( 1, 1) [000170] ------------ t170 = CNS_INT int 0 $40 /--* t169 int +--* t170 int N003 ( 5, 4) [000171] N------N---- t171 = * EQ int $361 /--* t171 int N004 ( 7, 6) [000172] ------------ * JTRUE void ------------ BB27 [126..12F), preds={BB26} succs={BB28} [000954] ------------ IL_OFFSET void IL offset: 0x126 N003 ( 3, 2) [000344] -------N---- t344 = LCL_VAR_ADDR byref V15 loc12 * ref V15._bits (offs=0x00) -> V56 tmp26 * int V15._sign (offs=0x08) -> V57 tmp27 N005 ( 1, 1) [000346] ------------ t346 = LCL_VAR int V19 loc16 u:2 $248 /--* t344 byref arg0 in rcx +--* t346 int arg1 in rdx N006 ( 18, 11) [000347] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft $VN.Void ------------ BB28 [12F..13E) -> BB32 (cond), preds={BB26,BB27} succs={BB29,BB32} [000955] ------------ IL_OFFSET void IL offset: 0x12f N001 ( 3, 2) [000173] ------------ t173 = LCL_VAR int V03 loc0 u:2 (last use) $348 N002 ( 1, 1) [000174] ------------ t174 = LCL_VAR int V13 loc10 u:2 $293 /--* t173 int +--* t174 int N003 ( 5, 4) [000175] ------------ t175 = * SUB int $362 /--* t175 int N005 ( 9, 7) [000177] DA---------- * STORE_LCL_VAR int V20 loc17 d:2 [000956] ------------ IL_OFFSET void IL offset: 0x135 N001 ( 3, 2) [000178] ------------ t178 = LCL_VAR int V20 loc17 u:2 $362 /--* t178 int N003 ( 7, 5) [000180] DA---------- * STORE_LCL_VAR int V21 loc18 d:2 [000957] ------------ IL_OFFSET void IL offset: 0x139 N001 ( 1, 1) [000181] ------------ t181 = LCL_VAR int V13 loc10 u:2 $293 N002 ( 1, 1) [000182] ------------ t182 = CNS_INT int 0 $40 /--* t181 int +--* t182 int N003 ( 3, 3) [000183] N------N---- t183 = * EQ int $363 /--* t183 int N004 ( 5, 5) [000184] ------------ * JTRUE void ------------ BB29 [13E..144) -> BB31 (cond), preds={BB28} succs={BB30,BB31} [000958] ------------ IL_OFFSET void IL offset: 0x13e N001 ( 1, 1) [000326] ------------ t326 = LCL_VAR int V19 loc16 u:2 $248 N002 ( 3, 2) [000327] ------------ t327 = LCL_VAR int V20 loc17 u:2 $362 /--* t326 int +--* t327 int N003 ( 5, 4) [000328] N------N-U-- t328 = * LE int $364 /--* t328 int N004 ( 7, 6) [000329] ------------ * JTRUE void ------------ BB30 [144..155) -> BB44 (always), preds={BB29} succs={BB44} [000959] ------------ IL_OFFSET void IL offset: 0x144 N005 ( 1, 1) [000341] ------------ t341 = LCL_VAR byref V02 arg2 u:1 (last use) $81 N006 ( 1, 1) [000339] ------------ t339 = CNS_INT int 1 $41 N007 ( 3, 2) [000335] ------------ t335 = LCL_VAR ref (AX) V12 loc9 $18c N008 ( 1, 1) [000336] ------------ t336 = LCL_VAR int V13 loc10 u:2 (last use) $293 N009 ( 1, 1) [000340] ------------ t340 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t341 byref arg4 out+20 +--* t339 int arg2 in r8 +--* t335 ref arg0 in rcx +--* t336 int arg1 in rdx +--* t340 ref arg3 in r9 N010 ( 24, 15) [000342] --CXG------- t342 = * CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits $5c2 /--* t342 int N012 ( 24, 15) [000717] DA-XG------- * STORE_LCL_VAR int V51 tmp21 d:5 ------------ BB31 [155..15C), preds={BB29} succs={BB32} [000960] ------------ IL_OFFSET void IL offset: 0x155 N001 ( 3, 2) [000330] ------------ t330 = LCL_VAR int V20 loc17 u:2 (last use) $362 N002 ( 1, 1) [000331] ------------ t331 = LCL_VAR int V19 loc16 u:2 $248 /--* t330 int +--* t331 int N003 ( 5, 4) [000332] ------------ t332 = * SUB int $365 /--* t332 int N005 ( 9, 7) [000334] DA---------- * STORE_LCL_VAR int V21 loc18 d:4 ------------ BB32 [15C..167) -> BB34 (cond), preds={BB28,BB31} succs={BB33,BB34} N001 ( 0, 0) [000900] ------------ t900 = PHI_ARG int V21 loc18 u:4 $365 N002 ( 0, 0) [000888] ------------ t888 = PHI_ARG int V21 loc18 u:2 $362 /--* t900 int +--* t888 int N003 ( 0, 0) [000873] ------------ t873 = * PHI int /--* t873 int N005 ( 0, 0) [000874] DA---------- * STORE_LCL_VAR int V21 loc18 d:3 [000961] ------------ IL_OFFSET void IL offset: 0x15c N001 ( 3, 2) [000719] -------N---- t719 = LCL_VAR ref (AX) V56 tmp26 $186 /--* t719 ref N003 ( 7, 5) [000720] DA--G------- * STORE_LCL_VAR ref (AX) V68 tmp38 N004 ( 3, 2) [000722] -------N---- t722 = LCL_VAR int (AX) V57 tmp27 $24a /--* t722 int N006 ( 7, 5) [000723] DA--G------- * STORE_LCL_VAR int (AX) V69 tmp39 [000962] ------------ IL_OFFSET void IL offset: 0x15c N001 ( 3, 2) [000726] -------N---- t726 = LCL_VAR ref (AX) V58 tmp28 $187 /--* t726 ref N003 ( 7, 5) [000727] DA--G------- * STORE_LCL_VAR ref V70 tmp40 d:2 N004 ( 3, 2) [000729] -------N---- t729 = LCL_VAR int (AX) V59 tmp29 $24b /--* t729 int N006 ( 7, 5) [000730] DA--G------- * STORE_LCL_VAR int V71 tmp41 d:2 N001 ( 3, 2) [000496] -------N---- t496 = LCL_VAR_ADDR byref V49 tmp19 * ref V49._bits (offs=0x00) -> V68 tmp38 * int V49._sign (offs=0x08) -> V69 tmp39 /--* t496 byref N004 ( 7, 6) [000752] DA--------L- * STORE_LCL_VAR byref V84 tmp54 d:2 N005 ( 3, 2) [000736] -------N---- t736 = LCL_VAR_ADDR byref V76 tmp46 /--* t736 byref N008 ( 3, 3) [000738] DA---------- * STORE_LCL_VAR byref V83 tmp53 d:2 N009 ( 1, 1) [000739] ------------ t739 = LCL_VAR byref V83 tmp53 u:2 Zero Fseq[_bits] $417 N011 ( 3, 2) [000741] -------N---- t741 = LCL_VAR ref V70 tmp40 u:2 (last use) $187 /--* t739 byref +--* t741 ref [000963] -A---------- * STOREIND ref N014 ( 1, 1) [000744] ------------ t744 = LCL_VAR byref V83 tmp53 u:2 (last use) $417 N015 ( 1, 1) [000745] ------------ t745 = CNS_INT long 8 Fseq[_sign] $101 /--* t744 byref +--* t745 long N016 ( 2, 2) [000746] -------N---- t746 = * ADD byref $216 N018 ( 3, 2) [000748] -------N---- t748 = LCL_VAR int V71 tmp41 u:2 (last use) $24b /--* t746 byref +--* t748 int [000964] -A--------L- * STOREIND int N021 ( 3, 2) [000753] ------------ t753 = LCL_VAR byref V84 tmp54 u:2 (last use) $415 N022 ( 3, 2) [000754] -------N---- t754 = LCL_VAR_ADDR byref V76 tmp46 /--* t753 byref this in rcx +--* t754 byref arg1 in rdx N024 ( 48, 34) [000499] --CXG------- t499 = * CALL int System.Numerics.BigInteger.CompareTo $2ae N025 ( 1, 1) [000502] ------------ t502 = CNS_INT int 0 $40 /--* t499 int +--* t502 int N026 ( 50, 36) [000503] J--XG--N---- t503 = * LT int $367 /--* t503 int N027 ( 52, 38) [000195] ---XG------- * JTRUE void ------------ BB33 [167..16B) -> BB35 (always), preds={BB32} succs={BB35} [000965] ------------ IL_OFFSET void IL offset: 0x167 N001 ( 1, 1) [000322] ------------ t322 = LCL_VAR int V19 loc16 u:2 (last use) $248 /--* t322 int N003 ( 5, 4) [000324] DA---------- * STORE_LCL_VAR int V34 tmp4 d:4 ------------ BB34 [16B..16F), preds={BB32} succs={BB35} [000966] ------------ IL_OFFSET void IL offset: 0x16b N001 ( 1, 1) [000196] ------------ t196 = LCL_VAR int V19 loc16 u:2 (last use) $248 N002 ( 1, 1) [000197] ------------ t197 = CNS_INT int 1 $41 /--* t196 int +--* t197 int N003 ( 3, 3) [000198] ------------ t198 = * ADD int $368 /--* t198 int N005 ( 7, 6) [000200] DA---------- * STORE_LCL_VAR int V34 tmp4 d:3 ------------ BB35 [16F..1A4) -> BB40 (cond), preds={BB33,BB34} succs={BB36,BB40} N001 ( 0, 0) [000899] ------------ t899 = PHI_ARG int V34 tmp4 u:4 $248 N002 ( 0, 0) [000898] ------------ t898 = PHI_ARG int V34 tmp4 u:3 $368 /--* t899 int +--* t898 int N003 ( 0, 0) [000870] ------------ t870 = * PHI int /--* t870 int N005 ( 0, 0) [000871] DA---------- * STORE_LCL_VAR int V34 tmp4 d:2 N001 ( 3, 2) [000202] ------------ t202 = LCL_VAR int V34 tmp4 u:2 (last use) $24c /--* t202 int N003 ( 7, 5) [000204] DA---------- * STORE_LCL_VAR int V22 loc19 d:2 [000967] ------------ IL_OFFSET void IL offset: 0x171 N003 ( 3, 2) [000205] -------N---- t205 = LCL_VAR_ADDR byref V15 loc12 * ref V15._bits (offs=0x00) -> V56 tmp26 * int V15._sign (offs=0x08) -> V57 tmp27 N005 ( 3, 2) [000207] ------------ t207 = LCL_VAR int V21 loc18 u:3 (last use) $249 /--* t205 byref arg0 in rcx +--* t207 int arg1 in rdx N006 ( 20, 12) [000208] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft $VN.Void [000968] ------------ IL_OFFSET void IL offset: 0x17a N001 ( 3, 2) [000219] -------N---- t219 = LCL_VAR_ADDR byref V35 tmp5 * ref V35._bits (offs=0x00) -> V62 tmp32 * int V35._sign (offs=0x08) -> V63 tmp33 /--* t219 byref N004 ( 7, 6) [000797] DA--------L- * STORE_LCL_VAR long V88 tmp58 d:2 N005 ( 3, 2) [000762] -------N---- t762 = LCL_VAR_ADDR byref V76 tmp46 /--* t762 byref N008 ( 3, 3) [000764] DA---------- * STORE_LCL_VAR byref V85 tmp55 d:2 N009 ( 1, 1) [000765] ------------ t765 = LCL_VAR byref V85 tmp55 u:2 Zero Fseq[_bits] $41c N011 ( 3, 2) [000767] -------N---- t767 = LCL_VAR ref (AX) V56 tmp26 $188 /--* t765 byref +--* t767 ref [000969] -A--G------- * STOREIND ref N014 ( 1, 1) [000770] ------------ t770 = LCL_VAR byref V85 tmp55 u:2 (last use) $41c N015 ( 1, 1) [000771] ------------ t771 = CNS_INT long 8 Fseq[_sign] $101 /--* t770 byref +--* t771 long N016 ( 2, 2) [000772] -------N---- t772 = * ADD byref $218 N018 ( 3, 2) [000774] -------N---- t774 = LCL_VAR int (AX) V57 tmp27 $24d /--* t772 byref +--* t774 int [000970] -A--G-----L- * STOREIND int N021 ( 3, 2) [000781] -------N---- t781 = LCL_VAR_ADDR byref V86 tmp56 /--* t781 byref N024 ( 3, 3) [000783] DA---------- * STORE_LCL_VAR byref V87 tmp57 d:2 N025 ( 1, 1) [000784] ------------ t784 = LCL_VAR byref V87 tmp57 u:2 Zero Fseq[_bits] $41e N027 ( 3, 2) [000786] -------N---- t786 = LCL_VAR ref (AX) V58 tmp28 $189 /--* t784 byref +--* t786 ref [000971] -A--G------- * STOREIND ref N030 ( 1, 1) [000789] ------------ t789 = LCL_VAR byref V87 tmp57 u:2 (last use) $41e N031 ( 1, 1) [000790] ------------ t790 = CNS_INT long 8 Fseq[_sign] $101 /--* t789 byref +--* t790 long N032 ( 2, 2) [000791] -------N---- t791 = * ADD byref $21a N034 ( 3, 2) [000793] -------N---- t793 = LCL_VAR int (AX) V59 tmp29 $24e /--* t791 byref +--* t793 int [000972] -A--G-----L- * STOREIND int N038 ( 3, 2) [000798] ------------ t798 = LCL_VAR long V88 tmp58 u:2 (last use) $41b N039 ( 3, 2) [000799] -------N---- t799 = LCL_VAR_ADDR byref V76 tmp46 N041 ( 3, 2) [000801] -------N---- t801 = LCL_VAR_ADDR byref V86 tmp56 N043 ( 3, 2) [000211] -------N---- t211 = LCL_VAR_ADDR byref V23 loc20 * ref V23._bits (offs=0x00) -> V60 tmp30 * int V23._sign (offs=0x08) -> V61 tmp31 /--* t798 long arg0 in rcx +--* t799 byref arg1 in rdx +--* t801 byref arg2 in r8 +--* t211 byref arg3 in r9 N045 ( 78, 56) [000213] S-CXG------- * CALL void System.Numerics.BigInteger.DivRem $VN.Void N001 ( 3, 2) [000808] -------N---- t808 = LCL_VAR_ADDR byref V76 tmp46 /--* t808 byref N004 ( 3, 3) [000810] DA---------- * STORE_LCL_VAR byref V89 tmp59 d:2 N005 ( 1, 1) [000811] ------------ t811 = LCL_VAR byref V89 tmp59 u:2 Zero Fseq[_bits] $423 N007 ( 3, 2) [000813] -------N---- t813 = LCL_VAR ref (AX) V62 tmp32 $18a /--* t811 byref +--* t813 ref [000973] -A--G------- * STOREIND ref N010 ( 1, 1) [000816] ------------ t816 = LCL_VAR byref V89 tmp59 u:2 (last use) $423 N011 ( 1, 1) [000817] ------------ t817 = CNS_INT long 8 Fseq[_sign] $101 /--* t816 byref +--* t817 long N012 ( 2, 2) [000818] -------N---- t818 = * ADD byref $21d N014 ( 3, 2) [000820] -------N---- t820 = LCL_VAR int (AX) V63 tmp33 $24f /--* t818 byref +--* t820 int [000974] -A--G-----L- * STOREIND int N017 ( 3, 2) [000823] -------N---- t823 = LCL_VAR_ADDR byref V76 tmp46 /--* t823 byref arg0 in rcx N019 ( 38, 24) [000218] --CXG------- t218 = * CALL long System.Numerics.BigInteger.op_Explicit $450 /--* t218 long N021 ( 38, 24) [000226] DA-XG------- * STORE_LCL_VAR long V24 loc21 d:2 N001 ( 3, 2) [000514] ------------ t514 = LCL_VAR int (AX) V61 tmp31 $250 N002 ( 1, 1) [000515] ------------ t515 = CNS_INT int 0 $40 /--* t514 int +--* t515 int N003 ( 8, 4) [000516] ----G------- t516 = * EQ int $369 /--* t516 int N005 ( 12, 7) [000232] DA--G------- * STORE_LCL_VAR int V25 loc22 d:2 N002 ( 1, 1) [000233] ------------ t233 = LCL_VAR long V24 loc21 u:2 $450 /--* t233 long arg0 in rcx N003 ( 15, 7) [000234] --CXG------- t234 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $2b4 /--* t234 int N005 ( 19, 10) [000237] DA-XG------- * STORE_LCL_VAR int V26 loc23 d:2 [000975] ------------ IL_OFFSET void IL offset: 0x19e N001 ( 3, 2) [000238] ------------ t238 = LCL_VAR int V26 loc23 u:2 $2b4 N002 ( 3, 2) [000239] ------------ t239 = LCL_VAR int V20 loc17 u:2 $362 /--* t238 int +--* t239 int N003 ( 7, 5) [000240] N------N-U-- t240 = * LE int $36a /--* t240 int N004 ( 9, 7) [000241] ------------ * JTRUE void ------------ BB36 [1A4..1AF) -> BB38 (cond), preds={BB35} succs={BB37,BB38} [000976] ------------ IL_OFFSET void IL offset: 0x1a4 N001 ( 3, 2) [000282] ------------ t282 = LCL_VAR int V26 loc23 u:2 (last use) $2b4 N002 ( 3, 2) [000283] ------------ t283 = LCL_VAR int V20 loc17 u:2 $362 /--* t282 int +--* t283 int N003 ( 7, 5) [000284] ------------ t284 = * SUB int $36b /--* t284 int N005 ( 11, 8) [000286] DA---------- * STORE_LCL_VAR int V29 loc26 d:2 [000977] ------------ IL_OFFSET void IL offset: 0x1ab N001 ( 3, 2) [000287] ------------ t287 = LCL_VAR int V25 loc22 u:2 (last use) $369 N002 ( 1, 1) [000288] ------------ t288 = CNS_INT int 0 $40 /--* t287 int +--* t288 int N003 ( 5, 4) [000289] J------N---- t289 = * EQ int $36c /--* t289 int N004 ( 7, 6) [000290] ------------ * JTRUE void ------------ BB37 [1AF..1C3) -> BB39 (always), preds={BB36} succs={BB39} [000978] ------------ IL_OFFSET void IL offset: 0x1af N001 ( 1, 1) [000305] ------------ t305 = LCL_VAR long V24 loc21 u:2 $450 N002 ( 3, 2) [000308] ------------ t308 = LCL_VAR int V29 loc26 u:2 $36b N003 ( 1, 1) [000309] ------------ t309 = CNS_INT int 63 $66 /--* t308 int +--* t309 int N004 ( 5, 4) [000310] ------------ t310 = * AND int $36d N005 ( 1, 1) [000307] ------------ t307 = CNS_INT long 1 $103 /--* t307 long +--* t310 int N006 ( 10, 6) [000311] ------------ t311 = * LSH long $48e N007 ( 1, 1) [000313] ------------ t313 = CNS_INT long -1 $104 /--* t311 long +--* t313 long N008 ( 12, 8) [000314] ------------ t314 = * ADD long $48f /--* t305 long +--* t314 long N009 ( 14, 10) [000315] ------------ t315 = * AND long $490 N010 ( 1, 1) [000317] ------------ t317 = CNS_INT long 0 $100 /--* t315 long +--* t317 long N011 ( 19, 12) [000318] ------------ t318 = * EQ int $36e /--* t318 int N013 ( 23, 15) [000320] DA---------- * STORE_LCL_VAR int V37 tmp7 d:4 ------------ BB38 [1C3..1C4), preds={BB36} succs={BB39} [000979] ------------ IL_OFFSET void IL offset: 0x1c3 N001 ( 1, 1) [000291] ------------ t291 = CNS_INT int 0 $40 /--* t291 int N003 ( 5, 4) [000293] DA---------- * STORE_LCL_VAR int V37 tmp7 d:3 ------------ BB39 [1C4..1D0), preds={BB37,BB38} succs={BB40} N001 ( 0, 0) [000897] ------------ t897 = PHI_ARG int V37 tmp7 u:4 $36e N002 ( 0, 0) [000896] ------------ t896 = PHI_ARG int V37 tmp7 u:3 $40 /--* t897 int +--* t896 int N003 ( 0, 0) [000867] ------------ t867 = * PHI int /--* t867 int N005 ( 0, 0) [000868] DA---------- * STORE_LCL_VAR int V37 tmp7 d:2 N001 ( 3, 2) [000295] ------------ t295 = LCL_VAR int V37 tmp7 u:2 (last use) $251 /--* t295 int N002 ( 4, 4) [000826] ------------ t826 = * CAST int <- bool <- int $36f /--* t826 int N004 ( 8, 7) [000297] DA---------- * STORE_LCL_VAR int V25 loc22 d:4 [000980] ------------ IL_OFFSET void IL offset: 0x1c6 N001 ( 1, 1) [000298] ------------ t298 = LCL_VAR long V24 loc21 u:2 (last use) $450 N002 ( 3, 2) [000299] ------------ t299 = LCL_VAR int V29 loc26 u:2 (last use) $36b N003 ( 1, 1) [000300] ------------ t300 = CNS_INT int 63 $66 /--* t299 int +--* t300 int N004 ( 5, 4) [000301] ------------ t301 = * AND int $36d /--* t298 long +--* t301 int N005 ( 10, 6) [000302] ------------ t302 = * RSZ long $491 /--* t302 long N007 ( 10, 6) [000304] DA---------- * STORE_LCL_VAR long V24 loc21 d:4 ------------ BB40 [1D0..1E7) -> BB42 (cond), preds={BB35,BB39} succs={BB41,BB42} N001 ( 0, 0) [000894] ------------ t894 = PHI_ARG bool V25 loc22 u:4 $36f N002 ( 0, 0) [000889] ------------ t889 = PHI_ARG bool V25 loc22 u:2 $369 /--* t894 bool +--* t889 bool N003 ( 0, 0) [000864] ------------ t864 = * PHI bool /--* t864 bool N005 ( 0, 0) [000865] DA---------- * STORE_LCL_VAR bool V25 loc22 d:3 N001 ( 0, 0) [000895] ------------ t895 = PHI_ARG long V24 loc21 u:4 $491 N002 ( 0, 0) [000890] ------------ t890 = PHI_ARG long V24 loc21 u:2 $450 /--* t895 long +--* t890 long N003 ( 0, 0) [000861] ------------ t861 = * PHI long /--* t861 long N005 ( 0, 0) [000862] DA---------- * STORE_LCL_VAR long V24 loc21 d:3 N001 ( 3, 2) [000831] -------N---- t831 = LCL_VAR_ADDR byref V76 tmp46 /--* t831 byref N004 ( 3, 3) [000833] DA---------- * STORE_LCL_VAR byref V90 tmp60 d:2 N005 ( 1, 1) [000834] ------------ t834 = LCL_VAR byref V90 tmp60 u:2 Zero Fseq[_bits] $426 N007 ( 3, 2) [000836] -------N---- t836 = LCL_VAR ref (AX) V54 tmp24 $18b /--* t834 byref +--* t836 ref [000981] -A--G------- * STOREIND ref N010 ( 1, 1) [000839] ------------ t839 = LCL_VAR byref V90 tmp60 u:2 (last use) $426 N011 ( 1, 1) [000840] ------------ t840 = CNS_INT long 8 Fseq[_sign] $101 /--* t839 byref +--* t840 long N012 ( 2, 2) [000841] -------N---- t841 = * ADD byref $220 N014 ( 3, 2) [000843] -------N---- t843 = LCL_VAR int (AX) V55 tmp25 $252 /--* t841 byref +--* t843 int [000982] -A--G-----L- * STOREIND int N017 ( 3, 2) [000846] -------N---- t846 = LCL_VAR_ADDR byref V76 tmp46 /--* t846 byref arg0 in rcx N019 ( 38, 24) [000243] --CXG------- t243 = * CALL long System.Numerics.BigInteger.op_Explicit $454 N020 ( 3, 2) [000247] ------------ t247 = LCL_VAR int V20 loc17 u:2 (last use) $362 N021 ( 1, 1) [000248] ------------ t248 = CNS_INT int 63 $66 /--* t247 int +--* t248 int N022 ( 5, 4) [000249] ------------ t249 = * AND int $370 /--* t243 long +--* t249 int N023 ( 47, 29) [000250] ---XG------- t250 = * LSH long $492 N024 ( 1, 1) [000251] ------------ t251 = LCL_VAR long V24 loc21 u:3 (last use) $580 /--* t250 long +--* t251 long N025 ( 49, 31) [000252] ---XG------- t252 = * ADD long $493 /--* t252 long N027 ( 53, 34) [000254] DA-XG------- * STORE_LCL_VAR long V27 loc24 d:2 [000983] ------------ IL_OFFSET void IL offset: 0x1e2 N001 ( 1, 1) [000255] ------------ t255 = LCL_VAR int V13 loc10 u:2 $293 N002 ( 1, 1) [000256] ------------ t256 = CNS_INT int 0 $40 /--* t255 int +--* t256 int N003 ( 3, 3) [000257] N------N---- t257 = * NE int $35a /--* t257 int N004 ( 5, 5) [000258] ------------ * JTRUE void ------------ BB41 [1E7..1EE) -> BB43 (always), preds={BB40} succs={BB43} [000984] ------------ IL_OFFSET void IL offset: 0x1e7 N001 ( 3, 2) [000275] ------------ t275 = LCL_VAR int V22 loc19 u:2 (last use) $24c /--* t275 int N002 ( 4, 3) [000276] ------------ t276 = * NEG int $2c2 N003 ( 1, 1) [000277] ------------ t277 = CNS_INT int -1 $43 /--* t276 int +--* t277 int N004 ( 6, 5) [000278] ------------ t278 = * ADD int $372 /--* t278 int N006 ( 10, 8) [000280] DA---------- * STORE_LCL_VAR int V36 tmp6 d:4 ------------ BB42 [1EE..1F2), preds={BB40} succs={BB43} [000985] ------------ IL_OFFSET void IL offset: 0x1ee N001 ( 1, 1) [000259] ------------ t259 = LCL_VAR int V13 loc10 u:2 (last use) $293 N002 ( 1, 1) [000260] ------------ t260 = CNS_INT int -2 $68 /--* t259 int +--* t260 int N003 ( 3, 3) [000261] ------------ t261 = * ADD int $371 /--* t261 int N005 ( 7, 6) [000263] DA---------- * STORE_LCL_VAR int V36 tmp6 d:3 ------------ BB43 [1F2..202), preds={BB41,BB42} succs={BB44} N001 ( 0, 0) [000893] ------------ t893 = PHI_ARG int V36 tmp6 u:4 $372 N002 ( 0, 0) [000892] ------------ t892 = PHI_ARG int V36 tmp6 u:3 $371 /--* t893 int +--* t892 int N003 ( 0, 0) [000858] ------------ t858 = * PHI int /--* t858 int N005 ( 0, 0) [000859] DA---------- * STORE_LCL_VAR int V36 tmp6 d:2 [000986] ------------ IL_OFFSET void IL offset: 0x1f4 N005 ( 1, 1) [000272] ------------ t272 = LCL_VAR byref V02 arg2 u:1 (last use) $81 N006 ( 1, 1) [000268] ------------ t268 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 N007 ( 3, 2) [000269] ------------ t269 = LCL_VAR long V27 loc24 u:2 (last use) $493 N008 ( 3, 2) [000270] ------------ t270 = LCL_VAR int V36 tmp6 u:2 (last use) $253 N009 ( 3, 2) [000271] ------------ t271 = LCL_VAR int V25 loc22 u:3 (last use) $540 /--* t272 byref arg4 out+20 +--* t268 ref this in rcx +--* t269 long arg1 in rdx +--* t270 int arg2 in r8 +--* t271 int arg3 in r9 N010 ( 28, 18) [000273] --CXG------- t273 = * CALL int FloatingPointType.AssembleFloatingPointValue $2be /--* t273 int N012 ( 28, 18) [000853] DA-XG------- * STORE_LCL_VAR int V51 tmp21 d:4 ------------ BB44 [???..???) (return), preds={BB16,BB30,BB43} succs={} N001 ( 0, 0) [000901] ------------ t901 = PHI_ARG int V51 tmp21 u:5 $5c2 N002 ( 0, 0) [000891] ------------ t891 = PHI_ARG int V51 tmp21 u:4 $2be N003 ( 0, 0) [000887] ------------ t887 = PHI_ARG int V51 tmp21 u:3 $5c7 /--* t901 int +--* t891 int +--* t887 int N004 ( 0, 0) [000855] ------------ t855 = * PHI int /--* t855 int N006 ( 0, 0) [000856] DA---------- * STORE_LCL_VAR int V51 tmp21 d:2 N001 ( 1, 1) [000522] -------N---- t522 = LCL_VAR int V51 tmp21 u:2 (last use) $254 /--* t522 int N002 ( 2, 2) [000523] ------------ * RETURN int $5c9 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Starting PHASE Do 'simple' lowering Bumping outgoingArgSpaceSize to 32 for call [000401] outgoingArgSpaceSize 32 sufficient for call [000406], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000059], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000383], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000394], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000391], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000072], which needs 32 Bumping outgoingArgSpaceSize to 40 for call [000089] outgoingArgSpaceSize 40 sufficient for call [000361], which needs 32 outgoingArgSpaceSize 40 sufficient for call [000371], which needs 32 outgoingArgSpaceSize 40 sufficient for call [000120], which needs 32 outgoingArgSpaceSize 40 sufficient for call [000133], which needs 32 outgoingArgSpaceSize 40 sufficient for call [000141], which needs 32 outgoingArgSpaceSize 40 sufficient for call [000463], which needs 32 outgoingArgSpaceSize 40 sufficient for call [000481], which needs 32 outgoingArgSpaceSize 40 sufficient for call [000347], which needs 32 outgoingArgSpaceSize 40 sufficient for call [000342], which needs 40 outgoingArgSpaceSize 40 sufficient for call [000499], which needs 32 outgoingArgSpaceSize 40 sufficient for call [000208], which needs 32 outgoingArgSpaceSize 40 sufficient for call [000213], which needs 32 outgoingArgSpaceSize 40 sufficient for call [000218], which needs 32 outgoingArgSpaceSize 40 sufficient for call [000234], which needs 32 outgoingArgSpaceSize 40 sufficient for call [000243], which needs 32 outgoingArgSpaceSize 40 sufficient for call [000273], which needs 40 *************** Finishing PHASE Do 'simple' lowering *************** In fgDebugCheckBBlist Trees before Lowering nodeinfo ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0056] 1 1 [???..???) i internal label target LIR BB02 [0000] 1 BB01 1 [000..00D)-> BB04 ( cond ) i label target idxlen LIR BB03 [0001] 1 BB02 0.50 [00D..017) (return) i hascall gcsafe LIR BB04 [0002] 1 BB02 0.50 [017..065)-> BB06 ( cond ) i label target hascall gcsafe LIR BB05 [0038] 1 BB04 0.50 [020..021)-> BB07 (always) i gcsafe LIR BB06 [0039] 1 BB04 0.50 [020..021) i label target gcsafe LIR BB07 [0040] 2 BB05,BB06 0.50 [000..000)-> BB09 ( cond ) i internal label target gcsafe idxlen LIR BB08 [0043] 1 BB07 0.50 [000..000)-> BB10 (always) i internal gcsafe LIR BB09 [0044] 1 BB07 0.50 [000..000) i internal label target gcsafe LIR BB10 [0045] 2 BB08,BB09 0.50 [???..???)-> BB14 ( cond ) i internal label target hascall gcsafe idxlen LIR BB11 [0003] 1 BB10 0.50 [065..070)-> BB13 ( cond ) i hascall gcsafe LIR BB12 [0004] 1 BB11 0.50 [070..07A) (return) i hascall gcsafe LIR BB13 [0005] 1 BB11 0.50 [07A..082) i label target hascall gcsafe LIR BB14 [0006] 2 BB10,BB13 0.50 [082..092)-> BB16 ( cond ) i label target hascall gcsafe LIR BB15 [0007] 1 BB14 0.50 [092..096)-> BB17 ( cond ) i gcsafe LIR BB16 [0008] 2 BB14,BB15 0.50 [096..0A7)-> BB44 (always) i label target hascall gcsafe LIR BB17 [0009] 1 BB15 0.50 [0A7..0B0)-> BB19 ( cond ) i label target gcsafe LIR BB18 [0010] 1 BB17 0.50 [0B0..0B4)-> BB20 (always) i gcsafe LIR BB19 [0011] 1 BB17 0.50 [0B4..0BE) i label target gcsafe LIR BB20 [0012] 2 BB18,BB19 0.50 [0BE..0C4)-> BB23 ( cond ) i label target gcsafe LIR BB21 [0013] 1 BB20 0.50 [0C4..0D9)-> BB23 ( cond ) i hascall gcsafe idxlen LIR BB22 [0014] 1 BB21 0.50 [0D9..0E3) (return) i hascall gcsafe LIR BB23 [0015] 2 BB20,BB21 0.50 [0E3..117)-> BB25 ( cond ) i label target hascall gcsafe LIR BB24 [0016] 1 BB23 0.50 [117..11A)-> BB26 (always) i gcsafe LIR BB25 [0017] 1 BB23 0.50 [11A..11F) i label target gcsafe LIR BB26 [0018] 2 BB24,BB25 0.50 [11F..126)-> BB28 ( cond ) i label target gcsafe LIR BB27 [0019] 1 BB26 0.50 [126..12F) i hascall gcsafe LIR BB28 [0020] 2 BB26,BB27 0.50 [12F..13E)-> BB32 ( cond ) i label target gcsafe LIR BB29 [0021] 1 BB28 0.50 [13E..144)-> BB31 ( cond ) i gcsafe LIR BB30 [0022] 1 BB29 0.50 [144..155)-> BB44 (always) i hascall gcsafe LIR BB31 [0023] 1 BB29 0.50 [155..15C) i label target gcsafe LIR BB32 [0024] 2 BB28,BB31 0.50 [15C..167)-> BB34 ( cond ) i label target hascall gcsafe LIR BB33 [0025] 1 BB32 0.50 [167..16B)-> BB35 (always) i gcsafe LIR BB34 [0026] 1 BB32 0.50 [16B..16F) i label target gcsafe LIR BB35 [0027] 2 BB33,BB34 0.50 [16F..1A4)-> BB40 ( cond ) i label target hascall gcsafe LIR BB36 [0028] 1 BB35 0.50 [1A4..1AF)-> BB38 ( cond ) i gcsafe LIR BB37 [0029] 1 BB36 0.50 [1AF..1C3)-> BB39 (always) i gcsafe LIR BB38 [0030] 1 BB36 0.50 [1C3..1C4) i label target gcsafe LIR BB39 [0031] 2 BB37,BB38 0.50 [1C4..1D0) i label target gcsafe LIR BB40 [0032] 2 BB35,BB39 0.50 [1D0..1E7)-> BB42 ( cond ) i label target hascall gcsafe LIR BB41 [0033] 1 BB40 0.50 [1E7..1EE)-> BB43 (always) i gcsafe LIR BB42 [0034] 1 BB40 0.50 [1EE..1F2) i label target gcsafe LIR BB43 [0035] 2 BB41,BB42 0.50 [1F2..202) i label target hascall gcsafe LIR BB44 [0054] 3 BB16,BB30,BB43 0.50 [???..???) (return) keep internal target gcsafe LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} N001 ( 1, 1) [000531] ------------ t531 = LCL_VAR byref V00 arg0 u:1 Zero Fseq[Mantissa] $80 /--* t531 byref N002 ( 3, 2) [000532] n----------- t532 = * IND ref /--* t532 ref N004 ( 3, 3) [000533] DA---------- * STORE_LCL_VAR ref V52 tmp22 d:2 N005 ( 1, 1) [000535] ------------ t535 = LCL_VAR byref V00 arg0 u:1 (last use) $80 N006 ( 1, 1) [000536] ------------ t536 = CNS_INT long 8 Fseq[Exponent] $101 /--* t535 byref +--* t536 long N007 ( 2, 2) [000537] -------N---- t537 = * ADD byref $200 /--* t537 byref N008 ( 4, 4) [000538] n----------- t538 = * IND int /--* t538 int N010 ( 4, 4) [000539] DA---------- * STORE_LCL_VAR int V53 tmp23 d:2 ------------ BB02 [000..00D) -> BB04 (cond), preds={BB01} succs={BB03,BB04} [000910] ------------ IL_OFFSET void IL offset: 0x0 N001 ( 1, 1) [000002] ------------ t2 = LCL_VAR ref V52 tmp22 u:2 [000987] ------------ t987 = CNS_INT long 8 /--* t2 ref +--* t987 long [000988] ------------ t988 = * ADD ref /--* t988 ref N002 ( 3, 3) [000003] ---XG------- t3 = * IND int N003 ( 1, 1) [000004] ------------ t4 = CNS_INT int 0 $40 /--* t3 int +--* t4 int N004 ( 5, 5) [000005] J--XG--N---- t5 = * NE int /--* t5 int N005 ( 7, 7) [000006] ---XG------- * JTRUE void ------------ BB03 [00D..017) (return), preds={BB02} succs={} [000911] ------------ IL_OFFSET void IL offset: 0xd N002 ( 1, 1) [000400] ------------ t400 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t400 ref this in rcx N003 ( 21, 10) [000401] --CXG------- t401 = * CALLV ind long FloatingPointType.get_Zero $459 N004 ( 1, 1) [000399] ------------ t399 = LCL_VAR byref V02 arg2 u:1 (last use) $81 /--* t399 byref +--* t401 long [000912] -ACXG------- * STOREIND long N001 ( 1, 1) [000404] ------------ t404 = CNS_INT int 1 $41 /--* t404 int N002 ( 2, 2) [000520] ------------ * RETURN int $5cb ------------ BB04 [017..065) -> BB06 (cond), preds={BB02} succs={BB05,BB06} N002 ( 1, 1) [000007] ------------ t7 = LCL_VAR ref V01 arg1 u:1 $c0 /--* t7 ref this in rcx N003 ( 21, 10) [000406] --CXG------- t406 = * CALLV ind int FloatingPointType.get_DenormalMantissaBits $282 N004 ( 1, 1) [000407] ------------ t407 = CNS_INT int 1 $41 /--* t406 int +--* t407 int N005 ( 23, 12) [000408] ---XG------- t408 = * ADD int $346 /--* t408 int N006 ( 24, 14) [000409] ---XG------- t409 = * CAST int <- ushort <- int $347 N007 ( 1, 1) [000010] ------------ t10 = CNS_INT int 1 $41 /--* t409 int +--* t10 int N008 ( 26, 16) [000011] ---XG------- t11 = * ADD int $348 /--* t11 int N010 ( 30, 19) [000013] DA-XG------- * STORE_LCL_VAR int V03 loc0 d:2 [000913] ------------ IL_OFFSET void IL offset: 0x20 N001 ( 1, 1) [000017] ------------ t17 = LCL_VAR int V53 tmp23 u:2 /--* t17 int N003 ( 5, 4) [000424] DA--G------- * STORE_LCL_VAR int V40 tmp10 d:2 [000914] ------------ IL_OFFSET void IL offset: 0x20 N001 ( 1, 1) [000412] ------------ t412 = LCL_VAR int V40 tmp10 u:2 N002 ( 1, 1) [000411] ------------ t411 = CNS_INT int 0 $40 /--* t412 int +--* t411 int N003 ( 3, 3) [000413] J------N---- t413 = * LE int /--* t413 int N004 ( 5, 5) [000414] ------------ * JTRUE void ------------ BB05 [020..021) -> BB07 (always), preds={BB04} succs={BB07} [000915] ------------ IL_OFFSET void IL offset: 0x20 N001 ( 3, 2) [000419] ------------ t419 = LCL_VAR int V53 tmp23 u:2 (last use) /--* t419 int N003 ( 7, 5) [000421] DA---------- * STORE_LCL_VAR int V39 tmp9 d:4 ------------ BB06 [020..021), preds={BB04} succs={BB07} [000916] ------------ IL_OFFSET void IL offset: 0x20 N001 ( 1, 1) [000415] ------------ t415 = CNS_INT int 0 $40 /--* t415 int N003 ( 5, 4) [000417] DA---------- * STORE_LCL_VAR int V39 tmp9 d:3 ------------ BB07 [000..000) -> BB09 (cond), preds={BB05,BB06} succs={BB08,BB09} N001 ( 0, 0) [000909] ------------ t909 = PHI_ARG int V39 tmp9 u:4 N002 ( 0, 0) [000908] ------------ t908 = PHI_ARG int V39 tmp9 u:3 $40 /--* t909 int +--* t908 int N003 ( 0, 0) [000885] ------------ t885 = * PHI int /--* t885 int N005 ( 0, 0) [000886] DA---------- * STORE_LCL_VAR int V39 tmp9 d:2 N001 ( 3, 2) [000422] ------------ t422 = LCL_VAR int V39 tmp9 u:2 $241 /--* t422 int N003 ( 3, 3) [000021] DA---------- * STORE_LCL_VAR int V31 tmp1 d:2 N001 ( 1, 1) [000428] ------------ t428 = LCL_VAR ref V52 tmp22 u:2 [000989] ------------ t989 = CNS_INT long 8 /--* t428 ref +--* t989 long [000990] ------------ t990 = * ADD ref /--* t990 ref N002 ( 3, 3) [000429] ---XG------- t429 = * IND int /--* t429 int N004 ( 3, 3) [000443] DA-XG------- * STORE_LCL_VAR int V42 tmp12 d:2 N001 ( 3, 2) [000023] ------------ t23 = LCL_VAR int V31 tmp1 u:2 (last use) $241 N002 ( 1, 1) [000431] ------------ t431 = LCL_VAR int V42 tmp12 u:2 /--* t23 int +--* t431 int N003 ( 5, 4) [000432] N------N-U-- t432 = * LE int /--* t432 int N004 ( 7, 6) [000433] ------------ * JTRUE void ------------ BB08 [000..000) -> BB10 (always), preds={BB07} succs={BB10} N001 ( 1, 1) [000438] ------------ t438 = LCL_VAR int V42 tmp12 u:2 (last use) /--* t438 int N003 ( 1, 3) [000440] DA---------- * STORE_LCL_VAR int V41 tmp11 d:4 ------------ BB09 [000..000), preds={BB07} succs={BB10} N001 ( 1, 1) [000434] ------------ t434 = LCL_VAR int V31 tmp1 u:2 $241 /--* t434 int N003 ( 1, 3) [000436] DA---------- * STORE_LCL_VAR int V41 tmp11 d:3 ------------ BB10 [???..???) -> BB14 (cond), preds={BB08,BB09} succs={BB11,BB14} N001 ( 0, 0) [000907] ------------ t907 = PHI_ARG int V41 tmp11 u:4 N002 ( 0, 0) [000906] ------------ t906 = PHI_ARG int V41 tmp11 u:3 $241 /--* t907 int +--* t906 int N003 ( 0, 0) [000882] ------------ t882 = * PHI int /--* t882 int N005 ( 0, 0) [000883] DA---------- * STORE_LCL_VAR int V41 tmp11 d:2 N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR int V31 tmp1 u:2 (last use) $241 N002 ( 1, 1) [000032] ------------ t32 = LCL_VAR int V41 tmp11 u:2 $242 /--* t22 int +--* t32 int N003 ( 3, 3) [000033] ------------ t33 = * SUB int $34e /--* t33 int N005 ( 7, 6) [000035] DA---------- * STORE_LCL_VAR int V05 loc2 d:2 [000917] ------------ IL_OFFSET void IL offset: 0x42 N001 ( 1, 1) [000042] ------------ t42 = LCL_VAR int V41 tmp11 u:2 $242 /--* t42 int N003 ( 5, 4) [000044] DA---------- * STORE_LCL_VAR int V08 loc5 d:2 N001 ( 1, 1) [000447] ------------ t447 = LCL_VAR ref V52 tmp22 u:2 [000991] ------------ t991 = CNS_INT long 8 /--* t447 ref +--* t991 long [000992] ------------ t992 = * ADD ref /--* t992 ref N002 ( 3, 3) [000448] ---XG------- t448 = * IND int /--* t448 int N004 ( 7, 6) [000050] DA-XG------- * STORE_LCL_VAR int V09 loc6 d:2 [000918] ------------ IL_OFFSET void IL offset: 0x4f N001 ( 3, 2) [000051] ------------ t51 = LCL_VAR int V09 loc6 u:2 N002 ( 1, 1) [000052] ------------ t52 = LCL_VAR int V08 loc5 u:2 $242 /--* t51 int +--* t52 int N003 ( 5, 4) [000053] ------------ t53 = * SUB int /--* t53 int N005 ( 5, 4) [000055] DA---------- * STORE_LCL_VAR int V10 loc7 d:2 N001 ( 3, 2) [000063] -------N---- t63 = LCL_VAR_ADDR byref V11 loc8 * ref V11._bits (offs=0x00) -> V54 tmp24 * int V11._sign (offs=0x08) -> V55 tmp25 /--* t63 byref N004 ( 7, 6) [000563] DA--------L- * STORE_LCL_VAR long V75 tmp45 d:2 N005 ( 3, 2) [000547] -------N---- t547 = LCL_VAR_ADDR byref V73 tmp43 /--* t547 byref N008 ( 3, 3) [000549] DA---------- * STORE_LCL_VAR byref V74 tmp44 d:2 N009 ( 1, 1) [000550] ------------ t550 = LCL_VAR byref V74 tmp44 u:2 Zero Fseq[Mantissa] $401 N011 ( 1, 1) [000552] -------N---- t552 = LCL_VAR ref V52 tmp22 u:2 /--* t550 byref +--* t552 ref [000919] -A---------- * STOREIND ref N014 ( 1, 1) [000555] ------------ t555 = LCL_VAR byref V74 tmp44 u:2 (last use) $401 N015 ( 1, 1) [000556] ------------ t556 = CNS_INT long 8 Fseq[Exponent] $101 /--* t555 byref +--* t556 long N016 ( 2, 2) [000557] -------N---- t557 = * ADD byref $203 N018 ( 1, 1) [000559] -------N---- t559 = LCL_VAR int V53 tmp23 u:2 /--* t557 byref +--* t559 int [000920] -A--------L- * STOREIND int N023 ( 3, 2) [000564] ------------ t564 = LCL_VAR long V75 tmp45 u:2 (last use) $400 N024 ( 3, 2) [000565] -------N---- t565 = LCL_VAR_ADDR byref V73 tmp43 N026 ( 1, 1) [000058] ------------ t58 = LCL_VAR int V08 loc5 u:2 (last use) $242 N027 ( 1, 1) [000057] ------------ t57 = CNS_INT int 0 $40 /--* t564 long arg0 in rcx +--* t565 byref arg1 in rdx +--* t58 int arg3 in r9 +--* t57 int arg2 in r8 N028 ( 49, 35) [000059] S-CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger $VN.Void [000921] ------------ IL_OFFSET void IL offset: 0x61 N001 ( 3, 2) [000065] ------------ t65 = LCL_VAR int V05 loc2 u:2 $34e N002 ( 1, 1) [000066] ------------ t66 = CNS_INT int 0 $40 /--* t65 int +--* t66 int N003 ( 5, 4) [000067] N------N---- t67 = * EQ int $351 /--* t67 int N004 ( 7, 6) [000068] ------------ * JTRUE void ------------ BB11 [065..070) -> BB13 (cond), preds={BB10} succs={BB12,BB13} N002 ( 1, 1) [000382] ------------ t382 = LCL_VAR ref V01 arg1 u:1 $c0 /--* t382 ref this in rcx N003 ( 15, 8) [000383] --CXG------- t383 = * CALL int FloatingPointType.get_OverflowDecimalExponent $291 /--* t383 int N004 ( 16, 10) [000385] ---XG------- t385 = * CAST long <- int $480 N005 ( 3, 2) [000380] ------------ t380 = LCL_VAR int V05 loc2 u:2 $34e /--* t380 int N006 ( 4, 4) [000381] ---------U-- t381 = * CAST long <- ulong <- uint $481 /--* t385 long +--* t381 long N007 ( 21, 15) [000386] J--XG--N---- t386 = * GE int $352 /--* t386 int N008 ( 23, 17) [000387] ---XG------- * JTRUE void ------------ BB12 [070..07A) (return), preds={BB11} succs={} [000922] ------------ IL_OFFSET void IL offset: 0x70 N002 ( 1, 1) [000393] ------------ t393 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t393 ref this in rcx N003 ( 21, 10) [000394] --CXG------- t394 = * CALLV ind long FloatingPointType.get_Infinity $458 N004 ( 1, 1) [000392] ------------ t392 = LCL_VAR byref V02 arg2 u:1 (last use) $81 /--* t392 byref +--* t394 long [000923] -ACXG------- * STOREIND long N001 ( 1, 1) [000397] ------------ t397 = CNS_INT int 3 $48 /--* t397 int N002 ( 2, 2) [000521] ------------ * RETURN int $5ca ------------ BB13 [07A..082), preds={BB11} succs={BB14} [000924] ------------ IL_OFFSET void IL offset: 0x7a N003 ( 3, 2) [000388] -------N---- t388 = LCL_VAR_ADDR byref V11 loc8 * ref V11._bits (offs=0x00) -> V54 tmp24 * int V11._sign (offs=0x08) -> V55 tmp25 N005 ( 3, 2) [000390] ------------ t390 = LCL_VAR int V05 loc2 u:2 (last use) $34e /--* t388 byref arg0 in rcx +--* t390 int arg1 in rdx N006 ( 20, 12) [000391] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen $VN.Void ------------ BB14 [082..092) -> BB16 (cond), preds={BB10,BB13} succs={BB15,BB16} N001 ( 3, 2) [000577] -------N---- t577 = LCL_VAR_ADDR byref V76 tmp46 /--* t577 byref N004 ( 3, 3) [000579] DA---------- * STORE_LCL_VAR byref V77 tmp47 d:2 N005 ( 1, 1) [000580] ------------ t580 = LCL_VAR byref V77 tmp47 u:2 Zero Fseq[_bits] $405 N007 ( 3, 2) [000582] -------N---- t582 = LCL_VAR ref (AX) V54 tmp24 $181 /--* t580 byref +--* t582 ref [000925] -A--G------- * STOREIND ref N010 ( 1, 1) [000585] ------------ t585 = LCL_VAR byref V77 tmp47 u:2 (last use) $405 N011 ( 1, 1) [000586] ------------ t586 = CNS_INT long 8 Fseq[_sign] $101 /--* t585 byref +--* t586 long N012 ( 2, 2) [000587] -------N---- t587 = * ADD byref $206 N014 ( 3, 2) [000589] -------N---- t589 = LCL_VAR int (AX) V55 tmp25 $243 /--* t587 byref +--* t589 int [000926] -A--G-----L- * STOREIND int N018 ( 3, 2) [000592] -------N---- t592 = LCL_VAR_ADDR byref V76 tmp46 N020 ( 3, 3) [000071] ------------ t71 = LCL_VAR_ADDR long V12 loc9 $443 /--* t592 byref arg0 in rcx +--* t71 long arg1 in rdx N021 ( 41, 28) [000072] --CXG------- t72 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $293 /--* t72 int N023 ( 41, 28) [000077] DA-XG------- * STORE_LCL_VAR int V13 loc10 d:2 [000927] ------------ IL_OFFSET void IL offset: 0x8d N001 ( 1, 1) [000078] ------------ t78 = LCL_VAR int V13 loc10 u:2 $293 N002 ( 3, 2) [000079] ------------ t79 = LCL_VAR int V03 loc0 u:2 $348 /--* t78 int +--* t79 int N003 ( 5, 4) [000080] N------N-U-- t80 = * GE int $353 /--* t80 int N004 ( 7, 6) [000081] ------------ * JTRUE void ------------ BB15 [092..096) -> BB17 (cond), preds={BB14} succs={BB16,BB17} [000928] ------------ IL_OFFSET void IL offset: 0x92 N001 ( 1, 1) [000091] ------------ t91 = LCL_VAR int V10 loc7 u:2 N002 ( 1, 1) [000092] ------------ t92 = CNS_INT int 0 $40 /--* t91 int +--* t92 int N003 ( 3, 3) [000093] J------N---- t93 = * NE int /--* t93 int N004 ( 5, 5) [000094] ------------ * JTRUE void ------------ BB16 [096..0A7) -> BB44 (always), preds={BB14,BB15} succs={BB44} [000929] ------------ IL_OFFSET void IL offset: 0x96 N005 ( 1, 1) [000088] ------------ t88 = LCL_VAR byref V02 arg2 u:1 (last use) $81 N006 ( 1, 1) [000084] ------------ t84 = LCL_VAR int V10 loc7 u:2 (last use) N007 ( 1, 1) [000085] ------------ t85 = CNS_INT int 0 $40 /--* t84 int +--* t85 int N008 ( 6, 3) [000086] N----------- t86 = * NE int N009 ( 3, 2) [000082] ------------ t82 = LCL_VAR ref (AX) V12 loc9 $18d N010 ( 1, 1) [000083] ------------ t83 = LCL_VAR int V13 loc10 u:2 (last use) $293 N011 ( 1, 1) [000087] ------------ t87 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t88 byref arg4 out+20 +--* t86 int arg2 in r8 +--* t82 ref arg0 in rcx +--* t83 int arg1 in rdx +--* t87 ref arg3 in r9 N012 ( 29, 17) [000089] --CXG------- t89 = * CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits $5c7 /--* t89 int N014 ( 29, 17) [000600] DA-XG------- * STORE_LCL_VAR int V51 tmp21 d:3 ------------ BB17 [0A7..0B0) -> BB19 (cond), preds={BB15} succs={BB18,BB19} [000930] ------------ IL_OFFSET void IL offset: 0xa7 N001 ( 1, 1) [000097] ------------ t97 = LCL_VAR int V53 tmp23 u:2 N002 ( 1, 1) [000098] ------------ t98 = CNS_INT int 0 $40 /--* t97 int +--* t98 int N003 ( 3, 3) [000099] J---G--N---- t99 = * LT int /--* t99 int N004 ( 5, 5) [000100] ----G------- * JTRUE void ------------ BB18 [0B0..0B4) -> BB20 (always), preds={BB17} succs={BB20} [000931] ------------ IL_OFFSET void IL offset: 0xb0 N001 ( 1, 1) [000376] ------------ t376 = LCL_VAR int V10 loc7 u:2 /--* t376 int N003 ( 5, 4) [000378] DA---------- * STORE_LCL_VAR int V32 tmp2 d:4 ------------ BB19 [0B4..0BE), preds={BB17} succs={BB20} [000932] ------------ IL_OFFSET void IL offset: 0xb4 N001 ( 1, 1) [000101] ------------ t101 = LCL_VAR int V10 loc7 u:2 N002 ( 1, 1) [000104] ------------ t104 = LCL_VAR int V53 tmp23 u:2 /--* t101 int +--* t104 int N003 ( 3, 3) [000106] ----G------- t106 = * SUB int /--* t106 int N005 ( 7, 6) [000108] DA--G------- * STORE_LCL_VAR int V32 tmp2 d:3 ------------ BB20 [0BE..0C4) -> BB23 (cond), preds={BB18,BB19} succs={BB21,BB23} N001 ( 0, 0) [000905] ------------ t905 = PHI_ARG int V32 tmp2 u:4 N002 ( 0, 0) [000904] ------------ t904 = PHI_ARG int V32 tmp2 u:3 /--* t905 int +--* t904 int N003 ( 0, 0) [000879] ------------ t879 = * PHI int /--* t879 int N005 ( 0, 0) [000880] DA---------- * STORE_LCL_VAR int V32 tmp2 d:2 N001 ( 3, 2) [000110] ------------ t110 = LCL_VAR int V32 tmp2 u:2 (last use) $244 /--* t110 int N003 ( 7, 5) [000112] DA---------- * STORE_LCL_VAR int V14 loc11 d:2 [000933] ------------ IL_OFFSET void IL offset: 0xc0 N001 ( 1, 1) [000113] ------------ t113 = LCL_VAR int V13 loc10 u:2 $293 N002 ( 1, 1) [000114] ------------ t114 = CNS_INT int 0 $40 /--* t113 int +--* t114 int N003 ( 3, 3) [000115] J------N---- t115 = * NE int $35a /--* t115 int N004 ( 5, 5) [000116] ------------ * JTRUE void ------------ BB21 [0C4..0D9) -> BB23 (cond), preds={BB20} succs={BB22,BB23} N001 ( 1, 1) [000455] ------------ t455 = LCL_VAR ref V52 tmp22 u:2 [000993] ------------ t993 = CNS_INT long 8 /--* t455 ref +--* t993 long [000994] ------------ t994 = * ADD ref /--* t994 ref N002 ( 3, 3) [000456] ---XG------- t456 = * IND int /--* t456 int N003 ( 4, 5) [000358] ---XG------- t358 = * CAST long <- int N004 ( 3, 2) [000352] ------------ t352 = LCL_VAR int V14 loc11 u:2 $244 /--* t352 int N005 ( 4, 4) [000353] ---------U-- t353 = * CAST long <- ulong <- uint $486 /--* t353 long +--* t358 long N006 ( 9, 10) [000359] ---XG------- t359 = * SUB long /--* t359 long N008 ( 13, 13) [000363] DA-XG------- * STORE_LCL_VAR long V38 tmp8 d:2 N002 ( 1, 1) [000360] ------------ t360 = LCL_VAR ref V01 arg1 u:1 $c0 /--* t360 ref this in rcx N003 ( 15, 8) [000361] --CXG------- t361 = * CALL int FloatingPointType.get_OverflowDecimalExponent $298 /--* t361 int N004 ( 16, 10) [000366] ---XG------- t366 = * CAST long <- int $48b N005 ( 3, 2) [000364] ------------ t364 = LCL_VAR long V38 tmp8 u:2 (last use) /--* t366 long +--* t364 long N006 ( 20, 13) [000367] J--XG--N---- t367 = * GE int /--* t367 int N007 ( 22, 15) [000368] ---XG------- * JTRUE void ------------ BB22 [0D9..0E3) (return), preds={BB21} succs={} [000934] ------------ IL_OFFSET void IL offset: 0xd9 N002 ( 1, 1) [000370] ------------ t370 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t370 ref this in rcx N003 ( 21, 10) [000371] --CXG------- t371 = * CALLV ind long FloatingPointType.get_Zero $457 N004 ( 1, 1) [000369] ------------ t369 = LCL_VAR byref V02 arg2 u:1 (last use) $81 /--* t369 byref +--* t371 long [000935] -ACXG------- * STOREIND long N001 ( 1, 1) [000374] ------------ t374 = CNS_INT int 2 $42 /--* t374 int N002 ( 2, 2) [000524] ------------ * RETURN int $5c4 ------------ BB23 [0E3..117) -> BB25 (cond), preds={BB20,BB21} succs={BB24,BB25} N001 ( 3, 2) [000124] -------N---- t124 = LCL_VAR_ADDR byref V15 loc12 * ref V15._bits (offs=0x00) -> V56 tmp26 * int V15._sign (offs=0x08) -> V57 tmp27 /--* t124 byref N004 ( 7, 6) [000623] DA--------L- * STORE_LCL_VAR long V79 tmp49 d:2 N005 ( 3, 2) [000607] -------N---- t607 = LCL_VAR_ADDR byref V73 tmp43 /--* t607 byref N008 ( 3, 3) [000609] DA---------- * STORE_LCL_VAR byref V78 tmp48 d:2 N009 ( 1, 1) [000610] ------------ t610 = LCL_VAR byref V78 tmp48 u:2 Zero Fseq[Mantissa] $409 N011 ( 1, 1) [000612] -------N---- t612 = LCL_VAR ref V52 tmp22 u:2 (last use) /--* t610 byref +--* t612 ref [000936] -A---------- * STOREIND ref N014 ( 1, 1) [000615] ------------ t615 = LCL_VAR byref V78 tmp48 u:2 (last use) $409 N015 ( 1, 1) [000616] ------------ t616 = CNS_INT long 8 Fseq[Exponent] $101 /--* t615 byref +--* t616 long N016 ( 2, 2) [000617] -------N---- t617 = * ADD byref $209 N018 ( 1, 1) [000619] -------N---- t619 = LCL_VAR int V53 tmp23 u:2 (last use) /--* t617 byref +--* t619 int [000937] -A--------L- * STOREIND int N023 ( 3, 2) [000624] ------------ t624 = LCL_VAR long V79 tmp49 u:2 (last use) $408 N024 ( 3, 2) [000625] -------N---- t625 = LCL_VAR_ADDR byref V73 tmp43 N026 ( 3, 2) [000118] ------------ t118 = LCL_VAR int V08 loc5 u:2 (last use) $242 N027 ( 3, 2) [000119] ------------ t119 = LCL_VAR int V09 loc6 u:2 (last use) /--* t624 long arg0 in rcx +--* t625 byref arg1 in rdx +--* t118 int arg2 in r8 +--* t119 int arg3 in r9 N028 ( 53, 37) [000120] S-CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger $VN.Void [000938] ------------ IL_OFFSET void IL offset: 0xef N003 ( 2, 10) [000131] ------------ t131 = CNS_INT long 0x7ff815262aa0 $102 N004 ( 1, 4) [000132] ------------ t132 = CNS_INT int 173 $58 /--* t131 long arg0 in rcx +--* t132 int arg1 in rdx N005 ( 17, 21) [000133] H-CXG------- t133 = * CALL help long HELPER.CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE $48d N001 ( 2, 10) [000634] I----------- t634 = CNS_INT(h) long 0xd1ffab1e static Fseq[BigOne] $4c2 /--* t634 long N002 ( 4, 12) [000633] n---G------- t633 = * IND ref N003 ( 1, 1) [000635] ------------ t635 = CNS_INT long 8 Fseq[#FirstElem] $101 /--* t633 ref +--* t635 long N004 ( 6, 14) [000632] ----G------- t632 = * ADD byref /--* t632 byref N006 ( 6, 14) [000637] DA--G------- * STORE_LCL_VAR byref V80 tmp50 d:2 N007 ( 1, 1) [000639] ------------ t639 = LCL_VAR byref V80 tmp50 u:2 Zero Fseq[_bits] /--* t639 byref N008 ( 3, 2) [000640] ---X-------- t640 = * IND ref /--* t640 ref N010 ( 7, 5) [000641] DA-XG------- * STORE_LCL_VAR ref (AX) V58 tmp28 N012 ( 1, 1) [000644] ------------ t644 = LCL_VAR byref V80 tmp50 u:2 (last use) N013 ( 1, 1) [000645] ------------ t645 = CNS_INT long 8 Fseq[_sign] $101 /--* t644 byref +--* t645 long N014 ( 2, 2) [000646] -------N---- t646 = * ADD byref /--* t646 byref N015 ( 4, 4) [000647] ---X-------- t647 = * IND int /--* t647 int N017 ( 8, 7) [000648] DA-XG------- * STORE_LCL_VAR int (AX) V59 tmp29 [000939] ------------ IL_OFFSET void IL offset: 0xf6 N003 ( 3, 2) [000138] -------N---- t138 = LCL_VAR_ADDR byref V16 loc13 * ref V16._bits (offs=0x00) -> V58 tmp28 * int V16._sign (offs=0x08) -> V59 tmp29 N005 ( 3, 2) [000140] ------------ t140 = LCL_VAR int V14 loc11 u:2 (last use) $244 /--* t138 byref arg0 in rcx +--* t140 int arg1 in rdx N006 ( 20, 12) [000141] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen $VN.Void [000940] ------------ IL_OFFSET void IL offset: 0xff N001 ( 3, 2) [000653] -------N---- t653 = LCL_VAR ref (AX) V56 tmp26 $184 /--* t653 ref N003 ( 7, 5) [000654] DA--G------- * STORE_LCL_VAR ref V64 tmp34 d:2 N004 ( 3, 2) [000656] -------N---- t656 = LCL_VAR int (AX) V57 tmp27 $246 /--* t656 int N006 ( 7, 5) [000657] DA--G------- * STORE_LCL_VAR int V65 tmp35 d:2 [000941] ------------ IL_OFFSET void IL offset: 0xff N001 ( 3, 2) [000663] -------N---- t663 = LCL_VAR_ADDR byref V76 tmp46 /--* t663 byref N004 ( 3, 3) [000665] DA---------- * STORE_LCL_VAR byref V81 tmp51 d:2 N005 ( 1, 1) [000666] ------------ t666 = LCL_VAR byref V81 tmp51 u:2 Zero Fseq[_bits] $40e N007 ( 3, 2) [000668] -------N---- t668 = LCL_VAR ref V64 tmp34 u:2 (last use) $184 /--* t666 byref +--* t668 ref [000942] -A---------- * STOREIND ref N010 ( 1, 1) [000671] ------------ t671 = LCL_VAR byref V81 tmp51 u:2 (last use) $40e N011 ( 1, 1) [000672] ------------ t672 = CNS_INT long 8 Fseq[_sign] $101 /--* t671 byref +--* t672 long N012 ( 2, 2) [000673] -------N---- t673 = * ADD byref $211 N014 ( 3, 2) [000675] -------N---- t675 = LCL_VAR int V65 tmp35 u:2 (last use) $246 /--* t673 byref +--* t675 int [000943] -A--------L- * STOREIND int N018 ( 3, 2) [000678] -------N---- t678 = LCL_VAR_ADDR byref V76 tmp46 N020 ( 3, 3) [000462] ------------ t462 = LCL_VAR_ADDR long V45 tmp15 $449 /--* t678 byref arg0 in rcx +--* t462 long arg1 in rdx N021 ( 41, 28) [000463] --CXG------- t463 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $29f /--* t463 int N023 ( 45, 31) [000468] DA-XG------- * STORE_LCL_VAR int V43 tmp13 d:2 [000944] ------------ IL_OFFSET void IL offset: 0xff N001 ( 1, 1) [000473] ------------ t473 = CNS_INT ref null $VN.Null /--* t473 ref N003 ( 5, 4) [000475] DA--G------- * STORE_LCL_VAR ref (AX) V45 tmp15 N001 ( 3, 2) [000469] ------------ t469 = LCL_VAR int V43 tmp13 u:2 $29f /--* t469 int N003 ( 7, 5) [000148] DA---------- * STORE_LCL_VAR int V17 loc14 d:2 [000945] ------------ IL_OFFSET void IL offset: 0x108 N001 ( 3, 2) [000682] -------N---- t682 = LCL_VAR ref (AX) V58 tmp28 $185 /--* t682 ref N003 ( 7, 5) [000683] DA--G------- * STORE_LCL_VAR ref V66 tmp36 d:2 N004 ( 3, 2) [000685] -------N---- t685 = LCL_VAR int (AX) V59 tmp29 $247 /--* t685 int N006 ( 7, 5) [000686] DA--G------- * STORE_LCL_VAR int V67 tmp37 d:2 [000946] ------------ IL_OFFSET void IL offset: 0x108 N001 ( 3, 2) [000692] -------N---- t692 = LCL_VAR_ADDR byref V76 tmp46 /--* t692 byref N004 ( 3, 3) [000694] DA---------- * STORE_LCL_VAR byref V82 tmp52 d:2 N005 ( 1, 1) [000695] ------------ t695 = LCL_VAR byref V82 tmp52 u:2 Zero Fseq[_bits] $411 N007 ( 3, 2) [000697] -------N---- t697 = LCL_VAR ref V66 tmp36 u:2 (last use) $185 /--* t695 byref +--* t697 ref [000947] -A---------- * STOREIND ref N010 ( 1, 1) [000700] ------------ t700 = LCL_VAR byref V82 tmp52 u:2 (last use) $411 N011 ( 1, 1) [000701] ------------ t701 = CNS_INT long 8 Fseq[_sign] $101 /--* t700 byref +--* t701 long N012 ( 2, 2) [000702] -------N---- t702 = * ADD byref $214 N014 ( 3, 2) [000704] -------N---- t704 = LCL_VAR int V67 tmp37 u:2 (last use) $247 /--* t702 byref +--* t704 int [000948] -A--------L- * STOREIND int N018 ( 3, 2) [000707] -------N---- t707 = LCL_VAR_ADDR byref V76 tmp46 N020 ( 3, 3) [000480] ------------ t480 = LCL_VAR_ADDR long V48 tmp18 $44b /--* t707 byref arg0 in rcx +--* t480 long arg1 in rdx N021 ( 41, 28) [000481] --CXG------- t481 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $2a3 /--* t481 int N023 ( 45, 31) [000486] DA-XG------- * STORE_LCL_VAR int V46 tmp16 d:2 [000949] ------------ IL_OFFSET void IL offset: 0x108 N001 ( 1, 1) [000491] ------------ t491 = CNS_INT ref null $VN.Null /--* t491 ref N003 ( 5, 4) [000493] DA--G------- * STORE_LCL_VAR ref (AX) V48 tmp18 N001 ( 3, 2) [000487] ------------ t487 = LCL_VAR int V46 tmp16 u:2 $2a3 /--* t487 int N003 ( 7, 5) [000155] DA---------- * STORE_LCL_VAR int V18 loc15 d:2 [000950] ------------ IL_OFFSET void IL offset: 0x111 N001 ( 3, 2) [000156] ------------ t156 = LCL_VAR int V18 loc15 u:2 (last use) $2a3 N002 ( 3, 2) [000157] ------------ t157 = LCL_VAR int V17 loc14 u:2 (last use) $29f /--* t156 int +--* t157 int N003 ( 7, 5) [000158] N------N-U-- t158 = * GT int $35f /--* t158 int N004 ( 9, 7) [000159] ------------ * JTRUE void ------------ BB24 [117..11A) -> BB26 (always), preds={BB23} succs={BB26} [000951] ------------ IL_OFFSET void IL offset: 0x117 N001 ( 1, 1) [000348] ------------ t348 = CNS_INT int 0 $40 /--* t348 int N003 ( 5, 4) [000350] DA---------- * STORE_LCL_VAR int V33 tmp3 d:4 ------------ BB25 [11A..11F), preds={BB23} succs={BB26} [000952] ------------ IL_OFFSET void IL offset: 0x11a N001 ( 3, 2) [000160] ------------ t160 = LCL_VAR int V18 loc15 u:2 (last use) $2a3 N002 ( 3, 2) [000161] ------------ t161 = LCL_VAR int V17 loc14 u:2 (last use) $29f /--* t160 int +--* t161 int N003 ( 7, 5) [000162] ------------ t162 = * SUB int $360 /--* t162 int N005 ( 11, 8) [000164] DA---------- * STORE_LCL_VAR int V33 tmp3 d:3 ------------ BB26 [11F..126) -> BB28 (cond), preds={BB24,BB25} succs={BB27,BB28} N001 ( 0, 0) [000903] ------------ t903 = PHI_ARG int V33 tmp3 u:4 $40 N002 ( 0, 0) [000902] ------------ t902 = PHI_ARG int V33 tmp3 u:3 $360 /--* t903 int +--* t902 int N003 ( 0, 0) [000876] ------------ t876 = * PHI int /--* t876 int N005 ( 0, 0) [000877] DA---------- * STORE_LCL_VAR int V33 tmp3 d:2 N001 ( 3, 2) [000166] ------------ t166 = LCL_VAR int V33 tmp3 u:2 $248 /--* t166 int N003 ( 3, 3) [000168] DA---------- * STORE_LCL_VAR int V19 loc16 d:2 [000953] ------------ IL_OFFSET void IL offset: 0x121 N001 ( 3, 2) [000169] ------------ t169 = LCL_VAR int V19 loc16 u:2 (last use) $248 N002 ( 1, 1) [000170] ------------ t170 = CNS_INT int 0 $40 /--* t169 int +--* t170 int N003 ( 5, 4) [000171] N------N---- t171 = * EQ int $361 /--* t171 int N004 ( 7, 6) [000172] ------------ * JTRUE void ------------ BB27 [126..12F), preds={BB26} succs={BB28} [000954] ------------ IL_OFFSET void IL offset: 0x126 N003 ( 3, 2) [000344] -------N---- t344 = LCL_VAR_ADDR byref V15 loc12 * ref V15._bits (offs=0x00) -> V56 tmp26 * int V15._sign (offs=0x08) -> V57 tmp27 N005 ( 1, 1) [000346] ------------ t346 = LCL_VAR int V19 loc16 u:2 $248 /--* t344 byref arg0 in rcx +--* t346 int arg1 in rdx N006 ( 18, 11) [000347] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft $VN.Void ------------ BB28 [12F..13E) -> BB32 (cond), preds={BB26,BB27} succs={BB29,BB32} [000955] ------------ IL_OFFSET void IL offset: 0x12f N001 ( 3, 2) [000173] ------------ t173 = LCL_VAR int V03 loc0 u:2 (last use) $348 N002 ( 1, 1) [000174] ------------ t174 = LCL_VAR int V13 loc10 u:2 $293 /--* t173 int +--* t174 int N003 ( 5, 4) [000175] ------------ t175 = * SUB int $362 /--* t175 int N005 ( 9, 7) [000177] DA---------- * STORE_LCL_VAR int V20 loc17 d:2 [000956] ------------ IL_OFFSET void IL offset: 0x135 N001 ( 3, 2) [000178] ------------ t178 = LCL_VAR int V20 loc17 u:2 $362 /--* t178 int N003 ( 7, 5) [000180] DA---------- * STORE_LCL_VAR int V21 loc18 d:2 [000957] ------------ IL_OFFSET void IL offset: 0x139 N001 ( 1, 1) [000181] ------------ t181 = LCL_VAR int V13 loc10 u:2 $293 N002 ( 1, 1) [000182] ------------ t182 = CNS_INT int 0 $40 /--* t181 int +--* t182 int N003 ( 3, 3) [000183] N------N---- t183 = * EQ int $363 /--* t183 int N004 ( 5, 5) [000184] ------------ * JTRUE void ------------ BB29 [13E..144) -> BB31 (cond), preds={BB28} succs={BB30,BB31} [000958] ------------ IL_OFFSET void IL offset: 0x13e N001 ( 1, 1) [000326] ------------ t326 = LCL_VAR int V19 loc16 u:2 $248 N002 ( 3, 2) [000327] ------------ t327 = LCL_VAR int V20 loc17 u:2 $362 /--* t326 int +--* t327 int N003 ( 5, 4) [000328] N------N-U-- t328 = * LE int $364 /--* t328 int N004 ( 7, 6) [000329] ------------ * JTRUE void ------------ BB30 [144..155) -> BB44 (always), preds={BB29} succs={BB44} [000959] ------------ IL_OFFSET void IL offset: 0x144 N005 ( 1, 1) [000341] ------------ t341 = LCL_VAR byref V02 arg2 u:1 (last use) $81 N006 ( 1, 1) [000339] ------------ t339 = CNS_INT int 1 $41 N007 ( 3, 2) [000335] ------------ t335 = LCL_VAR ref (AX) V12 loc9 $18c N008 ( 1, 1) [000336] ------------ t336 = LCL_VAR int V13 loc10 u:2 (last use) $293 N009 ( 1, 1) [000340] ------------ t340 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t341 byref arg4 out+20 +--* t339 int arg2 in r8 +--* t335 ref arg0 in rcx +--* t336 int arg1 in rdx +--* t340 ref arg3 in r9 N010 ( 24, 15) [000342] --CXG------- t342 = * CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits $5c2 /--* t342 int N012 ( 24, 15) [000717] DA-XG------- * STORE_LCL_VAR int V51 tmp21 d:5 ------------ BB31 [155..15C), preds={BB29} succs={BB32} [000960] ------------ IL_OFFSET void IL offset: 0x155 N001 ( 3, 2) [000330] ------------ t330 = LCL_VAR int V20 loc17 u:2 (last use) $362 N002 ( 1, 1) [000331] ------------ t331 = LCL_VAR int V19 loc16 u:2 $248 /--* t330 int +--* t331 int N003 ( 5, 4) [000332] ------------ t332 = * SUB int $365 /--* t332 int N005 ( 9, 7) [000334] DA---------- * STORE_LCL_VAR int V21 loc18 d:4 ------------ BB32 [15C..167) -> BB34 (cond), preds={BB28,BB31} succs={BB33,BB34} N001 ( 0, 0) [000900] ------------ t900 = PHI_ARG int V21 loc18 u:4 $365 N002 ( 0, 0) [000888] ------------ t888 = PHI_ARG int V21 loc18 u:2 $362 /--* t900 int +--* t888 int N003 ( 0, 0) [000873] ------------ t873 = * PHI int /--* t873 int N005 ( 0, 0) [000874] DA---------- * STORE_LCL_VAR int V21 loc18 d:3 [000961] ------------ IL_OFFSET void IL offset: 0x15c N001 ( 3, 2) [000719] -------N---- t719 = LCL_VAR ref (AX) V56 tmp26 $186 /--* t719 ref N003 ( 7, 5) [000720] DA--G------- * STORE_LCL_VAR ref (AX) V68 tmp38 N004 ( 3, 2) [000722] -------N---- t722 = LCL_VAR int (AX) V57 tmp27 $24a /--* t722 int N006 ( 7, 5) [000723] DA--G------- * STORE_LCL_VAR int (AX) V69 tmp39 [000962] ------------ IL_OFFSET void IL offset: 0x15c N001 ( 3, 2) [000726] -------N---- t726 = LCL_VAR ref (AX) V58 tmp28 $187 /--* t726 ref N003 ( 7, 5) [000727] DA--G------- * STORE_LCL_VAR ref V70 tmp40 d:2 N004 ( 3, 2) [000729] -------N---- t729 = LCL_VAR int (AX) V59 tmp29 $24b /--* t729 int N006 ( 7, 5) [000730] DA--G------- * STORE_LCL_VAR int V71 tmp41 d:2 N001 ( 3, 2) [000496] -------N---- t496 = LCL_VAR_ADDR byref V49 tmp19 * ref V49._bits (offs=0x00) -> V68 tmp38 * int V49._sign (offs=0x08) -> V69 tmp39 /--* t496 byref N004 ( 7, 6) [000752] DA--------L- * STORE_LCL_VAR byref V84 tmp54 d:2 N005 ( 3, 2) [000736] -------N---- t736 = LCL_VAR_ADDR byref V76 tmp46 /--* t736 byref N008 ( 3, 3) [000738] DA---------- * STORE_LCL_VAR byref V83 tmp53 d:2 N009 ( 1, 1) [000739] ------------ t739 = LCL_VAR byref V83 tmp53 u:2 Zero Fseq[_bits] $417 N011 ( 3, 2) [000741] -------N---- t741 = LCL_VAR ref V70 tmp40 u:2 (last use) $187 /--* t739 byref +--* t741 ref [000963] -A---------- * STOREIND ref N014 ( 1, 1) [000744] ------------ t744 = LCL_VAR byref V83 tmp53 u:2 (last use) $417 N015 ( 1, 1) [000745] ------------ t745 = CNS_INT long 8 Fseq[_sign] $101 /--* t744 byref +--* t745 long N016 ( 2, 2) [000746] -------N---- t746 = * ADD byref $216 N018 ( 3, 2) [000748] -------N---- t748 = LCL_VAR int V71 tmp41 u:2 (last use) $24b /--* t746 byref +--* t748 int [000964] -A--------L- * STOREIND int N021 ( 3, 2) [000753] ------------ t753 = LCL_VAR byref V84 tmp54 u:2 (last use) $415 N022 ( 3, 2) [000754] -------N---- t754 = LCL_VAR_ADDR byref V76 tmp46 /--* t753 byref this in rcx +--* t754 byref arg1 in rdx N024 ( 48, 34) [000499] --CXG------- t499 = * CALL int System.Numerics.BigInteger.CompareTo $2ae N025 ( 1, 1) [000502] ------------ t502 = CNS_INT int 0 $40 /--* t499 int +--* t502 int N026 ( 50, 36) [000503] J--XG--N---- t503 = * LT int $367 /--* t503 int N027 ( 52, 38) [000195] ---XG------- * JTRUE void ------------ BB33 [167..16B) -> BB35 (always), preds={BB32} succs={BB35} [000965] ------------ IL_OFFSET void IL offset: 0x167 N001 ( 1, 1) [000322] ------------ t322 = LCL_VAR int V19 loc16 u:2 (last use) $248 /--* t322 int N003 ( 5, 4) [000324] DA---------- * STORE_LCL_VAR int V34 tmp4 d:4 ------------ BB34 [16B..16F), preds={BB32} succs={BB35} [000966] ------------ IL_OFFSET void IL offset: 0x16b N001 ( 1, 1) [000196] ------------ t196 = LCL_VAR int V19 loc16 u:2 (last use) $248 N002 ( 1, 1) [000197] ------------ t197 = CNS_INT int 1 $41 /--* t196 int +--* t197 int N003 ( 3, 3) [000198] ------------ t198 = * ADD int $368 /--* t198 int N005 ( 7, 6) [000200] DA---------- * STORE_LCL_VAR int V34 tmp4 d:3 ------------ BB35 [16F..1A4) -> BB40 (cond), preds={BB33,BB34} succs={BB36,BB40} N001 ( 0, 0) [000899] ------------ t899 = PHI_ARG int V34 tmp4 u:4 $248 N002 ( 0, 0) [000898] ------------ t898 = PHI_ARG int V34 tmp4 u:3 $368 /--* t899 int +--* t898 int N003 ( 0, 0) [000870] ------------ t870 = * PHI int /--* t870 int N005 ( 0, 0) [000871] DA---------- * STORE_LCL_VAR int V34 tmp4 d:2 N001 ( 3, 2) [000202] ------------ t202 = LCL_VAR int V34 tmp4 u:2 (last use) $24c /--* t202 int N003 ( 7, 5) [000204] DA---------- * STORE_LCL_VAR int V22 loc19 d:2 [000967] ------------ IL_OFFSET void IL offset: 0x171 N003 ( 3, 2) [000205] -------N---- t205 = LCL_VAR_ADDR byref V15 loc12 * ref V15._bits (offs=0x00) -> V56 tmp26 * int V15._sign (offs=0x08) -> V57 tmp27 N005 ( 3, 2) [000207] ------------ t207 = LCL_VAR int V21 loc18 u:3 (last use) $249 /--* t205 byref arg0 in rcx +--* t207 int arg1 in rdx N006 ( 20, 12) [000208] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft $VN.Void [000968] ------------ IL_OFFSET void IL offset: 0x17a N001 ( 3, 2) [000219] -------N---- t219 = LCL_VAR_ADDR byref V35 tmp5 * ref V35._bits (offs=0x00) -> V62 tmp32 * int V35._sign (offs=0x08) -> V63 tmp33 /--* t219 byref N004 ( 7, 6) [000797] DA--------L- * STORE_LCL_VAR long V88 tmp58 d:2 N005 ( 3, 2) [000762] -------N---- t762 = LCL_VAR_ADDR byref V76 tmp46 /--* t762 byref N008 ( 3, 3) [000764] DA---------- * STORE_LCL_VAR byref V85 tmp55 d:2 N009 ( 1, 1) [000765] ------------ t765 = LCL_VAR byref V85 tmp55 u:2 Zero Fseq[_bits] $41c N011 ( 3, 2) [000767] -------N---- t767 = LCL_VAR ref (AX) V56 tmp26 $188 /--* t765 byref +--* t767 ref [000969] -A--G------- * STOREIND ref N014 ( 1, 1) [000770] ------------ t770 = LCL_VAR byref V85 tmp55 u:2 (last use) $41c N015 ( 1, 1) [000771] ------------ t771 = CNS_INT long 8 Fseq[_sign] $101 /--* t770 byref +--* t771 long N016 ( 2, 2) [000772] -------N---- t772 = * ADD byref $218 N018 ( 3, 2) [000774] -------N---- t774 = LCL_VAR int (AX) V57 tmp27 $24d /--* t772 byref +--* t774 int [000970] -A--G-----L- * STOREIND int N021 ( 3, 2) [000781] -------N---- t781 = LCL_VAR_ADDR byref V86 tmp56 /--* t781 byref N024 ( 3, 3) [000783] DA---------- * STORE_LCL_VAR byref V87 tmp57 d:2 N025 ( 1, 1) [000784] ------------ t784 = LCL_VAR byref V87 tmp57 u:2 Zero Fseq[_bits] $41e N027 ( 3, 2) [000786] -------N---- t786 = LCL_VAR ref (AX) V58 tmp28 $189 /--* t784 byref +--* t786 ref [000971] -A--G------- * STOREIND ref N030 ( 1, 1) [000789] ------------ t789 = LCL_VAR byref V87 tmp57 u:2 (last use) $41e N031 ( 1, 1) [000790] ------------ t790 = CNS_INT long 8 Fseq[_sign] $101 /--* t789 byref +--* t790 long N032 ( 2, 2) [000791] -------N---- t791 = * ADD byref $21a N034 ( 3, 2) [000793] -------N---- t793 = LCL_VAR int (AX) V59 tmp29 $24e /--* t791 byref +--* t793 int [000972] -A--G-----L- * STOREIND int N038 ( 3, 2) [000798] ------------ t798 = LCL_VAR long V88 tmp58 u:2 (last use) $41b N039 ( 3, 2) [000799] -------N---- t799 = LCL_VAR_ADDR byref V76 tmp46 N041 ( 3, 2) [000801] -------N---- t801 = LCL_VAR_ADDR byref V86 tmp56 N043 ( 3, 2) [000211] -------N---- t211 = LCL_VAR_ADDR byref V23 loc20 * ref V23._bits (offs=0x00) -> V60 tmp30 * int V23._sign (offs=0x08) -> V61 tmp31 /--* t798 long arg0 in rcx +--* t799 byref arg1 in rdx +--* t801 byref arg2 in r8 +--* t211 byref arg3 in r9 N045 ( 78, 56) [000213] S-CXG------- * CALL void System.Numerics.BigInteger.DivRem $VN.Void N001 ( 3, 2) [000808] -------N---- t808 = LCL_VAR_ADDR byref V76 tmp46 /--* t808 byref N004 ( 3, 3) [000810] DA---------- * STORE_LCL_VAR byref V89 tmp59 d:2 N005 ( 1, 1) [000811] ------------ t811 = LCL_VAR byref V89 tmp59 u:2 Zero Fseq[_bits] $423 N007 ( 3, 2) [000813] -------N---- t813 = LCL_VAR ref (AX) V62 tmp32 $18a /--* t811 byref +--* t813 ref [000973] -A--G------- * STOREIND ref N010 ( 1, 1) [000816] ------------ t816 = LCL_VAR byref V89 tmp59 u:2 (last use) $423 N011 ( 1, 1) [000817] ------------ t817 = CNS_INT long 8 Fseq[_sign] $101 /--* t816 byref +--* t817 long N012 ( 2, 2) [000818] -------N---- t818 = * ADD byref $21d N014 ( 3, 2) [000820] -------N---- t820 = LCL_VAR int (AX) V63 tmp33 $24f /--* t818 byref +--* t820 int [000974] -A--G-----L- * STOREIND int N017 ( 3, 2) [000823] -------N---- t823 = LCL_VAR_ADDR byref V76 tmp46 /--* t823 byref arg0 in rcx N019 ( 38, 24) [000218] --CXG------- t218 = * CALL long System.Numerics.BigInteger.op_Explicit $450 /--* t218 long N021 ( 38, 24) [000226] DA-XG------- * STORE_LCL_VAR long V24 loc21 d:2 N001 ( 3, 2) [000514] ------------ t514 = LCL_VAR int (AX) V61 tmp31 $250 N002 ( 1, 1) [000515] ------------ t515 = CNS_INT int 0 $40 /--* t514 int +--* t515 int N003 ( 8, 4) [000516] ----G------- t516 = * EQ int $369 /--* t516 int N005 ( 12, 7) [000232] DA--G------- * STORE_LCL_VAR int V25 loc22 d:2 N002 ( 1, 1) [000233] ------------ t233 = LCL_VAR long V24 loc21 u:2 $450 /--* t233 long arg0 in rcx N003 ( 15, 7) [000234] --CXG------- t234 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $2b4 /--* t234 int N005 ( 19, 10) [000237] DA-XG------- * STORE_LCL_VAR int V26 loc23 d:2 [000975] ------------ IL_OFFSET void IL offset: 0x19e N001 ( 3, 2) [000238] ------------ t238 = LCL_VAR int V26 loc23 u:2 $2b4 N002 ( 3, 2) [000239] ------------ t239 = LCL_VAR int V20 loc17 u:2 $362 /--* t238 int +--* t239 int N003 ( 7, 5) [000240] N------N-U-- t240 = * LE int $36a /--* t240 int N004 ( 9, 7) [000241] ------------ * JTRUE void ------------ BB36 [1A4..1AF) -> BB38 (cond), preds={BB35} succs={BB37,BB38} [000976] ------------ IL_OFFSET void IL offset: 0x1a4 N001 ( 3, 2) [000282] ------------ t282 = LCL_VAR int V26 loc23 u:2 (last use) $2b4 N002 ( 3, 2) [000283] ------------ t283 = LCL_VAR int V20 loc17 u:2 $362 /--* t282 int +--* t283 int N003 ( 7, 5) [000284] ------------ t284 = * SUB int $36b /--* t284 int N005 ( 11, 8) [000286] DA---------- * STORE_LCL_VAR int V29 loc26 d:2 [000977] ------------ IL_OFFSET void IL offset: 0x1ab N001 ( 3, 2) [000287] ------------ t287 = LCL_VAR int V25 loc22 u:2 (last use) $369 N002 ( 1, 1) [000288] ------------ t288 = CNS_INT int 0 $40 /--* t287 int +--* t288 int N003 ( 5, 4) [000289] J------N---- t289 = * EQ int $36c /--* t289 int N004 ( 7, 6) [000290] ------------ * JTRUE void ------------ BB37 [1AF..1C3) -> BB39 (always), preds={BB36} succs={BB39} [000978] ------------ IL_OFFSET void IL offset: 0x1af N001 ( 1, 1) [000305] ------------ t305 = LCL_VAR long V24 loc21 u:2 $450 N002 ( 3, 2) [000308] ------------ t308 = LCL_VAR int V29 loc26 u:2 $36b N003 ( 1, 1) [000309] ------------ t309 = CNS_INT int 63 $66 /--* t308 int +--* t309 int N004 ( 5, 4) [000310] ------------ t310 = * AND int $36d N005 ( 1, 1) [000307] ------------ t307 = CNS_INT long 1 $103 /--* t307 long +--* t310 int N006 ( 10, 6) [000311] ------------ t311 = * LSH long $48e N007 ( 1, 1) [000313] ------------ t313 = CNS_INT long -1 $104 /--* t311 long +--* t313 long N008 ( 12, 8) [000314] ------------ t314 = * ADD long $48f /--* t305 long +--* t314 long N009 ( 14, 10) [000315] ------------ t315 = * AND long $490 N010 ( 1, 1) [000317] ------------ t317 = CNS_INT long 0 $100 /--* t315 long +--* t317 long N011 ( 19, 12) [000318] ------------ t318 = * EQ int $36e /--* t318 int N013 ( 23, 15) [000320] DA---------- * STORE_LCL_VAR int V37 tmp7 d:4 ------------ BB38 [1C3..1C4), preds={BB36} succs={BB39} [000979] ------------ IL_OFFSET void IL offset: 0x1c3 N001 ( 1, 1) [000291] ------------ t291 = CNS_INT int 0 $40 /--* t291 int N003 ( 5, 4) [000293] DA---------- * STORE_LCL_VAR int V37 tmp7 d:3 ------------ BB39 [1C4..1D0), preds={BB37,BB38} succs={BB40} N001 ( 0, 0) [000897] ------------ t897 = PHI_ARG int V37 tmp7 u:4 $36e N002 ( 0, 0) [000896] ------------ t896 = PHI_ARG int V37 tmp7 u:3 $40 /--* t897 int +--* t896 int N003 ( 0, 0) [000867] ------------ t867 = * PHI int /--* t867 int N005 ( 0, 0) [000868] DA---------- * STORE_LCL_VAR int V37 tmp7 d:2 N001 ( 3, 2) [000295] ------------ t295 = LCL_VAR int V37 tmp7 u:2 (last use) $251 /--* t295 int N002 ( 4, 4) [000826] ------------ t826 = * CAST int <- bool <- int $36f /--* t826 int N004 ( 8, 7) [000297] DA---------- * STORE_LCL_VAR int V25 loc22 d:4 [000980] ------------ IL_OFFSET void IL offset: 0x1c6 N001 ( 1, 1) [000298] ------------ t298 = LCL_VAR long V24 loc21 u:2 (last use) $450 N002 ( 3, 2) [000299] ------------ t299 = LCL_VAR int V29 loc26 u:2 (last use) $36b N003 ( 1, 1) [000300] ------------ t300 = CNS_INT int 63 $66 /--* t299 int +--* t300 int N004 ( 5, 4) [000301] ------------ t301 = * AND int $36d /--* t298 long +--* t301 int N005 ( 10, 6) [000302] ------------ t302 = * RSZ long $491 /--* t302 long N007 ( 10, 6) [000304] DA---------- * STORE_LCL_VAR long V24 loc21 d:4 ------------ BB40 [1D0..1E7) -> BB42 (cond), preds={BB35,BB39} succs={BB41,BB42} N001 ( 0, 0) [000894] ------------ t894 = PHI_ARG bool V25 loc22 u:4 $36f N002 ( 0, 0) [000889] ------------ t889 = PHI_ARG bool V25 loc22 u:2 $369 /--* t894 bool +--* t889 bool N003 ( 0, 0) [000864] ------------ t864 = * PHI bool /--* t864 bool N005 ( 0, 0) [000865] DA---------- * STORE_LCL_VAR bool V25 loc22 d:3 N001 ( 0, 0) [000895] ------------ t895 = PHI_ARG long V24 loc21 u:4 $491 N002 ( 0, 0) [000890] ------------ t890 = PHI_ARG long V24 loc21 u:2 $450 /--* t895 long +--* t890 long N003 ( 0, 0) [000861] ------------ t861 = * PHI long /--* t861 long N005 ( 0, 0) [000862] DA---------- * STORE_LCL_VAR long V24 loc21 d:3 N001 ( 3, 2) [000831] -------N---- t831 = LCL_VAR_ADDR byref V76 tmp46 /--* t831 byref N004 ( 3, 3) [000833] DA---------- * STORE_LCL_VAR byref V90 tmp60 d:2 N005 ( 1, 1) [000834] ------------ t834 = LCL_VAR byref V90 tmp60 u:2 Zero Fseq[_bits] $426 N007 ( 3, 2) [000836] -------N---- t836 = LCL_VAR ref (AX) V54 tmp24 $18b /--* t834 byref +--* t836 ref [000981] -A--G------- * STOREIND ref N010 ( 1, 1) [000839] ------------ t839 = LCL_VAR byref V90 tmp60 u:2 (last use) $426 N011 ( 1, 1) [000840] ------------ t840 = CNS_INT long 8 Fseq[_sign] $101 /--* t839 byref +--* t840 long N012 ( 2, 2) [000841] -------N---- t841 = * ADD byref $220 N014 ( 3, 2) [000843] -------N---- t843 = LCL_VAR int (AX) V55 tmp25 $252 /--* t841 byref +--* t843 int [000982] -A--G-----L- * STOREIND int N017 ( 3, 2) [000846] -------N---- t846 = LCL_VAR_ADDR byref V76 tmp46 /--* t846 byref arg0 in rcx N019 ( 38, 24) [000243] --CXG------- t243 = * CALL long System.Numerics.BigInteger.op_Explicit $454 N020 ( 3, 2) [000247] ------------ t247 = LCL_VAR int V20 loc17 u:2 (last use) $362 N021 ( 1, 1) [000248] ------------ t248 = CNS_INT int 63 $66 /--* t247 int +--* t248 int N022 ( 5, 4) [000249] ------------ t249 = * AND int $370 /--* t243 long +--* t249 int N023 ( 47, 29) [000250] ---XG------- t250 = * LSH long $492 N024 ( 1, 1) [000251] ------------ t251 = LCL_VAR long V24 loc21 u:3 (last use) $580 /--* t250 long +--* t251 long N025 ( 49, 31) [000252] ---XG------- t252 = * ADD long $493 /--* t252 long N027 ( 53, 34) [000254] DA-XG------- * STORE_LCL_VAR long V27 loc24 d:2 [000983] ------------ IL_OFFSET void IL offset: 0x1e2 N001 ( 1, 1) [000255] ------------ t255 = LCL_VAR int V13 loc10 u:2 $293 N002 ( 1, 1) [000256] ------------ t256 = CNS_INT int 0 $40 /--* t255 int +--* t256 int N003 ( 3, 3) [000257] N------N---- t257 = * NE int $35a /--* t257 int N004 ( 5, 5) [000258] ------------ * JTRUE void ------------ BB41 [1E7..1EE) -> BB43 (always), preds={BB40} succs={BB43} [000984] ------------ IL_OFFSET void IL offset: 0x1e7 N001 ( 3, 2) [000275] ------------ t275 = LCL_VAR int V22 loc19 u:2 (last use) $24c /--* t275 int N002 ( 4, 3) [000276] ------------ t276 = * NEG int $2c2 N003 ( 1, 1) [000277] ------------ t277 = CNS_INT int -1 $43 /--* t276 int +--* t277 int N004 ( 6, 5) [000278] ------------ t278 = * ADD int $372 /--* t278 int N006 ( 10, 8) [000280] DA---------- * STORE_LCL_VAR int V36 tmp6 d:4 ------------ BB42 [1EE..1F2), preds={BB40} succs={BB43} [000985] ------------ IL_OFFSET void IL offset: 0x1ee N001 ( 1, 1) [000259] ------------ t259 = LCL_VAR int V13 loc10 u:2 (last use) $293 N002 ( 1, 1) [000260] ------------ t260 = CNS_INT int -2 $68 /--* t259 int +--* t260 int N003 ( 3, 3) [000261] ------------ t261 = * ADD int $371 /--* t261 int N005 ( 7, 6) [000263] DA---------- * STORE_LCL_VAR int V36 tmp6 d:3 ------------ BB43 [1F2..202), preds={BB41,BB42} succs={BB44} N001 ( 0, 0) [000893] ------------ t893 = PHI_ARG int V36 tmp6 u:4 $372 N002 ( 0, 0) [000892] ------------ t892 = PHI_ARG int V36 tmp6 u:3 $371 /--* t893 int +--* t892 int N003 ( 0, 0) [000858] ------------ t858 = * PHI int /--* t858 int N005 ( 0, 0) [000859] DA---------- * STORE_LCL_VAR int V36 tmp6 d:2 [000986] ------------ IL_OFFSET void IL offset: 0x1f4 N005 ( 1, 1) [000272] ------------ t272 = LCL_VAR byref V02 arg2 u:1 (last use) $81 N006 ( 1, 1) [000268] ------------ t268 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 N007 ( 3, 2) [000269] ------------ t269 = LCL_VAR long V27 loc24 u:2 (last use) $493 N008 ( 3, 2) [000270] ------------ t270 = LCL_VAR int V36 tmp6 u:2 (last use) $253 N009 ( 3, 2) [000271] ------------ t271 = LCL_VAR int V25 loc22 u:3 (last use) $540 /--* t272 byref arg4 out+20 +--* t268 ref this in rcx +--* t269 long arg1 in rdx +--* t270 int arg2 in r8 +--* t271 int arg3 in r9 N010 ( 28, 18) [000273] --CXG------- t273 = * CALL int FloatingPointType.AssembleFloatingPointValue $2be /--* t273 int N012 ( 28, 18) [000853] DA-XG------- * STORE_LCL_VAR int V51 tmp21 d:4 ------------ BB44 [???..???) (return), preds={BB16,BB30,BB43} succs={} N001 ( 0, 0) [000901] ------------ t901 = PHI_ARG int V51 tmp21 u:5 $5c2 N002 ( 0, 0) [000891] ------------ t891 = PHI_ARG int V51 tmp21 u:4 $2be N003 ( 0, 0) [000887] ------------ t887 = PHI_ARG int V51 tmp21 u:3 $5c7 /--* t901 int +--* t891 int +--* t887 int N004 ( 0, 0) [000855] ------------ t855 = * PHI int /--* t855 int N006 ( 0, 0) [000856] DA---------- * STORE_LCL_VAR int V51 tmp21 d:2 N001 ( 1, 1) [000522] -------N---- t522 = LCL_VAR int V51 tmp21 u:2 (last use) $254 /--* t522 int N002 ( 2, 2) [000523] ------------ * RETURN int $5c9 ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Lowering nodeinfo lowering store lcl var/field (before): N001 ( 1, 1) [000531] ------------ t531 = LCL_VAR byref V00 arg0 u:1 Zero Fseq[Mantissa] $80 /--* t531 byref N002 ( 3, 2) [000532] n----------- t532 = * IND ref /--* t532 ref N004 ( 3, 3) [000533] DA---------- * STORE_LCL_VAR ref V52 tmp22 d:2 lowering store lcl var/field (after): N001 ( 1, 1) [000531] ------------ t531 = LCL_VAR byref V00 arg0 u:1 Zero Fseq[Mantissa] $80 /--* t531 byref N002 ( 3, 2) [000532] n----------- t532 = * IND ref /--* t532 ref N004 ( 3, 3) [000533] DA---------- * STORE_LCL_VAR ref V52 tmp22 d:2 Addressing mode: Base N005 ( 1, 1) [000535] ------------ * LCL_VAR byref V00 arg0 u:1 (last use) $80 + 8 Removing unused node: N006 ( 1, 1) [000536] -c---------- * CNS_INT long 8 Fseq[Exponent] $101 New addressing mode node: N007 ( 2, 2) [000537] ------------ * LEA(b+8) byref lowering store lcl var/field (before): N005 ( 1, 1) [000535] ------------ t535 = LCL_VAR byref V00 arg0 u:1 (last use) $80 /--* t535 byref N007 ( 2, 2) [000537] -c---------- t537 = * LEA(b+8) byref /--* t537 byref N008 ( 4, 4) [000538] n----------- t538 = * IND int /--* t538 int N010 ( 4, 4) [000539] DA---------- * STORE_LCL_VAR int V53 tmp23 d:2 lowering store lcl var/field (after): N005 ( 1, 1) [000535] ------------ t535 = LCL_VAR byref V00 arg0 u:1 (last use) $80 /--* t535 byref N007 ( 2, 2) [000537] -c---------- t537 = * LEA(b+8) byref /--* t537 byref N008 ( 4, 4) [000538] n----------- t538 = * IND int /--* t538 int N010 ( 4, 4) [000539] DA---------- * STORE_LCL_VAR int V53 tmp23 d:2 Addressing mode: Base N001 ( 1, 1) [000002] ------------ * LCL_VAR ref V52 tmp22 u:2 + 8 Removing unused node: [000987] -c---------- * CNS_INT long 8 New addressing mode node: [000988] ------------ * LEA(b+8) ref lowering call (before): N002 ( 1, 1) [000400] ------------ t400 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t400 ref this in rcx N003 ( 21, 10) [000401] --CXG------- t401 = * CALLV ind long FloatingPointType.get_Zero $459 objp: ====== lowering arg : N001 ( 0, 0) [000541] ----------L- * ARGPLACE ref $1fd args: ====== late: ====== lowering arg : N002 ( 1, 1) [000400] ------------ * LCL_VAR ref V01 arg1 u:1 (last use) $c0 new node is : [000995] ------------ * PUTARG_REG ref REG rcx results of lowering call: N001 ( 1, 1) [000996] ------------ t996 = LCL_VAR ref V01 arg1 /--* t996 ref N002 ( 2, 2) [000997] ------------ t997 = * LEA(b+0) byref /--* t997 byref N003 ( 5, 4) [000998] ------------ t998 = * IND long /--* t998 long N004 ( 6, 5) [000999] ------------ t999 = * LEA(b+80) long /--* t999 long N005 ( 9, 7) [001000] ------------ t1000 = * IND long /--* t1000 long N006 ( 10, 8) [001001] ------------ t1001 = * LEA(b+0) long /--* t1001 long N007 ( 13, 10) [001002] ------------ t1002 = * IND long lowering call (after): N002 ( 1, 1) [000400] ------------ t400 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t400 ref [000995] ------------ t995 = * PUTARG_REG ref REG rcx N001 ( 1, 1) [000996] ------------ t996 = LCL_VAR ref V01 arg1 /--* t996 ref N002 ( 2, 2) [000997] -c---------- t997 = * LEA(b+0) byref /--* t997 byref N003 ( 5, 4) [000998] ------------ t998 = * IND long /--* t998 long N004 ( 6, 5) [000999] -c---------- t999 = * LEA(b+80) long /--* t999 long N005 ( 9, 7) [001000] ------------ t1000 = * IND long /--* t1000 long N006 ( 10, 8) [001001] -c---------- t1001 = * LEA(b+0) long /--* t1001 long N007 ( 13, 10) [001002] -c---------- t1002 = * IND long REG NA /--* t995 ref this in rcx +--* t1002 long control expr N003 ( 21, 10) [000401] --CXG------- t401 = * CALLV ind long FloatingPointType.get_Zero $459 Lower of StoreInd didn't mark the node as self contained for reason: 4 N002 ( 1, 1) [000400] ------------ t400 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t400 ref [000995] ------------ t995 = * PUTARG_REG ref REG rcx N001 ( 1, 1) [000996] ------------ t996 = LCL_VAR ref V01 arg1 /--* t996 ref N002 ( 2, 2) [000997] -c---------- t997 = * LEA(b+0) byref /--* t997 byref N003 ( 5, 4) [000998] ------------ t998 = * IND long /--* t998 long N004 ( 6, 5) [000999] -c---------- t999 = * LEA(b+80) long /--* t999 long N005 ( 9, 7) [001000] ------------ t1000 = * IND long /--* t1000 long N006 ( 10, 8) [001001] -c---------- t1001 = * LEA(b+0) long /--* t1001 long N007 ( 13, 10) [001002] -c---------- t1002 = * IND long REG NA /--* t995 ref this in rcx +--* t1002 long control expr N003 ( 21, 10) [000401] --CXG------- t401 = * CALLV ind long FloatingPointType.get_Zero $459 N004 ( 1, 1) [000399] ------------ t399 = LCL_VAR byref V02 arg2 u:1 (last use) $81 /--* t399 byref +--* t401 long [000912] -ACXG------- * STOREIND long lowering GT_RETURN N002 ( 2, 2) [000520] ------------ * RETURN int $5cb ============lowering call (before): N002 ( 1, 1) [000007] ------------ t7 = LCL_VAR ref V01 arg1 u:1 $c0 /--* t7 ref this in rcx N003 ( 21, 10) [000406] --CXG------- t406 = * CALLV ind int FloatingPointType.get_DenormalMantissaBits $282 objp: ====== lowering arg : N001 ( 0, 0) [000542] ----------L- * ARGPLACE ref $1c2 args: ====== late: ====== lowering arg : N002 ( 1, 1) [000007] ------------ * LCL_VAR ref V01 arg1 u:1 $c0 new node is : [001003] ------------ * PUTARG_REG ref REG rcx results of lowering call: N001 ( 1, 1) [001004] ------------ t1004 = LCL_VAR ref V01 arg1 /--* t1004 ref N002 ( 2, 2) [001005] ------------ t1005 = * LEA(b+0) byref /--* t1005 byref N003 ( 5, 4) [001006] ------------ t1006 = * IND long /--* t1006 long N004 ( 6, 5) [001007] ------------ t1007 = * LEA(b+72) long /--* t1007 long N005 ( 9, 7) [001008] ------------ t1008 = * IND long /--* t1008 long N006 ( 10, 8) [001009] ------------ t1009 = * LEA(b+32) long /--* t1009 long N007 ( 13, 10) [001010] ------------ t1010 = * IND long lowering call (after): N002 ( 1, 1) [000007] ------------ t7 = LCL_VAR ref V01 arg1 u:1 $c0 /--* t7 ref [001003] ------------ t1003 = * PUTARG_REG ref REG rcx N001 ( 1, 1) [001004] ------------ t1004 = LCL_VAR ref V01 arg1 /--* t1004 ref N002 ( 2, 2) [001005] -c---------- t1005 = * LEA(b+0) byref /--* t1005 byref N003 ( 5, 4) [001006] ------------ t1006 = * IND long /--* t1006 long N004 ( 6, 5) [001007] -c---------- t1007 = * LEA(b+72) long /--* t1007 long N005 ( 9, 7) [001008] ------------ t1008 = * IND long /--* t1008 long N006 ( 10, 8) [001009] -c---------- t1009 = * LEA(b+32) long /--* t1009 long N007 ( 13, 10) [001010] -c---------- t1010 = * IND long REG NA /--* t1003 ref this in rcx +--* t1010 long control expr N003 ( 21, 10) [000406] --CXG------- t406 = * CALLV ind int FloatingPointType.get_DenormalMantissaBits $282 lowering store lcl var/field (before): N002 ( 1, 1) [000007] ------------ t7 = LCL_VAR ref V01 arg1 u:1 $c0 /--* t7 ref [001003] ------------ t1003 = * PUTARG_REG ref REG rcx N001 ( 1, 1) [001004] ------------ t1004 = LCL_VAR ref V01 arg1 /--* t1004 ref N002 ( 2, 2) [001005] -c---------- t1005 = * LEA(b+0) byref /--* t1005 byref N003 ( 5, 4) [001006] ------------ t1006 = * IND long /--* t1006 long N004 ( 6, 5) [001007] -c---------- t1007 = * LEA(b+72) long /--* t1007 long N005 ( 9, 7) [001008] ------------ t1008 = * IND long /--* t1008 long N006 ( 10, 8) [001009] -c---------- t1009 = * LEA(b+32) long /--* t1009 long N007 ( 13, 10) [001010] -c---------- t1010 = * IND long REG NA /--* t1003 ref this in rcx +--* t1010 long control expr N003 ( 21, 10) [000406] --CXG------- t406 = * CALLV ind int FloatingPointType.get_DenormalMantissaBits $282 N004 ( 1, 1) [000407] -c---------- t407 = CNS_INT int 1 $41 /--* t406 int +--* t407 int N005 ( 23, 12) [000408] ---XG------- t408 = * ADD int $346 /--* t408 int N006 ( 24, 14) [000409] ---XG------- t409 = * CAST int <- ushort <- int $347 N007 ( 1, 1) [000010] -c---------- t10 = CNS_INT int 1 $41 /--* t409 int +--* t10 int N008 ( 26, 16) [000011] ---XG------- t11 = * ADD int $348 /--* t11 int N010 ( 30, 19) [000013] DA-XG------- * STORE_LCL_VAR int V03 loc0 d:2 lowering store lcl var/field (after): N002 ( 1, 1) [000007] ------------ t7 = LCL_VAR ref V01 arg1 u:1 $c0 /--* t7 ref [001003] ------------ t1003 = * PUTARG_REG ref REG rcx N001 ( 1, 1) [001004] ------------ t1004 = LCL_VAR ref V01 arg1 /--* t1004 ref N002 ( 2, 2) [001005] -c---------- t1005 = * LEA(b+0) byref /--* t1005 byref N003 ( 5, 4) [001006] ------------ t1006 = * IND long /--* t1006 long N004 ( 6, 5) [001007] -c---------- t1007 = * LEA(b+72) long /--* t1007 long N005 ( 9, 7) [001008] ------------ t1008 = * IND long /--* t1008 long N006 ( 10, 8) [001009] -c---------- t1009 = * LEA(b+32) long /--* t1009 long N007 ( 13, 10) [001010] -c---------- t1010 = * IND long REG NA /--* t1003 ref this in rcx +--* t1010 long control expr N003 ( 21, 10) [000406] --CXG------- t406 = * CALLV ind int FloatingPointType.get_DenormalMantissaBits $282 N004 ( 1, 1) [000407] -c---------- t407 = CNS_INT int 1 $41 /--* t406 int +--* t407 int N005 ( 23, 12) [000408] ---XG------- t408 = * ADD int $346 /--* t408 int N006 ( 24, 14) [000409] ---XG------- t409 = * CAST int <- ushort <- int $347 N007 ( 1, 1) [000010] -c---------- t10 = CNS_INT int 1 $41 /--* t409 int +--* t10 int N008 ( 26, 16) [000011] ---XG------- t11 = * ADD int $348 /--* t11 int N010 ( 30, 19) [000013] DA-XG------- * STORE_LCL_VAR int V03 loc0 d:2 lowering store lcl var/field (before): N001 ( 1, 1) [000017] ------------ t17 = LCL_VAR int V53 tmp23 u:2 /--* t17 int N003 ( 5, 4) [000424] DA--G------- * STORE_LCL_VAR int V40 tmp10 d:2 lowering store lcl var/field (after): N001 ( 1, 1) [000017] ------------ t17 = LCL_VAR int V53 tmp23 u:2 /--* t17 int N003 ( 5, 4) [000424] DA--G------- * STORE_LCL_VAR int V40 tmp10 d:2 lowering store lcl var/field (before): N001 ( 3, 2) [000419] ------------ t419 = LCL_VAR int V53 tmp23 u:2 (last use) /--* t419 int N003 ( 7, 5) [000421] DA---------- * STORE_LCL_VAR int V39 tmp9 d:4 lowering store lcl var/field (after): N001 ( 3, 2) [000419] ------------ t419 = LCL_VAR int V53 tmp23 u:2 (last use) /--* t419 int N003 ( 7, 5) [000421] DA---------- * STORE_LCL_VAR int V39 tmp9 d:4 lowering store lcl var/field (before): N001 ( 1, 1) [000415] ------------ t415 = CNS_INT int 0 $40 /--* t415 int N003 ( 5, 4) [000417] DA---------- * STORE_LCL_VAR int V39 tmp9 d:3 lowering store lcl var/field (after): N001 ( 1, 1) [000415] ------------ t415 = CNS_INT int 0 $40 /--* t415 int N003 ( 5, 4) [000417] DA---------- * STORE_LCL_VAR int V39 tmp9 d:3 lowering store lcl var/field (before): N001 ( 0, 0) [000909] ------------ t909 = PHI_ARG int V39 tmp9 u:4 N002 ( 0, 0) [000908] ------------ t908 = PHI_ARG int V39 tmp9 u:3 $40 /--* t909 int +--* t908 int N003 ( 0, 0) [000885] ------------ t885 = * PHI int /--* t885 int N005 ( 0, 0) [000886] DA---------- * STORE_LCL_VAR int V39 tmp9 d:2 lowering store lcl var/field (after): N001 ( 0, 0) [000909] ------------ t909 = PHI_ARG int V39 tmp9 u:4 N002 ( 0, 0) [000908] ------------ t908 = PHI_ARG int V39 tmp9 u:3 $40 /--* t909 int +--* t908 int N003 ( 0, 0) [000885] ------------ t885 = * PHI int /--* t885 int N005 ( 0, 0) [000886] DA---------- * STORE_LCL_VAR int V39 tmp9 d:2 lowering store lcl var/field (before): N001 ( 3, 2) [000422] ------------ t422 = LCL_VAR int V39 tmp9 u:2 $241 /--* t422 int N003 ( 3, 3) [000021] DA---------- * STORE_LCL_VAR int V31 tmp1 d:2 lowering store lcl var/field (after): N001 ( 3, 2) [000422] ------------ t422 = LCL_VAR int V39 tmp9 u:2 $241 /--* t422 int N003 ( 3, 3) [000021] DA---------- * STORE_LCL_VAR int V31 tmp1 d:2 Addressing mode: Base N001 ( 1, 1) [000428] ------------ * LCL_VAR ref V52 tmp22 u:2 + 8 Removing unused node: [000989] -c---------- * CNS_INT long 8 New addressing mode node: [000990] ------------ * LEA(b+8) ref lowering store lcl var/field (before): N001 ( 1, 1) [000428] ------------ t428 = LCL_VAR ref V52 tmp22 u:2 /--* t428 ref [000990] -c---------- t990 = * LEA(b+8) ref /--* t990 ref N002 ( 3, 3) [000429] ---XG------- t429 = * IND int /--* t429 int N004 ( 3, 3) [000443] DA-XG------- * STORE_LCL_VAR int V42 tmp12 d:2 lowering store lcl var/field (after): N001 ( 1, 1) [000428] ------------ t428 = LCL_VAR ref V52 tmp22 u:2 /--* t428 ref [000990] -c---------- t990 = * LEA(b+8) ref /--* t990 ref N002 ( 3, 3) [000429] ---XG------- t429 = * IND int /--* t429 int N004 ( 3, 3) [000443] DA-XG------- * STORE_LCL_VAR int V42 tmp12 d:2 lowering store lcl var/field (before): N001 ( 1, 1) [000438] ------------ t438 = LCL_VAR int V42 tmp12 u:2 (last use) /--* t438 int N003 ( 1, 3) [000440] DA---------- * STORE_LCL_VAR int V41 tmp11 d:4 lowering store lcl var/field (after): N001 ( 1, 1) [000438] ------------ t438 = LCL_VAR int V42 tmp12 u:2 (last use) /--* t438 int N003 ( 1, 3) [000440] DA---------- * STORE_LCL_VAR int V41 tmp11 d:4 lowering store lcl var/field (before): N001 ( 1, 1) [000434] ------------ t434 = LCL_VAR int V31 tmp1 u:2 $241 /--* t434 int N003 ( 1, 3) [000436] DA---------- * STORE_LCL_VAR int V41 tmp11 d:3 lowering store lcl var/field (after): N001 ( 1, 1) [000434] ------------ t434 = LCL_VAR int V31 tmp1 u:2 $241 /--* t434 int N003 ( 1, 3) [000436] DA---------- * STORE_LCL_VAR int V41 tmp11 d:3 lowering store lcl var/field (before): N001 ( 0, 0) [000907] ------------ t907 = PHI_ARG int V41 tmp11 u:4 N002 ( 0, 0) [000906] ------------ t906 = PHI_ARG int V41 tmp11 u:3 $241 /--* t907 int +--* t906 int N003 ( 0, 0) [000882] ------------ t882 = * PHI int /--* t882 int N005 ( 0, 0) [000883] DA---------- * STORE_LCL_VAR int V41 tmp11 d:2 lowering store lcl var/field (after): N001 ( 0, 0) [000907] ------------ t907 = PHI_ARG int V41 tmp11 u:4 N002 ( 0, 0) [000906] ------------ t906 = PHI_ARG int V41 tmp11 u:3 $241 /--* t907 int +--* t906 int N003 ( 0, 0) [000882] ------------ t882 = * PHI int /--* t882 int N005 ( 0, 0) [000883] DA---------- * STORE_LCL_VAR int V41 tmp11 d:2 lowering store lcl var/field (before): N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR int V31 tmp1 u:2 (last use) $241 N002 ( 1, 1) [000032] ------------ t32 = LCL_VAR int V41 tmp11 u:2 $242 /--* t22 int +--* t32 int N003 ( 3, 3) [000033] ------------ t33 = * SUB int $34e /--* t33 int N005 ( 7, 6) [000035] DA---------- * STORE_LCL_VAR int V05 loc2 d:2 lowering store lcl var/field (after): N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR int V31 tmp1 u:2 (last use) $241 N002 ( 1, 1) [000032] ------------ t32 = LCL_VAR int V41 tmp11 u:2 $242 /--* t22 int +--* t32 int N003 ( 3, 3) [000033] ------------ t33 = * SUB int $34e /--* t33 int N005 ( 7, 6) [000035] DA---------- * STORE_LCL_VAR int V05 loc2 d:2 lowering store lcl var/field (before): N001 ( 1, 1) [000042] ------------ t42 = LCL_VAR int V41 tmp11 u:2 $242 /--* t42 int N003 ( 5, 4) [000044] DA---------- * STORE_LCL_VAR int V08 loc5 d:2 lowering store lcl var/field (after): N001 ( 1, 1) [000042] ------------ t42 = LCL_VAR int V41 tmp11 u:2 $242 /--* t42 int N003 ( 5, 4) [000044] DA---------- * STORE_LCL_VAR int V08 loc5 d:2 Addressing mode: Base N001 ( 1, 1) [000447] ------------ * LCL_VAR ref V52 tmp22 u:2 + 8 Removing unused node: [000991] -c---------- * CNS_INT long 8 New addressing mode node: [000992] ------------ * LEA(b+8) ref lowering store lcl var/field (before): N001 ( 1, 1) [000447] ------------ t447 = LCL_VAR ref V52 tmp22 u:2 /--* t447 ref [000992] -c---------- t992 = * LEA(b+8) ref /--* t992 ref N002 ( 3, 3) [000448] ---XG------- t448 = * IND int /--* t448 int N004 ( 7, 6) [000050] DA-XG------- * STORE_LCL_VAR int V09 loc6 d:2 lowering store lcl var/field (after): N001 ( 1, 1) [000447] ------------ t447 = LCL_VAR ref V52 tmp22 u:2 /--* t447 ref [000992] -c---------- t992 = * LEA(b+8) ref /--* t992 ref N002 ( 3, 3) [000448] ---XG------- t448 = * IND int /--* t448 int N004 ( 7, 6) [000050] DA-XG------- * STORE_LCL_VAR int V09 loc6 d:2 lowering store lcl var/field (before): N001 ( 3, 2) [000051] ------------ t51 = LCL_VAR int V09 loc6 u:2 N002 ( 1, 1) [000052] ------------ t52 = LCL_VAR int V08 loc5 u:2 $242 /--* t51 int +--* t52 int N003 ( 5, 4) [000053] ------------ t53 = * SUB int /--* t53 int N005 ( 5, 4) [000055] DA---------- * STORE_LCL_VAR int V10 loc7 d:2 lowering store lcl var/field (after): N001 ( 3, 2) [000051] ------------ t51 = LCL_VAR int V09 loc6 u:2 N002 ( 1, 1) [000052] ------------ t52 = LCL_VAR int V08 loc5 u:2 $242 /--* t51 int +--* t52 int N003 ( 5, 4) [000053] ------------ t53 = * SUB int /--* t53 int N005 ( 5, 4) [000055] DA---------- * STORE_LCL_VAR int V10 loc7 d:2 lowering store lcl var/field (before): N001 ( 3, 2) [000063] -------N---- t63 = LCL_VAR_ADDR byref V11 loc8 * ref V11._bits (offs=0x00) -> V54 tmp24 * int V11._sign (offs=0x08) -> V55 tmp25 /--* t63 byref N004 ( 7, 6) [000563] DA--------L- * STORE_LCL_VAR long V75 tmp45 d:2 lowering store lcl var/field (after): N001 ( 3, 2) [000063] -------N---- t63 = LCL_VAR_ADDR byref V11 loc8 * ref V11._bits (offs=0x00) -> V54 tmp24 * int V11._sign (offs=0x08) -> V55 tmp25 /--* t63 byref N004 ( 7, 6) [000563] DA--------L- * STORE_LCL_VAR long V75 tmp45 d:2 lowering store lcl var/field (before): N005 ( 3, 2) [000547] -------N---- t547 = LCL_VAR_ADDR byref V73 tmp43 /--* t547 byref N008 ( 3, 3) [000549] DA---------- * STORE_LCL_VAR byref V74 tmp44 d:2 lowering store lcl var/field (after): N005 ( 3, 2) [000547] -------N---- t547 = LCL_VAR_ADDR byref V73 tmp43 /--* t547 byref N008 ( 3, 3) [000549] DA---------- * STORE_LCL_VAR byref V74 tmp44 d:2 Lower of StoreInd didn't mark the node as self contained for reason: 4 N009 ( 1, 1) [000550] ------------ t550 = LCL_VAR byref V74 tmp44 u:2 Zero Fseq[Mantissa] $401 N011 ( 1, 1) [000552] -------N---- t552 = LCL_VAR ref V52 tmp22 u:2 /--* t550 byref +--* t552 ref [000919] -A---------- * STOREIND ref Addressing mode: Base N014 ( 1, 1) [000555] ------------ * LCL_VAR byref V74 tmp44 u:2 (last use) $401 + 8 Removing unused node: N015 ( 1, 1) [000556] -c---------- * CNS_INT long 8 Fseq[Exponent] $101 New addressing mode node: N016 ( 2, 2) [000557] ------------ * LEA(b+8) byref Lower of StoreInd didn't mark the node as self contained for reason: 4 N014 ( 1, 1) [000555] ------------ t555 = LCL_VAR byref V74 tmp44 u:2 (last use) $401 /--* t555 byref N016 ( 2, 2) [000557] ------------ t557 = * LEA(b+8) byref N018 ( 1, 1) [000559] -------N---- t559 = LCL_VAR int V53 tmp23 u:2 /--* t557 byref +--* t559 int [000920] -A--------L- * STOREIND int lowering call (before): N001 ( 3, 2) [000063] -------N---- t63 = LCL_VAR_ADDR byref V11 loc8 * ref V11._bits (offs=0x00) -> V54 tmp24 * int V11._sign (offs=0x08) -> V55 tmp25 /--* t63 byref N004 ( 7, 6) [000563] DA--------L- * STORE_LCL_VAR long V75 tmp45 d:2 N005 ( 3, 2) [000547] -------N---- t547 = LCL_VAR_ADDR byref V73 tmp43 /--* t547 byref N008 ( 3, 3) [000549] DA---------- * STORE_LCL_VAR byref V74 tmp44 d:2 N009 ( 1, 1) [000550] ------------ t550 = LCL_VAR byref V74 tmp44 u:2 Zero Fseq[Mantissa] $401 N011 ( 1, 1) [000552] -------N---- t552 = LCL_VAR ref V52 tmp22 u:2 /--* t550 byref +--* t552 ref [000919] -A---------- * STOREIND ref N014 ( 1, 1) [000555] ------------ t555 = LCL_VAR byref V74 tmp44 u:2 (last use) $401 /--* t555 byref N016 ( 2, 2) [000557] -c---------- t557 = * LEA(b+8) byref N018 ( 1, 1) [000559] -------N---- t559 = LCL_VAR int V53 tmp23 u:2 /--* t557 byref +--* t559 int [000920] -A--------L- * STOREIND int N023 ( 3, 2) [000564] ------------ t564 = LCL_VAR long V75 tmp45 u:2 (last use) $400 N024 ( 3, 2) [000565] -------N---- t565 = LCL_VAR_ADDR byref V73 tmp43 N026 ( 1, 1) [000058] ------------ t58 = LCL_VAR int V08 loc5 u:2 (last use) $242 N027 ( 1, 1) [000057] ------------ t57 = CNS_INT int 0 $40 /--* t564 long arg0 in rcx +--* t565 byref arg1 in rdx +--* t58 int arg3 in r9 +--* t57 int arg2 in r8 N028 ( 49, 35) [000059] S-CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger $VN.Void objp: ====== args: ====== lowering arg : N004 ( 7, 6) [000563] DA--------L- * STORE_LCL_VAR long V75 tmp45 d:2 lowering arg : [000920] -A--------L- * STOREIND int lowering arg : N021 ( 0, 0) [000568] ----------L- * ARGPLACE int $40 lowering arg : N022 ( 0, 0) [000567] ----------L- * ARGPLACE int $242 late: ====== lowering arg : N023 ( 3, 2) [000564] ------------ * LCL_VAR long V75 tmp45 u:2 (last use) $400 new node is : [001011] ------------ * PUTARG_REG long REG rcx lowering arg : N024 ( 3, 2) [000565] -------N---- * LCL_VAR_ADDR byref V73 tmp43 new node is : [001012] ------------ * PUTARG_REG byref REG rdx lowering arg : N026 ( 1, 1) [000058] ------------ * LCL_VAR int V08 loc5 u:2 (last use) $242 new node is : [001013] ------------ * PUTARG_REG int REG r9 lowering arg : N027 ( 1, 1) [000057] ------------ * CNS_INT int 0 $40 new node is : [001014] ------------ * PUTARG_REG int REG r8 lowering call (after): N001 ( 3, 2) [000063] -------N---- t63 = LCL_VAR_ADDR byref V11 loc8 * ref V11._bits (offs=0x00) -> V54 tmp24 * int V11._sign (offs=0x08) -> V55 tmp25 /--* t63 byref N004 ( 7, 6) [000563] DA--------L- * STORE_LCL_VAR long V75 tmp45 d:2 N005 ( 3, 2) [000547] -------N---- t547 = LCL_VAR_ADDR byref V73 tmp43 /--* t547 byref N008 ( 3, 3) [000549] DA---------- * STORE_LCL_VAR byref V74 tmp44 d:2 N009 ( 1, 1) [000550] ------------ t550 = LCL_VAR byref V74 tmp44 u:2 Zero Fseq[Mantissa] $401 N011 ( 1, 1) [000552] -------N---- t552 = LCL_VAR ref V52 tmp22 u:2 /--* t550 byref +--* t552 ref [000919] -A---------- * STOREIND ref N014 ( 1, 1) [000555] ------------ t555 = LCL_VAR byref V74 tmp44 u:2 (last use) $401 /--* t555 byref N016 ( 2, 2) [000557] -c---------- t557 = * LEA(b+8) byref N018 ( 1, 1) [000559] -------N---- t559 = LCL_VAR int V53 tmp23 u:2 /--* t557 byref +--* t559 int [000920] -A--------L- * STOREIND int N023 ( 3, 2) [000564] ------------ t564 = LCL_VAR long V75 tmp45 u:2 (last use) $400 /--* t564 long [001011] ------------ t1011 = * PUTARG_REG long REG rcx N024 ( 3, 2) [000565] -------N---- t565 = LCL_VAR_ADDR byref V73 tmp43 /--* t565 byref [001012] ------------ t1012 = * PUTARG_REG byref REG rdx N026 ( 1, 1) [000058] ------------ t58 = LCL_VAR int V08 loc5 u:2 (last use) $242 /--* t58 int [001013] ------------ t1013 = * PUTARG_REG int REG r9 N027 ( 1, 1) [000057] ------------ t57 = CNS_INT int 0 $40 /--* t57 int [001014] ------------ t1014 = * PUTARG_REG int REG r8 /--* t1011 long arg0 in rcx +--* t1012 byref arg1 in rdx +--* t1013 int arg3 in r9 +--* t1014 int arg2 in r8 N028 ( 49, 35) [000059] S-CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger $VN.Void lowering call (before): N002 ( 1, 1) [000382] ------------ t382 = LCL_VAR ref V01 arg1 u:1 $c0 /--* t382 ref this in rcx N003 ( 15, 8) [000383] --CXG------- t383 = * CALL int FloatingPointType.get_OverflowDecimalExponent $291 objp: ====== lowering arg : N001 ( 0, 0) [000569] ----------L- * ARGPLACE ref $1c7 args: ====== late: ====== lowering arg : N002 ( 1, 1) [000382] ------------ * LCL_VAR ref V01 arg1 u:1 $c0 new node is : [001015] ------------ * PUTARG_REG ref REG rcx lowering call (after): N002 ( 1, 1) [000382] ------------ t382 = LCL_VAR ref V01 arg1 u:1 $c0 /--* t382 ref [001015] ------------ t1015 = * PUTARG_REG ref REG rcx /--* t1015 ref this in rcx N003 ( 15, 8) [000383] --CXG------- t383 = * CALL int FloatingPointType.get_OverflowDecimalExponent $291 lowering call (before): N002 ( 1, 1) [000393] ------------ t393 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t393 ref this in rcx N003 ( 21, 10) [000394] --CXG------- t394 = * CALLV ind long FloatingPointType.get_Infinity $458 objp: ====== lowering arg : N001 ( 0, 0) [000570] ----------L- * ARGPLACE ref $1fa args: ====== late: ====== lowering arg : N002 ( 1, 1) [000393] ------------ * LCL_VAR ref V01 arg1 u:1 (last use) $c0 new node is : [001016] ------------ * PUTARG_REG ref REG rcx results of lowering call: N001 ( 1, 1) [001017] ------------ t1017 = LCL_VAR ref V01 arg1 /--* t1017 ref N002 ( 2, 2) [001018] ------------ t1018 = * LEA(b+0) byref /--* t1018 byref N003 ( 5, 4) [001019] ------------ t1019 = * IND long /--* t1019 long N004 ( 6, 5) [001020] ------------ t1020 = * LEA(b+80) long /--* t1020 long N005 ( 9, 7) [001021] ------------ t1021 = * IND long /--* t1021 long N006 ( 10, 8) [001022] ------------ t1022 = * LEA(b+8) long /--* t1022 long N007 ( 13, 10) [001023] ------------ t1023 = * IND long lowering call (after): N002 ( 1, 1) [000393] ------------ t393 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t393 ref [001016] ------------ t1016 = * PUTARG_REG ref REG rcx N001 ( 1, 1) [001017] ------------ t1017 = LCL_VAR ref V01 arg1 /--* t1017 ref N002 ( 2, 2) [001018] -c---------- t1018 = * LEA(b+0) byref /--* t1018 byref N003 ( 5, 4) [001019] ------------ t1019 = * IND long /--* t1019 long N004 ( 6, 5) [001020] -c---------- t1020 = * LEA(b+80) long /--* t1020 long N005 ( 9, 7) [001021] ------------ t1021 = * IND long /--* t1021 long N006 ( 10, 8) [001022] -c---------- t1022 = * LEA(b+8) long /--* t1022 long N007 ( 13, 10) [001023] -c---------- t1023 = * IND long REG NA /--* t1016 ref this in rcx +--* t1023 long control expr N003 ( 21, 10) [000394] --CXG------- t394 = * CALLV ind long FloatingPointType.get_Infinity $458 Lower of StoreInd didn't mark the node as self contained for reason: 4 N002 ( 1, 1) [000393] ------------ t393 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t393 ref [001016] ------------ t1016 = * PUTARG_REG ref REG rcx N001 ( 1, 1) [001017] ------------ t1017 = LCL_VAR ref V01 arg1 /--* t1017 ref N002 ( 2, 2) [001018] -c---------- t1018 = * LEA(b+0) byref /--* t1018 byref N003 ( 5, 4) [001019] ------------ t1019 = * IND long /--* t1019 long N004 ( 6, 5) [001020] -c---------- t1020 = * LEA(b+80) long /--* t1020 long N005 ( 9, 7) [001021] ------------ t1021 = * IND long /--* t1021 long N006 ( 10, 8) [001022] -c---------- t1022 = * LEA(b+8) long /--* t1022 long N007 ( 13, 10) [001023] -c---------- t1023 = * IND long REG NA /--* t1016 ref this in rcx +--* t1023 long control expr N003 ( 21, 10) [000394] --CXG------- t394 = * CALLV ind long FloatingPointType.get_Infinity $458 N004 ( 1, 1) [000392] ------------ t392 = LCL_VAR byref V02 arg2 u:1 (last use) $81 /--* t392 byref +--* t394 long [000923] -ACXG------- * STOREIND long lowering GT_RETURN N002 ( 2, 2) [000521] ------------ * RETURN int $5ca ============lowering call (before): N003 ( 3, 2) [000388] -------N---- t388 = LCL_VAR_ADDR byref V11 loc8 * ref V11._bits (offs=0x00) -> V54 tmp24 * int V11._sign (offs=0x08) -> V55 tmp25 N005 ( 3, 2) [000390] ------------ t390 = LCL_VAR int V05 loc2 u:2 (last use) $34e /--* t388 byref arg0 in rcx +--* t390 int arg1 in rdx N006 ( 20, 12) [000391] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen $VN.Void objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000571] ----------L- * ARGPLACE long $404 lowering arg : N002 ( 0, 0) [000572] ----------L- * ARGPLACE int $34e late: ====== lowering arg : N003 ( 3, 2) [000388] -------N---- * LCL_VAR_ADDR byref V11 loc8 * ref V11._bits (offs=0x00) -> V54 tmp24 * int V11._sign (offs=0x08) -> V55 tmp25 new node is : [001024] ------------ * PUTARG_REG byref REG rcx lowering arg : N005 ( 3, 2) [000390] ------------ * LCL_VAR int V05 loc2 u:2 (last use) $34e new node is : [001025] ------------ * PUTARG_REG int REG rdx lowering call (after): N003 ( 3, 2) [000388] -------N---- t388 = LCL_VAR_ADDR byref V11 loc8 * ref V11._bits (offs=0x00) -> V54 tmp24 * int V11._sign (offs=0x08) -> V55 tmp25 /--* t388 byref [001024] ------------ t1024 = * PUTARG_REG byref REG rcx N005 ( 3, 2) [000390] ------------ t390 = LCL_VAR int V05 loc2 u:2 (last use) $34e /--* t390 int [001025] ------------ t1025 = * PUTARG_REG int REG rdx /--* t1024 byref arg0 in rcx +--* t1025 int arg1 in rdx N006 ( 20, 12) [000391] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen $VN.Void lowering store lcl var/field (before): N001 ( 3, 2) [000577] -------N---- t577 = LCL_VAR_ADDR byref V76 tmp46 /--* t577 byref N004 ( 3, 3) [000579] DA---------- * STORE_LCL_VAR byref V77 tmp47 d:2 lowering store lcl var/field (after): N001 ( 3, 2) [000577] -------N---- t577 = LCL_VAR_ADDR byref V76 tmp46 /--* t577 byref N004 ( 3, 3) [000579] DA---------- * STORE_LCL_VAR byref V77 tmp47 d:2 Lower of StoreInd didn't mark the node as self contained for reason: 4 N005 ( 1, 1) [000580] ------------ t580 = LCL_VAR byref V77 tmp47 u:2 Zero Fseq[_bits] $405 N007 ( 3, 2) [000582] -------N---- t582 = LCL_VAR ref (AX) V54 tmp24 $181 /--* t580 byref +--* t582 ref [000925] -A--G------- * STOREIND ref Addressing mode: Base N010 ( 1, 1) [000585] ------------ * LCL_VAR byref V77 tmp47 u:2 (last use) $405 + 8 Removing unused node: N011 ( 1, 1) [000586] -c---------- * CNS_INT long 8 Fseq[_sign] $101 New addressing mode node: N012 ( 2, 2) [000587] ------------ * LEA(b+8) byref Lower of StoreInd didn't mark the node as self contained for reason: 4 N010 ( 1, 1) [000585] ------------ t585 = LCL_VAR byref V77 tmp47 u:2 (last use) $405 /--* t585 byref N012 ( 2, 2) [000587] ------------ t587 = * LEA(b+8) byref N014 ( 3, 2) [000589] -------N---- t589 = LCL_VAR int (AX) V55 tmp25 $243 /--* t587 byref +--* t589 int [000926] -A--G-----L- * STOREIND int lowering call (before): N010 ( 1, 1) [000585] ------------ t585 = LCL_VAR byref V77 tmp47 u:2 (last use) $405 /--* t585 byref N012 ( 2, 2) [000587] -c---------- t587 = * LEA(b+8) byref N014 ( 3, 2) [000589] -------N---- t589 = LCL_VAR int (AX) V55 tmp25 $243 /--* t587 byref +--* t589 int [000926] -A--G-----L- * STOREIND int N018 ( 3, 2) [000592] -------N---- t592 = LCL_VAR_ADDR byref V76 tmp46 N020 ( 3, 3) [000071] ------------ t71 = LCL_VAR_ADDR long V12 loc9 $443 /--* t592 byref arg0 in rcx +--* t71 long arg1 in rdx N021 ( 41, 28) [000072] --CXG------- t72 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $293 objp: ====== args: ====== lowering arg : [000926] -A--G-----L- * STOREIND int lowering arg : N017 ( 0, 0) [000594] ----------L- * ARGPLACE long $443 late: ====== lowering arg : N018 ( 3, 2) [000592] -------N---- * LCL_VAR_ADDR byref V76 tmp46 new node is : [001026] ------------ * PUTARG_REG byref REG rcx lowering arg : N020 ( 3, 3) [000071] ------------ * LCL_VAR_ADDR long V12 loc9 $443 new node is : [001027] ------------ * PUTARG_REG long REG rdx lowering call (after): N010 ( 1, 1) [000585] ------------ t585 = LCL_VAR byref V77 tmp47 u:2 (last use) $405 /--* t585 byref N012 ( 2, 2) [000587] -c---------- t587 = * LEA(b+8) byref N014 ( 3, 2) [000589] -------N---- t589 = LCL_VAR int (AX) V55 tmp25 $243 /--* t587 byref +--* t589 int [000926] -A--G-----L- * STOREIND int N018 ( 3, 2) [000592] -------N---- t592 = LCL_VAR_ADDR byref V76 tmp46 /--* t592 byref [001026] ------------ t1026 = * PUTARG_REG byref REG rcx N020 ( 3, 3) [000071] ------------ t71 = LCL_VAR_ADDR long V12 loc9 $443 /--* t71 long [001027] ------------ t1027 = * PUTARG_REG long REG rdx /--* t1026 byref arg0 in rcx +--* t1027 long arg1 in rdx N021 ( 41, 28) [000072] --CXG------- t72 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $293 lowering store lcl var/field (before): N010 ( 1, 1) [000585] ------------ t585 = LCL_VAR byref V77 tmp47 u:2 (last use) $405 /--* t585 byref N012 ( 2, 2) [000587] -c---------- t587 = * LEA(b+8) byref N014 ( 3, 2) [000589] -------N---- t589 = LCL_VAR int (AX) V55 tmp25 $243 /--* t587 byref +--* t589 int [000926] -A--G-----L- * STOREIND int N018 ( 3, 2) [000592] -------N---- t592 = LCL_VAR_ADDR byref V76 tmp46 /--* t592 byref [001026] ------------ t1026 = * PUTARG_REG byref REG rcx N020 ( 3, 3) [000071] ------------ t71 = LCL_VAR_ADDR long V12 loc9 $443 /--* t71 long [001027] ------------ t1027 = * PUTARG_REG long REG rdx /--* t1026 byref arg0 in rcx +--* t1027 long arg1 in rdx N021 ( 41, 28) [000072] --CXG------- t72 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $293 /--* t72 int N023 ( 41, 28) [000077] DA-XG------- * STORE_LCL_VAR int V13 loc10 d:2 lowering store lcl var/field (after): N010 ( 1, 1) [000585] ------------ t585 = LCL_VAR byref V77 tmp47 u:2 (last use) $405 /--* t585 byref N012 ( 2, 2) [000587] -c---------- t587 = * LEA(b+8) byref N014 ( 3, 2) [000589] -------N---- t589 = LCL_VAR int (AX) V55 tmp25 $243 /--* t587 byref +--* t589 int [000926] -A--G-----L- * STOREIND int N018 ( 3, 2) [000592] -------N---- t592 = LCL_VAR_ADDR byref V76 tmp46 /--* t592 byref [001026] ------------ t1026 = * PUTARG_REG byref REG rcx N020 ( 3, 3) [000071] ------------ t71 = LCL_VAR_ADDR long V12 loc9 $443 /--* t71 long [001027] ------------ t1027 = * PUTARG_REG long REG rdx /--* t1026 byref arg0 in rcx +--* t1027 long arg1 in rdx N021 ( 41, 28) [000072] --CXG------- t72 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $293 /--* t72 int N023 ( 41, 28) [000077] DA-XG------- * STORE_LCL_VAR int V13 loc10 d:2 lowering call (before): N005 ( 1, 1) [000088] ------------ t88 = LCL_VAR byref V02 arg2 u:1 (last use) $81 N006 ( 1, 1) [000084] ------------ t84 = LCL_VAR int V10 loc7 u:2 (last use) N007 ( 1, 1) [000085] -c---------- t85 = CNS_INT int 0 $40 /--* t84 int +--* t85 int N008 ( 6, 3) [000086] N----------- t86 = * NE int N009 ( 3, 2) [000082] ------------ t82 = LCL_VAR ref (AX) V12 loc9 $18d N010 ( 1, 1) [000083] ------------ t83 = LCL_VAR int V13 loc10 u:2 (last use) $293 N011 ( 1, 1) [000087] ------------ t87 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t88 byref arg4 out+20 +--* t86 int arg2 in r8 +--* t82 ref arg0 in rcx +--* t83 int arg1 in rdx +--* t87 ref arg3 in r9 N012 ( 29, 17) [000089] --CXG------- t89 = * CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits $5c7 objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000596] ----------L- * ARGPLACE ref $18d lowering arg : N002 ( 0, 0) [000597] ----------L- * ARGPLACE int $293 lowering arg : N003 ( 0, 0) [000595] ----------L- * ARGPLACE int lowering arg : N004 ( 0, 0) [000598] ----------L- * ARGPLACE ref $c0 lowering arg : N005 ( 1, 1) [000088] ------------ * LCL_VAR byref V02 arg2 u:1 (last use) $81 new node is : [001028] ------------ * PUTARG_STK [+0x20] void late: ====== lowering arg : N008 ( 6, 3) [000086] N----------- * NE int new node is : [001029] ------------ * PUTARG_REG int REG r8 lowering arg : N009 ( 3, 2) [000082] ------------ * LCL_VAR ref (AX) V12 loc9 $18d new node is : [001030] ------------ * PUTARG_REG ref REG rcx lowering arg : N010 ( 1, 1) [000083] ------------ * LCL_VAR int V13 loc10 u:2 (last use) $293 new node is : [001031] ------------ * PUTARG_REG int REG rdx lowering arg : N011 ( 1, 1) [000087] ------------ * LCL_VAR ref V01 arg1 u:1 (last use) $c0 new node is : [001032] ------------ * PUTARG_REG ref REG r9 lowering call (after): N005 ( 1, 1) [000088] ------------ t88 = LCL_VAR byref V02 arg2 u:1 (last use) $81 /--* t88 byref [001028] ------------ * PUTARG_STK [+0x20] void N006 ( 1, 1) [000084] ------------ t84 = LCL_VAR int V10 loc7 u:2 (last use) N007 ( 1, 1) [000085] -c---------- t85 = CNS_INT int 0 $40 /--* t84 int +--* t85 int N008 ( 6, 3) [000086] N----------- t86 = * NE int /--* t86 int [001029] ------------ t1029 = * PUTARG_REG int REG r8 N009 ( 3, 2) [000082] ------------ t82 = LCL_VAR ref (AX) V12 loc9 $18d /--* t82 ref [001030] ------------ t1030 = * PUTARG_REG ref REG rcx N010 ( 1, 1) [000083] ------------ t83 = LCL_VAR int V13 loc10 u:2 (last use) $293 /--* t83 int [001031] ------------ t1031 = * PUTARG_REG int REG rdx N011 ( 1, 1) [000087] ------------ t87 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t87 ref [001032] ------------ t1032 = * PUTARG_REG ref REG r9 /--* t1029 int arg2 in r8 +--* t1030 ref arg0 in rcx +--* t1031 int arg1 in rdx +--* t1032 ref arg3 in r9 N012 ( 29, 17) [000089] --CXG------- t89 = * CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits $5c7 lowering store lcl var/field (before): N005 ( 1, 1) [000088] ------------ t88 = LCL_VAR byref V02 arg2 u:1 (last use) $81 /--* t88 byref [001028] ------------ * PUTARG_STK [+0x20] void N006 ( 1, 1) [000084] ------------ t84 = LCL_VAR int V10 loc7 u:2 (last use) N007 ( 1, 1) [000085] -c---------- t85 = CNS_INT int 0 $40 /--* t84 int +--* t85 int N008 ( 6, 3) [000086] N----------- t86 = * NE int /--* t86 int [001029] ------------ t1029 = * PUTARG_REG int REG r8 N009 ( 3, 2) [000082] ------------ t82 = LCL_VAR ref (AX) V12 loc9 $18d /--* t82 ref [001030] ------------ t1030 = * PUTARG_REG ref REG rcx N010 ( 1, 1) [000083] ------------ t83 = LCL_VAR int V13 loc10 u:2 (last use) $293 /--* t83 int [001031] ------------ t1031 = * PUTARG_REG int REG rdx N011 ( 1, 1) [000087] ------------ t87 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t87 ref [001032] ------------ t1032 = * PUTARG_REG ref REG r9 /--* t1029 int arg2 in r8 +--* t1030 ref arg0 in rcx +--* t1031 int arg1 in rdx +--* t1032 ref arg3 in r9 N012 ( 29, 17) [000089] --CXG------- t89 = * CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits $5c7 /--* t89 int N014 ( 29, 17) [000600] DA-XG------- * STORE_LCL_VAR int V51 tmp21 d:3 lowering store lcl var/field (after): N005 ( 1, 1) [000088] ------------ t88 = LCL_VAR byref V02 arg2 u:1 (last use) $81 /--* t88 byref [001028] ------------ * PUTARG_STK [+0x20] void N006 ( 1, 1) [000084] ------------ t84 = LCL_VAR int V10 loc7 u:2 (last use) N007 ( 1, 1) [000085] -c---------- t85 = CNS_INT int 0 $40 /--* t84 int +--* t85 int N008 ( 6, 3) [000086] N----------- t86 = * NE int /--* t86 int [001029] ------------ t1029 = * PUTARG_REG int REG r8 N009 ( 3, 2) [000082] ------------ t82 = LCL_VAR ref (AX) V12 loc9 $18d /--* t82 ref [001030] ------------ t1030 = * PUTARG_REG ref REG rcx N010 ( 1, 1) [000083] ------------ t83 = LCL_VAR int V13 loc10 u:2 (last use) $293 /--* t83 int [001031] ------------ t1031 = * PUTARG_REG int REG rdx N011 ( 1, 1) [000087] ------------ t87 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t87 ref [001032] ------------ t1032 = * PUTARG_REG ref REG r9 /--* t1029 int arg2 in r8 +--* t1030 ref arg0 in rcx +--* t1031 int arg1 in rdx +--* t1032 ref arg3 in r9 N012 ( 29, 17) [000089] --CXG------- t89 = * CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits $5c7 /--* t89 int N014 ( 29, 17) [000600] DA-XG------- * STORE_LCL_VAR int V51 tmp21 d:3 lowering store lcl var/field (before): N001 ( 1, 1) [000376] ------------ t376 = LCL_VAR int V10 loc7 u:2 /--* t376 int N003 ( 5, 4) [000378] DA---------- * STORE_LCL_VAR int V32 tmp2 d:4 lowering store lcl var/field (after): N001 ( 1, 1) [000376] ------------ t376 = LCL_VAR int V10 loc7 u:2 /--* t376 int N003 ( 5, 4) [000378] DA---------- * STORE_LCL_VAR int V32 tmp2 d:4 lowering store lcl var/field (before): N001 ( 1, 1) [000101] ------------ t101 = LCL_VAR int V10 loc7 u:2 N002 ( 1, 1) [000104] ------------ t104 = LCL_VAR int V53 tmp23 u:2 /--* t101 int +--* t104 int N003 ( 3, 3) [000106] ----G------- t106 = * SUB int /--* t106 int N005 ( 7, 6) [000108] DA--G------- * STORE_LCL_VAR int V32 tmp2 d:3 lowering store lcl var/field (after): N001 ( 1, 1) [000101] ------------ t101 = LCL_VAR int V10 loc7 u:2 N002 ( 1, 1) [000104] ------------ t104 = LCL_VAR int V53 tmp23 u:2 /--* t101 int +--* t104 int N003 ( 3, 3) [000106] ----G------- t106 = * SUB int /--* t106 int N005 ( 7, 6) [000108] DA--G------- * STORE_LCL_VAR int V32 tmp2 d:3 lowering store lcl var/field (before): N001 ( 0, 0) [000905] ------------ t905 = PHI_ARG int V32 tmp2 u:4 N002 ( 0, 0) [000904] ------------ t904 = PHI_ARG int V32 tmp2 u:3 /--* t905 int +--* t904 int N003 ( 0, 0) [000879] ------------ t879 = * PHI int /--* t879 int N005 ( 0, 0) [000880] DA---------- * STORE_LCL_VAR int V32 tmp2 d:2 lowering store lcl var/field (after): N001 ( 0, 0) [000905] ------------ t905 = PHI_ARG int V32 tmp2 u:4 N002 ( 0, 0) [000904] ------------ t904 = PHI_ARG int V32 tmp2 u:3 /--* t905 int +--* t904 int N003 ( 0, 0) [000879] ------------ t879 = * PHI int /--* t879 int N005 ( 0, 0) [000880] DA---------- * STORE_LCL_VAR int V32 tmp2 d:2 lowering store lcl var/field (before): N001 ( 3, 2) [000110] ------------ t110 = LCL_VAR int V32 tmp2 u:2 (last use) $244 /--* t110 int N003 ( 7, 5) [000112] DA---------- * STORE_LCL_VAR int V14 loc11 d:2 lowering store lcl var/field (after): N001 ( 3, 2) [000110] ------------ t110 = LCL_VAR int V32 tmp2 u:2 (last use) $244 /--* t110 int N003 ( 7, 5) [000112] DA---------- * STORE_LCL_VAR int V14 loc11 d:2 Addressing mode: Base N001 ( 1, 1) [000455] ------------ * LCL_VAR ref V52 tmp22 u:2 + 8 Removing unused node: [000993] -c---------- * CNS_INT long 8 New addressing mode node: [000994] ------------ * LEA(b+8) ref lowering store lcl var/field (before): N001 ( 1, 1) [000455] ------------ t455 = LCL_VAR ref V52 tmp22 u:2 /--* t455 ref [000994] -c---------- t994 = * LEA(b+8) ref /--* t994 ref N002 ( 3, 3) [000456] ---XG------- t456 = * IND int /--* t456 int N003 ( 4, 5) [000358] ---XG------- t358 = * CAST long <- int N004 ( 3, 2) [000352] ------------ t352 = LCL_VAR int V14 loc11 u:2 $244 /--* t352 int N005 ( 4, 4) [000353] ---------U-- t353 = * CAST long <- ulong <- uint $486 /--* t353 long +--* t358 long N006 ( 9, 10) [000359] ---XG------- t359 = * SUB long /--* t359 long N008 ( 13, 13) [000363] DA-XG------- * STORE_LCL_VAR long V38 tmp8 d:2 lowering store lcl var/field (after): N001 ( 1, 1) [000455] ------------ t455 = LCL_VAR ref V52 tmp22 u:2 /--* t455 ref [000994] -c---------- t994 = * LEA(b+8) ref /--* t994 ref N002 ( 3, 3) [000456] ---XG------- t456 = * IND int /--* t456 int N003 ( 4, 5) [000358] ---XG------- t358 = * CAST long <- int N004 ( 3, 2) [000352] ------------ t352 = LCL_VAR int V14 loc11 u:2 $244 /--* t352 int N005 ( 4, 4) [000353] ---------U-- t353 = * CAST long <- ulong <- uint $486 /--* t353 long +--* t358 long N006 ( 9, 10) [000359] ---XG------- t359 = * SUB long /--* t359 long N008 ( 13, 13) [000363] DA-XG------- * STORE_LCL_VAR long V38 tmp8 d:2 lowering call (before): N002 ( 1, 1) [000360] ------------ t360 = LCL_VAR ref V01 arg1 u:1 $c0 /--* t360 ref this in rcx N003 ( 15, 8) [000361] --CXG------- t361 = * CALL int FloatingPointType.get_OverflowDecimalExponent $298 objp: ====== lowering arg : N001 ( 0, 0) [000601] ----------L- * ARGPLACE ref $1cd args: ====== late: ====== lowering arg : N002 ( 1, 1) [000360] ------------ * LCL_VAR ref V01 arg1 u:1 $c0 new node is : [001033] ------------ * PUTARG_REG ref REG rcx lowering call (after): N002 ( 1, 1) [000360] ------------ t360 = LCL_VAR ref V01 arg1 u:1 $c0 /--* t360 ref [001033] ------------ t1033 = * PUTARG_REG ref REG rcx /--* t1033 ref this in rcx N003 ( 15, 8) [000361] --CXG------- t361 = * CALL int FloatingPointType.get_OverflowDecimalExponent $298 lowering call (before): N002 ( 1, 1) [000370] ------------ t370 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t370 ref this in rcx N003 ( 21, 10) [000371] --CXG------- t371 = * CALLV ind long FloatingPointType.get_Zero $457 objp: ====== lowering arg : N001 ( 0, 0) [000602] ----------L- * ARGPLACE ref $1f4 args: ====== late: ====== lowering arg : N002 ( 1, 1) [000370] ------------ * LCL_VAR ref V01 arg1 u:1 (last use) $c0 new node is : [001034] ------------ * PUTARG_REG ref REG rcx results of lowering call: N001 ( 1, 1) [001035] ------------ t1035 = LCL_VAR ref V01 arg1 /--* t1035 ref N002 ( 2, 2) [001036] ------------ t1036 = * LEA(b+0) byref /--* t1036 byref N003 ( 5, 4) [001037] ------------ t1037 = * IND long /--* t1037 long N004 ( 6, 5) [001038] ------------ t1038 = * LEA(b+80) long /--* t1038 long N005 ( 9, 7) [001039] ------------ t1039 = * IND long /--* t1039 long N006 ( 10, 8) [001040] ------------ t1040 = * LEA(b+0) long /--* t1040 long N007 ( 13, 10) [001041] ------------ t1041 = * IND long lowering call (after): N002 ( 1, 1) [000370] ------------ t370 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t370 ref [001034] ------------ t1034 = * PUTARG_REG ref REG rcx N001 ( 1, 1) [001035] ------------ t1035 = LCL_VAR ref V01 arg1 /--* t1035 ref N002 ( 2, 2) [001036] -c---------- t1036 = * LEA(b+0) byref /--* t1036 byref N003 ( 5, 4) [001037] ------------ t1037 = * IND long /--* t1037 long N004 ( 6, 5) [001038] -c---------- t1038 = * LEA(b+80) long /--* t1038 long N005 ( 9, 7) [001039] ------------ t1039 = * IND long /--* t1039 long N006 ( 10, 8) [001040] -c---------- t1040 = * LEA(b+0) long /--* t1040 long N007 ( 13, 10) [001041] -c---------- t1041 = * IND long REG NA /--* t1034 ref this in rcx +--* t1041 long control expr N003 ( 21, 10) [000371] --CXG------- t371 = * CALLV ind long FloatingPointType.get_Zero $457 Lower of StoreInd didn't mark the node as self contained for reason: 4 N002 ( 1, 1) [000370] ------------ t370 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t370 ref [001034] ------------ t1034 = * PUTARG_REG ref REG rcx N001 ( 1, 1) [001035] ------------ t1035 = LCL_VAR ref V01 arg1 /--* t1035 ref N002 ( 2, 2) [001036] -c---------- t1036 = * LEA(b+0) byref /--* t1036 byref N003 ( 5, 4) [001037] ------------ t1037 = * IND long /--* t1037 long N004 ( 6, 5) [001038] -c---------- t1038 = * LEA(b+80) long /--* t1038 long N005 ( 9, 7) [001039] ------------ t1039 = * IND long /--* t1039 long N006 ( 10, 8) [001040] -c---------- t1040 = * LEA(b+0) long /--* t1040 long N007 ( 13, 10) [001041] -c---------- t1041 = * IND long REG NA /--* t1034 ref this in rcx +--* t1041 long control expr N003 ( 21, 10) [000371] --CXG------- t371 = * CALLV ind long FloatingPointType.get_Zero $457 N004 ( 1, 1) [000369] ------------ t369 = LCL_VAR byref V02 arg2 u:1 (last use) $81 /--* t369 byref +--* t371 long [000935] -ACXG------- * STOREIND long lowering GT_RETURN N002 ( 2, 2) [000524] ------------ * RETURN int $5c4 ============lowering store lcl var/field (before): N001 ( 3, 2) [000124] -------N---- t124 = LCL_VAR_ADDR byref V15 loc12 * ref V15._bits (offs=0x00) -> V56 tmp26 * int V15._sign (offs=0x08) -> V57 tmp27 /--* t124 byref N004 ( 7, 6) [000623] DA--------L- * STORE_LCL_VAR long V79 tmp49 d:2 lowering store lcl var/field (after): N001 ( 3, 2) [000124] -------N---- t124 = LCL_VAR_ADDR byref V15 loc12 * ref V15._bits (offs=0x00) -> V56 tmp26 * int V15._sign (offs=0x08) -> V57 tmp27 /--* t124 byref N004 ( 7, 6) [000623] DA--------L- * STORE_LCL_VAR long V79 tmp49 d:2 lowering store lcl var/field (before): N005 ( 3, 2) [000607] -------N---- t607 = LCL_VAR_ADDR byref V73 tmp43 /--* t607 byref N008 ( 3, 3) [000609] DA---------- * STORE_LCL_VAR byref V78 tmp48 d:2 lowering store lcl var/field (after): N005 ( 3, 2) [000607] -------N---- t607 = LCL_VAR_ADDR byref V73 tmp43 /--* t607 byref N008 ( 3, 3) [000609] DA---------- * STORE_LCL_VAR byref V78 tmp48 d:2 Lower of StoreInd didn't mark the node as self contained for reason: 4 N009 ( 1, 1) [000610] ------------ t610 = LCL_VAR byref V78 tmp48 u:2 Zero Fseq[Mantissa] $409 N011 ( 1, 1) [000612] -------N---- t612 = LCL_VAR ref V52 tmp22 u:2 (last use) /--* t610 byref +--* t612 ref [000936] -A---------- * STOREIND ref Addressing mode: Base N014 ( 1, 1) [000615] ------------ * LCL_VAR byref V78 tmp48 u:2 (last use) $409 + 8 Removing unused node: N015 ( 1, 1) [000616] -c---------- * CNS_INT long 8 Fseq[Exponent] $101 New addressing mode node: N016 ( 2, 2) [000617] ------------ * LEA(b+8) byref Lower of StoreInd didn't mark the node as self contained for reason: 4 N014 ( 1, 1) [000615] ------------ t615 = LCL_VAR byref V78 tmp48 u:2 (last use) $409 /--* t615 byref N016 ( 2, 2) [000617] ------------ t617 = * LEA(b+8) byref N018 ( 1, 1) [000619] -------N---- t619 = LCL_VAR int V53 tmp23 u:2 (last use) /--* t617 byref +--* t619 int [000937] -A--------L- * STOREIND int lowering call (before): N001 ( 3, 2) [000124] -------N---- t124 = LCL_VAR_ADDR byref V15 loc12 * ref V15._bits (offs=0x00) -> V56 tmp26 * int V15._sign (offs=0x08) -> V57 tmp27 /--* t124 byref N004 ( 7, 6) [000623] DA--------L- * STORE_LCL_VAR long V79 tmp49 d:2 N005 ( 3, 2) [000607] -------N---- t607 = LCL_VAR_ADDR byref V73 tmp43 /--* t607 byref N008 ( 3, 3) [000609] DA---------- * STORE_LCL_VAR byref V78 tmp48 d:2 N009 ( 1, 1) [000610] ------------ t610 = LCL_VAR byref V78 tmp48 u:2 Zero Fseq[Mantissa] $409 N011 ( 1, 1) [000612] -------N---- t612 = LCL_VAR ref V52 tmp22 u:2 (last use) /--* t610 byref +--* t612 ref [000936] -A---------- * STOREIND ref N014 ( 1, 1) [000615] ------------ t615 = LCL_VAR byref V78 tmp48 u:2 (last use) $409 /--* t615 byref N016 ( 2, 2) [000617] -c---------- t617 = * LEA(b+8) byref N018 ( 1, 1) [000619] -------N---- t619 = LCL_VAR int V53 tmp23 u:2 (last use) /--* t617 byref +--* t619 int [000937] -A--------L- * STOREIND int N023 ( 3, 2) [000624] ------------ t624 = LCL_VAR long V79 tmp49 u:2 (last use) $408 N024 ( 3, 2) [000625] -------N---- t625 = LCL_VAR_ADDR byref V73 tmp43 N026 ( 3, 2) [000118] ------------ t118 = LCL_VAR int V08 loc5 u:2 (last use) $242 N027 ( 3, 2) [000119] ------------ t119 = LCL_VAR int V09 loc6 u:2 (last use) /--* t624 long arg0 in rcx +--* t625 byref arg1 in rdx +--* t118 int arg2 in r8 +--* t119 int arg3 in r9 N028 ( 53, 37) [000120] S-CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger $VN.Void objp: ====== args: ====== lowering arg : N004 ( 7, 6) [000623] DA--------L- * STORE_LCL_VAR long V79 tmp49 d:2 lowering arg : [000937] -A--------L- * STOREIND int lowering arg : N021 ( 0, 0) [000627] ----------L- * ARGPLACE int $242 lowering arg : N022 ( 0, 0) [000628] ----------L- * ARGPLACE int late: ====== lowering arg : N023 ( 3, 2) [000624] ------------ * LCL_VAR long V79 tmp49 u:2 (last use) $408 new node is : [001042] ------------ * PUTARG_REG long REG rcx lowering arg : N024 ( 3, 2) [000625] -------N---- * LCL_VAR_ADDR byref V73 tmp43 new node is : [001043] ------------ * PUTARG_REG byref REG rdx lowering arg : N026 ( 3, 2) [000118] ------------ * LCL_VAR int V08 loc5 u:2 (last use) $242 new node is : [001044] ------------ * PUTARG_REG int REG r8 lowering arg : N027 ( 3, 2) [000119] ------------ * LCL_VAR int V09 loc6 u:2 (last use) new node is : [001045] ------------ * PUTARG_REG int REG r9 lowering call (after): N001 ( 3, 2) [000124] -------N---- t124 = LCL_VAR_ADDR byref V15 loc12 * ref V15._bits (offs=0x00) -> V56 tmp26 * int V15._sign (offs=0x08) -> V57 tmp27 /--* t124 byref N004 ( 7, 6) [000623] DA--------L- * STORE_LCL_VAR long V79 tmp49 d:2 N005 ( 3, 2) [000607] -------N---- t607 = LCL_VAR_ADDR byref V73 tmp43 /--* t607 byref N008 ( 3, 3) [000609] DA---------- * STORE_LCL_VAR byref V78 tmp48 d:2 N009 ( 1, 1) [000610] ------------ t610 = LCL_VAR byref V78 tmp48 u:2 Zero Fseq[Mantissa] $409 N011 ( 1, 1) [000612] -------N---- t612 = LCL_VAR ref V52 tmp22 u:2 (last use) /--* t610 byref +--* t612 ref [000936] -A---------- * STOREIND ref N014 ( 1, 1) [000615] ------------ t615 = LCL_VAR byref V78 tmp48 u:2 (last use) $409 /--* t615 byref N016 ( 2, 2) [000617] -c---------- t617 = * LEA(b+8) byref N018 ( 1, 1) [000619] -------N---- t619 = LCL_VAR int V53 tmp23 u:2 (last use) /--* t617 byref +--* t619 int [000937] -A--------L- * STOREIND int N023 ( 3, 2) [000624] ------------ t624 = LCL_VAR long V79 tmp49 u:2 (last use) $408 /--* t624 long [001042] ------------ t1042 = * PUTARG_REG long REG rcx N024 ( 3, 2) [000625] -------N---- t625 = LCL_VAR_ADDR byref V73 tmp43 /--* t625 byref [001043] ------------ t1043 = * PUTARG_REG byref REG rdx N026 ( 3, 2) [000118] ------------ t118 = LCL_VAR int V08 loc5 u:2 (last use) $242 /--* t118 int [001044] ------------ t1044 = * PUTARG_REG int REG r8 N027 ( 3, 2) [000119] ------------ t119 = LCL_VAR int V09 loc6 u:2 (last use) /--* t119 int [001045] ------------ t1045 = * PUTARG_REG int REG r9 /--* t1042 long arg0 in rcx +--* t1043 byref arg1 in rdx +--* t1044 int arg2 in r8 +--* t1045 int arg3 in r9 N028 ( 53, 37) [000120] S-CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger $VN.Void lowering call (before): N003 ( 2, 10) [000131] ------------ t131 = CNS_INT long 0x7ff815262aa0 $102 N004 ( 1, 4) [000132] ------------ t132 = CNS_INT int 173 $58 /--* t131 long arg0 in rcx +--* t132 int arg1 in rdx N005 ( 17, 21) [000133] H-CXG------- t133 = * CALL help long HELPER.CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE $48d objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000629] ----------L- * ARGPLACE long $102 lowering arg : N002 ( 0, 0) [000630] ----------L- * ARGPLACE int $58 late: ====== lowering arg : N003 ( 2, 10) [000131] ------------ * CNS_INT long 0x7ff815262aa0 $102 new node is : [001046] ------------ * PUTARG_REG long REG rcx lowering arg : N004 ( 1, 4) [000132] ------------ * CNS_INT int 173 $58 new node is : [001047] ------------ * PUTARG_REG int REG rdx lowering call (after): N003 ( 2, 10) [000131] ------------ t131 = CNS_INT long 0x7ff815262aa0 $102 /--* t131 long [001046] ------------ t1046 = * PUTARG_REG long REG rcx N004 ( 1, 4) [000132] ------------ t132 = CNS_INT int 173 $58 /--* t132 int [001047] ------------ t1047 = * PUTARG_REG int REG rdx /--* t1046 long arg0 in rcx +--* t1047 int arg1 in rdx N005 ( 17, 21) [000133] H-CXG------- t133 = * CALL help long HELPER.CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE $48d lowering store lcl var/field (before): N001 ( 2, 10) [000634] I----------- t634 = CNS_INT(h) long 0xd1ffab1e static Fseq[BigOne] $4c2 /--* t634 long N002 ( 4, 12) [000633] n---G------- t633 = * IND ref N003 ( 1, 1) [000635] -c---------- t635 = CNS_INT long 8 Fseq[#FirstElem] $101 /--* t633 ref +--* t635 long N004 ( 6, 14) [000632] ----G------- t632 = * ADD byref /--* t632 byref N006 ( 6, 14) [000637] DA--G------- * STORE_LCL_VAR byref V80 tmp50 d:2 lowering store lcl var/field (after): N001 ( 2, 10) [000634] I----------- t634 = CNS_INT(h) long 0xd1ffab1e static Fseq[BigOne] $4c2 /--* t634 long N002 ( 4, 12) [000633] n---G------- t633 = * IND ref N003 ( 1, 1) [000635] -c---------- t635 = CNS_INT long 8 Fseq[#FirstElem] $101 /--* t633 ref +--* t635 long N004 ( 6, 14) [000632] ----G------- t632 = * ADD byref /--* t632 byref N006 ( 6, 14) [000637] DA--G------- * STORE_LCL_VAR byref V80 tmp50 d:2 lowering store lcl var/field (before): N007 ( 1, 1) [000639] ------------ t639 = LCL_VAR byref V80 tmp50 u:2 Zero Fseq[_bits] /--* t639 byref N008 ( 3, 2) [000640] ---X-------- t640 = * IND ref /--* t640 ref N010 ( 7, 5) [000641] DA-XG------- * STORE_LCL_VAR ref (AX) V58 tmp28 lowering store lcl var/field (after): N007 ( 1, 1) [000639] ------------ t639 = LCL_VAR byref V80 tmp50 u:2 Zero Fseq[_bits] /--* t639 byref N008 ( 3, 2) [000640] ---X-------- t640 = * IND ref /--* t640 ref N010 ( 7, 5) [000641] DA-XG------- * STORE_LCL_VAR ref (AX) V58 tmp28 Addressing mode: Base N012 ( 1, 1) [000644] ------------ * LCL_VAR byref V80 tmp50 u:2 (last use) + 8 Removing unused node: N013 ( 1, 1) [000645] -c---------- * CNS_INT long 8 Fseq[_sign] $101 New addressing mode node: N014 ( 2, 2) [000646] ------------ * LEA(b+8) byref lowering store lcl var/field (before): N012 ( 1, 1) [000644] ------------ t644 = LCL_VAR byref V80 tmp50 u:2 (last use) /--* t644 byref N014 ( 2, 2) [000646] -c---------- t646 = * LEA(b+8) byref /--* t646 byref N015 ( 4, 4) [000647] ---X-------- t647 = * IND int /--* t647 int N017 ( 8, 7) [000648] DA-XG------- * STORE_LCL_VAR int (AX) V59 tmp29 lowering store lcl var/field (after): N012 ( 1, 1) [000644] ------------ t644 = LCL_VAR byref V80 tmp50 u:2 (last use) /--* t644 byref N014 ( 2, 2) [000646] -c---------- t646 = * LEA(b+8) byref /--* t646 byref N015 ( 4, 4) [000647] ---X-------- t647 = * IND int /--* t647 int N017 ( 8, 7) [000648] DA-XG------- * STORE_LCL_VAR int (AX) V59 tmp29 lowering call (before): N003 ( 3, 2) [000138] -------N---- t138 = LCL_VAR_ADDR byref V16 loc13 * ref V16._bits (offs=0x00) -> V58 tmp28 * int V16._sign (offs=0x08) -> V59 tmp29 N005 ( 3, 2) [000140] ------------ t140 = LCL_VAR int V14 loc11 u:2 (last use) $244 /--* t138 byref arg0 in rcx +--* t140 int arg1 in rdx N006 ( 20, 12) [000141] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen $VN.Void objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000650] ----------L- * ARGPLACE long $40d lowering arg : N002 ( 0, 0) [000651] ----------L- * ARGPLACE int $244 late: ====== lowering arg : N003 ( 3, 2) [000138] -------N---- * LCL_VAR_ADDR byref V16 loc13 * ref V16._bits (offs=0x00) -> V58 tmp28 * int V16._sign (offs=0x08) -> V59 tmp29 new node is : [001048] ------------ * PUTARG_REG byref REG rcx lowering arg : N005 ( 3, 2) [000140] ------------ * LCL_VAR int V14 loc11 u:2 (last use) $244 new node is : [001049] ------------ * PUTARG_REG int REG rdx lowering call (after): N003 ( 3, 2) [000138] -------N---- t138 = LCL_VAR_ADDR byref V16 loc13 * ref V16._bits (offs=0x00) -> V58 tmp28 * int V16._sign (offs=0x08) -> V59 tmp29 /--* t138 byref [001048] ------------ t1048 = * PUTARG_REG byref REG rcx N005 ( 3, 2) [000140] ------------ t140 = LCL_VAR int V14 loc11 u:2 (last use) $244 /--* t140 int [001049] ------------ t1049 = * PUTARG_REG int REG rdx /--* t1048 byref arg0 in rcx +--* t1049 int arg1 in rdx N006 ( 20, 12) [000141] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen $VN.Void lowering store lcl var/field (before): N001 ( 3, 2) [000653] -------N---- t653 = LCL_VAR ref (AX) V56 tmp26 $184 /--* t653 ref N003 ( 7, 5) [000654] DA--G------- * STORE_LCL_VAR ref V64 tmp34 d:2 lowering store lcl var/field (after): N001 ( 3, 2) [000653] -------N---- t653 = LCL_VAR ref (AX) V56 tmp26 $184 /--* t653 ref N003 ( 7, 5) [000654] DA--G------- * STORE_LCL_VAR ref V64 tmp34 d:2 lowering store lcl var/field (before): N004 ( 3, 2) [000656] -------N---- t656 = LCL_VAR int (AX) V57 tmp27 $246 /--* t656 int N006 ( 7, 5) [000657] DA--G------- * STORE_LCL_VAR int V65 tmp35 d:2 lowering store lcl var/field (after): N004 ( 3, 2) [000656] -------N---- t656 = LCL_VAR int (AX) V57 tmp27 $246 /--* t656 int N006 ( 7, 5) [000657] DA--G------- * STORE_LCL_VAR int V65 tmp35 d:2 lowering store lcl var/field (before): N001 ( 3, 2) [000663] -------N---- t663 = LCL_VAR_ADDR byref V76 tmp46 /--* t663 byref N004 ( 3, 3) [000665] DA---------- * STORE_LCL_VAR byref V81 tmp51 d:2 lowering store lcl var/field (after): N001 ( 3, 2) [000663] -------N---- t663 = LCL_VAR_ADDR byref V76 tmp46 /--* t663 byref N004 ( 3, 3) [000665] DA---------- * STORE_LCL_VAR byref V81 tmp51 d:2 Lower of StoreInd didn't mark the node as self contained for reason: 4 N005 ( 1, 1) [000666] ------------ t666 = LCL_VAR byref V81 tmp51 u:2 Zero Fseq[_bits] $40e N007 ( 3, 2) [000668] -------N---- t668 = LCL_VAR ref V64 tmp34 u:2 (last use) $184 /--* t666 byref +--* t668 ref [000942] -A---------- * STOREIND ref Addressing mode: Base N010 ( 1, 1) [000671] ------------ * LCL_VAR byref V81 tmp51 u:2 (last use) $40e + 8 Removing unused node: N011 ( 1, 1) [000672] -c---------- * CNS_INT long 8 Fseq[_sign] $101 New addressing mode node: N012 ( 2, 2) [000673] ------------ * LEA(b+8) byref Lower of StoreInd didn't mark the node as self contained for reason: 4 N010 ( 1, 1) [000671] ------------ t671 = LCL_VAR byref V81 tmp51 u:2 (last use) $40e /--* t671 byref N012 ( 2, 2) [000673] ------------ t673 = * LEA(b+8) byref N014 ( 3, 2) [000675] -------N---- t675 = LCL_VAR int V65 tmp35 u:2 (last use) $246 /--* t673 byref +--* t675 int [000943] -A--------L- * STOREIND int lowering call (before): N010 ( 1, 1) [000671] ------------ t671 = LCL_VAR byref V81 tmp51 u:2 (last use) $40e /--* t671 byref N012 ( 2, 2) [000673] -c---------- t673 = * LEA(b+8) byref N014 ( 3, 2) [000675] -------N---- t675 = LCL_VAR int V65 tmp35 u:2 (last use) $246 /--* t673 byref +--* t675 int [000943] -A--------L- * STOREIND int N018 ( 3, 2) [000678] -------N---- t678 = LCL_VAR_ADDR byref V76 tmp46 N020 ( 3, 3) [000462] ------------ t462 = LCL_VAR_ADDR long V45 tmp15 $449 /--* t678 byref arg0 in rcx +--* t462 long arg1 in rdx N021 ( 41, 28) [000463] --CXG------- t463 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $29f objp: ====== args: ====== lowering arg : [000943] -A--------L- * STOREIND int lowering arg : N017 ( 0, 0) [000680] ----------L- * ARGPLACE long $449 late: ====== lowering arg : N018 ( 3, 2) [000678] -------N---- * LCL_VAR_ADDR byref V76 tmp46 new node is : [001050] ------------ * PUTARG_REG byref REG rcx lowering arg : N020 ( 3, 3) [000462] ------------ * LCL_VAR_ADDR long V45 tmp15 $449 new node is : [001051] ------------ * PUTARG_REG long REG rdx lowering call (after): N010 ( 1, 1) [000671] ------------ t671 = LCL_VAR byref V81 tmp51 u:2 (last use) $40e /--* t671 byref N012 ( 2, 2) [000673] -c---------- t673 = * LEA(b+8) byref N014 ( 3, 2) [000675] -------N---- t675 = LCL_VAR int V65 tmp35 u:2 (last use) $246 /--* t673 byref +--* t675 int [000943] -A--------L- * STOREIND int N018 ( 3, 2) [000678] -------N---- t678 = LCL_VAR_ADDR byref V76 tmp46 /--* t678 byref [001050] ------------ t1050 = * PUTARG_REG byref REG rcx N020 ( 3, 3) [000462] ------------ t462 = LCL_VAR_ADDR long V45 tmp15 $449 /--* t462 long [001051] ------------ t1051 = * PUTARG_REG long REG rdx /--* t1050 byref arg0 in rcx +--* t1051 long arg1 in rdx N021 ( 41, 28) [000463] --CXG------- t463 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $29f lowering store lcl var/field (before): N010 ( 1, 1) [000671] ------------ t671 = LCL_VAR byref V81 tmp51 u:2 (last use) $40e /--* t671 byref N012 ( 2, 2) [000673] -c---------- t673 = * LEA(b+8) byref N014 ( 3, 2) [000675] -------N---- t675 = LCL_VAR int V65 tmp35 u:2 (last use) $246 /--* t673 byref +--* t675 int [000943] -A--------L- * STOREIND int N018 ( 3, 2) [000678] -------N---- t678 = LCL_VAR_ADDR byref V76 tmp46 /--* t678 byref [001050] ------------ t1050 = * PUTARG_REG byref REG rcx N020 ( 3, 3) [000462] ------------ t462 = LCL_VAR_ADDR long V45 tmp15 $449 /--* t462 long [001051] ------------ t1051 = * PUTARG_REG long REG rdx /--* t1050 byref arg0 in rcx +--* t1051 long arg1 in rdx N021 ( 41, 28) [000463] --CXG------- t463 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $29f /--* t463 int N023 ( 45, 31) [000468] DA-XG------- * STORE_LCL_VAR int V43 tmp13 d:2 lowering store lcl var/field (after): N010 ( 1, 1) [000671] ------------ t671 = LCL_VAR byref V81 tmp51 u:2 (last use) $40e /--* t671 byref N012 ( 2, 2) [000673] -c---------- t673 = * LEA(b+8) byref N014 ( 3, 2) [000675] -------N---- t675 = LCL_VAR int V65 tmp35 u:2 (last use) $246 /--* t673 byref +--* t675 int [000943] -A--------L- * STOREIND int N018 ( 3, 2) [000678] -------N---- t678 = LCL_VAR_ADDR byref V76 tmp46 /--* t678 byref [001050] ------------ t1050 = * PUTARG_REG byref REG rcx N020 ( 3, 3) [000462] ------------ t462 = LCL_VAR_ADDR long V45 tmp15 $449 /--* t462 long [001051] ------------ t1051 = * PUTARG_REG long REG rdx /--* t1050 byref arg0 in rcx +--* t1051 long arg1 in rdx N021 ( 41, 28) [000463] --CXG------- t463 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $29f /--* t463 int N023 ( 45, 31) [000468] DA-XG------- * STORE_LCL_VAR int V43 tmp13 d:2 lowering store lcl var/field (before): N001 ( 1, 1) [000473] ------------ t473 = CNS_INT ref null $VN.Null /--* t473 ref N003 ( 5, 4) [000475] DA--G------- * STORE_LCL_VAR ref (AX) V45 tmp15 lowering store lcl var/field (after): N001 ( 1, 1) [000473] ------------ t473 = CNS_INT ref null $VN.Null /--* t473 ref N003 ( 5, 4) [000475] DA--G------- * STORE_LCL_VAR ref (AX) V45 tmp15 lowering store lcl var/field (before): N001 ( 3, 2) [000469] ------------ t469 = LCL_VAR int V43 tmp13 u:2 $29f /--* t469 int N003 ( 7, 5) [000148] DA---------- * STORE_LCL_VAR int V17 loc14 d:2 lowering store lcl var/field (after): N001 ( 3, 2) [000469] ------------ t469 = LCL_VAR int V43 tmp13 u:2 $29f /--* t469 int N003 ( 7, 5) [000148] DA---------- * STORE_LCL_VAR int V17 loc14 d:2 lowering store lcl var/field (before): N001 ( 3, 2) [000682] -------N---- t682 = LCL_VAR ref (AX) V58 tmp28 $185 /--* t682 ref N003 ( 7, 5) [000683] DA--G------- * STORE_LCL_VAR ref V66 tmp36 d:2 lowering store lcl var/field (after): N001 ( 3, 2) [000682] -------N---- t682 = LCL_VAR ref (AX) V58 tmp28 $185 /--* t682 ref N003 ( 7, 5) [000683] DA--G------- * STORE_LCL_VAR ref V66 tmp36 d:2 lowering store lcl var/field (before): N004 ( 3, 2) [000685] -------N---- t685 = LCL_VAR int (AX) V59 tmp29 $247 /--* t685 int N006 ( 7, 5) [000686] DA--G------- * STORE_LCL_VAR int V67 tmp37 d:2 lowering store lcl var/field (after): N004 ( 3, 2) [000685] -------N---- t685 = LCL_VAR int (AX) V59 tmp29 $247 /--* t685 int N006 ( 7, 5) [000686] DA--G------- * STORE_LCL_VAR int V67 tmp37 d:2 lowering store lcl var/field (before): N001 ( 3, 2) [000692] -------N---- t692 = LCL_VAR_ADDR byref V76 tmp46 /--* t692 byref N004 ( 3, 3) [000694] DA---------- * STORE_LCL_VAR byref V82 tmp52 d:2 lowering store lcl var/field (after): N001 ( 3, 2) [000692] -------N---- t692 = LCL_VAR_ADDR byref V76 tmp46 /--* t692 byref N004 ( 3, 3) [000694] DA---------- * STORE_LCL_VAR byref V82 tmp52 d:2 Lower of StoreInd didn't mark the node as self contained for reason: 4 N005 ( 1, 1) [000695] ------------ t695 = LCL_VAR byref V82 tmp52 u:2 Zero Fseq[_bits] $411 N007 ( 3, 2) [000697] -------N---- t697 = LCL_VAR ref V66 tmp36 u:2 (last use) $185 /--* t695 byref +--* t697 ref [000947] -A---------- * STOREIND ref Addressing mode: Base N010 ( 1, 1) [000700] ------------ * LCL_VAR byref V82 tmp52 u:2 (last use) $411 + 8 Removing unused node: N011 ( 1, 1) [000701] -c---------- * CNS_INT long 8 Fseq[_sign] $101 New addressing mode node: N012 ( 2, 2) [000702] ------------ * LEA(b+8) byref Lower of StoreInd didn't mark the node as self contained for reason: 4 N010 ( 1, 1) [000700] ------------ t700 = LCL_VAR byref V82 tmp52 u:2 (last use) $411 /--* t700 byref N012 ( 2, 2) [000702] ------------ t702 = * LEA(b+8) byref N014 ( 3, 2) [000704] -------N---- t704 = LCL_VAR int V67 tmp37 u:2 (last use) $247 /--* t702 byref +--* t704 int [000948] -A--------L- * STOREIND int lowering call (before): N010 ( 1, 1) [000700] ------------ t700 = LCL_VAR byref V82 tmp52 u:2 (last use) $411 /--* t700 byref N012 ( 2, 2) [000702] -c---------- t702 = * LEA(b+8) byref N014 ( 3, 2) [000704] -------N---- t704 = LCL_VAR int V67 tmp37 u:2 (last use) $247 /--* t702 byref +--* t704 int [000948] -A--------L- * STOREIND int N018 ( 3, 2) [000707] -------N---- t707 = LCL_VAR_ADDR byref V76 tmp46 N020 ( 3, 3) [000480] ------------ t480 = LCL_VAR_ADDR long V48 tmp18 $44b /--* t707 byref arg0 in rcx +--* t480 long arg1 in rdx N021 ( 41, 28) [000481] --CXG------- t481 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $2a3 objp: ====== args: ====== lowering arg : [000948] -A--------L- * STOREIND int lowering arg : N017 ( 0, 0) [000709] ----------L- * ARGPLACE long $44b late: ====== lowering arg : N018 ( 3, 2) [000707] -------N---- * LCL_VAR_ADDR byref V76 tmp46 new node is : [001052] ------------ * PUTARG_REG byref REG rcx lowering arg : N020 ( 3, 3) [000480] ------------ * LCL_VAR_ADDR long V48 tmp18 $44b new node is : [001053] ------------ * PUTARG_REG long REG rdx lowering call (after): N010 ( 1, 1) [000700] ------------ t700 = LCL_VAR byref V82 tmp52 u:2 (last use) $411 /--* t700 byref N012 ( 2, 2) [000702] -c---------- t702 = * LEA(b+8) byref N014 ( 3, 2) [000704] -------N---- t704 = LCL_VAR int V67 tmp37 u:2 (last use) $247 /--* t702 byref +--* t704 int [000948] -A--------L- * STOREIND int N018 ( 3, 2) [000707] -------N---- t707 = LCL_VAR_ADDR byref V76 tmp46 /--* t707 byref [001052] ------------ t1052 = * PUTARG_REG byref REG rcx N020 ( 3, 3) [000480] ------------ t480 = LCL_VAR_ADDR long V48 tmp18 $44b /--* t480 long [001053] ------------ t1053 = * PUTARG_REG long REG rdx /--* t1052 byref arg0 in rcx +--* t1053 long arg1 in rdx N021 ( 41, 28) [000481] --CXG------- t481 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $2a3 lowering store lcl var/field (before): N010 ( 1, 1) [000700] ------------ t700 = LCL_VAR byref V82 tmp52 u:2 (last use) $411 /--* t700 byref N012 ( 2, 2) [000702] -c---------- t702 = * LEA(b+8) byref N014 ( 3, 2) [000704] -------N---- t704 = LCL_VAR int V67 tmp37 u:2 (last use) $247 /--* t702 byref +--* t704 int [000948] -A--------L- * STOREIND int N018 ( 3, 2) [000707] -------N---- t707 = LCL_VAR_ADDR byref V76 tmp46 /--* t707 byref [001052] ------------ t1052 = * PUTARG_REG byref REG rcx N020 ( 3, 3) [000480] ------------ t480 = LCL_VAR_ADDR long V48 tmp18 $44b /--* t480 long [001053] ------------ t1053 = * PUTARG_REG long REG rdx /--* t1052 byref arg0 in rcx +--* t1053 long arg1 in rdx N021 ( 41, 28) [000481] --CXG------- t481 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $2a3 /--* t481 int N023 ( 45, 31) [000486] DA-XG------- * STORE_LCL_VAR int V46 tmp16 d:2 lowering store lcl var/field (after): N010 ( 1, 1) [000700] ------------ t700 = LCL_VAR byref V82 tmp52 u:2 (last use) $411 /--* t700 byref N012 ( 2, 2) [000702] -c---------- t702 = * LEA(b+8) byref N014 ( 3, 2) [000704] -------N---- t704 = LCL_VAR int V67 tmp37 u:2 (last use) $247 /--* t702 byref +--* t704 int [000948] -A--------L- * STOREIND int N018 ( 3, 2) [000707] -------N---- t707 = LCL_VAR_ADDR byref V76 tmp46 /--* t707 byref [001052] ------------ t1052 = * PUTARG_REG byref REG rcx N020 ( 3, 3) [000480] ------------ t480 = LCL_VAR_ADDR long V48 tmp18 $44b /--* t480 long [001053] ------------ t1053 = * PUTARG_REG long REG rdx /--* t1052 byref arg0 in rcx +--* t1053 long arg1 in rdx N021 ( 41, 28) [000481] --CXG------- t481 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $2a3 /--* t481 int N023 ( 45, 31) [000486] DA-XG------- * STORE_LCL_VAR int V46 tmp16 d:2 lowering store lcl var/field (before): N001 ( 1, 1) [000491] ------------ t491 = CNS_INT ref null $VN.Null /--* t491 ref N003 ( 5, 4) [000493] DA--G------- * STORE_LCL_VAR ref (AX) V48 tmp18 lowering store lcl var/field (after): N001 ( 1, 1) [000491] ------------ t491 = CNS_INT ref null $VN.Null /--* t491 ref N003 ( 5, 4) [000493] DA--G------- * STORE_LCL_VAR ref (AX) V48 tmp18 lowering store lcl var/field (before): N001 ( 3, 2) [000487] ------------ t487 = LCL_VAR int V46 tmp16 u:2 $2a3 /--* t487 int N003 ( 7, 5) [000155] DA---------- * STORE_LCL_VAR int V18 loc15 d:2 lowering store lcl var/field (after): N001 ( 3, 2) [000487] ------------ t487 = LCL_VAR int V46 tmp16 u:2 $2a3 /--* t487 int N003 ( 7, 5) [000155] DA---------- * STORE_LCL_VAR int V18 loc15 d:2 lowering store lcl var/field (before): N001 ( 1, 1) [000348] ------------ t348 = CNS_INT int 0 $40 /--* t348 int N003 ( 5, 4) [000350] DA---------- * STORE_LCL_VAR int V33 tmp3 d:4 lowering store lcl var/field (after): N001 ( 1, 1) [000348] ------------ t348 = CNS_INT int 0 $40 /--* t348 int N003 ( 5, 4) [000350] DA---------- * STORE_LCL_VAR int V33 tmp3 d:4 lowering store lcl var/field (before): N001 ( 3, 2) [000160] ------------ t160 = LCL_VAR int V18 loc15 u:2 (last use) $2a3 N002 ( 3, 2) [000161] ------------ t161 = LCL_VAR int V17 loc14 u:2 (last use) $29f /--* t160 int +--* t161 int N003 ( 7, 5) [000162] ------------ t162 = * SUB int $360 /--* t162 int N005 ( 11, 8) [000164] DA---------- * STORE_LCL_VAR int V33 tmp3 d:3 lowering store lcl var/field (after): N001 ( 3, 2) [000160] ------------ t160 = LCL_VAR int V18 loc15 u:2 (last use) $2a3 N002 ( 3, 2) [000161] ------------ t161 = LCL_VAR int V17 loc14 u:2 (last use) $29f /--* t160 int +--* t161 int N003 ( 7, 5) [000162] ------------ t162 = * SUB int $360 /--* t162 int N005 ( 11, 8) [000164] DA---------- * STORE_LCL_VAR int V33 tmp3 d:3 lowering store lcl var/field (before): N001 ( 0, 0) [000903] ------------ t903 = PHI_ARG int V33 tmp3 u:4 $40 N002 ( 0, 0) [000902] ------------ t902 = PHI_ARG int V33 tmp3 u:3 $360 /--* t903 int +--* t902 int N003 ( 0, 0) [000876] ------------ t876 = * PHI int /--* t876 int N005 ( 0, 0) [000877] DA---------- * STORE_LCL_VAR int V33 tmp3 d:2 lowering store lcl var/field (after): N001 ( 0, 0) [000903] ------------ t903 = PHI_ARG int V33 tmp3 u:4 $40 N002 ( 0, 0) [000902] ------------ t902 = PHI_ARG int V33 tmp3 u:3 $360 /--* t903 int +--* t902 int N003 ( 0, 0) [000876] ------------ t876 = * PHI int /--* t876 int N005 ( 0, 0) [000877] DA---------- * STORE_LCL_VAR int V33 tmp3 d:2 lowering store lcl var/field (before): N001 ( 3, 2) [000166] ------------ t166 = LCL_VAR int V33 tmp3 u:2 $248 /--* t166 int N003 ( 3, 3) [000168] DA---------- * STORE_LCL_VAR int V19 loc16 d:2 lowering store lcl var/field (after): N001 ( 3, 2) [000166] ------------ t166 = LCL_VAR int V33 tmp3 u:2 $248 /--* t166 int N003 ( 3, 3) [000168] DA---------- * STORE_LCL_VAR int V19 loc16 d:2 lowering call (before): N003 ( 3, 2) [000344] -------N---- t344 = LCL_VAR_ADDR byref V15 loc12 * ref V15._bits (offs=0x00) -> V56 tmp26 * int V15._sign (offs=0x08) -> V57 tmp27 N005 ( 1, 1) [000346] ------------ t346 = LCL_VAR int V19 loc16 u:2 $248 /--* t344 byref arg0 in rcx +--* t346 int arg1 in rdx N006 ( 18, 11) [000347] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft $VN.Void objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000710] ----------L- * ARGPLACE long $414 lowering arg : N002 ( 0, 0) [000711] ----------L- * ARGPLACE int $248 late: ====== lowering arg : N003 ( 3, 2) [000344] -------N---- * LCL_VAR_ADDR byref V15 loc12 * ref V15._bits (offs=0x00) -> V56 tmp26 * int V15._sign (offs=0x08) -> V57 tmp27 new node is : [001054] ------------ * PUTARG_REG byref REG rcx lowering arg : N005 ( 1, 1) [000346] ------------ * LCL_VAR int V19 loc16 u:2 $248 new node is : [001055] ------------ * PUTARG_REG int REG rdx lowering call (after): N003 ( 3, 2) [000344] -------N---- t344 = LCL_VAR_ADDR byref V15 loc12 * ref V15._bits (offs=0x00) -> V56 tmp26 * int V15._sign (offs=0x08) -> V57 tmp27 /--* t344 byref [001054] ------------ t1054 = * PUTARG_REG byref REG rcx N005 ( 1, 1) [000346] ------------ t346 = LCL_VAR int V19 loc16 u:2 $248 /--* t346 int [001055] ------------ t1055 = * PUTARG_REG int REG rdx /--* t1054 byref arg0 in rcx +--* t1055 int arg1 in rdx N006 ( 18, 11) [000347] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft $VN.Void lowering store lcl var/field (before): N001 ( 3, 2) [000173] ------------ t173 = LCL_VAR int V03 loc0 u:2 (last use) $348 N002 ( 1, 1) [000174] ------------ t174 = LCL_VAR int V13 loc10 u:2 $293 /--* t173 int +--* t174 int N003 ( 5, 4) [000175] ------------ t175 = * SUB int $362 /--* t175 int N005 ( 9, 7) [000177] DA---------- * STORE_LCL_VAR int V20 loc17 d:2 lowering store lcl var/field (after): N001 ( 3, 2) [000173] ------------ t173 = LCL_VAR int V03 loc0 u:2 (last use) $348 N002 ( 1, 1) [000174] ------------ t174 = LCL_VAR int V13 loc10 u:2 $293 /--* t173 int +--* t174 int N003 ( 5, 4) [000175] ------------ t175 = * SUB int $362 /--* t175 int N005 ( 9, 7) [000177] DA---------- * STORE_LCL_VAR int V20 loc17 d:2 lowering store lcl var/field (before): N001 ( 3, 2) [000178] ------------ t178 = LCL_VAR int V20 loc17 u:2 $362 /--* t178 int N003 ( 7, 5) [000180] DA---------- * STORE_LCL_VAR int V21 loc18 d:2 lowering store lcl var/field (after): N001 ( 3, 2) [000178] ------------ t178 = LCL_VAR int V20 loc17 u:2 $362 /--* t178 int N003 ( 7, 5) [000180] DA---------- * STORE_LCL_VAR int V21 loc18 d:2 lowering call (before): N005 ( 1, 1) [000341] ------------ t341 = LCL_VAR byref V02 arg2 u:1 (last use) $81 N006 ( 1, 1) [000339] ------------ t339 = CNS_INT int 1 $41 N007 ( 3, 2) [000335] ------------ t335 = LCL_VAR ref (AX) V12 loc9 $18c N008 ( 1, 1) [000336] ------------ t336 = LCL_VAR int V13 loc10 u:2 (last use) $293 N009 ( 1, 1) [000340] ------------ t340 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t341 byref arg4 out+20 +--* t339 int arg2 in r8 +--* t335 ref arg0 in rcx +--* t336 int arg1 in rdx +--* t340 ref arg3 in r9 N010 ( 24, 15) [000342] --CXG------- t342 = * CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits $5c2 objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000713] ----------L- * ARGPLACE ref $18c lowering arg : N002 ( 0, 0) [000714] ----------L- * ARGPLACE int $293 lowering arg : N003 ( 0, 0) [000712] ----------L- * ARGPLACE int lowering arg : N004 ( 0, 0) [000715] ----------L- * ARGPLACE ref $c0 lowering arg : N005 ( 1, 1) [000341] ------------ * LCL_VAR byref V02 arg2 u:1 (last use) $81 new node is : [001056] ------------ * PUTARG_STK [+0x20] void late: ====== lowering arg : N006 ( 1, 1) [000339] ------------ * CNS_INT int 1 $41 new node is : [001057] ------------ * PUTARG_REG int REG r8 lowering arg : N007 ( 3, 2) [000335] ------------ * LCL_VAR ref (AX) V12 loc9 $18c new node is : [001058] ------------ * PUTARG_REG ref REG rcx lowering arg : N008 ( 1, 1) [000336] ------------ * LCL_VAR int V13 loc10 u:2 (last use) $293 new node is : [001059] ------------ * PUTARG_REG int REG rdx lowering arg : N009 ( 1, 1) [000340] ------------ * LCL_VAR ref V01 arg1 u:1 (last use) $c0 new node is : [001060] ------------ * PUTARG_REG ref REG r9 lowering call (after): N005 ( 1, 1) [000341] ------------ t341 = LCL_VAR byref V02 arg2 u:1 (last use) $81 /--* t341 byref [001056] ------------ * PUTARG_STK [+0x20] void N006 ( 1, 1) [000339] ------------ t339 = CNS_INT int 1 $41 /--* t339 int [001057] ------------ t1057 = * PUTARG_REG int REG r8 N007 ( 3, 2) [000335] ------------ t335 = LCL_VAR ref (AX) V12 loc9 $18c /--* t335 ref [001058] ------------ t1058 = * PUTARG_REG ref REG rcx N008 ( 1, 1) [000336] ------------ t336 = LCL_VAR int V13 loc10 u:2 (last use) $293 /--* t336 int [001059] ------------ t1059 = * PUTARG_REG int REG rdx N009 ( 1, 1) [000340] ------------ t340 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t340 ref [001060] ------------ t1060 = * PUTARG_REG ref REG r9 /--* t1057 int arg2 in r8 +--* t1058 ref arg0 in rcx +--* t1059 int arg1 in rdx +--* t1060 ref arg3 in r9 N010 ( 24, 15) [000342] --CXG------- t342 = * CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits $5c2 lowering store lcl var/field (before): N005 ( 1, 1) [000341] ------------ t341 = LCL_VAR byref V02 arg2 u:1 (last use) $81 /--* t341 byref [001056] ------------ * PUTARG_STK [+0x20] void N006 ( 1, 1) [000339] ------------ t339 = CNS_INT int 1 $41 /--* t339 int [001057] ------------ t1057 = * PUTARG_REG int REG r8 N007 ( 3, 2) [000335] ------------ t335 = LCL_VAR ref (AX) V12 loc9 $18c /--* t335 ref [001058] ------------ t1058 = * PUTARG_REG ref REG rcx N008 ( 1, 1) [000336] ------------ t336 = LCL_VAR int V13 loc10 u:2 (last use) $293 /--* t336 int [001059] ------------ t1059 = * PUTARG_REG int REG rdx N009 ( 1, 1) [000340] ------------ t340 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t340 ref [001060] ------------ t1060 = * PUTARG_REG ref REG r9 /--* t1057 int arg2 in r8 +--* t1058 ref arg0 in rcx +--* t1059 int arg1 in rdx +--* t1060 ref arg3 in r9 N010 ( 24, 15) [000342] --CXG------- t342 = * CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits $5c2 /--* t342 int N012 ( 24, 15) [000717] DA-XG------- * STORE_LCL_VAR int V51 tmp21 d:5 lowering store lcl var/field (after): N005 ( 1, 1) [000341] ------------ t341 = LCL_VAR byref V02 arg2 u:1 (last use) $81 /--* t341 byref [001056] ------------ * PUTARG_STK [+0x20] void N006 ( 1, 1) [000339] ------------ t339 = CNS_INT int 1 $41 /--* t339 int [001057] ------------ t1057 = * PUTARG_REG int REG r8 N007 ( 3, 2) [000335] ------------ t335 = LCL_VAR ref (AX) V12 loc9 $18c /--* t335 ref [001058] ------------ t1058 = * PUTARG_REG ref REG rcx N008 ( 1, 1) [000336] ------------ t336 = LCL_VAR int V13 loc10 u:2 (last use) $293 /--* t336 int [001059] ------------ t1059 = * PUTARG_REG int REG rdx N009 ( 1, 1) [000340] ------------ t340 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t340 ref [001060] ------------ t1060 = * PUTARG_REG ref REG r9 /--* t1057 int arg2 in r8 +--* t1058 ref arg0 in rcx +--* t1059 int arg1 in rdx +--* t1060 ref arg3 in r9 N010 ( 24, 15) [000342] --CXG------- t342 = * CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits $5c2 /--* t342 int N012 ( 24, 15) [000717] DA-XG------- * STORE_LCL_VAR int V51 tmp21 d:5 lowering store lcl var/field (before): N001 ( 3, 2) [000330] ------------ t330 = LCL_VAR int V20 loc17 u:2 (last use) $362 N002 ( 1, 1) [000331] ------------ t331 = LCL_VAR int V19 loc16 u:2 $248 /--* t330 int +--* t331 int N003 ( 5, 4) [000332] ------------ t332 = * SUB int $365 /--* t332 int N005 ( 9, 7) [000334] DA---------- * STORE_LCL_VAR int V21 loc18 d:4 lowering store lcl var/field (after): N001 ( 3, 2) [000330] ------------ t330 = LCL_VAR int V20 loc17 u:2 (last use) $362 N002 ( 1, 1) [000331] ------------ t331 = LCL_VAR int V19 loc16 u:2 $248 /--* t330 int +--* t331 int N003 ( 5, 4) [000332] ------------ t332 = * SUB int $365 /--* t332 int N005 ( 9, 7) [000334] DA---------- * STORE_LCL_VAR int V21 loc18 d:4 lowering store lcl var/field (before): N001 ( 0, 0) [000900] ------------ t900 = PHI_ARG int V21 loc18 u:4 $365 N002 ( 0, 0) [000888] ------------ t888 = PHI_ARG int V21 loc18 u:2 $362 /--* t900 int +--* t888 int N003 ( 0, 0) [000873] ------------ t873 = * PHI int /--* t873 int N005 ( 0, 0) [000874] DA---------- * STORE_LCL_VAR int V21 loc18 d:3 lowering store lcl var/field (after): N001 ( 0, 0) [000900] ------------ t900 = PHI_ARG int V21 loc18 u:4 $365 N002 ( 0, 0) [000888] ------------ t888 = PHI_ARG int V21 loc18 u:2 $362 /--* t900 int +--* t888 int N003 ( 0, 0) [000873] ------------ t873 = * PHI int /--* t873 int N005 ( 0, 0) [000874] DA---------- * STORE_LCL_VAR int V21 loc18 d:3 lowering store lcl var/field (before): N001 ( 3, 2) [000719] -------N---- t719 = LCL_VAR ref (AX) V56 tmp26 $186 /--* t719 ref N003 ( 7, 5) [000720] DA--G------- * STORE_LCL_VAR ref (AX) V68 tmp38 lowering store lcl var/field (after): N001 ( 3, 2) [000719] -------N---- t719 = LCL_VAR ref (AX) V56 tmp26 $186 /--* t719 ref N003 ( 7, 5) [000720] DA--G------- * STORE_LCL_VAR ref (AX) V68 tmp38 lowering store lcl var/field (before): N004 ( 3, 2) [000722] -------N---- t722 = LCL_VAR int (AX) V57 tmp27 $24a /--* t722 int N006 ( 7, 5) [000723] DA--G------- * STORE_LCL_VAR int (AX) V69 tmp39 lowering store lcl var/field (after): N004 ( 3, 2) [000722] -------N---- t722 = LCL_VAR int (AX) V57 tmp27 $24a /--* t722 int N006 ( 7, 5) [000723] DA--G------- * STORE_LCL_VAR int (AX) V69 tmp39 lowering store lcl var/field (before): N001 ( 3, 2) [000726] -------N---- t726 = LCL_VAR ref (AX) V58 tmp28 $187 /--* t726 ref N003 ( 7, 5) [000727] DA--G------- * STORE_LCL_VAR ref V70 tmp40 d:2 lowering store lcl var/field (after): N001 ( 3, 2) [000726] -------N---- t726 = LCL_VAR ref (AX) V58 tmp28 $187 /--* t726 ref N003 ( 7, 5) [000727] DA--G------- * STORE_LCL_VAR ref V70 tmp40 d:2 lowering store lcl var/field (before): N004 ( 3, 2) [000729] -------N---- t729 = LCL_VAR int (AX) V59 tmp29 $24b /--* t729 int N006 ( 7, 5) [000730] DA--G------- * STORE_LCL_VAR int V71 tmp41 d:2 lowering store lcl var/field (after): N004 ( 3, 2) [000729] -------N---- t729 = LCL_VAR int (AX) V59 tmp29 $24b /--* t729 int N006 ( 7, 5) [000730] DA--G------- * STORE_LCL_VAR int V71 tmp41 d:2 lowering store lcl var/field (before): N001 ( 3, 2) [000496] -------N---- t496 = LCL_VAR_ADDR byref V49 tmp19 * ref V49._bits (offs=0x00) -> V68 tmp38 * int V49._sign (offs=0x08) -> V69 tmp39 /--* t496 byref N004 ( 7, 6) [000752] DA--------L- * STORE_LCL_VAR byref V84 tmp54 d:2 lowering store lcl var/field (after): N001 ( 3, 2) [000496] -------N---- t496 = LCL_VAR_ADDR byref V49 tmp19 * ref V49._bits (offs=0x00) -> V68 tmp38 * int V49._sign (offs=0x08) -> V69 tmp39 /--* t496 byref N004 ( 7, 6) [000752] DA--------L- * STORE_LCL_VAR byref V84 tmp54 d:2 lowering store lcl var/field (before): N005 ( 3, 2) [000736] -------N---- t736 = LCL_VAR_ADDR byref V76 tmp46 /--* t736 byref N008 ( 3, 3) [000738] DA---------- * STORE_LCL_VAR byref V83 tmp53 d:2 lowering store lcl var/field (after): N005 ( 3, 2) [000736] -------N---- t736 = LCL_VAR_ADDR byref V76 tmp46 /--* t736 byref N008 ( 3, 3) [000738] DA---------- * STORE_LCL_VAR byref V83 tmp53 d:2 Lower of StoreInd didn't mark the node as self contained for reason: 4 N009 ( 1, 1) [000739] ------------ t739 = LCL_VAR byref V83 tmp53 u:2 Zero Fseq[_bits] $417 N011 ( 3, 2) [000741] -------N---- t741 = LCL_VAR ref V70 tmp40 u:2 (last use) $187 /--* t739 byref +--* t741 ref [000963] -A---------- * STOREIND ref Addressing mode: Base N014 ( 1, 1) [000744] ------------ * LCL_VAR byref V83 tmp53 u:2 (last use) $417 + 8 Removing unused node: N015 ( 1, 1) [000745] -c---------- * CNS_INT long 8 Fseq[_sign] $101 New addressing mode node: N016 ( 2, 2) [000746] ------------ * LEA(b+8) byref Lower of StoreInd didn't mark the node as self contained for reason: 4 N014 ( 1, 1) [000744] ------------ t744 = LCL_VAR byref V83 tmp53 u:2 (last use) $417 /--* t744 byref N016 ( 2, 2) [000746] ------------ t746 = * LEA(b+8) byref N018 ( 3, 2) [000748] -------N---- t748 = LCL_VAR int V71 tmp41 u:2 (last use) $24b /--* t746 byref +--* t748 int [000964] -A--------L- * STOREIND int lowering call (before): N001 ( 3, 2) [000496] -------N---- t496 = LCL_VAR_ADDR byref V49 tmp19 * ref V49._bits (offs=0x00) -> V68 tmp38 * int V49._sign (offs=0x08) -> V69 tmp39 /--* t496 byref N004 ( 7, 6) [000752] DA--------L- * STORE_LCL_VAR byref V84 tmp54 d:2 N005 ( 3, 2) [000736] -------N---- t736 = LCL_VAR_ADDR byref V76 tmp46 /--* t736 byref N008 ( 3, 3) [000738] DA---------- * STORE_LCL_VAR byref V83 tmp53 d:2 N009 ( 1, 1) [000739] ------------ t739 = LCL_VAR byref V83 tmp53 u:2 Zero Fseq[_bits] $417 N011 ( 3, 2) [000741] -------N---- t741 = LCL_VAR ref V70 tmp40 u:2 (last use) $187 /--* t739 byref +--* t741 ref [000963] -A---------- * STOREIND ref N014 ( 1, 1) [000744] ------------ t744 = LCL_VAR byref V83 tmp53 u:2 (last use) $417 /--* t744 byref N016 ( 2, 2) [000746] -c---------- t746 = * LEA(b+8) byref N018 ( 3, 2) [000748] -------N---- t748 = LCL_VAR int V71 tmp41 u:2 (last use) $24b /--* t746 byref +--* t748 int [000964] -A--------L- * STOREIND int N021 ( 3, 2) [000753] ------------ t753 = LCL_VAR byref V84 tmp54 u:2 (last use) $415 N022 ( 3, 2) [000754] -------N---- t754 = LCL_VAR_ADDR byref V76 tmp46 /--* t753 byref this in rcx +--* t754 byref arg1 in rdx N024 ( 48, 34) [000499] --CXG------- t499 = * CALL int System.Numerics.BigInteger.CompareTo $2ae objp: ====== lowering arg : N004 ( 7, 6) [000752] DA--------L- * STORE_LCL_VAR byref V84 tmp54 d:2 args: ====== lowering arg : [000964] -A--------L- * STOREIND int late: ====== lowering arg : N021 ( 3, 2) [000753] ------------ * LCL_VAR byref V84 tmp54 u:2 (last use) $415 new node is : [001061] ------------ * PUTARG_REG byref REG rcx lowering arg : N022 ( 3, 2) [000754] -------N---- * LCL_VAR_ADDR byref V76 tmp46 new node is : [001062] ------------ * PUTARG_REG byref REG rdx lowering call (after): N001 ( 3, 2) [000496] -------N---- t496 = LCL_VAR_ADDR byref V49 tmp19 * ref V49._bits (offs=0x00) -> V68 tmp38 * int V49._sign (offs=0x08) -> V69 tmp39 /--* t496 byref N004 ( 7, 6) [000752] DA--------L- * STORE_LCL_VAR byref V84 tmp54 d:2 N005 ( 3, 2) [000736] -------N---- t736 = LCL_VAR_ADDR byref V76 tmp46 /--* t736 byref N008 ( 3, 3) [000738] DA---------- * STORE_LCL_VAR byref V83 tmp53 d:2 N009 ( 1, 1) [000739] ------------ t739 = LCL_VAR byref V83 tmp53 u:2 Zero Fseq[_bits] $417 N011 ( 3, 2) [000741] -------N---- t741 = LCL_VAR ref V70 tmp40 u:2 (last use) $187 /--* t739 byref +--* t741 ref [000963] -A---------- * STOREIND ref N014 ( 1, 1) [000744] ------------ t744 = LCL_VAR byref V83 tmp53 u:2 (last use) $417 /--* t744 byref N016 ( 2, 2) [000746] -c---------- t746 = * LEA(b+8) byref N018 ( 3, 2) [000748] -------N---- t748 = LCL_VAR int V71 tmp41 u:2 (last use) $24b /--* t746 byref +--* t748 int [000964] -A--------L- * STOREIND int N021 ( 3, 2) [000753] ------------ t753 = LCL_VAR byref V84 tmp54 u:2 (last use) $415 /--* t753 byref [001061] ------------ t1061 = * PUTARG_REG byref REG rcx N022 ( 3, 2) [000754] -------N---- t754 = LCL_VAR_ADDR byref V76 tmp46 /--* t754 byref [001062] ------------ t1062 = * PUTARG_REG byref REG rdx /--* t1061 byref this in rcx +--* t1062 byref arg1 in rdx N024 ( 48, 34) [000499] --CXG------- t499 = * CALL int System.Numerics.BigInteger.CompareTo $2ae lowering store lcl var/field (before): N001 ( 1, 1) [000322] ------------ t322 = LCL_VAR int V19 loc16 u:2 (last use) $248 /--* t322 int N003 ( 5, 4) [000324] DA---------- * STORE_LCL_VAR int V34 tmp4 d:4 lowering store lcl var/field (after): N001 ( 1, 1) [000322] ------------ t322 = LCL_VAR int V19 loc16 u:2 (last use) $248 /--* t322 int N003 ( 5, 4) [000324] DA---------- * STORE_LCL_VAR int V34 tmp4 d:4 lowering store lcl var/field (before): N001 ( 1, 1) [000196] ------------ t196 = LCL_VAR int V19 loc16 u:2 (last use) $248 N002 ( 1, 1) [000197] -c---------- t197 = CNS_INT int 1 $41 /--* t196 int +--* t197 int N003 ( 3, 3) [000198] ------------ t198 = * ADD int $368 /--* t198 int N005 ( 7, 6) [000200] DA---------- * STORE_LCL_VAR int V34 tmp4 d:3 lowering store lcl var/field (after): N001 ( 1, 1) [000196] ------------ t196 = LCL_VAR int V19 loc16 u:2 (last use) $248 N002 ( 1, 1) [000197] -c---------- t197 = CNS_INT int 1 $41 /--* t196 int +--* t197 int N003 ( 3, 3) [000198] ------------ t198 = * ADD int $368 /--* t198 int N005 ( 7, 6) [000200] DA---------- * STORE_LCL_VAR int V34 tmp4 d:3 lowering store lcl var/field (before): N001 ( 0, 0) [000899] ------------ t899 = PHI_ARG int V34 tmp4 u:4 $248 N002 ( 0, 0) [000898] ------------ t898 = PHI_ARG int V34 tmp4 u:3 $368 /--* t899 int +--* t898 int N003 ( 0, 0) [000870] ------------ t870 = * PHI int /--* t870 int N005 ( 0, 0) [000871] DA---------- * STORE_LCL_VAR int V34 tmp4 d:2 lowering store lcl var/field (after): N001 ( 0, 0) [000899] ------------ t899 = PHI_ARG int V34 tmp4 u:4 $248 N002 ( 0, 0) [000898] ------------ t898 = PHI_ARG int V34 tmp4 u:3 $368 /--* t899 int +--* t898 int N003 ( 0, 0) [000870] ------------ t870 = * PHI int /--* t870 int N005 ( 0, 0) [000871] DA---------- * STORE_LCL_VAR int V34 tmp4 d:2 lowering store lcl var/field (before): N001 ( 3, 2) [000202] ------------ t202 = LCL_VAR int V34 tmp4 u:2 (last use) $24c /--* t202 int N003 ( 7, 5) [000204] DA---------- * STORE_LCL_VAR int V22 loc19 d:2 lowering store lcl var/field (after): N001 ( 3, 2) [000202] ------------ t202 = LCL_VAR int V34 tmp4 u:2 (last use) $24c /--* t202 int N003 ( 7, 5) [000204] DA---------- * STORE_LCL_VAR int V22 loc19 d:2 lowering call (before): N003 ( 3, 2) [000205] -------N---- t205 = LCL_VAR_ADDR byref V15 loc12 * ref V15._bits (offs=0x00) -> V56 tmp26 * int V15._sign (offs=0x08) -> V57 tmp27 N005 ( 3, 2) [000207] ------------ t207 = LCL_VAR int V21 loc18 u:3 (last use) $249 /--* t205 byref arg0 in rcx +--* t207 int arg1 in rdx N006 ( 20, 12) [000208] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft $VN.Void objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000756] ----------L- * ARGPLACE long $41a lowering arg : N002 ( 0, 0) [000757] ----------L- * ARGPLACE int $249 late: ====== lowering arg : N003 ( 3, 2) [000205] -------N---- * LCL_VAR_ADDR byref V15 loc12 * ref V15._bits (offs=0x00) -> V56 tmp26 * int V15._sign (offs=0x08) -> V57 tmp27 new node is : [001063] ------------ * PUTARG_REG byref REG rcx lowering arg : N005 ( 3, 2) [000207] ------------ * LCL_VAR int V21 loc18 u:3 (last use) $249 new node is : [001064] ------------ * PUTARG_REG int REG rdx lowering call (after): N003 ( 3, 2) [000205] -------N---- t205 = LCL_VAR_ADDR byref V15 loc12 * ref V15._bits (offs=0x00) -> V56 tmp26 * int V15._sign (offs=0x08) -> V57 tmp27 /--* t205 byref [001063] ------------ t1063 = * PUTARG_REG byref REG rcx N005 ( 3, 2) [000207] ------------ t207 = LCL_VAR int V21 loc18 u:3 (last use) $249 /--* t207 int [001064] ------------ t1064 = * PUTARG_REG int REG rdx /--* t1063 byref arg0 in rcx +--* t1064 int arg1 in rdx N006 ( 20, 12) [000208] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft $VN.Void lowering store lcl var/field (before): N001 ( 3, 2) [000219] -------N---- t219 = LCL_VAR_ADDR byref V35 tmp5 * ref V35._bits (offs=0x00) -> V62 tmp32 * int V35._sign (offs=0x08) -> V63 tmp33 /--* t219 byref N004 ( 7, 6) [000797] DA--------L- * STORE_LCL_VAR long V88 tmp58 d:2 lowering store lcl var/field (after): N001 ( 3, 2) [000219] -------N---- t219 = LCL_VAR_ADDR byref V35 tmp5 * ref V35._bits (offs=0x00) -> V62 tmp32 * int V35._sign (offs=0x08) -> V63 tmp33 /--* t219 byref N004 ( 7, 6) [000797] DA--------L- * STORE_LCL_VAR long V88 tmp58 d:2 lowering store lcl var/field (before): N005 ( 3, 2) [000762] -------N---- t762 = LCL_VAR_ADDR byref V76 tmp46 /--* t762 byref N008 ( 3, 3) [000764] DA---------- * STORE_LCL_VAR byref V85 tmp55 d:2 lowering store lcl var/field (after): N005 ( 3, 2) [000762] -------N---- t762 = LCL_VAR_ADDR byref V76 tmp46 /--* t762 byref N008 ( 3, 3) [000764] DA---------- * STORE_LCL_VAR byref V85 tmp55 d:2 Lower of StoreInd didn't mark the node as self contained for reason: 4 N009 ( 1, 1) [000765] ------------ t765 = LCL_VAR byref V85 tmp55 u:2 Zero Fseq[_bits] $41c N011 ( 3, 2) [000767] -------N---- t767 = LCL_VAR ref (AX) V56 tmp26 $188 /--* t765 byref +--* t767 ref [000969] -A--G------- * STOREIND ref Addressing mode: Base N014 ( 1, 1) [000770] ------------ * LCL_VAR byref V85 tmp55 u:2 (last use) $41c + 8 Removing unused node: N015 ( 1, 1) [000771] -c---------- * CNS_INT long 8 Fseq[_sign] $101 New addressing mode node: N016 ( 2, 2) [000772] ------------ * LEA(b+8) byref Lower of StoreInd didn't mark the node as self contained for reason: 4 N014 ( 1, 1) [000770] ------------ t770 = LCL_VAR byref V85 tmp55 u:2 (last use) $41c /--* t770 byref N016 ( 2, 2) [000772] ------------ t772 = * LEA(b+8) byref N018 ( 3, 2) [000774] -------N---- t774 = LCL_VAR int (AX) V57 tmp27 $24d /--* t772 byref +--* t774 int [000970] -A--G-----L- * STOREIND int lowering store lcl var/field (before): N021 ( 3, 2) [000781] -------N---- t781 = LCL_VAR_ADDR byref V86 tmp56 /--* t781 byref N024 ( 3, 3) [000783] DA---------- * STORE_LCL_VAR byref V87 tmp57 d:2 lowering store lcl var/field (after): N021 ( 3, 2) [000781] -------N---- t781 = LCL_VAR_ADDR byref V86 tmp56 /--* t781 byref N024 ( 3, 3) [000783] DA---------- * STORE_LCL_VAR byref V87 tmp57 d:2 Lower of StoreInd didn't mark the node as self contained for reason: 4 N025 ( 1, 1) [000784] ------------ t784 = LCL_VAR byref V87 tmp57 u:2 Zero Fseq[_bits] $41e N027 ( 3, 2) [000786] -------N---- t786 = LCL_VAR ref (AX) V58 tmp28 $189 /--* t784 byref +--* t786 ref [000971] -A--G------- * STOREIND ref Addressing mode: Base N030 ( 1, 1) [000789] ------------ * LCL_VAR byref V87 tmp57 u:2 (last use) $41e + 8 Removing unused node: N031 ( 1, 1) [000790] -c---------- * CNS_INT long 8 Fseq[_sign] $101 New addressing mode node: N032 ( 2, 2) [000791] ------------ * LEA(b+8) byref Lower of StoreInd didn't mark the node as self contained for reason: 4 N030 ( 1, 1) [000789] ------------ t789 = LCL_VAR byref V87 tmp57 u:2 (last use) $41e /--* t789 byref N032 ( 2, 2) [000791] ------------ t791 = * LEA(b+8) byref N034 ( 3, 2) [000793] -------N---- t793 = LCL_VAR int (AX) V59 tmp29 $24e /--* t791 byref +--* t793 int [000972] -A--G-----L- * STOREIND int lowering call (before): N001 ( 3, 2) [000219] -------N---- t219 = LCL_VAR_ADDR byref V35 tmp5 * ref V35._bits (offs=0x00) -> V62 tmp32 * int V35._sign (offs=0x08) -> V63 tmp33 /--* t219 byref N004 ( 7, 6) [000797] DA--------L- * STORE_LCL_VAR long V88 tmp58 d:2 N005 ( 3, 2) [000762] -------N---- t762 = LCL_VAR_ADDR byref V76 tmp46 /--* t762 byref N008 ( 3, 3) [000764] DA---------- * STORE_LCL_VAR byref V85 tmp55 d:2 N009 ( 1, 1) [000765] ------------ t765 = LCL_VAR byref V85 tmp55 u:2 Zero Fseq[_bits] $41c N011 ( 3, 2) [000767] -------N---- t767 = LCL_VAR ref (AX) V56 tmp26 $188 /--* t765 byref +--* t767 ref [000969] -A--G------- * STOREIND ref N014 ( 1, 1) [000770] ------------ t770 = LCL_VAR byref V85 tmp55 u:2 (last use) $41c /--* t770 byref N016 ( 2, 2) [000772] -c---------- t772 = * LEA(b+8) byref N018 ( 3, 2) [000774] -------N---- t774 = LCL_VAR int (AX) V57 tmp27 $24d /--* t772 byref +--* t774 int [000970] -A--G-----L- * STOREIND int N021 ( 3, 2) [000781] -------N---- t781 = LCL_VAR_ADDR byref V86 tmp56 /--* t781 byref N024 ( 3, 3) [000783] DA---------- * STORE_LCL_VAR byref V87 tmp57 d:2 N025 ( 1, 1) [000784] ------------ t784 = LCL_VAR byref V87 tmp57 u:2 Zero Fseq[_bits] $41e N027 ( 3, 2) [000786] -------N---- t786 = LCL_VAR ref (AX) V58 tmp28 $189 /--* t784 byref +--* t786 ref [000971] -A--G------- * STOREIND ref N030 ( 1, 1) [000789] ------------ t789 = LCL_VAR byref V87 tmp57 u:2 (last use) $41e /--* t789 byref N032 ( 2, 2) [000791] -c---------- t791 = * LEA(b+8) byref N034 ( 3, 2) [000793] -------N---- t793 = LCL_VAR int (AX) V59 tmp29 $24e /--* t791 byref +--* t793 int [000972] -A--G-----L- * STOREIND int N038 ( 3, 2) [000798] ------------ t798 = LCL_VAR long V88 tmp58 u:2 (last use) $41b N039 ( 3, 2) [000799] -------N---- t799 = LCL_VAR_ADDR byref V76 tmp46 N041 ( 3, 2) [000801] -------N---- t801 = LCL_VAR_ADDR byref V86 tmp56 N043 ( 3, 2) [000211] -------N---- t211 = LCL_VAR_ADDR byref V23 loc20 * ref V23._bits (offs=0x00) -> V60 tmp30 * int V23._sign (offs=0x08) -> V61 tmp31 /--* t798 long arg0 in rcx +--* t799 byref arg1 in rdx +--* t801 byref arg2 in r8 +--* t211 byref arg3 in r9 N045 ( 78, 56) [000213] S-CXG------- * CALL void System.Numerics.BigInteger.DivRem $VN.Void objp: ====== args: ====== lowering arg : N004 ( 7, 6) [000797] DA--------L- * STORE_LCL_VAR long V88 tmp58 d:2 lowering arg : [000970] -A--G-----L- * STOREIND int lowering arg : [000972] -A--G-----L- * STOREIND int lowering arg : N037 ( 0, 0) [000803] ----------L- * ARGPLACE long $422 late: ====== lowering arg : N038 ( 3, 2) [000798] ------------ * LCL_VAR long V88 tmp58 u:2 (last use) $41b new node is : [001065] ------------ * PUTARG_REG long REG rcx lowering arg : N039 ( 3, 2) [000799] -------N---- * LCL_VAR_ADDR byref V76 tmp46 new node is : [001066] ------------ * PUTARG_REG byref REG rdx lowering arg : N041 ( 3, 2) [000801] -------N---- * LCL_VAR_ADDR byref V86 tmp56 new node is : [001067] ------------ * PUTARG_REG byref REG r8 lowering arg : N043 ( 3, 2) [000211] -------N---- * LCL_VAR_ADDR byref V23 loc20 * ref V23._bits (offs=0x00) -> V60 tmp30 * int V23._sign (offs=0x08) -> V61 tmp31 new node is : [001068] ------------ * PUTARG_REG byref REG r9 lowering call (after): N001 ( 3, 2) [000219] -------N---- t219 = LCL_VAR_ADDR byref V35 tmp5 * ref V35._bits (offs=0x00) -> V62 tmp32 * int V35._sign (offs=0x08) -> V63 tmp33 /--* t219 byref N004 ( 7, 6) [000797] DA--------L- * STORE_LCL_VAR long V88 tmp58 d:2 N005 ( 3, 2) [000762] -------N---- t762 = LCL_VAR_ADDR byref V76 tmp46 /--* t762 byref N008 ( 3, 3) [000764] DA---------- * STORE_LCL_VAR byref V85 tmp55 d:2 N009 ( 1, 1) [000765] ------------ t765 = LCL_VAR byref V85 tmp55 u:2 Zero Fseq[_bits] $41c N011 ( 3, 2) [000767] -------N---- t767 = LCL_VAR ref (AX) V56 tmp26 $188 /--* t765 byref +--* t767 ref [000969] -A--G------- * STOREIND ref N014 ( 1, 1) [000770] ------------ t770 = LCL_VAR byref V85 tmp55 u:2 (last use) $41c /--* t770 byref N016 ( 2, 2) [000772] -c---------- t772 = * LEA(b+8) byref N018 ( 3, 2) [000774] -------N---- t774 = LCL_VAR int (AX) V57 tmp27 $24d /--* t772 byref +--* t774 int [000970] -A--G-----L- * STOREIND int N021 ( 3, 2) [000781] -------N---- t781 = LCL_VAR_ADDR byref V86 tmp56 /--* t781 byref N024 ( 3, 3) [000783] DA---------- * STORE_LCL_VAR byref V87 tmp57 d:2 N025 ( 1, 1) [000784] ------------ t784 = LCL_VAR byref V87 tmp57 u:2 Zero Fseq[_bits] $41e N027 ( 3, 2) [000786] -------N---- t786 = LCL_VAR ref (AX) V58 tmp28 $189 /--* t784 byref +--* t786 ref [000971] -A--G------- * STOREIND ref N030 ( 1, 1) [000789] ------------ t789 = LCL_VAR byref V87 tmp57 u:2 (last use) $41e /--* t789 byref N032 ( 2, 2) [000791] -c---------- t791 = * LEA(b+8) byref N034 ( 3, 2) [000793] -------N---- t793 = LCL_VAR int (AX) V59 tmp29 $24e /--* t791 byref +--* t793 int [000972] -A--G-----L- * STOREIND int N038 ( 3, 2) [000798] ------------ t798 = LCL_VAR long V88 tmp58 u:2 (last use) $41b /--* t798 long [001065] ------------ t1065 = * PUTARG_REG long REG rcx N039 ( 3, 2) [000799] -------N---- t799 = LCL_VAR_ADDR byref V76 tmp46 /--* t799 byref [001066] ------------ t1066 = * PUTARG_REG byref REG rdx N041 ( 3, 2) [000801] -------N---- t801 = LCL_VAR_ADDR byref V86 tmp56 /--* t801 byref [001067] ------------ t1067 = * PUTARG_REG byref REG r8 N043 ( 3, 2) [000211] -------N---- t211 = LCL_VAR_ADDR byref V23 loc20 * ref V23._bits (offs=0x00) -> V60 tmp30 * int V23._sign (offs=0x08) -> V61 tmp31 /--* t211 byref [001068] ------------ t1068 = * PUTARG_REG byref REG r9 /--* t1065 long arg0 in rcx +--* t1066 byref arg1 in rdx +--* t1067 byref arg2 in r8 +--* t1068 byref arg3 in r9 N045 ( 78, 56) [000213] S-CXG------- * CALL void System.Numerics.BigInteger.DivRem $VN.Void lowering store lcl var/field (before): N001 ( 3, 2) [000808] -------N---- t808 = LCL_VAR_ADDR byref V76 tmp46 /--* t808 byref N004 ( 3, 3) [000810] DA---------- * STORE_LCL_VAR byref V89 tmp59 d:2 lowering store lcl var/field (after): N001 ( 3, 2) [000808] -------N---- t808 = LCL_VAR_ADDR byref V76 tmp46 /--* t808 byref N004 ( 3, 3) [000810] DA---------- * STORE_LCL_VAR byref V89 tmp59 d:2 Lower of StoreInd didn't mark the node as self contained for reason: 4 N005 ( 1, 1) [000811] ------------ t811 = LCL_VAR byref V89 tmp59 u:2 Zero Fseq[_bits] $423 N007 ( 3, 2) [000813] -------N---- t813 = LCL_VAR ref (AX) V62 tmp32 $18a /--* t811 byref +--* t813 ref [000973] -A--G------- * STOREIND ref Addressing mode: Base N010 ( 1, 1) [000816] ------------ * LCL_VAR byref V89 tmp59 u:2 (last use) $423 + 8 Removing unused node: N011 ( 1, 1) [000817] -c---------- * CNS_INT long 8 Fseq[_sign] $101 New addressing mode node: N012 ( 2, 2) [000818] ------------ * LEA(b+8) byref Lower of StoreInd didn't mark the node as self contained for reason: 4 N010 ( 1, 1) [000816] ------------ t816 = LCL_VAR byref V89 tmp59 u:2 (last use) $423 /--* t816 byref N012 ( 2, 2) [000818] ------------ t818 = * LEA(b+8) byref N014 ( 3, 2) [000820] -------N---- t820 = LCL_VAR int (AX) V63 tmp33 $24f /--* t818 byref +--* t820 int [000974] -A--G-----L- * STOREIND int lowering call (before): N010 ( 1, 1) [000816] ------------ t816 = LCL_VAR byref V89 tmp59 u:2 (last use) $423 /--* t816 byref N012 ( 2, 2) [000818] -c---------- t818 = * LEA(b+8) byref N014 ( 3, 2) [000820] -------N---- t820 = LCL_VAR int (AX) V63 tmp33 $24f /--* t818 byref +--* t820 int [000974] -A--G-----L- * STOREIND int N017 ( 3, 2) [000823] -------N---- t823 = LCL_VAR_ADDR byref V76 tmp46 /--* t823 byref arg0 in rcx N019 ( 38, 24) [000218] --CXG------- t218 = * CALL long System.Numerics.BigInteger.op_Explicit $450 objp: ====== args: ====== lowering arg : [000974] -A--G-----L- * STOREIND int late: ====== lowering arg : N017 ( 3, 2) [000823] -------N---- * LCL_VAR_ADDR byref V76 tmp46 new node is : [001069] ------------ * PUTARG_REG byref REG rcx lowering call (after): N010 ( 1, 1) [000816] ------------ t816 = LCL_VAR byref V89 tmp59 u:2 (last use) $423 /--* t816 byref N012 ( 2, 2) [000818] -c---------- t818 = * LEA(b+8) byref N014 ( 3, 2) [000820] -------N---- t820 = LCL_VAR int (AX) V63 tmp33 $24f /--* t818 byref +--* t820 int [000974] -A--G-----L- * STOREIND int N017 ( 3, 2) [000823] -------N---- t823 = LCL_VAR_ADDR byref V76 tmp46 /--* t823 byref [001069] ------------ t1069 = * PUTARG_REG byref REG rcx /--* t1069 byref arg0 in rcx N019 ( 38, 24) [000218] --CXG------- t218 = * CALL long System.Numerics.BigInteger.op_Explicit $450 lowering store lcl var/field (before): N010 ( 1, 1) [000816] ------------ t816 = LCL_VAR byref V89 tmp59 u:2 (last use) $423 /--* t816 byref N012 ( 2, 2) [000818] -c---------- t818 = * LEA(b+8) byref N014 ( 3, 2) [000820] -------N---- t820 = LCL_VAR int (AX) V63 tmp33 $24f /--* t818 byref +--* t820 int [000974] -A--G-----L- * STOREIND int N017 ( 3, 2) [000823] -------N---- t823 = LCL_VAR_ADDR byref V76 tmp46 /--* t823 byref [001069] ------------ t1069 = * PUTARG_REG byref REG rcx /--* t1069 byref arg0 in rcx N019 ( 38, 24) [000218] --CXG------- t218 = * CALL long System.Numerics.BigInteger.op_Explicit $450 /--* t218 long N021 ( 38, 24) [000226] DA-XG------- * STORE_LCL_VAR long V24 loc21 d:2 lowering store lcl var/field (after): N010 ( 1, 1) [000816] ------------ t816 = LCL_VAR byref V89 tmp59 u:2 (last use) $423 /--* t816 byref N012 ( 2, 2) [000818] -c---------- t818 = * LEA(b+8) byref N014 ( 3, 2) [000820] -------N---- t820 = LCL_VAR int (AX) V63 tmp33 $24f /--* t818 byref +--* t820 int [000974] -A--G-----L- * STOREIND int N017 ( 3, 2) [000823] -------N---- t823 = LCL_VAR_ADDR byref V76 tmp46 /--* t823 byref [001069] ------------ t1069 = * PUTARG_REG byref REG rcx /--* t1069 byref arg0 in rcx N019 ( 38, 24) [000218] --CXG------- t218 = * CALL long System.Numerics.BigInteger.op_Explicit $450 /--* t218 long N021 ( 38, 24) [000226] DA-XG------- * STORE_LCL_VAR long V24 loc21 d:2 lowering store lcl var/field (before): N001 ( 3, 2) [000514] -c---------- t514 = LCL_VAR int (AX) V61 tmp31 $250 N002 ( 1, 1) [000515] -c---------- t515 = CNS_INT int 0 $40 /--* t514 int +--* t515 int N003 ( 8, 4) [000516] ----G------- t516 = * EQ int $369 /--* t516 int N005 ( 12, 7) [000232] DA--G------- * STORE_LCL_VAR int V25 loc22 d:2 lowering store lcl var/field (after): N001 ( 3, 2) [000514] -c---------- t514 = LCL_VAR int (AX) V61 tmp31 $250 N002 ( 1, 1) [000515] -c---------- t515 = CNS_INT int 0 $40 /--* t514 int +--* t515 int N003 ( 8, 4) [000516] ----G------- t516 = * EQ int $369 /--* t516 int N005 ( 12, 7) [000232] DA--G------- * STORE_LCL_VAR int V25 loc22 d:2 lowering call (before): N002 ( 1, 1) [000233] ------------ t233 = LCL_VAR long V24 loc21 u:2 $450 /--* t233 long arg0 in rcx N003 ( 15, 7) [000234] --CXG------- t234 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $2b4 objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000825] ----------L- * ARGPLACE long $450 late: ====== lowering arg : N002 ( 1, 1) [000233] ------------ * LCL_VAR long V24 loc21 u:2 $450 new node is : [001070] ------------ * PUTARG_REG long REG rcx lowering call (after): N002 ( 1, 1) [000233] ------------ t233 = LCL_VAR long V24 loc21 u:2 $450 /--* t233 long [001070] ------------ t1070 = * PUTARG_REG long REG rcx /--* t1070 long arg0 in rcx N003 ( 15, 7) [000234] --CXG------- t234 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $2b4 lowering store lcl var/field (before): N002 ( 1, 1) [000233] ------------ t233 = LCL_VAR long V24 loc21 u:2 $450 /--* t233 long [001070] ------------ t1070 = * PUTARG_REG long REG rcx /--* t1070 long arg0 in rcx N003 ( 15, 7) [000234] --CXG------- t234 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $2b4 /--* t234 int N005 ( 19, 10) [000237] DA-XG------- * STORE_LCL_VAR int V26 loc23 d:2 lowering store lcl var/field (after): N002 ( 1, 1) [000233] ------------ t233 = LCL_VAR long V24 loc21 u:2 $450 /--* t233 long [001070] ------------ t1070 = * PUTARG_REG long REG rcx /--* t1070 long arg0 in rcx N003 ( 15, 7) [000234] --CXG------- t234 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $2b4 /--* t234 int N005 ( 19, 10) [000237] DA-XG------- * STORE_LCL_VAR int V26 loc23 d:2 lowering store lcl var/field (before): N001 ( 3, 2) [000282] ------------ t282 = LCL_VAR int V26 loc23 u:2 (last use) $2b4 N002 ( 3, 2) [000283] ------------ t283 = LCL_VAR int V20 loc17 u:2 $362 /--* t282 int +--* t283 int N003 ( 7, 5) [000284] ------------ t284 = * SUB int $36b /--* t284 int N005 ( 11, 8) [000286] DA---------- * STORE_LCL_VAR int V29 loc26 d:2 lowering store lcl var/field (after): N001 ( 3, 2) [000282] ------------ t282 = LCL_VAR int V26 loc23 u:2 (last use) $2b4 N002 ( 3, 2) [000283] ------------ t283 = LCL_VAR int V20 loc17 u:2 $362 /--* t282 int +--* t283 int N003 ( 7, 5) [000284] ------------ t284 = * SUB int $36b /--* t284 int N005 ( 11, 8) [000286] DA---------- * STORE_LCL_VAR int V29 loc26 d:2 lowering store lcl var/field (before): N001 ( 1, 1) [000305] ------------ t305 = LCL_VAR long V24 loc21 u:2 $450 N002 ( 3, 2) [000308] ------------ t308 = LCL_VAR int V29 loc26 u:2 $36b N005 ( 1, 1) [000307] ------------ t307 = CNS_INT long 1 $103 /--* t307 long +--* t308 int N006 ( 10, 6) [000311] ------------ t311 = * LSH long $48e N007 ( 1, 1) [000313] -c---------- t313 = CNS_INT long -1 $104 /--* t311 long +--* t313 long N008 ( 12, 8) [000314] ------------ t314 = * ADD long $48f /--* t305 long +--* t314 long N011 ( 19, 12) [000318] ------------ t318 = * TEST_EQ int $36e /--* t318 int N013 ( 23, 15) [000320] DA---------- * STORE_LCL_VAR int V37 tmp7 d:4 lowering store lcl var/field (after): N001 ( 1, 1) [000305] ------------ t305 = LCL_VAR long V24 loc21 u:2 $450 N002 ( 3, 2) [000308] ------------ t308 = LCL_VAR int V29 loc26 u:2 $36b N005 ( 1, 1) [000307] ------------ t307 = CNS_INT long 1 $103 /--* t307 long +--* t308 int N006 ( 10, 6) [000311] ------------ t311 = * LSH long $48e N007 ( 1, 1) [000313] -c---------- t313 = CNS_INT long -1 $104 /--* t311 long +--* t313 long N008 ( 12, 8) [000314] ------------ t314 = * ADD long $48f /--* t305 long +--* t314 long N011 ( 19, 12) [000318] ------------ t318 = * TEST_EQ int $36e /--* t318 int N013 ( 23, 15) [000320] DA---------- * STORE_LCL_VAR int V37 tmp7 d:4 lowering store lcl var/field (before): N001 ( 1, 1) [000291] ------------ t291 = CNS_INT int 0 $40 /--* t291 int N003 ( 5, 4) [000293] DA---------- * STORE_LCL_VAR int V37 tmp7 d:3 lowering store lcl var/field (after): N001 ( 1, 1) [000291] ------------ t291 = CNS_INT int 0 $40 /--* t291 int N003 ( 5, 4) [000293] DA---------- * STORE_LCL_VAR int V37 tmp7 d:3 lowering store lcl var/field (before): N001 ( 0, 0) [000897] ------------ t897 = PHI_ARG int V37 tmp7 u:4 $36e N002 ( 0, 0) [000896] ------------ t896 = PHI_ARG int V37 tmp7 u:3 $40 /--* t897 int +--* t896 int N003 ( 0, 0) [000867] ------------ t867 = * PHI int /--* t867 int N005 ( 0, 0) [000868] DA---------- * STORE_LCL_VAR int V37 tmp7 d:2 lowering store lcl var/field (after): N001 ( 0, 0) [000897] ------------ t897 = PHI_ARG int V37 tmp7 u:4 $36e N002 ( 0, 0) [000896] ------------ t896 = PHI_ARG int V37 tmp7 u:3 $40 /--* t897 int +--* t896 int N003 ( 0, 0) [000867] ------------ t867 = * PHI int /--* t867 int N005 ( 0, 0) [000868] DA---------- * STORE_LCL_VAR int V37 tmp7 d:2 lowering store lcl var/field (before): N001 ( 3, 2) [000295] ------------ t295 = LCL_VAR int V37 tmp7 u:2 (last use) $251 /--* t295 int N002 ( 4, 4) [000826] ------------ t826 = * CAST int <- bool <- int $36f /--* t826 int N004 ( 8, 7) [000297] DA---------- * STORE_LCL_VAR int V25 loc22 d:4 lowering store lcl var/field (after): N001 ( 3, 2) [000295] ------------ t295 = LCL_VAR int V37 tmp7 u:2 (last use) $251 /--* t295 int N002 ( 4, 4) [000826] ------------ t826 = * CAST int <- bool <- int $36f /--* t826 int N004 ( 8, 7) [000297] DA---------- * STORE_LCL_VAR int V25 loc22 d:4 lowering store lcl var/field (before): N001 ( 1, 1) [000298] ------------ t298 = LCL_VAR long V24 loc21 u:2 (last use) $450 N002 ( 3, 2) [000299] ------------ t299 = LCL_VAR int V29 loc26 u:2 (last use) $36b /--* t298 long +--* t299 int N005 ( 10, 6) [000302] ------------ t302 = * RSZ long $491 /--* t302 long N007 ( 10, 6) [000304] DA---------- * STORE_LCL_VAR long V24 loc21 d:4 lowering store lcl var/field (after): N001 ( 1, 1) [000298] ------------ t298 = LCL_VAR long V24 loc21 u:2 (last use) $450 N002 ( 3, 2) [000299] ------------ t299 = LCL_VAR int V29 loc26 u:2 (last use) $36b /--* t298 long +--* t299 int N005 ( 10, 6) [000302] ------------ t302 = * RSZ long $491 /--* t302 long N007 ( 10, 6) [000304] DA---------- * STORE_LCL_VAR long V24 loc21 d:4 lowering store lcl var/field (before): N001 ( 0, 0) [000894] ------------ t894 = PHI_ARG bool V25 loc22 u:4 $36f N002 ( 0, 0) [000889] ------------ t889 = PHI_ARG bool V25 loc22 u:2 $369 /--* t894 bool +--* t889 bool N003 ( 0, 0) [000864] ------------ t864 = * PHI bool /--* t864 bool N005 ( 0, 0) [000865] DA---------- * STORE_LCL_VAR bool V25 loc22 d:3 lowering store lcl var/field (after): N001 ( 0, 0) [000894] ------------ t894 = PHI_ARG bool V25 loc22 u:4 $36f N002 ( 0, 0) [000889] ------------ t889 = PHI_ARG bool V25 loc22 u:2 $369 /--* t894 bool +--* t889 bool N003 ( 0, 0) [000864] ------------ t864 = * PHI bool /--* t864 bool N005 ( 0, 0) [000865] DA---------- * STORE_LCL_VAR bool V25 loc22 d:3 lowering store lcl var/field (before): N001 ( 0, 0) [000895] ------------ t895 = PHI_ARG long V24 loc21 u:4 $491 N002 ( 0, 0) [000890] ------------ t890 = PHI_ARG long V24 loc21 u:2 $450 /--* t895 long +--* t890 long N003 ( 0, 0) [000861] ------------ t861 = * PHI long /--* t861 long N005 ( 0, 0) [000862] DA---------- * STORE_LCL_VAR long V24 loc21 d:3 lowering store lcl var/field (after): N001 ( 0, 0) [000895] ------------ t895 = PHI_ARG long V24 loc21 u:4 $491 N002 ( 0, 0) [000890] ------------ t890 = PHI_ARG long V24 loc21 u:2 $450 /--* t895 long +--* t890 long N003 ( 0, 0) [000861] ------------ t861 = * PHI long /--* t861 long N005 ( 0, 0) [000862] DA---------- * STORE_LCL_VAR long V24 loc21 d:3 lowering store lcl var/field (before): N001 ( 3, 2) [000831] -------N---- t831 = LCL_VAR_ADDR byref V76 tmp46 /--* t831 byref N004 ( 3, 3) [000833] DA---------- * STORE_LCL_VAR byref V90 tmp60 d:2 lowering store lcl var/field (after): N001 ( 3, 2) [000831] -------N---- t831 = LCL_VAR_ADDR byref V76 tmp46 /--* t831 byref N004 ( 3, 3) [000833] DA---------- * STORE_LCL_VAR byref V90 tmp60 d:2 Lower of StoreInd didn't mark the node as self contained for reason: 4 N005 ( 1, 1) [000834] ------------ t834 = LCL_VAR byref V90 tmp60 u:2 Zero Fseq[_bits] $426 N007 ( 3, 2) [000836] -------N---- t836 = LCL_VAR ref (AX) V54 tmp24 $18b /--* t834 byref +--* t836 ref [000981] -A--G------- * STOREIND ref Addressing mode: Base N010 ( 1, 1) [000839] ------------ * LCL_VAR byref V90 tmp60 u:2 (last use) $426 + 8 Removing unused node: N011 ( 1, 1) [000840] -c---------- * CNS_INT long 8 Fseq[_sign] $101 New addressing mode node: N012 ( 2, 2) [000841] ------------ * LEA(b+8) byref Lower of StoreInd didn't mark the node as self contained for reason: 4 N010 ( 1, 1) [000839] ------------ t839 = LCL_VAR byref V90 tmp60 u:2 (last use) $426 /--* t839 byref N012 ( 2, 2) [000841] ------------ t841 = * LEA(b+8) byref N014 ( 3, 2) [000843] -------N---- t843 = LCL_VAR int (AX) V55 tmp25 $252 /--* t841 byref +--* t843 int [000982] -A--G-----L- * STOREIND int lowering call (before): N010 ( 1, 1) [000839] ------------ t839 = LCL_VAR byref V90 tmp60 u:2 (last use) $426 /--* t839 byref N012 ( 2, 2) [000841] -c---------- t841 = * LEA(b+8) byref N014 ( 3, 2) [000843] -------N---- t843 = LCL_VAR int (AX) V55 tmp25 $252 /--* t841 byref +--* t843 int [000982] -A--G-----L- * STOREIND int N017 ( 3, 2) [000846] -------N---- t846 = LCL_VAR_ADDR byref V76 tmp46 /--* t846 byref arg0 in rcx N019 ( 38, 24) [000243] --CXG------- t243 = * CALL long System.Numerics.BigInteger.op_Explicit $454 objp: ====== args: ====== lowering arg : [000982] -A--G-----L- * STOREIND int late: ====== lowering arg : N017 ( 3, 2) [000846] -------N---- * LCL_VAR_ADDR byref V76 tmp46 new node is : [001071] ------------ * PUTARG_REG byref REG rcx lowering call (after): N010 ( 1, 1) [000839] ------------ t839 = LCL_VAR byref V90 tmp60 u:2 (last use) $426 /--* t839 byref N012 ( 2, 2) [000841] -c---------- t841 = * LEA(b+8) byref N014 ( 3, 2) [000843] -------N---- t843 = LCL_VAR int (AX) V55 tmp25 $252 /--* t841 byref +--* t843 int [000982] -A--G-----L- * STOREIND int N017 ( 3, 2) [000846] -------N---- t846 = LCL_VAR_ADDR byref V76 tmp46 /--* t846 byref [001071] ------------ t1071 = * PUTARG_REG byref REG rcx /--* t1071 byref arg0 in rcx N019 ( 38, 24) [000243] --CXG------- t243 = * CALL long System.Numerics.BigInteger.op_Explicit $454 lowering store lcl var/field (before): N010 ( 1, 1) [000839] ------------ t839 = LCL_VAR byref V90 tmp60 u:2 (last use) $426 /--* t839 byref N012 ( 2, 2) [000841] -c---------- t841 = * LEA(b+8) byref N014 ( 3, 2) [000843] -------N---- t843 = LCL_VAR int (AX) V55 tmp25 $252 /--* t841 byref +--* t843 int [000982] -A--G-----L- * STOREIND int N017 ( 3, 2) [000846] -------N---- t846 = LCL_VAR_ADDR byref V76 tmp46 /--* t846 byref [001071] ------------ t1071 = * PUTARG_REG byref REG rcx /--* t1071 byref arg0 in rcx N019 ( 38, 24) [000243] --CXG------- t243 = * CALL long System.Numerics.BigInteger.op_Explicit $454 N020 ( 3, 2) [000247] ------------ t247 = LCL_VAR int V20 loc17 u:2 (last use) $362 /--* t243 long +--* t247 int N023 ( 47, 29) [000250] ---XG------- t250 = * LSH long $492 N024 ( 1, 1) [000251] ------------ t251 = LCL_VAR long V24 loc21 u:3 (last use) $580 /--* t250 long +--* t251 long N025 ( 49, 31) [000252] ---XG------- t252 = * ADD long $493 /--* t252 long N027 ( 53, 34) [000254] DA-XG------- * STORE_LCL_VAR long V27 loc24 d:2 lowering store lcl var/field (after): N010 ( 1, 1) [000839] ------------ t839 = LCL_VAR byref V90 tmp60 u:2 (last use) $426 /--* t839 byref N012 ( 2, 2) [000841] -c---------- t841 = * LEA(b+8) byref N014 ( 3, 2) [000843] -------N---- t843 = LCL_VAR int (AX) V55 tmp25 $252 /--* t841 byref +--* t843 int [000982] -A--G-----L- * STOREIND int N017 ( 3, 2) [000846] -------N---- t846 = LCL_VAR_ADDR byref V76 tmp46 /--* t846 byref [001071] ------------ t1071 = * PUTARG_REG byref REG rcx /--* t1071 byref arg0 in rcx N019 ( 38, 24) [000243] --CXG------- t243 = * CALL long System.Numerics.BigInteger.op_Explicit $454 N020 ( 3, 2) [000247] ------------ t247 = LCL_VAR int V20 loc17 u:2 (last use) $362 /--* t243 long +--* t247 int N023 ( 47, 29) [000250] ---XG------- t250 = * LSH long $492 N024 ( 1, 1) [000251] ------------ t251 = LCL_VAR long V24 loc21 u:3 (last use) $580 /--* t250 long +--* t251 long N025 ( 49, 31) [000252] ---XG------- t252 = * ADD long $493 /--* t252 long N027 ( 53, 34) [000254] DA-XG------- * STORE_LCL_VAR long V27 loc24 d:2 lowering store lcl var/field (before): N001 ( 3, 2) [000275] ------------ t275 = LCL_VAR int V22 loc19 u:2 (last use) $24c /--* t275 int N002 ( 4, 3) [000276] ------------ t276 = * NEG int $2c2 N003 ( 1, 1) [000277] -c---------- t277 = CNS_INT int -1 $43 /--* t276 int +--* t277 int N004 ( 6, 5) [000278] ------------ t278 = * ADD int $372 /--* t278 int N006 ( 10, 8) [000280] DA---------- * STORE_LCL_VAR int V36 tmp6 d:4 lowering store lcl var/field (after): N001 ( 3, 2) [000275] ------------ t275 = LCL_VAR int V22 loc19 u:2 (last use) $24c /--* t275 int N002 ( 4, 3) [000276] ------------ t276 = * NEG int $2c2 N003 ( 1, 1) [000277] -c---------- t277 = CNS_INT int -1 $43 /--* t276 int +--* t277 int N004 ( 6, 5) [000278] ------------ t278 = * ADD int $372 /--* t278 int N006 ( 10, 8) [000280] DA---------- * STORE_LCL_VAR int V36 tmp6 d:4 lowering store lcl var/field (before): N001 ( 1, 1) [000259] ------------ t259 = LCL_VAR int V13 loc10 u:2 (last use) $293 N002 ( 1, 1) [000260] -c---------- t260 = CNS_INT int -2 $68 /--* t259 int +--* t260 int N003 ( 3, 3) [000261] ------------ t261 = * ADD int $371 /--* t261 int N005 ( 7, 6) [000263] DA---------- * STORE_LCL_VAR int V36 tmp6 d:3 lowering store lcl var/field (after): N001 ( 1, 1) [000259] ------------ t259 = LCL_VAR int V13 loc10 u:2 (last use) $293 N002 ( 1, 1) [000260] -c---------- t260 = CNS_INT int -2 $68 /--* t259 int +--* t260 int N003 ( 3, 3) [000261] ------------ t261 = * ADD int $371 /--* t261 int N005 ( 7, 6) [000263] DA---------- * STORE_LCL_VAR int V36 tmp6 d:3 lowering store lcl var/field (before): N001 ( 0, 0) [000893] ------------ t893 = PHI_ARG int V36 tmp6 u:4 $372 N002 ( 0, 0) [000892] ------------ t892 = PHI_ARG int V36 tmp6 u:3 $371 /--* t893 int +--* t892 int N003 ( 0, 0) [000858] ------------ t858 = * PHI int /--* t858 int N005 ( 0, 0) [000859] DA---------- * STORE_LCL_VAR int V36 tmp6 d:2 lowering store lcl var/field (after): N001 ( 0, 0) [000893] ------------ t893 = PHI_ARG int V36 tmp6 u:4 $372 N002 ( 0, 0) [000892] ------------ t892 = PHI_ARG int V36 tmp6 u:3 $371 /--* t893 int +--* t892 int N003 ( 0, 0) [000858] ------------ t858 = * PHI int /--* t858 int N005 ( 0, 0) [000859] DA---------- * STORE_LCL_VAR int V36 tmp6 d:2 lowering call (before): N005 ( 1, 1) [000272] ------------ t272 = LCL_VAR byref V02 arg2 u:1 (last use) $81 N006 ( 1, 1) [000268] ------------ t268 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 N007 ( 3, 2) [000269] ------------ t269 = LCL_VAR long V27 loc24 u:2 (last use) $493 N008 ( 3, 2) [000270] ------------ t270 = LCL_VAR int V36 tmp6 u:2 (last use) $253 N009 ( 3, 2) [000271] ------------ t271 = LCL_VAR int V25 loc22 u:3 (last use) $540 /--* t272 byref arg4 out+20 +--* t268 ref this in rcx +--* t269 long arg1 in rdx +--* t270 int arg2 in r8 +--* t271 int arg3 in r9 N010 ( 28, 18) [000273] --CXG------- t273 = * CALL int FloatingPointType.AssembleFloatingPointValue $2be objp: ====== lowering arg : N001 ( 0, 0) [000848] ----------L- * ARGPLACE ref $1ef args: ====== lowering arg : N002 ( 0, 0) [000849] ----------L- * ARGPLACE long $c0 lowering arg : N003 ( 0, 0) [000850] ----------L- * ARGPLACE int $493 lowering arg : N004 ( 0, 0) [000851] ----------L- * ARGPLACE int $253 lowering arg : N005 ( 1, 1) [000272] ------------ * LCL_VAR byref V02 arg2 u:1 (last use) $81 new node is : [001072] ------------ * PUTARG_STK [+0x20] void late: ====== lowering arg : N006 ( 1, 1) [000268] ------------ * LCL_VAR ref V01 arg1 u:1 (last use) $c0 new node is : [001073] ------------ * PUTARG_REG ref REG rcx lowering arg : N007 ( 3, 2) [000269] ------------ * LCL_VAR long V27 loc24 u:2 (last use) $493 new node is : [001074] ------------ * PUTARG_REG long REG rdx lowering arg : N008 ( 3, 2) [000270] ------------ * LCL_VAR int V36 tmp6 u:2 (last use) $253 new node is : [001075] ------------ * PUTARG_REG int REG r8 lowering arg : N009 ( 3, 2) [000271] ------------ * LCL_VAR int V25 loc22 u:3 (last use) $540 new node is : [001076] ------------ * PUTARG_REG int REG r9 lowering call (after): N005 ( 1, 1) [000272] ------------ t272 = LCL_VAR byref V02 arg2 u:1 (last use) $81 /--* t272 byref [001072] ------------ * PUTARG_STK [+0x20] void N006 ( 1, 1) [000268] ------------ t268 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t268 ref [001073] ------------ t1073 = * PUTARG_REG ref REG rcx N007 ( 3, 2) [000269] ------------ t269 = LCL_VAR long V27 loc24 u:2 (last use) $493 /--* t269 long [001074] ------------ t1074 = * PUTARG_REG long REG rdx N008 ( 3, 2) [000270] ------------ t270 = LCL_VAR int V36 tmp6 u:2 (last use) $253 /--* t270 int [001075] ------------ t1075 = * PUTARG_REG int REG r8 N009 ( 3, 2) [000271] ------------ t271 = LCL_VAR int V25 loc22 u:3 (last use) $540 /--* t271 int [001076] ------------ t1076 = * PUTARG_REG int REG r9 /--* t1073 ref this in rcx +--* t1074 long arg1 in rdx +--* t1075 int arg2 in r8 +--* t1076 int arg3 in r9 N010 ( 28, 18) [000273] --CXG------- t273 = * CALL int FloatingPointType.AssembleFloatingPointValue $2be lowering store lcl var/field (before): N005 ( 1, 1) [000272] ------------ t272 = LCL_VAR byref V02 arg2 u:1 (last use) $81 /--* t272 byref [001072] ------------ * PUTARG_STK [+0x20] void N006 ( 1, 1) [000268] ------------ t268 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t268 ref [001073] ------------ t1073 = * PUTARG_REG ref REG rcx N007 ( 3, 2) [000269] ------------ t269 = LCL_VAR long V27 loc24 u:2 (last use) $493 /--* t269 long [001074] ------------ t1074 = * PUTARG_REG long REG rdx N008 ( 3, 2) [000270] ------------ t270 = LCL_VAR int V36 tmp6 u:2 (last use) $253 /--* t270 int [001075] ------------ t1075 = * PUTARG_REG int REG r8 N009 ( 3, 2) [000271] ------------ t271 = LCL_VAR int V25 loc22 u:3 (last use) $540 /--* t271 int [001076] ------------ t1076 = * PUTARG_REG int REG r9 /--* t1073 ref this in rcx +--* t1074 long arg1 in rdx +--* t1075 int arg2 in r8 +--* t1076 int arg3 in r9 N010 ( 28, 18) [000273] --CXG------- t273 = * CALL int FloatingPointType.AssembleFloatingPointValue $2be /--* t273 int N012 ( 28, 18) [000853] DA-XG------- * STORE_LCL_VAR int V51 tmp21 d:4 lowering store lcl var/field (after): N005 ( 1, 1) [000272] ------------ t272 = LCL_VAR byref V02 arg2 u:1 (last use) $81 /--* t272 byref [001072] ------------ * PUTARG_STK [+0x20] void N006 ( 1, 1) [000268] ------------ t268 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t268 ref [001073] ------------ t1073 = * PUTARG_REG ref REG rcx N007 ( 3, 2) [000269] ------------ t269 = LCL_VAR long V27 loc24 u:2 (last use) $493 /--* t269 long [001074] ------------ t1074 = * PUTARG_REG long REG rdx N008 ( 3, 2) [000270] ------------ t270 = LCL_VAR int V36 tmp6 u:2 (last use) $253 /--* t270 int [001075] ------------ t1075 = * PUTARG_REG int REG r8 N009 ( 3, 2) [000271] ------------ t271 = LCL_VAR int V25 loc22 u:3 (last use) $540 /--* t271 int [001076] ------------ t1076 = * PUTARG_REG int REG r9 /--* t1073 ref this in rcx +--* t1074 long arg1 in rdx +--* t1075 int arg2 in r8 +--* t1076 int arg3 in r9 N010 ( 28, 18) [000273] --CXG------- t273 = * CALL int FloatingPointType.AssembleFloatingPointValue $2be /--* t273 int N012 ( 28, 18) [000853] DA-XG------- * STORE_LCL_VAR int V51 tmp21 d:4 lowering store lcl var/field (before): N001 ( 0, 0) [000901] ------------ t901 = PHI_ARG int V51 tmp21 u:5 $5c2 N002 ( 0, 0) [000891] ------------ t891 = PHI_ARG int V51 tmp21 u:4 $2be N003 ( 0, 0) [000887] ------------ t887 = PHI_ARG int V51 tmp21 u:3 $5c7 /--* t901 int +--* t891 int +--* t887 int N004 ( 0, 0) [000855] ------------ t855 = * PHI int /--* t855 int N006 ( 0, 0) [000856] DA---------- * STORE_LCL_VAR int V51 tmp21 d:2 lowering store lcl var/field (after): N001 ( 0, 0) [000901] ------------ t901 = PHI_ARG int V51 tmp21 u:5 $5c2 N002 ( 0, 0) [000891] ------------ t891 = PHI_ARG int V51 tmp21 u:4 $2be N003 ( 0, 0) [000887] ------------ t887 = PHI_ARG int V51 tmp21 u:3 $5c7 /--* t901 int +--* t891 int +--* t887 int N004 ( 0, 0) [000855] ------------ t855 = * PHI int /--* t855 int N006 ( 0, 0) [000856] DA---------- * STORE_LCL_VAR int V51 tmp21 d:2 lowering GT_RETURN N002 ( 2, 2) [000523] ------------ * RETURN int $5c9 ============Lower has completed modifying nodes. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0056] 1 1 [???..???) i internal label target LIR BB02 [0000] 1 BB01 1 [000..00D)-> BB04 ( cond ) i label target idxlen LIR BB03 [0001] 1 BB02 0.50 [00D..017) (return) i hascall gcsafe LIR BB04 [0002] 1 BB02 0.50 [017..065)-> BB06 ( cond ) i label target hascall gcsafe LIR BB05 [0038] 1 BB04 0.50 [020..021)-> BB07 (always) i gcsafe LIR BB06 [0039] 1 BB04 0.50 [020..021) i label target gcsafe LIR BB07 [0040] 2 BB05,BB06 0.50 [000..000)-> BB09 ( cond ) i internal label target gcsafe idxlen LIR BB08 [0043] 1 BB07 0.50 [000..000)-> BB10 (always) i internal gcsafe LIR BB09 [0044] 1 BB07 0.50 [000..000) i internal label target gcsafe LIR BB10 [0045] 2 BB08,BB09 0.50 [???..???)-> BB14 ( cond ) i internal label target hascall gcsafe idxlen LIR BB11 [0003] 1 BB10 0.50 [065..070)-> BB13 ( cond ) i hascall gcsafe LIR BB12 [0004] 1 BB11 0.50 [070..07A) (return) i hascall gcsafe LIR BB13 [0005] 1 BB11 0.50 [07A..082) i label target hascall gcsafe LIR BB14 [0006] 2 BB10,BB13 0.50 [082..092)-> BB16 ( cond ) i label target hascall gcsafe LIR BB15 [0007] 1 BB14 0.50 [092..096)-> BB17 ( cond ) i gcsafe LIR BB16 [0008] 2 BB14,BB15 0.50 [096..0A7)-> BB44 (always) i label target hascall gcsafe LIR BB17 [0009] 1 BB15 0.50 [0A7..0B0)-> BB19 ( cond ) i label target gcsafe LIR BB18 [0010] 1 BB17 0.50 [0B0..0B4)-> BB20 (always) i gcsafe LIR BB19 [0011] 1 BB17 0.50 [0B4..0BE) i label target gcsafe LIR BB20 [0012] 2 BB18,BB19 0.50 [0BE..0C4)-> BB23 ( cond ) i label target gcsafe LIR BB21 [0013] 1 BB20 0.50 [0C4..0D9)-> BB23 ( cond ) i hascall gcsafe idxlen LIR BB22 [0014] 1 BB21 0.50 [0D9..0E3) (return) i hascall gcsafe LIR BB23 [0015] 2 BB20,BB21 0.50 [0E3..117)-> BB25 ( cond ) i label target hascall gcsafe LIR BB24 [0016] 1 BB23 0.50 [117..11A)-> BB26 (always) i gcsafe LIR BB25 [0017] 1 BB23 0.50 [11A..11F) i label target gcsafe LIR BB26 [0018] 2 BB24,BB25 0.50 [11F..126)-> BB28 ( cond ) i label target gcsafe LIR BB27 [0019] 1 BB26 0.50 [126..12F) i hascall gcsafe LIR BB28 [0020] 2 BB26,BB27 0.50 [12F..13E)-> BB32 ( cond ) i label target gcsafe LIR BB29 [0021] 1 BB28 0.50 [13E..144)-> BB31 ( cond ) i gcsafe LIR BB30 [0022] 1 BB29 0.50 [144..155)-> BB44 (always) i hascall gcsafe LIR BB31 [0023] 1 BB29 0.50 [155..15C) i label target gcsafe LIR BB32 [0024] 2 BB28,BB31 0.50 [15C..167)-> BB34 ( cond ) i label target hascall gcsafe LIR BB33 [0025] 1 BB32 0.50 [167..16B)-> BB35 (always) i gcsafe LIR BB34 [0026] 1 BB32 0.50 [16B..16F) i label target gcsafe LIR BB35 [0027] 2 BB33,BB34 0.50 [16F..1A4)-> BB40 ( cond ) i label target hascall gcsafe LIR BB36 [0028] 1 BB35 0.50 [1A4..1AF)-> BB38 ( cond ) i gcsafe LIR BB37 [0029] 1 BB36 0.50 [1AF..1C3)-> BB39 (always) i gcsafe LIR BB38 [0030] 1 BB36 0.50 [1C3..1C4) i label target gcsafe LIR BB39 [0031] 2 BB37,BB38 0.50 [1C4..1D0) i label target gcsafe LIR BB40 [0032] 2 BB35,BB39 0.50 [1D0..1E7)-> BB42 ( cond ) i label target hascall gcsafe LIR BB41 [0033] 1 BB40 0.50 [1E7..1EE)-> BB43 (always) i gcsafe LIR BB42 [0034] 1 BB40 0.50 [1EE..1F2) i label target gcsafe LIR BB43 [0035] 2 BB41,BB42 0.50 [1F2..202) i label target hascall gcsafe LIR BB44 [0054] 3 BB16,BB30,BB43 0.50 [???..???) (return) keep internal target gcsafe LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} N001 ( 1, 1) [000531] ------------ t531 = LCL_VAR byref V00 arg0 u:1 Zero Fseq[Mantissa] $80 /--* t531 byref N002 ( 3, 2) [000532] n----------- t532 = * IND ref /--* t532 ref N004 ( 3, 3) [000533] DA---------- * STORE_LCL_VAR ref V52 tmp22 d:2 N005 ( 1, 1) [000535] ------------ t535 = LCL_VAR byref V00 arg0 u:1 (last use) $80 /--* t535 byref N007 ( 2, 2) [000537] -c---------- t537 = * LEA(b+8) byref /--* t537 byref N008 ( 4, 4) [000538] n----------- t538 = * IND int /--* t538 int N010 ( 4, 4) [000539] DA---------- * STORE_LCL_VAR int V53 tmp23 d:2 ------------ BB02 [000..00D) -> BB04 (cond), preds={BB01} succs={BB03,BB04} [000910] ------------ IL_OFFSET void IL offset: 0x0 N001 ( 1, 1) [000002] ------------ t2 = LCL_VAR ref V52 tmp22 u:2 /--* t2 ref [000988] -c---------- t988 = * LEA(b+8) ref /--* t988 ref N002 ( 3, 3) [000003] -c-XG------- t3 = * IND int N003 ( 1, 1) [000004] -c---------- t4 = CNS_INT int 0 $40 /--* t3 int +--* t4 int N004 ( 5, 5) [000005] J--XG--N---- * NE void N005 ( 7, 7) [000006] ---XG------- * JTRUE void ------------ BB03 [00D..017) (return), preds={BB02} succs={} [000911] ------------ IL_OFFSET void IL offset: 0xd N002 ( 1, 1) [000400] ------------ t400 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t400 ref [000995] ------------ t995 = * PUTARG_REG ref REG rcx N001 ( 1, 1) [000996] ------------ t996 = LCL_VAR ref V01 arg1 /--* t996 ref N002 ( 2, 2) [000997] -c---------- t997 = * LEA(b+0) byref /--* t997 byref N003 ( 5, 4) [000998] ------------ t998 = * IND long /--* t998 long N004 ( 6, 5) [000999] -c---------- t999 = * LEA(b+80) long /--* t999 long N005 ( 9, 7) [001000] ------------ t1000 = * IND long /--* t1000 long N006 ( 10, 8) [001001] -c---------- t1001 = * LEA(b+0) long /--* t1001 long N007 ( 13, 10) [001002] -c---------- t1002 = * IND long REG NA /--* t995 ref this in rcx +--* t1002 long control expr N003 ( 21, 10) [000401] --CXG------- t401 = * CALLV ind long FloatingPointType.get_Zero $459 N004 ( 1, 1) [000399] ------------ t399 = LCL_VAR byref V02 arg2 u:1 (last use) $81 /--* t399 byref +--* t401 long [000912] -ACXG------- * STOREIND long N001 ( 1, 1) [000404] ------------ t404 = CNS_INT int 1 $41 /--* t404 int N002 ( 2, 2) [000520] ------------ * RETURN int $5cb ------------ BB04 [017..065) -> BB06 (cond), preds={BB02} succs={BB05,BB06} N002 ( 1, 1) [000007] ------------ t7 = LCL_VAR ref V01 arg1 u:1 $c0 /--* t7 ref [001003] ------------ t1003 = * PUTARG_REG ref REG rcx N001 ( 1, 1) [001004] ------------ t1004 = LCL_VAR ref V01 arg1 /--* t1004 ref N002 ( 2, 2) [001005] -c---------- t1005 = * LEA(b+0) byref /--* t1005 byref N003 ( 5, 4) [001006] ------------ t1006 = * IND long /--* t1006 long N004 ( 6, 5) [001007] -c---------- t1007 = * LEA(b+72) long /--* t1007 long N005 ( 9, 7) [001008] ------------ t1008 = * IND long /--* t1008 long N006 ( 10, 8) [001009] -c---------- t1009 = * LEA(b+32) long /--* t1009 long N007 ( 13, 10) [001010] -c---------- t1010 = * IND long REG NA /--* t1003 ref this in rcx +--* t1010 long control expr N003 ( 21, 10) [000406] --CXG------- t406 = * CALLV ind int FloatingPointType.get_DenormalMantissaBits $282 N004 ( 1, 1) [000407] -c---------- t407 = CNS_INT int 1 $41 /--* t406 int +--* t407 int N005 ( 23, 12) [000408] ---XG------- t408 = * ADD int $346 /--* t408 int N006 ( 24, 14) [000409] ---XG------- t409 = * CAST int <- ushort <- int $347 N007 ( 1, 1) [000010] -c---------- t10 = CNS_INT int 1 $41 /--* t409 int +--* t10 int N008 ( 26, 16) [000011] ---XG------- t11 = * ADD int $348 /--* t11 int N010 ( 30, 19) [000013] DA-XG------- * STORE_LCL_VAR int V03 loc0 d:2 [000913] ------------ IL_OFFSET void IL offset: 0x20 N001 ( 1, 1) [000017] ------------ t17 = LCL_VAR int V53 tmp23 u:2 /--* t17 int N003 ( 5, 4) [000424] DA--G------- * STORE_LCL_VAR int V40 tmp10 d:2 [000914] ------------ IL_OFFSET void IL offset: 0x20 N001 ( 1, 1) [000412] ------------ t412 = LCL_VAR int V40 tmp10 u:2 N002 ( 1, 1) [000411] -c---------- t411 = CNS_INT int 0 $40 /--* t412 int +--* t411 int N003 ( 3, 3) [000413] J------N---- * LE void N004 ( 5, 5) [000414] ------------ * JTRUE void ------------ BB05 [020..021) -> BB07 (always), preds={BB04} succs={BB07} [000915] ------------ IL_OFFSET void IL offset: 0x20 N001 ( 3, 2) [000419] ------------ t419 = LCL_VAR int V53 tmp23 u:2 (last use) /--* t419 int N003 ( 7, 5) [000421] DA---------- * STORE_LCL_VAR int V39 tmp9 d:4 ------------ BB06 [020..021), preds={BB04} succs={BB07} [000916] ------------ IL_OFFSET void IL offset: 0x20 N001 ( 1, 1) [000415] ------------ t415 = CNS_INT int 0 $40 /--* t415 int N003 ( 5, 4) [000417] DA---------- * STORE_LCL_VAR int V39 tmp9 d:3 ------------ BB07 [000..000) -> BB09 (cond), preds={BB05,BB06} succs={BB08,BB09} N001 ( 0, 0) [000909] ------------ t909 = PHI_ARG int V39 tmp9 u:4 N002 ( 0, 0) [000908] ------------ t908 = PHI_ARG int V39 tmp9 u:3 $40 /--* t909 int +--* t908 int N003 ( 0, 0) [000885] ------------ t885 = * PHI int /--* t885 int N005 ( 0, 0) [000886] DA---------- * STORE_LCL_VAR int V39 tmp9 d:2 N001 ( 3, 2) [000422] ------------ t422 = LCL_VAR int V39 tmp9 u:2 $241 /--* t422 int N003 ( 3, 3) [000021] DA---------- * STORE_LCL_VAR int V31 tmp1 d:2 N001 ( 1, 1) [000428] ------------ t428 = LCL_VAR ref V52 tmp22 u:2 /--* t428 ref [000990] -c---------- t990 = * LEA(b+8) ref /--* t990 ref N002 ( 3, 3) [000429] ---XG------- t429 = * IND int /--* t429 int N004 ( 3, 3) [000443] DA-XG------- * STORE_LCL_VAR int V42 tmp12 d:2 N001 ( 3, 2) [000023] ------------ t23 = LCL_VAR int V31 tmp1 u:2 (last use) $241 N002 ( 1, 1) [000431] ------------ t431 = LCL_VAR int V42 tmp12 u:2 /--* t23 int +--* t431 int N003 ( 5, 4) [000432] N------N-U-- * LE void N004 ( 7, 6) [000433] ------------ * JTRUE void ------------ BB08 [000..000) -> BB10 (always), preds={BB07} succs={BB10} N001 ( 1, 1) [000438] ------------ t438 = LCL_VAR int V42 tmp12 u:2 (last use) /--* t438 int N003 ( 1, 3) [000440] DA---------- * STORE_LCL_VAR int V41 tmp11 d:4 ------------ BB09 [000..000), preds={BB07} succs={BB10} N001 ( 1, 1) [000434] ------------ t434 = LCL_VAR int V31 tmp1 u:2 $241 /--* t434 int N003 ( 1, 3) [000436] DA---------- * STORE_LCL_VAR int V41 tmp11 d:3 ------------ BB10 [???..???) -> BB14 (cond), preds={BB08,BB09} succs={BB11,BB14} N001 ( 0, 0) [000907] ------------ t907 = PHI_ARG int V41 tmp11 u:4 N002 ( 0, 0) [000906] ------------ t906 = PHI_ARG int V41 tmp11 u:3 $241 /--* t907 int +--* t906 int N003 ( 0, 0) [000882] ------------ t882 = * PHI int /--* t882 int N005 ( 0, 0) [000883] DA---------- * STORE_LCL_VAR int V41 tmp11 d:2 N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR int V31 tmp1 u:2 (last use) $241 N002 ( 1, 1) [000032] ------------ t32 = LCL_VAR int V41 tmp11 u:2 $242 /--* t22 int +--* t32 int N003 ( 3, 3) [000033] ------------ t33 = * SUB int $34e /--* t33 int N005 ( 7, 6) [000035] DA---------- * STORE_LCL_VAR int V05 loc2 d:2 [000917] ------------ IL_OFFSET void IL offset: 0x42 N001 ( 1, 1) [000042] ------------ t42 = LCL_VAR int V41 tmp11 u:2 $242 /--* t42 int N003 ( 5, 4) [000044] DA---------- * STORE_LCL_VAR int V08 loc5 d:2 N001 ( 1, 1) [000447] ------------ t447 = LCL_VAR ref V52 tmp22 u:2 /--* t447 ref [000992] -c---------- t992 = * LEA(b+8) ref /--* t992 ref N002 ( 3, 3) [000448] ---XG------- t448 = * IND int /--* t448 int N004 ( 7, 6) [000050] DA-XG------- * STORE_LCL_VAR int V09 loc6 d:2 [000918] ------------ IL_OFFSET void IL offset: 0x4f N001 ( 3, 2) [000051] ------------ t51 = LCL_VAR int V09 loc6 u:2 N002 ( 1, 1) [000052] ------------ t52 = LCL_VAR int V08 loc5 u:2 $242 /--* t51 int +--* t52 int N003 ( 5, 4) [000053] ------------ t53 = * SUB int /--* t53 int N005 ( 5, 4) [000055] DA---------- * STORE_LCL_VAR int V10 loc7 d:2 N001 ( 3, 2) [000063] -------N---- t63 = LCL_VAR_ADDR byref V11 loc8 * ref V11._bits (offs=0x00) -> V54 tmp24 * int V11._sign (offs=0x08) -> V55 tmp25 /--* t63 byref N004 ( 7, 6) [000563] DA--------L- * STORE_LCL_VAR long V75 tmp45 d:2 N005 ( 3, 2) [000547] -------N---- t547 = LCL_VAR_ADDR byref V73 tmp43 /--* t547 byref N008 ( 3, 3) [000549] DA---------- * STORE_LCL_VAR byref V74 tmp44 d:2 N009 ( 1, 1) [000550] ------------ t550 = LCL_VAR byref V74 tmp44 u:2 Zero Fseq[Mantissa] $401 N011 ( 1, 1) [000552] -------N---- t552 = LCL_VAR ref V52 tmp22 u:2 /--* t550 byref +--* t552 ref [000919] -A---------- * STOREIND ref N014 ( 1, 1) [000555] ------------ t555 = LCL_VAR byref V74 tmp44 u:2 (last use) $401 /--* t555 byref N016 ( 2, 2) [000557] -c---------- t557 = * LEA(b+8) byref N018 ( 1, 1) [000559] -------N---- t559 = LCL_VAR int V53 tmp23 u:2 /--* t557 byref +--* t559 int [000920] -A--------L- * STOREIND int N023 ( 3, 2) [000564] ------------ t564 = LCL_VAR long V75 tmp45 u:2 (last use) $400 /--* t564 long [001011] ------------ t1011 = * PUTARG_REG long REG rcx N024 ( 3, 2) [000565] -------N---- t565 = LCL_VAR_ADDR byref V73 tmp43 /--* t565 byref [001012] ------------ t1012 = * PUTARG_REG byref REG rdx N026 ( 1, 1) [000058] ------------ t58 = LCL_VAR int V08 loc5 u:2 (last use) $242 /--* t58 int [001013] ------------ t1013 = * PUTARG_REG int REG r9 N027 ( 1, 1) [000057] ------------ t57 = CNS_INT int 0 $40 /--* t57 int [001014] ------------ t1014 = * PUTARG_REG int REG r8 /--* t1011 long arg0 in rcx +--* t1012 byref arg1 in rdx +--* t1013 int arg3 in r9 +--* t1014 int arg2 in r8 N028 ( 49, 35) [000059] S-CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger $VN.Void [000921] ------------ IL_OFFSET void IL offset: 0x61 N001 ( 3, 2) [000065] ------------ t65 = LCL_VAR int V05 loc2 u:2 $34e N002 ( 1, 1) [000066] -c---------- t66 = CNS_INT int 0 $40 /--* t65 int +--* t66 int N003 ( 5, 4) [000067] N------N---- * EQ void $351 N004 ( 7, 6) [000068] ------------ * JTRUE void ------------ BB11 [065..070) -> BB13 (cond), preds={BB10} succs={BB12,BB13} N002 ( 1, 1) [000382] ------------ t382 = LCL_VAR ref V01 arg1 u:1 $c0 /--* t382 ref [001015] ------------ t1015 = * PUTARG_REG ref REG rcx /--* t1015 ref this in rcx N003 ( 15, 8) [000383] --CXG------- t383 = * CALL int FloatingPointType.get_OverflowDecimalExponent $291 /--* t383 int N004 ( 16, 10) [000385] ---XG------- t385 = * CAST long <- int $480 N005 ( 3, 2) [000380] ------------ t380 = LCL_VAR int V05 loc2 u:2 $34e /--* t380 int N006 ( 4, 4) [000381] ---------U-- t381 = * CAST long <- ulong <- uint $481 /--* t385 long +--* t381 long N007 ( 21, 15) [000386] J--XG--N---- * GE void $352 N008 ( 23, 17) [000387] ---XG------- * JTRUE void ------------ BB12 [070..07A) (return), preds={BB11} succs={} [000922] ------------ IL_OFFSET void IL offset: 0x70 N002 ( 1, 1) [000393] ------------ t393 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t393 ref [001016] ------------ t1016 = * PUTARG_REG ref REG rcx N001 ( 1, 1) [001017] ------------ t1017 = LCL_VAR ref V01 arg1 /--* t1017 ref N002 ( 2, 2) [001018] -c---------- t1018 = * LEA(b+0) byref /--* t1018 byref N003 ( 5, 4) [001019] ------------ t1019 = * IND long /--* t1019 long N004 ( 6, 5) [001020] -c---------- t1020 = * LEA(b+80) long /--* t1020 long N005 ( 9, 7) [001021] ------------ t1021 = * IND long /--* t1021 long N006 ( 10, 8) [001022] -c---------- t1022 = * LEA(b+8) long /--* t1022 long N007 ( 13, 10) [001023] -c---------- t1023 = * IND long REG NA /--* t1016 ref this in rcx +--* t1023 long control expr N003 ( 21, 10) [000394] --CXG------- t394 = * CALLV ind long FloatingPointType.get_Infinity $458 N004 ( 1, 1) [000392] ------------ t392 = LCL_VAR byref V02 arg2 u:1 (last use) $81 /--* t392 byref +--* t394 long [000923] -ACXG------- * STOREIND long N001 ( 1, 1) [000397] ------------ t397 = CNS_INT int 3 $48 /--* t397 int N002 ( 2, 2) [000521] ------------ * RETURN int $5ca ------------ BB13 [07A..082), preds={BB11} succs={BB14} [000924] ------------ IL_OFFSET void IL offset: 0x7a N003 ( 3, 2) [000388] -------N---- t388 = LCL_VAR_ADDR byref V11 loc8 * ref V11._bits (offs=0x00) -> V54 tmp24 * int V11._sign (offs=0x08) -> V55 tmp25 /--* t388 byref [001024] ------------ t1024 = * PUTARG_REG byref REG rcx N005 ( 3, 2) [000390] ------------ t390 = LCL_VAR int V05 loc2 u:2 (last use) $34e /--* t390 int [001025] ------------ t1025 = * PUTARG_REG int REG rdx /--* t1024 byref arg0 in rcx +--* t1025 int arg1 in rdx N006 ( 20, 12) [000391] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen $VN.Void ------------ BB14 [082..092) -> BB16 (cond), preds={BB10,BB13} succs={BB15,BB16} N001 ( 3, 2) [000577] -------N---- t577 = LCL_VAR_ADDR byref V76 tmp46 /--* t577 byref N004 ( 3, 3) [000579] DA---------- * STORE_LCL_VAR byref V77 tmp47 d:2 N005 ( 1, 1) [000580] ------------ t580 = LCL_VAR byref V77 tmp47 u:2 Zero Fseq[_bits] $405 N007 ( 3, 2) [000582] -------N---- t582 = LCL_VAR ref (AX) V54 tmp24 $181 /--* t580 byref +--* t582 ref [000925] -A--G------- * STOREIND ref N010 ( 1, 1) [000585] ------------ t585 = LCL_VAR byref V77 tmp47 u:2 (last use) $405 /--* t585 byref N012 ( 2, 2) [000587] -c---------- t587 = * LEA(b+8) byref N014 ( 3, 2) [000589] -------N---- t589 = LCL_VAR int (AX) V55 tmp25 $243 /--* t587 byref +--* t589 int [000926] -A--G-----L- * STOREIND int N018 ( 3, 2) [000592] -------N---- t592 = LCL_VAR_ADDR byref V76 tmp46 /--* t592 byref [001026] ------------ t1026 = * PUTARG_REG byref REG rcx N020 ( 3, 3) [000071] ------------ t71 = LCL_VAR_ADDR long V12 loc9 $443 /--* t71 long [001027] ------------ t1027 = * PUTARG_REG long REG rdx /--* t1026 byref arg0 in rcx +--* t1027 long arg1 in rdx N021 ( 41, 28) [000072] --CXG------- t72 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $293 /--* t72 int N023 ( 41, 28) [000077] DA-XG------- * STORE_LCL_VAR int V13 loc10 d:2 [000927] ------------ IL_OFFSET void IL offset: 0x8d N001 ( 1, 1) [000078] ------------ t78 = LCL_VAR int V13 loc10 u:2 $293 N002 ( 3, 2) [000079] ------------ t79 = LCL_VAR int V03 loc0 u:2 $348 /--* t78 int +--* t79 int N003 ( 5, 4) [000080] N------N-U-- * GE void $353 N004 ( 7, 6) [000081] ------------ * JTRUE void ------------ BB15 [092..096) -> BB17 (cond), preds={BB14} succs={BB16,BB17} [000928] ------------ IL_OFFSET void IL offset: 0x92 N001 ( 1, 1) [000091] ------------ t91 = LCL_VAR int V10 loc7 u:2 N002 ( 1, 1) [000092] -c---------- t92 = CNS_INT int 0 $40 /--* t91 int +--* t92 int N003 ( 3, 3) [000093] J------N---- * NE void N004 ( 5, 5) [000094] ------------ * JTRUE void ------------ BB16 [096..0A7) -> BB44 (always), preds={BB14,BB15} succs={BB44} [000929] ------------ IL_OFFSET void IL offset: 0x96 N005 ( 1, 1) [000088] ------------ t88 = LCL_VAR byref V02 arg2 u:1 (last use) $81 /--* t88 byref [001028] ------------ * PUTARG_STK [+0x20] void N006 ( 1, 1) [000084] ------------ t84 = LCL_VAR int V10 loc7 u:2 (last use) N007 ( 1, 1) [000085] -c---------- t85 = CNS_INT int 0 $40 /--* t84 int +--* t85 int N008 ( 6, 3) [000086] N----------- t86 = * NE int /--* t86 int [001029] ------------ t1029 = * PUTARG_REG int REG r8 N009 ( 3, 2) [000082] ------------ t82 = LCL_VAR ref (AX) V12 loc9 $18d /--* t82 ref [001030] ------------ t1030 = * PUTARG_REG ref REG rcx N010 ( 1, 1) [000083] ------------ t83 = LCL_VAR int V13 loc10 u:2 (last use) $293 /--* t83 int [001031] ------------ t1031 = * PUTARG_REG int REG rdx N011 ( 1, 1) [000087] ------------ t87 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t87 ref [001032] ------------ t1032 = * PUTARG_REG ref REG r9 /--* t1029 int arg2 in r8 +--* t1030 ref arg0 in rcx +--* t1031 int arg1 in rdx +--* t1032 ref arg3 in r9 N012 ( 29, 17) [000089] --CXG------- t89 = * CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits $5c7 /--* t89 int N014 ( 29, 17) [000600] DA-XG------- * STORE_LCL_VAR int V51 tmp21 d:3 ------------ BB17 [0A7..0B0) -> BB19 (cond), preds={BB15} succs={BB18,BB19} [000930] ------------ IL_OFFSET void IL offset: 0xa7 N001 ( 1, 1) [000097] ------------ t97 = LCL_VAR int V53 tmp23 u:2 N002 ( 1, 1) [000098] -c---------- t98 = CNS_INT int 0 $40 /--* t97 int +--* t98 int N003 ( 3, 3) [000099] J---G--N---- * LT void N004 ( 5, 5) [000100] ----G------- * JTRUE void ------------ BB18 [0B0..0B4) -> BB20 (always), preds={BB17} succs={BB20} [000931] ------------ IL_OFFSET void IL offset: 0xb0 N001 ( 1, 1) [000376] ------------ t376 = LCL_VAR int V10 loc7 u:2 /--* t376 int N003 ( 5, 4) [000378] DA---------- * STORE_LCL_VAR int V32 tmp2 d:4 ------------ BB19 [0B4..0BE), preds={BB17} succs={BB20} [000932] ------------ IL_OFFSET void IL offset: 0xb4 N001 ( 1, 1) [000101] ------------ t101 = LCL_VAR int V10 loc7 u:2 N002 ( 1, 1) [000104] ------------ t104 = LCL_VAR int V53 tmp23 u:2 /--* t101 int +--* t104 int N003 ( 3, 3) [000106] ----G------- t106 = * SUB int /--* t106 int N005 ( 7, 6) [000108] DA--G------- * STORE_LCL_VAR int V32 tmp2 d:3 ------------ BB20 [0BE..0C4) -> BB23 (cond), preds={BB18,BB19} succs={BB21,BB23} N001 ( 0, 0) [000905] ------------ t905 = PHI_ARG int V32 tmp2 u:4 N002 ( 0, 0) [000904] ------------ t904 = PHI_ARG int V32 tmp2 u:3 /--* t905 int +--* t904 int N003 ( 0, 0) [000879] ------------ t879 = * PHI int /--* t879 int N005 ( 0, 0) [000880] DA---------- * STORE_LCL_VAR int V32 tmp2 d:2 N001 ( 3, 2) [000110] ------------ t110 = LCL_VAR int V32 tmp2 u:2 (last use) $244 /--* t110 int N003 ( 7, 5) [000112] DA---------- * STORE_LCL_VAR int V14 loc11 d:2 [000933] ------------ IL_OFFSET void IL offset: 0xc0 N001 ( 1, 1) [000113] ------------ t113 = LCL_VAR int V13 loc10 u:2 $293 N002 ( 1, 1) [000114] -c---------- t114 = CNS_INT int 0 $40 /--* t113 int +--* t114 int N003 ( 3, 3) [000115] J------N---- * NE void $35a N004 ( 5, 5) [000116] ------------ * JTRUE void ------------ BB21 [0C4..0D9) -> BB23 (cond), preds={BB20} succs={BB22,BB23} N001 ( 1, 1) [000455] ------------ t455 = LCL_VAR ref V52 tmp22 u:2 /--* t455 ref [000994] -c---------- t994 = * LEA(b+8) ref /--* t994 ref N002 ( 3, 3) [000456] ---XG------- t456 = * IND int /--* t456 int N003 ( 4, 5) [000358] ---XG------- t358 = * CAST long <- int N004 ( 3, 2) [000352] ------------ t352 = LCL_VAR int V14 loc11 u:2 $244 /--* t352 int N005 ( 4, 4) [000353] ---------U-- t353 = * CAST long <- ulong <- uint $486 /--* t353 long +--* t358 long N006 ( 9, 10) [000359] ---XG------- t359 = * SUB long /--* t359 long N008 ( 13, 13) [000363] DA-XG------- * STORE_LCL_VAR long V38 tmp8 d:2 N002 ( 1, 1) [000360] ------------ t360 = LCL_VAR ref V01 arg1 u:1 $c0 /--* t360 ref [001033] ------------ t1033 = * PUTARG_REG ref REG rcx /--* t1033 ref this in rcx N003 ( 15, 8) [000361] --CXG------- t361 = * CALL int FloatingPointType.get_OverflowDecimalExponent $298 /--* t361 int N004 ( 16, 10) [000366] ---XG------- t366 = * CAST long <- int $48b N005 ( 3, 2) [000364] ------------ t364 = LCL_VAR long V38 tmp8 u:2 (last use) /--* t366 long +--* t364 long N006 ( 20, 13) [000367] J--XG--N---- * GE void N007 ( 22, 15) [000368] ---XG------- * JTRUE void ------------ BB22 [0D9..0E3) (return), preds={BB21} succs={} [000934] ------------ IL_OFFSET void IL offset: 0xd9 N002 ( 1, 1) [000370] ------------ t370 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t370 ref [001034] ------------ t1034 = * PUTARG_REG ref REG rcx N001 ( 1, 1) [001035] ------------ t1035 = LCL_VAR ref V01 arg1 /--* t1035 ref N002 ( 2, 2) [001036] -c---------- t1036 = * LEA(b+0) byref /--* t1036 byref N003 ( 5, 4) [001037] ------------ t1037 = * IND long /--* t1037 long N004 ( 6, 5) [001038] -c---------- t1038 = * LEA(b+80) long /--* t1038 long N005 ( 9, 7) [001039] ------------ t1039 = * IND long /--* t1039 long N006 ( 10, 8) [001040] -c---------- t1040 = * LEA(b+0) long /--* t1040 long N007 ( 13, 10) [001041] -c---------- t1041 = * IND long REG NA /--* t1034 ref this in rcx +--* t1041 long control expr N003 ( 21, 10) [000371] --CXG------- t371 = * CALLV ind long FloatingPointType.get_Zero $457 N004 ( 1, 1) [000369] ------------ t369 = LCL_VAR byref V02 arg2 u:1 (last use) $81 /--* t369 byref +--* t371 long [000935] -ACXG------- * STOREIND long N001 ( 1, 1) [000374] ------------ t374 = CNS_INT int 2 $42 /--* t374 int N002 ( 2, 2) [000524] ------------ * RETURN int $5c4 ------------ BB23 [0E3..117) -> BB25 (cond), preds={BB20,BB21} succs={BB24,BB25} N001 ( 3, 2) [000124] -------N---- t124 = LCL_VAR_ADDR byref V15 loc12 * ref V15._bits (offs=0x00) -> V56 tmp26 * int V15._sign (offs=0x08) -> V57 tmp27 /--* t124 byref N004 ( 7, 6) [000623] DA--------L- * STORE_LCL_VAR long V79 tmp49 d:2 N005 ( 3, 2) [000607] -------N---- t607 = LCL_VAR_ADDR byref V73 tmp43 /--* t607 byref N008 ( 3, 3) [000609] DA---------- * STORE_LCL_VAR byref V78 tmp48 d:2 N009 ( 1, 1) [000610] ------------ t610 = LCL_VAR byref V78 tmp48 u:2 Zero Fseq[Mantissa] $409 N011 ( 1, 1) [000612] -------N---- t612 = LCL_VAR ref V52 tmp22 u:2 (last use) /--* t610 byref +--* t612 ref [000936] -A---------- * STOREIND ref N014 ( 1, 1) [000615] ------------ t615 = LCL_VAR byref V78 tmp48 u:2 (last use) $409 /--* t615 byref N016 ( 2, 2) [000617] -c---------- t617 = * LEA(b+8) byref N018 ( 1, 1) [000619] -------N---- t619 = LCL_VAR int V53 tmp23 u:2 (last use) /--* t617 byref +--* t619 int [000937] -A--------L- * STOREIND int N023 ( 3, 2) [000624] ------------ t624 = LCL_VAR long V79 tmp49 u:2 (last use) $408 /--* t624 long [001042] ------------ t1042 = * PUTARG_REG long REG rcx N024 ( 3, 2) [000625] -------N---- t625 = LCL_VAR_ADDR byref V73 tmp43 /--* t625 byref [001043] ------------ t1043 = * PUTARG_REG byref REG rdx N026 ( 3, 2) [000118] ------------ t118 = LCL_VAR int V08 loc5 u:2 (last use) $242 /--* t118 int [001044] ------------ t1044 = * PUTARG_REG int REG r8 N027 ( 3, 2) [000119] ------------ t119 = LCL_VAR int V09 loc6 u:2 (last use) /--* t119 int [001045] ------------ t1045 = * PUTARG_REG int REG r9 /--* t1042 long arg0 in rcx +--* t1043 byref arg1 in rdx +--* t1044 int arg2 in r8 +--* t1045 int arg3 in r9 N028 ( 53, 37) [000120] S-CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger $VN.Void [000938] ------------ IL_OFFSET void IL offset: 0xef N003 ( 2, 10) [000131] ------------ t131 = CNS_INT long 0x7ff815262aa0 $102 /--* t131 long [001046] ------------ t1046 = * PUTARG_REG long REG rcx N004 ( 1, 4) [000132] ------------ t132 = CNS_INT int 173 $58 /--* t132 int [001047] ------------ t1047 = * PUTARG_REG int REG rdx /--* t1046 long arg0 in rcx +--* t1047 int arg1 in rdx N005 ( 17, 21) [000133] H-CXG------- t133 = * CALL help long HELPER.CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE $48d N001 ( 2, 10) [000634] I----------- t634 = CNS_INT(h) long 0xd1ffab1e static Fseq[BigOne] $4c2 /--* t634 long N002 ( 4, 12) [000633] n---G------- t633 = * IND ref N003 ( 1, 1) [000635] -c---------- t635 = CNS_INT long 8 Fseq[#FirstElem] $101 /--* t633 ref +--* t635 long N004 ( 6, 14) [000632] ----G------- t632 = * ADD byref /--* t632 byref N006 ( 6, 14) [000637] DA--G------- * STORE_LCL_VAR byref V80 tmp50 d:2 N007 ( 1, 1) [000639] ------------ t639 = LCL_VAR byref V80 tmp50 u:2 Zero Fseq[_bits] /--* t639 byref N008 ( 3, 2) [000640] ---X-------- t640 = * IND ref /--* t640 ref N010 ( 7, 5) [000641] DA-XG------- * STORE_LCL_VAR ref (AX) V58 tmp28 N012 ( 1, 1) [000644] ------------ t644 = LCL_VAR byref V80 tmp50 u:2 (last use) /--* t644 byref N014 ( 2, 2) [000646] -c---------- t646 = * LEA(b+8) byref /--* t646 byref N015 ( 4, 4) [000647] ---X-------- t647 = * IND int /--* t647 int N017 ( 8, 7) [000648] DA-XG------- * STORE_LCL_VAR int (AX) V59 tmp29 [000939] ------------ IL_OFFSET void IL offset: 0xf6 N003 ( 3, 2) [000138] -------N---- t138 = LCL_VAR_ADDR byref V16 loc13 * ref V16._bits (offs=0x00) -> V58 tmp28 * int V16._sign (offs=0x08) -> V59 tmp29 /--* t138 byref [001048] ------------ t1048 = * PUTARG_REG byref REG rcx N005 ( 3, 2) [000140] ------------ t140 = LCL_VAR int V14 loc11 u:2 (last use) $244 /--* t140 int [001049] ------------ t1049 = * PUTARG_REG int REG rdx /--* t1048 byref arg0 in rcx +--* t1049 int arg1 in rdx N006 ( 20, 12) [000141] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen $VN.Void [000940] ------------ IL_OFFSET void IL offset: 0xff N001 ( 3, 2) [000653] -------N---- t653 = LCL_VAR ref (AX) V56 tmp26 $184 /--* t653 ref N003 ( 7, 5) [000654] DA--G------- * STORE_LCL_VAR ref V64 tmp34 d:2 N004 ( 3, 2) [000656] -------N---- t656 = LCL_VAR int (AX) V57 tmp27 $246 /--* t656 int N006 ( 7, 5) [000657] DA--G------- * STORE_LCL_VAR int V65 tmp35 d:2 [000941] ------------ IL_OFFSET void IL offset: 0xff N001 ( 3, 2) [000663] -------N---- t663 = LCL_VAR_ADDR byref V76 tmp46 /--* t663 byref N004 ( 3, 3) [000665] DA---------- * STORE_LCL_VAR byref V81 tmp51 d:2 N005 ( 1, 1) [000666] ------------ t666 = LCL_VAR byref V81 tmp51 u:2 Zero Fseq[_bits] $40e N007 ( 3, 2) [000668] -------N---- t668 = LCL_VAR ref V64 tmp34 u:2 (last use) $184 /--* t666 byref +--* t668 ref [000942] -A---------- * STOREIND ref N010 ( 1, 1) [000671] ------------ t671 = LCL_VAR byref V81 tmp51 u:2 (last use) $40e /--* t671 byref N012 ( 2, 2) [000673] -c---------- t673 = * LEA(b+8) byref N014 ( 3, 2) [000675] -------N---- t675 = LCL_VAR int V65 tmp35 u:2 (last use) $246 /--* t673 byref +--* t675 int [000943] -A--------L- * STOREIND int N018 ( 3, 2) [000678] -------N---- t678 = LCL_VAR_ADDR byref V76 tmp46 /--* t678 byref [001050] ------------ t1050 = * PUTARG_REG byref REG rcx N020 ( 3, 3) [000462] ------------ t462 = LCL_VAR_ADDR long V45 tmp15 $449 /--* t462 long [001051] ------------ t1051 = * PUTARG_REG long REG rdx /--* t1050 byref arg0 in rcx +--* t1051 long arg1 in rdx N021 ( 41, 28) [000463] --CXG------- t463 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $29f /--* t463 int N023 ( 45, 31) [000468] DA-XG------- * STORE_LCL_VAR int V43 tmp13 d:2 [000944] ------------ IL_OFFSET void IL offset: 0xff N001 ( 1, 1) [000473] ------------ t473 = CNS_INT ref null $VN.Null /--* t473 ref N003 ( 5, 4) [000475] DA--G------- * STORE_LCL_VAR ref (AX) V45 tmp15 N001 ( 3, 2) [000469] ------------ t469 = LCL_VAR int V43 tmp13 u:2 $29f /--* t469 int N003 ( 7, 5) [000148] DA---------- * STORE_LCL_VAR int V17 loc14 d:2 [000945] ------------ IL_OFFSET void IL offset: 0x108 N001 ( 3, 2) [000682] -------N---- t682 = LCL_VAR ref (AX) V58 tmp28 $185 /--* t682 ref N003 ( 7, 5) [000683] DA--G------- * STORE_LCL_VAR ref V66 tmp36 d:2 N004 ( 3, 2) [000685] -------N---- t685 = LCL_VAR int (AX) V59 tmp29 $247 /--* t685 int N006 ( 7, 5) [000686] DA--G------- * STORE_LCL_VAR int V67 tmp37 d:2 [000946] ------------ IL_OFFSET void IL offset: 0x108 N001 ( 3, 2) [000692] -------N---- t692 = LCL_VAR_ADDR byref V76 tmp46 /--* t692 byref N004 ( 3, 3) [000694] DA---------- * STORE_LCL_VAR byref V82 tmp52 d:2 N005 ( 1, 1) [000695] ------------ t695 = LCL_VAR byref V82 tmp52 u:2 Zero Fseq[_bits] $411 N007 ( 3, 2) [000697] -------N---- t697 = LCL_VAR ref V66 tmp36 u:2 (last use) $185 /--* t695 byref +--* t697 ref [000947] -A---------- * STOREIND ref N010 ( 1, 1) [000700] ------------ t700 = LCL_VAR byref V82 tmp52 u:2 (last use) $411 /--* t700 byref N012 ( 2, 2) [000702] -c---------- t702 = * LEA(b+8) byref N014 ( 3, 2) [000704] -------N---- t704 = LCL_VAR int V67 tmp37 u:2 (last use) $247 /--* t702 byref +--* t704 int [000948] -A--------L- * STOREIND int N018 ( 3, 2) [000707] -------N---- t707 = LCL_VAR_ADDR byref V76 tmp46 /--* t707 byref [001052] ------------ t1052 = * PUTARG_REG byref REG rcx N020 ( 3, 3) [000480] ------------ t480 = LCL_VAR_ADDR long V48 tmp18 $44b /--* t480 long [001053] ------------ t1053 = * PUTARG_REG long REG rdx /--* t1052 byref arg0 in rcx +--* t1053 long arg1 in rdx N021 ( 41, 28) [000481] --CXG------- t481 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $2a3 /--* t481 int N023 ( 45, 31) [000486] DA-XG------- * STORE_LCL_VAR int V46 tmp16 d:2 [000949] ------------ IL_OFFSET void IL offset: 0x108 N001 ( 1, 1) [000491] ------------ t491 = CNS_INT ref null $VN.Null /--* t491 ref N003 ( 5, 4) [000493] DA--G------- * STORE_LCL_VAR ref (AX) V48 tmp18 N001 ( 3, 2) [000487] ------------ t487 = LCL_VAR int V46 tmp16 u:2 $2a3 /--* t487 int N003 ( 7, 5) [000155] DA---------- * STORE_LCL_VAR int V18 loc15 d:2 [000950] ------------ IL_OFFSET void IL offset: 0x111 N001 ( 3, 2) [000156] ------------ t156 = LCL_VAR int V18 loc15 u:2 (last use) $2a3 N002 ( 3, 2) [000157] ------------ t157 = LCL_VAR int V17 loc14 u:2 (last use) $29f /--* t156 int +--* t157 int N003 ( 7, 5) [000158] N------N-U-- * GT void $35f N004 ( 9, 7) [000159] ------------ * JTRUE void ------------ BB24 [117..11A) -> BB26 (always), preds={BB23} succs={BB26} [000951] ------------ IL_OFFSET void IL offset: 0x117 N001 ( 1, 1) [000348] ------------ t348 = CNS_INT int 0 $40 /--* t348 int N003 ( 5, 4) [000350] DA---------- * STORE_LCL_VAR int V33 tmp3 d:4 ------------ BB25 [11A..11F), preds={BB23} succs={BB26} [000952] ------------ IL_OFFSET void IL offset: 0x11a N001 ( 3, 2) [000160] ------------ t160 = LCL_VAR int V18 loc15 u:2 (last use) $2a3 N002 ( 3, 2) [000161] ------------ t161 = LCL_VAR int V17 loc14 u:2 (last use) $29f /--* t160 int +--* t161 int N003 ( 7, 5) [000162] ------------ t162 = * SUB int $360 /--* t162 int N005 ( 11, 8) [000164] DA---------- * STORE_LCL_VAR int V33 tmp3 d:3 ------------ BB26 [11F..126) -> BB28 (cond), preds={BB24,BB25} succs={BB27,BB28} N001 ( 0, 0) [000903] ------------ t903 = PHI_ARG int V33 tmp3 u:4 $40 N002 ( 0, 0) [000902] ------------ t902 = PHI_ARG int V33 tmp3 u:3 $360 /--* t903 int +--* t902 int N003 ( 0, 0) [000876] ------------ t876 = * PHI int /--* t876 int N005 ( 0, 0) [000877] DA---------- * STORE_LCL_VAR int V33 tmp3 d:2 N001 ( 3, 2) [000166] ------------ t166 = LCL_VAR int V33 tmp3 u:2 $248 /--* t166 int N003 ( 3, 3) [000168] DA---------- * STORE_LCL_VAR int V19 loc16 d:2 [000953] ------------ IL_OFFSET void IL offset: 0x121 N001 ( 3, 2) [000169] ------------ t169 = LCL_VAR int V19 loc16 u:2 (last use) $248 N002 ( 1, 1) [000170] -c---------- t170 = CNS_INT int 0 $40 /--* t169 int +--* t170 int N003 ( 5, 4) [000171] N------N---- * EQ void $361 N004 ( 7, 6) [000172] ------------ * JTRUE void ------------ BB27 [126..12F), preds={BB26} succs={BB28} [000954] ------------ IL_OFFSET void IL offset: 0x126 N003 ( 3, 2) [000344] -------N---- t344 = LCL_VAR_ADDR byref V15 loc12 * ref V15._bits (offs=0x00) -> V56 tmp26 * int V15._sign (offs=0x08) -> V57 tmp27 /--* t344 byref [001054] ------------ t1054 = * PUTARG_REG byref REG rcx N005 ( 1, 1) [000346] ------------ t346 = LCL_VAR int V19 loc16 u:2 $248 /--* t346 int [001055] ------------ t1055 = * PUTARG_REG int REG rdx /--* t1054 byref arg0 in rcx +--* t1055 int arg1 in rdx N006 ( 18, 11) [000347] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft $VN.Void ------------ BB28 [12F..13E) -> BB32 (cond), preds={BB26,BB27} succs={BB29,BB32} [000955] ------------ IL_OFFSET void IL offset: 0x12f N001 ( 3, 2) [000173] ------------ t173 = LCL_VAR int V03 loc0 u:2 (last use) $348 N002 ( 1, 1) [000174] ------------ t174 = LCL_VAR int V13 loc10 u:2 $293 /--* t173 int +--* t174 int N003 ( 5, 4) [000175] ------------ t175 = * SUB int $362 /--* t175 int N005 ( 9, 7) [000177] DA---------- * STORE_LCL_VAR int V20 loc17 d:2 [000956] ------------ IL_OFFSET void IL offset: 0x135 N001 ( 3, 2) [000178] ------------ t178 = LCL_VAR int V20 loc17 u:2 $362 /--* t178 int N003 ( 7, 5) [000180] DA---------- * STORE_LCL_VAR int V21 loc18 d:2 [000957] ------------ IL_OFFSET void IL offset: 0x139 N001 ( 1, 1) [000181] ------------ t181 = LCL_VAR int V13 loc10 u:2 $293 N002 ( 1, 1) [000182] -c---------- t182 = CNS_INT int 0 $40 /--* t181 int +--* t182 int N003 ( 3, 3) [000183] N------N---- * EQ void $363 N004 ( 5, 5) [000184] ------------ * JTRUE void ------------ BB29 [13E..144) -> BB31 (cond), preds={BB28} succs={BB30,BB31} [000958] ------------ IL_OFFSET void IL offset: 0x13e N001 ( 1, 1) [000326] ------------ t326 = LCL_VAR int V19 loc16 u:2 $248 N002 ( 3, 2) [000327] ------------ t327 = LCL_VAR int V20 loc17 u:2 $362 /--* t326 int +--* t327 int N003 ( 5, 4) [000328] N------N-U-- * LE void $364 N004 ( 7, 6) [000329] ------------ * JTRUE void ------------ BB30 [144..155) -> BB44 (always), preds={BB29} succs={BB44} [000959] ------------ IL_OFFSET void IL offset: 0x144 N005 ( 1, 1) [000341] ------------ t341 = LCL_VAR byref V02 arg2 u:1 (last use) $81 /--* t341 byref [001056] ------------ * PUTARG_STK [+0x20] void N006 ( 1, 1) [000339] ------------ t339 = CNS_INT int 1 $41 /--* t339 int [001057] ------------ t1057 = * PUTARG_REG int REG r8 N007 ( 3, 2) [000335] ------------ t335 = LCL_VAR ref (AX) V12 loc9 $18c /--* t335 ref [001058] ------------ t1058 = * PUTARG_REG ref REG rcx N008 ( 1, 1) [000336] ------------ t336 = LCL_VAR int V13 loc10 u:2 (last use) $293 /--* t336 int [001059] ------------ t1059 = * PUTARG_REG int REG rdx N009 ( 1, 1) [000340] ------------ t340 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t340 ref [001060] ------------ t1060 = * PUTARG_REG ref REG r9 /--* t1057 int arg2 in r8 +--* t1058 ref arg0 in rcx +--* t1059 int arg1 in rdx +--* t1060 ref arg3 in r9 N010 ( 24, 15) [000342] --CXG------- t342 = * CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits $5c2 /--* t342 int N012 ( 24, 15) [000717] DA-XG------- * STORE_LCL_VAR int V51 tmp21 d:5 ------------ BB31 [155..15C), preds={BB29} succs={BB32} [000960] ------------ IL_OFFSET void IL offset: 0x155 N001 ( 3, 2) [000330] ------------ t330 = LCL_VAR int V20 loc17 u:2 (last use) $362 N002 ( 1, 1) [000331] ------------ t331 = LCL_VAR int V19 loc16 u:2 $248 /--* t330 int +--* t331 int N003 ( 5, 4) [000332] ------------ t332 = * SUB int $365 /--* t332 int N005 ( 9, 7) [000334] DA---------- * STORE_LCL_VAR int V21 loc18 d:4 ------------ BB32 [15C..167) -> BB34 (cond), preds={BB28,BB31} succs={BB33,BB34} N001 ( 0, 0) [000900] ------------ t900 = PHI_ARG int V21 loc18 u:4 $365 N002 ( 0, 0) [000888] ------------ t888 = PHI_ARG int V21 loc18 u:2 $362 /--* t900 int +--* t888 int N003 ( 0, 0) [000873] ------------ t873 = * PHI int /--* t873 int N005 ( 0, 0) [000874] DA---------- * STORE_LCL_VAR int V21 loc18 d:3 [000961] ------------ IL_OFFSET void IL offset: 0x15c N001 ( 3, 2) [000719] -------N---- t719 = LCL_VAR ref (AX) V56 tmp26 $186 /--* t719 ref N003 ( 7, 5) [000720] DA--G------- * STORE_LCL_VAR ref (AX) V68 tmp38 N004 ( 3, 2) [000722] -------N---- t722 = LCL_VAR int (AX) V57 tmp27 $24a /--* t722 int N006 ( 7, 5) [000723] DA--G------- * STORE_LCL_VAR int (AX) V69 tmp39 [000962] ------------ IL_OFFSET void IL offset: 0x15c N001 ( 3, 2) [000726] -------N---- t726 = LCL_VAR ref (AX) V58 tmp28 $187 /--* t726 ref N003 ( 7, 5) [000727] DA--G------- * STORE_LCL_VAR ref V70 tmp40 d:2 N004 ( 3, 2) [000729] -------N---- t729 = LCL_VAR int (AX) V59 tmp29 $24b /--* t729 int N006 ( 7, 5) [000730] DA--G------- * STORE_LCL_VAR int V71 tmp41 d:2 N001 ( 3, 2) [000496] -------N---- t496 = LCL_VAR_ADDR byref V49 tmp19 * ref V49._bits (offs=0x00) -> V68 tmp38 * int V49._sign (offs=0x08) -> V69 tmp39 /--* t496 byref N004 ( 7, 6) [000752] DA--------L- * STORE_LCL_VAR byref V84 tmp54 d:2 N005 ( 3, 2) [000736] -------N---- t736 = LCL_VAR_ADDR byref V76 tmp46 /--* t736 byref N008 ( 3, 3) [000738] DA---------- * STORE_LCL_VAR byref V83 tmp53 d:2 N009 ( 1, 1) [000739] ------------ t739 = LCL_VAR byref V83 tmp53 u:2 Zero Fseq[_bits] $417 N011 ( 3, 2) [000741] -------N---- t741 = LCL_VAR ref V70 tmp40 u:2 (last use) $187 /--* t739 byref +--* t741 ref [000963] -A---------- * STOREIND ref N014 ( 1, 1) [000744] ------------ t744 = LCL_VAR byref V83 tmp53 u:2 (last use) $417 /--* t744 byref N016 ( 2, 2) [000746] -c---------- t746 = * LEA(b+8) byref N018 ( 3, 2) [000748] -------N---- t748 = LCL_VAR int V71 tmp41 u:2 (last use) $24b /--* t746 byref +--* t748 int [000964] -A--------L- * STOREIND int N021 ( 3, 2) [000753] ------------ t753 = LCL_VAR byref V84 tmp54 u:2 (last use) $415 /--* t753 byref [001061] ------------ t1061 = * PUTARG_REG byref REG rcx N022 ( 3, 2) [000754] -------N---- t754 = LCL_VAR_ADDR byref V76 tmp46 /--* t754 byref [001062] ------------ t1062 = * PUTARG_REG byref REG rdx /--* t1061 byref this in rcx +--* t1062 byref arg1 in rdx N024 ( 48, 34) [000499] --CXG------- t499 = * CALL int System.Numerics.BigInteger.CompareTo $2ae N025 ( 1, 1) [000502] -c---------- t502 = CNS_INT int 0 $40 /--* t499 int +--* t502 int N026 ( 50, 36) [000503] J--XG--N---- * LT void $367 N027 ( 52, 38) [000195] ---XG------- * JTRUE void ------------ BB33 [167..16B) -> BB35 (always), preds={BB32} succs={BB35} [000965] ------------ IL_OFFSET void IL offset: 0x167 N001 ( 1, 1) [000322] ------------ t322 = LCL_VAR int V19 loc16 u:2 (last use) $248 /--* t322 int N003 ( 5, 4) [000324] DA---------- * STORE_LCL_VAR int V34 tmp4 d:4 ------------ BB34 [16B..16F), preds={BB32} succs={BB35} [000966] ------------ IL_OFFSET void IL offset: 0x16b N001 ( 1, 1) [000196] ------------ t196 = LCL_VAR int V19 loc16 u:2 (last use) $248 N002 ( 1, 1) [000197] -c---------- t197 = CNS_INT int 1 $41 /--* t196 int +--* t197 int N003 ( 3, 3) [000198] ------------ t198 = * ADD int $368 /--* t198 int N005 ( 7, 6) [000200] DA---------- * STORE_LCL_VAR int V34 tmp4 d:3 ------------ BB35 [16F..1A4) -> BB40 (cond), preds={BB33,BB34} succs={BB36,BB40} N001 ( 0, 0) [000899] ------------ t899 = PHI_ARG int V34 tmp4 u:4 $248 N002 ( 0, 0) [000898] ------------ t898 = PHI_ARG int V34 tmp4 u:3 $368 /--* t899 int +--* t898 int N003 ( 0, 0) [000870] ------------ t870 = * PHI int /--* t870 int N005 ( 0, 0) [000871] DA---------- * STORE_LCL_VAR int V34 tmp4 d:2 N001 ( 3, 2) [000202] ------------ t202 = LCL_VAR int V34 tmp4 u:2 (last use) $24c /--* t202 int N003 ( 7, 5) [000204] DA---------- * STORE_LCL_VAR int V22 loc19 d:2 [000967] ------------ IL_OFFSET void IL offset: 0x171 N003 ( 3, 2) [000205] -------N---- t205 = LCL_VAR_ADDR byref V15 loc12 * ref V15._bits (offs=0x00) -> V56 tmp26 * int V15._sign (offs=0x08) -> V57 tmp27 /--* t205 byref [001063] ------------ t1063 = * PUTARG_REG byref REG rcx N005 ( 3, 2) [000207] ------------ t207 = LCL_VAR int V21 loc18 u:3 (last use) $249 /--* t207 int [001064] ------------ t1064 = * PUTARG_REG int REG rdx /--* t1063 byref arg0 in rcx +--* t1064 int arg1 in rdx N006 ( 20, 12) [000208] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft $VN.Void [000968] ------------ IL_OFFSET void IL offset: 0x17a N001 ( 3, 2) [000219] -------N---- t219 = LCL_VAR_ADDR byref V35 tmp5 * ref V35._bits (offs=0x00) -> V62 tmp32 * int V35._sign (offs=0x08) -> V63 tmp33 /--* t219 byref N004 ( 7, 6) [000797] DA--------L- * STORE_LCL_VAR long V88 tmp58 d:2 N005 ( 3, 2) [000762] -------N---- t762 = LCL_VAR_ADDR byref V76 tmp46 /--* t762 byref N008 ( 3, 3) [000764] DA---------- * STORE_LCL_VAR byref V85 tmp55 d:2 N009 ( 1, 1) [000765] ------------ t765 = LCL_VAR byref V85 tmp55 u:2 Zero Fseq[_bits] $41c N011 ( 3, 2) [000767] -------N---- t767 = LCL_VAR ref (AX) V56 tmp26 $188 /--* t765 byref +--* t767 ref [000969] -A--G------- * STOREIND ref N014 ( 1, 1) [000770] ------------ t770 = LCL_VAR byref V85 tmp55 u:2 (last use) $41c /--* t770 byref N016 ( 2, 2) [000772] -c---------- t772 = * LEA(b+8) byref N018 ( 3, 2) [000774] -------N---- t774 = LCL_VAR int (AX) V57 tmp27 $24d /--* t772 byref +--* t774 int [000970] -A--G-----L- * STOREIND int N021 ( 3, 2) [000781] -------N---- t781 = LCL_VAR_ADDR byref V86 tmp56 /--* t781 byref N024 ( 3, 3) [000783] DA---------- * STORE_LCL_VAR byref V87 tmp57 d:2 N025 ( 1, 1) [000784] ------------ t784 = LCL_VAR byref V87 tmp57 u:2 Zero Fseq[_bits] $41e N027 ( 3, 2) [000786] -------N---- t786 = LCL_VAR ref (AX) V58 tmp28 $189 /--* t784 byref +--* t786 ref [000971] -A--G------- * STOREIND ref N030 ( 1, 1) [000789] ------------ t789 = LCL_VAR byref V87 tmp57 u:2 (last use) $41e /--* t789 byref N032 ( 2, 2) [000791] -c---------- t791 = * LEA(b+8) byref N034 ( 3, 2) [000793] -------N---- t793 = LCL_VAR int (AX) V59 tmp29 $24e /--* t791 byref +--* t793 int [000972] -A--G-----L- * STOREIND int N038 ( 3, 2) [000798] ------------ t798 = LCL_VAR long V88 tmp58 u:2 (last use) $41b /--* t798 long [001065] ------------ t1065 = * PUTARG_REG long REG rcx N039 ( 3, 2) [000799] -------N---- t799 = LCL_VAR_ADDR byref V76 tmp46 /--* t799 byref [001066] ------------ t1066 = * PUTARG_REG byref REG rdx N041 ( 3, 2) [000801] -------N---- t801 = LCL_VAR_ADDR byref V86 tmp56 /--* t801 byref [001067] ------------ t1067 = * PUTARG_REG byref REG r8 N043 ( 3, 2) [000211] -------N---- t211 = LCL_VAR_ADDR byref V23 loc20 * ref V23._bits (offs=0x00) -> V60 tmp30 * int V23._sign (offs=0x08) -> V61 tmp31 /--* t211 byref [001068] ------------ t1068 = * PUTARG_REG byref REG r9 /--* t1065 long arg0 in rcx +--* t1066 byref arg1 in rdx +--* t1067 byref arg2 in r8 +--* t1068 byref arg3 in r9 N045 ( 78, 56) [000213] S-CXG------- * CALL void System.Numerics.BigInteger.DivRem $VN.Void N001 ( 3, 2) [000808] -------N---- t808 = LCL_VAR_ADDR byref V76 tmp46 /--* t808 byref N004 ( 3, 3) [000810] DA---------- * STORE_LCL_VAR byref V89 tmp59 d:2 N005 ( 1, 1) [000811] ------------ t811 = LCL_VAR byref V89 tmp59 u:2 Zero Fseq[_bits] $423 N007 ( 3, 2) [000813] -------N---- t813 = LCL_VAR ref (AX) V62 tmp32 $18a /--* t811 byref +--* t813 ref [000973] -A--G------- * STOREIND ref N010 ( 1, 1) [000816] ------------ t816 = LCL_VAR byref V89 tmp59 u:2 (last use) $423 /--* t816 byref N012 ( 2, 2) [000818] -c---------- t818 = * LEA(b+8) byref N014 ( 3, 2) [000820] -------N---- t820 = LCL_VAR int (AX) V63 tmp33 $24f /--* t818 byref +--* t820 int [000974] -A--G-----L- * STOREIND int N017 ( 3, 2) [000823] -------N---- t823 = LCL_VAR_ADDR byref V76 tmp46 /--* t823 byref [001069] ------------ t1069 = * PUTARG_REG byref REG rcx /--* t1069 byref arg0 in rcx N019 ( 38, 24) [000218] --CXG------- t218 = * CALL long System.Numerics.BigInteger.op_Explicit $450 /--* t218 long N021 ( 38, 24) [000226] DA-XG------- * STORE_LCL_VAR long V24 loc21 d:2 N001 ( 3, 2) [000514] -c---------- t514 = LCL_VAR int (AX) V61 tmp31 $250 N002 ( 1, 1) [000515] -c---------- t515 = CNS_INT int 0 $40 /--* t514 int +--* t515 int N003 ( 8, 4) [000516] ----G------- t516 = * EQ int $369 /--* t516 int N005 ( 12, 7) [000232] DA--G------- * STORE_LCL_VAR int V25 loc22 d:2 N002 ( 1, 1) [000233] ------------ t233 = LCL_VAR long V24 loc21 u:2 $450 /--* t233 long [001070] ------------ t1070 = * PUTARG_REG long REG rcx /--* t1070 long arg0 in rcx N003 ( 15, 7) [000234] --CXG------- t234 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $2b4 /--* t234 int N005 ( 19, 10) [000237] DA-XG------- * STORE_LCL_VAR int V26 loc23 d:2 [000975] ------------ IL_OFFSET void IL offset: 0x19e N001 ( 3, 2) [000238] ------------ t238 = LCL_VAR int V26 loc23 u:2 $2b4 N002 ( 3, 2) [000239] ------------ t239 = LCL_VAR int V20 loc17 u:2 $362 /--* t238 int +--* t239 int N003 ( 7, 5) [000240] N------N-U-- * LE void $36a N004 ( 9, 7) [000241] ------------ * JTRUE void ------------ BB36 [1A4..1AF) -> BB38 (cond), preds={BB35} succs={BB37,BB38} [000976] ------------ IL_OFFSET void IL offset: 0x1a4 N001 ( 3, 2) [000282] ------------ t282 = LCL_VAR int V26 loc23 u:2 (last use) $2b4 N002 ( 3, 2) [000283] ------------ t283 = LCL_VAR int V20 loc17 u:2 $362 /--* t282 int +--* t283 int N003 ( 7, 5) [000284] ------------ t284 = * SUB int $36b /--* t284 int N005 ( 11, 8) [000286] DA---------- * STORE_LCL_VAR int V29 loc26 d:2 [000977] ------------ IL_OFFSET void IL offset: 0x1ab N001 ( 3, 2) [000287] ------------ t287 = LCL_VAR int V25 loc22 u:2 (last use) $369 N002 ( 1, 1) [000288] -c---------- t288 = CNS_INT int 0 $40 /--* t287 int +--* t288 int N003 ( 5, 4) [000289] J------N---- * EQ void $36c N004 ( 7, 6) [000290] ------------ * JTRUE void ------------ BB37 [1AF..1C3) -> BB39 (always), preds={BB36} succs={BB39} [000978] ------------ IL_OFFSET void IL offset: 0x1af N001 ( 1, 1) [000305] ------------ t305 = LCL_VAR long V24 loc21 u:2 $450 N002 ( 3, 2) [000308] ------------ t308 = LCL_VAR int V29 loc26 u:2 $36b N005 ( 1, 1) [000307] ------------ t307 = CNS_INT long 1 $103 /--* t307 long +--* t308 int N006 ( 10, 6) [000311] ------------ t311 = * LSH long $48e N007 ( 1, 1) [000313] -c---------- t313 = CNS_INT long -1 $104 /--* t311 long +--* t313 long N008 ( 12, 8) [000314] ------------ t314 = * ADD long $48f /--* t305 long +--* t314 long N011 ( 19, 12) [000318] ------------ t318 = * TEST_EQ int $36e /--* t318 int N013 ( 23, 15) [000320] DA---------- * STORE_LCL_VAR int V37 tmp7 d:4 ------------ BB38 [1C3..1C4), preds={BB36} succs={BB39} [000979] ------------ IL_OFFSET void IL offset: 0x1c3 N001 ( 1, 1) [000291] ------------ t291 = CNS_INT int 0 $40 /--* t291 int N003 ( 5, 4) [000293] DA---------- * STORE_LCL_VAR int V37 tmp7 d:3 ------------ BB39 [1C4..1D0), preds={BB37,BB38} succs={BB40} N001 ( 0, 0) [000897] ------------ t897 = PHI_ARG int V37 tmp7 u:4 $36e N002 ( 0, 0) [000896] ------------ t896 = PHI_ARG int V37 tmp7 u:3 $40 /--* t897 int +--* t896 int N003 ( 0, 0) [000867] ------------ t867 = * PHI int /--* t867 int N005 ( 0, 0) [000868] DA---------- * STORE_LCL_VAR int V37 tmp7 d:2 N001 ( 3, 2) [000295] ------------ t295 = LCL_VAR int V37 tmp7 u:2 (last use) $251 /--* t295 int N002 ( 4, 4) [000826] ------------ t826 = * CAST int <- bool <- int $36f /--* t826 int N004 ( 8, 7) [000297] DA---------- * STORE_LCL_VAR int V25 loc22 d:4 [000980] ------------ IL_OFFSET void IL offset: 0x1c6 N001 ( 1, 1) [000298] ------------ t298 = LCL_VAR long V24 loc21 u:2 (last use) $450 N002 ( 3, 2) [000299] ------------ t299 = LCL_VAR int V29 loc26 u:2 (last use) $36b /--* t298 long +--* t299 int N005 ( 10, 6) [000302] ------------ t302 = * RSZ long $491 /--* t302 long N007 ( 10, 6) [000304] DA---------- * STORE_LCL_VAR long V24 loc21 d:4 ------------ BB40 [1D0..1E7) -> BB42 (cond), preds={BB35,BB39} succs={BB41,BB42} N001 ( 0, 0) [000894] ------------ t894 = PHI_ARG bool V25 loc22 u:4 $36f N002 ( 0, 0) [000889] ------------ t889 = PHI_ARG bool V25 loc22 u:2 $369 /--* t894 bool +--* t889 bool N003 ( 0, 0) [000864] ------------ t864 = * PHI bool /--* t864 bool N005 ( 0, 0) [000865] DA---------- * STORE_LCL_VAR bool V25 loc22 d:3 N001 ( 0, 0) [000895] ------------ t895 = PHI_ARG long V24 loc21 u:4 $491 N002 ( 0, 0) [000890] ------------ t890 = PHI_ARG long V24 loc21 u:2 $450 /--* t895 long +--* t890 long N003 ( 0, 0) [000861] ------------ t861 = * PHI long /--* t861 long N005 ( 0, 0) [000862] DA---------- * STORE_LCL_VAR long V24 loc21 d:3 N001 ( 3, 2) [000831] -------N---- t831 = LCL_VAR_ADDR byref V76 tmp46 /--* t831 byref N004 ( 3, 3) [000833] DA---------- * STORE_LCL_VAR byref V90 tmp60 d:2 N005 ( 1, 1) [000834] ------------ t834 = LCL_VAR byref V90 tmp60 u:2 Zero Fseq[_bits] $426 N007 ( 3, 2) [000836] -------N---- t836 = LCL_VAR ref (AX) V54 tmp24 $18b /--* t834 byref +--* t836 ref [000981] -A--G------- * STOREIND ref N010 ( 1, 1) [000839] ------------ t839 = LCL_VAR byref V90 tmp60 u:2 (last use) $426 /--* t839 byref N012 ( 2, 2) [000841] -c---------- t841 = * LEA(b+8) byref N014 ( 3, 2) [000843] -------N---- t843 = LCL_VAR int (AX) V55 tmp25 $252 /--* t841 byref +--* t843 int [000982] -A--G-----L- * STOREIND int N017 ( 3, 2) [000846] -------N---- t846 = LCL_VAR_ADDR byref V76 tmp46 /--* t846 byref [001071] ------------ t1071 = * PUTARG_REG byref REG rcx /--* t1071 byref arg0 in rcx N019 ( 38, 24) [000243] --CXG------- t243 = * CALL long System.Numerics.BigInteger.op_Explicit $454 N020 ( 3, 2) [000247] ------------ t247 = LCL_VAR int V20 loc17 u:2 (last use) $362 /--* t243 long +--* t247 int N023 ( 47, 29) [000250] ---XG------- t250 = * LSH long $492 N024 ( 1, 1) [000251] ------------ t251 = LCL_VAR long V24 loc21 u:3 (last use) $580 /--* t250 long +--* t251 long N025 ( 49, 31) [000252] ---XG------- t252 = * ADD long $493 /--* t252 long N027 ( 53, 34) [000254] DA-XG------- * STORE_LCL_VAR long V27 loc24 d:2 [000983] ------------ IL_OFFSET void IL offset: 0x1e2 N001 ( 1, 1) [000255] ------------ t255 = LCL_VAR int V13 loc10 u:2 $293 N002 ( 1, 1) [000256] -c---------- t256 = CNS_INT int 0 $40 /--* t255 int +--* t256 int N003 ( 3, 3) [000257] N------N---- * NE void $35a N004 ( 5, 5) [000258] ------------ * JTRUE void ------------ BB41 [1E7..1EE) -> BB43 (always), preds={BB40} succs={BB43} [000984] ------------ IL_OFFSET void IL offset: 0x1e7 N001 ( 3, 2) [000275] ------------ t275 = LCL_VAR int V22 loc19 u:2 (last use) $24c /--* t275 int N002 ( 4, 3) [000276] ------------ t276 = * NEG int $2c2 N003 ( 1, 1) [000277] -c---------- t277 = CNS_INT int -1 $43 /--* t276 int +--* t277 int N004 ( 6, 5) [000278] ------------ t278 = * ADD int $372 /--* t278 int N006 ( 10, 8) [000280] DA---------- * STORE_LCL_VAR int V36 tmp6 d:4 ------------ BB42 [1EE..1F2), preds={BB40} succs={BB43} [000985] ------------ IL_OFFSET void IL offset: 0x1ee N001 ( 1, 1) [000259] ------------ t259 = LCL_VAR int V13 loc10 u:2 (last use) $293 N002 ( 1, 1) [000260] -c---------- t260 = CNS_INT int -2 $68 /--* t259 int +--* t260 int N003 ( 3, 3) [000261] ------------ t261 = * ADD int $371 /--* t261 int N005 ( 7, 6) [000263] DA---------- * STORE_LCL_VAR int V36 tmp6 d:3 ------------ BB43 [1F2..202), preds={BB41,BB42} succs={BB44} N001 ( 0, 0) [000893] ------------ t893 = PHI_ARG int V36 tmp6 u:4 $372 N002 ( 0, 0) [000892] ------------ t892 = PHI_ARG int V36 tmp6 u:3 $371 /--* t893 int +--* t892 int N003 ( 0, 0) [000858] ------------ t858 = * PHI int /--* t858 int N005 ( 0, 0) [000859] DA---------- * STORE_LCL_VAR int V36 tmp6 d:2 [000986] ------------ IL_OFFSET void IL offset: 0x1f4 N005 ( 1, 1) [000272] ------------ t272 = LCL_VAR byref V02 arg2 u:1 (last use) $81 /--* t272 byref [001072] ------------ * PUTARG_STK [+0x20] void N006 ( 1, 1) [000268] ------------ t268 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t268 ref [001073] ------------ t1073 = * PUTARG_REG ref REG rcx N007 ( 3, 2) [000269] ------------ t269 = LCL_VAR long V27 loc24 u:2 (last use) $493 /--* t269 long [001074] ------------ t1074 = * PUTARG_REG long REG rdx N008 ( 3, 2) [000270] ------------ t270 = LCL_VAR int V36 tmp6 u:2 (last use) $253 /--* t270 int [001075] ------------ t1075 = * PUTARG_REG int REG r8 N009 ( 3, 2) [000271] ------------ t271 = LCL_VAR int V25 loc22 u:3 (last use) $540 /--* t271 int [001076] ------------ t1076 = * PUTARG_REG int REG r9 /--* t1073 ref this in rcx +--* t1074 long arg1 in rdx +--* t1075 int arg2 in r8 +--* t1076 int arg3 in r9 N010 ( 28, 18) [000273] --CXG------- t273 = * CALL int FloatingPointType.AssembleFloatingPointValue $2be /--* t273 int N012 ( 28, 18) [000853] DA-XG------- * STORE_LCL_VAR int V51 tmp21 d:4 ------------ BB44 [???..???) (return), preds={BB16,BB30,BB43} succs={} N001 ( 0, 0) [000901] ------------ t901 = PHI_ARG int V51 tmp21 u:5 $5c2 N002 ( 0, 0) [000891] ------------ t891 = PHI_ARG int V51 tmp21 u:4 $2be N003 ( 0, 0) [000887] ------------ t887 = PHI_ARG int V51 tmp21 u:3 $5c7 /--* t901 int +--* t891 int +--* t887 int N004 ( 0, 0) [000855] ------------ t855 = * PHI int /--* t855 int N006 ( 0, 0) [000856] DA---------- * STORE_LCL_VAR int V51 tmp21 d:2 N001 ( 1, 1) [000522] -------N---- t522 = LCL_VAR int V51 tmp21 u:2 (last use) $254 /--* t522 int N002 ( 2, 2) [000523] ------------ * RETURN int $5c9 ------------------------------------------------------------------------------------------------------------------- *** lvaComputeRefCounts *** *** lvaComputeRefCounts -- explicit counts *** New refCnts for V00: refCnt = 1, refCntWtd = 2 New refCnts for V52: refCnt = 1, refCntWtd = 1 New refCnts for V00: refCnt = 2, refCntWtd = 4 New refCnts for V53: refCnt = 1, refCntWtd = 1 New refCnts for V52: refCnt = 2, refCntWtd = 2 New refCnts for V01: refCnt = 1, refCntWtd = 0.50 New refCnts for V01: refCnt = 2, refCntWtd = 1 New refCnts for V02: refCnt = 1, refCntWtd = 0.50 New refCnts for V01: refCnt = 3, refCntWtd = 1.50 New refCnts for V01: refCnt = 4, refCntWtd = 2 New refCnts for V03: refCnt = 1, refCntWtd = 0.50 New refCnts for V53: refCnt = 2, refCntWtd = 1.50 New refCnts for V40: refCnt = 1, refCntWtd = 1 New refCnts for V40: refCnt = 2, refCntWtd = 2 New refCnts for V53: refCnt = 3, refCntWtd = 2 New refCnts for V39: refCnt = 1, refCntWtd = 0.50 New refCnts for V39: refCnt = 2, refCntWtd = 1 New refCnts for V39: refCnt = 3, refCntWtd = 1.50 New refCnts for V31: refCnt = 1, refCntWtd = 1 New refCnts for V52: refCnt = 3, refCntWtd = 2.50 New refCnts for V42: refCnt = 1, refCntWtd = 1 New refCnts for V31: refCnt = 2, refCntWtd = 2 New refCnts for V42: refCnt = 2, refCntWtd = 2 New refCnts for V42: refCnt = 3, refCntWtd = 3 New refCnts for V41: refCnt = 1, refCntWtd = 0.50 New refCnts for V31: refCnt = 3, refCntWtd = 3 New refCnts for V41: refCnt = 2, refCntWtd = 1 New refCnts for V31: refCnt = 4, refCntWtd = 4 New refCnts for V41: refCnt = 3, refCntWtd = 1.50 New refCnts for V05: refCnt = 1, refCntWtd = 0.50 New refCnts for V41: refCnt = 4, refCntWtd = 2 New refCnts for V08: refCnt = 1, refCntWtd = 0.50 New refCnts for V52: refCnt = 4, refCntWtd = 3 New refCnts for V09: refCnt = 1, refCntWtd = 0.50 New refCnts for V09: refCnt = 2, refCntWtd = 1 New refCnts for V08: refCnt = 2, refCntWtd = 1 New refCnts for V10: refCnt = 1, refCntWtd = 0.50 New refCnts for V54: refCnt = 1, refCntWtd = 0.50 New refCnts for V55: refCnt = 1, refCntWtd = 0.50 New refCnts for V11: refCnt = 1, refCntWtd = 0.50 New refCnts for V75: refCnt = 1, refCntWtd = 1 New refCnts for V73: refCnt = 1, refCntWtd = 1 New refCnts for V74: refCnt = 1, refCntWtd = 1 New refCnts for V74: refCnt = 2, refCntWtd = 2 New refCnts for V52: refCnt = 5, refCntWtd = 3.50 New refCnts for V74: refCnt = 3, refCntWtd = 3 New refCnts for V53: refCnt = 4, refCntWtd = 2.50 New refCnts for V75: refCnt = 2, refCntWtd = 2 New refCnts for V73: refCnt = 2, refCntWtd = 2 New refCnts for V08: refCnt = 3, refCntWtd = 1.50 New refCnts for V05: refCnt = 2, refCntWtd = 1 New refCnts for V01: refCnt = 5, refCntWtd = 2.50 New refCnts for V05: refCnt = 3, refCntWtd = 1.50 New refCnts for V01: refCnt = 6, refCntWtd = 3 New refCnts for V01: refCnt = 7, refCntWtd = 3.50 New refCnts for V02: refCnt = 2, refCntWtd = 1 New refCnts for V54: refCnt = 2, refCntWtd = 1 New refCnts for V55: refCnt = 2, refCntWtd = 1 New refCnts for V11: refCnt = 2, refCntWtd = 1 New refCnts for V05: refCnt = 4, refCntWtd = 2 New refCnts for V76: refCnt = 1, refCntWtd = 1 New refCnts for V77: refCnt = 1, refCntWtd = 1 New refCnts for V77: refCnt = 2, refCntWtd = 2 New refCnts for V11: refCnt = 3, refCntWtd = 1.50 New refCnts for V54: refCnt = 3, refCntWtd = 1.50 New refCnts for V77: refCnt = 3, refCntWtd = 3 New refCnts for V11: refCnt = 4, refCntWtd = 2 New refCnts for V55: refCnt = 3, refCntWtd = 1.50 New refCnts for V76: refCnt = 2, refCntWtd = 2 New refCnts for V12: refCnt = 1, refCntWtd = 0.50 New refCnts for V13: refCnt = 1, refCntWtd = 0.50 New refCnts for V13: refCnt = 2, refCntWtd = 1 New refCnts for V03: refCnt = 2, refCntWtd = 1 New refCnts for V10: refCnt = 2, refCntWtd = 1 New refCnts for V02: refCnt = 3, refCntWtd = 1.50 New refCnts for V10: refCnt = 3, refCntWtd = 1.50 New refCnts for V12: refCnt = 2, refCntWtd = 1 New refCnts for V13: refCnt = 3, refCntWtd = 1.50 New refCnts for V01: refCnt = 8, refCntWtd = 4 New refCnts for V51: refCnt = 1, refCntWtd = 1 New refCnts for V53: refCnt = 5, refCntWtd = 3 New refCnts for V10: refCnt = 4, refCntWtd = 2 New refCnts for V32: refCnt = 1, refCntWtd = 0.50 New refCnts for V10: refCnt = 5, refCntWtd = 2.50 New refCnts for V53: refCnt = 6, refCntWtd = 3.50 New refCnts for V32: refCnt = 2, refCntWtd = 1 New refCnts for V32: refCnt = 3, refCntWtd = 1.50 New refCnts for V14: refCnt = 1, refCntWtd = 0.50 New refCnts for V13: refCnt = 4, refCntWtd = 2 New refCnts for V52: refCnt = 6, refCntWtd = 4 New refCnts for V14: refCnt = 2, refCntWtd = 1 New refCnts for V38: refCnt = 1, refCntWtd = 1 New refCnts for V01: refCnt = 9, refCntWtd = 4.50 New refCnts for V38: refCnt = 2, refCntWtd = 2 New refCnts for V01: refCnt = 10, refCntWtd = 5 New refCnts for V01: refCnt = 11, refCntWtd = 5.50 New refCnts for V02: refCnt = 4, refCntWtd = 2 New refCnts for V56: refCnt = 1, refCntWtd = 0.50 New refCnts for V57: refCnt = 1, refCntWtd = 0.50 New refCnts for V15: refCnt = 1, refCntWtd = 0.50 New refCnts for V79: refCnt = 1, refCntWtd = 1 New refCnts for V73: refCnt = 3, refCntWtd = 3 New refCnts for V78: refCnt = 1, refCntWtd = 1 New refCnts for V78: refCnt = 2, refCntWtd = 2 New refCnts for V52: refCnt = 7, refCntWtd = 4.50 New refCnts for V78: refCnt = 3, refCntWtd = 3 New refCnts for V53: refCnt = 7, refCntWtd = 4 New refCnts for V79: refCnt = 2, refCntWtd = 2 New refCnts for V73: refCnt = 4, refCntWtd = 4 New refCnts for V08: refCnt = 4, refCntWtd = 2 New refCnts for V09: refCnt = 3, refCntWtd = 1.50 New refCnts for V80: refCnt = 1, refCntWtd = 1 New refCnts for V80: refCnt = 2, refCntWtd = 2 New refCnts for V16: refCnt = 1, refCntWtd = 0.50 New refCnts for V58: refCnt = 1, refCntWtd = 0.50 New refCnts for V80: refCnt = 3, refCntWtd = 3 New refCnts for V16: refCnt = 2, refCntWtd = 1 New refCnts for V59: refCnt = 1, refCntWtd = 0.50 New refCnts for V58: refCnt = 2, refCntWtd = 1 New refCnts for V59: refCnt = 2, refCntWtd = 1 New refCnts for V16: refCnt = 3, refCntWtd = 1.50 New refCnts for V14: refCnt = 3, refCntWtd = 1.50 New refCnts for V15: refCnt = 2, refCntWtd = 1 New refCnts for V56: refCnt = 2, refCntWtd = 1 New refCnts for V64: refCnt = 1, refCntWtd = 0.50 New refCnts for V15: refCnt = 3, refCntWtd = 1.50 New refCnts for V57: refCnt = 2, refCntWtd = 1 New refCnts for V65: refCnt = 1, refCntWtd = 0.50 New refCnts for V76: refCnt = 3, refCntWtd = 3 New refCnts for V81: refCnt = 1, refCntWtd = 1 New refCnts for V81: refCnt = 2, refCntWtd = 2 New refCnts for V64: refCnt = 2, refCntWtd = 1 New refCnts for V81: refCnt = 3, refCntWtd = 3 New refCnts for V65: refCnt = 2, refCntWtd = 1 New refCnts for V76: refCnt = 4, refCntWtd = 4 New refCnts for V45: refCnt = 1, refCntWtd = 0.50 New refCnts for V43: refCnt = 1, refCntWtd = 0.50 New refCnts for V45: refCnt = 2, refCntWtd = 1 New refCnts for V43: refCnt = 2, refCntWtd = 1 New refCnts for V17: refCnt = 1, refCntWtd = 0.50 New refCnts for V16: refCnt = 4, refCntWtd = 2 New refCnts for V58: refCnt = 3, refCntWtd = 1.50 New refCnts for V66: refCnt = 1, refCntWtd = 0.50 New refCnts for V16: refCnt = 5, refCntWtd = 2.50 New refCnts for V59: refCnt = 3, refCntWtd = 1.50 New refCnts for V67: refCnt = 1, refCntWtd = 0.50 New refCnts for V76: refCnt = 5, refCntWtd = 5 New refCnts for V82: refCnt = 1, refCntWtd = 1 New refCnts for V82: refCnt = 2, refCntWtd = 2 New refCnts for V66: refCnt = 2, refCntWtd = 1 New refCnts for V82: refCnt = 3, refCntWtd = 3 New refCnts for V67: refCnt = 2, refCntWtd = 1 New refCnts for V76: refCnt = 6, refCntWtd = 6 New refCnts for V48: refCnt = 1, refCntWtd = 0.50 New refCnts for V46: refCnt = 1, refCntWtd = 0.50 New refCnts for V48: refCnt = 2, refCntWtd = 1 New refCnts for V46: refCnt = 2, refCntWtd = 1 New refCnts for V18: refCnt = 1, refCntWtd = 0.50 New refCnts for V18: refCnt = 2, refCntWtd = 1 New refCnts for V17: refCnt = 2, refCntWtd = 1 New refCnts for V33: refCnt = 1, refCntWtd = 0.50 New refCnts for V18: refCnt = 3, refCntWtd = 1.50 New refCnts for V17: refCnt = 3, refCntWtd = 1.50 New refCnts for V33: refCnt = 2, refCntWtd = 1 New refCnts for V33: refCnt = 3, refCntWtd = 1.50 New refCnts for V19: refCnt = 1, refCntWtd = 0.50 New refCnts for V19: refCnt = 2, refCntWtd = 1 New refCnts for V56: refCnt = 3, refCntWtd = 1.50 New refCnts for V57: refCnt = 3, refCntWtd = 1.50 New refCnts for V15: refCnt = 4, refCntWtd = 2 New refCnts for V19: refCnt = 3, refCntWtd = 1.50 New refCnts for V03: refCnt = 3, refCntWtd = 1.50 New refCnts for V13: refCnt = 5, refCntWtd = 2.50 New refCnts for V20: refCnt = 1, refCntWtd = 0.50 New refCnts for V20: refCnt = 2, refCntWtd = 1 New refCnts for V21: refCnt = 1, refCntWtd = 0.50 New refCnts for V13: refCnt = 6, refCntWtd = 3 New refCnts for V19: refCnt = 4, refCntWtd = 2 New refCnts for V20: refCnt = 3, refCntWtd = 1.50 New refCnts for V02: refCnt = 5, refCntWtd = 2.50 New refCnts for V12: refCnt = 3, refCntWtd = 1.50 New refCnts for V13: refCnt = 7, refCntWtd = 3.50 New refCnts for V01: refCnt = 12, refCntWtd = 6 New refCnts for V51: refCnt = 2, refCntWtd = 2 New refCnts for V20: refCnt = 4, refCntWtd = 2 New refCnts for V19: refCnt = 5, refCntWtd = 2.50 New refCnts for V21: refCnt = 2, refCntWtd = 1 New refCnts for V15: refCnt = 5, refCntWtd = 2.50 New refCnts for V56: refCnt = 4, refCntWtd = 2 New refCnts for V49: refCnt = 1, refCntWtd = 1 New refCnts for V68: refCnt = 1, refCntWtd = 0.50 New refCnts for V15: refCnt = 6, refCntWtd = 3 New refCnts for V57: refCnt = 4, refCntWtd = 2 New refCnts for V49: refCnt = 2, refCntWtd = 2 New refCnts for V69: refCnt = 1, refCntWtd = 0.50 New refCnts for V16: refCnt = 6, refCntWtd = 3 New refCnts for V58: refCnt = 4, refCntWtd = 2 New refCnts for V70: refCnt = 1, refCntWtd = 0.50 New refCnts for V16: refCnt = 7, refCntWtd = 3.50 New refCnts for V59: refCnt = 4, refCntWtd = 2 New refCnts for V71: refCnt = 1, refCntWtd = 0.50 New refCnts for V68: refCnt = 2, refCntWtd = 1.50 New refCnts for V69: refCnt = 2, refCntWtd = 1.50 New refCnts for V49: refCnt = 3, refCntWtd = 3 New refCnts for V84: refCnt = 1, refCntWtd = 1 New refCnts for V76: refCnt = 7, refCntWtd = 7 New refCnts for V83: refCnt = 1, refCntWtd = 1 New refCnts for V83: refCnt = 2, refCntWtd = 2 New refCnts for V70: refCnt = 2, refCntWtd = 1 New refCnts for V83: refCnt = 3, refCntWtd = 3 New refCnts for V71: refCnt = 2, refCntWtd = 1 New refCnts for V84: refCnt = 2, refCntWtd = 2 New refCnts for V76: refCnt = 8, refCntWtd = 8 New refCnts for V19: refCnt = 6, refCntWtd = 3 New refCnts for V34: refCnt = 1, refCntWtd = 0.50 New refCnts for V19: refCnt = 7, refCntWtd = 3.50 New refCnts for V34: refCnt = 2, refCntWtd = 1 New refCnts for V34: refCnt = 3, refCntWtd = 1.50 New refCnts for V22: refCnt = 1, refCntWtd = 0.50 New refCnts for V56: refCnt = 5, refCntWtd = 2.50 New refCnts for V57: refCnt = 5, refCntWtd = 2.50 New refCnts for V15: refCnt = 7, refCntWtd = 3.50 New refCnts for V21: refCnt = 3, refCntWtd = 1.50 New refCnts for V62: refCnt = 1, refCntWtd = 1 New refCnts for V63: refCnt = 1, refCntWtd = 1 New refCnts for V35: refCnt = 1, refCntWtd = 1 New refCnts for V88: refCnt = 1, refCntWtd = 1 New refCnts for V76: refCnt = 9, refCntWtd = 9 New refCnts for V85: refCnt = 1, refCntWtd = 1 New refCnts for V85: refCnt = 2, refCntWtd = 2 New refCnts for V15: refCnt = 8, refCntWtd = 4 New refCnts for V56: refCnt = 6, refCntWtd = 3 New refCnts for V85: refCnt = 3, refCntWtd = 3 New refCnts for V15: refCnt = 9, refCntWtd = 4.50 New refCnts for V57: refCnt = 6, refCntWtd = 3 New refCnts for V86: refCnt = 1, refCntWtd = 1 New refCnts for V87: refCnt = 1, refCntWtd = 1 New refCnts for V87: refCnt = 2, refCntWtd = 2 New refCnts for V16: refCnt = 8, refCntWtd = 4 New refCnts for V58: refCnt = 5, refCntWtd = 2.50 New refCnts for V87: refCnt = 3, refCntWtd = 3 New refCnts for V16: refCnt = 9, refCntWtd = 4.50 New refCnts for V59: refCnt = 5, refCntWtd = 2.50 New refCnts for V88: refCnt = 2, refCntWtd = 2 New refCnts for V76: refCnt = 10, refCntWtd = 10 New refCnts for V86: refCnt = 2, refCntWtd = 2 New refCnts for V60: refCnt = 1, refCntWtd = 0.50 New refCnts for V61: refCnt = 1, refCntWtd = 0.50 New refCnts for V23: refCnt = 1, refCntWtd = 0.50 New refCnts for V76: refCnt = 11, refCntWtd = 11 New refCnts for V89: refCnt = 1, refCntWtd = 1 New refCnts for V89: refCnt = 2, refCntWtd = 2 New refCnts for V35: refCnt = 2, refCntWtd = 2 New refCnts for V62: refCnt = 2, refCntWtd = 1.50 New refCnts for V89: refCnt = 3, refCntWtd = 3 New refCnts for V35: refCnt = 3, refCntWtd = 3 New refCnts for V63: refCnt = 2, refCntWtd = 1.50 New refCnts for V76: refCnt = 12, refCntWtd = 12 New refCnts for V24: refCnt = 1, refCntWtd = 0.50 New refCnts for V23: refCnt = 2, refCntWtd = 1 New refCnts for V61: refCnt = 2, refCntWtd = 1 New refCnts for V25: refCnt = 1, refCntWtd = 0.50 New refCnts for V24: refCnt = 2, refCntWtd = 1 New refCnts for V26: refCnt = 1, refCntWtd = 0.50 New refCnts for V26: refCnt = 2, refCntWtd = 1 New refCnts for V20: refCnt = 5, refCntWtd = 2.50 New refCnts for V26: refCnt = 3, refCntWtd = 1.50 New refCnts for V20: refCnt = 6, refCntWtd = 3 New refCnts for V29: refCnt = 1, refCntWtd = 0.50 New refCnts for V25: refCnt = 2, refCntWtd = 1 New refCnts for V24: refCnt = 3, refCntWtd = 1.50 New refCnts for V29: refCnt = 2, refCntWtd = 1 New refCnts for V37: refCnt = 1, refCntWtd = 0.50 New refCnts for V37: refCnt = 2, refCntWtd = 1 New refCnts for V37: refCnt = 3, refCntWtd = 1.50 New refCnts for V25: refCnt = 3, refCntWtd = 1.50 New refCnts for V24: refCnt = 4, refCntWtd = 2 New refCnts for V29: refCnt = 3, refCntWtd = 1.50 New refCnts for V24: refCnt = 5, refCntWtd = 2.50 New refCnts for V76: refCnt = 13, refCntWtd = 13 New refCnts for V90: refCnt = 1, refCntWtd = 1 New refCnts for V90: refCnt = 2, refCntWtd = 2 New refCnts for V11: refCnt = 5, refCntWtd = 2.50 New refCnts for V54: refCnt = 4, refCntWtd = 2 New refCnts for V90: refCnt = 3, refCntWtd = 3 New refCnts for V11: refCnt = 6, refCntWtd = 3 New refCnts for V55: refCnt = 4, refCntWtd = 2 New refCnts for V76: refCnt = 14, refCntWtd = 14 New refCnts for V20: refCnt = 7, refCntWtd = 3.50 New refCnts for V24: refCnt = 6, refCntWtd = 3 New refCnts for V27: refCnt = 1, refCntWtd = 0.50 New refCnts for V13: refCnt = 8, refCntWtd = 4 New refCnts for V22: refCnt = 2, refCntWtd = 1 New refCnts for V36: refCnt = 1, refCntWtd = 0.50 New refCnts for V13: refCnt = 9, refCntWtd = 4.50 New refCnts for V36: refCnt = 2, refCntWtd = 1 New refCnts for V02: refCnt = 6, refCntWtd = 3 New refCnts for V01: refCnt = 13, refCntWtd = 6.50 New refCnts for V27: refCnt = 2, refCntWtd = 1 New refCnts for V36: refCnt = 3, refCntWtd = 1.50 New refCnts for V25: refCnt = 4, refCntWtd = 2 New refCnts for V51: refCnt = 3, refCntWtd = 3 New refCnts for V51: refCnt = 4, refCntWtd = 4 *** lvaComputeRefCounts -- implicit counts *** New refCnts for V00: refCnt = 3, refCntWtd = 6 New refCnts for V00: refCnt = 4, refCntWtd = 8 New refCnts for V01: refCnt = 14, refCntWtd = 7.50 New refCnts for V01: refCnt = 15, refCntWtd = 8.50 New refCnts for V02: refCnt = 7, refCntWtd = 4 New refCnts for V02: refCnt = 8, refCntWtd = 5 *************** In fgLocalVarLiveness() ; Initial local variable assignments ; ; V00 arg0 byref ld-addr-op ; V01 arg1 ref class-hnd ; V02 arg2 byref ; V03 loc0 int ; V04 loc1 int ; V05 loc2 int ; V06 loc3 int ; V07 loc4 int ; V08 loc5 int ; V09 loc6 int ; V10 loc7 int ; V11 loc8 struct do-not-enreg[XS] addr-exposed ld-addr-op ; V12 loc9 ref do-not-enreg[X] addr-exposed ld-addr-op class-hnd ; V13 loc10 int ; V14 loc11 int ; V15 loc12 struct do-not-enreg[XS] addr-exposed ld-addr-op ; V16 loc13 struct do-not-enreg[XS] addr-exposed ld-addr-op ; V17 loc14 int ; V18 loc15 int ; V19 loc16 int ; V20 loc17 int ; V21 loc18 int ; V22 loc19 int ; V23 loc20 struct do-not-enreg[XS] addr-exposed ld-addr-op ; V24 loc21 long ; V25 loc22 bool ; V26 loc23 int ; V27 loc24 long ; V28 loc25 int ; V29 loc26 int ; V30 OutArgs lclBlk <40> "OutgoingArgSpace" ; V31 tmp1 int "dup spill" ; V32 tmp2 int ; V33 tmp3 int ; V34 tmp4 int ; V35 tmp5 struct do-not-enreg[XS] addr-exposed "struct address for call/obj" ; V36 tmp6 int ; V37 tmp7 int ; V38 tmp8 long "impAppendStmt" ; V39 tmp9 int "Inline return value spill temp" ; V40 tmp10 int "Inlining Arg" ; V41 tmp11 int "Inline return value spill temp" ; V42 tmp12 int "Inlining Arg" ; V43 tmp13 int "Inline return value spill temp" ; V44 tmp14 struct "Inlining Arg" ; V45 tmp15 ref do-not-enreg[X] addr-exposed ld-addr-op class-hnd "Inline ldloca(s) first use temp" ; V46 tmp16 int "Inline return value spill temp" ; V47 tmp17 struct "Inlining Arg" ; V48 tmp18 ref do-not-enreg[X] addr-exposed ld-addr-op class-hnd "Inline ldloca(s) first use temp" ; V49 tmp19 struct do-not-enreg[XS] addr-exposed ld-addr-op "Inlining Arg" ; V50 tmp20 struct "Inlining Arg" ; V51 tmp21 int "Single return block return value" ; V52 tmp22 ref V72.Mantissa(offs=0x00) P-INDEP "field V00.Mantissa (fldOffset=0x0)" ; V53 tmp23 int V72.Exponent(offs=0x08) P-INDEP "field V00.Exponent (fldOffset=0x8)" ; V54 tmp24 ref do-not-enreg[X] addr-exposed V11._bits(offs=0x00) P-DEP "field V11._bits (fldOffset=0x0)" ; V55 tmp25 int do-not-enreg[X] addr-exposed V11._sign(offs=0x08) P-DEP "field V11._sign (fldOffset=0x8)" ; V56 tmp26 ref do-not-enreg[X] addr-exposed V15._bits(offs=0x00) P-DEP "field V15._bits (fldOffset=0x0)" ; V57 tmp27 int do-not-enreg[X] addr-exposed V15._sign(offs=0x08) P-DEP "field V15._sign (fldOffset=0x8)" ; V58 tmp28 ref do-not-enreg[X] addr-exposed V16._bits(offs=0x00) P-DEP "field V16._bits (fldOffset=0x0)" ; V59 tmp29 int do-not-enreg[X] addr-exposed V16._sign(offs=0x08) P-DEP "field V16._sign (fldOffset=0x8)" ; V60 tmp30 ref do-not-enreg[X] addr-exposed V23._bits(offs=0x00) P-DEP "field V23._bits (fldOffset=0x0)" ; V61 tmp31 int do-not-enreg[X] addr-exposed V23._sign(offs=0x08) P-DEP "field V23._sign (fldOffset=0x8)" ; V62 tmp32 ref do-not-enreg[X] addr-exposed V35._bits(offs=0x00) P-DEP "field V35._bits (fldOffset=0x0)" ; V63 tmp33 int do-not-enreg[X] addr-exposed V35._sign(offs=0x08) P-DEP "field V35._sign (fldOffset=0x8)" ; V64 tmp34 ref V44._bits(offs=0x00) P-INDEP "field V44._bits (fldOffset=0x0)" ; V65 tmp35 int V44._sign(offs=0x08) P-INDEP "field V44._sign (fldOffset=0x8)" ; V66 tmp36 ref V47._bits(offs=0x00) P-INDEP "field V47._bits (fldOffset=0x0)" ; V67 tmp37 int V47._sign(offs=0x08) P-INDEP "field V47._sign (fldOffset=0x8)" ; V68 tmp38 ref do-not-enreg[X] addr-exposed V49._bits(offs=0x00) P-DEP "field V49._bits (fldOffset=0x0)" ; V69 tmp39 int do-not-enreg[X] addr-exposed V49._sign(offs=0x08) P-DEP "field V49._sign (fldOffset=0x8)" ; V70 tmp40 ref V50._bits(offs=0x00) P-INDEP "field V50._bits (fldOffset=0x0)" ; V71 tmp41 int V50._sign(offs=0x08) P-INDEP "field V50._sign (fldOffset=0x8)" ; V72 tmp42 struct "Promoted implicit byref" ; V73 tmp43 struct do-not-enreg[XSB] addr-exposed "by-value struct argument" ; V74 tmp44 byref stack-byref "BlockOp address local" ; V75 tmp45 long "argument with side effect" ; V76 tmp46 struct do-not-enreg[XSB] addr-exposed "by-value struct argument" ; V77 tmp47 byref stack-byref "BlockOp address local" ; V78 tmp48 byref stack-byref "BlockOp address local" ; V79 tmp49 long "argument with side effect" ; V80 tmp50 byref "BlockOp address local" ; V81 tmp51 byref stack-byref "BlockOp address local" ; V82 tmp52 byref stack-byref "BlockOp address local" ; V83 tmp53 byref stack-byref "BlockOp address local" ; V84 tmp54 byref "argument with side effect" ; V85 tmp55 byref stack-byref "BlockOp address local" ; V86 tmp56 struct do-not-enreg[XSB] addr-exposed "by-value struct argument" ; V87 tmp57 byref stack-byref "BlockOp address local" ; V88 tmp58 long "argument with side effect" ; V89 tmp59 byref stack-byref "BlockOp address local" ; V90 tmp60 byref stack-byref "BlockOp address local" In fgLocalVarLivenessInit Tracked variable (58 out of 91) table: V01 arg1 [ ref]: refCnt = 15, refCntWtd = 8.50 V00 arg0 [ byref]: refCnt = 4, refCntWtd = 8 V02 arg2 [ byref]: refCnt = 8, refCntWtd = 5 V13 loc10 [ int]: refCnt = 9, refCntWtd = 4.50 V52 tmp22 [ ref]: refCnt = 7, refCntWtd = 4.50 V53 tmp23 [ int]: refCnt = 7, refCntWtd = 4 V31 tmp1 [ int]: refCnt = 4, refCntWtd = 4 V51 tmp21 [ int]: refCnt = 4, refCntWtd = 4 V19 loc16 [ int]: refCnt = 7, refCntWtd = 3.50 V20 loc17 [ int]: refCnt = 7, refCntWtd = 3.50 V24 loc21 [ long]: refCnt = 6, refCntWtd = 3 V74 tmp44 [ byref]: refCnt = 3, refCntWtd = 3 V77 tmp47 [ byref]: refCnt = 3, refCntWtd = 3 V78 tmp48 [ byref]: refCnt = 3, refCntWtd = 3 V80 tmp50 [ byref]: refCnt = 3, refCntWtd = 3 V81 tmp51 [ byref]: refCnt = 3, refCntWtd = 3 V82 tmp52 [ byref]: refCnt = 3, refCntWtd = 3 V83 tmp53 [ byref]: refCnt = 3, refCntWtd = 3 V85 tmp55 [ byref]: refCnt = 3, refCntWtd = 3 V87 tmp57 [ byref]: refCnt = 3, refCntWtd = 3 V89 tmp59 [ byref]: refCnt = 3, refCntWtd = 3 V90 tmp60 [ byref]: refCnt = 3, refCntWtd = 3 V42 tmp12 [ int]: refCnt = 3, refCntWtd = 3 V10 loc7 [ int]: refCnt = 5, refCntWtd = 2.50 V05 loc2 [ int]: refCnt = 4, refCntWtd = 2 V08 loc5 [ int]: refCnt = 4, refCntWtd = 2 V25 loc22 [ bool]: refCnt = 4, refCntWtd = 2 V41 tmp11 [ int]: refCnt = 4, refCntWtd = 2 V84 tmp54 [ byref]: refCnt = 2, refCntWtd = 2 V38 tmp8 [ long]: refCnt = 2, refCntWtd = 2 V40 tmp10 [ int]: refCnt = 2, refCntWtd = 2 V75 tmp45 [ long]: refCnt = 2, refCntWtd = 2 V79 tmp49 [ long]: refCnt = 2, refCntWtd = 2 V88 tmp58 [ long]: refCnt = 2, refCntWtd = 2 V03 loc0 [ int]: refCnt = 3, refCntWtd = 1.50 V09 loc6 [ int]: refCnt = 3, refCntWtd = 1.50 V14 loc11 [ int]: refCnt = 3, refCntWtd = 1.50 V17 loc14 [ int]: refCnt = 3, refCntWtd = 1.50 V18 loc15 [ int]: refCnt = 3, refCntWtd = 1.50 V21 loc18 [ int]: refCnt = 3, refCntWtd = 1.50 V26 loc23 [ int]: refCnt = 3, refCntWtd = 1.50 V29 loc26 [ int]: refCnt = 3, refCntWtd = 1.50 V32 tmp2 [ int]: refCnt = 3, refCntWtd = 1.50 V33 tmp3 [ int]: refCnt = 3, refCntWtd = 1.50 V34 tmp4 [ int]: refCnt = 3, refCntWtd = 1.50 V36 tmp6 [ int]: refCnt = 3, refCntWtd = 1.50 V37 tmp7 [ int]: refCnt = 3, refCntWtd = 1.50 V39 tmp9 [ int]: refCnt = 3, refCntWtd = 1.50 V64 tmp34 [ ref]: refCnt = 2, refCntWtd = 1 V66 tmp36 [ ref]: refCnt = 2, refCntWtd = 1 V70 tmp40 [ ref]: refCnt = 2, refCntWtd = 1 V22 loc19 [ int]: refCnt = 2, refCntWtd = 1 V27 loc24 [ long]: refCnt = 2, refCntWtd = 1 V43 tmp13 [ int]: refCnt = 2, refCntWtd = 1 V46 tmp16 [ int]: refCnt = 2, refCntWtd = 1 V65 tmp35 [ int]: refCnt = 2, refCntWtd = 1 V67 tmp37 [ int]: refCnt = 2, refCntWtd = 1 V71 tmp41 [ int]: refCnt = 2, refCntWtd = 1 *************** In fgPerBlockLocalVarLiveness() BB01 USE(1)={V00 } + ByrefExposed + GcHeap DEF(2)={ V52 V53} BB02 USE(1)={V52} + ByrefExposed + GcHeap DEF(0)={ } BB03 USE(2)={V01 V02} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB04 USE(2)={V01 V53 } + ByrefExposed + GcHeap DEF(2)={ V40 V03} + ByrefExposed* + GcHeap* BB05 USE(1)={V53 } DEF(1)={ V39} BB06 USE(0)={ } DEF(1)={V39} BB07 USE(2)={V52 V39} + ByrefExposed + GcHeap DEF(2)={ V31 V42 } BB08 USE(1)={V42 } DEF(1)={ V41} BB09 USE(1)={V31 } DEF(1)={ V41} BB10 USE(4)={V52 V53 V31 V41 } + ByrefExposed + GcHeap DEF(6)={ V74 V10 V05 V08 V75 V09} + ByrefExposed* + GcHeap* BB11 USE(2)={V01 V05} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB12 USE(2)={V01 V02} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB13 USE(1)={V05} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB14 USE(1)={ V03} + ByrefExposed + GcHeap DEF(2)={V13 V77 } + ByrefExposed* + GcHeap* BB15 USE(1)={V10} DEF(0)={ } BB16 USE(4)={V01 V02 V13 V10} + ByrefExposed + GcHeap DEF(1)={ V51 } + ByrefExposed* + GcHeap* BB17 USE(1)={V53} DEF(0)={ } BB18 USE(1)={V10 } DEF(1)={ V32} BB19 USE(2)={V53 V10 } DEF(1)={ V32} BB20 USE(2)={V13 V32} DEF(1)={ V14 } BB21 USE(3)={V01 V52 V14} + ByrefExposed + GcHeap DEF(1)={ V38 } + ByrefExposed* + GcHeap* BB22 USE(2)={V01 V02} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB23 USE(5)={V52 V53 V08 V09 V14 } + ByrefExposed + GcHeap DEF(13)={ V78 V80 V81 V82 V79 V17 V18 V64 V66 V43 V46 V65 V67} + ByrefExposed* + GcHeap* BB24 USE(0)={ } DEF(1)={V33} BB25 USE(2)={V17 V18 } DEF(1)={ V33} BB26 USE(1)={ V33} DEF(1)={V19 } BB27 USE(1)={V19} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB28 USE(2)={V13 V03 } DEF(2)={ V20 V21} BB29 USE(2)={V19 V20} DEF(0)={ } BB30 USE(3)={V01 V02 V13 } + ByrefExposed + GcHeap DEF(1)={ V51} + ByrefExposed* + GcHeap* BB31 USE(2)={V19 V20 } DEF(1)={ V21} BB32 USE(0)={ } + ByrefExposed + GcHeap DEF(4)={V83 V84 V70 V71} + ByrefExposed* + GcHeap* BB33 USE(1)={V19 } DEF(1)={ V34} BB34 USE(1)={V19 } DEF(1)={ V34} BB35 USE(3)={V20 V21 V34 } + ByrefExposed + GcHeap DEF(8)={ V24 V85 V87 V89 V25 V88 V26 V22} + ByrefExposed* + GcHeap* BB36 USE(3)={V20 V25 V26 } DEF(1)={ V29} BB37 USE(2)={V24 V29 } DEF(1)={ V37} BB38 USE(0)={ } DEF(1)={V37} BB39 USE(3)={V24 V29 V37} DEF(2)={V24 V25 } BB40 USE(3)={V13 V20 V24 } + ByrefExposed + GcHeap DEF(2)={ V90 V27} + ByrefExposed* + GcHeap* BB41 USE(1)={ V22} DEF(1)={V36 } BB42 USE(1)={V13 } DEF(1)={ V36} BB43 USE(5)={V01 V02 V25 V36 V27} + ByrefExposed + GcHeap DEF(1)={ V51 } + ByrefExposed* + GcHeap* BB44 USE(1)={V51} DEF(0)={ } ** Memory liveness computed, GcHeap states and ByrefExposed states diverge *************** In fgInterBlockLocalVarLiveness() BB liveness after fgLiveVarAnalysis(): BB01 IN (3)={V01 V00 V02 } + ByrefExposed + GcHeap OUT(4)={V01 V02 V52 V53} + ByrefExposed + GcHeap BB02 IN (4)={V01 V02 V52 V53} + ByrefExposed + GcHeap OUT(4)={V01 V02 V52 V53} + ByrefExposed + GcHeap BB03 IN (2)={V01 V02} + ByrefExposed + GcHeap OUT(0)={ } BB04 IN (4)={V01 V02 V52 V53 } + ByrefExposed + GcHeap OUT(5)={V01 V02 V52 V53 V03} + ByrefExposed + GcHeap BB05 IN (5)={V01 V02 V52 V53 V03 } + ByrefExposed + GcHeap OUT(6)={V01 V02 V52 V53 V03 V39} + ByrefExposed + GcHeap BB06 IN (5)={V01 V02 V52 V53 V03 } + ByrefExposed + GcHeap OUT(6)={V01 V02 V52 V53 V03 V39} + ByrefExposed + GcHeap BB07 IN (6)={V01 V02 V52 V53 V03 V39} + ByrefExposed + GcHeap OUT(7)={V01 V02 V52 V53 V31 V42 V03 } + ByrefExposed + GcHeap BB08 IN (7)={V01 V02 V52 V53 V31 V42 V03} + ByrefExposed + GcHeap OUT(7)={V01 V02 V52 V53 V31 V41 V03} + ByrefExposed + GcHeap BB09 IN (6)={V01 V02 V52 V53 V31 V03} + ByrefExposed + GcHeap OUT(7)={V01 V02 V52 V53 V31 V41 V03} + ByrefExposed + GcHeap BB10 IN (7)={V01 V02 V52 V53 V31 V41 V03 } + ByrefExposed + GcHeap OUT(9)={V01 V02 V52 V53 V10 V05 V08 V03 V09} + ByrefExposed + GcHeap BB11 IN (9)={V01 V02 V52 V53 V10 V05 V08 V03 V09} + ByrefExposed + GcHeap OUT(9)={V01 V02 V52 V53 V10 V05 V08 V03 V09} + ByrefExposed + GcHeap BB12 IN (2)={V01 V02} + ByrefExposed + GcHeap OUT(0)={ } BB13 IN (9)={V01 V02 V52 V53 V10 V05 V08 V03 V09} + ByrefExposed + GcHeap OUT(8)={V01 V02 V52 V53 V10 V08 V03 V09} + ByrefExposed + GcHeap BB14 IN (8)={V01 V02 V52 V53 V10 V08 V03 V09} + ByrefExposed + GcHeap OUT(9)={V01 V02 V13 V52 V53 V10 V08 V03 V09} + ByrefExposed + GcHeap BB15 IN (9)={V01 V02 V13 V52 V53 V10 V08 V03 V09} + ByrefExposed + GcHeap OUT(9)={V01 V02 V13 V52 V53 V10 V08 V03 V09} + ByrefExposed + GcHeap BB16 IN (4)={V01 V02 V13 V10} + ByrefExposed + GcHeap OUT(1)={ V51 } BB17 IN (9)={V01 V02 V13 V52 V53 V10 V08 V03 V09} + ByrefExposed + GcHeap OUT(9)={V01 V02 V13 V52 V53 V10 V08 V03 V09} + ByrefExposed + GcHeap BB18 IN (9)={V01 V02 V13 V52 V53 V10 V08 V03 V09 } + ByrefExposed + GcHeap OUT(9)={V01 V02 V13 V52 V53 V08 V03 V09 V32} + ByrefExposed + GcHeap BB19 IN (9)={V01 V02 V13 V52 V53 V10 V08 V03 V09 } + ByrefExposed + GcHeap OUT(9)={V01 V02 V13 V52 V53 V08 V03 V09 V32} + ByrefExposed + GcHeap BB20 IN (9)={V01 V02 V13 V52 V53 V08 V03 V09 V32} + ByrefExposed + GcHeap OUT(9)={V01 V02 V13 V52 V53 V08 V03 V09 V14 } + ByrefExposed + GcHeap BB21 IN (9)={V01 V02 V13 V52 V53 V08 V03 V09 V14} + ByrefExposed + GcHeap OUT(9)={V01 V02 V13 V52 V53 V08 V03 V09 V14} + ByrefExposed + GcHeap BB22 IN (2)={V01 V02} + ByrefExposed + GcHeap OUT(0)={ } BB23 IN (9)={V01 V02 V13 V52 V53 V08 V03 V09 V14 } + ByrefExposed + GcHeap OUT(6)={V01 V02 V13 V03 V17 V18} + ByrefExposed + GcHeap BB24 IN (4)={V01 V02 V13 V03 } + ByrefExposed + GcHeap OUT(5)={V01 V02 V13 V03 V33} + ByrefExposed + GcHeap BB25 IN (6)={V01 V02 V13 V03 V17 V18 } + ByrefExposed + GcHeap OUT(5)={V01 V02 V13 V03 V33} + ByrefExposed + GcHeap BB26 IN (5)={V01 V02 V13 V03 V33} + ByrefExposed + GcHeap OUT(5)={V01 V02 V13 V19 V03 } + ByrefExposed + GcHeap BB27 IN (5)={V01 V02 V13 V19 V03} + ByrefExposed + GcHeap OUT(5)={V01 V02 V13 V19 V03} + ByrefExposed + GcHeap BB28 IN (5)={V01 V02 V13 V19 V03 } + ByrefExposed + GcHeap OUT(6)={V01 V02 V13 V19 V20 V21} + ByrefExposed + GcHeap BB29 IN (5)={V01 V02 V13 V19 V20} + ByrefExposed + GcHeap OUT(5)={V01 V02 V13 V19 V20} + ByrefExposed + GcHeap BB30 IN (3)={V01 V02 V13 } + ByrefExposed + GcHeap OUT(1)={ V51} BB31 IN (5)={V01 V02 V13 V19 V20 } + ByrefExposed + GcHeap OUT(6)={V01 V02 V13 V19 V20 V21} + ByrefExposed + GcHeap BB32 IN (6)={V01 V02 V13 V19 V20 V21} + ByrefExposed + GcHeap OUT(6)={V01 V02 V13 V19 V20 V21} + ByrefExposed + GcHeap BB33 IN (6)={V01 V02 V13 V19 V20 V21 } + ByrefExposed + GcHeap OUT(6)={V01 V02 V13 V20 V21 V34} + ByrefExposed + GcHeap BB34 IN (6)={V01 V02 V13 V19 V20 V21 } + ByrefExposed + GcHeap OUT(6)={V01 V02 V13 V20 V21 V34} + ByrefExposed + GcHeap BB35 IN (6)={V01 V02 V13 V20 V21 V34 } + ByrefExposed + GcHeap OUT(8)={V01 V02 V13 V20 V24 V25 V26 V22} + ByrefExposed + GcHeap BB36 IN (8)={V01 V02 V13 V20 V24 V25 V26 V22} + ByrefExposed + GcHeap OUT(7)={V01 V02 V13 V20 V24 V29 V22} + ByrefExposed + GcHeap BB37 IN (7)={V01 V02 V13 V20 V24 V29 V22} + ByrefExposed + GcHeap OUT(8)={V01 V02 V13 V20 V24 V29 V37 V22} + ByrefExposed + GcHeap BB38 IN (7)={V01 V02 V13 V20 V24 V29 V22} + ByrefExposed + GcHeap OUT(8)={V01 V02 V13 V20 V24 V29 V37 V22} + ByrefExposed + GcHeap BB39 IN (8)={V01 V02 V13 V20 V24 V29 V37 V22} + ByrefExposed + GcHeap OUT(7)={V01 V02 V13 V20 V24 V25 V22} + ByrefExposed + GcHeap BB40 IN (7)={V01 V02 V13 V20 V24 V25 V22 } + ByrefExposed + GcHeap OUT(6)={V01 V02 V13 V25 V22 V27} + ByrefExposed + GcHeap BB41 IN (5)={V01 V02 V25 V22 V27} + ByrefExposed + GcHeap OUT(5)={V01 V02 V25 V36 V27} + ByrefExposed + GcHeap BB42 IN (5)={V01 V02 V13 V25 V27} + ByrefExposed + GcHeap OUT(5)={V01 V02 V25 V36 V27} + ByrefExposed + GcHeap BB43 IN (5)={V01 V02 V25 V36 V27} + ByrefExposed + GcHeap OUT(1)={ V51 } BB44 IN (1)={V51} OUT(0)={ } *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0056] 1 1 [???..???) i internal label target LIR BB02 [0000] 1 BB01 1 [000..00D)-> BB04 ( cond ) i label target idxlen LIR BB03 [0001] 1 BB02 0.50 [00D..017) (return) i hascall gcsafe LIR BB04 [0002] 1 BB02 0.50 [017..065)-> BB06 ( cond ) i label target hascall gcsafe LIR BB05 [0038] 1 BB04 0.50 [020..021)-> BB07 (always) i gcsafe LIR BB06 [0039] 1 BB04 0.50 [020..021) i label target gcsafe LIR BB07 [0040] 2 BB05,BB06 0.50 [000..000)-> BB09 ( cond ) i internal label target gcsafe idxlen LIR BB08 [0043] 1 BB07 0.50 [000..000)-> BB10 (always) i internal gcsafe LIR BB09 [0044] 1 BB07 0.50 [000..000) i internal label target gcsafe LIR BB10 [0045] 2 BB08,BB09 0.50 [???..???)-> BB14 ( cond ) i internal label target hascall gcsafe idxlen LIR BB11 [0003] 1 BB10 0.50 [065..070)-> BB13 ( cond ) i hascall gcsafe LIR BB12 [0004] 1 BB11 0.50 [070..07A) (return) i hascall gcsafe LIR BB13 [0005] 1 BB11 0.50 [07A..082) i label target hascall gcsafe LIR BB14 [0006] 2 BB10,BB13 0.50 [082..092)-> BB16 ( cond ) i label target hascall gcsafe LIR BB15 [0007] 1 BB14 0.50 [092..096)-> BB17 ( cond ) i gcsafe LIR BB16 [0008] 2 BB14,BB15 0.50 [096..0A7)-> BB44 (always) i label target hascall gcsafe LIR BB17 [0009] 1 BB15 0.50 [0A7..0B0)-> BB19 ( cond ) i label target gcsafe LIR BB18 [0010] 1 BB17 0.50 [0B0..0B4)-> BB20 (always) i gcsafe LIR BB19 [0011] 1 BB17 0.50 [0B4..0BE) i label target gcsafe LIR BB20 [0012] 2 BB18,BB19 0.50 [0BE..0C4)-> BB23 ( cond ) i label target gcsafe LIR BB21 [0013] 1 BB20 0.50 [0C4..0D9)-> BB23 ( cond ) i hascall gcsafe idxlen LIR BB22 [0014] 1 BB21 0.50 [0D9..0E3) (return) i hascall gcsafe LIR BB23 [0015] 2 BB20,BB21 0.50 [0E3..117)-> BB25 ( cond ) i label target hascall gcsafe LIR BB24 [0016] 1 BB23 0.50 [117..11A)-> BB26 (always) i gcsafe LIR BB25 [0017] 1 BB23 0.50 [11A..11F) i label target gcsafe LIR BB26 [0018] 2 BB24,BB25 0.50 [11F..126)-> BB28 ( cond ) i label target gcsafe LIR BB27 [0019] 1 BB26 0.50 [126..12F) i hascall gcsafe LIR BB28 [0020] 2 BB26,BB27 0.50 [12F..13E)-> BB32 ( cond ) i label target gcsafe LIR BB29 [0021] 1 BB28 0.50 [13E..144)-> BB31 ( cond ) i gcsafe LIR BB30 [0022] 1 BB29 0.50 [144..155)-> BB44 (always) i hascall gcsafe LIR BB31 [0023] 1 BB29 0.50 [155..15C) i label target gcsafe LIR BB32 [0024] 2 BB28,BB31 0.50 [15C..167)-> BB34 ( cond ) i label target hascall gcsafe LIR BB33 [0025] 1 BB32 0.50 [167..16B)-> BB35 (always) i gcsafe LIR BB34 [0026] 1 BB32 0.50 [16B..16F) i label target gcsafe LIR BB35 [0027] 2 BB33,BB34 0.50 [16F..1A4)-> BB40 ( cond ) i label target hascall gcsafe LIR BB36 [0028] 1 BB35 0.50 [1A4..1AF)-> BB38 ( cond ) i gcsafe LIR BB37 [0029] 1 BB36 0.50 [1AF..1C3)-> BB39 (always) i gcsafe LIR BB38 [0030] 1 BB36 0.50 [1C3..1C4) i label target gcsafe LIR BB39 [0031] 2 BB37,BB38 0.50 [1C4..1D0) i label target gcsafe LIR BB40 [0032] 2 BB35,BB39 0.50 [1D0..1E7)-> BB42 ( cond ) i label target hascall gcsafe LIR BB41 [0033] 1 BB40 0.50 [1E7..1EE)-> BB43 (always) i gcsafe LIR BB42 [0034] 1 BB40 0.50 [1EE..1F2) i label target gcsafe LIR BB43 [0035] 2 BB41,BB42 0.50 [1F2..202) i label target hascall gcsafe LIR BB44 [0054] 3 BB16,BB30,BB43 0.50 [???..???) (return) keep internal target gcsafe LIR ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *** lvaComputeRefCounts *** *** lvaComputeRefCounts -- explicit counts *** New refCnts for V00: refCnt = 1, refCntWtd = 2 New refCnts for V52: refCnt = 1, refCntWtd = 1 New refCnts for V00: refCnt = 2, refCntWtd = 4 New refCnts for V53: refCnt = 1, refCntWtd = 1 New refCnts for V52: refCnt = 2, refCntWtd = 2 New refCnts for V01: refCnt = 1, refCntWtd = 0.50 New refCnts for V01: refCnt = 2, refCntWtd = 1 New refCnts for V02: refCnt = 1, refCntWtd = 0.50 New refCnts for V01: refCnt = 3, refCntWtd = 1.50 New refCnts for V01: refCnt = 4, refCntWtd = 2 New refCnts for V03: refCnt = 1, refCntWtd = 0.50 New refCnts for V53: refCnt = 2, refCntWtd = 1.50 New refCnts for V40: refCnt = 1, refCntWtd = 1 New refCnts for V40: refCnt = 2, refCntWtd = 2 New refCnts for V53: refCnt = 3, refCntWtd = 2 New refCnts for V39: refCnt = 1, refCntWtd = 0.50 New refCnts for V39: refCnt = 2, refCntWtd = 1 New refCnts for V39: refCnt = 3, refCntWtd = 1.50 New refCnts for V31: refCnt = 1, refCntWtd = 1 New refCnts for V52: refCnt = 3, refCntWtd = 2.50 New refCnts for V42: refCnt = 1, refCntWtd = 1 New refCnts for V31: refCnt = 2, refCntWtd = 2 New refCnts for V42: refCnt = 2, refCntWtd = 2 New refCnts for V42: refCnt = 3, refCntWtd = 3 New refCnts for V41: refCnt = 1, refCntWtd = 0.50 New refCnts for V31: refCnt = 3, refCntWtd = 3 New refCnts for V41: refCnt = 2, refCntWtd = 1 New refCnts for V31: refCnt = 4, refCntWtd = 4 New refCnts for V41: refCnt = 3, refCntWtd = 1.50 New refCnts for V05: refCnt = 1, refCntWtd = 0.50 New refCnts for V41: refCnt = 4, refCntWtd = 2 New refCnts for V08: refCnt = 1, refCntWtd = 0.50 New refCnts for V52: refCnt = 4, refCntWtd = 3 New refCnts for V09: refCnt = 1, refCntWtd = 0.50 New refCnts for V09: refCnt = 2, refCntWtd = 1 New refCnts for V08: refCnt = 2, refCntWtd = 1 New refCnts for V10: refCnt = 1, refCntWtd = 0.50 New refCnts for V54: refCnt = 1, refCntWtd = 0.50 New refCnts for V55: refCnt = 1, refCntWtd = 0.50 New refCnts for V11: refCnt = 1, refCntWtd = 0.50 New refCnts for V75: refCnt = 1, refCntWtd = 1 New refCnts for V73: refCnt = 1, refCntWtd = 1 New refCnts for V74: refCnt = 1, refCntWtd = 1 New refCnts for V74: refCnt = 2, refCntWtd = 2 New refCnts for V52: refCnt = 5, refCntWtd = 3.50 New refCnts for V74: refCnt = 3, refCntWtd = 3 New refCnts for V53: refCnt = 4, refCntWtd = 2.50 New refCnts for V75: refCnt = 2, refCntWtd = 2 New refCnts for V73: refCnt = 2, refCntWtd = 2 New refCnts for V08: refCnt = 3, refCntWtd = 1.50 New refCnts for V05: refCnt = 2, refCntWtd = 1 New refCnts for V01: refCnt = 5, refCntWtd = 2.50 New refCnts for V05: refCnt = 3, refCntWtd = 1.50 New refCnts for V01: refCnt = 6, refCntWtd = 3 New refCnts for V01: refCnt = 7, refCntWtd = 3.50 New refCnts for V02: refCnt = 2, refCntWtd = 1 New refCnts for V54: refCnt = 2, refCntWtd = 1 New refCnts for V55: refCnt = 2, refCntWtd = 1 New refCnts for V11: refCnt = 2, refCntWtd = 1 New refCnts for V05: refCnt = 4, refCntWtd = 2 New refCnts for V76: refCnt = 1, refCntWtd = 1 New refCnts for V77: refCnt = 1, refCntWtd = 1 New refCnts for V77: refCnt = 2, refCntWtd = 2 New refCnts for V11: refCnt = 3, refCntWtd = 1.50 New refCnts for V54: refCnt = 3, refCntWtd = 1.50 New refCnts for V77: refCnt = 3, refCntWtd = 3 New refCnts for V11: refCnt = 4, refCntWtd = 2 New refCnts for V55: refCnt = 3, refCntWtd = 1.50 New refCnts for V76: refCnt = 2, refCntWtd = 2 New refCnts for V12: refCnt = 1, refCntWtd = 0.50 New refCnts for V13: refCnt = 1, refCntWtd = 0.50 New refCnts for V13: refCnt = 2, refCntWtd = 1 New refCnts for V03: refCnt = 2, refCntWtd = 1 New refCnts for V10: refCnt = 2, refCntWtd = 1 New refCnts for V02: refCnt = 3, refCntWtd = 1.50 New refCnts for V10: refCnt = 3, refCntWtd = 1.50 New refCnts for V12: refCnt = 2, refCntWtd = 1 New refCnts for V13: refCnt = 3, refCntWtd = 1.50 New refCnts for V01: refCnt = 8, refCntWtd = 4 New refCnts for V51: refCnt = 1, refCntWtd = 1 New refCnts for V53: refCnt = 5, refCntWtd = 3 New refCnts for V10: refCnt = 4, refCntWtd = 2 New refCnts for V32: refCnt = 1, refCntWtd = 0.50 New refCnts for V10: refCnt = 5, refCntWtd = 2.50 New refCnts for V53: refCnt = 6, refCntWtd = 3.50 New refCnts for V32: refCnt = 2, refCntWtd = 1 New refCnts for V32: refCnt = 3, refCntWtd = 1.50 New refCnts for V14: refCnt = 1, refCntWtd = 0.50 New refCnts for V13: refCnt = 4, refCntWtd = 2 New refCnts for V52: refCnt = 6, refCntWtd = 4 New refCnts for V14: refCnt = 2, refCntWtd = 1 New refCnts for V38: refCnt = 1, refCntWtd = 1 New refCnts for V01: refCnt = 9, refCntWtd = 4.50 New refCnts for V38: refCnt = 2, refCntWtd = 2 New refCnts for V01: refCnt = 10, refCntWtd = 5 New refCnts for V01: refCnt = 11, refCntWtd = 5.50 New refCnts for V02: refCnt = 4, refCntWtd = 2 New refCnts for V56: refCnt = 1, refCntWtd = 0.50 New refCnts for V57: refCnt = 1, refCntWtd = 0.50 New refCnts for V15: refCnt = 1, refCntWtd = 0.50 New refCnts for V79: refCnt = 1, refCntWtd = 1 New refCnts for V73: refCnt = 3, refCntWtd = 3 New refCnts for V78: refCnt = 1, refCntWtd = 1 New refCnts for V78: refCnt = 2, refCntWtd = 2 New refCnts for V52: refCnt = 7, refCntWtd = 4.50 New refCnts for V78: refCnt = 3, refCntWtd = 3 New refCnts for V53: refCnt = 7, refCntWtd = 4 New refCnts for V79: refCnt = 2, refCntWtd = 2 New refCnts for V73: refCnt = 4, refCntWtd = 4 New refCnts for V08: refCnt = 4, refCntWtd = 2 New refCnts for V09: refCnt = 3, refCntWtd = 1.50 New refCnts for V80: refCnt = 1, refCntWtd = 1 New refCnts for V80: refCnt = 2, refCntWtd = 2 New refCnts for V16: refCnt = 1, refCntWtd = 0.50 New refCnts for V58: refCnt = 1, refCntWtd = 0.50 New refCnts for V80: refCnt = 3, refCntWtd = 3 New refCnts for V16: refCnt = 2, refCntWtd = 1 New refCnts for V59: refCnt = 1, refCntWtd = 0.50 New refCnts for V58: refCnt = 2, refCntWtd = 1 New refCnts for V59: refCnt = 2, refCntWtd = 1 New refCnts for V16: refCnt = 3, refCntWtd = 1.50 New refCnts for V14: refCnt = 3, refCntWtd = 1.50 New refCnts for V15: refCnt = 2, refCntWtd = 1 New refCnts for V56: refCnt = 2, refCntWtd = 1 New refCnts for V64: refCnt = 1, refCntWtd = 0.50 New refCnts for V15: refCnt = 3, refCntWtd = 1.50 New refCnts for V57: refCnt = 2, refCntWtd = 1 New refCnts for V65: refCnt = 1, refCntWtd = 0.50 New refCnts for V76: refCnt = 3, refCntWtd = 3 New refCnts for V81: refCnt = 1, refCntWtd = 1 New refCnts for V81: refCnt = 2, refCntWtd = 2 New refCnts for V64: refCnt = 2, refCntWtd = 1 New refCnts for V81: refCnt = 3, refCntWtd = 3 New refCnts for V65: refCnt = 2, refCntWtd = 1 New refCnts for V76: refCnt = 4, refCntWtd = 4 New refCnts for V45: refCnt = 1, refCntWtd = 0.50 New refCnts for V43: refCnt = 1, refCntWtd = 0.50 New refCnts for V45: refCnt = 2, refCntWtd = 1 New refCnts for V43: refCnt = 2, refCntWtd = 1 New refCnts for V17: refCnt = 1, refCntWtd = 0.50 New refCnts for V16: refCnt = 4, refCntWtd = 2 New refCnts for V58: refCnt = 3, refCntWtd = 1.50 New refCnts for V66: refCnt = 1, refCntWtd = 0.50 New refCnts for V16: refCnt = 5, refCntWtd = 2.50 New refCnts for V59: refCnt = 3, refCntWtd = 1.50 New refCnts for V67: refCnt = 1, refCntWtd = 0.50 New refCnts for V76: refCnt = 5, refCntWtd = 5 New refCnts for V82: refCnt = 1, refCntWtd = 1 New refCnts for V82: refCnt = 2, refCntWtd = 2 New refCnts for V66: refCnt = 2, refCntWtd = 1 New refCnts for V82: refCnt = 3, refCntWtd = 3 New refCnts for V67: refCnt = 2, refCntWtd = 1 New refCnts for V76: refCnt = 6, refCntWtd = 6 New refCnts for V48: refCnt = 1, refCntWtd = 0.50 New refCnts for V46: refCnt = 1, refCntWtd = 0.50 New refCnts for V48: refCnt = 2, refCntWtd = 1 New refCnts for V46: refCnt = 2, refCntWtd = 1 New refCnts for V18: refCnt = 1, refCntWtd = 0.50 New refCnts for V18: refCnt = 2, refCntWtd = 1 New refCnts for V17: refCnt = 2, refCntWtd = 1 New refCnts for V33: refCnt = 1, refCntWtd = 0.50 New refCnts for V18: refCnt = 3, refCntWtd = 1.50 New refCnts for V17: refCnt = 3, refCntWtd = 1.50 New refCnts for V33: refCnt = 2, refCntWtd = 1 New refCnts for V33: refCnt = 3, refCntWtd = 1.50 New refCnts for V19: refCnt = 1, refCntWtd = 0.50 New refCnts for V19: refCnt = 2, refCntWtd = 1 New refCnts for V56: refCnt = 3, refCntWtd = 1.50 New refCnts for V57: refCnt = 3, refCntWtd = 1.50 New refCnts for V15: refCnt = 4, refCntWtd = 2 New refCnts for V19: refCnt = 3, refCntWtd = 1.50 New refCnts for V03: refCnt = 3, refCntWtd = 1.50 New refCnts for V13: refCnt = 5, refCntWtd = 2.50 New refCnts for V20: refCnt = 1, refCntWtd = 0.50 New refCnts for V20: refCnt = 2, refCntWtd = 1 New refCnts for V21: refCnt = 1, refCntWtd = 0.50 New refCnts for V13: refCnt = 6, refCntWtd = 3 New refCnts for V19: refCnt = 4, refCntWtd = 2 New refCnts for V20: refCnt = 3, refCntWtd = 1.50 New refCnts for V02: refCnt = 5, refCntWtd = 2.50 New refCnts for V12: refCnt = 3, refCntWtd = 1.50 New refCnts for V13: refCnt = 7, refCntWtd = 3.50 New refCnts for V01: refCnt = 12, refCntWtd = 6 New refCnts for V51: refCnt = 2, refCntWtd = 2 New refCnts for V20: refCnt = 4, refCntWtd = 2 New refCnts for V19: refCnt = 5, refCntWtd = 2.50 New refCnts for V21: refCnt = 2, refCntWtd = 1 New refCnts for V15: refCnt = 5, refCntWtd = 2.50 New refCnts for V56: refCnt = 4, refCntWtd = 2 New refCnts for V49: refCnt = 1, refCntWtd = 1 New refCnts for V68: refCnt = 1, refCntWtd = 0.50 New refCnts for V15: refCnt = 6, refCntWtd = 3 New refCnts for V57: refCnt = 4, refCntWtd = 2 New refCnts for V49: refCnt = 2, refCntWtd = 2 New refCnts for V69: refCnt = 1, refCntWtd = 0.50 New refCnts for V16: refCnt = 6, refCntWtd = 3 New refCnts for V58: refCnt = 4, refCntWtd = 2 New refCnts for V70: refCnt = 1, refCntWtd = 0.50 New refCnts for V16: refCnt = 7, refCntWtd = 3.50 New refCnts for V59: refCnt = 4, refCntWtd = 2 New refCnts for V71: refCnt = 1, refCntWtd = 0.50 New refCnts for V68: refCnt = 2, refCntWtd = 1.50 New refCnts for V69: refCnt = 2, refCntWtd = 1.50 New refCnts for V49: refCnt = 3, refCntWtd = 3 New refCnts for V84: refCnt = 1, refCntWtd = 1 New refCnts for V76: refCnt = 7, refCntWtd = 7 New refCnts for V83: refCnt = 1, refCntWtd = 1 New refCnts for V83: refCnt = 2, refCntWtd = 2 New refCnts for V70: refCnt = 2, refCntWtd = 1 New refCnts for V83: refCnt = 3, refCntWtd = 3 New refCnts for V71: refCnt = 2, refCntWtd = 1 New refCnts for V84: refCnt = 2, refCntWtd = 2 New refCnts for V76: refCnt = 8, refCntWtd = 8 New refCnts for V19: refCnt = 6, refCntWtd = 3 New refCnts for V34: refCnt = 1, refCntWtd = 0.50 New refCnts for V19: refCnt = 7, refCntWtd = 3.50 New refCnts for V34: refCnt = 2, refCntWtd = 1 New refCnts for V34: refCnt = 3, refCntWtd = 1.50 New refCnts for V22: refCnt = 1, refCntWtd = 0.50 New refCnts for V56: refCnt = 5, refCntWtd = 2.50 New refCnts for V57: refCnt = 5, refCntWtd = 2.50 New refCnts for V15: refCnt = 7, refCntWtd = 3.50 New refCnts for V21: refCnt = 3, refCntWtd = 1.50 New refCnts for V62: refCnt = 1, refCntWtd = 1 New refCnts for V63: refCnt = 1, refCntWtd = 1 New refCnts for V35: refCnt = 1, refCntWtd = 1 New refCnts for V88: refCnt = 1, refCntWtd = 1 New refCnts for V76: refCnt = 9, refCntWtd = 9 New refCnts for V85: refCnt = 1, refCntWtd = 1 New refCnts for V85: refCnt = 2, refCntWtd = 2 New refCnts for V15: refCnt = 8, refCntWtd = 4 New refCnts for V56: refCnt = 6, refCntWtd = 3 New refCnts for V85: refCnt = 3, refCntWtd = 3 New refCnts for V15: refCnt = 9, refCntWtd = 4.50 New refCnts for V57: refCnt = 6, refCntWtd = 3 New refCnts for V86: refCnt = 1, refCntWtd = 1 New refCnts for V87: refCnt = 1, refCntWtd = 1 New refCnts for V87: refCnt = 2, refCntWtd = 2 New refCnts for V16: refCnt = 8, refCntWtd = 4 New refCnts for V58: refCnt = 5, refCntWtd = 2.50 New refCnts for V87: refCnt = 3, refCntWtd = 3 New refCnts for V16: refCnt = 9, refCntWtd = 4.50 New refCnts for V59: refCnt = 5, refCntWtd = 2.50 New refCnts for V88: refCnt = 2, refCntWtd = 2 New refCnts for V76: refCnt = 10, refCntWtd = 10 New refCnts for V86: refCnt = 2, refCntWtd = 2 New refCnts for V60: refCnt = 1, refCntWtd = 0.50 New refCnts for V61: refCnt = 1, refCntWtd = 0.50 New refCnts for V23: refCnt = 1, refCntWtd = 0.50 New refCnts for V76: refCnt = 11, refCntWtd = 11 New refCnts for V89: refCnt = 1, refCntWtd = 1 New refCnts for V89: refCnt = 2, refCntWtd = 2 New refCnts for V35: refCnt = 2, refCntWtd = 2 New refCnts for V62: refCnt = 2, refCntWtd = 1.50 New refCnts for V89: refCnt = 3, refCntWtd = 3 New refCnts for V35: refCnt = 3, refCntWtd = 3 New refCnts for V63: refCnt = 2, refCntWtd = 1.50 New refCnts for V76: refCnt = 12, refCntWtd = 12 New refCnts for V24: refCnt = 1, refCntWtd = 0.50 New refCnts for V23: refCnt = 2, refCntWtd = 1 New refCnts for V61: refCnt = 2, refCntWtd = 1 New refCnts for V25: refCnt = 1, refCntWtd = 0.50 New refCnts for V24: refCnt = 2, refCntWtd = 1 New refCnts for V26: refCnt = 1, refCntWtd = 0.50 New refCnts for V26: refCnt = 2, refCntWtd = 1 New refCnts for V20: refCnt = 5, refCntWtd = 2.50 New refCnts for V26: refCnt = 3, refCntWtd = 1.50 New refCnts for V20: refCnt = 6, refCntWtd = 3 New refCnts for V29: refCnt = 1, refCntWtd = 0.50 New refCnts for V25: refCnt = 2, refCntWtd = 1 New refCnts for V24: refCnt = 3, refCntWtd = 1.50 New refCnts for V29: refCnt = 2, refCntWtd = 1 New refCnts for V37: refCnt = 1, refCntWtd = 0.50 New refCnts for V37: refCnt = 2, refCntWtd = 1 New refCnts for V37: refCnt = 3, refCntWtd = 1.50 New refCnts for V25: refCnt = 3, refCntWtd = 1.50 New refCnts for V24: refCnt = 4, refCntWtd = 2 New refCnts for V29: refCnt = 3, refCntWtd = 1.50 New refCnts for V24: refCnt = 5, refCntWtd = 2.50 New refCnts for V76: refCnt = 13, refCntWtd = 13 New refCnts for V90: refCnt = 1, refCntWtd = 1 New refCnts for V90: refCnt = 2, refCntWtd = 2 New refCnts for V11: refCnt = 5, refCntWtd = 2.50 New refCnts for V54: refCnt = 4, refCntWtd = 2 New refCnts for V90: refCnt = 3, refCntWtd = 3 New refCnts for V11: refCnt = 6, refCntWtd = 3 New refCnts for V55: refCnt = 4, refCntWtd = 2 New refCnts for V76: refCnt = 14, refCntWtd = 14 New refCnts for V20: refCnt = 7, refCntWtd = 3.50 New refCnts for V24: refCnt = 6, refCntWtd = 3 New refCnts for V27: refCnt = 1, refCntWtd = 0.50 New refCnts for V13: refCnt = 8, refCntWtd = 4 New refCnts for V22: refCnt = 2, refCntWtd = 1 New refCnts for V36: refCnt = 1, refCntWtd = 0.50 New refCnts for V13: refCnt = 9, refCntWtd = 4.50 New refCnts for V36: refCnt = 2, refCntWtd = 1 New refCnts for V02: refCnt = 6, refCntWtd = 3 New refCnts for V01: refCnt = 13, refCntWtd = 6.50 New refCnts for V27: refCnt = 2, refCntWtd = 1 New refCnts for V36: refCnt = 3, refCntWtd = 1.50 New refCnts for V25: refCnt = 4, refCntWtd = 2 New refCnts for V51: refCnt = 3, refCntWtd = 3 New refCnts for V51: refCnt = 4, refCntWtd = 4 *** lvaComputeRefCounts -- implicit counts *** New refCnts for V00: refCnt = 3, refCntWtd = 6 New refCnts for V00: refCnt = 4, refCntWtd = 8 New refCnts for V01: refCnt = 14, refCntWtd = 7.50 New refCnts for V01: refCnt = 15, refCntWtd = 8.50 New refCnts for V02: refCnt = 7, refCntWtd = 4 New refCnts for V02: refCnt = 8, refCntWtd = 5 *************** Finishing PHASE Lowering nodeinfo Trees after Lowering nodeinfo ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0056] 1 1 [???..???) i internal label target LIR BB02 [0000] 1 BB01 1 [000..00D)-> BB04 ( cond ) i label target idxlen LIR BB03 [0001] 1 BB02 0.50 [00D..017) (return) i hascall gcsafe LIR BB04 [0002] 1 BB02 0.50 [017..065)-> BB06 ( cond ) i label target hascall gcsafe LIR BB05 [0038] 1 BB04 0.50 [020..021)-> BB07 (always) i gcsafe LIR BB06 [0039] 1 BB04 0.50 [020..021) i label target gcsafe LIR BB07 [0040] 2 BB05,BB06 0.50 [000..000)-> BB09 ( cond ) i internal label target gcsafe idxlen LIR BB08 [0043] 1 BB07 0.50 [000..000)-> BB10 (always) i internal gcsafe LIR BB09 [0044] 1 BB07 0.50 [000..000) i internal label target gcsafe LIR BB10 [0045] 2 BB08,BB09 0.50 [???..???)-> BB14 ( cond ) i internal label target hascall gcsafe idxlen LIR BB11 [0003] 1 BB10 0.50 [065..070)-> BB13 ( cond ) i hascall gcsafe LIR BB12 [0004] 1 BB11 0.50 [070..07A) (return) i hascall gcsafe LIR BB13 [0005] 1 BB11 0.50 [07A..082) i label target hascall gcsafe LIR BB14 [0006] 2 BB10,BB13 0.50 [082..092)-> BB16 ( cond ) i label target hascall gcsafe LIR BB15 [0007] 1 BB14 0.50 [092..096)-> BB17 ( cond ) i gcsafe LIR BB16 [0008] 2 BB14,BB15 0.50 [096..0A7)-> BB44 (always) i label target hascall gcsafe LIR BB17 [0009] 1 BB15 0.50 [0A7..0B0)-> BB19 ( cond ) i label target gcsafe LIR BB18 [0010] 1 BB17 0.50 [0B0..0B4)-> BB20 (always) i gcsafe LIR BB19 [0011] 1 BB17 0.50 [0B4..0BE) i label target gcsafe LIR BB20 [0012] 2 BB18,BB19 0.50 [0BE..0C4)-> BB23 ( cond ) i label target gcsafe LIR BB21 [0013] 1 BB20 0.50 [0C4..0D9)-> BB23 ( cond ) i hascall gcsafe idxlen LIR BB22 [0014] 1 BB21 0.50 [0D9..0E3) (return) i hascall gcsafe LIR BB23 [0015] 2 BB20,BB21 0.50 [0E3..117)-> BB25 ( cond ) i label target hascall gcsafe LIR BB24 [0016] 1 BB23 0.50 [117..11A)-> BB26 (always) i gcsafe LIR BB25 [0017] 1 BB23 0.50 [11A..11F) i label target gcsafe LIR BB26 [0018] 2 BB24,BB25 0.50 [11F..126)-> BB28 ( cond ) i label target gcsafe LIR BB27 [0019] 1 BB26 0.50 [126..12F) i hascall gcsafe LIR BB28 [0020] 2 BB26,BB27 0.50 [12F..13E)-> BB32 ( cond ) i label target gcsafe LIR BB29 [0021] 1 BB28 0.50 [13E..144)-> BB31 ( cond ) i gcsafe LIR BB30 [0022] 1 BB29 0.50 [144..155)-> BB44 (always) i hascall gcsafe LIR BB31 [0023] 1 BB29 0.50 [155..15C) i label target gcsafe LIR BB32 [0024] 2 BB28,BB31 0.50 [15C..167)-> BB34 ( cond ) i label target hascall gcsafe LIR BB33 [0025] 1 BB32 0.50 [167..16B)-> BB35 (always) i gcsafe LIR BB34 [0026] 1 BB32 0.50 [16B..16F) i label target gcsafe LIR BB35 [0027] 2 BB33,BB34 0.50 [16F..1A4)-> BB40 ( cond ) i label target hascall gcsafe LIR BB36 [0028] 1 BB35 0.50 [1A4..1AF)-> BB38 ( cond ) i gcsafe LIR BB37 [0029] 1 BB36 0.50 [1AF..1C3)-> BB39 (always) i gcsafe LIR BB38 [0030] 1 BB36 0.50 [1C3..1C4) i label target gcsafe LIR BB39 [0031] 2 BB37,BB38 0.50 [1C4..1D0) i label target gcsafe LIR BB40 [0032] 2 BB35,BB39 0.50 [1D0..1E7)-> BB42 ( cond ) i label target hascall gcsafe LIR BB41 [0033] 1 BB40 0.50 [1E7..1EE)-> BB43 (always) i gcsafe LIR BB42 [0034] 1 BB40 0.50 [1EE..1F2) i label target gcsafe LIR BB43 [0035] 2 BB41,BB42 0.50 [1F2..202) i label target hascall gcsafe LIR BB44 [0054] 3 BB16,BB30,BB43 0.50 [???..???) (return) keep internal target gcsafe LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} N001 ( 1, 1) [000531] ------------ t531 = LCL_VAR byref V00 arg0 u:1 Zero Fseq[Mantissa] $80 /--* t531 byref N002 ( 3, 2) [000532] n----------- t532 = * IND ref /--* t532 ref N004 ( 3, 3) [000533] DA---------- * STORE_LCL_VAR ref V52 tmp22 d:2 N005 ( 1, 1) [000535] ------------ t535 = LCL_VAR byref V00 arg0 u:1 (last use) $80 /--* t535 byref N007 ( 2, 2) [000537] -c---------- t537 = * LEA(b+8) byref /--* t537 byref N008 ( 4, 4) [000538] n----------- t538 = * IND int /--* t538 int N010 ( 4, 4) [000539] DA---------- * STORE_LCL_VAR int V53 tmp23 d:2 ------------ BB02 [000..00D) -> BB04 (cond), preds={BB01} succs={BB03,BB04} [000910] ------------ IL_OFFSET void IL offset: 0x0 N001 ( 1, 1) [000002] ------------ t2 = LCL_VAR ref V52 tmp22 u:2 /--* t2 ref [000988] -c---------- t988 = * LEA(b+8) ref /--* t988 ref N002 ( 3, 3) [000003] -c-XG------- t3 = * IND int N003 ( 1, 1) [000004] -c---------- t4 = CNS_INT int 0 $40 /--* t3 int +--* t4 int N004 ( 5, 5) [000005] J--XG--N---- * NE void N005 ( 7, 7) [000006] ---XG------- * JTRUE void ------------ BB03 [00D..017) (return), preds={BB02} succs={} [000911] ------------ IL_OFFSET void IL offset: 0xd N002 ( 1, 1) [000400] ------------ t400 = LCL_VAR ref V01 arg1 u:1 $c0 /--* t400 ref [000995] ------------ t995 = * PUTARG_REG ref REG rcx N001 ( 1, 1) [000996] ------------ t996 = LCL_VAR ref V01 arg1 (last use) /--* t996 ref N002 ( 2, 2) [000997] -c---------- t997 = * LEA(b+0) byref /--* t997 byref N003 ( 5, 4) [000998] ------------ t998 = * IND long /--* t998 long N004 ( 6, 5) [000999] -c---------- t999 = * LEA(b+80) long /--* t999 long N005 ( 9, 7) [001000] ------------ t1000 = * IND long /--* t1000 long N006 ( 10, 8) [001001] -c---------- t1001 = * LEA(b+0) long /--* t1001 long N007 ( 13, 10) [001002] -c---------- t1002 = * IND long REG NA /--* t995 ref this in rcx +--* t1002 long control expr N003 ( 21, 10) [000401] --CXG------- t401 = * CALLV ind long FloatingPointType.get_Zero $459 N004 ( 1, 1) [000399] ------------ t399 = LCL_VAR byref V02 arg2 u:1 (last use) $81 /--* t399 byref +--* t401 long [000912] -ACXG------- * STOREIND long N001 ( 1, 1) [000404] ------------ t404 = CNS_INT int 1 $41 /--* t404 int N002 ( 2, 2) [000520] ------------ * RETURN int $5cb ------------ BB04 [017..065) -> BB06 (cond), preds={BB02} succs={BB05,BB06} N002 ( 1, 1) [000007] ------------ t7 = LCL_VAR ref V01 arg1 u:1 $c0 /--* t7 ref [001003] ------------ t1003 = * PUTARG_REG ref REG rcx N001 ( 1, 1) [001004] ------------ t1004 = LCL_VAR ref V01 arg1 /--* t1004 ref N002 ( 2, 2) [001005] -c---------- t1005 = * LEA(b+0) byref /--* t1005 byref N003 ( 5, 4) [001006] ------------ t1006 = * IND long /--* t1006 long N004 ( 6, 5) [001007] -c---------- t1007 = * LEA(b+72) long /--* t1007 long N005 ( 9, 7) [001008] ------------ t1008 = * IND long /--* t1008 long N006 ( 10, 8) [001009] -c---------- t1009 = * LEA(b+32) long /--* t1009 long N007 ( 13, 10) [001010] -c---------- t1010 = * IND long REG NA /--* t1003 ref this in rcx +--* t1010 long control expr N003 ( 21, 10) [000406] --CXG------- t406 = * CALLV ind int FloatingPointType.get_DenormalMantissaBits $282 N004 ( 1, 1) [000407] -c---------- t407 = CNS_INT int 1 $41 /--* t406 int +--* t407 int N005 ( 23, 12) [000408] ---XG------- t408 = * ADD int $346 /--* t408 int N006 ( 24, 14) [000409] ---XG------- t409 = * CAST int <- ushort <- int $347 N007 ( 1, 1) [000010] -c---------- t10 = CNS_INT int 1 $41 /--* t409 int +--* t10 int N008 ( 26, 16) [000011] ---XG------- t11 = * ADD int $348 /--* t11 int N010 ( 30, 19) [000013] DA-XG------- * STORE_LCL_VAR int V03 loc0 d:2 [000913] ------------ IL_OFFSET void IL offset: 0x20 N001 ( 1, 1) [000017] ------------ t17 = LCL_VAR int V53 tmp23 u:2 /--* t17 int N003 ( 5, 4) [000424] DA--G------- * STORE_LCL_VAR int V40 tmp10 d:2 [000914] ------------ IL_OFFSET void IL offset: 0x20 N001 ( 1, 1) [000412] ------------ t412 = LCL_VAR int V40 tmp10 u:2 (last use) N002 ( 1, 1) [000411] -c---------- t411 = CNS_INT int 0 $40 /--* t412 int +--* t411 int N003 ( 3, 3) [000413] J------N---- * LE void N004 ( 5, 5) [000414] ------------ * JTRUE void ------------ BB05 [020..021) -> BB07 (always), preds={BB04} succs={BB07} [000915] ------------ IL_OFFSET void IL offset: 0x20 N001 ( 3, 2) [000419] ------------ t419 = LCL_VAR int V53 tmp23 u:2 /--* t419 int N003 ( 7, 5) [000421] DA---------- * STORE_LCL_VAR int V39 tmp9 d:4 ------------ BB06 [020..021), preds={BB04} succs={BB07} [000916] ------------ IL_OFFSET void IL offset: 0x20 N001 ( 1, 1) [000415] ------------ t415 = CNS_INT int 0 $40 /--* t415 int N003 ( 5, 4) [000417] DA---------- * STORE_LCL_VAR int V39 tmp9 d:3 ------------ BB07 [000..000) -> BB09 (cond), preds={BB05,BB06} succs={BB08,BB09} N001 ( 0, 0) [000909] ------------ t909 = PHI_ARG int V39 tmp9 u:4 N002 ( 0, 0) [000908] ------------ t908 = PHI_ARG int V39 tmp9 u:3 $40 /--* t909 int +--* t908 int N003 ( 0, 0) [000885] ------------ t885 = * PHI int /--* t885 int N005 ( 0, 0) [000886] DA---------- * STORE_LCL_VAR int V39 tmp9 d:2 N001 ( 3, 2) [000422] ------------ t422 = LCL_VAR int V39 tmp9 u:2 (last use) $241 /--* t422 int N003 ( 3, 3) [000021] DA---------- * STORE_LCL_VAR int V31 tmp1 d:2 N001 ( 1, 1) [000428] ------------ t428 = LCL_VAR ref V52 tmp22 u:2 /--* t428 ref [000990] -c---------- t990 = * LEA(b+8) ref /--* t990 ref N002 ( 3, 3) [000429] ---XG------- t429 = * IND int /--* t429 int N004 ( 3, 3) [000443] DA-XG------- * STORE_LCL_VAR int V42 tmp12 d:2 N001 ( 3, 2) [000023] ------------ t23 = LCL_VAR int V31 tmp1 u:2 $241 N002 ( 1, 1) [000431] ------------ t431 = LCL_VAR int V42 tmp12 u:2 /--* t23 int +--* t431 int N003 ( 5, 4) [000432] N------N-U-- * LE void N004 ( 7, 6) [000433] ------------ * JTRUE void ------------ BB08 [000..000) -> BB10 (always), preds={BB07} succs={BB10} N001 ( 1, 1) [000438] ------------ t438 = LCL_VAR int V42 tmp12 u:2 (last use) /--* t438 int N003 ( 1, 3) [000440] DA---------- * STORE_LCL_VAR int V41 tmp11 d:4 ------------ BB09 [000..000), preds={BB07} succs={BB10} N001 ( 1, 1) [000434] ------------ t434 = LCL_VAR int V31 tmp1 u:2 $241 /--* t434 int N003 ( 1, 3) [000436] DA---------- * STORE_LCL_VAR int V41 tmp11 d:3 ------------ BB10 [???..???) -> BB14 (cond), preds={BB08,BB09} succs={BB11,BB14} N001 ( 0, 0) [000907] ------------ t907 = PHI_ARG int V41 tmp11 u:4 N002 ( 0, 0) [000906] ------------ t906 = PHI_ARG int V41 tmp11 u:3 $241 /--* t907 int +--* t906 int N003 ( 0, 0) [000882] ------------ t882 = * PHI int /--* t882 int N005 ( 0, 0) [000883] DA---------- * STORE_LCL_VAR int V41 tmp11 d:2 N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR int V31 tmp1 u:2 (last use) $241 N002 ( 1, 1) [000032] ------------ t32 = LCL_VAR int V41 tmp11 u:2 $242 /--* t22 int +--* t32 int N003 ( 3, 3) [000033] ------------ t33 = * SUB int $34e /--* t33 int N005 ( 7, 6) [000035] DA---------- * STORE_LCL_VAR int V05 loc2 d:2 [000917] ------------ IL_OFFSET void IL offset: 0x42 N001 ( 1, 1) [000042] ------------ t42 = LCL_VAR int V41 tmp11 u:2 (last use) $242 /--* t42 int N003 ( 5, 4) [000044] DA---------- * STORE_LCL_VAR int V08 loc5 d:2 N001 ( 1, 1) [000447] ------------ t447 = LCL_VAR ref V52 tmp22 u:2 /--* t447 ref [000992] -c---------- t992 = * LEA(b+8) ref /--* t992 ref N002 ( 3, 3) [000448] ---XG------- t448 = * IND int /--* t448 int N004 ( 7, 6) [000050] DA-XG------- * STORE_LCL_VAR int V09 loc6 d:2 [000918] ------------ IL_OFFSET void IL offset: 0x4f N001 ( 3, 2) [000051] ------------ t51 = LCL_VAR int V09 loc6 u:2 N002 ( 1, 1) [000052] ------------ t52 = LCL_VAR int V08 loc5 u:2 $242 /--* t51 int +--* t52 int N003 ( 5, 4) [000053] ------------ t53 = * SUB int /--* t53 int N005 ( 5, 4) [000055] DA---------- * STORE_LCL_VAR int V10 loc7 d:2 N001 ( 3, 2) [000063] -------N---- t63 = LCL_VAR_ADDR byref V11 loc8 * ref V11._bits (offs=0x00) -> V54 tmp24 * int V11._sign (offs=0x08) -> V55 tmp25 /--* t63 byref N004 ( 7, 6) [000563] DA--------L- * STORE_LCL_VAR long V75 tmp45 d:2 N005 ( 3, 2) [000547] -------N---- t547 = LCL_VAR_ADDR byref V73 tmp43 /--* t547 byref N008 ( 3, 3) [000549] DA---------- * STORE_LCL_VAR byref V74 tmp44 d:2 N009 ( 1, 1) [000550] ------------ t550 = LCL_VAR byref V74 tmp44 u:2 Zero Fseq[Mantissa] $401 N011 ( 1, 1) [000552] -------N---- t552 = LCL_VAR ref V52 tmp22 u:2 /--* t550 byref +--* t552 ref [000919] -A---------- * STOREIND ref N014 ( 1, 1) [000555] ------------ t555 = LCL_VAR byref V74 tmp44 u:2 (last use) $401 /--* t555 byref N016 ( 2, 2) [000557] -c---------- t557 = * LEA(b+8) byref N018 ( 1, 1) [000559] -------N---- t559 = LCL_VAR int V53 tmp23 u:2 /--* t557 byref +--* t559 int [000920] -A--------L- * STOREIND int N023 ( 3, 2) [000564] ------------ t564 = LCL_VAR long V75 tmp45 u:2 (last use) $400 /--* t564 long [001011] ------------ t1011 = * PUTARG_REG long REG rcx N024 ( 3, 2) [000565] -------N---- t565 = LCL_VAR_ADDR byref V73 tmp43 /--* t565 byref [001012] ------------ t1012 = * PUTARG_REG byref REG rdx N026 ( 1, 1) [000058] ------------ t58 = LCL_VAR int V08 loc5 u:2 $242 /--* t58 int [001013] ------------ t1013 = * PUTARG_REG int REG r9 N027 ( 1, 1) [000057] ------------ t57 = CNS_INT int 0 $40 /--* t57 int [001014] ------------ t1014 = * PUTARG_REG int REG r8 /--* t1011 long arg0 in rcx +--* t1012 byref arg1 in rdx +--* t1013 int arg3 in r9 +--* t1014 int arg2 in r8 N028 ( 49, 35) [000059] S-CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger $VN.Void [000921] ------------ IL_OFFSET void IL offset: 0x61 N001 ( 3, 2) [000065] ------------ t65 = LCL_VAR int V05 loc2 u:2 $34e N002 ( 1, 1) [000066] -c---------- t66 = CNS_INT int 0 $40 /--* t65 int +--* t66 int N003 ( 5, 4) [000067] N------N---- * EQ void $351 N004 ( 7, 6) [000068] ------------ * JTRUE void ------------ BB11 [065..070) -> BB13 (cond), preds={BB10} succs={BB12,BB13} N002 ( 1, 1) [000382] ------------ t382 = LCL_VAR ref V01 arg1 u:1 $c0 /--* t382 ref [001015] ------------ t1015 = * PUTARG_REG ref REG rcx /--* t1015 ref this in rcx N003 ( 15, 8) [000383] --CXG------- t383 = * CALL int FloatingPointType.get_OverflowDecimalExponent $291 /--* t383 int N004 ( 16, 10) [000385] ---XG------- t385 = * CAST long <- int $480 N005 ( 3, 2) [000380] ------------ t380 = LCL_VAR int V05 loc2 u:2 $34e /--* t380 int N006 ( 4, 4) [000381] ---------U-- t381 = * CAST long <- ulong <- uint $481 /--* t385 long +--* t381 long N007 ( 21, 15) [000386] J--XG--N---- * GE void $352 N008 ( 23, 17) [000387] ---XG------- * JTRUE void ------------ BB12 [070..07A) (return), preds={BB11} succs={} [000922] ------------ IL_OFFSET void IL offset: 0x70 N002 ( 1, 1) [000393] ------------ t393 = LCL_VAR ref V01 arg1 u:1 $c0 /--* t393 ref [001016] ------------ t1016 = * PUTARG_REG ref REG rcx N001 ( 1, 1) [001017] ------------ t1017 = LCL_VAR ref V01 arg1 (last use) /--* t1017 ref N002 ( 2, 2) [001018] -c---------- t1018 = * LEA(b+0) byref /--* t1018 byref N003 ( 5, 4) [001019] ------------ t1019 = * IND long /--* t1019 long N004 ( 6, 5) [001020] -c---------- t1020 = * LEA(b+80) long /--* t1020 long N005 ( 9, 7) [001021] ------------ t1021 = * IND long /--* t1021 long N006 ( 10, 8) [001022] -c---------- t1022 = * LEA(b+8) long /--* t1022 long N007 ( 13, 10) [001023] -c---------- t1023 = * IND long REG NA /--* t1016 ref this in rcx +--* t1023 long control expr N003 ( 21, 10) [000394] --CXG------- t394 = * CALLV ind long FloatingPointType.get_Infinity $458 N004 ( 1, 1) [000392] ------------ t392 = LCL_VAR byref V02 arg2 u:1 (last use) $81 /--* t392 byref +--* t394 long [000923] -ACXG------- * STOREIND long N001 ( 1, 1) [000397] ------------ t397 = CNS_INT int 3 $48 /--* t397 int N002 ( 2, 2) [000521] ------------ * RETURN int $5ca ------------ BB13 [07A..082), preds={BB11} succs={BB14} [000924] ------------ IL_OFFSET void IL offset: 0x7a N003 ( 3, 2) [000388] -------N---- t388 = LCL_VAR_ADDR byref V11 loc8 * ref V11._bits (offs=0x00) -> V54 tmp24 * int V11._sign (offs=0x08) -> V55 tmp25 /--* t388 byref [001024] ------------ t1024 = * PUTARG_REG byref REG rcx N005 ( 3, 2) [000390] ------------ t390 = LCL_VAR int V05 loc2 u:2 (last use) $34e /--* t390 int [001025] ------------ t1025 = * PUTARG_REG int REG rdx /--* t1024 byref arg0 in rcx +--* t1025 int arg1 in rdx N006 ( 20, 12) [000391] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen $VN.Void ------------ BB14 [082..092) -> BB16 (cond), preds={BB10,BB13} succs={BB15,BB16} N001 ( 3, 2) [000577] -------N---- t577 = LCL_VAR_ADDR byref V76 tmp46 /--* t577 byref N004 ( 3, 3) [000579] DA---------- * STORE_LCL_VAR byref V77 tmp47 d:2 N005 ( 1, 1) [000580] ------------ t580 = LCL_VAR byref V77 tmp47 u:2 Zero Fseq[_bits] $405 N007 ( 3, 2) [000582] -------N---- t582 = LCL_VAR ref (AX) V54 tmp24 $181 /--* t580 byref +--* t582 ref [000925] -A--G------- * STOREIND ref N010 ( 1, 1) [000585] ------------ t585 = LCL_VAR byref V77 tmp47 u:2 (last use) $405 /--* t585 byref N012 ( 2, 2) [000587] -c---------- t587 = * LEA(b+8) byref N014 ( 3, 2) [000589] -------N---- t589 = LCL_VAR int (AX) V55 tmp25 $243 /--* t587 byref +--* t589 int [000926] -A--G-----L- * STOREIND int N018 ( 3, 2) [000592] -------N---- t592 = LCL_VAR_ADDR byref V76 tmp46 /--* t592 byref [001026] ------------ t1026 = * PUTARG_REG byref REG rcx N020 ( 3, 3) [000071] ------------ t71 = LCL_VAR_ADDR long V12 loc9 $443 /--* t71 long [001027] ------------ t1027 = * PUTARG_REG long REG rdx /--* t1026 byref arg0 in rcx +--* t1027 long arg1 in rdx N021 ( 41, 28) [000072] --CXG------- t72 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $293 /--* t72 int N023 ( 41, 28) [000077] DA-XG------- * STORE_LCL_VAR int V13 loc10 d:2 [000927] ------------ IL_OFFSET void IL offset: 0x8d N001 ( 1, 1) [000078] ------------ t78 = LCL_VAR int V13 loc10 u:2 $293 N002 ( 3, 2) [000079] ------------ t79 = LCL_VAR int V03 loc0 u:2 $348 /--* t78 int +--* t79 int N003 ( 5, 4) [000080] N------N-U-- * GE void $353 N004 ( 7, 6) [000081] ------------ * JTRUE void ------------ BB15 [092..096) -> BB17 (cond), preds={BB14} succs={BB16,BB17} [000928] ------------ IL_OFFSET void IL offset: 0x92 N001 ( 1, 1) [000091] ------------ t91 = LCL_VAR int V10 loc7 u:2 N002 ( 1, 1) [000092] -c---------- t92 = CNS_INT int 0 $40 /--* t91 int +--* t92 int N003 ( 3, 3) [000093] J------N---- * NE void N004 ( 5, 5) [000094] ------------ * JTRUE void ------------ BB16 [096..0A7) -> BB44 (always), preds={BB14,BB15} succs={BB44} [000929] ------------ IL_OFFSET void IL offset: 0x96 N005 ( 1, 1) [000088] ------------ t88 = LCL_VAR byref V02 arg2 u:1 (last use) $81 /--* t88 byref [001028] ------------ * PUTARG_STK [+0x20] void N006 ( 1, 1) [000084] ------------ t84 = LCL_VAR int V10 loc7 u:2 (last use) N007 ( 1, 1) [000085] -c---------- t85 = CNS_INT int 0 $40 /--* t84 int +--* t85 int N008 ( 6, 3) [000086] N----------- t86 = * NE int /--* t86 int [001029] ------------ t1029 = * PUTARG_REG int REG r8 N009 ( 3, 2) [000082] ------------ t82 = LCL_VAR ref (AX) V12 loc9 $18d /--* t82 ref [001030] ------------ t1030 = * PUTARG_REG ref REG rcx N010 ( 1, 1) [000083] ------------ t83 = LCL_VAR int V13 loc10 u:2 (last use) $293 /--* t83 int [001031] ------------ t1031 = * PUTARG_REG int REG rdx N011 ( 1, 1) [000087] ------------ t87 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t87 ref [001032] ------------ t1032 = * PUTARG_REG ref REG r9 /--* t1029 int arg2 in r8 +--* t1030 ref arg0 in rcx +--* t1031 int arg1 in rdx +--* t1032 ref arg3 in r9 N012 ( 29, 17) [000089] --CXG------- t89 = * CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits $5c7 /--* t89 int N014 ( 29, 17) [000600] DA-XG------- * STORE_LCL_VAR int V51 tmp21 d:3 ------------ BB17 [0A7..0B0) -> BB19 (cond), preds={BB15} succs={BB18,BB19} [000930] ------------ IL_OFFSET void IL offset: 0xa7 N001 ( 1, 1) [000097] ------------ t97 = LCL_VAR int V53 tmp23 u:2 N002 ( 1, 1) [000098] -c---------- t98 = CNS_INT int 0 $40 /--* t97 int +--* t98 int N003 ( 3, 3) [000099] J---G--N---- * LT void N004 ( 5, 5) [000100] ----G------- * JTRUE void ------------ BB18 [0B0..0B4) -> BB20 (always), preds={BB17} succs={BB20} [000931] ------------ IL_OFFSET void IL offset: 0xb0 N001 ( 1, 1) [000376] ------------ t376 = LCL_VAR int V10 loc7 u:2 (last use) /--* t376 int N003 ( 5, 4) [000378] DA---------- * STORE_LCL_VAR int V32 tmp2 d:4 ------------ BB19 [0B4..0BE), preds={BB17} succs={BB20} [000932] ------------ IL_OFFSET void IL offset: 0xb4 N001 ( 1, 1) [000101] ------------ t101 = LCL_VAR int V10 loc7 u:2 (last use) N002 ( 1, 1) [000104] ------------ t104 = LCL_VAR int V53 tmp23 u:2 /--* t101 int +--* t104 int N003 ( 3, 3) [000106] ----G------- t106 = * SUB int /--* t106 int N005 ( 7, 6) [000108] DA--G------- * STORE_LCL_VAR int V32 tmp2 d:3 ------------ BB20 [0BE..0C4) -> BB23 (cond), preds={BB18,BB19} succs={BB21,BB23} N001 ( 0, 0) [000905] ------------ t905 = PHI_ARG int V32 tmp2 u:4 N002 ( 0, 0) [000904] ------------ t904 = PHI_ARG int V32 tmp2 u:3 /--* t905 int +--* t904 int N003 ( 0, 0) [000879] ------------ t879 = * PHI int /--* t879 int N005 ( 0, 0) [000880] DA---------- * STORE_LCL_VAR int V32 tmp2 d:2 N001 ( 3, 2) [000110] ------------ t110 = LCL_VAR int V32 tmp2 u:2 (last use) $244 /--* t110 int N003 ( 7, 5) [000112] DA---------- * STORE_LCL_VAR int V14 loc11 d:2 [000933] ------------ IL_OFFSET void IL offset: 0xc0 N001 ( 1, 1) [000113] ------------ t113 = LCL_VAR int V13 loc10 u:2 $293 N002 ( 1, 1) [000114] -c---------- t114 = CNS_INT int 0 $40 /--* t113 int +--* t114 int N003 ( 3, 3) [000115] J------N---- * NE void $35a N004 ( 5, 5) [000116] ------------ * JTRUE void ------------ BB21 [0C4..0D9) -> BB23 (cond), preds={BB20} succs={BB22,BB23} N001 ( 1, 1) [000455] ------------ t455 = LCL_VAR ref V52 tmp22 u:2 /--* t455 ref [000994] -c---------- t994 = * LEA(b+8) ref /--* t994 ref N002 ( 3, 3) [000456] ---XG------- t456 = * IND int /--* t456 int N003 ( 4, 5) [000358] ---XG------- t358 = * CAST long <- int N004 ( 3, 2) [000352] ------------ t352 = LCL_VAR int V14 loc11 u:2 $244 /--* t352 int N005 ( 4, 4) [000353] ---------U-- t353 = * CAST long <- ulong <- uint $486 /--* t353 long +--* t358 long N006 ( 9, 10) [000359] ---XG------- t359 = * SUB long /--* t359 long N008 ( 13, 13) [000363] DA-XG------- * STORE_LCL_VAR long V38 tmp8 d:2 N002 ( 1, 1) [000360] ------------ t360 = LCL_VAR ref V01 arg1 u:1 $c0 /--* t360 ref [001033] ------------ t1033 = * PUTARG_REG ref REG rcx /--* t1033 ref this in rcx N003 ( 15, 8) [000361] --CXG------- t361 = * CALL int FloatingPointType.get_OverflowDecimalExponent $298 /--* t361 int N004 ( 16, 10) [000366] ---XG------- t366 = * CAST long <- int $48b N005 ( 3, 2) [000364] ------------ t364 = LCL_VAR long V38 tmp8 u:2 (last use) /--* t366 long +--* t364 long N006 ( 20, 13) [000367] J--XG--N---- * GE void N007 ( 22, 15) [000368] ---XG------- * JTRUE void ------------ BB22 [0D9..0E3) (return), preds={BB21} succs={} [000934] ------------ IL_OFFSET void IL offset: 0xd9 N002 ( 1, 1) [000370] ------------ t370 = LCL_VAR ref V01 arg1 u:1 $c0 /--* t370 ref [001034] ------------ t1034 = * PUTARG_REG ref REG rcx N001 ( 1, 1) [001035] ------------ t1035 = LCL_VAR ref V01 arg1 (last use) /--* t1035 ref N002 ( 2, 2) [001036] -c---------- t1036 = * LEA(b+0) byref /--* t1036 byref N003 ( 5, 4) [001037] ------------ t1037 = * IND long /--* t1037 long N004 ( 6, 5) [001038] -c---------- t1038 = * LEA(b+80) long /--* t1038 long N005 ( 9, 7) [001039] ------------ t1039 = * IND long /--* t1039 long N006 ( 10, 8) [001040] -c---------- t1040 = * LEA(b+0) long /--* t1040 long N007 ( 13, 10) [001041] -c---------- t1041 = * IND long REG NA /--* t1034 ref this in rcx +--* t1041 long control expr N003 ( 21, 10) [000371] --CXG------- t371 = * CALLV ind long FloatingPointType.get_Zero $457 N004 ( 1, 1) [000369] ------------ t369 = LCL_VAR byref V02 arg2 u:1 (last use) $81 /--* t369 byref +--* t371 long [000935] -ACXG------- * STOREIND long N001 ( 1, 1) [000374] ------------ t374 = CNS_INT int 2 $42 /--* t374 int N002 ( 2, 2) [000524] ------------ * RETURN int $5c4 ------------ BB23 [0E3..117) -> BB25 (cond), preds={BB20,BB21} succs={BB24,BB25} N001 ( 3, 2) [000124] -------N---- t124 = LCL_VAR_ADDR byref V15 loc12 * ref V15._bits (offs=0x00) -> V56 tmp26 * int V15._sign (offs=0x08) -> V57 tmp27 /--* t124 byref N004 ( 7, 6) [000623] DA--------L- * STORE_LCL_VAR long V79 tmp49 d:2 N005 ( 3, 2) [000607] -------N---- t607 = LCL_VAR_ADDR byref V73 tmp43 /--* t607 byref N008 ( 3, 3) [000609] DA---------- * STORE_LCL_VAR byref V78 tmp48 d:2 N009 ( 1, 1) [000610] ------------ t610 = LCL_VAR byref V78 tmp48 u:2 Zero Fseq[Mantissa] $409 N011 ( 1, 1) [000612] -------N---- t612 = LCL_VAR ref V52 tmp22 u:2 (last use) /--* t610 byref +--* t612 ref [000936] -A---------- * STOREIND ref N014 ( 1, 1) [000615] ------------ t615 = LCL_VAR byref V78 tmp48 u:2 (last use) $409 /--* t615 byref N016 ( 2, 2) [000617] -c---------- t617 = * LEA(b+8) byref N018 ( 1, 1) [000619] -------N---- t619 = LCL_VAR int V53 tmp23 u:2 (last use) /--* t617 byref +--* t619 int [000937] -A--------L- * STOREIND int N023 ( 3, 2) [000624] ------------ t624 = LCL_VAR long V79 tmp49 u:2 (last use) $408 /--* t624 long [001042] ------------ t1042 = * PUTARG_REG long REG rcx N024 ( 3, 2) [000625] -------N---- t625 = LCL_VAR_ADDR byref V73 tmp43 /--* t625 byref [001043] ------------ t1043 = * PUTARG_REG byref REG rdx N026 ( 3, 2) [000118] ------------ t118 = LCL_VAR int V08 loc5 u:2 (last use) $242 /--* t118 int [001044] ------------ t1044 = * PUTARG_REG int REG r8 N027 ( 3, 2) [000119] ------------ t119 = LCL_VAR int V09 loc6 u:2 (last use) /--* t119 int [001045] ------------ t1045 = * PUTARG_REG int REG r9 /--* t1042 long arg0 in rcx +--* t1043 byref arg1 in rdx +--* t1044 int arg2 in r8 +--* t1045 int arg3 in r9 N028 ( 53, 37) [000120] S-CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger $VN.Void [000938] ------------ IL_OFFSET void IL offset: 0xef N003 ( 2, 10) [000131] ------------ t131 = CNS_INT long 0x7ff815262aa0 $102 /--* t131 long [001046] ------------ t1046 = * PUTARG_REG long REG rcx N004 ( 1, 4) [000132] ------------ t132 = CNS_INT int 173 $58 /--* t132 int [001047] ------------ t1047 = * PUTARG_REG int REG rdx /--* t1046 long arg0 in rcx +--* t1047 int arg1 in rdx N005 ( 17, 21) [000133] H-CXG------- t133 = * CALL help long HELPER.CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE $48d N001 ( 2, 10) [000634] I----------- t634 = CNS_INT(h) long 0xd1ffab1e static Fseq[BigOne] $4c2 /--* t634 long N002 ( 4, 12) [000633] n---G------- t633 = * IND ref N003 ( 1, 1) [000635] -c---------- t635 = CNS_INT long 8 Fseq[#FirstElem] $101 /--* t633 ref +--* t635 long N004 ( 6, 14) [000632] ----G------- t632 = * ADD byref /--* t632 byref N006 ( 6, 14) [000637] DA--G------- * STORE_LCL_VAR byref V80 tmp50 d:2 N007 ( 1, 1) [000639] ------------ t639 = LCL_VAR byref V80 tmp50 u:2 Zero Fseq[_bits] /--* t639 byref N008 ( 3, 2) [000640] ---X-------- t640 = * IND ref /--* t640 ref N010 ( 7, 5) [000641] DA-XG------- * STORE_LCL_VAR ref (AX) V58 tmp28 N012 ( 1, 1) [000644] ------------ t644 = LCL_VAR byref V80 tmp50 u:2 (last use) /--* t644 byref N014 ( 2, 2) [000646] -c---------- t646 = * LEA(b+8) byref /--* t646 byref N015 ( 4, 4) [000647] ---X-------- t647 = * IND int /--* t647 int N017 ( 8, 7) [000648] DA-XG------- * STORE_LCL_VAR int (AX) V59 tmp29 [000939] ------------ IL_OFFSET void IL offset: 0xf6 N003 ( 3, 2) [000138] -------N---- t138 = LCL_VAR_ADDR byref V16 loc13 * ref V16._bits (offs=0x00) -> V58 tmp28 * int V16._sign (offs=0x08) -> V59 tmp29 /--* t138 byref [001048] ------------ t1048 = * PUTARG_REG byref REG rcx N005 ( 3, 2) [000140] ------------ t140 = LCL_VAR int V14 loc11 u:2 (last use) $244 /--* t140 int [001049] ------------ t1049 = * PUTARG_REG int REG rdx /--* t1048 byref arg0 in rcx +--* t1049 int arg1 in rdx N006 ( 20, 12) [000141] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen $VN.Void [000940] ------------ IL_OFFSET void IL offset: 0xff N001 ( 3, 2) [000653] -------N---- t653 = LCL_VAR ref (AX) V56 tmp26 $184 /--* t653 ref N003 ( 7, 5) [000654] DA--G------- * STORE_LCL_VAR ref V64 tmp34 d:2 N004 ( 3, 2) [000656] -------N---- t656 = LCL_VAR int (AX) V57 tmp27 $246 /--* t656 int N006 ( 7, 5) [000657] DA--G------- * STORE_LCL_VAR int V65 tmp35 d:2 [000941] ------------ IL_OFFSET void IL offset: 0xff N001 ( 3, 2) [000663] -------N---- t663 = LCL_VAR_ADDR byref V76 tmp46 /--* t663 byref N004 ( 3, 3) [000665] DA---------- * STORE_LCL_VAR byref V81 tmp51 d:2 N005 ( 1, 1) [000666] ------------ t666 = LCL_VAR byref V81 tmp51 u:2 Zero Fseq[_bits] $40e N007 ( 3, 2) [000668] -------N---- t668 = LCL_VAR ref V64 tmp34 u:2 (last use) $184 /--* t666 byref +--* t668 ref [000942] -A---------- * STOREIND ref N010 ( 1, 1) [000671] ------------ t671 = LCL_VAR byref V81 tmp51 u:2 (last use) $40e /--* t671 byref N012 ( 2, 2) [000673] -c---------- t673 = * LEA(b+8) byref N014 ( 3, 2) [000675] -------N---- t675 = LCL_VAR int V65 tmp35 u:2 (last use) $246 /--* t673 byref +--* t675 int [000943] -A--------L- * STOREIND int N018 ( 3, 2) [000678] -------N---- t678 = LCL_VAR_ADDR byref V76 tmp46 /--* t678 byref [001050] ------------ t1050 = * PUTARG_REG byref REG rcx N020 ( 3, 3) [000462] ------------ t462 = LCL_VAR_ADDR long V45 tmp15 $449 /--* t462 long [001051] ------------ t1051 = * PUTARG_REG long REG rdx /--* t1050 byref arg0 in rcx +--* t1051 long arg1 in rdx N021 ( 41, 28) [000463] --CXG------- t463 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $29f /--* t463 int N023 ( 45, 31) [000468] DA-XG------- * STORE_LCL_VAR int V43 tmp13 d:2 [000944] ------------ IL_OFFSET void IL offset: 0xff N001 ( 1, 1) [000473] ------------ t473 = CNS_INT ref null $VN.Null /--* t473 ref N003 ( 5, 4) [000475] DA--G------- * STORE_LCL_VAR ref (AX) V45 tmp15 N001 ( 3, 2) [000469] ------------ t469 = LCL_VAR int V43 tmp13 u:2 (last use) $29f /--* t469 int N003 ( 7, 5) [000148] DA---------- * STORE_LCL_VAR int V17 loc14 d:2 [000945] ------------ IL_OFFSET void IL offset: 0x108 N001 ( 3, 2) [000682] -------N---- t682 = LCL_VAR ref (AX) V58 tmp28 $185 /--* t682 ref N003 ( 7, 5) [000683] DA--G------- * STORE_LCL_VAR ref V66 tmp36 d:2 N004 ( 3, 2) [000685] -------N---- t685 = LCL_VAR int (AX) V59 tmp29 $247 /--* t685 int N006 ( 7, 5) [000686] DA--G------- * STORE_LCL_VAR int V67 tmp37 d:2 [000946] ------------ IL_OFFSET void IL offset: 0x108 N001 ( 3, 2) [000692] -------N---- t692 = LCL_VAR_ADDR byref V76 tmp46 /--* t692 byref N004 ( 3, 3) [000694] DA---------- * STORE_LCL_VAR byref V82 tmp52 d:2 N005 ( 1, 1) [000695] ------------ t695 = LCL_VAR byref V82 tmp52 u:2 Zero Fseq[_bits] $411 N007 ( 3, 2) [000697] -------N---- t697 = LCL_VAR ref V66 tmp36 u:2 (last use) $185 /--* t695 byref +--* t697 ref [000947] -A---------- * STOREIND ref N010 ( 1, 1) [000700] ------------ t700 = LCL_VAR byref V82 tmp52 u:2 (last use) $411 /--* t700 byref N012 ( 2, 2) [000702] -c---------- t702 = * LEA(b+8) byref N014 ( 3, 2) [000704] -------N---- t704 = LCL_VAR int V67 tmp37 u:2 (last use) $247 /--* t702 byref +--* t704 int [000948] -A--------L- * STOREIND int N018 ( 3, 2) [000707] -------N---- t707 = LCL_VAR_ADDR byref V76 tmp46 /--* t707 byref [001052] ------------ t1052 = * PUTARG_REG byref REG rcx N020 ( 3, 3) [000480] ------------ t480 = LCL_VAR_ADDR long V48 tmp18 $44b /--* t480 long [001053] ------------ t1053 = * PUTARG_REG long REG rdx /--* t1052 byref arg0 in rcx +--* t1053 long arg1 in rdx N021 ( 41, 28) [000481] --CXG------- t481 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $2a3 /--* t481 int N023 ( 45, 31) [000486] DA-XG------- * STORE_LCL_VAR int V46 tmp16 d:2 [000949] ------------ IL_OFFSET void IL offset: 0x108 N001 ( 1, 1) [000491] ------------ t491 = CNS_INT ref null $VN.Null /--* t491 ref N003 ( 5, 4) [000493] DA--G------- * STORE_LCL_VAR ref (AX) V48 tmp18 N001 ( 3, 2) [000487] ------------ t487 = LCL_VAR int V46 tmp16 u:2 (last use) $2a3 /--* t487 int N003 ( 7, 5) [000155] DA---------- * STORE_LCL_VAR int V18 loc15 d:2 [000950] ------------ IL_OFFSET void IL offset: 0x111 N001 ( 3, 2) [000156] ------------ t156 = LCL_VAR int V18 loc15 u:2 $2a3 N002 ( 3, 2) [000157] ------------ t157 = LCL_VAR int V17 loc14 u:2 $29f /--* t156 int +--* t157 int N003 ( 7, 5) [000158] N------N-U-- * GT void $35f N004 ( 9, 7) [000159] ------------ * JTRUE void ------------ BB24 [117..11A) -> BB26 (always), preds={BB23} succs={BB26} [000951] ------------ IL_OFFSET void IL offset: 0x117 N001 ( 1, 1) [000348] ------------ t348 = CNS_INT int 0 $40 /--* t348 int N003 ( 5, 4) [000350] DA---------- * STORE_LCL_VAR int V33 tmp3 d:4 ------------ BB25 [11A..11F), preds={BB23} succs={BB26} [000952] ------------ IL_OFFSET void IL offset: 0x11a N001 ( 3, 2) [000160] ------------ t160 = LCL_VAR int V18 loc15 u:2 (last use) $2a3 N002 ( 3, 2) [000161] ------------ t161 = LCL_VAR int V17 loc14 u:2 (last use) $29f /--* t160 int +--* t161 int N003 ( 7, 5) [000162] ------------ t162 = * SUB int $360 /--* t162 int N005 ( 11, 8) [000164] DA---------- * STORE_LCL_VAR int V33 tmp3 d:3 ------------ BB26 [11F..126) -> BB28 (cond), preds={BB24,BB25} succs={BB27,BB28} N001 ( 0, 0) [000903] ------------ t903 = PHI_ARG int V33 tmp3 u:4 $40 N002 ( 0, 0) [000902] ------------ t902 = PHI_ARG int V33 tmp3 u:3 $360 /--* t903 int +--* t902 int N003 ( 0, 0) [000876] ------------ t876 = * PHI int /--* t876 int N005 ( 0, 0) [000877] DA---------- * STORE_LCL_VAR int V33 tmp3 d:2 N001 ( 3, 2) [000166] ------------ t166 = LCL_VAR int V33 tmp3 u:2 (last use) $248 /--* t166 int N003 ( 3, 3) [000168] DA---------- * STORE_LCL_VAR int V19 loc16 d:2 [000953] ------------ IL_OFFSET void IL offset: 0x121 N001 ( 3, 2) [000169] ------------ t169 = LCL_VAR int V19 loc16 u:2 $248 N002 ( 1, 1) [000170] -c---------- t170 = CNS_INT int 0 $40 /--* t169 int +--* t170 int N003 ( 5, 4) [000171] N------N---- * EQ void $361 N004 ( 7, 6) [000172] ------------ * JTRUE void ------------ BB27 [126..12F), preds={BB26} succs={BB28} [000954] ------------ IL_OFFSET void IL offset: 0x126 N003 ( 3, 2) [000344] -------N---- t344 = LCL_VAR_ADDR byref V15 loc12 * ref V15._bits (offs=0x00) -> V56 tmp26 * int V15._sign (offs=0x08) -> V57 tmp27 /--* t344 byref [001054] ------------ t1054 = * PUTARG_REG byref REG rcx N005 ( 1, 1) [000346] ------------ t346 = LCL_VAR int V19 loc16 u:2 $248 /--* t346 int [001055] ------------ t1055 = * PUTARG_REG int REG rdx /--* t1054 byref arg0 in rcx +--* t1055 int arg1 in rdx N006 ( 18, 11) [000347] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft $VN.Void ------------ BB28 [12F..13E) -> BB32 (cond), preds={BB26,BB27} succs={BB29,BB32} [000955] ------------ IL_OFFSET void IL offset: 0x12f N001 ( 3, 2) [000173] ------------ t173 = LCL_VAR int V03 loc0 u:2 (last use) $348 N002 ( 1, 1) [000174] ------------ t174 = LCL_VAR int V13 loc10 u:2 $293 /--* t173 int +--* t174 int N003 ( 5, 4) [000175] ------------ t175 = * SUB int $362 /--* t175 int N005 ( 9, 7) [000177] DA---------- * STORE_LCL_VAR int V20 loc17 d:2 [000956] ------------ IL_OFFSET void IL offset: 0x135 N001 ( 3, 2) [000178] ------------ t178 = LCL_VAR int V20 loc17 u:2 $362 /--* t178 int N003 ( 7, 5) [000180] DA---------- * STORE_LCL_VAR int V21 loc18 d:2 [000957] ------------ IL_OFFSET void IL offset: 0x139 N001 ( 1, 1) [000181] ------------ t181 = LCL_VAR int V13 loc10 u:2 $293 N002 ( 1, 1) [000182] -c---------- t182 = CNS_INT int 0 $40 /--* t181 int +--* t182 int N003 ( 3, 3) [000183] N------N---- * EQ void $363 N004 ( 5, 5) [000184] ------------ * JTRUE void ------------ BB29 [13E..144) -> BB31 (cond), preds={BB28} succs={BB30,BB31} [000958] ------------ IL_OFFSET void IL offset: 0x13e N001 ( 1, 1) [000326] ------------ t326 = LCL_VAR int V19 loc16 u:2 $248 N002 ( 3, 2) [000327] ------------ t327 = LCL_VAR int V20 loc17 u:2 $362 /--* t326 int +--* t327 int N003 ( 5, 4) [000328] N------N-U-- * LE void $364 N004 ( 7, 6) [000329] ------------ * JTRUE void ------------ BB30 [144..155) -> BB44 (always), preds={BB29} succs={BB44} [000959] ------------ IL_OFFSET void IL offset: 0x144 N005 ( 1, 1) [000341] ------------ t341 = LCL_VAR byref V02 arg2 u:1 (last use) $81 /--* t341 byref [001056] ------------ * PUTARG_STK [+0x20] void N006 ( 1, 1) [000339] ------------ t339 = CNS_INT int 1 $41 /--* t339 int [001057] ------------ t1057 = * PUTARG_REG int REG r8 N007 ( 3, 2) [000335] ------------ t335 = LCL_VAR ref (AX) V12 loc9 $18c /--* t335 ref [001058] ------------ t1058 = * PUTARG_REG ref REG rcx N008 ( 1, 1) [000336] ------------ t336 = LCL_VAR int V13 loc10 u:2 (last use) $293 /--* t336 int [001059] ------------ t1059 = * PUTARG_REG int REG rdx N009 ( 1, 1) [000340] ------------ t340 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t340 ref [001060] ------------ t1060 = * PUTARG_REG ref REG r9 /--* t1057 int arg2 in r8 +--* t1058 ref arg0 in rcx +--* t1059 int arg1 in rdx +--* t1060 ref arg3 in r9 N010 ( 24, 15) [000342] --CXG------- t342 = * CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits $5c2 /--* t342 int N012 ( 24, 15) [000717] DA-XG------- * STORE_LCL_VAR int V51 tmp21 d:5 ------------ BB31 [155..15C), preds={BB29} succs={BB32} [000960] ------------ IL_OFFSET void IL offset: 0x155 N001 ( 3, 2) [000330] ------------ t330 = LCL_VAR int V20 loc17 u:2 $362 N002 ( 1, 1) [000331] ------------ t331 = LCL_VAR int V19 loc16 u:2 $248 /--* t330 int +--* t331 int N003 ( 5, 4) [000332] ------------ t332 = * SUB int $365 /--* t332 int N005 ( 9, 7) [000334] DA---------- * STORE_LCL_VAR int V21 loc18 d:4 ------------ BB32 [15C..167) -> BB34 (cond), preds={BB28,BB31} succs={BB33,BB34} N001 ( 0, 0) [000900] ------------ t900 = PHI_ARG int V21 loc18 u:4 $365 N002 ( 0, 0) [000888] ------------ t888 = PHI_ARG int V21 loc18 u:2 $362 /--* t900 int +--* t888 int N003 ( 0, 0) [000873] ------------ t873 = * PHI int /--* t873 int N005 ( 0, 0) [000874] DA---------- * STORE_LCL_VAR int V21 loc18 d:3 [000961] ------------ IL_OFFSET void IL offset: 0x15c N001 ( 3, 2) [000719] -------N---- t719 = LCL_VAR ref (AX) V56 tmp26 $186 /--* t719 ref N003 ( 7, 5) [000720] DA--G------- * STORE_LCL_VAR ref (AX) V68 tmp38 N004 ( 3, 2) [000722] -------N---- t722 = LCL_VAR int (AX) V57 tmp27 $24a /--* t722 int N006 ( 7, 5) [000723] DA--G------- * STORE_LCL_VAR int (AX) V69 tmp39 [000962] ------------ IL_OFFSET void IL offset: 0x15c N001 ( 3, 2) [000726] -------N---- t726 = LCL_VAR ref (AX) V58 tmp28 $187 /--* t726 ref N003 ( 7, 5) [000727] DA--G------- * STORE_LCL_VAR ref V70 tmp40 d:2 N004 ( 3, 2) [000729] -------N---- t729 = LCL_VAR int (AX) V59 tmp29 $24b /--* t729 int N006 ( 7, 5) [000730] DA--G------- * STORE_LCL_VAR int V71 tmp41 d:2 N001 ( 3, 2) [000496] -------N---- t496 = LCL_VAR_ADDR byref V49 tmp19 * ref V49._bits (offs=0x00) -> V68 tmp38 * int V49._sign (offs=0x08) -> V69 tmp39 /--* t496 byref N004 ( 7, 6) [000752] DA--------L- * STORE_LCL_VAR byref V84 tmp54 d:2 N005 ( 3, 2) [000736] -------N---- t736 = LCL_VAR_ADDR byref V76 tmp46 /--* t736 byref N008 ( 3, 3) [000738] DA---------- * STORE_LCL_VAR byref V83 tmp53 d:2 N009 ( 1, 1) [000739] ------------ t739 = LCL_VAR byref V83 tmp53 u:2 Zero Fseq[_bits] $417 N011 ( 3, 2) [000741] -------N---- t741 = LCL_VAR ref V70 tmp40 u:2 (last use) $187 /--* t739 byref +--* t741 ref [000963] -A---------- * STOREIND ref N014 ( 1, 1) [000744] ------------ t744 = LCL_VAR byref V83 tmp53 u:2 (last use) $417 /--* t744 byref N016 ( 2, 2) [000746] -c---------- t746 = * LEA(b+8) byref N018 ( 3, 2) [000748] -------N---- t748 = LCL_VAR int V71 tmp41 u:2 (last use) $24b /--* t746 byref +--* t748 int [000964] -A--------L- * STOREIND int N021 ( 3, 2) [000753] ------------ t753 = LCL_VAR byref V84 tmp54 u:2 (last use) $415 /--* t753 byref [001061] ------------ t1061 = * PUTARG_REG byref REG rcx N022 ( 3, 2) [000754] -------N---- t754 = LCL_VAR_ADDR byref V76 tmp46 /--* t754 byref [001062] ------------ t1062 = * PUTARG_REG byref REG rdx /--* t1061 byref this in rcx +--* t1062 byref arg1 in rdx N024 ( 48, 34) [000499] --CXG------- t499 = * CALL int System.Numerics.BigInteger.CompareTo $2ae N025 ( 1, 1) [000502] -c---------- t502 = CNS_INT int 0 $40 /--* t499 int +--* t502 int N026 ( 50, 36) [000503] J--XG--N---- * LT void $367 N027 ( 52, 38) [000195] ---XG------- * JTRUE void ------------ BB33 [167..16B) -> BB35 (always), preds={BB32} succs={BB35} [000965] ------------ IL_OFFSET void IL offset: 0x167 N001 ( 1, 1) [000322] ------------ t322 = LCL_VAR int V19 loc16 u:2 (last use) $248 /--* t322 int N003 ( 5, 4) [000324] DA---------- * STORE_LCL_VAR int V34 tmp4 d:4 ------------ BB34 [16B..16F), preds={BB32} succs={BB35} [000966] ------------ IL_OFFSET void IL offset: 0x16b N001 ( 1, 1) [000196] ------------ t196 = LCL_VAR int V19 loc16 u:2 (last use) $248 N002 ( 1, 1) [000197] -c---------- t197 = CNS_INT int 1 $41 /--* t196 int +--* t197 int N003 ( 3, 3) [000198] ------------ t198 = * ADD int $368 /--* t198 int N005 ( 7, 6) [000200] DA---------- * STORE_LCL_VAR int V34 tmp4 d:3 ------------ BB35 [16F..1A4) -> BB40 (cond), preds={BB33,BB34} succs={BB36,BB40} N001 ( 0, 0) [000899] ------------ t899 = PHI_ARG int V34 tmp4 u:4 $248 N002 ( 0, 0) [000898] ------------ t898 = PHI_ARG int V34 tmp4 u:3 $368 /--* t899 int +--* t898 int N003 ( 0, 0) [000870] ------------ t870 = * PHI int /--* t870 int N005 ( 0, 0) [000871] DA---------- * STORE_LCL_VAR int V34 tmp4 d:2 N001 ( 3, 2) [000202] ------------ t202 = LCL_VAR int V34 tmp4 u:2 (last use) $24c /--* t202 int N003 ( 7, 5) [000204] DA---------- * STORE_LCL_VAR int V22 loc19 d:2 [000967] ------------ IL_OFFSET void IL offset: 0x171 N003 ( 3, 2) [000205] -------N---- t205 = LCL_VAR_ADDR byref V15 loc12 * ref V15._bits (offs=0x00) -> V56 tmp26 * int V15._sign (offs=0x08) -> V57 tmp27 /--* t205 byref [001063] ------------ t1063 = * PUTARG_REG byref REG rcx N005 ( 3, 2) [000207] ------------ t207 = LCL_VAR int V21 loc18 u:3 (last use) $249 /--* t207 int [001064] ------------ t1064 = * PUTARG_REG int REG rdx /--* t1063 byref arg0 in rcx +--* t1064 int arg1 in rdx N006 ( 20, 12) [000208] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft $VN.Void [000968] ------------ IL_OFFSET void IL offset: 0x17a N001 ( 3, 2) [000219] -------N---- t219 = LCL_VAR_ADDR byref V35 tmp5 * ref V35._bits (offs=0x00) -> V62 tmp32 * int V35._sign (offs=0x08) -> V63 tmp33 /--* t219 byref N004 ( 7, 6) [000797] DA--------L- * STORE_LCL_VAR long V88 tmp58 d:2 N005 ( 3, 2) [000762] -------N---- t762 = LCL_VAR_ADDR byref V76 tmp46 /--* t762 byref N008 ( 3, 3) [000764] DA---------- * STORE_LCL_VAR byref V85 tmp55 d:2 N009 ( 1, 1) [000765] ------------ t765 = LCL_VAR byref V85 tmp55 u:2 Zero Fseq[_bits] $41c N011 ( 3, 2) [000767] -------N---- t767 = LCL_VAR ref (AX) V56 tmp26 $188 /--* t765 byref +--* t767 ref [000969] -A--G------- * STOREIND ref N014 ( 1, 1) [000770] ------------ t770 = LCL_VAR byref V85 tmp55 u:2 (last use) $41c /--* t770 byref N016 ( 2, 2) [000772] -c---------- t772 = * LEA(b+8) byref N018 ( 3, 2) [000774] -------N---- t774 = LCL_VAR int (AX) V57 tmp27 $24d /--* t772 byref +--* t774 int [000970] -A--G-----L- * STOREIND int N021 ( 3, 2) [000781] -------N---- t781 = LCL_VAR_ADDR byref V86 tmp56 /--* t781 byref N024 ( 3, 3) [000783] DA---------- * STORE_LCL_VAR byref V87 tmp57 d:2 N025 ( 1, 1) [000784] ------------ t784 = LCL_VAR byref V87 tmp57 u:2 Zero Fseq[_bits] $41e N027 ( 3, 2) [000786] -------N---- t786 = LCL_VAR ref (AX) V58 tmp28 $189 /--* t784 byref +--* t786 ref [000971] -A--G------- * STOREIND ref N030 ( 1, 1) [000789] ------------ t789 = LCL_VAR byref V87 tmp57 u:2 (last use) $41e /--* t789 byref N032 ( 2, 2) [000791] -c---------- t791 = * LEA(b+8) byref N034 ( 3, 2) [000793] -------N---- t793 = LCL_VAR int (AX) V59 tmp29 $24e /--* t791 byref +--* t793 int [000972] -A--G-----L- * STOREIND int N038 ( 3, 2) [000798] ------------ t798 = LCL_VAR long V88 tmp58 u:2 (last use) $41b /--* t798 long [001065] ------------ t1065 = * PUTARG_REG long REG rcx N039 ( 3, 2) [000799] -------N---- t799 = LCL_VAR_ADDR byref V76 tmp46 /--* t799 byref [001066] ------------ t1066 = * PUTARG_REG byref REG rdx N041 ( 3, 2) [000801] -------N---- t801 = LCL_VAR_ADDR byref V86 tmp56 /--* t801 byref [001067] ------------ t1067 = * PUTARG_REG byref REG r8 N043 ( 3, 2) [000211] -------N---- t211 = LCL_VAR_ADDR byref V23 loc20 * ref V23._bits (offs=0x00) -> V60 tmp30 * int V23._sign (offs=0x08) -> V61 tmp31 /--* t211 byref [001068] ------------ t1068 = * PUTARG_REG byref REG r9 /--* t1065 long arg0 in rcx +--* t1066 byref arg1 in rdx +--* t1067 byref arg2 in r8 +--* t1068 byref arg3 in r9 N045 ( 78, 56) [000213] S-CXG------- * CALL void System.Numerics.BigInteger.DivRem $VN.Void N001 ( 3, 2) [000808] -------N---- t808 = LCL_VAR_ADDR byref V76 tmp46 /--* t808 byref N004 ( 3, 3) [000810] DA---------- * STORE_LCL_VAR byref V89 tmp59 d:2 N005 ( 1, 1) [000811] ------------ t811 = LCL_VAR byref V89 tmp59 u:2 Zero Fseq[_bits] $423 N007 ( 3, 2) [000813] -------N---- t813 = LCL_VAR ref (AX) V62 tmp32 $18a /--* t811 byref +--* t813 ref [000973] -A--G------- * STOREIND ref N010 ( 1, 1) [000816] ------------ t816 = LCL_VAR byref V89 tmp59 u:2 (last use) $423 /--* t816 byref N012 ( 2, 2) [000818] -c---------- t818 = * LEA(b+8) byref N014 ( 3, 2) [000820] -------N---- t820 = LCL_VAR int (AX) V63 tmp33 $24f /--* t818 byref +--* t820 int [000974] -A--G-----L- * STOREIND int N017 ( 3, 2) [000823] -------N---- t823 = LCL_VAR_ADDR byref V76 tmp46 /--* t823 byref [001069] ------------ t1069 = * PUTARG_REG byref REG rcx /--* t1069 byref arg0 in rcx N019 ( 38, 24) [000218] --CXG------- t218 = * CALL long System.Numerics.BigInteger.op_Explicit $450 /--* t218 long N021 ( 38, 24) [000226] DA-XG------- * STORE_LCL_VAR long V24 loc21 d:2 N001 ( 3, 2) [000514] -c---------- t514 = LCL_VAR int (AX) V61 tmp31 $250 N002 ( 1, 1) [000515] -c---------- t515 = CNS_INT int 0 $40 /--* t514 int +--* t515 int N003 ( 8, 4) [000516] ----G------- t516 = * EQ int $369 /--* t516 int N005 ( 12, 7) [000232] DA--G------- * STORE_LCL_VAR int V25 loc22 d:2 N002 ( 1, 1) [000233] ------------ t233 = LCL_VAR long V24 loc21 u:2 $450 /--* t233 long [001070] ------------ t1070 = * PUTARG_REG long REG rcx /--* t1070 long arg0 in rcx N003 ( 15, 7) [000234] --CXG------- t234 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $2b4 /--* t234 int N005 ( 19, 10) [000237] DA-XG------- * STORE_LCL_VAR int V26 loc23 d:2 [000975] ------------ IL_OFFSET void IL offset: 0x19e N001 ( 3, 2) [000238] ------------ t238 = LCL_VAR int V26 loc23 u:2 $2b4 N002 ( 3, 2) [000239] ------------ t239 = LCL_VAR int V20 loc17 u:2 $362 /--* t238 int +--* t239 int N003 ( 7, 5) [000240] N------N-U-- * LE void $36a N004 ( 9, 7) [000241] ------------ * JTRUE void ------------ BB36 [1A4..1AF) -> BB38 (cond), preds={BB35} succs={BB37,BB38} [000976] ------------ IL_OFFSET void IL offset: 0x1a4 N001 ( 3, 2) [000282] ------------ t282 = LCL_VAR int V26 loc23 u:2 (last use) $2b4 N002 ( 3, 2) [000283] ------------ t283 = LCL_VAR int V20 loc17 u:2 $362 /--* t282 int +--* t283 int N003 ( 7, 5) [000284] ------------ t284 = * SUB int $36b /--* t284 int N005 ( 11, 8) [000286] DA---------- * STORE_LCL_VAR int V29 loc26 d:2 [000977] ------------ IL_OFFSET void IL offset: 0x1ab N001 ( 3, 2) [000287] ------------ t287 = LCL_VAR int V25 loc22 u:2 (last use) $369 N002 ( 1, 1) [000288] -c---------- t288 = CNS_INT int 0 $40 /--* t287 int +--* t288 int N003 ( 5, 4) [000289] J------N---- * EQ void $36c N004 ( 7, 6) [000290] ------------ * JTRUE void ------------ BB37 [1AF..1C3) -> BB39 (always), preds={BB36} succs={BB39} [000978] ------------ IL_OFFSET void IL offset: 0x1af N001 ( 1, 1) [000305] ------------ t305 = LCL_VAR long V24 loc21 u:2 $450 N002 ( 3, 2) [000308] ------------ t308 = LCL_VAR int V29 loc26 u:2 $36b N005 ( 1, 1) [000307] ------------ t307 = CNS_INT long 1 $103 /--* t307 long +--* t308 int N006 ( 10, 6) [000311] ------------ t311 = * LSH long $48e N007 ( 1, 1) [000313] -c---------- t313 = CNS_INT long -1 $104 /--* t311 long +--* t313 long N008 ( 12, 8) [000314] ------------ t314 = * ADD long $48f /--* t305 long +--* t314 long N011 ( 19, 12) [000318] ------------ t318 = * TEST_EQ int $36e /--* t318 int N013 ( 23, 15) [000320] DA---------- * STORE_LCL_VAR int V37 tmp7 d:4 ------------ BB38 [1C3..1C4), preds={BB36} succs={BB39} [000979] ------------ IL_OFFSET void IL offset: 0x1c3 N001 ( 1, 1) [000291] ------------ t291 = CNS_INT int 0 $40 /--* t291 int N003 ( 5, 4) [000293] DA---------- * STORE_LCL_VAR int V37 tmp7 d:3 ------------ BB39 [1C4..1D0), preds={BB37,BB38} succs={BB40} N001 ( 0, 0) [000897] ------------ t897 = PHI_ARG int V37 tmp7 u:4 $36e N002 ( 0, 0) [000896] ------------ t896 = PHI_ARG int V37 tmp7 u:3 $40 /--* t897 int +--* t896 int N003 ( 0, 0) [000867] ------------ t867 = * PHI int /--* t867 int N005 ( 0, 0) [000868] DA---------- * STORE_LCL_VAR int V37 tmp7 d:2 N001 ( 3, 2) [000295] ------------ t295 = LCL_VAR int V37 tmp7 u:2 (last use) $251 /--* t295 int N002 ( 4, 4) [000826] ------------ t826 = * CAST int <- bool <- int $36f /--* t826 int N004 ( 8, 7) [000297] DA---------- * STORE_LCL_VAR int V25 loc22 d:4 [000980] ------------ IL_OFFSET void IL offset: 0x1c6 N001 ( 1, 1) [000298] ------------ t298 = LCL_VAR long V24 loc21 u:2 (last use) $450 N002 ( 3, 2) [000299] ------------ t299 = LCL_VAR int V29 loc26 u:2 (last use) $36b /--* t298 long +--* t299 int N005 ( 10, 6) [000302] ------------ t302 = * RSZ long $491 /--* t302 long N007 ( 10, 6) [000304] DA---------- * STORE_LCL_VAR long V24 loc21 d:4 ------------ BB40 [1D0..1E7) -> BB42 (cond), preds={BB35,BB39} succs={BB41,BB42} N001 ( 0, 0) [000894] ------------ t894 = PHI_ARG bool V25 loc22 u:4 $36f N002 ( 0, 0) [000889] ------------ t889 = PHI_ARG bool V25 loc22 u:2 $369 /--* t894 bool +--* t889 bool N003 ( 0, 0) [000864] ------------ t864 = * PHI bool /--* t864 bool N005 ( 0, 0) [000865] DA---------- * STORE_LCL_VAR bool V25 loc22 d:3 N001 ( 0, 0) [000895] ------------ t895 = PHI_ARG long V24 loc21 u:4 $491 N002 ( 0, 0) [000890] ------------ t890 = PHI_ARG long V24 loc21 u:2 $450 /--* t895 long +--* t890 long N003 ( 0, 0) [000861] ------------ t861 = * PHI long /--* t861 long N005 ( 0, 0) [000862] DA---------- * STORE_LCL_VAR long V24 loc21 d:3 N001 ( 3, 2) [000831] -------N---- t831 = LCL_VAR_ADDR byref V76 tmp46 /--* t831 byref N004 ( 3, 3) [000833] DA---------- * STORE_LCL_VAR byref V90 tmp60 d:2 N005 ( 1, 1) [000834] ------------ t834 = LCL_VAR byref V90 tmp60 u:2 Zero Fseq[_bits] $426 N007 ( 3, 2) [000836] -------N---- t836 = LCL_VAR ref (AX) V54 tmp24 $18b /--* t834 byref +--* t836 ref [000981] -A--G------- * STOREIND ref N010 ( 1, 1) [000839] ------------ t839 = LCL_VAR byref V90 tmp60 u:2 (last use) $426 /--* t839 byref N012 ( 2, 2) [000841] -c---------- t841 = * LEA(b+8) byref N014 ( 3, 2) [000843] -------N---- t843 = LCL_VAR int (AX) V55 tmp25 $252 /--* t841 byref +--* t843 int [000982] -A--G-----L- * STOREIND int N017 ( 3, 2) [000846] -------N---- t846 = LCL_VAR_ADDR byref V76 tmp46 /--* t846 byref [001071] ------------ t1071 = * PUTARG_REG byref REG rcx /--* t1071 byref arg0 in rcx N019 ( 38, 24) [000243] --CXG------- t243 = * CALL long System.Numerics.BigInteger.op_Explicit $454 N020 ( 3, 2) [000247] ------------ t247 = LCL_VAR int V20 loc17 u:2 (last use) $362 /--* t243 long +--* t247 int N023 ( 47, 29) [000250] ---XG------- t250 = * LSH long $492 N024 ( 1, 1) [000251] ------------ t251 = LCL_VAR long V24 loc21 u:3 (last use) $580 /--* t250 long +--* t251 long N025 ( 49, 31) [000252] ---XG------- t252 = * ADD long $493 /--* t252 long N027 ( 53, 34) [000254] DA-XG------- * STORE_LCL_VAR long V27 loc24 d:2 [000983] ------------ IL_OFFSET void IL offset: 0x1e2 N001 ( 1, 1) [000255] ------------ t255 = LCL_VAR int V13 loc10 u:2 $293 N002 ( 1, 1) [000256] -c---------- t256 = CNS_INT int 0 $40 /--* t255 int +--* t256 int N003 ( 3, 3) [000257] N------N---- * NE void $35a N004 ( 5, 5) [000258] ------------ * JTRUE void ------------ BB41 [1E7..1EE) -> BB43 (always), preds={BB40} succs={BB43} [000984] ------------ IL_OFFSET void IL offset: 0x1e7 N001 ( 3, 2) [000275] ------------ t275 = LCL_VAR int V22 loc19 u:2 (last use) $24c /--* t275 int N002 ( 4, 3) [000276] ------------ t276 = * NEG int $2c2 N003 ( 1, 1) [000277] -c---------- t277 = CNS_INT int -1 $43 /--* t276 int +--* t277 int N004 ( 6, 5) [000278] ------------ t278 = * ADD int $372 /--* t278 int N006 ( 10, 8) [000280] DA---------- * STORE_LCL_VAR int V36 tmp6 d:4 ------------ BB42 [1EE..1F2), preds={BB40} succs={BB43} [000985] ------------ IL_OFFSET void IL offset: 0x1ee N001 ( 1, 1) [000259] ------------ t259 = LCL_VAR int V13 loc10 u:2 (last use) $293 N002 ( 1, 1) [000260] -c---------- t260 = CNS_INT int -2 $68 /--* t259 int +--* t260 int N003 ( 3, 3) [000261] ------------ t261 = * ADD int $371 /--* t261 int N005 ( 7, 6) [000263] DA---------- * STORE_LCL_VAR int V36 tmp6 d:3 ------------ BB43 [1F2..202), preds={BB41,BB42} succs={BB44} N001 ( 0, 0) [000893] ------------ t893 = PHI_ARG int V36 tmp6 u:4 $372 N002 ( 0, 0) [000892] ------------ t892 = PHI_ARG int V36 tmp6 u:3 $371 /--* t893 int +--* t892 int N003 ( 0, 0) [000858] ------------ t858 = * PHI int /--* t858 int N005 ( 0, 0) [000859] DA---------- * STORE_LCL_VAR int V36 tmp6 d:2 [000986] ------------ IL_OFFSET void IL offset: 0x1f4 N005 ( 1, 1) [000272] ------------ t272 = LCL_VAR byref V02 arg2 u:1 (last use) $81 /--* t272 byref [001072] ------------ * PUTARG_STK [+0x20] void N006 ( 1, 1) [000268] ------------ t268 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t268 ref [001073] ------------ t1073 = * PUTARG_REG ref REG rcx N007 ( 3, 2) [000269] ------------ t269 = LCL_VAR long V27 loc24 u:2 (last use) $493 /--* t269 long [001074] ------------ t1074 = * PUTARG_REG long REG rdx N008 ( 3, 2) [000270] ------------ t270 = LCL_VAR int V36 tmp6 u:2 (last use) $253 /--* t270 int [001075] ------------ t1075 = * PUTARG_REG int REG r8 N009 ( 3, 2) [000271] ------------ t271 = LCL_VAR int V25 loc22 u:3 (last use) $540 /--* t271 int [001076] ------------ t1076 = * PUTARG_REG int REG r9 /--* t1073 ref this in rcx +--* t1074 long arg1 in rdx +--* t1075 int arg2 in r8 +--* t1076 int arg3 in r9 N010 ( 28, 18) [000273] --CXG------- t273 = * CALL int FloatingPointType.AssembleFloatingPointValue $2be /--* t273 int N012 ( 28, 18) [000853] DA-XG------- * STORE_LCL_VAR int V51 tmp21 d:4 ------------ BB44 [???..???) (return), preds={BB16,BB30,BB43} succs={} N001 ( 0, 0) [000901] ------------ t901 = PHI_ARG int V51 tmp21 u:5 $5c2 N002 ( 0, 0) [000891] ------------ t891 = PHI_ARG int V51 tmp21 u:4 $2be N003 ( 0, 0) [000887] ------------ t887 = PHI_ARG int V51 tmp21 u:3 $5c7 /--* t901 int +--* t891 int +--* t887 int N004 ( 0, 0) [000855] ------------ t855 = * PHI int /--* t855 int N006 ( 0, 0) [000856] DA---------- * STORE_LCL_VAR int V51 tmp21 d:2 N001 ( 1, 1) [000522] -------N---- t522 = LCL_VAR int V51 tmp21 u:2 (last use) $254 /--* t522 int N002 ( 2, 2) [000523] ------------ * RETURN int $5c9 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist Trees before Calculate stack level slots ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0056] 1 1 [???..???) i internal label target LIR BB02 [0000] 1 BB01 1 [000..00D)-> BB04 ( cond ) i label target idxlen LIR BB03 [0001] 1 BB02 0.50 [00D..017) (return) i hascall gcsafe LIR BB04 [0002] 1 BB02 0.50 [017..065)-> BB06 ( cond ) i label target hascall gcsafe LIR BB05 [0038] 1 BB04 0.50 [020..021)-> BB07 (always) i gcsafe LIR BB06 [0039] 1 BB04 0.50 [020..021) i label target gcsafe LIR BB07 [0040] 2 BB05,BB06 0.50 [000..000)-> BB09 ( cond ) i internal label target gcsafe idxlen LIR BB08 [0043] 1 BB07 0.50 [000..000)-> BB10 (always) i internal gcsafe LIR BB09 [0044] 1 BB07 0.50 [000..000) i internal label target gcsafe LIR BB10 [0045] 2 BB08,BB09 0.50 [???..???)-> BB14 ( cond ) i internal label target hascall gcsafe idxlen LIR BB11 [0003] 1 BB10 0.50 [065..070)-> BB13 ( cond ) i hascall gcsafe LIR BB12 [0004] 1 BB11 0.50 [070..07A) (return) i hascall gcsafe LIR BB13 [0005] 1 BB11 0.50 [07A..082) i label target hascall gcsafe LIR BB14 [0006] 2 BB10,BB13 0.50 [082..092)-> BB16 ( cond ) i label target hascall gcsafe LIR BB15 [0007] 1 BB14 0.50 [092..096)-> BB17 ( cond ) i gcsafe LIR BB16 [0008] 2 BB14,BB15 0.50 [096..0A7)-> BB44 (always) i label target hascall gcsafe LIR BB17 [0009] 1 BB15 0.50 [0A7..0B0)-> BB19 ( cond ) i label target gcsafe LIR BB18 [0010] 1 BB17 0.50 [0B0..0B4)-> BB20 (always) i gcsafe LIR BB19 [0011] 1 BB17 0.50 [0B4..0BE) i label target gcsafe LIR BB20 [0012] 2 BB18,BB19 0.50 [0BE..0C4)-> BB23 ( cond ) i label target gcsafe LIR BB21 [0013] 1 BB20 0.50 [0C4..0D9)-> BB23 ( cond ) i hascall gcsafe idxlen LIR BB22 [0014] 1 BB21 0.50 [0D9..0E3) (return) i hascall gcsafe LIR BB23 [0015] 2 BB20,BB21 0.50 [0E3..117)-> BB25 ( cond ) i label target hascall gcsafe LIR BB24 [0016] 1 BB23 0.50 [117..11A)-> BB26 (always) i gcsafe LIR BB25 [0017] 1 BB23 0.50 [11A..11F) i label target gcsafe LIR BB26 [0018] 2 BB24,BB25 0.50 [11F..126)-> BB28 ( cond ) i label target gcsafe LIR BB27 [0019] 1 BB26 0.50 [126..12F) i hascall gcsafe LIR BB28 [0020] 2 BB26,BB27 0.50 [12F..13E)-> BB32 ( cond ) i label target gcsafe LIR BB29 [0021] 1 BB28 0.50 [13E..144)-> BB31 ( cond ) i gcsafe LIR BB30 [0022] 1 BB29 0.50 [144..155)-> BB44 (always) i hascall gcsafe LIR BB31 [0023] 1 BB29 0.50 [155..15C) i label target gcsafe LIR BB32 [0024] 2 BB28,BB31 0.50 [15C..167)-> BB34 ( cond ) i label target hascall gcsafe LIR BB33 [0025] 1 BB32 0.50 [167..16B)-> BB35 (always) i gcsafe LIR BB34 [0026] 1 BB32 0.50 [16B..16F) i label target gcsafe LIR BB35 [0027] 2 BB33,BB34 0.50 [16F..1A4)-> BB40 ( cond ) i label target hascall gcsafe LIR BB36 [0028] 1 BB35 0.50 [1A4..1AF)-> BB38 ( cond ) i gcsafe LIR BB37 [0029] 1 BB36 0.50 [1AF..1C3)-> BB39 (always) i gcsafe LIR BB38 [0030] 1 BB36 0.50 [1C3..1C4) i label target gcsafe LIR BB39 [0031] 2 BB37,BB38 0.50 [1C4..1D0) i label target gcsafe LIR BB40 [0032] 2 BB35,BB39 0.50 [1D0..1E7)-> BB42 ( cond ) i label target hascall gcsafe LIR BB41 [0033] 1 BB40 0.50 [1E7..1EE)-> BB43 (always) i gcsafe LIR BB42 [0034] 1 BB40 0.50 [1EE..1F2) i label target gcsafe LIR BB43 [0035] 2 BB41,BB42 0.50 [1F2..202) i label target hascall gcsafe LIR BB44 [0054] 3 BB16,BB30,BB43 0.50 [???..???) (return) keep internal target gcsafe LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} N001 ( 1, 1) [000531] ------------ t531 = LCL_VAR byref V00 arg0 u:1 Zero Fseq[Mantissa] $80 /--* t531 byref N002 ( 3, 2) [000532] n----------- t532 = * IND ref /--* t532 ref N004 ( 3, 3) [000533] DA---------- * STORE_LCL_VAR ref V52 tmp22 d:2 N005 ( 1, 1) [000535] ------------ t535 = LCL_VAR byref V00 arg0 u:1 (last use) $80 /--* t535 byref N007 ( 2, 2) [000537] -c---------- t537 = * LEA(b+8) byref /--* t537 byref N008 ( 4, 4) [000538] n----------- t538 = * IND int /--* t538 int N010 ( 4, 4) [000539] DA---------- * STORE_LCL_VAR int V53 tmp23 d:2 ------------ BB02 [000..00D) -> BB04 (cond), preds={BB01} succs={BB03,BB04} [000910] ------------ IL_OFFSET void IL offset: 0x0 N001 ( 1, 1) [000002] ------------ t2 = LCL_VAR ref V52 tmp22 u:2 /--* t2 ref [000988] -c---------- t988 = * LEA(b+8) ref /--* t988 ref N002 ( 3, 3) [000003] -c-XG------- t3 = * IND int N003 ( 1, 1) [000004] -c---------- t4 = CNS_INT int 0 $40 /--* t3 int +--* t4 int N004 ( 5, 5) [000005] J--XG--N---- * NE void N005 ( 7, 7) [000006] ---XG------- * JTRUE void ------------ BB03 [00D..017) (return), preds={BB02} succs={} [000911] ------------ IL_OFFSET void IL offset: 0xd N002 ( 1, 1) [000400] ------------ t400 = LCL_VAR ref V01 arg1 u:1 $c0 /--* t400 ref [000995] ------------ t995 = * PUTARG_REG ref REG rcx N001 ( 1, 1) [000996] ------------ t996 = LCL_VAR ref V01 arg1 (last use) /--* t996 ref N002 ( 2, 2) [000997] -c---------- t997 = * LEA(b+0) byref /--* t997 byref N003 ( 5, 4) [000998] ------------ t998 = * IND long /--* t998 long N004 ( 6, 5) [000999] -c---------- t999 = * LEA(b+80) long /--* t999 long N005 ( 9, 7) [001000] ------------ t1000 = * IND long /--* t1000 long N006 ( 10, 8) [001001] -c---------- t1001 = * LEA(b+0) long /--* t1001 long N007 ( 13, 10) [001002] -c---------- t1002 = * IND long REG NA /--* t995 ref this in rcx +--* t1002 long control expr N003 ( 21, 10) [000401] --CXG------- t401 = * CALLV ind long FloatingPointType.get_Zero $459 N004 ( 1, 1) [000399] ------------ t399 = LCL_VAR byref V02 arg2 u:1 (last use) $81 /--* t399 byref +--* t401 long [000912] -ACXG------- * STOREIND long N001 ( 1, 1) [000404] ------------ t404 = CNS_INT int 1 $41 /--* t404 int N002 ( 2, 2) [000520] ------------ * RETURN int $5cb ------------ BB04 [017..065) -> BB06 (cond), preds={BB02} succs={BB05,BB06} N002 ( 1, 1) [000007] ------------ t7 = LCL_VAR ref V01 arg1 u:1 $c0 /--* t7 ref [001003] ------------ t1003 = * PUTARG_REG ref REG rcx N001 ( 1, 1) [001004] ------------ t1004 = LCL_VAR ref V01 arg1 /--* t1004 ref N002 ( 2, 2) [001005] -c---------- t1005 = * LEA(b+0) byref /--* t1005 byref N003 ( 5, 4) [001006] ------------ t1006 = * IND long /--* t1006 long N004 ( 6, 5) [001007] -c---------- t1007 = * LEA(b+72) long /--* t1007 long N005 ( 9, 7) [001008] ------------ t1008 = * IND long /--* t1008 long N006 ( 10, 8) [001009] -c---------- t1009 = * LEA(b+32) long /--* t1009 long N007 ( 13, 10) [001010] -c---------- t1010 = * IND long REG NA /--* t1003 ref this in rcx +--* t1010 long control expr N003 ( 21, 10) [000406] --CXG------- t406 = * CALLV ind int FloatingPointType.get_DenormalMantissaBits $282 N004 ( 1, 1) [000407] -c---------- t407 = CNS_INT int 1 $41 /--* t406 int +--* t407 int N005 ( 23, 12) [000408] ---XG------- t408 = * ADD int $346 /--* t408 int N006 ( 24, 14) [000409] ---XG------- t409 = * CAST int <- ushort <- int $347 N007 ( 1, 1) [000010] -c---------- t10 = CNS_INT int 1 $41 /--* t409 int +--* t10 int N008 ( 26, 16) [000011] ---XG------- t11 = * ADD int $348 /--* t11 int N010 ( 30, 19) [000013] DA-XG------- * STORE_LCL_VAR int V03 loc0 d:2 [000913] ------------ IL_OFFSET void IL offset: 0x20 N001 ( 1, 1) [000017] ------------ t17 = LCL_VAR int V53 tmp23 u:2 /--* t17 int N003 ( 5, 4) [000424] DA--G------- * STORE_LCL_VAR int V40 tmp10 d:2 [000914] ------------ IL_OFFSET void IL offset: 0x20 N001 ( 1, 1) [000412] ------------ t412 = LCL_VAR int V40 tmp10 u:2 (last use) N002 ( 1, 1) [000411] -c---------- t411 = CNS_INT int 0 $40 /--* t412 int +--* t411 int N003 ( 3, 3) [000413] J------N---- * LE void N004 ( 5, 5) [000414] ------------ * JTRUE void ------------ BB05 [020..021) -> BB07 (always), preds={BB04} succs={BB07} [000915] ------------ IL_OFFSET void IL offset: 0x20 N001 ( 3, 2) [000419] ------------ t419 = LCL_VAR int V53 tmp23 u:2 /--* t419 int N003 ( 7, 5) [000421] DA---------- * STORE_LCL_VAR int V39 tmp9 d:4 ------------ BB06 [020..021), preds={BB04} succs={BB07} [000916] ------------ IL_OFFSET void IL offset: 0x20 N001 ( 1, 1) [000415] ------------ t415 = CNS_INT int 0 $40 /--* t415 int N003 ( 5, 4) [000417] DA---------- * STORE_LCL_VAR int V39 tmp9 d:3 ------------ BB07 [000..000) -> BB09 (cond), preds={BB05,BB06} succs={BB08,BB09} N001 ( 0, 0) [000909] ------------ t909 = PHI_ARG int V39 tmp9 u:4 N002 ( 0, 0) [000908] ------------ t908 = PHI_ARG int V39 tmp9 u:3 $40 /--* t909 int +--* t908 int N003 ( 0, 0) [000885] ------------ t885 = * PHI int /--* t885 int N005 ( 0, 0) [000886] DA---------- * STORE_LCL_VAR int V39 tmp9 d:2 N001 ( 3, 2) [000422] ------------ t422 = LCL_VAR int V39 tmp9 u:2 (last use) $241 /--* t422 int N003 ( 3, 3) [000021] DA---------- * STORE_LCL_VAR int V31 tmp1 d:2 N001 ( 1, 1) [000428] ------------ t428 = LCL_VAR ref V52 tmp22 u:2 /--* t428 ref [000990] -c---------- t990 = * LEA(b+8) ref /--* t990 ref N002 ( 3, 3) [000429] ---XG------- t429 = * IND int /--* t429 int N004 ( 3, 3) [000443] DA-XG------- * STORE_LCL_VAR int V42 tmp12 d:2 N001 ( 3, 2) [000023] ------------ t23 = LCL_VAR int V31 tmp1 u:2 $241 N002 ( 1, 1) [000431] ------------ t431 = LCL_VAR int V42 tmp12 u:2 /--* t23 int +--* t431 int N003 ( 5, 4) [000432] N------N-U-- * LE void N004 ( 7, 6) [000433] ------------ * JTRUE void ------------ BB08 [000..000) -> BB10 (always), preds={BB07} succs={BB10} N001 ( 1, 1) [000438] ------------ t438 = LCL_VAR int V42 tmp12 u:2 (last use) /--* t438 int N003 ( 1, 3) [000440] DA---------- * STORE_LCL_VAR int V41 tmp11 d:4 ------------ BB09 [000..000), preds={BB07} succs={BB10} N001 ( 1, 1) [000434] ------------ t434 = LCL_VAR int V31 tmp1 u:2 $241 /--* t434 int N003 ( 1, 3) [000436] DA---------- * STORE_LCL_VAR int V41 tmp11 d:3 ------------ BB10 [???..???) -> BB14 (cond), preds={BB08,BB09} succs={BB11,BB14} N001 ( 0, 0) [000907] ------------ t907 = PHI_ARG int V41 tmp11 u:4 N002 ( 0, 0) [000906] ------------ t906 = PHI_ARG int V41 tmp11 u:3 $241 /--* t907 int +--* t906 int N003 ( 0, 0) [000882] ------------ t882 = * PHI int /--* t882 int N005 ( 0, 0) [000883] DA---------- * STORE_LCL_VAR int V41 tmp11 d:2 N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR int V31 tmp1 u:2 (last use) $241 N002 ( 1, 1) [000032] ------------ t32 = LCL_VAR int V41 tmp11 u:2 $242 /--* t22 int +--* t32 int N003 ( 3, 3) [000033] ------------ t33 = * SUB int $34e /--* t33 int N005 ( 7, 6) [000035] DA---------- * STORE_LCL_VAR int V05 loc2 d:2 [000917] ------------ IL_OFFSET void IL offset: 0x42 N001 ( 1, 1) [000042] ------------ t42 = LCL_VAR int V41 tmp11 u:2 (last use) $242 /--* t42 int N003 ( 5, 4) [000044] DA---------- * STORE_LCL_VAR int V08 loc5 d:2 N001 ( 1, 1) [000447] ------------ t447 = LCL_VAR ref V52 tmp22 u:2 /--* t447 ref [000992] -c---------- t992 = * LEA(b+8) ref /--* t992 ref N002 ( 3, 3) [000448] ---XG------- t448 = * IND int /--* t448 int N004 ( 7, 6) [000050] DA-XG------- * STORE_LCL_VAR int V09 loc6 d:2 [000918] ------------ IL_OFFSET void IL offset: 0x4f N001 ( 3, 2) [000051] ------------ t51 = LCL_VAR int V09 loc6 u:2 N002 ( 1, 1) [000052] ------------ t52 = LCL_VAR int V08 loc5 u:2 $242 /--* t51 int +--* t52 int N003 ( 5, 4) [000053] ------------ t53 = * SUB int /--* t53 int N005 ( 5, 4) [000055] DA---------- * STORE_LCL_VAR int V10 loc7 d:2 N001 ( 3, 2) [000063] -------N---- t63 = LCL_VAR_ADDR byref V11 loc8 * ref V11._bits (offs=0x00) -> V54 tmp24 * int V11._sign (offs=0x08) -> V55 tmp25 /--* t63 byref N004 ( 7, 6) [000563] DA--------L- * STORE_LCL_VAR long V75 tmp45 d:2 N005 ( 3, 2) [000547] -------N---- t547 = LCL_VAR_ADDR byref V73 tmp43 /--* t547 byref N008 ( 3, 3) [000549] DA---------- * STORE_LCL_VAR byref V74 tmp44 d:2 N009 ( 1, 1) [000550] ------------ t550 = LCL_VAR byref V74 tmp44 u:2 Zero Fseq[Mantissa] $401 N011 ( 1, 1) [000552] -------N---- t552 = LCL_VAR ref V52 tmp22 u:2 /--* t550 byref +--* t552 ref [000919] -A---------- * STOREIND ref N014 ( 1, 1) [000555] ------------ t555 = LCL_VAR byref V74 tmp44 u:2 (last use) $401 /--* t555 byref N016 ( 2, 2) [000557] -c---------- t557 = * LEA(b+8) byref N018 ( 1, 1) [000559] -------N---- t559 = LCL_VAR int V53 tmp23 u:2 /--* t557 byref +--* t559 int [000920] -A--------L- * STOREIND int N023 ( 3, 2) [000564] ------------ t564 = LCL_VAR long V75 tmp45 u:2 (last use) $400 /--* t564 long [001011] ------------ t1011 = * PUTARG_REG long REG rcx N024 ( 3, 2) [000565] -------N---- t565 = LCL_VAR_ADDR byref V73 tmp43 /--* t565 byref [001012] ------------ t1012 = * PUTARG_REG byref REG rdx N026 ( 1, 1) [000058] ------------ t58 = LCL_VAR int V08 loc5 u:2 $242 /--* t58 int [001013] ------------ t1013 = * PUTARG_REG int REG r9 N027 ( 1, 1) [000057] ------------ t57 = CNS_INT int 0 $40 /--* t57 int [001014] ------------ t1014 = * PUTARG_REG int REG r8 /--* t1011 long arg0 in rcx +--* t1012 byref arg1 in rdx +--* t1013 int arg3 in r9 +--* t1014 int arg2 in r8 N028 ( 49, 35) [000059] S-CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger $VN.Void [000921] ------------ IL_OFFSET void IL offset: 0x61 N001 ( 3, 2) [000065] ------------ t65 = LCL_VAR int V05 loc2 u:2 $34e N002 ( 1, 1) [000066] -c---------- t66 = CNS_INT int 0 $40 /--* t65 int +--* t66 int N003 ( 5, 4) [000067] N------N---- * EQ void $351 N004 ( 7, 6) [000068] ------------ * JTRUE void ------------ BB11 [065..070) -> BB13 (cond), preds={BB10} succs={BB12,BB13} N002 ( 1, 1) [000382] ------------ t382 = LCL_VAR ref V01 arg1 u:1 $c0 /--* t382 ref [001015] ------------ t1015 = * PUTARG_REG ref REG rcx /--* t1015 ref this in rcx N003 ( 15, 8) [000383] --CXG------- t383 = * CALL int FloatingPointType.get_OverflowDecimalExponent $291 /--* t383 int N004 ( 16, 10) [000385] ---XG------- t385 = * CAST long <- int $480 N005 ( 3, 2) [000380] ------------ t380 = LCL_VAR int V05 loc2 u:2 $34e /--* t380 int N006 ( 4, 4) [000381] ---------U-- t381 = * CAST long <- ulong <- uint $481 /--* t385 long +--* t381 long N007 ( 21, 15) [000386] J--XG--N---- * GE void $352 N008 ( 23, 17) [000387] ---XG------- * JTRUE void ------------ BB12 [070..07A) (return), preds={BB11} succs={} [000922] ------------ IL_OFFSET void IL offset: 0x70 N002 ( 1, 1) [000393] ------------ t393 = LCL_VAR ref V01 arg1 u:1 $c0 /--* t393 ref [001016] ------------ t1016 = * PUTARG_REG ref REG rcx N001 ( 1, 1) [001017] ------------ t1017 = LCL_VAR ref V01 arg1 (last use) /--* t1017 ref N002 ( 2, 2) [001018] -c---------- t1018 = * LEA(b+0) byref /--* t1018 byref N003 ( 5, 4) [001019] ------------ t1019 = * IND long /--* t1019 long N004 ( 6, 5) [001020] -c---------- t1020 = * LEA(b+80) long /--* t1020 long N005 ( 9, 7) [001021] ------------ t1021 = * IND long /--* t1021 long N006 ( 10, 8) [001022] -c---------- t1022 = * LEA(b+8) long /--* t1022 long N007 ( 13, 10) [001023] -c---------- t1023 = * IND long REG NA /--* t1016 ref this in rcx +--* t1023 long control expr N003 ( 21, 10) [000394] --CXG------- t394 = * CALLV ind long FloatingPointType.get_Infinity $458 N004 ( 1, 1) [000392] ------------ t392 = LCL_VAR byref V02 arg2 u:1 (last use) $81 /--* t392 byref +--* t394 long [000923] -ACXG------- * STOREIND long N001 ( 1, 1) [000397] ------------ t397 = CNS_INT int 3 $48 /--* t397 int N002 ( 2, 2) [000521] ------------ * RETURN int $5ca ------------ BB13 [07A..082), preds={BB11} succs={BB14} [000924] ------------ IL_OFFSET void IL offset: 0x7a N003 ( 3, 2) [000388] -------N---- t388 = LCL_VAR_ADDR byref V11 loc8 * ref V11._bits (offs=0x00) -> V54 tmp24 * int V11._sign (offs=0x08) -> V55 tmp25 /--* t388 byref [001024] ------------ t1024 = * PUTARG_REG byref REG rcx N005 ( 3, 2) [000390] ------------ t390 = LCL_VAR int V05 loc2 u:2 (last use) $34e /--* t390 int [001025] ------------ t1025 = * PUTARG_REG int REG rdx /--* t1024 byref arg0 in rcx +--* t1025 int arg1 in rdx N006 ( 20, 12) [000391] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen $VN.Void ------------ BB14 [082..092) -> BB16 (cond), preds={BB10,BB13} succs={BB15,BB16} N001 ( 3, 2) [000577] -------N---- t577 = LCL_VAR_ADDR byref V76 tmp46 /--* t577 byref N004 ( 3, 3) [000579] DA---------- * STORE_LCL_VAR byref V77 tmp47 d:2 N005 ( 1, 1) [000580] ------------ t580 = LCL_VAR byref V77 tmp47 u:2 Zero Fseq[_bits] $405 N007 ( 3, 2) [000582] -------N---- t582 = LCL_VAR ref (AX) V54 tmp24 $181 /--* t580 byref +--* t582 ref [000925] -A--G------- * STOREIND ref N010 ( 1, 1) [000585] ------------ t585 = LCL_VAR byref V77 tmp47 u:2 (last use) $405 /--* t585 byref N012 ( 2, 2) [000587] -c---------- t587 = * LEA(b+8) byref N014 ( 3, 2) [000589] -------N---- t589 = LCL_VAR int (AX) V55 tmp25 $243 /--* t587 byref +--* t589 int [000926] -A--G-----L- * STOREIND int N018 ( 3, 2) [000592] -------N---- t592 = LCL_VAR_ADDR byref V76 tmp46 /--* t592 byref [001026] ------------ t1026 = * PUTARG_REG byref REG rcx N020 ( 3, 3) [000071] ------------ t71 = LCL_VAR_ADDR long V12 loc9 $443 /--* t71 long [001027] ------------ t1027 = * PUTARG_REG long REG rdx /--* t1026 byref arg0 in rcx +--* t1027 long arg1 in rdx N021 ( 41, 28) [000072] --CXG------- t72 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $293 /--* t72 int N023 ( 41, 28) [000077] DA-XG------- * STORE_LCL_VAR int V13 loc10 d:2 [000927] ------------ IL_OFFSET void IL offset: 0x8d N001 ( 1, 1) [000078] ------------ t78 = LCL_VAR int V13 loc10 u:2 $293 N002 ( 3, 2) [000079] ------------ t79 = LCL_VAR int V03 loc0 u:2 $348 /--* t78 int +--* t79 int N003 ( 5, 4) [000080] N------N-U-- * GE void $353 N004 ( 7, 6) [000081] ------------ * JTRUE void ------------ BB15 [092..096) -> BB17 (cond), preds={BB14} succs={BB16,BB17} [000928] ------------ IL_OFFSET void IL offset: 0x92 N001 ( 1, 1) [000091] ------------ t91 = LCL_VAR int V10 loc7 u:2 N002 ( 1, 1) [000092] -c---------- t92 = CNS_INT int 0 $40 /--* t91 int +--* t92 int N003 ( 3, 3) [000093] J------N---- * NE void N004 ( 5, 5) [000094] ------------ * JTRUE void ------------ BB16 [096..0A7) -> BB44 (always), preds={BB14,BB15} succs={BB44} [000929] ------------ IL_OFFSET void IL offset: 0x96 N005 ( 1, 1) [000088] ------------ t88 = LCL_VAR byref V02 arg2 u:1 (last use) $81 /--* t88 byref [001028] ------------ * PUTARG_STK [+0x20] void N006 ( 1, 1) [000084] ------------ t84 = LCL_VAR int V10 loc7 u:2 (last use) N007 ( 1, 1) [000085] -c---------- t85 = CNS_INT int 0 $40 /--* t84 int +--* t85 int N008 ( 6, 3) [000086] N----------- t86 = * NE int /--* t86 int [001029] ------------ t1029 = * PUTARG_REG int REG r8 N009 ( 3, 2) [000082] ------------ t82 = LCL_VAR ref (AX) V12 loc9 $18d /--* t82 ref [001030] ------------ t1030 = * PUTARG_REG ref REG rcx N010 ( 1, 1) [000083] ------------ t83 = LCL_VAR int V13 loc10 u:2 (last use) $293 /--* t83 int [001031] ------------ t1031 = * PUTARG_REG int REG rdx N011 ( 1, 1) [000087] ------------ t87 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t87 ref [001032] ------------ t1032 = * PUTARG_REG ref REG r9 /--* t1029 int arg2 in r8 +--* t1030 ref arg0 in rcx +--* t1031 int arg1 in rdx +--* t1032 ref arg3 in r9 N012 ( 29, 17) [000089] --CXG------- t89 = * CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits $5c7 /--* t89 int N014 ( 29, 17) [000600] DA-XG------- * STORE_LCL_VAR int V51 tmp21 d:3 ------------ BB17 [0A7..0B0) -> BB19 (cond), preds={BB15} succs={BB18,BB19} [000930] ------------ IL_OFFSET void IL offset: 0xa7 N001 ( 1, 1) [000097] ------------ t97 = LCL_VAR int V53 tmp23 u:2 N002 ( 1, 1) [000098] -c---------- t98 = CNS_INT int 0 $40 /--* t97 int +--* t98 int N003 ( 3, 3) [000099] J---G--N---- * LT void N004 ( 5, 5) [000100] ----G------- * JTRUE void ------------ BB18 [0B0..0B4) -> BB20 (always), preds={BB17} succs={BB20} [000931] ------------ IL_OFFSET void IL offset: 0xb0 N001 ( 1, 1) [000376] ------------ t376 = LCL_VAR int V10 loc7 u:2 (last use) /--* t376 int N003 ( 5, 4) [000378] DA---------- * STORE_LCL_VAR int V32 tmp2 d:4 ------------ BB19 [0B4..0BE), preds={BB17} succs={BB20} [000932] ------------ IL_OFFSET void IL offset: 0xb4 N001 ( 1, 1) [000101] ------------ t101 = LCL_VAR int V10 loc7 u:2 (last use) N002 ( 1, 1) [000104] ------------ t104 = LCL_VAR int V53 tmp23 u:2 /--* t101 int +--* t104 int N003 ( 3, 3) [000106] ----G------- t106 = * SUB int /--* t106 int N005 ( 7, 6) [000108] DA--G------- * STORE_LCL_VAR int V32 tmp2 d:3 ------------ BB20 [0BE..0C4) -> BB23 (cond), preds={BB18,BB19} succs={BB21,BB23} N001 ( 0, 0) [000905] ------------ t905 = PHI_ARG int V32 tmp2 u:4 N002 ( 0, 0) [000904] ------------ t904 = PHI_ARG int V32 tmp2 u:3 /--* t905 int +--* t904 int N003 ( 0, 0) [000879] ------------ t879 = * PHI int /--* t879 int N005 ( 0, 0) [000880] DA---------- * STORE_LCL_VAR int V32 tmp2 d:2 N001 ( 3, 2) [000110] ------------ t110 = LCL_VAR int V32 tmp2 u:2 (last use) $244 /--* t110 int N003 ( 7, 5) [000112] DA---------- * STORE_LCL_VAR int V14 loc11 d:2 [000933] ------------ IL_OFFSET void IL offset: 0xc0 N001 ( 1, 1) [000113] ------------ t113 = LCL_VAR int V13 loc10 u:2 $293 N002 ( 1, 1) [000114] -c---------- t114 = CNS_INT int 0 $40 /--* t113 int +--* t114 int N003 ( 3, 3) [000115] J------N---- * NE void $35a N004 ( 5, 5) [000116] ------------ * JTRUE void ------------ BB21 [0C4..0D9) -> BB23 (cond), preds={BB20} succs={BB22,BB23} N001 ( 1, 1) [000455] ------------ t455 = LCL_VAR ref V52 tmp22 u:2 /--* t455 ref [000994] -c---------- t994 = * LEA(b+8) ref /--* t994 ref N002 ( 3, 3) [000456] ---XG------- t456 = * IND int /--* t456 int N003 ( 4, 5) [000358] ---XG------- t358 = * CAST long <- int N004 ( 3, 2) [000352] ------------ t352 = LCL_VAR int V14 loc11 u:2 $244 /--* t352 int N005 ( 4, 4) [000353] ---------U-- t353 = * CAST long <- ulong <- uint $486 /--* t353 long +--* t358 long N006 ( 9, 10) [000359] ---XG------- t359 = * SUB long /--* t359 long N008 ( 13, 13) [000363] DA-XG------- * STORE_LCL_VAR long V38 tmp8 d:2 N002 ( 1, 1) [000360] ------------ t360 = LCL_VAR ref V01 arg1 u:1 $c0 /--* t360 ref [001033] ------------ t1033 = * PUTARG_REG ref REG rcx /--* t1033 ref this in rcx N003 ( 15, 8) [000361] --CXG------- t361 = * CALL int FloatingPointType.get_OverflowDecimalExponent $298 /--* t361 int N004 ( 16, 10) [000366] ---XG------- t366 = * CAST long <- int $48b N005 ( 3, 2) [000364] ------------ t364 = LCL_VAR long V38 tmp8 u:2 (last use) /--* t366 long +--* t364 long N006 ( 20, 13) [000367] J--XG--N---- * GE void N007 ( 22, 15) [000368] ---XG------- * JTRUE void ------------ BB22 [0D9..0E3) (return), preds={BB21} succs={} [000934] ------------ IL_OFFSET void IL offset: 0xd9 N002 ( 1, 1) [000370] ------------ t370 = LCL_VAR ref V01 arg1 u:1 $c0 /--* t370 ref [001034] ------------ t1034 = * PUTARG_REG ref REG rcx N001 ( 1, 1) [001035] ------------ t1035 = LCL_VAR ref V01 arg1 (last use) /--* t1035 ref N002 ( 2, 2) [001036] -c---------- t1036 = * LEA(b+0) byref /--* t1036 byref N003 ( 5, 4) [001037] ------------ t1037 = * IND long /--* t1037 long N004 ( 6, 5) [001038] -c---------- t1038 = * LEA(b+80) long /--* t1038 long N005 ( 9, 7) [001039] ------------ t1039 = * IND long /--* t1039 long N006 ( 10, 8) [001040] -c---------- t1040 = * LEA(b+0) long /--* t1040 long N007 ( 13, 10) [001041] -c---------- t1041 = * IND long REG NA /--* t1034 ref this in rcx +--* t1041 long control expr N003 ( 21, 10) [000371] --CXG------- t371 = * CALLV ind long FloatingPointType.get_Zero $457 N004 ( 1, 1) [000369] ------------ t369 = LCL_VAR byref V02 arg2 u:1 (last use) $81 /--* t369 byref +--* t371 long [000935] -ACXG------- * STOREIND long N001 ( 1, 1) [000374] ------------ t374 = CNS_INT int 2 $42 /--* t374 int N002 ( 2, 2) [000524] ------------ * RETURN int $5c4 ------------ BB23 [0E3..117) -> BB25 (cond), preds={BB20,BB21} succs={BB24,BB25} N001 ( 3, 2) [000124] -------N---- t124 = LCL_VAR_ADDR byref V15 loc12 * ref V15._bits (offs=0x00) -> V56 tmp26 * int V15._sign (offs=0x08) -> V57 tmp27 /--* t124 byref N004 ( 7, 6) [000623] DA--------L- * STORE_LCL_VAR long V79 tmp49 d:2 N005 ( 3, 2) [000607] -------N---- t607 = LCL_VAR_ADDR byref V73 tmp43 /--* t607 byref N008 ( 3, 3) [000609] DA---------- * STORE_LCL_VAR byref V78 tmp48 d:2 N009 ( 1, 1) [000610] ------------ t610 = LCL_VAR byref V78 tmp48 u:2 Zero Fseq[Mantissa] $409 N011 ( 1, 1) [000612] -------N---- t612 = LCL_VAR ref V52 tmp22 u:2 (last use) /--* t610 byref +--* t612 ref [000936] -A---------- * STOREIND ref N014 ( 1, 1) [000615] ------------ t615 = LCL_VAR byref V78 tmp48 u:2 (last use) $409 /--* t615 byref N016 ( 2, 2) [000617] -c---------- t617 = * LEA(b+8) byref N018 ( 1, 1) [000619] -------N---- t619 = LCL_VAR int V53 tmp23 u:2 (last use) /--* t617 byref +--* t619 int [000937] -A--------L- * STOREIND int N023 ( 3, 2) [000624] ------------ t624 = LCL_VAR long V79 tmp49 u:2 (last use) $408 /--* t624 long [001042] ------------ t1042 = * PUTARG_REG long REG rcx N024 ( 3, 2) [000625] -------N---- t625 = LCL_VAR_ADDR byref V73 tmp43 /--* t625 byref [001043] ------------ t1043 = * PUTARG_REG byref REG rdx N026 ( 3, 2) [000118] ------------ t118 = LCL_VAR int V08 loc5 u:2 (last use) $242 /--* t118 int [001044] ------------ t1044 = * PUTARG_REG int REG r8 N027 ( 3, 2) [000119] ------------ t119 = LCL_VAR int V09 loc6 u:2 (last use) /--* t119 int [001045] ------------ t1045 = * PUTARG_REG int REG r9 /--* t1042 long arg0 in rcx +--* t1043 byref arg1 in rdx +--* t1044 int arg2 in r8 +--* t1045 int arg3 in r9 N028 ( 53, 37) [000120] S-CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger $VN.Void [000938] ------------ IL_OFFSET void IL offset: 0xef N003 ( 2, 10) [000131] ------------ t131 = CNS_INT long 0x7ff815262aa0 $102 /--* t131 long [001046] ------------ t1046 = * PUTARG_REG long REG rcx N004 ( 1, 4) [000132] ------------ t132 = CNS_INT int 173 $58 /--* t132 int [001047] ------------ t1047 = * PUTARG_REG int REG rdx /--* t1046 long arg0 in rcx +--* t1047 int arg1 in rdx N005 ( 17, 21) [000133] H-CXG------- t133 = * CALL help long HELPER.CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE $48d N001 ( 2, 10) [000634] I----------- t634 = CNS_INT(h) long 0xd1ffab1e static Fseq[BigOne] $4c2 /--* t634 long N002 ( 4, 12) [000633] n---G------- t633 = * IND ref N003 ( 1, 1) [000635] -c---------- t635 = CNS_INT long 8 Fseq[#FirstElem] $101 /--* t633 ref +--* t635 long N004 ( 6, 14) [000632] ----G------- t632 = * ADD byref /--* t632 byref N006 ( 6, 14) [000637] DA--G------- * STORE_LCL_VAR byref V80 tmp50 d:2 N007 ( 1, 1) [000639] ------------ t639 = LCL_VAR byref V80 tmp50 u:2 Zero Fseq[_bits] /--* t639 byref N008 ( 3, 2) [000640] ---X-------- t640 = * IND ref /--* t640 ref N010 ( 7, 5) [000641] DA-XG------- * STORE_LCL_VAR ref (AX) V58 tmp28 N012 ( 1, 1) [000644] ------------ t644 = LCL_VAR byref V80 tmp50 u:2 (last use) /--* t644 byref N014 ( 2, 2) [000646] -c---------- t646 = * LEA(b+8) byref /--* t646 byref N015 ( 4, 4) [000647] ---X-------- t647 = * IND int /--* t647 int N017 ( 8, 7) [000648] DA-XG------- * STORE_LCL_VAR int (AX) V59 tmp29 [000939] ------------ IL_OFFSET void IL offset: 0xf6 N003 ( 3, 2) [000138] -------N---- t138 = LCL_VAR_ADDR byref V16 loc13 * ref V16._bits (offs=0x00) -> V58 tmp28 * int V16._sign (offs=0x08) -> V59 tmp29 /--* t138 byref [001048] ------------ t1048 = * PUTARG_REG byref REG rcx N005 ( 3, 2) [000140] ------------ t140 = LCL_VAR int V14 loc11 u:2 (last use) $244 /--* t140 int [001049] ------------ t1049 = * PUTARG_REG int REG rdx /--* t1048 byref arg0 in rcx +--* t1049 int arg1 in rdx N006 ( 20, 12) [000141] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen $VN.Void [000940] ------------ IL_OFFSET void IL offset: 0xff N001 ( 3, 2) [000653] -------N---- t653 = LCL_VAR ref (AX) V56 tmp26 $184 /--* t653 ref N003 ( 7, 5) [000654] DA--G------- * STORE_LCL_VAR ref V64 tmp34 d:2 N004 ( 3, 2) [000656] -------N---- t656 = LCL_VAR int (AX) V57 tmp27 $246 /--* t656 int N006 ( 7, 5) [000657] DA--G------- * STORE_LCL_VAR int V65 tmp35 d:2 [000941] ------------ IL_OFFSET void IL offset: 0xff N001 ( 3, 2) [000663] -------N---- t663 = LCL_VAR_ADDR byref V76 tmp46 /--* t663 byref N004 ( 3, 3) [000665] DA---------- * STORE_LCL_VAR byref V81 tmp51 d:2 N005 ( 1, 1) [000666] ------------ t666 = LCL_VAR byref V81 tmp51 u:2 Zero Fseq[_bits] $40e N007 ( 3, 2) [000668] -------N---- t668 = LCL_VAR ref V64 tmp34 u:2 (last use) $184 /--* t666 byref +--* t668 ref [000942] -A---------- * STOREIND ref N010 ( 1, 1) [000671] ------------ t671 = LCL_VAR byref V81 tmp51 u:2 (last use) $40e /--* t671 byref N012 ( 2, 2) [000673] -c---------- t673 = * LEA(b+8) byref N014 ( 3, 2) [000675] -------N---- t675 = LCL_VAR int V65 tmp35 u:2 (last use) $246 /--* t673 byref +--* t675 int [000943] -A--------L- * STOREIND int N018 ( 3, 2) [000678] -------N---- t678 = LCL_VAR_ADDR byref V76 tmp46 /--* t678 byref [001050] ------------ t1050 = * PUTARG_REG byref REG rcx N020 ( 3, 3) [000462] ------------ t462 = LCL_VAR_ADDR long V45 tmp15 $449 /--* t462 long [001051] ------------ t1051 = * PUTARG_REG long REG rdx /--* t1050 byref arg0 in rcx +--* t1051 long arg1 in rdx N021 ( 41, 28) [000463] --CXG------- t463 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $29f /--* t463 int N023 ( 45, 31) [000468] DA-XG------- * STORE_LCL_VAR int V43 tmp13 d:2 [000944] ------------ IL_OFFSET void IL offset: 0xff N001 ( 1, 1) [000473] ------------ t473 = CNS_INT ref null $VN.Null /--* t473 ref N003 ( 5, 4) [000475] DA--G------- * STORE_LCL_VAR ref (AX) V45 tmp15 N001 ( 3, 2) [000469] ------------ t469 = LCL_VAR int V43 tmp13 u:2 (last use) $29f /--* t469 int N003 ( 7, 5) [000148] DA---------- * STORE_LCL_VAR int V17 loc14 d:2 [000945] ------------ IL_OFFSET void IL offset: 0x108 N001 ( 3, 2) [000682] -------N---- t682 = LCL_VAR ref (AX) V58 tmp28 $185 /--* t682 ref N003 ( 7, 5) [000683] DA--G------- * STORE_LCL_VAR ref V66 tmp36 d:2 N004 ( 3, 2) [000685] -------N---- t685 = LCL_VAR int (AX) V59 tmp29 $247 /--* t685 int N006 ( 7, 5) [000686] DA--G------- * STORE_LCL_VAR int V67 tmp37 d:2 [000946] ------------ IL_OFFSET void IL offset: 0x108 N001 ( 3, 2) [000692] -------N---- t692 = LCL_VAR_ADDR byref V76 tmp46 /--* t692 byref N004 ( 3, 3) [000694] DA---------- * STORE_LCL_VAR byref V82 tmp52 d:2 N005 ( 1, 1) [000695] ------------ t695 = LCL_VAR byref V82 tmp52 u:2 Zero Fseq[_bits] $411 N007 ( 3, 2) [000697] -------N---- t697 = LCL_VAR ref V66 tmp36 u:2 (last use) $185 /--* t695 byref +--* t697 ref [000947] -A---------- * STOREIND ref N010 ( 1, 1) [000700] ------------ t700 = LCL_VAR byref V82 tmp52 u:2 (last use) $411 /--* t700 byref N012 ( 2, 2) [000702] -c---------- t702 = * LEA(b+8) byref N014 ( 3, 2) [000704] -------N---- t704 = LCL_VAR int V67 tmp37 u:2 (last use) $247 /--* t702 byref +--* t704 int [000948] -A--------L- * STOREIND int N018 ( 3, 2) [000707] -------N---- t707 = LCL_VAR_ADDR byref V76 tmp46 /--* t707 byref [001052] ------------ t1052 = * PUTARG_REG byref REG rcx N020 ( 3, 3) [000480] ------------ t480 = LCL_VAR_ADDR long V48 tmp18 $44b /--* t480 long [001053] ------------ t1053 = * PUTARG_REG long REG rdx /--* t1052 byref arg0 in rcx +--* t1053 long arg1 in rdx N021 ( 41, 28) [000481] --CXG------- t481 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $2a3 /--* t481 int N023 ( 45, 31) [000486] DA-XG------- * STORE_LCL_VAR int V46 tmp16 d:2 [000949] ------------ IL_OFFSET void IL offset: 0x108 N001 ( 1, 1) [000491] ------------ t491 = CNS_INT ref null $VN.Null /--* t491 ref N003 ( 5, 4) [000493] DA--G------- * STORE_LCL_VAR ref (AX) V48 tmp18 N001 ( 3, 2) [000487] ------------ t487 = LCL_VAR int V46 tmp16 u:2 (last use) $2a3 /--* t487 int N003 ( 7, 5) [000155] DA---------- * STORE_LCL_VAR int V18 loc15 d:2 [000950] ------------ IL_OFFSET void IL offset: 0x111 N001 ( 3, 2) [000156] ------------ t156 = LCL_VAR int V18 loc15 u:2 $2a3 N002 ( 3, 2) [000157] ------------ t157 = LCL_VAR int V17 loc14 u:2 $29f /--* t156 int +--* t157 int N003 ( 7, 5) [000158] N------N-U-- * GT void $35f N004 ( 9, 7) [000159] ------------ * JTRUE void ------------ BB24 [117..11A) -> BB26 (always), preds={BB23} succs={BB26} [000951] ------------ IL_OFFSET void IL offset: 0x117 N001 ( 1, 1) [000348] ------------ t348 = CNS_INT int 0 $40 /--* t348 int N003 ( 5, 4) [000350] DA---------- * STORE_LCL_VAR int V33 tmp3 d:4 ------------ BB25 [11A..11F), preds={BB23} succs={BB26} [000952] ------------ IL_OFFSET void IL offset: 0x11a N001 ( 3, 2) [000160] ------------ t160 = LCL_VAR int V18 loc15 u:2 (last use) $2a3 N002 ( 3, 2) [000161] ------------ t161 = LCL_VAR int V17 loc14 u:2 (last use) $29f /--* t160 int +--* t161 int N003 ( 7, 5) [000162] ------------ t162 = * SUB int $360 /--* t162 int N005 ( 11, 8) [000164] DA---------- * STORE_LCL_VAR int V33 tmp3 d:3 ------------ BB26 [11F..126) -> BB28 (cond), preds={BB24,BB25} succs={BB27,BB28} N001 ( 0, 0) [000903] ------------ t903 = PHI_ARG int V33 tmp3 u:4 $40 N002 ( 0, 0) [000902] ------------ t902 = PHI_ARG int V33 tmp3 u:3 $360 /--* t903 int +--* t902 int N003 ( 0, 0) [000876] ------------ t876 = * PHI int /--* t876 int N005 ( 0, 0) [000877] DA---------- * STORE_LCL_VAR int V33 tmp3 d:2 N001 ( 3, 2) [000166] ------------ t166 = LCL_VAR int V33 tmp3 u:2 (last use) $248 /--* t166 int N003 ( 3, 3) [000168] DA---------- * STORE_LCL_VAR int V19 loc16 d:2 [000953] ------------ IL_OFFSET void IL offset: 0x121 N001 ( 3, 2) [000169] ------------ t169 = LCL_VAR int V19 loc16 u:2 $248 N002 ( 1, 1) [000170] -c---------- t170 = CNS_INT int 0 $40 /--* t169 int +--* t170 int N003 ( 5, 4) [000171] N------N---- * EQ void $361 N004 ( 7, 6) [000172] ------------ * JTRUE void ------------ BB27 [126..12F), preds={BB26} succs={BB28} [000954] ------------ IL_OFFSET void IL offset: 0x126 N003 ( 3, 2) [000344] -------N---- t344 = LCL_VAR_ADDR byref V15 loc12 * ref V15._bits (offs=0x00) -> V56 tmp26 * int V15._sign (offs=0x08) -> V57 tmp27 /--* t344 byref [001054] ------------ t1054 = * PUTARG_REG byref REG rcx N005 ( 1, 1) [000346] ------------ t346 = LCL_VAR int V19 loc16 u:2 $248 /--* t346 int [001055] ------------ t1055 = * PUTARG_REG int REG rdx /--* t1054 byref arg0 in rcx +--* t1055 int arg1 in rdx N006 ( 18, 11) [000347] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft $VN.Void ------------ BB28 [12F..13E) -> BB32 (cond), preds={BB26,BB27} succs={BB29,BB32} [000955] ------------ IL_OFFSET void IL offset: 0x12f N001 ( 3, 2) [000173] ------------ t173 = LCL_VAR int V03 loc0 u:2 (last use) $348 N002 ( 1, 1) [000174] ------------ t174 = LCL_VAR int V13 loc10 u:2 $293 /--* t173 int +--* t174 int N003 ( 5, 4) [000175] ------------ t175 = * SUB int $362 /--* t175 int N005 ( 9, 7) [000177] DA---------- * STORE_LCL_VAR int V20 loc17 d:2 [000956] ------------ IL_OFFSET void IL offset: 0x135 N001 ( 3, 2) [000178] ------------ t178 = LCL_VAR int V20 loc17 u:2 $362 /--* t178 int N003 ( 7, 5) [000180] DA---------- * STORE_LCL_VAR int V21 loc18 d:2 [000957] ------------ IL_OFFSET void IL offset: 0x139 N001 ( 1, 1) [000181] ------------ t181 = LCL_VAR int V13 loc10 u:2 $293 N002 ( 1, 1) [000182] -c---------- t182 = CNS_INT int 0 $40 /--* t181 int +--* t182 int N003 ( 3, 3) [000183] N------N---- * EQ void $363 N004 ( 5, 5) [000184] ------------ * JTRUE void ------------ BB29 [13E..144) -> BB31 (cond), preds={BB28} succs={BB30,BB31} [000958] ------------ IL_OFFSET void IL offset: 0x13e N001 ( 1, 1) [000326] ------------ t326 = LCL_VAR int V19 loc16 u:2 $248 N002 ( 3, 2) [000327] ------------ t327 = LCL_VAR int V20 loc17 u:2 $362 /--* t326 int +--* t327 int N003 ( 5, 4) [000328] N------N-U-- * LE void $364 N004 ( 7, 6) [000329] ------------ * JTRUE void ------------ BB30 [144..155) -> BB44 (always), preds={BB29} succs={BB44} [000959] ------------ IL_OFFSET void IL offset: 0x144 N005 ( 1, 1) [000341] ------------ t341 = LCL_VAR byref V02 arg2 u:1 (last use) $81 /--* t341 byref [001056] ------------ * PUTARG_STK [+0x20] void N006 ( 1, 1) [000339] ------------ t339 = CNS_INT int 1 $41 /--* t339 int [001057] ------------ t1057 = * PUTARG_REG int REG r8 N007 ( 3, 2) [000335] ------------ t335 = LCL_VAR ref (AX) V12 loc9 $18c /--* t335 ref [001058] ------------ t1058 = * PUTARG_REG ref REG rcx N008 ( 1, 1) [000336] ------------ t336 = LCL_VAR int V13 loc10 u:2 (last use) $293 /--* t336 int [001059] ------------ t1059 = * PUTARG_REG int REG rdx N009 ( 1, 1) [000340] ------------ t340 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t340 ref [001060] ------------ t1060 = * PUTARG_REG ref REG r9 /--* t1057 int arg2 in r8 +--* t1058 ref arg0 in rcx +--* t1059 int arg1 in rdx +--* t1060 ref arg3 in r9 N010 ( 24, 15) [000342] --CXG------- t342 = * CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits $5c2 /--* t342 int N012 ( 24, 15) [000717] DA-XG------- * STORE_LCL_VAR int V51 tmp21 d:5 ------------ BB31 [155..15C), preds={BB29} succs={BB32} [000960] ------------ IL_OFFSET void IL offset: 0x155 N001 ( 3, 2) [000330] ------------ t330 = LCL_VAR int V20 loc17 u:2 $362 N002 ( 1, 1) [000331] ------------ t331 = LCL_VAR int V19 loc16 u:2 $248 /--* t330 int +--* t331 int N003 ( 5, 4) [000332] ------------ t332 = * SUB int $365 /--* t332 int N005 ( 9, 7) [000334] DA---------- * STORE_LCL_VAR int V21 loc18 d:4 ------------ BB32 [15C..167) -> BB34 (cond), preds={BB28,BB31} succs={BB33,BB34} N001 ( 0, 0) [000900] ------------ t900 = PHI_ARG int V21 loc18 u:4 $365 N002 ( 0, 0) [000888] ------------ t888 = PHI_ARG int V21 loc18 u:2 $362 /--* t900 int +--* t888 int N003 ( 0, 0) [000873] ------------ t873 = * PHI int /--* t873 int N005 ( 0, 0) [000874] DA---------- * STORE_LCL_VAR int V21 loc18 d:3 [000961] ------------ IL_OFFSET void IL offset: 0x15c N001 ( 3, 2) [000719] -------N---- t719 = LCL_VAR ref (AX) V56 tmp26 $186 /--* t719 ref N003 ( 7, 5) [000720] DA--G------- * STORE_LCL_VAR ref (AX) V68 tmp38 N004 ( 3, 2) [000722] -------N---- t722 = LCL_VAR int (AX) V57 tmp27 $24a /--* t722 int N006 ( 7, 5) [000723] DA--G------- * STORE_LCL_VAR int (AX) V69 tmp39 [000962] ------------ IL_OFFSET void IL offset: 0x15c N001 ( 3, 2) [000726] -------N---- t726 = LCL_VAR ref (AX) V58 tmp28 $187 /--* t726 ref N003 ( 7, 5) [000727] DA--G------- * STORE_LCL_VAR ref V70 tmp40 d:2 N004 ( 3, 2) [000729] -------N---- t729 = LCL_VAR int (AX) V59 tmp29 $24b /--* t729 int N006 ( 7, 5) [000730] DA--G------- * STORE_LCL_VAR int V71 tmp41 d:2 N001 ( 3, 2) [000496] -------N---- t496 = LCL_VAR_ADDR byref V49 tmp19 * ref V49._bits (offs=0x00) -> V68 tmp38 * int V49._sign (offs=0x08) -> V69 tmp39 /--* t496 byref N004 ( 7, 6) [000752] DA--------L- * STORE_LCL_VAR byref V84 tmp54 d:2 N005 ( 3, 2) [000736] -------N---- t736 = LCL_VAR_ADDR byref V76 tmp46 /--* t736 byref N008 ( 3, 3) [000738] DA---------- * STORE_LCL_VAR byref V83 tmp53 d:2 N009 ( 1, 1) [000739] ------------ t739 = LCL_VAR byref V83 tmp53 u:2 Zero Fseq[_bits] $417 N011 ( 3, 2) [000741] -------N---- t741 = LCL_VAR ref V70 tmp40 u:2 (last use) $187 /--* t739 byref +--* t741 ref [000963] -A---------- * STOREIND ref N014 ( 1, 1) [000744] ------------ t744 = LCL_VAR byref V83 tmp53 u:2 (last use) $417 /--* t744 byref N016 ( 2, 2) [000746] -c---------- t746 = * LEA(b+8) byref N018 ( 3, 2) [000748] -------N---- t748 = LCL_VAR int V71 tmp41 u:2 (last use) $24b /--* t746 byref +--* t748 int [000964] -A--------L- * STOREIND int N021 ( 3, 2) [000753] ------------ t753 = LCL_VAR byref V84 tmp54 u:2 (last use) $415 /--* t753 byref [001061] ------------ t1061 = * PUTARG_REG byref REG rcx N022 ( 3, 2) [000754] -------N---- t754 = LCL_VAR_ADDR byref V76 tmp46 /--* t754 byref [001062] ------------ t1062 = * PUTARG_REG byref REG rdx /--* t1061 byref this in rcx +--* t1062 byref arg1 in rdx N024 ( 48, 34) [000499] --CXG------- t499 = * CALL int System.Numerics.BigInteger.CompareTo $2ae N025 ( 1, 1) [000502] -c---------- t502 = CNS_INT int 0 $40 /--* t499 int +--* t502 int N026 ( 50, 36) [000503] J--XG--N---- * LT void $367 N027 ( 52, 38) [000195] ---XG------- * JTRUE void ------------ BB33 [167..16B) -> BB35 (always), preds={BB32} succs={BB35} [000965] ------------ IL_OFFSET void IL offset: 0x167 N001 ( 1, 1) [000322] ------------ t322 = LCL_VAR int V19 loc16 u:2 (last use) $248 /--* t322 int N003 ( 5, 4) [000324] DA---------- * STORE_LCL_VAR int V34 tmp4 d:4 ------------ BB34 [16B..16F), preds={BB32} succs={BB35} [000966] ------------ IL_OFFSET void IL offset: 0x16b N001 ( 1, 1) [000196] ------------ t196 = LCL_VAR int V19 loc16 u:2 (last use) $248 N002 ( 1, 1) [000197] -c---------- t197 = CNS_INT int 1 $41 /--* t196 int +--* t197 int N003 ( 3, 3) [000198] ------------ t198 = * ADD int $368 /--* t198 int N005 ( 7, 6) [000200] DA---------- * STORE_LCL_VAR int V34 tmp4 d:3 ------------ BB35 [16F..1A4) -> BB40 (cond), preds={BB33,BB34} succs={BB36,BB40} N001 ( 0, 0) [000899] ------------ t899 = PHI_ARG int V34 tmp4 u:4 $248 N002 ( 0, 0) [000898] ------------ t898 = PHI_ARG int V34 tmp4 u:3 $368 /--* t899 int +--* t898 int N003 ( 0, 0) [000870] ------------ t870 = * PHI int /--* t870 int N005 ( 0, 0) [000871] DA---------- * STORE_LCL_VAR int V34 tmp4 d:2 N001 ( 3, 2) [000202] ------------ t202 = LCL_VAR int V34 tmp4 u:2 (last use) $24c /--* t202 int N003 ( 7, 5) [000204] DA---------- * STORE_LCL_VAR int V22 loc19 d:2 [000967] ------------ IL_OFFSET void IL offset: 0x171 N003 ( 3, 2) [000205] -------N---- t205 = LCL_VAR_ADDR byref V15 loc12 * ref V15._bits (offs=0x00) -> V56 tmp26 * int V15._sign (offs=0x08) -> V57 tmp27 /--* t205 byref [001063] ------------ t1063 = * PUTARG_REG byref REG rcx N005 ( 3, 2) [000207] ------------ t207 = LCL_VAR int V21 loc18 u:3 (last use) $249 /--* t207 int [001064] ------------ t1064 = * PUTARG_REG int REG rdx /--* t1063 byref arg0 in rcx +--* t1064 int arg1 in rdx N006 ( 20, 12) [000208] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft $VN.Void [000968] ------------ IL_OFFSET void IL offset: 0x17a N001 ( 3, 2) [000219] -------N---- t219 = LCL_VAR_ADDR byref V35 tmp5 * ref V35._bits (offs=0x00) -> V62 tmp32 * int V35._sign (offs=0x08) -> V63 tmp33 /--* t219 byref N004 ( 7, 6) [000797] DA--------L- * STORE_LCL_VAR long V88 tmp58 d:2 N005 ( 3, 2) [000762] -------N---- t762 = LCL_VAR_ADDR byref V76 tmp46 /--* t762 byref N008 ( 3, 3) [000764] DA---------- * STORE_LCL_VAR byref V85 tmp55 d:2 N009 ( 1, 1) [000765] ------------ t765 = LCL_VAR byref V85 tmp55 u:2 Zero Fseq[_bits] $41c N011 ( 3, 2) [000767] -------N---- t767 = LCL_VAR ref (AX) V56 tmp26 $188 /--* t765 byref +--* t767 ref [000969] -A--G------- * STOREIND ref N014 ( 1, 1) [000770] ------------ t770 = LCL_VAR byref V85 tmp55 u:2 (last use) $41c /--* t770 byref N016 ( 2, 2) [000772] -c---------- t772 = * LEA(b+8) byref N018 ( 3, 2) [000774] -------N---- t774 = LCL_VAR int (AX) V57 tmp27 $24d /--* t772 byref +--* t774 int [000970] -A--G-----L- * STOREIND int N021 ( 3, 2) [000781] -------N---- t781 = LCL_VAR_ADDR byref V86 tmp56 /--* t781 byref N024 ( 3, 3) [000783] DA---------- * STORE_LCL_VAR byref V87 tmp57 d:2 N025 ( 1, 1) [000784] ------------ t784 = LCL_VAR byref V87 tmp57 u:2 Zero Fseq[_bits] $41e N027 ( 3, 2) [000786] -------N---- t786 = LCL_VAR ref (AX) V58 tmp28 $189 /--* t784 byref +--* t786 ref [000971] -A--G------- * STOREIND ref N030 ( 1, 1) [000789] ------------ t789 = LCL_VAR byref V87 tmp57 u:2 (last use) $41e /--* t789 byref N032 ( 2, 2) [000791] -c---------- t791 = * LEA(b+8) byref N034 ( 3, 2) [000793] -------N---- t793 = LCL_VAR int (AX) V59 tmp29 $24e /--* t791 byref +--* t793 int [000972] -A--G-----L- * STOREIND int N038 ( 3, 2) [000798] ------------ t798 = LCL_VAR long V88 tmp58 u:2 (last use) $41b /--* t798 long [001065] ------------ t1065 = * PUTARG_REG long REG rcx N039 ( 3, 2) [000799] -------N---- t799 = LCL_VAR_ADDR byref V76 tmp46 /--* t799 byref [001066] ------------ t1066 = * PUTARG_REG byref REG rdx N041 ( 3, 2) [000801] -------N---- t801 = LCL_VAR_ADDR byref V86 tmp56 /--* t801 byref [001067] ------------ t1067 = * PUTARG_REG byref REG r8 N043 ( 3, 2) [000211] -------N---- t211 = LCL_VAR_ADDR byref V23 loc20 * ref V23._bits (offs=0x00) -> V60 tmp30 * int V23._sign (offs=0x08) -> V61 tmp31 /--* t211 byref [001068] ------------ t1068 = * PUTARG_REG byref REG r9 /--* t1065 long arg0 in rcx +--* t1066 byref arg1 in rdx +--* t1067 byref arg2 in r8 +--* t1068 byref arg3 in r9 N045 ( 78, 56) [000213] S-CXG------- * CALL void System.Numerics.BigInteger.DivRem $VN.Void N001 ( 3, 2) [000808] -------N---- t808 = LCL_VAR_ADDR byref V76 tmp46 /--* t808 byref N004 ( 3, 3) [000810] DA---------- * STORE_LCL_VAR byref V89 tmp59 d:2 N005 ( 1, 1) [000811] ------------ t811 = LCL_VAR byref V89 tmp59 u:2 Zero Fseq[_bits] $423 N007 ( 3, 2) [000813] -------N---- t813 = LCL_VAR ref (AX) V62 tmp32 $18a /--* t811 byref +--* t813 ref [000973] -A--G------- * STOREIND ref N010 ( 1, 1) [000816] ------------ t816 = LCL_VAR byref V89 tmp59 u:2 (last use) $423 /--* t816 byref N012 ( 2, 2) [000818] -c---------- t818 = * LEA(b+8) byref N014 ( 3, 2) [000820] -------N---- t820 = LCL_VAR int (AX) V63 tmp33 $24f /--* t818 byref +--* t820 int [000974] -A--G-----L- * STOREIND int N017 ( 3, 2) [000823] -------N---- t823 = LCL_VAR_ADDR byref V76 tmp46 /--* t823 byref [001069] ------------ t1069 = * PUTARG_REG byref REG rcx /--* t1069 byref arg0 in rcx N019 ( 38, 24) [000218] --CXG------- t218 = * CALL long System.Numerics.BigInteger.op_Explicit $450 /--* t218 long N021 ( 38, 24) [000226] DA-XG------- * STORE_LCL_VAR long V24 loc21 d:2 N001 ( 3, 2) [000514] -c---------- t514 = LCL_VAR int (AX) V61 tmp31 $250 N002 ( 1, 1) [000515] -c---------- t515 = CNS_INT int 0 $40 /--* t514 int +--* t515 int N003 ( 8, 4) [000516] ----G------- t516 = * EQ int $369 /--* t516 int N005 ( 12, 7) [000232] DA--G------- * STORE_LCL_VAR int V25 loc22 d:2 N002 ( 1, 1) [000233] ------------ t233 = LCL_VAR long V24 loc21 u:2 $450 /--* t233 long [001070] ------------ t1070 = * PUTARG_REG long REG rcx /--* t1070 long arg0 in rcx N003 ( 15, 7) [000234] --CXG------- t234 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits $2b4 /--* t234 int N005 ( 19, 10) [000237] DA-XG------- * STORE_LCL_VAR int V26 loc23 d:2 [000975] ------------ IL_OFFSET void IL offset: 0x19e N001 ( 3, 2) [000238] ------------ t238 = LCL_VAR int V26 loc23 u:2 $2b4 N002 ( 3, 2) [000239] ------------ t239 = LCL_VAR int V20 loc17 u:2 $362 /--* t238 int +--* t239 int N003 ( 7, 5) [000240] N------N-U-- * LE void $36a N004 ( 9, 7) [000241] ------------ * JTRUE void ------------ BB36 [1A4..1AF) -> BB38 (cond), preds={BB35} succs={BB37,BB38} [000976] ------------ IL_OFFSET void IL offset: 0x1a4 N001 ( 3, 2) [000282] ------------ t282 = LCL_VAR int V26 loc23 u:2 (last use) $2b4 N002 ( 3, 2) [000283] ------------ t283 = LCL_VAR int V20 loc17 u:2 $362 /--* t282 int +--* t283 int N003 ( 7, 5) [000284] ------------ t284 = * SUB int $36b /--* t284 int N005 ( 11, 8) [000286] DA---------- * STORE_LCL_VAR int V29 loc26 d:2 [000977] ------------ IL_OFFSET void IL offset: 0x1ab N001 ( 3, 2) [000287] ------------ t287 = LCL_VAR int V25 loc22 u:2 (last use) $369 N002 ( 1, 1) [000288] -c---------- t288 = CNS_INT int 0 $40 /--* t287 int +--* t288 int N003 ( 5, 4) [000289] J------N---- * EQ void $36c N004 ( 7, 6) [000290] ------------ * JTRUE void ------------ BB37 [1AF..1C3) -> BB39 (always), preds={BB36} succs={BB39} [000978] ------------ IL_OFFSET void IL offset: 0x1af N001 ( 1, 1) [000305] ------------ t305 = LCL_VAR long V24 loc21 u:2 $450 N002 ( 3, 2) [000308] ------------ t308 = LCL_VAR int V29 loc26 u:2 $36b N005 ( 1, 1) [000307] ------------ t307 = CNS_INT long 1 $103 /--* t307 long +--* t308 int N006 ( 10, 6) [000311] ------------ t311 = * LSH long $48e N007 ( 1, 1) [000313] -c---------- t313 = CNS_INT long -1 $104 /--* t311 long +--* t313 long N008 ( 12, 8) [000314] ------------ t314 = * ADD long $48f /--* t305 long +--* t314 long N011 ( 19, 12) [000318] ------------ t318 = * TEST_EQ int $36e /--* t318 int N013 ( 23, 15) [000320] DA---------- * STORE_LCL_VAR int V37 tmp7 d:4 ------------ BB38 [1C3..1C4), preds={BB36} succs={BB39} [000979] ------------ IL_OFFSET void IL offset: 0x1c3 N001 ( 1, 1) [000291] ------------ t291 = CNS_INT int 0 $40 /--* t291 int N003 ( 5, 4) [000293] DA---------- * STORE_LCL_VAR int V37 tmp7 d:3 ------------ BB39 [1C4..1D0), preds={BB37,BB38} succs={BB40} N001 ( 0, 0) [000897] ------------ t897 = PHI_ARG int V37 tmp7 u:4 $36e N002 ( 0, 0) [000896] ------------ t896 = PHI_ARG int V37 tmp7 u:3 $40 /--* t897 int +--* t896 int N003 ( 0, 0) [000867] ------------ t867 = * PHI int /--* t867 int N005 ( 0, 0) [000868] DA---------- * STORE_LCL_VAR int V37 tmp7 d:2 N001 ( 3, 2) [000295] ------------ t295 = LCL_VAR int V37 tmp7 u:2 (last use) $251 /--* t295 int N002 ( 4, 4) [000826] ------------ t826 = * CAST int <- bool <- int $36f /--* t826 int N004 ( 8, 7) [000297] DA---------- * STORE_LCL_VAR int V25 loc22 d:4 [000980] ------------ IL_OFFSET void IL offset: 0x1c6 N001 ( 1, 1) [000298] ------------ t298 = LCL_VAR long V24 loc21 u:2 (last use) $450 N002 ( 3, 2) [000299] ------------ t299 = LCL_VAR int V29 loc26 u:2 (last use) $36b /--* t298 long +--* t299 int N005 ( 10, 6) [000302] ------------ t302 = * RSZ long $491 /--* t302 long N007 ( 10, 6) [000304] DA---------- * STORE_LCL_VAR long V24 loc21 d:4 ------------ BB40 [1D0..1E7) -> BB42 (cond), preds={BB35,BB39} succs={BB41,BB42} N001 ( 0, 0) [000894] ------------ t894 = PHI_ARG bool V25 loc22 u:4 $36f N002 ( 0, 0) [000889] ------------ t889 = PHI_ARG bool V25 loc22 u:2 $369 /--* t894 bool +--* t889 bool N003 ( 0, 0) [000864] ------------ t864 = * PHI bool /--* t864 bool N005 ( 0, 0) [000865] DA---------- * STORE_LCL_VAR bool V25 loc22 d:3 N001 ( 0, 0) [000895] ------------ t895 = PHI_ARG long V24 loc21 u:4 $491 N002 ( 0, 0) [000890] ------------ t890 = PHI_ARG long V24 loc21 u:2 $450 /--* t895 long +--* t890 long N003 ( 0, 0) [000861] ------------ t861 = * PHI long /--* t861 long N005 ( 0, 0) [000862] DA---------- * STORE_LCL_VAR long V24 loc21 d:3 N001 ( 3, 2) [000831] -------N---- t831 = LCL_VAR_ADDR byref V76 tmp46 /--* t831 byref N004 ( 3, 3) [000833] DA---------- * STORE_LCL_VAR byref V90 tmp60 d:2 N005 ( 1, 1) [000834] ------------ t834 = LCL_VAR byref V90 tmp60 u:2 Zero Fseq[_bits] $426 N007 ( 3, 2) [000836] -------N---- t836 = LCL_VAR ref (AX) V54 tmp24 $18b /--* t834 byref +--* t836 ref [000981] -A--G------- * STOREIND ref N010 ( 1, 1) [000839] ------------ t839 = LCL_VAR byref V90 tmp60 u:2 (last use) $426 /--* t839 byref N012 ( 2, 2) [000841] -c---------- t841 = * LEA(b+8) byref N014 ( 3, 2) [000843] -------N---- t843 = LCL_VAR int (AX) V55 tmp25 $252 /--* t841 byref +--* t843 int [000982] -A--G-----L- * STOREIND int N017 ( 3, 2) [000846] -------N---- t846 = LCL_VAR_ADDR byref V76 tmp46 /--* t846 byref [001071] ------------ t1071 = * PUTARG_REG byref REG rcx /--* t1071 byref arg0 in rcx N019 ( 38, 24) [000243] --CXG------- t243 = * CALL long System.Numerics.BigInteger.op_Explicit $454 N020 ( 3, 2) [000247] ------------ t247 = LCL_VAR int V20 loc17 u:2 (last use) $362 /--* t243 long +--* t247 int N023 ( 47, 29) [000250] ---XG------- t250 = * LSH long $492 N024 ( 1, 1) [000251] ------------ t251 = LCL_VAR long V24 loc21 u:3 (last use) $580 /--* t250 long +--* t251 long N025 ( 49, 31) [000252] ---XG------- t252 = * ADD long $493 /--* t252 long N027 ( 53, 34) [000254] DA-XG------- * STORE_LCL_VAR long V27 loc24 d:2 [000983] ------------ IL_OFFSET void IL offset: 0x1e2 N001 ( 1, 1) [000255] ------------ t255 = LCL_VAR int V13 loc10 u:2 $293 N002 ( 1, 1) [000256] -c---------- t256 = CNS_INT int 0 $40 /--* t255 int +--* t256 int N003 ( 3, 3) [000257] N------N---- * NE void $35a N004 ( 5, 5) [000258] ------------ * JTRUE void ------------ BB41 [1E7..1EE) -> BB43 (always), preds={BB40} succs={BB43} [000984] ------------ IL_OFFSET void IL offset: 0x1e7 N001 ( 3, 2) [000275] ------------ t275 = LCL_VAR int V22 loc19 u:2 (last use) $24c /--* t275 int N002 ( 4, 3) [000276] ------------ t276 = * NEG int $2c2 N003 ( 1, 1) [000277] -c---------- t277 = CNS_INT int -1 $43 /--* t276 int +--* t277 int N004 ( 6, 5) [000278] ------------ t278 = * ADD int $372 /--* t278 int N006 ( 10, 8) [000280] DA---------- * STORE_LCL_VAR int V36 tmp6 d:4 ------------ BB42 [1EE..1F2), preds={BB40} succs={BB43} [000985] ------------ IL_OFFSET void IL offset: 0x1ee N001 ( 1, 1) [000259] ------------ t259 = LCL_VAR int V13 loc10 u:2 (last use) $293 N002 ( 1, 1) [000260] -c---------- t260 = CNS_INT int -2 $68 /--* t259 int +--* t260 int N003 ( 3, 3) [000261] ------------ t261 = * ADD int $371 /--* t261 int N005 ( 7, 6) [000263] DA---------- * STORE_LCL_VAR int V36 tmp6 d:3 ------------ BB43 [1F2..202), preds={BB41,BB42} succs={BB44} N001 ( 0, 0) [000893] ------------ t893 = PHI_ARG int V36 tmp6 u:4 $372 N002 ( 0, 0) [000892] ------------ t892 = PHI_ARG int V36 tmp6 u:3 $371 /--* t893 int +--* t892 int N003 ( 0, 0) [000858] ------------ t858 = * PHI int /--* t858 int N005 ( 0, 0) [000859] DA---------- * STORE_LCL_VAR int V36 tmp6 d:2 [000986] ------------ IL_OFFSET void IL offset: 0x1f4 N005 ( 1, 1) [000272] ------------ t272 = LCL_VAR byref V02 arg2 u:1 (last use) $81 /--* t272 byref [001072] ------------ * PUTARG_STK [+0x20] void N006 ( 1, 1) [000268] ------------ t268 = LCL_VAR ref V01 arg1 u:1 (last use) $c0 /--* t268 ref [001073] ------------ t1073 = * PUTARG_REG ref REG rcx N007 ( 3, 2) [000269] ------------ t269 = LCL_VAR long V27 loc24 u:2 (last use) $493 /--* t269 long [001074] ------------ t1074 = * PUTARG_REG long REG rdx N008 ( 3, 2) [000270] ------------ t270 = LCL_VAR int V36 tmp6 u:2 (last use) $253 /--* t270 int [001075] ------------ t1075 = * PUTARG_REG int REG r8 N009 ( 3, 2) [000271] ------------ t271 = LCL_VAR int V25 loc22 u:3 (last use) $540 /--* t271 int [001076] ------------ t1076 = * PUTARG_REG int REG r9 /--* t1073 ref this in rcx +--* t1074 long arg1 in rdx +--* t1075 int arg2 in r8 +--* t1076 int arg3 in r9 N010 ( 28, 18) [000273] --CXG------- t273 = * CALL int FloatingPointType.AssembleFloatingPointValue $2be /--* t273 int N012 ( 28, 18) [000853] DA-XG------- * STORE_LCL_VAR int V51 tmp21 d:4 ------------ BB44 [???..???) (return), preds={BB16,BB30,BB43} succs={} N001 ( 0, 0) [000901] ------------ t901 = PHI_ARG int V51 tmp21 u:5 $5c2 N002 ( 0, 0) [000891] ------------ t891 = PHI_ARG int V51 tmp21 u:4 $2be N003 ( 0, 0) [000887] ------------ t887 = PHI_ARG int V51 tmp21 u:3 $5c7 /--* t901 int +--* t891 int +--* t887 int N004 ( 0, 0) [000855] ------------ t855 = * PHI int /--* t855 int N006 ( 0, 0) [000856] DA---------- * STORE_LCL_VAR int V51 tmp21 d:2 N001 ( 1, 1) [000522] -------N---- t522 = LCL_VAR int V51 tmp21 u:2 (last use) $254 /--* t522 int N002 ( 2, 2) [000523] ------------ * RETURN int $5c9 ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Calculate stack level slots *************** Finishing PHASE Calculate stack level slots [no changes] *************** Starting PHASE Linear scan register alloc Clearing modified regs. buildIntervals ======== ----------------- LIVENESS: ----------------- BB01 use def in out {V00} {V52 V53} {V00 V01 V02} {V01 V02 V52 V53} BB02 use def in out {V52} {} {V01 V02 V52 V53} {V01 V02 V52 V53} BB03 use def in out {V01 V02} {} {V01 V02} {} BB04 use def in out {V01 V53} {V03 V40} {V01 V02 V52 V53} {V01 V02 V03 V52 V53} BB05 use def in out {V53} {V39} {V01 V02 V03 V52 V53} {V01 V02 V03 V39 V52 V53} BB06 use def in out {} {V39} {V01 V02 V03 V52 V53} {V01 V02 V03 V39 V52 V53} BB07 use def in out {V39 V52} {V31 V42} {V01 V02 V03 V39 V52 V53} {V01 V02 V03 V31 V42 V52 V53} BB08 use def in out {V42} {V41} {V01 V02 V03 V31 V42 V52 V53} {V01 V02 V03 V31 V41 V52 V53} BB09 use def in out {V31} {V41} {V01 V02 V03 V31 V52 V53} {V01 V02 V03 V31 V41 V52 V53} BB10 use def in out {V31 V41 V52 V53} {V05 V08 V09 V10 V74 V75} {V01 V02 V03 V31 V41 V52 V53} {V01 V02 V03 V05 V08 V09 V10 V52 V53} BB11 use def in out {V01 V05} {} {V01 V02 V03 V05 V08 V09 V10 V52 V53} {V01 V02 V03 V05 V08 V09 V10 V52 V53} BB12 use def in out {V01 V02} {} {V01 V02} {} BB13 use def in out {V05} {} {V01 V02 V03 V05 V08 V09 V10 V52 V53} {V01 V02 V03 V08 V09 V10 V52 V53} BB14 use def in out {V03} {V13 V77} {V01 V02 V03 V08 V09 V10 V52 V53} {V01 V02 V03 V08 V09 V10 V13 V52 V53} BB15 use def in out {V10} {} {V01 V02 V03 V08 V09 V10 V13 V52 V53} {V01 V02 V03 V08 V09 V10 V13 V52 V53} BB16 use def in out {V01 V02 V10 V13} {V51} {V01 V02 V10 V13} {V51} BB17 use def in out {V53} {} {V01 V02 V03 V08 V09 V10 V13 V52 V53} {V01 V02 V03 V08 V09 V10 V13 V52 V53} BB18 use def in out {V10} {V32} {V01 V02 V03 V08 V09 V10 V13 V52 V53} {V01 V02 V03 V08 V09 V13 V32 V52 V53} BB19 use def in out {V10 V53} {V32} {V01 V02 V03 V08 V09 V10 V13 V52 V53} {V01 V02 V03 V08 V09 V13 V32 V52 V53} BB20 use def in out {V13 V32} {V14} {V01 V02 V03 V08 V09 V13 V32 V52 V53} {V01 V02 V03 V08 V09 V13 V14 V52 V53} BB21 use def in out {V01 V14 V52} {V38} {V01 V02 V03 V08 V09 V13 V14 V52 V53} {V01 V02 V03 V08 V09 V13 V14 V52 V53} BB22 use def in out {V01 V02} {} {V01 V02} {} BB23 use def in out {V08 V09 V14 V52 V53} {V17 V18 V43 V46 V64 V65 V66 V67 V78 V79 V80 V81 V82} {V01 V02 V03 V08 V09 V13 V14 V52 V53} {V01 V02 V03 V13 V17 V18} BB24 use def in out {} {V33} {V01 V02 V03 V13} {V01 V02 V03 V13 V33} BB25 use def in out {V17 V18} {V33} {V01 V02 V03 V13 V17 V18} {V01 V02 V03 V13 V33} BB26 use def in out {V33} {V19} {V01 V02 V03 V13 V33} {V01 V02 V03 V13 V19} BB27 use def in out {V19} {} {V01 V02 V03 V13 V19} {V01 V02 V03 V13 V19} BB28 use def in out {V03 V13} {V20 V21} {V01 V02 V03 V13 V19} {V01 V02 V13 V19 V20 V21} BB29 use def in out {V19 V20} {} {V01 V02 V13 V19 V20} {V01 V02 V13 V19 V20} BB30 use def in out {V01 V02 V13} {V51} {V01 V02 V13} {V51} BB31 use def in out {V19 V20} {V21} {V01 V02 V13 V19 V20} {V01 V02 V13 V19 V20 V21} BB32 use def in out {} {V70 V71 V83 V84} {V01 V02 V13 V19 V20 V21} {V01 V02 V13 V19 V20 V21} BB33 use def in out {V19} {V34} {V01 V02 V13 V19 V20 V21} {V01 V02 V13 V20 V21 V34} BB34 use def in out {V19} {V34} {V01 V02 V13 V19 V20 V21} {V01 V02 V13 V20 V21 V34} BB35 use def in out {V20 V21 V34} {V22 V24 V25 V26 V85 V87 V88 V89} {V01 V02 V13 V20 V21 V34} {V01 V02 V13 V20 V22 V24 V25 V26} BB36 use def in out {V20 V25 V26} {V29} {V01 V02 V13 V20 V22 V24 V25 V26} {V01 V02 V13 V20 V22 V24 V29} BB37 use def in out {V24 V29} {V37} {V01 V02 V13 V20 V22 V24 V29} {V01 V02 V13 V20 V22 V24 V29 V37} BB38 use def in out {} {V37} {V01 V02 V13 V20 V22 V24 V29} {V01 V02 V13 V20 V22 V24 V29 V37} BB39 use def in out {V24 V29 V37} {V24 V25} {V01 V02 V13 V20 V22 V24 V29 V37} {V01 V02 V13 V20 V22 V24 V25} BB40 use def in out {V13 V20 V24} {V27 V90} {V01 V02 V13 V20 V22 V24 V25} {V01 V02 V13 V22 V25 V27} BB41 use def in out {V22} {V36} {V01 V02 V22 V25 V27} {V01 V02 V25 V27 V36} BB42 use def in out {V13} {V36} {V01 V02 V13 V25 V27} {V01 V02 V25 V27 V36} BB43 use def in out {V01 V02 V25 V27 V36} {V51} {V01 V02 V25 V27 V36} {V51} BB44 use def in out {V51} {} {V51} {} Interval 0: byref RefPositions {} physReg:NA Preferences=[allInt] Interval 0: (V00) byref RefPositions {} physReg:NA Preferences=[allInt] Interval 1: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 1: (V01) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 2: byref RefPositions {} physReg:NA Preferences=[allInt] Interval 2: (V02) byref RefPositions {} physReg:NA Preferences=[allInt] Interval 3: int RefPositions {} physReg:NA Preferences=[allInt] Interval 3: (V03) int RefPositions {} physReg:NA Preferences=[allInt] Interval 4: int RefPositions {} physReg:NA Preferences=[allInt] Interval 4: (V05) int RefPositions {} physReg:NA Preferences=[allInt] Interval 5: int RefPositions {} physReg:NA Preferences=[allInt] Interval 5: (V08) int RefPositions {} physReg:NA Preferences=[allInt] Interval 6: int RefPositions {} physReg:NA Preferences=[allInt] Interval 6: (V09) int RefPositions {} physReg:NA Preferences=[allInt] Interval 7: int RefPositions {} physReg:NA Preferences=[allInt] Interval 7: (V10) int RefPositions {} physReg:NA Preferences=[allInt] Interval 8: int RefPositions {} physReg:NA Preferences=[allInt] Interval 8: (V13) int RefPositions {} physReg:NA Preferences=[allInt] Interval 9: int RefPositions {} physReg:NA Preferences=[allInt] Interval 9: (V14) int RefPositions {} physReg:NA Preferences=[allInt] Interval 10: int RefPositions {} physReg:NA Preferences=[allInt] Interval 10: (V17) int RefPositions {} physReg:NA Preferences=[allInt] Interval 11: int RefPositions {} physReg:NA Preferences=[allInt] Interval 11: (V18) int RefPositions {} physReg:NA Preferences=[allInt] Interval 12: int RefPositions {} physReg:NA Preferences=[allInt] Interval 12: (V19) int RefPositions {} physReg:NA Preferences=[allInt] Interval 13: int RefPositions {} physReg:NA Preferences=[allInt] Interval 13: (V20) int RefPositions {} physReg:NA Preferences=[allInt] Interval 14: int RefPositions {} physReg:NA Preferences=[allInt] Interval 14: (V21) int RefPositions {} physReg:NA Preferences=[allInt] Interval 15: int RefPositions {} physReg:NA Preferences=[allInt] Interval 15: (V22) int RefPositions {} physReg:NA Preferences=[allInt] Interval 16: long RefPositions {} physReg:NA Preferences=[allInt] Interval 16: (V24) long RefPositions {} physReg:NA Preferences=[allInt] Interval 17: int RefPositions {} physReg:NA Preferences=[allInt] Interval 17: (V25) int RefPositions {} physReg:NA Preferences=[allInt] Interval 18: int RefPositions {} physReg:NA Preferences=[allInt] Interval 18: (V26) int RefPositions {} physReg:NA Preferences=[allInt] Interval 19: long RefPositions {} physReg:NA Preferences=[allInt] Interval 19: (V27) long RefPositions {} physReg:NA Preferences=[allInt] Interval 20: int RefPositions {} physReg:NA Preferences=[allInt] Interval 20: (V29) int RefPositions {} physReg:NA Preferences=[allInt] Interval 21: int RefPositions {} physReg:NA Preferences=[allInt] Interval 21: (V31) int RefPositions {} physReg:NA Preferences=[allInt] Interval 22: int RefPositions {} physReg:NA Preferences=[allInt] Interval 22: (V32) int RefPositions {} physReg:NA Preferences=[allInt] Interval 23: int RefPositions {} physReg:NA Preferences=[allInt] Interval 23: (V33) int RefPositions {} physReg:NA Preferences=[allInt] Interval 24: int RefPositions {} physReg:NA Preferences=[allInt] Interval 24: (V34) int RefPositions {} physReg:NA Preferences=[allInt] Interval 25: int RefPositions {} physReg:NA Preferences=[allInt] Interval 25: (V36) int RefPositions {} physReg:NA Preferences=[allInt] Interval 26: int RefPositions {} physReg:NA Preferences=[allInt] Interval 26: (V37) int RefPositions {} physReg:NA Preferences=[allInt] Interval 27: long RefPositions {} physReg:NA Preferences=[allInt] Interval 27: (V38) long RefPositions {} physReg:NA Preferences=[allInt] Interval 28: int RefPositions {} physReg:NA Preferences=[allInt] Interval 28: (V39) int RefPositions {} physReg:NA Preferences=[allInt] Interval 29: int RefPositions {} physReg:NA Preferences=[allInt] Interval 29: (V40) int RefPositions {} physReg:NA Preferences=[allInt] Interval 30: int RefPositions {} physReg:NA Preferences=[allInt] Interval 30: (V41) int RefPositions {} physReg:NA Preferences=[allInt] Interval 31: int RefPositions {} physReg:NA Preferences=[allInt] Interval 31: (V42) int RefPositions {} physReg:NA Preferences=[allInt] Interval 32: int RefPositions {} physReg:NA Preferences=[allInt] Interval 32: (V43) int RefPositions {} physReg:NA Preferences=[allInt] Interval 33: int RefPositions {} physReg:NA Preferences=[allInt] Interval 33: (V46) int RefPositions {} physReg:NA Preferences=[allInt] Interval 34: int RefPositions {} physReg:NA Preferences=[allInt] Interval 34: (V51) int RefPositions {} physReg:NA Preferences=[allInt] Interval 35: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 35: (V52) ref (field) RefPositions {} physReg:NA Preferences=[allInt] Interval 36: int RefPositions {} physReg:NA Preferences=[allInt] Interval 36: (V53) int (field) RefPositions {} physReg:NA Preferences=[allInt] Interval 37: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 37: (V64) ref (field) RefPositions {} physReg:NA Preferences=[allInt] Interval 38: int RefPositions {} physReg:NA Preferences=[allInt] Interval 38: (V65) int (field) RefPositions {} physReg:NA Preferences=[allInt] Interval 39: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 39: (V66) ref (field) RefPositions {} physReg:NA Preferences=[allInt] Interval 40: int RefPositions {} physReg:NA Preferences=[allInt] Interval 40: (V67) int (field) RefPositions {} physReg:NA Preferences=[allInt] Interval 41: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 41: (V70) ref (field) RefPositions {} physReg:NA Preferences=[allInt] Interval 42: int RefPositions {} physReg:NA Preferences=[allInt] Interval 42: (V71) int (field) RefPositions {} physReg:NA Preferences=[allInt] Interval 43: byref RefPositions {} physReg:NA Preferences=[allInt] Interval 43: (V74) byref RefPositions {} physReg:NA Preferences=[allInt] Interval 44: long RefPositions {} physReg:NA Preferences=[allInt] Interval 44: (V75) long RefPositions {} physReg:NA Preferences=[allInt] Interval 45: byref RefPositions {} physReg:NA Preferences=[allInt] Interval 45: (V77) byref RefPositions {} physReg:NA Preferences=[allInt] Interval 46: byref RefPositions {} physReg:NA Preferences=[allInt] Interval 46: (V78) byref RefPositions {} physReg:NA Preferences=[allInt] Interval 47: long RefPositions {} physReg:NA Preferences=[allInt] Interval 47: (V79) long RefPositions {} physReg:NA Preferences=[allInt] Interval 48: byref RefPositions {} physReg:NA Preferences=[allInt] Interval 48: (V80) byref RefPositions {} physReg:NA Preferences=[allInt] Interval 49: byref RefPositions {} physReg:NA Preferences=[allInt] Interval 49: (V81) byref RefPositions {} physReg:NA Preferences=[allInt] Interval 50: byref RefPositions {} physReg:NA Preferences=[allInt] Interval 50: (V82) byref RefPositions {} physReg:NA Preferences=[allInt] Interval 51: byref RefPositions {} physReg:NA Preferences=[allInt] Interval 51: (V83) byref RefPositions {} physReg:NA Preferences=[allInt] Interval 52: byref RefPositions {} physReg:NA Preferences=[allInt] Interval 52: (V84) byref RefPositions {} physReg:NA Preferences=[allInt] Interval 53: byref RefPositions {} physReg:NA Preferences=[allInt] Interval 53: (V85) byref RefPositions {} physReg:NA Preferences=[allInt] Interval 54: byref RefPositions {} physReg:NA Preferences=[allInt] Interval 54: (V87) byref RefPositions {} physReg:NA Preferences=[allInt] Interval 55: long RefPositions {} physReg:NA Preferences=[allInt] Interval 55: (V88) long RefPositions {} physReg:NA Preferences=[allInt] Interval 56: byref RefPositions {} physReg:NA Preferences=[allInt] Interval 56: (V89) byref RefPositions {} physReg:NA Preferences=[allInt] Interval 57: byref RefPositions {} physReg:NA Preferences=[allInt] Interval 57: (V90) byref RefPositions {} physReg:NA Preferences=[allInt] FP callee save candidate vars: None floatVarCount = 0; hasLoops = 0, singleExit = 0 TUPLE STYLE DUMP BEFORE LSRA LSRA Block Sequence: BB01( 1 ) BB02( 1 ) BB03( 0.50) BB04( 0.50) BB05( 0.50) BB06( 0.50) BB07( 0.50) BB08( 0.50) BB09( 0.50) BB10( 0.50) BB11( 0.50) BB12( 0.50) BB13( 0.50) BB14( 0.50) BB15( 0.50) BB16( 0.50) BB17( 0.50) BB18( 0.50) BB19( 0.50) BB20( 0.50) BB21( 0.50) BB22( 0.50) BB23( 0.50) BB24( 0.50) BB25( 0.50) BB26( 0.50) BB27( 0.50) BB28( 0.50) BB29( 0.50) BB30( 0.50) BB31( 0.50) BB32( 0.50) BB33( 0.50) BB34( 0.50) BB35( 0.50) BB36( 0.50) BB37( 0.50) BB38( 0.50) BB39( 0.50) BB40( 0.50) BB41( 0.50) BB42( 0.50) BB43( 0.50) BB44( 0.50) BB01 [???..???), preds={} succs={BB02} ===== N001. V00(t531) N002. t532 = IND ; t531 N004. V52(t533); t532 N005. V00(t535*) N007. t537 = LEA(b+8) ; t535* N008. t538 = IND ; t537 N010. V53(t539); t538 BB02 [000..00D) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ===== N000. IL_OFFSET IL offset: 0x0 N001. V52(t2) N000. t988 = LEA(b+8) ; t2 N002. t3 = IND ; t988 N003. CNS_INT 0 N004. NE ; t3 N005. JTRUE BB03 [00D..017) (return), preds={BB02} succs={} ===== N000. IL_OFFSET IL offset: 0xd N002. V01(t400) N000. t995 = PUTARG_REG; t400 N001. V01(t996*) N002. t997 = LEA(b+0) ; t996* N003. t998 = IND ; t997 N004. t999 = LEA(b+80); t998 N005. t1000 = IND ; t999 N006. t1001 = LEA(b+0) ; t1000 N007. t1002 = IND ; t1001 N003. t401 = CALLV ind; t995,t1002 N004. V02(t399*) N000. STOREIND ; t399*,t401 N001. t404 = CNS_INT 1 N002. RETURN ; t404 BB04 [017..065) -> BB06 (cond), preds={BB02} succs={BB05,BB06} ===== N002. V01(t7) N000. t1003 = PUTARG_REG; t7 N001. V01(t1004) N002. t1005 = LEA(b+0) ; t1004 N003. t1006 = IND ; t1005 N004. t1007 = LEA(b+72); t1006 N005. t1008 = IND ; t1007 N006. t1009 = LEA(b+32); t1008 N007. t1010 = IND ; t1009 N003. t406 = CALLV ind; t1003,t1010 N004. CNS_INT 1 N005. t408 = ADD ; t406 N006. t409 = CAST ; t408 N007. CNS_INT 1 N008. t11 = ADD ; t409 N010. V03(t13); t11 N000. IL_OFFSET IL offset: 0x20 N001. V53(t17) N003. V40(t424); t17 N000. IL_OFFSET IL offset: 0x20 N001. V40(t412*) N002. CNS_INT 0 N003. LE ; t412* N004. JTRUE BB05 [020..021) -> BB07 (always), preds={BB04} succs={BB07} ===== N000. IL_OFFSET IL offset: 0x20 N001. V53(t419) N003. V39(t421); t419 BB06 [020..021), preds={BB04} succs={BB07} ===== N000. IL_OFFSET IL offset: 0x20 N001. t415 = CNS_INT 0 N003. V39(t417); t415 BB07 [000..000) -> BB09 (cond), preds={BB05,BB06} succs={BB08,BB09} ===== N001. V39(t422*) N003. V31(t21); t422* N001. V52(t428) N000. t990 = LEA(b+8) ; t428 N002. t429 = IND ; t990 N004. V42(t443); t429 N001. V31(t23) N002. V42(t431) N003. LE ; t23,t431 N004. JTRUE BB08 [000..000) -> BB10 (always), preds={BB07} succs={BB10} ===== N001. V42(t438*) N003. V41(t440); t438* BB09 [000..000), preds={BB07} succs={BB10} ===== N001. V31(t434) N003. V41(t436); t434 BB10 [???..???) -> BB14 (cond), preds={BB08,BB09} succs={BB11,BB14} ===== N001. V31(t22*) N002. V41(t32) N003. t33 = SUB ; t22*,t32 N005. V05(t35); t33 N000. IL_OFFSET IL offset: 0x42 N001. V41(t42*) N003. V08(t44); t42* N001. V52(t447) N000. t992 = LEA(b+8) ; t447 N002. t448 = IND ; t992 N004. V09(t50); t448 N000. IL_OFFSET IL offset: 0x4f N001. V09(t51) N002. V08(t52) N003. t53 = SUB ; t51,t52 N005. V10(t55); t53 N001. t63 = LCL_VAR_ADDR V11 loc8 ref V11._bits (offs=0x00) -> V54 tmp24 int V11._sign (offs=0x08) -> V55 tmp25 N004. V75(t563); t63 N005. t547 = LCL_VAR_ADDR V73 tmp43 N008. V74(t549); t547 N009. V74(t550) N011. V52(t552) N000. STOREIND ; t550,t552 N014. V74(t555*) N016. t557 = LEA(b+8) ; t555* N018. V53(t559) N000. STOREIND ; t557,t559 N023. V75(t564*) N000. t1011 = PUTARG_REG; t564* N024. t565 = LCL_VAR_ADDR V73 tmp43 N000. t1012 = PUTARG_REG; t565 N026. V08(t58) N000. t1013 = PUTARG_REG; t58 N027. t57 = CNS_INT 0 N000. t1014 = PUTARG_REG; t57 N028. CALL ; t1011,t1012,t1013,t1014 N000. IL_OFFSET IL offset: 0x61 N001. V05(t65) N002. CNS_INT 0 N003. EQ ; t65 N004. JTRUE BB11 [065..070) -> BB13 (cond), preds={BB10} succs={BB12,BB13} ===== N002. V01(t382) N000. t1015 = PUTARG_REG; t382 N003. t383 = CALL ; t1015 N004. t385 = CAST ; t383 N005. V05(t380) N006. t381 = CAST ; t380 N007. GE ; t385,t381 N008. JTRUE BB12 [070..07A) (return), preds={BB11} succs={} ===== N000. IL_OFFSET IL offset: 0x70 N002. V01(t393) N000. t1016 = PUTARG_REG; t393 N001. V01(t1017*) N002. t1018 = LEA(b+0) ; t1017* N003. t1019 = IND ; t1018 N004. t1020 = LEA(b+80); t1019 N005. t1021 = IND ; t1020 N006. t1022 = LEA(b+8) ; t1021 N007. t1023 = IND ; t1022 N003. t394 = CALLV ind; t1016,t1023 N004. V02(t392*) N000. STOREIND ; t392*,t394 N001. t397 = CNS_INT 3 N002. RETURN ; t397 BB13 [07A..082), preds={BB11} succs={BB14} ===== N000. IL_OFFSET IL offset: 0x7a N003. t388 = LCL_VAR_ADDR V11 loc8 ref V11._bits (offs=0x00) -> V54 tmp24 int V11._sign (offs=0x08) -> V55 tmp25 N000. t1024 = PUTARG_REG; t388 N005. V05(t390*) N000. t1025 = PUTARG_REG; t390* N006. CALL ; t1024,t1025 BB14 [082..092) -> BB16 (cond), preds={BB10,BB13} succs={BB15,BB16} ===== N001. t577 = LCL_VAR_ADDR V76 tmp46 N004. V77(t579); t577 N005. V77(t580) N007. t582 = V54 MEM N000. STOREIND ; t580,t582 N010. V77(t585*) N012. t587 = LEA(b+8) ; t585* N014. t589 = V55 MEM N000. STOREIND ; t587,t589 N018. t592 = LCL_VAR_ADDR V76 tmp46 N000. t1026 = PUTARG_REG; t592 N020. t71 = LCL_VAR_ADDR V12 loc9 N000. t1027 = PUTARG_REG; t71 N021. t72 = CALL ; t1026,t1027 N023. V13(t77); t72 N000. IL_OFFSET IL offset: 0x8d N001. V13(t78) N002. V03(t79) N003. GE ; t78,t79 N004. JTRUE BB15 [092..096) -> BB17 (cond), preds={BB14} succs={BB16,BB17} ===== N000. IL_OFFSET IL offset: 0x92 N001. V10(t91) N002. CNS_INT 0 N003. NE ; t91 N004. JTRUE BB16 [096..0A7) -> BB44 (always), preds={BB14,BB15} succs={BB44} ===== N000. IL_OFFSET IL offset: 0x96 N005. V02(t88*) N000. PUTARG_STK [+0x20]; t88* N006. V10(t84*) N007. CNS_INT 0 N008. t86 = NE ; t84* N000. t1029 = PUTARG_REG; t86 N009. t82 = V12 MEM N000. t1030 = PUTARG_REG; t82 N010. V13(t83*) N000. t1031 = PUTARG_REG; t83* N011. V01(t87*) N000. t1032 = PUTARG_REG; t87* N012. t89 = CALL ; t1029,t1030,t1031,t1032 N014. V51(t600); t89 BB17 [0A7..0B0) -> BB19 (cond), preds={BB15} succs={BB18,BB19} ===== N000. IL_OFFSET IL offset: 0xa7 N001. V53(t97) N002. CNS_INT 0 N003. LT ; t97 N004. JTRUE BB18 [0B0..0B4) -> BB20 (always), preds={BB17} succs={BB20} ===== N000. IL_OFFSET IL offset: 0xb0 N001. V10(t376*) N003. V32(t378); t376* BB19 [0B4..0BE), preds={BB17} succs={BB20} ===== N000. IL_OFFSET IL offset: 0xb4 N001. V10(t101*) N002. V53(t104) N003. t106 = SUB ; t101*,t104 N005. V32(t108); t106 BB20 [0BE..0C4) -> BB23 (cond), preds={BB18,BB19} succs={BB21,BB23} ===== N001. V32(t110*) N003. V14(t112); t110* N000. IL_OFFSET IL offset: 0xc0 N001. V13(t113) N002. CNS_INT 0 N003. NE ; t113 N004. JTRUE BB21 [0C4..0D9) -> BB23 (cond), preds={BB20} succs={BB22,BB23} ===== N001. V52(t455) N000. t994 = LEA(b+8) ; t455 N002. t456 = IND ; t994 N003. t358 = CAST ; t456 N004. V14(t352) N005. t353 = CAST ; t352 N006. t359 = SUB ; t353,t358 N008. V38(t363); t359 N002. V01(t360) N000. t1033 = PUTARG_REG; t360 N003. t361 = CALL ; t1033 N004. t366 = CAST ; t361 N005. V38(t364*) N006. GE ; t366,t364* N007. JTRUE BB22 [0D9..0E3) (return), preds={BB21} succs={} ===== N000. IL_OFFSET IL offset: 0xd9 N002. V01(t370) N000. t1034 = PUTARG_REG; t370 N001. V01(t1035*) N002. t1036 = LEA(b+0) ; t1035* N003. t1037 = IND ; t1036 N004. t1038 = LEA(b+80); t1037 N005. t1039 = IND ; t1038 N006. t1040 = LEA(b+0) ; t1039 N007. t1041 = IND ; t1040 N003. t371 = CALLV ind; t1034,t1041 N004. V02(t369*) N000. STOREIND ; t369*,t371 N001. t374 = CNS_INT 2 N002. RETURN ; t374 BB23 [0E3..117) -> BB25 (cond), preds={BB20,BB21} succs={BB24,BB25} ===== N001. t124 = LCL_VAR_ADDR V15 loc12 ref V15._bits (offs=0x00) -> V56 tmp26 int V15._sign (offs=0x08) -> V57 tmp27 N004. V79(t623); t124 N005. t607 = LCL_VAR_ADDR V73 tmp43 N008. V78(t609); t607 N009. V78(t610) N011. V52(t612*) N000. STOREIND ; t610,t612* N014. V78(t615*) N016. t617 = LEA(b+8) ; t615* N018. V53(t619*) N000. STOREIND ; t617,t619* N023. V79(t624*) N000. t1042 = PUTARG_REG; t624* N024. t625 = LCL_VAR_ADDR V73 tmp43 N000. t1043 = PUTARG_REG; t625 N026. V08(t118*) N000. t1044 = PUTARG_REG; t118* N027. V09(t119*) N000. t1045 = PUTARG_REG; t119* N028. CALL ; t1042,t1043,t1044,t1045 N000. IL_OFFSET IL offset: 0xef N003. t131 = CNS_INT 0x7ff815262aa0 N000. t1046 = PUTARG_REG; t131 N004. t132 = CNS_INT 173 N000. t1047 = PUTARG_REG; t132 N005. CALL help; t1046,t1047 N001. t634 = CNS_INT(h) 0xd1ffab1e static Fseq[BigOne] N002. t633 = IND ; t634 N003. CNS_INT 8 Fseq[#FirstElem] N004. t632 = ADD ; t633 N006. V80(t637); t632 N007. V80(t639) N008. t640 = IND ; t639 N010. V58 MEM; t640 N012. V80(t644*) N014. t646 = LEA(b+8) ; t644* N015. t647 = IND ; t646 N017. V59 MEM; t647 N000. IL_OFFSET IL offset: 0xf6 N003. t138 = LCL_VAR_ADDR V16 loc13 ref V16._bits (offs=0x00) -> V58 tmp28 int V16._sign (offs=0x08) -> V59 tmp29 N000. t1048 = PUTARG_REG; t138 N005. V14(t140*) N000. t1049 = PUTARG_REG; t140* N006. CALL ; t1048,t1049 N000. IL_OFFSET IL offset: 0xff N001. t653 = V56 MEM N003. V64(t654); t653 N004. t656 = V57 MEM N006. V65(t657); t656 N000. IL_OFFSET IL offset: 0xff N001. t663 = LCL_VAR_ADDR V76 tmp46 N004. V81(t665); t663 N005. V81(t666) N007. V64(t668*) N000. STOREIND ; t666,t668* N010. V81(t671*) N012. t673 = LEA(b+8) ; t671* N014. V65(t675*) N000. STOREIND ; t673,t675* N018. t678 = LCL_VAR_ADDR V76 tmp46 N000. t1050 = PUTARG_REG; t678 N020. t462 = LCL_VAR_ADDR V45 tmp15 N000. t1051 = PUTARG_REG; t462 N021. t463 = CALL ; t1050,t1051 N023. V43(t468); t463 N000. IL_OFFSET IL offset: 0xff N001. t473 = CNS_INT null N003. V45 MEM; t473 N001. V43(t469*) N003. V17(t148); t469* N000. IL_OFFSET IL offset: 0x108 N001. t682 = V58 MEM N003. V66(t683); t682 N004. t685 = V59 MEM N006. V67(t686); t685 N000. IL_OFFSET IL offset: 0x108 N001. t692 = LCL_VAR_ADDR V76 tmp46 N004. V82(t694); t692 N005. V82(t695) N007. V66(t697*) N000. STOREIND ; t695,t697* N010. V82(t700*) N012. t702 = LEA(b+8) ; t700* N014. V67(t704*) N000. STOREIND ; t702,t704* N018. t707 = LCL_VAR_ADDR V76 tmp46 N000. t1052 = PUTARG_REG; t707 N020. t480 = LCL_VAR_ADDR V48 tmp18 N000. t1053 = PUTARG_REG; t480 N021. t481 = CALL ; t1052,t1053 N023. V46(t486); t481 N000. IL_OFFSET IL offset: 0x108 N001. t491 = CNS_INT null N003. V48 MEM; t491 N001. V46(t487*) N003. V18(t155); t487* N000. IL_OFFSET IL offset: 0x111 N001. V18(t156) N002. V17(t157) N003. GT ; t156,t157 N004. JTRUE BB24 [117..11A) -> BB26 (always), preds={BB23} succs={BB26} ===== N000. IL_OFFSET IL offset: 0x117 N001. t348 = CNS_INT 0 N003. V33(t350); t348 BB25 [11A..11F), preds={BB23} succs={BB26} ===== N000. IL_OFFSET IL offset: 0x11a N001. V18(t160*) N002. V17(t161*) N003. t162 = SUB ; t160*,t161* N005. V33(t164); t162 BB26 [11F..126) -> BB28 (cond), preds={BB24,BB25} succs={BB27,BB28} ===== N001. V33(t166*) N003. V19(t168); t166* N000. IL_OFFSET IL offset: 0x121 N001. V19(t169) N002. CNS_INT 0 N003. EQ ; t169 N004. JTRUE BB27 [126..12F), preds={BB26} succs={BB28} ===== N000. IL_OFFSET IL offset: 0x126 N003. t344 = LCL_VAR_ADDR V15 loc12 ref V15._bits (offs=0x00) -> V56 tmp26 int V15._sign (offs=0x08) -> V57 tmp27 N000. t1054 = PUTARG_REG; t344 N005. V19(t346) N000. t1055 = PUTARG_REG; t346 N006. CALL ; t1054,t1055 BB28 [12F..13E) -> BB32 (cond), preds={BB26,BB27} succs={BB29,BB32} ===== N000. IL_OFFSET IL offset: 0x12f N001. V03(t173*) N002. V13(t174) N003. t175 = SUB ; t173*,t174 N005. V20(t177); t175 N000. IL_OFFSET IL offset: 0x135 N001. V20(t178) N003. V21(t180); t178 N000. IL_OFFSET IL offset: 0x139 N001. V13(t181) N002. CNS_INT 0 N003. EQ ; t181 N004. JTRUE BB29 [13E..144) -> BB31 (cond), preds={BB28} succs={BB30,BB31} ===== N000. IL_OFFSET IL offset: 0x13e N001. V19(t326) N002. V20(t327) N003. LE ; t326,t327 N004. JTRUE BB30 [144..155) -> BB44 (always), preds={BB29} succs={BB44} ===== N000. IL_OFFSET IL offset: 0x144 N005. V02(t341*) N000. PUTARG_STK [+0x20]; t341* N006. t339 = CNS_INT 1 N000. t1057 = PUTARG_REG; t339 N007. t335 = V12 MEM N000. t1058 = PUTARG_REG; t335 N008. V13(t336*) N000. t1059 = PUTARG_REG; t336* N009. V01(t340*) N000. t1060 = PUTARG_REG; t340* N010. t342 = CALL ; t1057,t1058,t1059,t1060 N012. V51(t717); t342 BB31 [155..15C), preds={BB29} succs={BB32} ===== N000. IL_OFFSET IL offset: 0x155 N001. V20(t330) N002. V19(t331) N003. t332 = SUB ; t330,t331 N005. V21(t334); t332 BB32 [15C..167) -> BB34 (cond), preds={BB28,BB31} succs={BB33,BB34} ===== N000. IL_OFFSET IL offset: 0x15c N001. t719 = V56 MEM N003. V68 MEM; t719 N004. t722 = V57 MEM N006. V69 MEM; t722 N000. IL_OFFSET IL offset: 0x15c N001. t726 = V58 MEM N003. V70(t727); t726 N004. t729 = V59 MEM N006. V71(t730); t729 N001. t496 = LCL_VAR_ADDR V49 tmp19 ref V49._bits (offs=0x00) -> V68 tmp38 int V49._sign (offs=0x08) -> V69 tmp39 N004. V84(t752); t496 N005. t736 = LCL_VAR_ADDR V76 tmp46 N008. V83(t738); t736 N009. V83(t739) N011. V70(t741*) N000. STOREIND ; t739,t741* N014. V83(t744*) N016. t746 = LEA(b+8) ; t744* N018. V71(t748*) N000. STOREIND ; t746,t748* N021. V84(t753*) N000. t1061 = PUTARG_REG; t753* N022. t754 = LCL_VAR_ADDR V76 tmp46 N000. t1062 = PUTARG_REG; t754 N024. t499 = CALL ; t1061,t1062 N025. CNS_INT 0 N026. LT ; t499 N027. JTRUE BB33 [167..16B) -> BB35 (always), preds={BB32} succs={BB35} ===== N000. IL_OFFSET IL offset: 0x167 N001. V19(t322*) N003. V34(t324); t322* BB34 [16B..16F), preds={BB32} succs={BB35} ===== N000. IL_OFFSET IL offset: 0x16b N001. V19(t196*) N002. CNS_INT 1 N003. t198 = ADD ; t196* N005. V34(t200); t198 BB35 [16F..1A4) -> BB40 (cond), preds={BB33,BB34} succs={BB36,BB40} ===== N001. V34(t202*) N003. V22(t204); t202* N000. IL_OFFSET IL offset: 0x171 N003. t205 = LCL_VAR_ADDR V15 loc12 ref V15._bits (offs=0x00) -> V56 tmp26 int V15._sign (offs=0x08) -> V57 tmp27 N000. t1063 = PUTARG_REG; t205 N005. V21(t207*) N000. t1064 = PUTARG_REG; t207* N006. CALL ; t1063,t1064 N000. IL_OFFSET IL offset: 0x17a N001. t219 = LCL_VAR_ADDR V35 tmp5 ref V35._bits (offs=0x00) -> V62 tmp32 int V35._sign (offs=0x08) -> V63 tmp33 N004. V88(t797); t219 N005. t762 = LCL_VAR_ADDR V76 tmp46 N008. V85(t764); t762 N009. V85(t765) N011. t767 = V56 MEM N000. STOREIND ; t765,t767 N014. V85(t770*) N016. t772 = LEA(b+8) ; t770* N018. t774 = V57 MEM N000. STOREIND ; t772,t774 N021. t781 = LCL_VAR_ADDR V86 tmp56 N024. V87(t783); t781 N025. V87(t784) N027. t786 = V58 MEM N000. STOREIND ; t784,t786 N030. V87(t789*) N032. t791 = LEA(b+8) ; t789* N034. t793 = V59 MEM N000. STOREIND ; t791,t793 N038. V88(t798*) N000. t1065 = PUTARG_REG; t798* N039. t799 = LCL_VAR_ADDR V76 tmp46 N000. t1066 = PUTARG_REG; t799 N041. t801 = LCL_VAR_ADDR V86 tmp56 N000. t1067 = PUTARG_REG; t801 N043. t211 = LCL_VAR_ADDR V23 loc20 ref V23._bits (offs=0x00) -> V60 tmp30 int V23._sign (offs=0x08) -> V61 tmp31 N000. t1068 = PUTARG_REG; t211 N045. CALL ; t1065,t1066,t1067,t1068 N001. t808 = LCL_VAR_ADDR V76 tmp46 N004. V89(t810); t808 N005. V89(t811) N007. t813 = V62 MEM N000. STOREIND ; t811,t813 N010. V89(t816*) N012. t818 = LEA(b+8) ; t816* N014. t820 = V63 MEM N000. STOREIND ; t818,t820 N017. t823 = LCL_VAR_ADDR V76 tmp46 N000. t1069 = PUTARG_REG; t823 N019. t218 = CALL ; t1069 N021. V24(t226); t218 N001. V61 MEM N002. CNS_INT 0 N003. t516 = EQ N005. V25(t232); t516 N002. V24(t233) N000. t1070 = PUTARG_REG; t233 N003. t234 = CALL ; t1070 N005. V26(t237); t234 N000. IL_OFFSET IL offset: 0x19e N001. V26(t238) N002. V20(t239) N003. LE ; t238,t239 N004. JTRUE BB36 [1A4..1AF) -> BB38 (cond), preds={BB35} succs={BB37,BB38} ===== N000. IL_OFFSET IL offset: 0x1a4 N001. V26(t282*) N002. V20(t283) N003. t284 = SUB ; t282*,t283 N005. V29(t286); t284 N000. IL_OFFSET IL offset: 0x1ab N001. V25(t287*) N002. CNS_INT 0 N003. EQ ; t287* N004. JTRUE BB37 [1AF..1C3) -> BB39 (always), preds={BB36} succs={BB39} ===== N000. IL_OFFSET IL offset: 0x1af N001. V24(t305) N002. V29(t308) N005. t307 = CNS_INT 1 N006. t311 = LSH ; t307,t308 N007. CNS_INT -1 N008. t314 = ADD ; t311 N011. t318 = TEST_EQ ; t305,t314 N013. V37(t320); t318 BB38 [1C3..1C4), preds={BB36} succs={BB39} ===== N000. IL_OFFSET IL offset: 0x1c3 N001. t291 = CNS_INT 0 N003. V37(t293); t291 BB39 [1C4..1D0), preds={BB37,BB38} succs={BB40} ===== N001. V37(t295*) N002. t826 = CAST ; t295* N004. V25(t297); t826 N000. IL_OFFSET IL offset: 0x1c6 N001. V24(t298*) N002. V29(t299*) N005. t302 = RSZ ; t298*,t299* N007. V24(t304); t302 BB40 [1D0..1E7) -> BB42 (cond), preds={BB35,BB39} succs={BB41,BB42} ===== N001. t831 = LCL_VAR_ADDR V76 tmp46 N004. V90(t833); t831 N005. V90(t834) N007. t836 = V54 MEM N000. STOREIND ; t834,t836 N010. V90(t839*) N012. t841 = LEA(b+8) ; t839* N014. t843 = V55 MEM N000. STOREIND ; t841,t843 N017. t846 = LCL_VAR_ADDR V76 tmp46 N000. t1071 = PUTARG_REG; t846 N019. t243 = CALL ; t1071 N020. V20(t247*) N023. t250 = LSH ; t243,t247* N024. V24(t251*) N025. t252 = ADD ; t250,t251* N027. V27(t254); t252 N000. IL_OFFSET IL offset: 0x1e2 N001. V13(t255) N002. CNS_INT 0 N003. NE ; t255 N004. JTRUE BB41 [1E7..1EE) -> BB43 (always), preds={BB40} succs={BB43} ===== N000. IL_OFFSET IL offset: 0x1e7 N001. V22(t275*) N002. t276 = NEG ; t275* N003. CNS_INT -1 N004. t278 = ADD ; t276 N006. V36(t280); t278 BB42 [1EE..1F2), preds={BB40} succs={BB43} ===== N000. IL_OFFSET IL offset: 0x1ee N001. V13(t259*) N002. CNS_INT -2 N003. t261 = ADD ; t259* N005. V36(t263); t261 BB43 [1F2..202), preds={BB41,BB42} succs={BB44} ===== N000. IL_OFFSET IL offset: 0x1f4 N005. V02(t272*) N000. PUTARG_STK [+0x20]; t272* N006. V01(t268*) N000. t1073 = PUTARG_REG; t268* N007. V27(t269*) N000. t1074 = PUTARG_REG; t269* N008. V36(t270*) N000. t1075 = PUTARG_REG; t270* N009. V25(t271*) N000. t1076 = PUTARG_REG; t271* N010. t273 = CALL ; t1073,t1074,t1075,t1076 N012. V51(t853); t273 BB44 [???..???) (return), preds={BB16,BB30,BB43} succs={} ===== N001. V51(t522*) N002. RETURN ; t522* buildIntervals second part ======== Int arg V01 in reg rdx BB00 regmask=[rdx] minReg=1 fixed> Int arg V00 in reg rcx BB00 regmask=[rcx] minReg=1 fixed> Int arg V02 in reg r8 BB00 regmask=[r8] minReg=1 fixed> NEW BLOCK BB01 DefList: { } N003 ( 1, 1) [000531] ------------ * LCL_VAR byref V00 arg0 u:1 NA Zero Fseq[Mantissa] REG NA $80 DefList: { } N005 ( 3, 2) [000532] n----------- * IND ref REG NA LCL_VAR BB01 regmask=[allInt] minReg=1 last> Interval 58: ref RefPositions {} physReg:NA Preferences=[allInt] IND BB01 regmask=[allInt] minReg=1> DefList: { N005.t532. IND } N007 ( 3, 3) [000533] DA---------- * STORE_LCL_VAR ref V52 tmp22 d:2 NA REG NA BB01 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last> DefList: { } N009 ( 1, 1) [000535] ------------ * LCL_VAR byref V00 arg0 u:1 NA (last use) REG NA $80 DefList: { } N011 ( 2, 2) [000537] -c---------- * LEA(b+8) byref REG NA Contained DefList: { } N013 ( 4, 4) [000538] n----------- * IND int REG NA LCL_VAR BB01 regmask=[allInt] minReg=1 last> Interval 59: int RefPositions {} physReg:NA Preferences=[allInt] IND BB01 regmask=[allInt] minReg=1> DefList: { N013.t538. IND } N015 ( 4, 4) [000539] DA---------- * STORE_LCL_VAR int V53 tmp23 d:2 NA REG NA BB01 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last> CHECKING LAST USES for BB01, liveout={V01 V02 V52 V53} ============================== use: {V00} def: {V52 V53} NEW BLOCK BB02 Setting BB01 as the predecessor for determining incoming variable registers of BB02 DefList: { } N019 (???,???) [000910] ------------ * IL_OFFSET void IL offset: 0x0 REG NA DefList: { } N021 ( 1, 1) [000002] ------------ * LCL_VAR ref V52 tmp22 u:2 NA REG NA DefList: { } N023 (???,???) [000988] -c---------- * LEA(b+8) ref REG NA Contained DefList: { } N025 ( 3, 3) [000003] -c-XG------- * IND int REG NA Contained DefList: { } N027 ( 1, 1) [000004] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { } N029 ( 5, 5) [000005] J--XG--N---- * NE void REG NA LCL_VAR BB02 regmask=[allInt] minReg=1 last> DefList: { } N031 ( 7, 7) [000006] ---XG------- * JTRUE void REG NA CHECKING LAST USES for BB02, liveout={V01 V02 V52 V53} ============================== use: {V52} def: {} NEW BLOCK BB03 Setting BB02 as the predecessor for determining incoming variable registers of BB03 DefList: { } N035 (???,???) [000911] ------------ * IL_OFFSET void IL offset: 0xd REG NA DefList: { } N037 ( 1, 1) [000400] ------------ * LCL_VAR ref V01 arg1 u:1 NA REG NA $c0 DefList: { } N039 (???,???) [000995] ------------ * PUTARG_REG ref REG rcx BB03 regmask=[rcx] minReg=1> LCL_VAR BB03 regmask=[rcx] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 60: ref RefPositions {} physReg:NA Preferences=[allInt] BB03 regmask=[rcx] minReg=1> PUTARG_REG BB03 regmask=[rcx] minReg=1 fixed> Assigning related to DefList: { N039.t995. PUTARG_REG } N041 ( 1, 1) [000996] ------------ * LCL_VAR ref V01 arg1 NA (last use) REG NA DefList: { N039.t995. PUTARG_REG } N043 ( 2, 2) [000997] -c---------- * LEA(b+0) byref REG NA Contained DefList: { N039.t995. PUTARG_REG } N045 ( 5, 4) [000998] ------------ * IND long REG NA LCL_VAR BB03 regmask=[allInt] minReg=1 last> Interval 61: long RefPositions {} physReg:NA Preferences=[allInt] IND BB03 regmask=[allInt] minReg=1> DefList: { N039.t995. PUTARG_REG; N045.t998. IND } N047 ( 6, 5) [000999] -c---------- * LEA(b+80) long REG NA Contained DefList: { N039.t995. PUTARG_REG; N045.t998. IND } N049 ( 9, 7) [001000] ------------ * IND long REG NA BB03 regmask=[allInt] minReg=1 last> Interval 62: long RefPositions {} physReg:NA Preferences=[allInt] IND BB03 regmask=[allInt] minReg=1> DefList: { N039.t995. PUTARG_REG; N049.t1000. IND } N051 ( 10, 8) [001001] -c---------- * LEA(b+0) long REG NA Contained DefList: { N039.t995. PUTARG_REG; N049.t1000. IND } N053 ( 13, 10) [001002] -c---------- * IND long REG NA Contained DefList: { N039.t995. PUTARG_REG; N049.t1000. IND } N055 ( 21, 10) [000401] --CXG------- * CALLV ind long FloatingPointType.get_Zero REG NA $459 BB03 regmask=[rcx] minReg=1> BB03 regmask=[rcx] minReg=1 last fixed> BB03 regmask=[allInt] minReg=1 last> BB03 regmask=[rax] minReg=1> BB03 regmask=[rcx] minReg=1> BB03 regmask=[rdx] minReg=1> BB03 regmask=[r8] minReg=1> BB03 regmask=[r9] minReg=1> BB03 regmask=[r10] minReg=1> BB03 regmask=[r11] minReg=1> Interval 63: long RefPositions {} physReg:NA Preferences=[allInt] BB03 regmask=[rax] minReg=1> CALL BB03 regmask=[rax] minReg=1 fixed> DefList: { N055.t401. CALL } N057 ( 1, 1) [000399] ------------ * LCL_VAR byref V02 arg2 u:1 NA (last use) REG NA $81 DefList: { N055.t401. CALL } N059 (???,???) [000912] -ACXG------- * STOREIND long REG NA LCL_VAR BB03 regmask=[allInt] minReg=1 last> BB03 regmask=[allInt] minReg=1 last> DefList: { } N061 ( 1, 1) [000404] ------------ * CNS_INT int 1 REG NA $41 Interval 64: int RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB03 regmask=[allInt] minReg=1> DefList: { N061.t404. CNS_INT } N063 ( 2, 2) [000520] ------------ * RETURN int REG NA $5cb BB03 regmask=[rax] minReg=1> BB03 regmask=[rax] minReg=1 last fixed> CHECKING LAST USES for BB03, liveout={} ============================== use: {V01 V02} def: {} NEW BLOCK BB04 Setting BB02 as the predecessor for determining incoming variable registers of BB04 DefList: { } N067 ( 1, 1) [000007] ------------ * LCL_VAR ref V01 arg1 u:1 NA REG NA $c0 DefList: { } N069 (???,???) [001003] ------------ * PUTARG_REG ref REG rcx BB04 regmask=[rcx] minReg=1> LCL_VAR BB04 regmask=[rcx] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 65: ref RefPositions {} physReg:NA Preferences=[allInt] BB04 regmask=[rcx] minReg=1> PUTARG_REG BB04 regmask=[rcx] minReg=1 fixed> Assigning related to DefList: { N069.t1003. PUTARG_REG } N071 ( 1, 1) [001004] ------------ * LCL_VAR ref V01 arg1 NA REG NA DefList: { N069.t1003. PUTARG_REG } N073 ( 2, 2) [001005] -c---------- * LEA(b+0) byref REG NA Contained DefList: { N069.t1003. PUTARG_REG } N075 ( 5, 4) [001006] ------------ * IND long REG NA LCL_VAR BB04 regmask=[allInt] minReg=1 last> Interval 66: long RefPositions {} physReg:NA Preferences=[allInt] IND BB04 regmask=[allInt] minReg=1> DefList: { N069.t1003. PUTARG_REG; N075.t1006. IND } N077 ( 6, 5) [001007] -c---------- * LEA(b+72) long REG NA Contained DefList: { N069.t1003. PUTARG_REG; N075.t1006. IND } N079 ( 9, 7) [001008] ------------ * IND long REG NA BB04 regmask=[allInt] minReg=1 last> Interval 67: long RefPositions {} physReg:NA Preferences=[allInt] IND BB04 regmask=[allInt] minReg=1> DefList: { N069.t1003. PUTARG_REG; N079.t1008. IND } N081 ( 10, 8) [001009] -c---------- * LEA(b+32) long REG NA Contained DefList: { N069.t1003. PUTARG_REG; N079.t1008. IND } N083 ( 13, 10) [001010] -c---------- * IND long REG NA Contained DefList: { N069.t1003. PUTARG_REG; N079.t1008. IND } N085 ( 21, 10) [000406] --CXG------- * CALLV ind int FloatingPointType.get_DenormalMantissaBits REG NA $282 BB04 regmask=[rcx] minReg=1> BB04 regmask=[rcx] minReg=1 last fixed> BB04 regmask=[allInt] minReg=1 last> BB04 regmask=[rax] minReg=1> BB04 regmask=[rcx] minReg=1> BB04 regmask=[rdx] minReg=1> BB04 regmask=[r8] minReg=1> BB04 regmask=[r9] minReg=1> BB04 regmask=[r10] minReg=1> BB04 regmask=[r11] minReg=1> Interval 68: int RefPositions {} physReg:NA Preferences=[allInt] BB04 regmask=[rax] minReg=1> CALL BB04 regmask=[rax] minReg=1 fixed> DefList: { N085.t406. CALL } N087 ( 1, 1) [000407] -c---------- * CNS_INT int 1 REG NA $41 Contained DefList: { N085.t406. CALL } N089 ( 23, 12) [000408] ---XG------- * ADD int REG NA $346 BB04 regmask=[allInt] minReg=1 last> Interval 69: int RefPositions {} physReg:NA Preferences=[allInt] ADD BB04 regmask=[allInt] minReg=1> Assigning related to DefList: { N089.t408. ADD } N091 ( 24, 14) [000409] ---XG------- * CAST int <- ushort <- int REG NA $347 BB04 regmask=[allInt] minReg=1 last> Interval 70: int RefPositions {} physReg:NA Preferences=[allInt] CAST BB04 regmask=[allInt] minReg=1> DefList: { N091.t409. CAST } N093 ( 1, 1) [000010] -c---------- * CNS_INT int 1 REG NA $41 Contained DefList: { N091.t409. CAST } N095 ( 26, 16) [000011] ---XG------- * ADD int REG NA $348 BB04 regmask=[allInt] minReg=1 last> Interval 71: int RefPositions {} physReg:NA Preferences=[allInt] ADD BB04 regmask=[allInt] minReg=1> Assigning related to DefList: { N095.t11. ADD } N097 ( 30, 19) [000013] DA-XG------- * STORE_LCL_VAR int V03 loc0 d:2 NA REG NA BB04 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB04 regmask=[allInt] minReg=1 last> DefList: { } N099 (???,???) [000913] ------------ * IL_OFFSET void IL offset: 0x20 REG NA DefList: { } N101 ( 1, 1) [000017] ------------ * LCL_VAR int V53 tmp23 u:2 NA REG NA DefList: { } N103 ( 5, 4) [000424] DA--G------- * STORE_LCL_VAR int V40 tmp10 d:2 NA REG NA LCL_VAR BB04 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1 last> DefList: { } N105 (???,???) [000914] ------------ * IL_OFFSET void IL offset: 0x20 REG NA DefList: { } N107 ( 1, 1) [000412] ------------ * LCL_VAR int V40 tmp10 u:2 NA (last use) REG NA DefList: { } N109 ( 1, 1) [000411] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { } N111 ( 3, 3) [000413] J------N---- * LE void REG NA LCL_VAR BB04 regmask=[allInt] minReg=1 last> DefList: { } N113 ( 5, 5) [000414] ------------ * JTRUE void REG NA CHECKING LAST USES for BB04, liveout={V01 V02 V03 V52 V53} ============================== use: {V01 V53} def: {V03 V40} NEW BLOCK BB05 Setting BB04 as the predecessor for determining incoming variable registers of BB05 DefList: { } N117 (???,???) [000915] ------------ * IL_OFFSET void IL offset: 0x20 REG NA DefList: { } N119 ( 3, 2) [000419] ------------ * LCL_VAR int V53 tmp23 u:2 NA REG NA DefList: { } N121 ( 7, 5) [000421] DA---------- * STORE_LCL_VAR int V39 tmp9 d:4 NA REG NA LCL_VAR BB05 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB05 regmask=[allInt] minReg=1 last> CHECKING LAST USES for BB05, liveout={V01 V02 V03 V39 V52 V53} ============================== use: {V53} def: {V39} NEW BLOCK BB06 Setting BB04 as the predecessor for determining incoming variable registers of BB06 DefList: { } N125 (???,???) [000916] ------------ * IL_OFFSET void IL offset: 0x20 REG NA DefList: { } N127 ( 1, 1) [000415] ------------ * CNS_INT int 0 REG NA $40 Interval 72: int RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB06 regmask=[allInt] minReg=1> DefList: { N127.t415. CNS_INT } N129 ( 5, 4) [000417] DA---------- * STORE_LCL_VAR int V39 tmp9 d:3 NA REG NA BB06 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB06 regmask=[allInt] minReg=1 last> CHECKING LAST USES for BB06, liveout={V01 V02 V03 V39 V52 V53} ============================== use: {} def: {V39} NEW BLOCK BB07 Setting BB05 as the predecessor for determining incoming variable registers of BB07 DefList: { } N133 ( 3, 2) [000422] ------------ * LCL_VAR int V39 tmp9 u:2 NA (last use) REG NA $241 DefList: { } N135 ( 3, 3) [000021] DA---------- * STORE_LCL_VAR int V31 tmp1 d:2 NA REG NA LCL_VAR BB07 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB07 regmask=[allInt] minReg=1 last> DefList: { } N137 ( 1, 1) [000428] ------------ * LCL_VAR ref V52 tmp22 u:2 NA REG NA DefList: { } N139 (???,???) [000990] -c---------- * LEA(b+8) ref REG NA Contained DefList: { } N141 ( 3, 3) [000429] ---XG------- * IND int REG NA LCL_VAR BB07 regmask=[allInt] minReg=1 last> Interval 73: int RefPositions {} physReg:NA Preferences=[allInt] IND BB07 regmask=[allInt] minReg=1> DefList: { N141.t429. IND } N143 ( 3, 3) [000443] DA-XG------- * STORE_LCL_VAR int V42 tmp12 d:2 NA REG NA BB07 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB07 regmask=[allInt] minReg=1 last> DefList: { } N145 ( 3, 2) [000023] ------------ * LCL_VAR int V31 tmp1 u:2 NA REG NA $241 DefList: { } N147 ( 1, 1) [000431] ------------ * LCL_VAR int V42 tmp12 u:2 NA REG NA DefList: { } N149 ( 5, 4) [000432] N------N-U-- * LE void REG NA LCL_VAR BB07 regmask=[allInt] minReg=1 last> LCL_VAR BB07 regmask=[allInt] minReg=1 last> DefList: { } N151 ( 7, 6) [000433] ------------ * JTRUE void REG NA CHECKING LAST USES for BB07, liveout={V01 V02 V03 V31 V42 V52 V53} ============================== use: {V39 V52} def: {V31 V42} NEW BLOCK BB08 Setting BB07 as the predecessor for determining incoming variable registers of BB08 DefList: { } N155 ( 1, 1) [000438] ------------ * LCL_VAR int V42 tmp12 u:2 NA (last use) REG NA DefList: { } N157 ( 1, 3) [000440] DA---------- * STORE_LCL_VAR int V41 tmp11 d:4 NA REG NA LCL_VAR BB08 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB08 regmask=[allInt] minReg=1 last> CHECKING LAST USES for BB08, liveout={V01 V02 V03 V31 V41 V52 V53} ============================== use: {V42} def: {V41} NEW BLOCK BB09 Setting BB07 as the predecessor for determining incoming variable registers of BB09 DefList: { } N161 ( 1, 1) [000434] ------------ * LCL_VAR int V31 tmp1 u:2 NA REG NA $241 DefList: { } N163 ( 1, 3) [000436] DA---------- * STORE_LCL_VAR int V41 tmp11 d:3 NA REG NA LCL_VAR BB09 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB09 regmask=[allInt] minReg=1 last> CHECKING LAST USES for BB09, liveout={V01 V02 V03 V31 V41 V52 V53} ============================== use: {V31} def: {V41} NEW BLOCK BB10 Setting BB08 as the predecessor for determining incoming variable registers of BB10 DefList: { } N167 ( 1, 1) [000022] ------------ * LCL_VAR int V31 tmp1 u:2 NA (last use) REG NA $241 DefList: { } N169 ( 1, 1) [000032] ------------ * LCL_VAR int V41 tmp11 u:2 NA REG NA $242 DefList: { } N171 ( 3, 3) [000033] ------------ * SUB int REG NA $34e LCL_VAR BB10 regmask=[allInt] minReg=1 last> LCL_VAR BB10 regmask=[allInt] minReg=1 last> Interval 74: int RefPositions {} physReg:NA Preferences=[allInt] SUB BB10 regmask=[allInt] minReg=1> Assigning related to DefList: { N171.t33. SUB } N173 ( 7, 6) [000035] DA---------- * STORE_LCL_VAR int V05 loc2 d:2 NA REG NA BB10 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB10 regmask=[allInt] minReg=1 last> DefList: { } N175 (???,???) [000917] ------------ * IL_OFFSET void IL offset: 0x42 REG NA DefList: { } N177 ( 1, 1) [000042] ------------ * LCL_VAR int V41 tmp11 u:2 NA (last use) REG NA $242 DefList: { } N179 ( 5, 4) [000044] DA---------- * STORE_LCL_VAR int V08 loc5 d:2 NA REG NA LCL_VAR BB10 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB10 regmask=[allInt] minReg=1 last> DefList: { } N181 ( 1, 1) [000447] ------------ * LCL_VAR ref V52 tmp22 u:2 NA REG NA DefList: { } N183 (???,???) [000992] -c---------- * LEA(b+8) ref REG NA Contained DefList: { } N185 ( 3, 3) [000448] ---XG------- * IND int REG NA LCL_VAR BB10 regmask=[allInt] minReg=1 last> Interval 75: int RefPositions {} physReg:NA Preferences=[allInt] IND BB10 regmask=[allInt] minReg=1> DefList: { N185.t448. IND } N187 ( 7, 6) [000050] DA-XG------- * STORE_LCL_VAR int V09 loc6 d:2 NA REG NA BB10 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB10 regmask=[allInt] minReg=1 last> DefList: { } N189 (???,???) [000918] ------------ * IL_OFFSET void IL offset: 0x4f REG NA DefList: { } N191 ( 3, 2) [000051] ------------ * LCL_VAR int V09 loc6 u:2 NA REG NA DefList: { } N193 ( 1, 1) [000052] ------------ * LCL_VAR int V08 loc5 u:2 NA REG NA $242 DefList: { } N195 ( 5, 4) [000053] ------------ * SUB int REG NA LCL_VAR BB10 regmask=[allInt] minReg=1 last> LCL_VAR BB10 regmask=[allInt] minReg=1 last> Interval 76: int RefPositions {} physReg:NA Preferences=[allInt] SUB BB10 regmask=[allInt] minReg=1> DefList: { N195.t53. SUB } N197 ( 5, 4) [000055] DA---------- * STORE_LCL_VAR int V10 loc7 d:2 NA REG NA BB10 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB10 regmask=[allInt] minReg=1 last> DefList: { } N199 ( 3, 2) [000063] -------N---- * LCL_VAR_ADDR byref V11 loc8 NA * ref V11._bits (offs=0x00) -> V54 tmp24 * int V11._sign (offs=0x08) -> V55 tmp25 REG NA Interval 77: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB10 regmask=[allInt] minReg=1> DefList: { N199.t63. LCL_VAR_ADDR } N201 ( 7, 6) [000563] DA--------L- * STORE_LCL_VAR long V75 tmp45 d:2 NA REG NA BB10 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB10 regmask=[allInt] minReg=1 last> DefList: { } N203 ( 3, 2) [000547] -------N---- * LCL_VAR_ADDR byref V73 tmp43 NA REG NA Interval 78: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB10 regmask=[allInt] minReg=1> DefList: { N203.t547. LCL_VAR_ADDR } N205 ( 3, 3) [000549] DA---------- * STORE_LCL_VAR byref V74 tmp44 d:2 NA REG NA BB10 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB10 regmask=[allInt] minReg=1 last> DefList: { } N207 ( 1, 1) [000550] ------------ * LCL_VAR byref V74 tmp44 u:2 NA Zero Fseq[Mantissa] REG NA $401 DefList: { } N209 ( 1, 1) [000552] -------N---- * LCL_VAR ref V52 tmp22 u:2 NA REG NA DefList: { } N211 (???,???) [000919] -A---------- * STOREIND ref REG NA LCL_VAR BB10 regmask=[allInt] minReg=1 last> LCL_VAR BB10 regmask=[allInt] minReg=1 last> DefList: { } N213 ( 1, 1) [000555] ------------ * LCL_VAR byref V74 tmp44 u:2 NA (last use) REG NA $401 DefList: { } N215 ( 2, 2) [000557] -c---------- * LEA(b+8) byref REG NA Contained DefList: { } N217 ( 1, 1) [000559] -------N---- * LCL_VAR int V53 tmp23 u:2 NA REG NA DefList: { } N219 (???,???) [000920] -A--------L- * STOREIND int REG NA LCL_VAR BB10 regmask=[allInt] minReg=1 last> LCL_VAR BB10 regmask=[allInt] minReg=1 last> DefList: { } N221 ( 3, 2) [000564] ------------ * LCL_VAR long V75 tmp45 u:2 NA (last use) REG NA $400 DefList: { } N223 (???,???) [001011] ------------ * PUTARG_REG long REG rcx BB10 regmask=[rcx] minReg=1> LCL_VAR BB10 regmask=[rcx] minReg=1 last fixed> Interval 79: long RefPositions {} physReg:NA Preferences=[allInt] BB10 regmask=[rcx] minReg=1> PUTARG_REG BB10 regmask=[rcx] minReg=1 fixed> DefList: { N223.t1011. PUTARG_REG } N225 ( 3, 2) [000565] -------N---- * LCL_VAR_ADDR byref V73 tmp43 NA REG NA Interval 80: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB10 regmask=[allInt] minReg=1> DefList: { N223.t1011. PUTARG_REG; N225.t565. LCL_VAR_ADDR } N227 (???,???) [001012] ------------ * PUTARG_REG byref REG rdx BB10 regmask=[rdx] minReg=1> BB10 regmask=[rdx] minReg=1 last fixed> Interval 81: byref RefPositions {} physReg:NA Preferences=[allInt] BB10 regmask=[rdx] minReg=1> PUTARG_REG BB10 regmask=[rdx] minReg=1 fixed> DefList: { N223.t1011. PUTARG_REG; N227.t1012. PUTARG_REG } N229 ( 1, 1) [000058] ------------ * LCL_VAR int V08 loc5 u:2 NA REG NA $242 DefList: { N223.t1011. PUTARG_REG; N227.t1012. PUTARG_REG } N231 (???,???) [001013] ------------ * PUTARG_REG int REG r9 BB10 regmask=[r9] minReg=1> LCL_VAR BB10 regmask=[r9] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 82: int RefPositions {} physReg:NA Preferences=[allInt] BB10 regmask=[r9] minReg=1> PUTARG_REG BB10 regmask=[r9] minReg=1 fixed> Assigning related to DefList: { N223.t1011. PUTARG_REG; N227.t1012. PUTARG_REG; N231.t1013. PUTARG_REG } N233 ( 1, 1) [000057] ------------ * CNS_INT int 0 REG NA $40 Interval 83: int RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB10 regmask=[allInt] minReg=1> DefList: { N223.t1011. PUTARG_REG; N227.t1012. PUTARG_REG; N231.t1013. PUTARG_REG; N233.t57. CNS_INT } N235 (???,???) [001014] ------------ * PUTARG_REG int REG r8 BB10 regmask=[r8] minReg=1> BB10 regmask=[r8] minReg=1 last fixed> Interval 84: int RefPositions {} physReg:NA Preferences=[allInt] BB10 regmask=[r8] minReg=1> PUTARG_REG BB10 regmask=[r8] minReg=1 fixed> DefList: { N223.t1011. PUTARG_REG; N227.t1012. PUTARG_REG; N231.t1013. PUTARG_REG; N235.t1014. PUTARG_REG } N237 ( 49, 35) [000059] S-CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger REG NA $VN.Void BB10 regmask=[rcx] minReg=1> BB10 regmask=[rcx] minReg=1 last fixed> BB10 regmask=[rdx] minReg=1> BB10 regmask=[rdx] minReg=1 last fixed> BB10 regmask=[r9] minReg=1> BB10 regmask=[r9] minReg=1 last fixed> BB10 regmask=[r8] minReg=1> BB10 regmask=[r8] minReg=1 last fixed> BB10 regmask=[rax] minReg=1> BB10 regmask=[rcx] minReg=1> BB10 regmask=[rdx] minReg=1> BB10 regmask=[r8] minReg=1> BB10 regmask=[r9] minReg=1> BB10 regmask=[r10] minReg=1> BB10 regmask=[r11] minReg=1> DefList: { } N239 (???,???) [000921] ------------ * IL_OFFSET void IL offset: 0x61 REG NA DefList: { } N241 ( 3, 2) [000065] ------------ * LCL_VAR int V05 loc2 u:2 NA REG NA $34e DefList: { } N243 ( 1, 1) [000066] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { } N245 ( 5, 4) [000067] N------N---- * EQ void REG NA $351 LCL_VAR BB10 regmask=[allInt] minReg=1 last> DefList: { } N247 ( 7, 6) [000068] ------------ * JTRUE void REG NA CHECKING LAST USES for BB10, liveout={V01 V02 V03 V05 V08 V09 V10 V52 V53} ============================== use: {V31 V41 V52 V53} def: {V05 V08 V09 V10 V74 V75} NEW BLOCK BB11 Setting BB10 as the predecessor for determining incoming variable registers of BB11 DefList: { } N251 ( 1, 1) [000382] ------------ * LCL_VAR ref V01 arg1 u:1 NA REG NA $c0 DefList: { } N253 (???,???) [001015] ------------ * PUTARG_REG ref REG rcx BB11 regmask=[rcx] minReg=1> LCL_VAR BB11 regmask=[rcx] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 85: ref RefPositions {} physReg:NA Preferences=[allInt] BB11 regmask=[rcx] minReg=1> PUTARG_REG BB11 regmask=[rcx] minReg=1 fixed> Assigning related to DefList: { N253.t1015. PUTARG_REG } N255 ( 15, 8) [000383] --CXG------- * CALL int FloatingPointType.get_OverflowDecimalExponent REG NA $291 BB11 regmask=[rcx] minReg=1> BB11 regmask=[rcx] minReg=1 last fixed> BB11 regmask=[rax] minReg=1> BB11 regmask=[rcx] minReg=1> BB11 regmask=[rdx] minReg=1> BB11 regmask=[r8] minReg=1> BB11 regmask=[r9] minReg=1> BB11 regmask=[r10] minReg=1> BB11 regmask=[r11] minReg=1> Interval 86: int RefPositions {} physReg:NA Preferences=[allInt] BB11 regmask=[rax] minReg=1> CALL BB11 regmask=[rax] minReg=1 fixed> DefList: { N255.t383. CALL } N257 ( 16, 10) [000385] ---XG------- * CAST long <- int REG NA $480 BB11 regmask=[allInt] minReg=1 last> Interval 87: long RefPositions {} physReg:NA Preferences=[allInt] CAST BB11 regmask=[allInt] minReg=1> DefList: { N257.t385. CAST } N259 ( 3, 2) [000380] ------------ * LCL_VAR int V05 loc2 u:2 NA REG NA $34e DefList: { N257.t385. CAST } N261 ( 4, 4) [000381] ---------U-- * CAST long <- ulong <- uint REG NA $481 LCL_VAR BB11 regmask=[allInt] minReg=1 last> Interval 88: long RefPositions {} physReg:NA Preferences=[allInt] CAST BB11 regmask=[allInt] minReg=1> DefList: { N257.t385. CAST; N261.t381. CAST } N263 ( 21, 15) [000386] J--XG--N---- * GE void REG NA $352 BB11 regmask=[allInt] minReg=1 last> BB11 regmask=[allInt] minReg=1 last> DefList: { } N265 ( 23, 17) [000387] ---XG------- * JTRUE void REG NA CHECKING LAST USES for BB11, liveout={V01 V02 V03 V05 V08 V09 V10 V52 V53} ============================== use: {V01 V05} def: {} NEW BLOCK BB12 Setting BB11 as the predecessor for determining incoming variable registers of BB12 DefList: { } N269 (???,???) [000922] ------------ * IL_OFFSET void IL offset: 0x70 REG NA DefList: { } N271 ( 1, 1) [000393] ------------ * LCL_VAR ref V01 arg1 u:1 NA REG NA $c0 DefList: { } N273 (???,???) [001016] ------------ * PUTARG_REG ref REG rcx BB12 regmask=[rcx] minReg=1> LCL_VAR BB12 regmask=[rcx] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 89: ref RefPositions {} physReg:NA Preferences=[allInt] BB12 regmask=[rcx] minReg=1> PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed> Assigning related to DefList: { N273.t1016. PUTARG_REG } N275 ( 1, 1) [001017] ------------ * LCL_VAR ref V01 arg1 NA (last use) REG NA DefList: { N273.t1016. PUTARG_REG } N277 ( 2, 2) [001018] -c---------- * LEA(b+0) byref REG NA Contained DefList: { N273.t1016. PUTARG_REG } N279 ( 5, 4) [001019] ------------ * IND long REG NA LCL_VAR BB12 regmask=[allInt] minReg=1 last> Interval 90: long RefPositions {} physReg:NA Preferences=[allInt] IND BB12 regmask=[allInt] minReg=1> DefList: { N273.t1016. PUTARG_REG; N279.t1019. IND } N281 ( 6, 5) [001020] -c---------- * LEA(b+80) long REG NA Contained DefList: { N273.t1016. PUTARG_REG; N279.t1019. IND } N283 ( 9, 7) [001021] ------------ * IND long REG NA BB12 regmask=[allInt] minReg=1 last> Interval 91: long RefPositions {} physReg:NA Preferences=[allInt] IND BB12 regmask=[allInt] minReg=1> DefList: { N273.t1016. PUTARG_REG; N283.t1021. IND } N285 ( 10, 8) [001022] -c---------- * LEA(b+8) long REG NA Contained DefList: { N273.t1016. PUTARG_REG; N283.t1021. IND } N287 ( 13, 10) [001023] -c---------- * IND long REG NA Contained DefList: { N273.t1016. PUTARG_REG; N283.t1021. IND } N289 ( 21, 10) [000394] --CXG------- * CALLV ind long FloatingPointType.get_Infinity REG NA $458 BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> BB12 regmask=[allInt] minReg=1 last> BB12 regmask=[rax] minReg=1> BB12 regmask=[rcx] minReg=1> BB12 regmask=[rdx] minReg=1> BB12 regmask=[r8] minReg=1> BB12 regmask=[r9] minReg=1> BB12 regmask=[r10] minReg=1> BB12 regmask=[r11] minReg=1> Interval 92: long RefPositions {} physReg:NA Preferences=[allInt] BB12 regmask=[rax] minReg=1> CALL BB12 regmask=[rax] minReg=1 fixed> DefList: { N289.t394. CALL } N291 ( 1, 1) [000392] ------------ * LCL_VAR byref V02 arg2 u:1 NA (last use) REG NA $81 DefList: { N289.t394. CALL } N293 (???,???) [000923] -ACXG------- * STOREIND long REG NA LCL_VAR BB12 regmask=[allInt] minReg=1 last> BB12 regmask=[allInt] minReg=1 last> DefList: { } N295 ( 1, 1) [000397] ------------ * CNS_INT int 3 REG NA $48 Interval 93: int RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB12 regmask=[allInt] minReg=1> DefList: { N295.t397. CNS_INT } N297 ( 2, 2) [000521] ------------ * RETURN int REG NA $5ca BB12 regmask=[rax] minReg=1> BB12 regmask=[rax] minReg=1 last fixed> CHECKING LAST USES for BB12, liveout={} ============================== use: {V01 V02} def: {} NEW BLOCK BB13 Setting BB11 as the predecessor for determining incoming variable registers of BB13 DefList: { } N301 (???,???) [000924] ------------ * IL_OFFSET void IL offset: 0x7a REG NA DefList: { } N303 ( 3, 2) [000388] -------N---- * LCL_VAR_ADDR byref V11 loc8 NA * ref V11._bits (offs=0x00) -> V54 tmp24 * int V11._sign (offs=0x08) -> V55 tmp25 REG NA Interval 94: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB13 regmask=[allInt] minReg=1> DefList: { N303.t388. LCL_VAR_ADDR } N305 (???,???) [001024] ------------ * PUTARG_REG byref REG rcx BB13 regmask=[rcx] minReg=1> BB13 regmask=[rcx] minReg=1 last fixed> Interval 95: byref RefPositions {} physReg:NA Preferences=[allInt] BB13 regmask=[rcx] minReg=1> PUTARG_REG BB13 regmask=[rcx] minReg=1 fixed> DefList: { N305.t1024. PUTARG_REG } N307 ( 3, 2) [000390] ------------ * LCL_VAR int V05 loc2 u:2 NA (last use) REG NA $34e DefList: { N305.t1024. PUTARG_REG } N309 (???,???) [001025] ------------ * PUTARG_REG int REG rdx BB13 regmask=[rdx] minReg=1> LCL_VAR BB13 regmask=[rdx] minReg=1 last fixed> Interval 96: int RefPositions {} physReg:NA Preferences=[allInt] BB13 regmask=[rdx] minReg=1> PUTARG_REG BB13 regmask=[rdx] minReg=1 fixed> DefList: { N305.t1024. PUTARG_REG; N309.t1025. PUTARG_REG } N311 ( 20, 12) [000391] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen REG NA $VN.Void BB13 regmask=[rcx] minReg=1> BB13 regmask=[rcx] minReg=1 last fixed> BB13 regmask=[rdx] minReg=1> BB13 regmask=[rdx] minReg=1 last fixed> BB13 regmask=[rax] minReg=1> BB13 regmask=[rcx] minReg=1> BB13 regmask=[rdx] minReg=1> BB13 regmask=[r8] minReg=1> BB13 regmask=[r9] minReg=1> BB13 regmask=[r10] minReg=1> BB13 regmask=[r11] minReg=1> CHECKING LAST USES for BB13, liveout={V01 V02 V03 V08 V09 V10 V52 V53} ============================== use: {V05} def: {} NEW BLOCK BB14 Setting BB10 as the predecessor for determining incoming variable registers of BB14 DefList: { } N315 ( 3, 2) [000577] -------N---- * LCL_VAR_ADDR byref V76 tmp46 NA REG NA Interval 97: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB14 regmask=[allInt] minReg=1> DefList: { N315.t577. LCL_VAR_ADDR } N317 ( 3, 3) [000579] DA---------- * STORE_LCL_VAR byref V77 tmp47 d:2 NA REG NA BB14 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB14 regmask=[allInt] minReg=1 last> DefList: { } N319 ( 1, 1) [000580] ------------ * LCL_VAR byref V77 tmp47 u:2 NA Zero Fseq[_bits] REG NA $405 DefList: { } N321 ( 3, 2) [000582] -------N---- * LCL_VAR ref (AX) V54 tmp24 NA REG NA $181 Interval 98: ref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR BB14 regmask=[allInt] minReg=1> DefList: { N321.t582. LCL_VAR } N323 (???,???) [000925] -A--G------- * STOREIND ref REG NA LCL_VAR BB14 regmask=[allInt] minReg=1 last> BB14 regmask=[allInt] minReg=1 last> DefList: { } N325 ( 1, 1) [000585] ------------ * LCL_VAR byref V77 tmp47 u:2 NA (last use) REG NA $405 DefList: { } N327 ( 2, 2) [000587] -c---------- * LEA(b+8) byref REG NA Contained DefList: { } N329 ( 3, 2) [000589] -------N---- * LCL_VAR int (AX) V55 tmp25 NA REG NA $243 Interval 99: int RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR BB14 regmask=[allInt] minReg=1> DefList: { N329.t589. LCL_VAR } N331 (???,???) [000926] -A--G-----L- * STOREIND int REG NA LCL_VAR BB14 regmask=[allInt] minReg=1 last> BB14 regmask=[allInt] minReg=1 last> DefList: { } N333 ( 3, 2) [000592] -------N---- * LCL_VAR_ADDR byref V76 tmp46 NA REG NA Interval 100: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB14 regmask=[allInt] minReg=1> DefList: { N333.t592. LCL_VAR_ADDR } N335 (???,???) [001026] ------------ * PUTARG_REG byref REG rcx BB14 regmask=[rcx] minReg=1> BB14 regmask=[rcx] minReg=1 last fixed> Interval 101: byref RefPositions {} physReg:NA Preferences=[allInt] BB14 regmask=[rcx] minReg=1> PUTARG_REG BB14 regmask=[rcx] minReg=1 fixed> DefList: { N335.t1026. PUTARG_REG } N337 ( 3, 3) [000071] ------------ * LCL_VAR_ADDR long V12 loc9 NA REG NA $443 Interval 102: long RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB14 regmask=[allInt] minReg=1> DefList: { N335.t1026. PUTARG_REG; N337.t71. LCL_VAR_ADDR } N339 (???,???) [001027] ------------ * PUTARG_REG long REG rdx BB14 regmask=[rdx] minReg=1> BB14 regmask=[rdx] minReg=1 last fixed> Interval 103: long RefPositions {} physReg:NA Preferences=[allInt] BB14 regmask=[rdx] minReg=1> PUTARG_REG BB14 regmask=[rdx] minReg=1 fixed> DefList: { N335.t1026. PUTARG_REG; N339.t1027. PUTARG_REG } N341 ( 41, 28) [000072] --CXG------- * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits REG NA $293 BB14 regmask=[rcx] minReg=1> BB14 regmask=[rcx] minReg=1 last fixed> BB14 regmask=[rdx] minReg=1> BB14 regmask=[rdx] minReg=1 last fixed> BB14 regmask=[rax] minReg=1> BB14 regmask=[rcx] minReg=1> BB14 regmask=[rdx] minReg=1> BB14 regmask=[r8] minReg=1> BB14 regmask=[r9] minReg=1> BB14 regmask=[r10] minReg=1> BB14 regmask=[r11] minReg=1> Interval 104: int RefPositions {} physReg:NA Preferences=[allInt] BB14 regmask=[rax] minReg=1> CALL BB14 regmask=[rax] minReg=1 fixed> DefList: { N341.t72. CALL } N343 ( 41, 28) [000077] DA-XG------- * STORE_LCL_VAR int V13 loc10 d:2 NA REG NA BB14 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB14 regmask=[allInt] minReg=1 last> DefList: { } N345 (???,???) [000927] ------------ * IL_OFFSET void IL offset: 0x8d REG NA DefList: { } N347 ( 1, 1) [000078] ------------ * LCL_VAR int V13 loc10 u:2 NA REG NA $293 DefList: { } N349 ( 3, 2) [000079] ------------ * LCL_VAR int V03 loc0 u:2 NA REG NA $348 DefList: { } N351 ( 5, 4) [000080] N------N-U-- * GE void REG NA $353 LCL_VAR BB14 regmask=[allInt] minReg=1 last> LCL_VAR BB14 regmask=[allInt] minReg=1 last> DefList: { } N353 ( 7, 6) [000081] ------------ * JTRUE void REG NA CHECKING LAST USES for BB14, liveout={V01 V02 V03 V08 V09 V10 V13 V52 V53} ============================== use: {V03} def: {V13 V77} NEW BLOCK BB15 Setting BB14 as the predecessor for determining incoming variable registers of BB15 DefList: { } N357 (???,???) [000928] ------------ * IL_OFFSET void IL offset: 0x92 REG NA DefList: { } N359 ( 1, 1) [000091] ------------ * LCL_VAR int V10 loc7 u:2 NA REG NA DefList: { } N361 ( 1, 1) [000092] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { } N363 ( 3, 3) [000093] J------N---- * NE void REG NA LCL_VAR BB15 regmask=[allInt] minReg=1 last> DefList: { } N365 ( 5, 5) [000094] ------------ * JTRUE void REG NA CHECKING LAST USES for BB15, liveout={V01 V02 V03 V08 V09 V10 V13 V52 V53} ============================== use: {V10} def: {} NEW BLOCK BB16 Setting BB14 as the predecessor for determining incoming variable registers of BB16 DefList: { } N369 (???,???) [000929] ------------ * IL_OFFSET void IL offset: 0x96 REG NA DefList: { } N371 ( 1, 1) [000088] ------------ * LCL_VAR byref V02 arg2 u:1 NA (last use) REG NA $81 DefList: { } N373 (???,???) [001028] ------------ * PUTARG_STK [+0x20] void REG NA LCL_VAR BB16 regmask=[allInt] minReg=1 last> DefList: { } N375 ( 1, 1) [000084] ------------ * LCL_VAR int V10 loc7 u:2 NA (last use) REG NA DefList: { } N377 ( 1, 1) [000085] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { } N379 ( 6, 3) [000086] N----------- * NE int REG NA LCL_VAR BB16 regmask=[allInt] minReg=1 last> Interval 105: int RefPositions {} physReg:NA Preferences=[allInt] NE BB16 regmask=[allInt] minReg=1> DefList: { N379.t86. NE } N381 (???,???) [001029] ------------ * PUTARG_REG int REG r8 BB16 regmask=[r8] minReg=1> BB16 regmask=[r8] minReg=1 last fixed> Interval 106: int RefPositions {} physReg:NA Preferences=[allInt] BB16 regmask=[r8] minReg=1> PUTARG_REG BB16 regmask=[r8] minReg=1 fixed> DefList: { N381.t1029. PUTARG_REG } N383 ( 3, 2) [000082] ------------ * LCL_VAR ref (AX) V12 loc9 NA REG NA $18d Interval 107: ref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR BB16 regmask=[allInt] minReg=1> DefList: { N381.t1029. PUTARG_REG; N383.t82. LCL_VAR } N385 (???,???) [001030] ------------ * PUTARG_REG ref REG rcx BB16 regmask=[rcx] minReg=1> BB16 regmask=[rcx] minReg=1 last fixed> Interval 108: ref RefPositions {} physReg:NA Preferences=[allInt] BB16 regmask=[rcx] minReg=1> PUTARG_REG BB16 regmask=[rcx] minReg=1 fixed> DefList: { N381.t1029. PUTARG_REG; N385.t1030. PUTARG_REG } N387 ( 1, 1) [000083] ------------ * LCL_VAR int V13 loc10 u:2 NA (last use) REG NA $293 DefList: { N381.t1029. PUTARG_REG; N385.t1030. PUTARG_REG } N389 (???,???) [001031] ------------ * PUTARG_REG int REG rdx BB16 regmask=[rdx] minReg=1> LCL_VAR BB16 regmask=[rdx] minReg=1 last fixed> Interval 109: int RefPositions {} physReg:NA Preferences=[allInt] BB16 regmask=[rdx] minReg=1> PUTARG_REG BB16 regmask=[rdx] minReg=1 fixed> DefList: { N381.t1029. PUTARG_REG; N385.t1030. PUTARG_REG; N389.t1031. PUTARG_REG } N391 ( 1, 1) [000087] ------------ * LCL_VAR ref V01 arg1 u:1 NA (last use) REG NA $c0 DefList: { N381.t1029. PUTARG_REG; N385.t1030. PUTARG_REG; N389.t1031. PUTARG_REG } N393 (???,???) [001032] ------------ * PUTARG_REG ref REG r9 BB16 regmask=[r9] minReg=1> LCL_VAR BB16 regmask=[r9] minReg=1 last fixed> Interval 110: ref RefPositions {} physReg:NA Preferences=[allInt] BB16 regmask=[r9] minReg=1> PUTARG_REG BB16 regmask=[r9] minReg=1 fixed> DefList: { N381.t1029. PUTARG_REG; N385.t1030. PUTARG_REG; N389.t1031. PUTARG_REG; N393.t1032. PUTARG_REG } N395 ( 29, 17) [000089] --CXG------- * CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits REG NA $5c7 BB16 regmask=[r8] minReg=1> BB16 regmask=[r8] minReg=1 last fixed> BB16 regmask=[rcx] minReg=1> BB16 regmask=[rcx] minReg=1 last fixed> BB16 regmask=[rdx] minReg=1> BB16 regmask=[rdx] minReg=1 last fixed> BB16 regmask=[r9] minReg=1> BB16 regmask=[r9] minReg=1 last fixed> BB16 regmask=[rax] minReg=1> BB16 regmask=[rcx] minReg=1> BB16 regmask=[rdx] minReg=1> BB16 regmask=[r8] minReg=1> BB16 regmask=[r9] minReg=1> BB16 regmask=[r10] minReg=1> BB16 regmask=[r11] minReg=1> Interval 111: int RefPositions {} physReg:NA Preferences=[allInt] BB16 regmask=[rax] minReg=1> CALL BB16 regmask=[rax] minReg=1 fixed> DefList: { N395.t89. CALL } N397 ( 29, 17) [000600] DA-XG------- * STORE_LCL_VAR int V51 tmp21 d:3 NA REG NA BB16 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB16 regmask=[allInt] minReg=1 last> CHECKING LAST USES for BB16, liveout={V51} ============================== use: {V01 V02 V10 V13} def: {V51} NEW BLOCK BB17 Setting BB14 as the predecessor for determining incoming variable registers of BB17 DefList: { } N401 (???,???) [000930] ------------ * IL_OFFSET void IL offset: 0xa7 REG NA DefList: { } N403 ( 1, 1) [000097] ------------ * LCL_VAR int V53 tmp23 u:2 NA REG NA DefList: { } N405 ( 1, 1) [000098] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { } N407 ( 3, 3) [000099] J---G--N---- * LT void REG NA LCL_VAR BB17 regmask=[allInt] minReg=1 last> DefList: { } N409 ( 5, 5) [000100] ----G------- * JTRUE void REG NA CHECKING LAST USES for BB17, liveout={V01 V02 V03 V08 V09 V10 V13 V52 V53} ============================== use: {V53} def: {} NEW BLOCK BB18 Setting BB17 as the predecessor for determining incoming variable registers of BB18 DefList: { } N413 (???,???) [000931] ------------ * IL_OFFSET void IL offset: 0xb0 REG NA DefList: { } N415 ( 1, 1) [000376] ------------ * LCL_VAR int V10 loc7 u:2 NA (last use) REG NA DefList: { } N417 ( 5, 4) [000378] DA---------- * STORE_LCL_VAR int V32 tmp2 d:4 NA REG NA LCL_VAR BB18 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB18 regmask=[allInt] minReg=1 last> CHECKING LAST USES for BB18, liveout={V01 V02 V03 V08 V09 V13 V32 V52 V53} ============================== use: {V10} def: {V32} NEW BLOCK BB19 Setting BB17 as the predecessor for determining incoming variable registers of BB19 DefList: { } N421 (???,???) [000932] ------------ * IL_OFFSET void IL offset: 0xb4 REG NA DefList: { } N423 ( 1, 1) [000101] ------------ * LCL_VAR int V10 loc7 u:2 NA (last use) REG NA DefList: { } N425 ( 1, 1) [000104] ------------ * LCL_VAR int V53 tmp23 u:2 NA REG NA DefList: { } N427 ( 3, 3) [000106] ----G------- * SUB int REG NA LCL_VAR BB19 regmask=[allInt] minReg=1 last> LCL_VAR BB19 regmask=[allInt] minReg=1 last> Interval 112: int RefPositions {} physReg:NA Preferences=[allInt] SUB BB19 regmask=[allInt] minReg=1> Interval already has a related interval DefList: { N427.t106. SUB } N429 ( 7, 6) [000108] DA--G------- * STORE_LCL_VAR int V32 tmp2 d:3 NA REG NA BB19 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB19 regmask=[allInt] minReg=1 last> CHECKING LAST USES for BB19, liveout={V01 V02 V03 V08 V09 V13 V32 V52 V53} ============================== use: {V10 V53} def: {V32} NEW BLOCK BB20 Setting BB18 as the predecessor for determining incoming variable registers of BB20 DefList: { } N433 ( 3, 2) [000110] ------------ * LCL_VAR int V32 tmp2 u:2 NA (last use) REG NA $244 DefList: { } N435 ( 7, 5) [000112] DA---------- * STORE_LCL_VAR int V14 loc11 d:2 NA REG NA LCL_VAR BB20 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB20 regmask=[allInt] minReg=1 last> DefList: { } N437 (???,???) [000933] ------------ * IL_OFFSET void IL offset: 0xc0 REG NA DefList: { } N439 ( 1, 1) [000113] ------------ * LCL_VAR int V13 loc10 u:2 NA REG NA $293 DefList: { } N441 ( 1, 1) [000114] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { } N443 ( 3, 3) [000115] J------N---- * NE void REG NA $35a LCL_VAR BB20 regmask=[allInt] minReg=1 last> DefList: { } N445 ( 5, 5) [000116] ------------ * JTRUE void REG NA CHECKING LAST USES for BB20, liveout={V01 V02 V03 V08 V09 V13 V14 V52 V53} ============================== use: {V13 V32} def: {V14} NEW BLOCK BB21 Setting BB20 as the predecessor for determining incoming variable registers of BB21 DefList: { } N449 ( 1, 1) [000455] ------------ * LCL_VAR ref V52 tmp22 u:2 NA REG NA DefList: { } N451 (???,???) [000994] -c---------- * LEA(b+8) ref REG NA Contained DefList: { } N453 ( 3, 3) [000456] ---XG------- * IND int REG NA LCL_VAR BB21 regmask=[allInt] minReg=1 last> Interval 113: int RefPositions {} physReg:NA Preferences=[allInt] IND BB21 regmask=[allInt] minReg=1> DefList: { N453.t456. IND } N455 ( 4, 5) [000358] ---XG------- * CAST long <- int REG NA BB21 regmask=[allInt] minReg=1 last> Interval 114: long RefPositions {} physReg:NA Preferences=[allInt] CAST BB21 regmask=[allInt] minReg=1> DefList: { N455.t358. CAST } N457 ( 3, 2) [000352] ------------ * LCL_VAR int V14 loc11 u:2 NA REG NA $244 DefList: { N455.t358. CAST } N459 ( 4, 4) [000353] ---------U-- * CAST long <- ulong <- uint REG NA $486 LCL_VAR BB21 regmask=[allInt] minReg=1 last> Interval 115: long RefPositions {} physReg:NA Preferences=[allInt] CAST BB21 regmask=[allInt] minReg=1> DefList: { N455.t358. CAST; N459.t353. CAST } N461 ( 9, 10) [000359] ---XG------- * SUB long REG NA BB21 regmask=[allInt] minReg=1 last> BB21 regmask=[allInt] minReg=1 last> Interval 116: long RefPositions {} physReg:NA Preferences=[allInt] SUB BB21 regmask=[allInt] minReg=1> Assigning related to DefList: { N461.t359. SUB } N463 ( 13, 13) [000363] DA-XG------- * STORE_LCL_VAR long V38 tmp8 d:2 NA REG NA BB21 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB21 regmask=[allInt] minReg=1 last> DefList: { } N465 ( 1, 1) [000360] ------------ * LCL_VAR ref V01 arg1 u:1 NA REG NA $c0 DefList: { } N467 (???,???) [001033] ------------ * PUTARG_REG ref REG rcx BB21 regmask=[rcx] minReg=1> LCL_VAR BB21 regmask=[rcx] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 117: ref RefPositions {} physReg:NA Preferences=[allInt] BB21 regmask=[rcx] minReg=1> PUTARG_REG BB21 regmask=[rcx] minReg=1 fixed> Assigning related to DefList: { N467.t1033. PUTARG_REG } N469 ( 15, 8) [000361] --CXG------- * CALL int FloatingPointType.get_OverflowDecimalExponent REG NA $298 BB21 regmask=[rcx] minReg=1> BB21 regmask=[rcx] minReg=1 last fixed> BB21 regmask=[rax] minReg=1> BB21 regmask=[rcx] minReg=1> BB21 regmask=[rdx] minReg=1> BB21 regmask=[r8] minReg=1> BB21 regmask=[r9] minReg=1> BB21 regmask=[r10] minReg=1> BB21 regmask=[r11] minReg=1> Interval 118: int RefPositions {} physReg:NA Preferences=[allInt] BB21 regmask=[rax] minReg=1> CALL BB21 regmask=[rax] minReg=1 fixed> DefList: { N469.t361. CALL } N471 ( 16, 10) [000366] ---XG------- * CAST long <- int REG NA $48b BB21 regmask=[allInt] minReg=1 last> Interval 119: long RefPositions {} physReg:NA Preferences=[allInt] CAST BB21 regmask=[allInt] minReg=1> DefList: { N471.t366. CAST } N473 ( 3, 2) [000364] ------------ * LCL_VAR long V38 tmp8 u:2 NA (last use) REG NA DefList: { N471.t366. CAST } N475 ( 20, 13) [000367] J--XG--N---- * GE void REG NA BB21 regmask=[allInt] minReg=1 last> LCL_VAR BB21 regmask=[allInt] minReg=1 last> DefList: { } N477 ( 22, 15) [000368] ---XG------- * JTRUE void REG NA CHECKING LAST USES for BB21, liveout={V01 V02 V03 V08 V09 V13 V14 V52 V53} ============================== use: {V01 V14 V52} def: {V38} NEW BLOCK BB22 Setting BB21 as the predecessor for determining incoming variable registers of BB22 DefList: { } N481 (???,???) [000934] ------------ * IL_OFFSET void IL offset: 0xd9 REG NA DefList: { } N483 ( 1, 1) [000370] ------------ * LCL_VAR ref V01 arg1 u:1 NA REG NA $c0 DefList: { } N485 (???,???) [001034] ------------ * PUTARG_REG ref REG rcx BB22 regmask=[rcx] minReg=1> LCL_VAR BB22 regmask=[rcx] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 120: ref RefPositions {} physReg:NA Preferences=[allInt] BB22 regmask=[rcx] minReg=1> PUTARG_REG BB22 regmask=[rcx] minReg=1 fixed> Assigning related to DefList: { N485.t1034. PUTARG_REG } N487 ( 1, 1) [001035] ------------ * LCL_VAR ref V01 arg1 NA (last use) REG NA DefList: { N485.t1034. PUTARG_REG } N489 ( 2, 2) [001036] -c---------- * LEA(b+0) byref REG NA Contained DefList: { N485.t1034. PUTARG_REG } N491 ( 5, 4) [001037] ------------ * IND long REG NA LCL_VAR BB22 regmask=[allInt] minReg=1 last> Interval 121: long RefPositions {} physReg:NA Preferences=[allInt] IND BB22 regmask=[allInt] minReg=1> DefList: { N485.t1034. PUTARG_REG; N491.t1037. IND } N493 ( 6, 5) [001038] -c---------- * LEA(b+80) long REG NA Contained DefList: { N485.t1034. PUTARG_REG; N491.t1037. IND } N495 ( 9, 7) [001039] ------------ * IND long REG NA BB22 regmask=[allInt] minReg=1 last> Interval 122: long RefPositions {} physReg:NA Preferences=[allInt] IND BB22 regmask=[allInt] minReg=1> DefList: { N485.t1034. PUTARG_REG; N495.t1039. IND } N497 ( 10, 8) [001040] -c---------- * LEA(b+0) long REG NA Contained DefList: { N485.t1034. PUTARG_REG; N495.t1039. IND } N499 ( 13, 10) [001041] -c---------- * IND long REG NA Contained DefList: { N485.t1034. PUTARG_REG; N495.t1039. IND } N501 ( 21, 10) [000371] --CXG------- * CALLV ind long FloatingPointType.get_Zero REG NA $457 BB22 regmask=[rcx] minReg=1> BB22 regmask=[rcx] minReg=1 last fixed> BB22 regmask=[allInt] minReg=1 last> BB22 regmask=[rax] minReg=1> BB22 regmask=[rcx] minReg=1> BB22 regmask=[rdx] minReg=1> BB22 regmask=[r8] minReg=1> BB22 regmask=[r9] minReg=1> BB22 regmask=[r10] minReg=1> BB22 regmask=[r11] minReg=1> Interval 123: long RefPositions {} physReg:NA Preferences=[allInt] BB22 regmask=[rax] minReg=1> CALL BB22 regmask=[rax] minReg=1 fixed> DefList: { N501.t371. CALL } N503 ( 1, 1) [000369] ------------ * LCL_VAR byref V02 arg2 u:1 NA (last use) REG NA $81 DefList: { N501.t371. CALL } N505 (???,???) [000935] -ACXG------- * STOREIND long REG NA LCL_VAR BB22 regmask=[allInt] minReg=1 last> BB22 regmask=[allInt] minReg=1 last> DefList: { } N507 ( 1, 1) [000374] ------------ * CNS_INT int 2 REG NA $42 Interval 124: int RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB22 regmask=[allInt] minReg=1> DefList: { N507.t374. CNS_INT } N509 ( 2, 2) [000524] ------------ * RETURN int REG NA $5c4 BB22 regmask=[rax] minReg=1> BB22 regmask=[rax] minReg=1 last fixed> CHECKING LAST USES for BB22, liveout={} ============================== use: {V01 V02} def: {} NEW BLOCK BB23 Setting BB20 as the predecessor for determining incoming variable registers of BB23 DefList: { } N513 ( 3, 2) [000124] -------N---- * LCL_VAR_ADDR byref V15 loc12 NA * ref V15._bits (offs=0x00) -> V56 tmp26 * int V15._sign (offs=0x08) -> V57 tmp27 REG NA Interval 125: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB23 regmask=[allInt] minReg=1> DefList: { N513.t124. LCL_VAR_ADDR } N515 ( 7, 6) [000623] DA--------L- * STORE_LCL_VAR long V79 tmp49 d:2 NA REG NA BB23 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB23 regmask=[allInt] minReg=1 last> DefList: { } N517 ( 3, 2) [000607] -------N---- * LCL_VAR_ADDR byref V73 tmp43 NA REG NA Interval 126: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB23 regmask=[allInt] minReg=1> DefList: { N517.t607. LCL_VAR_ADDR } N519 ( 3, 3) [000609] DA---------- * STORE_LCL_VAR byref V78 tmp48 d:2 NA REG NA BB23 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB23 regmask=[allInt] minReg=1 last> DefList: { } N521 ( 1, 1) [000610] ------------ * LCL_VAR byref V78 tmp48 u:2 NA Zero Fseq[Mantissa] REG NA $409 DefList: { } N523 ( 1, 1) [000612] -------N---- * LCL_VAR ref V52 tmp22 u:2 NA (last use) REG NA DefList: { } N525 (???,???) [000936] -A---------- * STOREIND ref REG NA LCL_VAR BB23 regmask=[allInt] minReg=1 last> LCL_VAR BB23 regmask=[allInt] minReg=1 last> DefList: { } N527 ( 1, 1) [000615] ------------ * LCL_VAR byref V78 tmp48 u:2 NA (last use) REG NA $409 DefList: { } N529 ( 2, 2) [000617] -c---------- * LEA(b+8) byref REG NA Contained DefList: { } N531 ( 1, 1) [000619] -------N---- * LCL_VAR int V53 tmp23 u:2 NA (last use) REG NA DefList: { } N533 (???,???) [000937] -A--------L- * STOREIND int REG NA LCL_VAR BB23 regmask=[allInt] minReg=1 last> LCL_VAR BB23 regmask=[allInt] minReg=1 last> DefList: { } N535 ( 3, 2) [000624] ------------ * LCL_VAR long V79 tmp49 u:2 NA (last use) REG NA $408 DefList: { } N537 (???,???) [001042] ------------ * PUTARG_REG long REG rcx BB23 regmask=[rcx] minReg=1> LCL_VAR BB23 regmask=[rcx] minReg=1 last fixed> Interval 127: long RefPositions {} physReg:NA Preferences=[allInt] BB23 regmask=[rcx] minReg=1> PUTARG_REG BB23 regmask=[rcx] minReg=1 fixed> DefList: { N537.t1042. PUTARG_REG } N539 ( 3, 2) [000625] -------N---- * LCL_VAR_ADDR byref V73 tmp43 NA REG NA Interval 128: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB23 regmask=[allInt] minReg=1> DefList: { N537.t1042. PUTARG_REG; N539.t625. LCL_VAR_ADDR } N541 (???,???) [001043] ------------ * PUTARG_REG byref REG rdx BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last fixed> Interval 129: byref RefPositions {} physReg:NA Preferences=[allInt] BB23 regmask=[rdx] minReg=1> PUTARG_REG BB23 regmask=[rdx] minReg=1 fixed> DefList: { N537.t1042. PUTARG_REG; N541.t1043. PUTARG_REG } N543 ( 3, 2) [000118] ------------ * LCL_VAR int V08 loc5 u:2 NA (last use) REG NA $242 DefList: { N537.t1042. PUTARG_REG; N541.t1043. PUTARG_REG } N545 (???,???) [001044] ------------ * PUTARG_REG int REG r8 BB23 regmask=[r8] minReg=1> LCL_VAR BB23 regmask=[r8] minReg=1 last fixed> Interval 130: int RefPositions {} physReg:NA Preferences=[allInt] BB23 regmask=[r8] minReg=1> PUTARG_REG BB23 regmask=[r8] minReg=1 fixed> DefList: { N537.t1042. PUTARG_REG; N541.t1043. PUTARG_REG; N545.t1044. PUTARG_REG } N547 ( 3, 2) [000119] ------------ * LCL_VAR int V09 loc6 u:2 NA (last use) REG NA DefList: { N537.t1042. PUTARG_REG; N541.t1043. PUTARG_REG; N545.t1044. PUTARG_REG } N549 (???,???) [001045] ------------ * PUTARG_REG int REG r9 BB23 regmask=[r9] minReg=1> LCL_VAR BB23 regmask=[r9] minReg=1 last fixed> Interval 131: int RefPositions {} physReg:NA Preferences=[allInt] BB23 regmask=[r9] minReg=1> PUTARG_REG BB23 regmask=[r9] minReg=1 fixed> DefList: { N537.t1042. PUTARG_REG; N541.t1043. PUTARG_REG; N545.t1044. PUTARG_REG; N549.t1045. PUTARG_REG } N551 ( 53, 37) [000120] S-CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger REG NA $VN.Void BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last fixed> BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last fixed> BB23 regmask=[r8] minReg=1> BB23 regmask=[r8] minReg=1 last fixed> BB23 regmask=[r9] minReg=1> BB23 regmask=[r9] minReg=1 last fixed> BB23 regmask=[rax] minReg=1> BB23 regmask=[rcx] minReg=1> BB23 regmask=[rdx] minReg=1> BB23 regmask=[r8] minReg=1> BB23 regmask=[r9] minReg=1> BB23 regmask=[r10] minReg=1> BB23 regmask=[r11] minReg=1> DefList: { } N553 (???,???) [000938] ------------ * IL_OFFSET void IL offset: 0xef REG NA DefList: { } N555 ( 2, 10) [000131] ------------ * CNS_INT long 0x7ff815262aa0 REG NA $102 Interval 132: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB23 regmask=[allInt] minReg=1> DefList: { N555.t131. CNS_INT } N557 (???,???) [001046] ------------ * PUTARG_REG long REG rcx BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last fixed> Interval 133: long RefPositions {} physReg:NA Preferences=[allInt] BB23 regmask=[rcx] minReg=1> PUTARG_REG BB23 regmask=[rcx] minReg=1 fixed> DefList: { N557.t1046. PUTARG_REG } N559 ( 1, 4) [000132] ------------ * CNS_INT int 173 REG NA $58 Interval 134: int RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB23 regmask=[allInt] minReg=1> DefList: { N557.t1046. PUTARG_REG; N559.t132. CNS_INT } N561 (???,???) [001047] ------------ * PUTARG_REG int REG rdx BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last fixed> Interval 135: int RefPositions {} physReg:NA Preferences=[allInt] BB23 regmask=[rdx] minReg=1> PUTARG_REG BB23 regmask=[rdx] minReg=1 fixed> DefList: { N557.t1046. PUTARG_REG; N561.t1047. PUTARG_REG } N563 ( 17, 21) [000133] H-CXG------- * CALL help long HELPER.CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE REG NA $48d BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last fixed> BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last fixed> BB23 regmask=[rax] minReg=1> BB23 regmask=[rcx] minReg=1> BB23 regmask=[rdx] minReg=1> BB23 regmask=[r8] minReg=1> BB23 regmask=[r9] minReg=1> BB23 regmask=[r10] minReg=1> BB23 regmask=[r11] minReg=1> Interval 136: long RefPositions {} physReg:NA Preferences=[allInt] BB23 regmask=[rax] minReg=1> CALL BB23 regmask=[rax] minReg=1 fixed> DefList: { } N565 ( 2, 10) [000634] I----------- * CNS_INT(h) long 0xd1ffab1e static Fseq[BigOne] REG NA $4c2 Interval 137: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB23 regmask=[allInt] minReg=1> DefList: { N565.t634. CNS_INT } N567 ( 4, 12) [000633] n---G------- * IND ref REG NA BB23 regmask=[allInt] minReg=1 last> Interval 138: ref RefPositions {} physReg:NA Preferences=[allInt] IND BB23 regmask=[allInt] minReg=1> DefList: { N567.t633. IND } N569 ( 1, 1) [000635] -c---------- * CNS_INT long 8 Fseq[#FirstElem] REG NA $101 Contained DefList: { N567.t633. IND } N571 ( 6, 14) [000632] ----G------- * ADD byref REG NA BB23 regmask=[allInt] minReg=1 last> Interval 139: byref RefPositions {} physReg:NA Preferences=[allInt] ADD BB23 regmask=[allInt] minReg=1> Assigning related to DefList: { N571.t632. ADD } N573 ( 6, 14) [000637] DA--G------- * STORE_LCL_VAR byref V80 tmp50 d:2 NA REG NA BB23 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB23 regmask=[allInt] minReg=1 last> DefList: { } N575 ( 1, 1) [000639] ------------ * LCL_VAR byref V80 tmp50 u:2 NA Zero Fseq[_bits] REG NA DefList: { } N577 ( 3, 2) [000640] ---X-------- * IND ref REG NA LCL_VAR BB23 regmask=[allInt] minReg=1 last> Interval 140: ref RefPositions {} physReg:NA Preferences=[allInt] IND BB23 regmask=[allInt] minReg=1> DefList: { N577.t640. IND } N579 ( 7, 5) [000641] DA-XG------- * STORE_LCL_VAR ref (AX) V58 tmp28 NA REG NA BB23 regmask=[allInt] minReg=1 last> DefList: { } N581 ( 1, 1) [000644] ------------ * LCL_VAR byref V80 tmp50 u:2 NA (last use) REG NA DefList: { } N583 ( 2, 2) [000646] -c---------- * LEA(b+8) byref REG NA Contained DefList: { } N585 ( 4, 4) [000647] ---X-------- * IND int REG NA LCL_VAR BB23 regmask=[allInt] minReg=1 last> Interval 141: int RefPositions {} physReg:NA Preferences=[allInt] IND BB23 regmask=[allInt] minReg=1> DefList: { N585.t647. IND } N587 ( 8, 7) [000648] DA-XG------- * STORE_LCL_VAR int (AX) V59 tmp29 NA REG NA BB23 regmask=[allInt] minReg=1 last> DefList: { } N589 (???,???) [000939] ------------ * IL_OFFSET void IL offset: 0xf6 REG NA DefList: { } N591 ( 3, 2) [000138] -------N---- * LCL_VAR_ADDR byref V16 loc13 NA * ref V16._bits (offs=0x00) -> V58 tmp28 * int V16._sign (offs=0x08) -> V59 tmp29 REG NA Interval 142: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB23 regmask=[allInt] minReg=1> DefList: { N591.t138. LCL_VAR_ADDR } N593 (???,???) [001048] ------------ * PUTARG_REG byref REG rcx BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last fixed> Interval 143: byref RefPositions {} physReg:NA Preferences=[allInt] BB23 regmask=[rcx] minReg=1> PUTARG_REG BB23 regmask=[rcx] minReg=1 fixed> DefList: { N593.t1048. PUTARG_REG } N595 ( 3, 2) [000140] ------------ * LCL_VAR int V14 loc11 u:2 NA (last use) REG NA $244 DefList: { N593.t1048. PUTARG_REG } N597 (???,???) [001049] ------------ * PUTARG_REG int REG rdx BB23 regmask=[rdx] minReg=1> LCL_VAR BB23 regmask=[rdx] minReg=1 last fixed> Interval 144: int RefPositions {} physReg:NA Preferences=[allInt] BB23 regmask=[rdx] minReg=1> PUTARG_REG BB23 regmask=[rdx] minReg=1 fixed> DefList: { N593.t1048. PUTARG_REG; N597.t1049. PUTARG_REG } N599 ( 20, 12) [000141] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen REG NA $VN.Void BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last fixed> BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last fixed> BB23 regmask=[rax] minReg=1> BB23 regmask=[rcx] minReg=1> BB23 regmask=[rdx] minReg=1> BB23 regmask=[r8] minReg=1> BB23 regmask=[r9] minReg=1> BB23 regmask=[r10] minReg=1> BB23 regmask=[r11] minReg=1> DefList: { } N601 (???,???) [000940] ------------ * IL_OFFSET void IL offset: 0xff REG NA DefList: { } N603 ( 3, 2) [000653] -------N---- * LCL_VAR ref (AX) V56 tmp26 NA REG NA $184 Interval 145: ref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR BB23 regmask=[allInt] minReg=1> DefList: { N603.t653. LCL_VAR } N605 ( 7, 5) [000654] DA--G------- * STORE_LCL_VAR ref V64 tmp34 d:2 NA REG NA BB23 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB23 regmask=[allInt] minReg=1 last> DefList: { } N607 ( 3, 2) [000656] -------N---- * LCL_VAR int (AX) V57 tmp27 NA REG NA $246 Interval 146: int RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR BB23 regmask=[allInt] minReg=1> DefList: { N607.t656. LCL_VAR } N609 ( 7, 5) [000657] DA--G------- * STORE_LCL_VAR int V65 tmp35 d:2 NA REG NA BB23 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB23 regmask=[allInt] minReg=1 last> DefList: { } N611 (???,???) [000941] ------------ * IL_OFFSET void IL offset: 0xff REG NA DefList: { } N613 ( 3, 2) [000663] -------N---- * LCL_VAR_ADDR byref V76 tmp46 NA REG NA Interval 147: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB23 regmask=[allInt] minReg=1> DefList: { N613.t663. LCL_VAR_ADDR } N615 ( 3, 3) [000665] DA---------- * STORE_LCL_VAR byref V81 tmp51 d:2 NA REG NA BB23 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB23 regmask=[allInt] minReg=1 last> DefList: { } N617 ( 1, 1) [000666] ------------ * LCL_VAR byref V81 tmp51 u:2 NA Zero Fseq[_bits] REG NA $40e DefList: { } N619 ( 3, 2) [000668] -------N---- * LCL_VAR ref V64 tmp34 u:2 NA (last use) REG NA $184 DefList: { } N621 (???,???) [000942] -A---------- * STOREIND ref REG NA LCL_VAR BB23 regmask=[allInt] minReg=1 last> LCL_VAR BB23 regmask=[allInt] minReg=1 last> DefList: { } N623 ( 1, 1) [000671] ------------ * LCL_VAR byref V81 tmp51 u:2 NA (last use) REG NA $40e DefList: { } N625 ( 2, 2) [000673] -c---------- * LEA(b+8) byref REG NA Contained DefList: { } N627 ( 3, 2) [000675] -------N---- * LCL_VAR int V65 tmp35 u:2 NA (last use) REG NA $246 DefList: { } N629 (???,???) [000943] -A--------L- * STOREIND int REG NA LCL_VAR BB23 regmask=[allInt] minReg=1 last> LCL_VAR BB23 regmask=[allInt] minReg=1 last> DefList: { } N631 ( 3, 2) [000678] -------N---- * LCL_VAR_ADDR byref V76 tmp46 NA REG NA Interval 148: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB23 regmask=[allInt] minReg=1> DefList: { N631.t678. LCL_VAR_ADDR } N633 (???,???) [001050] ------------ * PUTARG_REG byref REG rcx BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last fixed> Interval 149: byref RefPositions {} physReg:NA Preferences=[allInt] BB23 regmask=[rcx] minReg=1> PUTARG_REG BB23 regmask=[rcx] minReg=1 fixed> DefList: { N633.t1050. PUTARG_REG } N635 ( 3, 3) [000462] ------------ * LCL_VAR_ADDR long V45 tmp15 NA REG NA $449 Interval 150: long RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB23 regmask=[allInt] minReg=1> DefList: { N633.t1050. PUTARG_REG; N635.t462. LCL_VAR_ADDR } N637 (???,???) [001051] ------------ * PUTARG_REG long REG rdx BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last fixed> Interval 151: long RefPositions {} physReg:NA Preferences=[allInt] BB23 regmask=[rdx] minReg=1> PUTARG_REG BB23 regmask=[rdx] minReg=1 fixed> DefList: { N633.t1050. PUTARG_REG; N637.t1051. PUTARG_REG } N639 ( 41, 28) [000463] --CXG------- * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits REG NA $29f BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last fixed> BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last fixed> BB23 regmask=[rax] minReg=1> BB23 regmask=[rcx] minReg=1> BB23 regmask=[rdx] minReg=1> BB23 regmask=[r8] minReg=1> BB23 regmask=[r9] minReg=1> BB23 regmask=[r10] minReg=1> BB23 regmask=[r11] minReg=1> Interval 152: int RefPositions {} physReg:NA Preferences=[allInt] BB23 regmask=[rax] minReg=1> CALL BB23 regmask=[rax] minReg=1 fixed> DefList: { N639.t463. CALL } N641 ( 45, 31) [000468] DA-XG------- * STORE_LCL_VAR int V43 tmp13 d:2 NA REG NA BB23 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB23 regmask=[allInt] minReg=1 last> DefList: { } N643 (???,???) [000944] ------------ * IL_OFFSET void IL offset: 0xff REG NA DefList: { } N645 ( 1, 1) [000473] ------------ * CNS_INT ref null REG NA $VN.Null Interval 153: ref RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB23 regmask=[allInt] minReg=1> DefList: { N645.t473. CNS_INT } N647 ( 5, 4) [000475] DA--G------- * STORE_LCL_VAR ref (AX) V45 tmp15 NA REG NA BB23 regmask=[allInt] minReg=1 last> DefList: { } N649 ( 3, 2) [000469] ------------ * LCL_VAR int V43 tmp13 u:2 NA (last use) REG NA $29f DefList: { } N651 ( 7, 5) [000148] DA---------- * STORE_LCL_VAR int V17 loc14 d:2 NA REG NA LCL_VAR BB23 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB23 regmask=[allInt] minReg=1 last> DefList: { } N653 (???,???) [000945] ------------ * IL_OFFSET void IL offset: 0x108 REG NA DefList: { } N655 ( 3, 2) [000682] -------N---- * LCL_VAR ref (AX) V58 tmp28 NA REG NA $185 Interval 154: ref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR BB23 regmask=[allInt] minReg=1> DefList: { N655.t682. LCL_VAR } N657 ( 7, 5) [000683] DA--G------- * STORE_LCL_VAR ref V66 tmp36 d:2 NA REG NA BB23 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB23 regmask=[allInt] minReg=1 last> DefList: { } N659 ( 3, 2) [000685] -------N---- * LCL_VAR int (AX) V59 tmp29 NA REG NA $247 Interval 155: int RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR BB23 regmask=[allInt] minReg=1> DefList: { N659.t685. LCL_VAR } N661 ( 7, 5) [000686] DA--G------- * STORE_LCL_VAR int V67 tmp37 d:2 NA REG NA BB23 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB23 regmask=[allInt] minReg=1 last> DefList: { } N663 (???,???) [000946] ------------ * IL_OFFSET void IL offset: 0x108 REG NA DefList: { } N665 ( 3, 2) [000692] -------N---- * LCL_VAR_ADDR byref V76 tmp46 NA REG NA Interval 156: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB23 regmask=[allInt] minReg=1> DefList: { N665.t692. LCL_VAR_ADDR } N667 ( 3, 3) [000694] DA---------- * STORE_LCL_VAR byref V82 tmp52 d:2 NA REG NA BB23 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB23 regmask=[allInt] minReg=1 last> DefList: { } N669 ( 1, 1) [000695] ------------ * LCL_VAR byref V82 tmp52 u:2 NA Zero Fseq[_bits] REG NA $411 DefList: { } N671 ( 3, 2) [000697] -------N---- * LCL_VAR ref V66 tmp36 u:2 NA (last use) REG NA $185 DefList: { } N673 (???,???) [000947] -A---------- * STOREIND ref REG NA LCL_VAR BB23 regmask=[allInt] minReg=1 last> LCL_VAR BB23 regmask=[allInt] minReg=1 last> DefList: { } N675 ( 1, 1) [000700] ------------ * LCL_VAR byref V82 tmp52 u:2 NA (last use) REG NA $411 DefList: { } N677 ( 2, 2) [000702] -c---------- * LEA(b+8) byref REG NA Contained DefList: { } N679 ( 3, 2) [000704] -------N---- * LCL_VAR int V67 tmp37 u:2 NA (last use) REG NA $247 DefList: { } N681 (???,???) [000948] -A--------L- * STOREIND int REG NA LCL_VAR BB23 regmask=[allInt] minReg=1 last> LCL_VAR BB23 regmask=[allInt] minReg=1 last> DefList: { } N683 ( 3, 2) [000707] -------N---- * LCL_VAR_ADDR byref V76 tmp46 NA REG NA Interval 157: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB23 regmask=[allInt] minReg=1> DefList: { N683.t707. LCL_VAR_ADDR } N685 (???,???) [001052] ------------ * PUTARG_REG byref REG rcx BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last fixed> Interval 158: byref RefPositions {} physReg:NA Preferences=[allInt] BB23 regmask=[rcx] minReg=1> PUTARG_REG BB23 regmask=[rcx] minReg=1 fixed> DefList: { N685.t1052. PUTARG_REG } N687 ( 3, 3) [000480] ------------ * LCL_VAR_ADDR long V48 tmp18 NA REG NA $44b Interval 159: long RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB23 regmask=[allInt] minReg=1> DefList: { N685.t1052. PUTARG_REG; N687.t480. LCL_VAR_ADDR } N689 (???,???) [001053] ------------ * PUTARG_REG long REG rdx BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last fixed> Interval 160: long RefPositions {} physReg:NA Preferences=[allInt] BB23 regmask=[rdx] minReg=1> PUTARG_REG BB23 regmask=[rdx] minReg=1 fixed> DefList: { N685.t1052. PUTARG_REG; N689.t1053. PUTARG_REG } N691 ( 41, 28) [000481] --CXG------- * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits REG NA $2a3 BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last fixed> BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last fixed> BB23 regmask=[rax] minReg=1> BB23 regmask=[rcx] minReg=1> BB23 regmask=[rdx] minReg=1> BB23 regmask=[r8] minReg=1> BB23 regmask=[r9] minReg=1> BB23 regmask=[r10] minReg=1> BB23 regmask=[r11] minReg=1> Interval 161: int RefPositions {} physReg:NA Preferences=[allInt] BB23 regmask=[rax] minReg=1> CALL BB23 regmask=[rax] minReg=1 fixed> DefList: { N691.t481. CALL } N693 ( 45, 31) [000486] DA-XG------- * STORE_LCL_VAR int V46 tmp16 d:2 NA REG NA BB23 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB23 regmask=[allInt] minReg=1 last> DefList: { } N695 (???,???) [000949] ------------ * IL_OFFSET void IL offset: 0x108 REG NA DefList: { } N697 ( 1, 1) [000491] ------------ * CNS_INT ref null REG NA $VN.Null Interval 162: ref RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB23 regmask=[allInt] minReg=1> DefList: { N697.t491. CNS_INT } N699 ( 5, 4) [000493] DA--G------- * STORE_LCL_VAR ref (AX) V48 tmp18 NA REG NA BB23 regmask=[allInt] minReg=1 last> DefList: { } N701 ( 3, 2) [000487] ------------ * LCL_VAR int V46 tmp16 u:2 NA (last use) REG NA $2a3 DefList: { } N703 ( 7, 5) [000155] DA---------- * STORE_LCL_VAR int V18 loc15 d:2 NA REG NA LCL_VAR BB23 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB23 regmask=[allInt] minReg=1 last> DefList: { } N705 (???,???) [000950] ------------ * IL_OFFSET void IL offset: 0x111 REG NA DefList: { } N707 ( 3, 2) [000156] ------------ * LCL_VAR int V18 loc15 u:2 NA REG NA $2a3 DefList: { } N709 ( 3, 2) [000157] ------------ * LCL_VAR int V17 loc14 u:2 NA REG NA $29f DefList: { } N711 ( 7, 5) [000158] N------N-U-- * GT void REG NA $35f LCL_VAR BB23 regmask=[allInt] minReg=1 last> LCL_VAR BB23 regmask=[allInt] minReg=1 last> DefList: { } N713 ( 9, 7) [000159] ------------ * JTRUE void REG NA CHECKING LAST USES for BB23, liveout={V01 V02 V03 V13 V17 V18} ============================== use: {V08 V09 V14 V52 V53} def: {V17 V18 V43 V46 V64 V65 V66 V67 V78 V79 V80 V81 V82} NEW BLOCK BB24 Setting BB23 as the predecessor for determining incoming variable registers of BB24 DefList: { } N717 (???,???) [000951] ------------ * IL_OFFSET void IL offset: 0x117 REG NA DefList: { } N719 ( 1, 1) [000348] ------------ * CNS_INT int 0 REG NA $40 Interval 163: int RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB24 regmask=[allInt] minReg=1> DefList: { N719.t348. CNS_INT } N721 ( 5, 4) [000350] DA---------- * STORE_LCL_VAR int V33 tmp3 d:4 NA REG NA BB24 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB24 regmask=[allInt] minReg=1 last> CHECKING LAST USES for BB24, liveout={V01 V02 V03 V13 V33} ============================== use: {} def: {V33} NEW BLOCK BB25 Setting BB23 as the predecessor for determining incoming variable registers of BB25 DefList: { } N725 (???,???) [000952] ------------ * IL_OFFSET void IL offset: 0x11a REG NA DefList: { } N727 ( 3, 2) [000160] ------------ * LCL_VAR int V18 loc15 u:2 NA (last use) REG NA $2a3 DefList: { } N729 ( 3, 2) [000161] ------------ * LCL_VAR int V17 loc14 u:2 NA (last use) REG NA $29f DefList: { } N731 ( 7, 5) [000162] ------------ * SUB int REG NA $360 LCL_VAR BB25 regmask=[allInt] minReg=1 last> LCL_VAR BB25 regmask=[allInt] minReg=1 last> Interval 164: int RefPositions {} physReg:NA Preferences=[allInt] SUB BB25 regmask=[allInt] minReg=1> Assigning related to DefList: { N731.t162. SUB } N733 ( 11, 8) [000164] DA---------- * STORE_LCL_VAR int V33 tmp3 d:3 NA REG NA BB25 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB25 regmask=[allInt] minReg=1 last> CHECKING LAST USES for BB25, liveout={V01 V02 V03 V13 V33} ============================== use: {V17 V18} def: {V33} NEW BLOCK BB26 Setting BB24 as the predecessor for determining incoming variable registers of BB26 DefList: { } N737 ( 3, 2) [000166] ------------ * LCL_VAR int V33 tmp3 u:2 NA (last use) REG NA $248 DefList: { } N739 ( 3, 3) [000168] DA---------- * STORE_LCL_VAR int V19 loc16 d:2 NA REG NA LCL_VAR BB26 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB26 regmask=[allInt] minReg=1 last> DefList: { } N741 (???,???) [000953] ------------ * IL_OFFSET void IL offset: 0x121 REG NA DefList: { } N743 ( 3, 2) [000169] ------------ * LCL_VAR int V19 loc16 u:2 NA REG NA $248 DefList: { } N745 ( 1, 1) [000170] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { } N747 ( 5, 4) [000171] N------N---- * EQ void REG NA $361 LCL_VAR BB26 regmask=[allInt] minReg=1 last> DefList: { } N749 ( 7, 6) [000172] ------------ * JTRUE void REG NA CHECKING LAST USES for BB26, liveout={V01 V02 V03 V13 V19} ============================== use: {V33} def: {V19} NEW BLOCK BB27 Setting BB26 as the predecessor for determining incoming variable registers of BB27 DefList: { } N753 (???,???) [000954] ------------ * IL_OFFSET void IL offset: 0x126 REG NA DefList: { } N755 ( 3, 2) [000344] -------N---- * LCL_VAR_ADDR byref V15 loc12 NA * ref V15._bits (offs=0x00) -> V56 tmp26 * int V15._sign (offs=0x08) -> V57 tmp27 REG NA Interval 165: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB27 regmask=[allInt] minReg=1> DefList: { N755.t344. LCL_VAR_ADDR } N757 (???,???) [001054] ------------ * PUTARG_REG byref REG rcx BB27 regmask=[rcx] minReg=1> BB27 regmask=[rcx] minReg=1 last fixed> Interval 166: byref RefPositions {} physReg:NA Preferences=[allInt] BB27 regmask=[rcx] minReg=1> PUTARG_REG BB27 regmask=[rcx] minReg=1 fixed> DefList: { N757.t1054. PUTARG_REG } N759 ( 1, 1) [000346] ------------ * LCL_VAR int V19 loc16 u:2 NA REG NA $248 DefList: { N757.t1054. PUTARG_REG } N761 (???,???) [001055] ------------ * PUTARG_REG int REG rdx BB27 regmask=[rdx] minReg=1> LCL_VAR BB27 regmask=[rdx] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 167: int RefPositions {} physReg:NA Preferences=[allInt] BB27 regmask=[rdx] minReg=1> PUTARG_REG BB27 regmask=[rdx] minReg=1 fixed> Assigning related to DefList: { N757.t1054. PUTARG_REG; N761.t1055. PUTARG_REG } N763 ( 18, 11) [000347] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft REG NA $VN.Void BB27 regmask=[rcx] minReg=1> BB27 regmask=[rcx] minReg=1 last fixed> BB27 regmask=[rdx] minReg=1> BB27 regmask=[rdx] minReg=1 last fixed> BB27 regmask=[rax] minReg=1> BB27 regmask=[rcx] minReg=1> BB27 regmask=[rdx] minReg=1> BB27 regmask=[r8] minReg=1> BB27 regmask=[r9] minReg=1> BB27 regmask=[r10] minReg=1> BB27 regmask=[r11] minReg=1> CHECKING LAST USES for BB27, liveout={V01 V02 V03 V13 V19} ============================== use: {V19} def: {} NEW BLOCK BB28 Setting BB26 as the predecessor for determining incoming variable registers of BB28 DefList: { } N767 (???,???) [000955] ------------ * IL_OFFSET void IL offset: 0x12f REG NA DefList: { } N769 ( 3, 2) [000173] ------------ * LCL_VAR int V03 loc0 u:2 NA (last use) REG NA $348 DefList: { } N771 ( 1, 1) [000174] ------------ * LCL_VAR int V13 loc10 u:2 NA REG NA $293 DefList: { } N773 ( 5, 4) [000175] ------------ * SUB int REG NA $362 LCL_VAR BB28 regmask=[allInt] minReg=1 last> LCL_VAR BB28 regmask=[allInt] minReg=1 last> Interval 168: int RefPositions {} physReg:NA Preferences=[allInt] SUB BB28 regmask=[allInt] minReg=1> Assigning related to DefList: { N773.t175. SUB } N775 ( 9, 7) [000177] DA---------- * STORE_LCL_VAR int V20 loc17 d:2 NA REG NA BB28 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB28 regmask=[allInt] minReg=1 last> DefList: { } N777 (???,???) [000956] ------------ * IL_OFFSET void IL offset: 0x135 REG NA DefList: { } N779 ( 3, 2) [000178] ------------ * LCL_VAR int V20 loc17 u:2 NA REG NA $362 DefList: { } N781 ( 7, 5) [000180] DA---------- * STORE_LCL_VAR int V21 loc18 d:2 NA REG NA LCL_VAR BB28 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB28 regmask=[allInt] minReg=1 last> DefList: { } N783 (???,???) [000957] ------------ * IL_OFFSET void IL offset: 0x139 REG NA DefList: { } N785 ( 1, 1) [000181] ------------ * LCL_VAR int V13 loc10 u:2 NA REG NA $293 DefList: { } N787 ( 1, 1) [000182] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { } N789 ( 3, 3) [000183] N------N---- * EQ void REG NA $363 LCL_VAR BB28 regmask=[allInt] minReg=1 last> DefList: { } N791 ( 5, 5) [000184] ------------ * JTRUE void REG NA CHECKING LAST USES for BB28, liveout={V01 V02 V13 V19 V20 V21} ============================== use: {V03 V13} def: {V20 V21} NEW BLOCK BB29 Setting BB28 as the predecessor for determining incoming variable registers of BB29 DefList: { } N795 (???,???) [000958] ------------ * IL_OFFSET void IL offset: 0x13e REG NA DefList: { } N797 ( 1, 1) [000326] ------------ * LCL_VAR int V19 loc16 u:2 NA REG NA $248 DefList: { } N799 ( 3, 2) [000327] ------------ * LCL_VAR int V20 loc17 u:2 NA REG NA $362 DefList: { } N801 ( 5, 4) [000328] N------N-U-- * LE void REG NA $364 LCL_VAR BB29 regmask=[allInt] minReg=1 last> LCL_VAR BB29 regmask=[allInt] minReg=1 last> DefList: { } N803 ( 7, 6) [000329] ------------ * JTRUE void REG NA CHECKING LAST USES for BB29, liveout={V01 V02 V13 V19 V20} ============================== use: {V19 V20} def: {} NEW BLOCK BB30 Setting BB29 as the predecessor for determining incoming variable registers of BB30 DefList: { } N807 (???,???) [000959] ------------ * IL_OFFSET void IL offset: 0x144 REG NA DefList: { } N809 ( 1, 1) [000341] ------------ * LCL_VAR byref V02 arg2 u:1 NA (last use) REG NA $81 DefList: { } N811 (???,???) [001056] ------------ * PUTARG_STK [+0x20] void REG NA LCL_VAR BB30 regmask=[allInt] minReg=1 last> DefList: { } N813 ( 1, 1) [000339] ------------ * CNS_INT int 1 REG NA $41 Interval 169: int RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB30 regmask=[allInt] minReg=1> DefList: { N813.t339. CNS_INT } N815 (???,???) [001057] ------------ * PUTARG_REG int REG r8 BB30 regmask=[r8] minReg=1> BB30 regmask=[r8] minReg=1 last fixed> Interval 170: int RefPositions {} physReg:NA Preferences=[allInt] BB30 regmask=[r8] minReg=1> PUTARG_REG BB30 regmask=[r8] minReg=1 fixed> DefList: { N815.t1057. PUTARG_REG } N817 ( 3, 2) [000335] ------------ * LCL_VAR ref (AX) V12 loc9 NA REG NA $18c Interval 171: ref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR BB30 regmask=[allInt] minReg=1> DefList: { N815.t1057. PUTARG_REG; N817.t335. LCL_VAR } N819 (???,???) [001058] ------------ * PUTARG_REG ref REG rcx BB30 regmask=[rcx] minReg=1> BB30 regmask=[rcx] minReg=1 last fixed> Interval 172: ref RefPositions {} physReg:NA Preferences=[allInt] BB30 regmask=[rcx] minReg=1> PUTARG_REG BB30 regmask=[rcx] minReg=1 fixed> DefList: { N815.t1057. PUTARG_REG; N819.t1058. PUTARG_REG } N821 ( 1, 1) [000336] ------------ * LCL_VAR int V13 loc10 u:2 NA (last use) REG NA $293 DefList: { N815.t1057. PUTARG_REG; N819.t1058. PUTARG_REG } N823 (???,???) [001059] ------------ * PUTARG_REG int REG rdx BB30 regmask=[rdx] minReg=1> LCL_VAR BB30 regmask=[rdx] minReg=1 last fixed> Interval 173: int RefPositions {} physReg:NA Preferences=[allInt] BB30 regmask=[rdx] minReg=1> PUTARG_REG BB30 regmask=[rdx] minReg=1 fixed> DefList: { N815.t1057. PUTARG_REG; N819.t1058. PUTARG_REG; N823.t1059. PUTARG_REG } N825 ( 1, 1) [000340] ------------ * LCL_VAR ref V01 arg1 u:1 NA (last use) REG NA $c0 DefList: { N815.t1057. PUTARG_REG; N819.t1058. PUTARG_REG; N823.t1059. PUTARG_REG } N827 (???,???) [001060] ------------ * PUTARG_REG ref REG r9 BB30 regmask=[r9] minReg=1> LCL_VAR BB30 regmask=[r9] minReg=1 last fixed> Interval 174: ref RefPositions {} physReg:NA Preferences=[allInt] BB30 regmask=[r9] minReg=1> PUTARG_REG BB30 regmask=[r9] minReg=1 fixed> DefList: { N815.t1057. PUTARG_REG; N819.t1058. PUTARG_REG; N823.t1059. PUTARG_REG; N827.t1060. PUTARG_REG } N829 ( 24, 15) [000342] --CXG------- * CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits REG NA $5c2 BB30 regmask=[r8] minReg=1> BB30 regmask=[r8] minReg=1 last fixed> BB30 regmask=[rcx] minReg=1> BB30 regmask=[rcx] minReg=1 last fixed> BB30 regmask=[rdx] minReg=1> BB30 regmask=[rdx] minReg=1 last fixed> BB30 regmask=[r9] minReg=1> BB30 regmask=[r9] minReg=1 last fixed> BB30 regmask=[rax] minReg=1> BB30 regmask=[rcx] minReg=1> BB30 regmask=[rdx] minReg=1> BB30 regmask=[r8] minReg=1> BB30 regmask=[r9] minReg=1> BB30 regmask=[r10] minReg=1> BB30 regmask=[r11] minReg=1> Interval 175: int RefPositions {} physReg:NA Preferences=[allInt] BB30 regmask=[rax] minReg=1> CALL BB30 regmask=[rax] minReg=1 fixed> DefList: { N829.t342. CALL } N831 ( 24, 15) [000717] DA-XG------- * STORE_LCL_VAR int V51 tmp21 d:5 NA REG NA BB30 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB30 regmask=[allInt] minReg=1 last> CHECKING LAST USES for BB30, liveout={V51} ============================== use: {V01 V02 V13} def: {V51} NEW BLOCK BB31 Setting BB29 as the predecessor for determining incoming variable registers of BB31 DefList: { } N835 (???,???) [000960] ------------ * IL_OFFSET void IL offset: 0x155 REG NA DefList: { } N837 ( 3, 2) [000330] ------------ * LCL_VAR int V20 loc17 u:2 NA REG NA $362 DefList: { } N839 ( 1, 1) [000331] ------------ * LCL_VAR int V19 loc16 u:2 NA REG NA $248 DefList: { } N841 ( 5, 4) [000332] ------------ * SUB int REG NA $365 LCL_VAR BB31 regmask=[allInt] minReg=1 last> LCL_VAR BB31 regmask=[allInt] minReg=1 last> Interval 176: int RefPositions {} physReg:NA Preferences=[allInt] SUB BB31 regmask=[allInt] minReg=1> DefList: { N841.t332. SUB } N843 ( 9, 7) [000334] DA---------- * STORE_LCL_VAR int V21 loc18 d:4 NA REG NA BB31 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB31 regmask=[allInt] minReg=1 last> CHECKING LAST USES for BB31, liveout={V01 V02 V13 V19 V20 V21} ============================== use: {V19 V20} def: {V21} NEW BLOCK BB32 Setting BB28 as the predecessor for determining incoming variable registers of BB32 DefList: { } N847 (???,???) [000961] ------------ * IL_OFFSET void IL offset: 0x15c REG NA DefList: { } N849 ( 3, 2) [000719] -------N---- * LCL_VAR ref (AX) V56 tmp26 NA REG NA $186 Interval 177: ref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR BB32 regmask=[allInt] minReg=1> DefList: { N849.t719. LCL_VAR } N851 ( 7, 5) [000720] DA--G------- * STORE_LCL_VAR ref (AX) V68 tmp38 NA REG NA BB32 regmask=[allInt] minReg=1 last> DefList: { } N853 ( 3, 2) [000722] -------N---- * LCL_VAR int (AX) V57 tmp27 NA REG NA $24a Interval 178: int RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR BB32 regmask=[allInt] minReg=1> DefList: { N853.t722. LCL_VAR } N855 ( 7, 5) [000723] DA--G------- * STORE_LCL_VAR int (AX) V69 tmp39 NA REG NA BB32 regmask=[allInt] minReg=1 last> DefList: { } N857 (???,???) [000962] ------------ * IL_OFFSET void IL offset: 0x15c REG NA DefList: { } N859 ( 3, 2) [000726] -------N---- * LCL_VAR ref (AX) V58 tmp28 NA REG NA $187 Interval 179: ref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR BB32 regmask=[allInt] minReg=1> DefList: { N859.t726. LCL_VAR } N861 ( 7, 5) [000727] DA--G------- * STORE_LCL_VAR ref V70 tmp40 d:2 NA REG NA BB32 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB32 regmask=[allInt] minReg=1 last> DefList: { } N863 ( 3, 2) [000729] -------N---- * LCL_VAR int (AX) V59 tmp29 NA REG NA $24b Interval 180: int RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR BB32 regmask=[allInt] minReg=1> DefList: { N863.t729. LCL_VAR } N865 ( 7, 5) [000730] DA--G------- * STORE_LCL_VAR int V71 tmp41 d:2 NA REG NA BB32 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB32 regmask=[allInt] minReg=1 last> DefList: { } N867 ( 3, 2) [000496] -------N---- * LCL_VAR_ADDR byref V49 tmp19 NA * ref V49._bits (offs=0x00) -> V68 tmp38 * int V49._sign (offs=0x08) -> V69 tmp39 REG NA Interval 181: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB32 regmask=[allInt] minReg=1> DefList: { N867.t496. LCL_VAR_ADDR } N869 ( 7, 6) [000752] DA--------L- * STORE_LCL_VAR byref V84 tmp54 d:2 NA REG NA BB32 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB32 regmask=[allInt] minReg=1 last> DefList: { } N871 ( 3, 2) [000736] -------N---- * LCL_VAR_ADDR byref V76 tmp46 NA REG NA Interval 182: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB32 regmask=[allInt] minReg=1> DefList: { N871.t736. LCL_VAR_ADDR } N873 ( 3, 3) [000738] DA---------- * STORE_LCL_VAR byref V83 tmp53 d:2 NA REG NA BB32 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB32 regmask=[allInt] minReg=1 last> DefList: { } N875 ( 1, 1) [000739] ------------ * LCL_VAR byref V83 tmp53 u:2 NA Zero Fseq[_bits] REG NA $417 DefList: { } N877 ( 3, 2) [000741] -------N---- * LCL_VAR ref V70 tmp40 u:2 NA (last use) REG NA $187 DefList: { } N879 (???,???) [000963] -A---------- * STOREIND ref REG NA LCL_VAR BB32 regmask=[allInt] minReg=1 last> LCL_VAR BB32 regmask=[allInt] minReg=1 last> DefList: { } N881 ( 1, 1) [000744] ------------ * LCL_VAR byref V83 tmp53 u:2 NA (last use) REG NA $417 DefList: { } N883 ( 2, 2) [000746] -c---------- * LEA(b+8) byref REG NA Contained DefList: { } N885 ( 3, 2) [000748] -------N---- * LCL_VAR int V71 tmp41 u:2 NA (last use) REG NA $24b DefList: { } N887 (???,???) [000964] -A--------L- * STOREIND int REG NA LCL_VAR BB32 regmask=[allInt] minReg=1 last> LCL_VAR BB32 regmask=[allInt] minReg=1 last> DefList: { } N889 ( 3, 2) [000753] ------------ * LCL_VAR byref V84 tmp54 u:2 NA (last use) REG NA $415 DefList: { } N891 (???,???) [001061] ------------ * PUTARG_REG byref REG rcx BB32 regmask=[rcx] minReg=1> LCL_VAR BB32 regmask=[rcx] minReg=1 last fixed> Interval 183: byref RefPositions {} physReg:NA Preferences=[allInt] BB32 regmask=[rcx] minReg=1> PUTARG_REG BB32 regmask=[rcx] minReg=1 fixed> DefList: { N891.t1061. PUTARG_REG } N893 ( 3, 2) [000754] -------N---- * LCL_VAR_ADDR byref V76 tmp46 NA REG NA Interval 184: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB32 regmask=[allInt] minReg=1> DefList: { N891.t1061. PUTARG_REG; N893.t754. LCL_VAR_ADDR } N895 (???,???) [001062] ------------ * PUTARG_REG byref REG rdx BB32 regmask=[rdx] minReg=1> BB32 regmask=[rdx] minReg=1 last fixed> Interval 185: byref RefPositions {} physReg:NA Preferences=[allInt] BB32 regmask=[rdx] minReg=1> PUTARG_REG BB32 regmask=[rdx] minReg=1 fixed> DefList: { N891.t1061. PUTARG_REG; N895.t1062. PUTARG_REG } N897 ( 48, 34) [000499] --CXG------- * CALL int System.Numerics.BigInteger.CompareTo REG NA $2ae BB32 regmask=[rcx] minReg=1> BB32 regmask=[rcx] minReg=1 last fixed> BB32 regmask=[rdx] minReg=1> BB32 regmask=[rdx] minReg=1 last fixed> BB32 regmask=[rax] minReg=1> BB32 regmask=[rcx] minReg=1> BB32 regmask=[rdx] minReg=1> BB32 regmask=[r8] minReg=1> BB32 regmask=[r9] minReg=1> BB32 regmask=[r10] minReg=1> BB32 regmask=[r11] minReg=1> Interval 186: int RefPositions {} physReg:NA Preferences=[allInt] BB32 regmask=[rax] minReg=1> CALL BB32 regmask=[rax] minReg=1 fixed> DefList: { N897.t499. CALL } N899 ( 1, 1) [000502] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { N897.t499. CALL } N901 ( 50, 36) [000503] J--XG--N---- * LT void REG NA $367 BB32 regmask=[allInt] minReg=1 last> DefList: { } N903 ( 52, 38) [000195] ---XG------- * JTRUE void REG NA CHECKING LAST USES for BB32, liveout={V01 V02 V13 V19 V20 V21} ============================== use: {} def: {V70 V71 V83 V84} NEW BLOCK BB33 Setting BB32 as the predecessor for determining incoming variable registers of BB33 DefList: { } N907 (???,???) [000965] ------------ * IL_OFFSET void IL offset: 0x167 REG NA DefList: { } N909 ( 1, 1) [000322] ------------ * LCL_VAR int V19 loc16 u:2 NA (last use) REG NA $248 DefList: { } N911 ( 5, 4) [000324] DA---------- * STORE_LCL_VAR int V34 tmp4 d:4 NA REG NA LCL_VAR BB33 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB33 regmask=[allInt] minReg=1 last> CHECKING LAST USES for BB33, liveout={V01 V02 V13 V20 V21 V34} ============================== use: {V19} def: {V34} NEW BLOCK BB34 Setting BB32 as the predecessor for determining incoming variable registers of BB34 DefList: { } N915 (???,???) [000966] ------------ * IL_OFFSET void IL offset: 0x16b REG NA DefList: { } N917 ( 1, 1) [000196] ------------ * LCL_VAR int V19 loc16 u:2 NA (last use) REG NA $248 DefList: { } N919 ( 1, 1) [000197] -c---------- * CNS_INT int 1 REG NA $41 Contained DefList: { } N921 ( 3, 3) [000198] ------------ * ADD int REG NA $368 LCL_VAR BB34 regmask=[allInt] minReg=1 last> Interval 187: int RefPositions {} physReg:NA Preferences=[allInt] ADD BB34 regmask=[allInt] minReg=1> Interval already has a related interval DefList: { N921.t198. ADD } N923 ( 7, 6) [000200] DA---------- * STORE_LCL_VAR int V34 tmp4 d:3 NA REG NA BB34 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB34 regmask=[allInt] minReg=1 last> CHECKING LAST USES for BB34, liveout={V01 V02 V13 V20 V21 V34} ============================== use: {V19} def: {V34} NEW BLOCK BB35 Setting BB33 as the predecessor for determining incoming variable registers of BB35 DefList: { } N927 ( 3, 2) [000202] ------------ * LCL_VAR int V34 tmp4 u:2 NA (last use) REG NA $24c DefList: { } N929 ( 7, 5) [000204] DA---------- * STORE_LCL_VAR int V22 loc19 d:2 NA REG NA LCL_VAR BB35 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB35 regmask=[allInt] minReg=1 last> DefList: { } N931 (???,???) [000967] ------------ * IL_OFFSET void IL offset: 0x171 REG NA DefList: { } N933 ( 3, 2) [000205] -------N---- * LCL_VAR_ADDR byref V15 loc12 NA * ref V15._bits (offs=0x00) -> V56 tmp26 * int V15._sign (offs=0x08) -> V57 tmp27 REG NA Interval 188: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB35 regmask=[allInt] minReg=1> DefList: { N933.t205. LCL_VAR_ADDR } N935 (???,???) [001063] ------------ * PUTARG_REG byref REG rcx BB35 regmask=[rcx] minReg=1> BB35 regmask=[rcx] minReg=1 last fixed> Interval 189: byref RefPositions {} physReg:NA Preferences=[allInt] BB35 regmask=[rcx] minReg=1> PUTARG_REG BB35 regmask=[rcx] minReg=1 fixed> DefList: { N935.t1063. PUTARG_REG } N937 ( 3, 2) [000207] ------------ * LCL_VAR int V21 loc18 u:3 NA (last use) REG NA $249 DefList: { N935.t1063. PUTARG_REG } N939 (???,???) [001064] ------------ * PUTARG_REG int REG rdx BB35 regmask=[rdx] minReg=1> LCL_VAR BB35 regmask=[rdx] minReg=1 last fixed> Interval 190: int RefPositions {} physReg:NA Preferences=[allInt] BB35 regmask=[rdx] minReg=1> PUTARG_REG BB35 regmask=[rdx] minReg=1 fixed> DefList: { N935.t1063. PUTARG_REG; N939.t1064. PUTARG_REG } N941 ( 20, 12) [000208] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft REG NA $VN.Void BB35 regmask=[rcx] minReg=1> BB35 regmask=[rcx] minReg=1 last fixed> BB35 regmask=[rdx] minReg=1> BB35 regmask=[rdx] minReg=1 last fixed> BB35 regmask=[rax] minReg=1> BB35 regmask=[rcx] minReg=1> BB35 regmask=[rdx] minReg=1> BB35 regmask=[r8] minReg=1> BB35 regmask=[r9] minReg=1> BB35 regmask=[r10] minReg=1> BB35 regmask=[r11] minReg=1> DefList: { } N943 (???,???) [000968] ------------ * IL_OFFSET void IL offset: 0x17a REG NA DefList: { } N945 ( 3, 2) [000219] -------N---- * LCL_VAR_ADDR byref V35 tmp5 NA * ref V35._bits (offs=0x00) -> V62 tmp32 * int V35._sign (offs=0x08) -> V63 tmp33 REG NA Interval 191: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB35 regmask=[allInt] minReg=1> DefList: { N945.t219. LCL_VAR_ADDR } N947 ( 7, 6) [000797] DA--------L- * STORE_LCL_VAR long V88 tmp58 d:2 NA REG NA BB35 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB35 regmask=[allInt] minReg=1 last> DefList: { } N949 ( 3, 2) [000762] -------N---- * LCL_VAR_ADDR byref V76 tmp46 NA REG NA Interval 192: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB35 regmask=[allInt] minReg=1> DefList: { N949.t762. LCL_VAR_ADDR } N951 ( 3, 3) [000764] DA---------- * STORE_LCL_VAR byref V85 tmp55 d:2 NA REG NA BB35 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB35 regmask=[allInt] minReg=1 last> DefList: { } N953 ( 1, 1) [000765] ------------ * LCL_VAR byref V85 tmp55 u:2 NA Zero Fseq[_bits] REG NA $41c DefList: { } N955 ( 3, 2) [000767] -------N---- * LCL_VAR ref (AX) V56 tmp26 NA REG NA $188 Interval 193: ref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR BB35 regmask=[allInt] minReg=1> DefList: { N955.t767. LCL_VAR } N957 (???,???) [000969] -A--G------- * STOREIND ref REG NA LCL_VAR BB35 regmask=[allInt] minReg=1 last> BB35 regmask=[allInt] minReg=1 last> DefList: { } N959 ( 1, 1) [000770] ------------ * LCL_VAR byref V85 tmp55 u:2 NA (last use) REG NA $41c DefList: { } N961 ( 2, 2) [000772] -c---------- * LEA(b+8) byref REG NA Contained DefList: { } N963 ( 3, 2) [000774] -------N---- * LCL_VAR int (AX) V57 tmp27 NA REG NA $24d Interval 194: int RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR BB35 regmask=[allInt] minReg=1> DefList: { N963.t774. LCL_VAR } N965 (???,???) [000970] -A--G-----L- * STOREIND int REG NA LCL_VAR BB35 regmask=[allInt] minReg=1 last> BB35 regmask=[allInt] minReg=1 last> DefList: { } N967 ( 3, 2) [000781] -------N---- * LCL_VAR_ADDR byref V86 tmp56 NA REG NA Interval 195: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB35 regmask=[allInt] minReg=1> DefList: { N967.t781. LCL_VAR_ADDR } N969 ( 3, 3) [000783] DA---------- * STORE_LCL_VAR byref V87 tmp57 d:2 NA REG NA BB35 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB35 regmask=[allInt] minReg=1 last> DefList: { } N971 ( 1, 1) [000784] ------------ * LCL_VAR byref V87 tmp57 u:2 NA Zero Fseq[_bits] REG NA $41e DefList: { } N973 ( 3, 2) [000786] -------N---- * LCL_VAR ref (AX) V58 tmp28 NA REG NA $189 Interval 196: ref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR BB35 regmask=[allInt] minReg=1> DefList: { N973.t786. LCL_VAR } N975 (???,???) [000971] -A--G------- * STOREIND ref REG NA LCL_VAR BB35 regmask=[allInt] minReg=1 last> BB35 regmask=[allInt] minReg=1 last> DefList: { } N977 ( 1, 1) [000789] ------------ * LCL_VAR byref V87 tmp57 u:2 NA (last use) REG NA $41e DefList: { } N979 ( 2, 2) [000791] -c---------- * LEA(b+8) byref REG NA Contained DefList: { } N981 ( 3, 2) [000793] -------N---- * LCL_VAR int (AX) V59 tmp29 NA REG NA $24e Interval 197: int RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR BB35 regmask=[allInt] minReg=1> DefList: { N981.t793. LCL_VAR } N983 (???,???) [000972] -A--G-----L- * STOREIND int REG NA LCL_VAR BB35 regmask=[allInt] minReg=1 last> BB35 regmask=[allInt] minReg=1 last> DefList: { } N985 ( 3, 2) [000798] ------------ * LCL_VAR long V88 tmp58 u:2 NA (last use) REG NA $41b DefList: { } N987 (???,???) [001065] ------------ * PUTARG_REG long REG rcx BB35 regmask=[rcx] minReg=1> LCL_VAR BB35 regmask=[rcx] minReg=1 last fixed> Interval 198: long RefPositions {} physReg:NA Preferences=[allInt] BB35 regmask=[rcx] minReg=1> PUTARG_REG BB35 regmask=[rcx] minReg=1 fixed> DefList: { N987.t1065. PUTARG_REG } N989 ( 3, 2) [000799] -------N---- * LCL_VAR_ADDR byref V76 tmp46 NA REG NA Interval 199: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB35 regmask=[allInt] minReg=1> DefList: { N987.t1065. PUTARG_REG; N989.t799. LCL_VAR_ADDR } N991 (???,???) [001066] ------------ * PUTARG_REG byref REG rdx BB35 regmask=[rdx] minReg=1> BB35 regmask=[rdx] minReg=1 last fixed> Interval 200: byref RefPositions {} physReg:NA Preferences=[allInt] BB35 regmask=[rdx] minReg=1> PUTARG_REG BB35 regmask=[rdx] minReg=1 fixed> DefList: { N987.t1065. PUTARG_REG; N991.t1066. PUTARG_REG } N993 ( 3, 2) [000801] -------N---- * LCL_VAR_ADDR byref V86 tmp56 NA REG NA Interval 201: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB35 regmask=[allInt] minReg=1> DefList: { N987.t1065. PUTARG_REG; N991.t1066. PUTARG_REG; N993.t801. LCL_VAR_ADDR } N995 (???,???) [001067] ------------ * PUTARG_REG byref REG r8 BB35 regmask=[r8] minReg=1> BB35 regmask=[r8] minReg=1 last fixed> Interval 202: byref RefPositions {} physReg:NA Preferences=[allInt] BB35 regmask=[r8] minReg=1> PUTARG_REG BB35 regmask=[r8] minReg=1 fixed> DefList: { N987.t1065. PUTARG_REG; N991.t1066. PUTARG_REG; N995.t1067. PUTARG_REG } N997 ( 3, 2) [000211] -------N---- * LCL_VAR_ADDR byref V23 loc20 NA * ref V23._bits (offs=0x00) -> V60 tmp30 * int V23._sign (offs=0x08) -> V61 tmp31 REG NA Interval 203: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB35 regmask=[allInt] minReg=1> DefList: { N987.t1065. PUTARG_REG; N991.t1066. PUTARG_REG; N995.t1067. PUTARG_REG; N997.t211. LCL_VAR_ADDR } N999 (???,???) [001068] ------------ * PUTARG_REG byref REG r9 BB35 regmask=[r9] minReg=1> BB35 regmask=[r9] minReg=1 last fixed> Interval 204: byref RefPositions {} physReg:NA Preferences=[allInt] BB35 regmask=[r9] minReg=1> PUTARG_REG BB35 regmask=[r9] minReg=1 fixed> DefList: { N987.t1065. PUTARG_REG; N991.t1066. PUTARG_REG; N995.t1067. PUTARG_REG; N999.t1068. PUTARG_REG } N1001 ( 78, 56) [000213] S-CXG------- * CALL void System.Numerics.BigInteger.DivRem REG NA $VN.Void BB35 regmask=[rcx] minReg=1> BB35 regmask=[rcx] minReg=1 last fixed> BB35 regmask=[rdx] minReg=1> BB35 regmask=[rdx] minReg=1 last fixed> BB35 regmask=[r8] minReg=1> BB35 regmask=[r8] minReg=1 last fixed> BB35 regmask=[r9] minReg=1> BB35 regmask=[r9] minReg=1 last fixed> BB35 regmask=[rax] minReg=1> BB35 regmask=[rcx] minReg=1> BB35 regmask=[rdx] minReg=1> BB35 regmask=[r8] minReg=1> BB35 regmask=[r9] minReg=1> BB35 regmask=[r10] minReg=1> BB35 regmask=[r11] minReg=1> DefList: { } N1003 ( 3, 2) [000808] -------N---- * LCL_VAR_ADDR byref V76 tmp46 NA REG NA Interval 205: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB35 regmask=[allInt] minReg=1> DefList: { N1003.t808. LCL_VAR_ADDR } N1005 ( 3, 3) [000810] DA---------- * STORE_LCL_VAR byref V89 tmp59 d:2 NA REG NA BB35 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB35 regmask=[allInt] minReg=1 last> DefList: { } N1007 ( 1, 1) [000811] ------------ * LCL_VAR byref V89 tmp59 u:2 NA Zero Fseq[_bits] REG NA $423 DefList: { } N1009 ( 3, 2) [000813] -------N---- * LCL_VAR ref (AX) V62 tmp32 NA REG NA $18a Interval 206: ref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR BB35 regmask=[allInt] minReg=1> DefList: { N1009.t813. LCL_VAR } N1011 (???,???) [000973] -A--G------- * STOREIND ref REG NA LCL_VAR BB35 regmask=[allInt] minReg=1 last> BB35 regmask=[allInt] minReg=1 last> DefList: { } N1013 ( 1, 1) [000816] ------------ * LCL_VAR byref V89 tmp59 u:2 NA (last use) REG NA $423 DefList: { } N1015 ( 2, 2) [000818] -c---------- * LEA(b+8) byref REG NA Contained DefList: { } N1017 ( 3, 2) [000820] -------N---- * LCL_VAR int (AX) V63 tmp33 NA REG NA $24f Interval 207: int RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR BB35 regmask=[allInt] minReg=1> DefList: { N1017.t820. LCL_VAR } N1019 (???,???) [000974] -A--G-----L- * STOREIND int REG NA LCL_VAR BB35 regmask=[allInt] minReg=1 last> BB35 regmask=[allInt] minReg=1 last> DefList: { } N1021 ( 3, 2) [000823] -------N---- * LCL_VAR_ADDR byref V76 tmp46 NA REG NA Interval 208: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB35 regmask=[allInt] minReg=1> DefList: { N1021.t823. LCL_VAR_ADDR } N1023 (???,???) [001069] ------------ * PUTARG_REG byref REG rcx BB35 regmask=[rcx] minReg=1> BB35 regmask=[rcx] minReg=1 last fixed> Interval 209: byref RefPositions {} physReg:NA Preferences=[allInt] BB35 regmask=[rcx] minReg=1> PUTARG_REG BB35 regmask=[rcx] minReg=1 fixed> DefList: { N1023.t1069. PUTARG_REG } N1025 ( 38, 24) [000218] --CXG------- * CALL long System.Numerics.BigInteger.op_Explicit REG NA $450 BB35 regmask=[rcx] minReg=1> BB35 regmask=[rcx] minReg=1 last fixed> BB35 regmask=[rax] minReg=1> BB35 regmask=[rcx] minReg=1> BB35 regmask=[rdx] minReg=1> BB35 regmask=[r8] minReg=1> BB35 regmask=[r9] minReg=1> BB35 regmask=[r10] minReg=1> BB35 regmask=[r11] minReg=1> Interval 210: long RefPositions {} physReg:NA Preferences=[allInt] BB35 regmask=[rax] minReg=1> CALL BB35 regmask=[rax] minReg=1 fixed> DefList: { N1025.t218. CALL } N1027 ( 38, 24) [000226] DA-XG------- * STORE_LCL_VAR long V24 loc21 d:2 NA REG NA BB35 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB35 regmask=[allInt] minReg=1 last> DefList: { } N1029 ( 3, 2) [000514] -c---------- * LCL_VAR int (AX) V61 tmp31 NA REG NA $250 Contained DefList: { } N1031 ( 1, 1) [000515] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { } N1033 ( 8, 4) [000516] ----G------- * EQ int REG NA $369 Interval 211: int RefPositions {} physReg:NA Preferences=[allInt] EQ BB35 regmask=[allInt] minReg=1> DefList: { N1033.t516. EQ } N1035 ( 12, 7) [000232] DA--G------- * STORE_LCL_VAR int V25 loc22 d:2 NA REG NA BB35 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB35 regmask=[allInt] minReg=1 last> DefList: { } N1037 ( 1, 1) [000233] ------------ * LCL_VAR long V24 loc21 u:2 NA REG NA $450 DefList: { } N1039 (???,???) [001070] ------------ * PUTARG_REG long REG rcx BB35 regmask=[rcx] minReg=1> LCL_VAR BB35 regmask=[rcx] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 212: long RefPositions {} physReg:NA Preferences=[allInt] BB35 regmask=[rcx] minReg=1> PUTARG_REG BB35 regmask=[rcx] minReg=1 fixed> Assigning related to DefList: { N1039.t1070. PUTARG_REG } N1041 ( 15, 7) [000234] --CXG------- * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits REG NA $2b4 BB35 regmask=[rcx] minReg=1> BB35 regmask=[rcx] minReg=1 last fixed> BB35 regmask=[rax] minReg=1> BB35 regmask=[rcx] minReg=1> BB35 regmask=[rdx] minReg=1> BB35 regmask=[r8] minReg=1> BB35 regmask=[r9] minReg=1> BB35 regmask=[r10] minReg=1> BB35 regmask=[r11] minReg=1> Interval 213: int RefPositions {} physReg:NA Preferences=[allInt] BB35 regmask=[rax] minReg=1> CALL BB35 regmask=[rax] minReg=1 fixed> DefList: { N1041.t234. CALL } N1043 ( 19, 10) [000237] DA-XG------- * STORE_LCL_VAR int V26 loc23 d:2 NA REG NA BB35 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB35 regmask=[allInt] minReg=1 last> DefList: { } N1045 (???,???) [000975] ------------ * IL_OFFSET void IL offset: 0x19e REG NA DefList: { } N1047 ( 3, 2) [000238] ------------ * LCL_VAR int V26 loc23 u:2 NA REG NA $2b4 DefList: { } N1049 ( 3, 2) [000239] ------------ * LCL_VAR int V20 loc17 u:2 NA REG NA $362 DefList: { } N1051 ( 7, 5) [000240] N------N-U-- * LE void REG NA $36a LCL_VAR BB35 regmask=[allInt] minReg=1 last> LCL_VAR BB35 regmask=[allInt] minReg=1 last> DefList: { } N1053 ( 9, 7) [000241] ------------ * JTRUE void REG NA CHECKING LAST USES for BB35, liveout={V01 V02 V13 V20 V22 V24 V25 V26} ============================== use: {V20 V21 V34} def: {V22 V24 V25 V26 V85 V87 V88 V89} NEW BLOCK BB36 Setting BB35 as the predecessor for determining incoming variable registers of BB36 DefList: { } N1057 (???,???) [000976] ------------ * IL_OFFSET void IL offset: 0x1a4 REG NA DefList: { } N1059 ( 3, 2) [000282] ------------ * LCL_VAR int V26 loc23 u:2 NA (last use) REG NA $2b4 DefList: { } N1061 ( 3, 2) [000283] ------------ * LCL_VAR int V20 loc17 u:2 NA REG NA $362 DefList: { } N1063 ( 7, 5) [000284] ------------ * SUB int REG NA $36b LCL_VAR BB36 regmask=[allInt] minReg=1 last> LCL_VAR BB36 regmask=[allInt] minReg=1 last> Interval 214: int RefPositions {} physReg:NA Preferences=[allInt] SUB BB36 regmask=[allInt] minReg=1> Assigning related to DefList: { N1063.t284. SUB } N1065 ( 11, 8) [000286] DA---------- * STORE_LCL_VAR int V29 loc26 d:2 NA REG NA BB36 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB36 regmask=[allInt] minReg=1 last> DefList: { } N1067 (???,???) [000977] ------------ * IL_OFFSET void IL offset: 0x1ab REG NA DefList: { } N1069 ( 3, 2) [000287] ------------ * LCL_VAR int V25 loc22 u:2 NA (last use) REG NA $369 DefList: { } N1071 ( 1, 1) [000288] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { } N1073 ( 5, 4) [000289] J------N---- * EQ void REG NA $36c LCL_VAR BB36 regmask=[allInt] minReg=1 last> DefList: { } N1075 ( 7, 6) [000290] ------------ * JTRUE void REG NA CHECKING LAST USES for BB36, liveout={V01 V02 V13 V20 V22 V24 V29} ============================== use: {V20 V25 V26} def: {V29} NEW BLOCK BB37 Setting BB36 as the predecessor for determining incoming variable registers of BB37 DefList: { } N1079 (???,???) [000978] ------------ * IL_OFFSET void IL offset: 0x1af REG NA DefList: { } N1081 ( 1, 1) [000305] ------------ * LCL_VAR long V24 loc21 u:2 NA REG NA $450 DefList: { } N1083 ( 3, 2) [000308] ------------ * LCL_VAR int V29 loc26 u:2 NA REG NA $36b DefList: { } N1085 ( 1, 1) [000307] ------------ * CNS_INT long 1 REG NA $103 Interval 215: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB37 regmask=[allInt] minReg=1> DefList: { N1085.t307. CNS_INT } N1087 ( 10, 6) [000311] ------------ * LSH long REG NA $48e BB37 regmask=[rax rdx rbx rbp rsi rdi r8-r15] minReg=1 last> BB37 regmask=[rcx] minReg=1> LCL_VAR BB37 regmask=[rcx] minReg=1 last fixed> BB37 regmask=[rcx] minReg=1> Interval 216: long RefPositions {} physReg:NA Preferences=[allInt] LSH BB37 regmask=[rax rdx rbx rbp rsi rdi r8-r15] minReg=1> Assigning related to DefList: { N1087.t311. LSH } N1089 ( 1, 1) [000313] -c---------- * CNS_INT long -1 REG NA $104 Contained DefList: { N1087.t311. LSH } N1091 ( 12, 8) [000314] ------------ * ADD long REG NA $48f BB37 regmask=[allInt] minReg=1 last> Interval 217: long RefPositions {} physReg:NA Preferences=[allInt] ADD BB37 regmask=[allInt] minReg=1> Assigning related to DefList: { N1091.t314. ADD } N1093 ( 19, 12) [000318] ------------ * TEST_EQ int REG NA $36e LCL_VAR BB37 regmask=[allInt] minReg=1 last> BB37 regmask=[allInt] minReg=1 last> Interval 218: int RefPositions {} physReg:NA Preferences=[allInt] TEST_EQ BB37 regmask=[allInt] minReg=1> DefList: { N1093.t318. TEST_EQ } N1095 ( 23, 15) [000320] DA---------- * STORE_LCL_VAR int V37 tmp7 d:4 NA REG NA BB37 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB37 regmask=[allInt] minReg=1 last> CHECKING LAST USES for BB37, liveout={V01 V02 V13 V20 V22 V24 V29 V37} ============================== use: {V24 V29} def: {V37} NEW BLOCK BB38 Setting BB36 as the predecessor for determining incoming variable registers of BB38 DefList: { } N1099 (???,???) [000979] ------------ * IL_OFFSET void IL offset: 0x1c3 REG NA DefList: { } N1101 ( 1, 1) [000291] ------------ * CNS_INT int 0 REG NA $40 Interval 219: int RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB38 regmask=[allInt] minReg=1> DefList: { N1101.t291. CNS_INT } N1103 ( 5, 4) [000293] DA---------- * STORE_LCL_VAR int V37 tmp7 d:3 NA REG NA BB38 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB38 regmask=[allInt] minReg=1 last> CHECKING LAST USES for BB38, liveout={V01 V02 V13 V20 V22 V24 V29 V37} ============================== use: {} def: {V37} NEW BLOCK BB39 Setting BB37 as the predecessor for determining incoming variable registers of BB39 DefList: { } N1107 ( 3, 2) [000295] ------------ * LCL_VAR int V37 tmp7 u:2 NA (last use) REG NA $251 DefList: { } N1109 ( 4, 4) [000826] ------------ * CAST int <- bool <- int REG NA $36f LCL_VAR BB39 regmask=[allInt] minReg=1 last> Interval 220: int RefPositions {} physReg:NA Preferences=[allInt] CAST BB39 regmask=[allInt] minReg=1> DefList: { N1109.t826. CAST } N1111 ( 8, 7) [000297] DA---------- * STORE_LCL_VAR int V25 loc22 d:4 NA REG NA BB39 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB39 regmask=[allInt] minReg=1 last> DefList: { } N1113 (???,???) [000980] ------------ * IL_OFFSET void IL offset: 0x1c6 REG NA DefList: { } N1115 ( 1, 1) [000298] ------------ * LCL_VAR long V24 loc21 u:2 NA (last use) REG NA $450 DefList: { } N1117 ( 3, 2) [000299] ------------ * LCL_VAR int V29 loc26 u:2 NA (last use) REG NA $36b DefList: { } N1119 ( 10, 6) [000302] ------------ * RSZ long REG NA $491 LCL_VAR BB39 regmask=[rax rdx rbx rbp rsi rdi r8-r15] minReg=1 last> BB39 regmask=[rcx] minReg=1> LCL_VAR BB39 regmask=[rcx] minReg=1 last fixed> BB39 regmask=[rcx] minReg=1> Interval 221: long RefPositions {} physReg:NA Preferences=[allInt] RSZ BB39 regmask=[rax rdx rbx rbp rsi rdi r8-r15] minReg=1> Assigning related to DefList: { N1119.t302. RSZ } N1121 ( 10, 6) [000304] DA---------- * STORE_LCL_VAR long V24 loc21 d:4 NA REG NA BB39 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB39 regmask=[allInt] minReg=1 last> CHECKING LAST USES for BB39, liveout={V01 V02 V13 V20 V22 V24 V25} ============================== use: {V24 V29 V37} def: {V24 V25} NEW BLOCK BB40 Setting BB35 as the predecessor for determining incoming variable registers of BB40 DefList: { } N1125 ( 3, 2) [000831] -------N---- * LCL_VAR_ADDR byref V76 tmp46 NA REG NA Interval 222: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB40 regmask=[allInt] minReg=1> DefList: { N1125.t831. LCL_VAR_ADDR } N1127 ( 3, 3) [000833] DA---------- * STORE_LCL_VAR byref V90 tmp60 d:2 NA REG NA BB40 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB40 regmask=[allInt] minReg=1 last> DefList: { } N1129 ( 1, 1) [000834] ------------ * LCL_VAR byref V90 tmp60 u:2 NA Zero Fseq[_bits] REG NA $426 DefList: { } N1131 ( 3, 2) [000836] -------N---- * LCL_VAR ref (AX) V54 tmp24 NA REG NA $18b Interval 223: ref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR BB40 regmask=[allInt] minReg=1> DefList: { N1131.t836. LCL_VAR } N1133 (???,???) [000981] -A--G------- * STOREIND ref REG NA LCL_VAR BB40 regmask=[allInt] minReg=1 last> BB40 regmask=[allInt] minReg=1 last> DefList: { } N1135 ( 1, 1) [000839] ------------ * LCL_VAR byref V90 tmp60 u:2 NA (last use) REG NA $426 DefList: { } N1137 ( 2, 2) [000841] -c---------- * LEA(b+8) byref REG NA Contained DefList: { } N1139 ( 3, 2) [000843] -------N---- * LCL_VAR int (AX) V55 tmp25 NA REG NA $252 Interval 224: int RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR BB40 regmask=[allInt] minReg=1> DefList: { N1139.t843. LCL_VAR } N1141 (???,???) [000982] -A--G-----L- * STOREIND int REG NA LCL_VAR BB40 regmask=[allInt] minReg=1 last> BB40 regmask=[allInt] minReg=1 last> DefList: { } N1143 ( 3, 2) [000846] -------N---- * LCL_VAR_ADDR byref V76 tmp46 NA REG NA Interval 225: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB40 regmask=[allInt] minReg=1> DefList: { N1143.t846. LCL_VAR_ADDR } N1145 (???,???) [001071] ------------ * PUTARG_REG byref REG rcx BB40 regmask=[rcx] minReg=1> BB40 regmask=[rcx] minReg=1 last fixed> Interval 226: byref RefPositions {} physReg:NA Preferences=[allInt] BB40 regmask=[rcx] minReg=1> PUTARG_REG BB40 regmask=[rcx] minReg=1 fixed> DefList: { N1145.t1071. PUTARG_REG } N1147 ( 38, 24) [000243] --CXG------- * CALL long System.Numerics.BigInteger.op_Explicit REG NA $454 BB40 regmask=[rcx] minReg=1> BB40 regmask=[rcx] minReg=1 last fixed> BB40 regmask=[rax] minReg=1> BB40 regmask=[rcx] minReg=1> BB40 regmask=[rdx] minReg=1> BB40 regmask=[r8] minReg=1> BB40 regmask=[r9] minReg=1> BB40 regmask=[r10] minReg=1> BB40 regmask=[r11] minReg=1> Interval 227: long RefPositions {} physReg:NA Preferences=[allInt] BB40 regmask=[rax] minReg=1> CALL BB40 regmask=[rax] minReg=1 fixed> DefList: { N1147.t243. CALL } N1149 ( 3, 2) [000247] ------------ * LCL_VAR int V20 loc17 u:2 NA (last use) REG NA $362 DefList: { N1147.t243. CALL } N1151 ( 47, 29) [000250] ---XG------- * LSH long REG NA $492 BB40 regmask=[rax rdx rbx rbp rsi rdi r8-r15] minReg=1 last> BB40 regmask=[rcx] minReg=1> LCL_VAR BB40 regmask=[rcx] minReg=1 last fixed> BB40 regmask=[rcx] minReg=1> Interval 228: long RefPositions {} physReg:NA Preferences=[allInt] LSH BB40 regmask=[rax rdx rbx rbp rsi rdi r8-r15] minReg=1> Assigning related to DefList: { N1151.t250. LSH } N1153 ( 1, 1) [000251] ------------ * LCL_VAR long V24 loc21 u:3 NA (last use) REG NA $580 DefList: { N1151.t250. LSH } N1155 ( 49, 31) [000252] ---XG------- * ADD long REG NA $493 BB40 regmask=[allInt] minReg=1 last> LCL_VAR BB40 regmask=[allInt] minReg=1 last> Interval 229: long RefPositions {} physReg:NA Preferences=[allInt] ADD BB40 regmask=[allInt] minReg=1> Assigning related to Interval already has a related interval DefList: { N1155.t252. ADD } N1157 ( 53, 34) [000254] DA-XG------- * STORE_LCL_VAR long V27 loc24 d:2 NA REG NA BB40 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB40 regmask=[allInt] minReg=1 last> DefList: { } N1159 (???,???) [000983] ------------ * IL_OFFSET void IL offset: 0x1e2 REG NA DefList: { } N1161 ( 1, 1) [000255] ------------ * LCL_VAR int V13 loc10 u:2 NA REG NA $293 DefList: { } N1163 ( 1, 1) [000256] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { } N1165 ( 3, 3) [000257] N------N---- * NE void REG NA $35a LCL_VAR BB40 regmask=[allInt] minReg=1 last> DefList: { } N1167 ( 5, 5) [000258] ------------ * JTRUE void REG NA CHECKING LAST USES for BB40, liveout={V01 V02 V13 V22 V25 V27} ============================== use: {V13 V20 V24} def: {V27 V90} NEW BLOCK BB41 Setting BB40 as the predecessor for determining incoming variable registers of BB41 DefList: { } N1171 (???,???) [000984] ------------ * IL_OFFSET void IL offset: 0x1e7 REG NA DefList: { } N1173 ( 3, 2) [000275] ------------ * LCL_VAR int V22 loc19 u:2 NA (last use) REG NA $24c DefList: { } N1175 ( 4, 3) [000276] ------------ * NEG int REG NA $2c2 LCL_VAR BB41 regmask=[allInt] minReg=1 last> Interval 230: int RefPositions {} physReg:NA Preferences=[allInt] NEG BB41 regmask=[allInt] minReg=1> DefList: { N1175.t276. NEG } N1177 ( 1, 1) [000277] -c---------- * CNS_INT int -1 REG NA $43 Contained DefList: { N1175.t276. NEG } N1179 ( 6, 5) [000278] ------------ * ADD int REG NA $372 BB41 regmask=[allInt] minReg=1 last> Interval 231: int RefPositions {} physReg:NA Preferences=[allInt] ADD BB41 regmask=[allInt] minReg=1> Assigning related to DefList: { N1179.t278. ADD } N1181 ( 10, 8) [000280] DA---------- * STORE_LCL_VAR int V36 tmp6 d:4 NA REG NA BB41 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB41 regmask=[allInt] minReg=1 last> CHECKING LAST USES for BB41, liveout={V01 V02 V25 V27 V36} ============================== use: {V22} def: {V36} NEW BLOCK BB42 Setting BB40 as the predecessor for determining incoming variable registers of BB42 DefList: { } N1185 (???,???) [000985] ------------ * IL_OFFSET void IL offset: 0x1ee REG NA DefList: { } N1187 ( 1, 1) [000259] ------------ * LCL_VAR int V13 loc10 u:2 NA (last use) REG NA $293 DefList: { } N1189 ( 1, 1) [000260] -c---------- * CNS_INT int -2 REG NA $68 Contained DefList: { } N1191 ( 3, 3) [000261] ------------ * ADD int REG NA $371 LCL_VAR BB42 regmask=[allInt] minReg=1 last> Interval 232: int RefPositions {} physReg:NA Preferences=[allInt] ADD BB42 regmask=[allInt] minReg=1> Assigning related to DefList: { N1191.t261. ADD } N1193 ( 7, 6) [000263] DA---------- * STORE_LCL_VAR int V36 tmp6 d:3 NA REG NA BB42 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB42 regmask=[allInt] minReg=1 last> CHECKING LAST USES for BB42, liveout={V01 V02 V25 V27 V36} ============================== use: {V13} def: {V36} NEW BLOCK BB43 Setting BB41 as the predecessor for determining incoming variable registers of BB43 DefList: { } N1197 (???,???) [000986] ------------ * IL_OFFSET void IL offset: 0x1f4 REG NA DefList: { } N1199 ( 1, 1) [000272] ------------ * LCL_VAR byref V02 arg2 u:1 NA (last use) REG NA $81 DefList: { } N1201 (???,???) [001072] ------------ * PUTARG_STK [+0x20] void REG NA LCL_VAR BB43 regmask=[allInt] minReg=1 last> DefList: { } N1203 ( 1, 1) [000268] ------------ * LCL_VAR ref V01 arg1 u:1 NA (last use) REG NA $c0 DefList: { } N1205 (???,???) [001073] ------------ * PUTARG_REG ref REG rcx BB43 regmask=[rcx] minReg=1> LCL_VAR BB43 regmask=[rcx] minReg=1 last fixed> Interval 233: ref RefPositions {} physReg:NA Preferences=[allInt] BB43 regmask=[rcx] minReg=1> PUTARG_REG BB43 regmask=[rcx] minReg=1 fixed> DefList: { N1205.t1073. PUTARG_REG } N1207 ( 3, 2) [000269] ------------ * LCL_VAR long V27 loc24 u:2 NA (last use) REG NA $493 DefList: { N1205.t1073. PUTARG_REG } N1209 (???,???) [001074] ------------ * PUTARG_REG long REG rdx BB43 regmask=[rdx] minReg=1> LCL_VAR BB43 regmask=[rdx] minReg=1 last fixed> Interval 234: long RefPositions {} physReg:NA Preferences=[allInt] BB43 regmask=[rdx] minReg=1> PUTARG_REG BB43 regmask=[rdx] minReg=1 fixed> DefList: { N1205.t1073. PUTARG_REG; N1209.t1074. PUTARG_REG } N1211 ( 3, 2) [000270] ------------ * LCL_VAR int V36 tmp6 u:2 NA (last use) REG NA $253 DefList: { N1205.t1073. PUTARG_REG; N1209.t1074. PUTARG_REG } N1213 (???,???) [001075] ------------ * PUTARG_REG int REG r8 BB43 regmask=[r8] minReg=1> LCL_VAR BB43 regmask=[r8] minReg=1 last fixed> Interval 235: int RefPositions {} physReg:NA Preferences=[allInt] BB43 regmask=[r8] minReg=1> PUTARG_REG BB43 regmask=[r8] minReg=1 fixed> DefList: { N1205.t1073. PUTARG_REG; N1209.t1074. PUTARG_REG; N1213.t1075. PUTARG_REG } N1215 ( 3, 2) [000271] ------------ * LCL_VAR int V25 loc22 u:3 NA (last use) REG NA $540 DefList: { N1205.t1073. PUTARG_REG; N1209.t1074. PUTARG_REG; N1213.t1075. PUTARG_REG } N1217 (???,???) [001076] ------------ * PUTARG_REG int REG r9 BB43 regmask=[r9] minReg=1> LCL_VAR BB43 regmask=[r9] minReg=1 last fixed> Interval 236: int RefPositions {} physReg:NA Preferences=[allInt] BB43 regmask=[r9] minReg=1> PUTARG_REG BB43 regmask=[r9] minReg=1 fixed> DefList: { N1205.t1073. PUTARG_REG; N1209.t1074. PUTARG_REG; N1213.t1075. PUTARG_REG; N1217.t1076. PUTARG_REG } N1219 ( 28, 18) [000273] --CXG------- * CALL int FloatingPointType.AssembleFloatingPointValue REG NA $2be BB43 regmask=[rcx] minReg=1> BB43 regmask=[rcx] minReg=1 last fixed> BB43 regmask=[rdx] minReg=1> BB43 regmask=[rdx] minReg=1 last fixed> BB43 regmask=[r8] minReg=1> BB43 regmask=[r8] minReg=1 last fixed> BB43 regmask=[r9] minReg=1> BB43 regmask=[r9] minReg=1 last fixed> BB43 regmask=[rax] minReg=1> BB43 regmask=[rcx] minReg=1> BB43 regmask=[rdx] minReg=1> BB43 regmask=[r8] minReg=1> BB43 regmask=[r9] minReg=1> BB43 regmask=[r10] minReg=1> BB43 regmask=[r11] minReg=1> Interval 237: int RefPositions {} physReg:NA Preferences=[allInt] BB43 regmask=[rax] minReg=1> CALL BB43 regmask=[rax] minReg=1 fixed> DefList: { N1219.t273. CALL } N1221 ( 28, 18) [000853] DA-XG------- * STORE_LCL_VAR int V51 tmp21 d:4 NA REG NA BB43 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB43 regmask=[allInt] minReg=1 last> CHECKING LAST USES for BB43, liveout={V51} ============================== use: {V01 V02 V25 V27 V36} def: {V51} NEW BLOCK BB44 Setting BB16 as the predecessor for determining incoming variable registers of BB44 DefList: { } N1225 ( 1, 1) [000522] -------N---- * LCL_VAR int V51 tmp21 u:2 NA (last use) REG NA $254 DefList: { } N1227 ( 2, 2) [000523] ------------ * RETURN int REG NA $5c9 BB44 regmask=[rax] minReg=1> LCL_VAR BB44 regmask=[rax] minReg=1 last fixed> CHECKING LAST USES for BB44, liveout={} ============================== use: {V51} def: {} Linear scan intervals BEFORE VALIDATING INTERVALS: Interval 0: (V00) byref RefPositions {#1@0 #4@5 #8@13} physReg:rcx Preferences=[rcx] Interval 1: (V01) ref RefPositions {#0@0 #16@39 #19@45 #42@69 #45@75 #157@253 #179@273 #182@279 #281@393 #331@467 #351@485 #354@491 #624@827 #920@1205} physReg:rdx Preferences=[rbx rbp rsi rdi r12-r15] Interval 2: (V02) byref RefPositions {#2@0 #35@59 #198@293 #264@373 #370@505 #608@811 #918@1201} physReg:r8 Preferences=[rbx rbp rsi rdi r12-r15] Interval 3: (V03) int RefPositions {#68@98 #260@351 #596@773} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval Interval 4: (V05) int RefPositions {#99@174 #154@245 #173@261 #210@309} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 5: (V08) int RefPositions {#101@180 #107@195 #131@231 #396@545} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 6: (V09) int RefPositions {#105@188 #106@195 #400@549} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 7: (V10) int RefPositions {#110@198 #262@363 #265@379 #306@417 #309@427} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval Interval 8: (V13) int RefPositions {#258@344 #259@351 #277@389 #317@443 #597@773 #603@789 #620@823 #904@1165 #913@1191} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval Interval 9: (V14) int RefPositions {#316@436 #323@459 #460@597} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 10: (V17) int RefPositions {#515@652 #559@711 #566@731} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 11: (V18) int RefPositions {#557@704 #558@711 #565@731} physReg:NA Preferences=[allInt] RelatedInterval Interval 12: (V19) int RefPositions {#572@740 #573@747 #581@761 #605@801 #648@841 #697@911 #700@921} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval Interval 13: (V20) int RefPositions {#600@776 #601@781 #606@801 #647@841 #830@1051 #833@1063 #896@1151} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 14: (V21) int RefPositions {#602@782 #651@844 #713@939} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 15: (V22) int RefPositions {#706@930 #906@1175} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 16: (V24) long RefPositions {#808@1028 #813@1039 #847@1093 #861@1119 #867@1122 #900@1155} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval Interval 17: (V25) int RefPositions {#811@1036 #837@1073 #860@1112 #932@1217} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 18: (V26) int RefPositions {#828@1044 #829@1051 #832@1063} physReg:NA Preferences=[allInt] RelatedInterval Interval 19: (V27) long RefPositions {#903@1158 #924@1209} physReg:NA Preferences=[rdx] Interval 20: (V29) int RefPositions {#836@1066 #842@1087 #863@1119} physReg:NA Preferences=[rax rdx rbx rbp rsi rdi r8-r15] Interval 21: (V31) int RefPositions {#81@136 #86@149 #92@163 #95@171} physReg:NA Preferences=[allInt] RelatedInterval Interval 22: (V32) int RefPositions {#307@418 #313@430 #315@435} physReg:NA Preferences=[allInt] RelatedInterval Interval 23: (V33) int RefPositions {#563@722 #569@734 #571@739} physReg:NA Preferences=[allInt] RelatedInterval Interval 24: (V34) int RefPositions {#698@912 #703@924 #705@929} physReg:NA Preferences=[allInt] RelatedInterval Interval 25: (V36) int RefPositions {#911@1182 #916@1194 #928@1213} physReg:NA Preferences=[r8] Interval 26: (V37) int RefPositions {#851@1096 #855@1104 #857@1109} physReg:NA Preferences=[allInt] Interval 27: (V38) long RefPositions {#329@464 #348@475} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 28: (V39) int RefPositions {#74@122 #78@130 #80@135} physReg:NA Preferences=[allInt] RelatedInterval Interval 29: (V40) int RefPositions {#70@104 #71@111} physReg:NA Preferences=[allInt] Interval 30: (V41) int RefPositions {#90@158 #93@164 #96@171 #100@179} physReg:NA Preferences=[allInt] RelatedInterval Interval 31: (V42) int RefPositions {#85@144 #87@149 #89@157} physReg:NA Preferences=[allInt] RelatedInterval Interval 32: (V43) int RefPositions {#511@642 #514@651} physReg:NA Preferences=[allInt] RelatedInterval Interval 33: (V46) int RefPositions {#553@694 #556@703} physReg:NA Preferences=[allInt] RelatedInterval Interval 34: (V51) int RefPositions {#302@398 #645@832 #953@1222 #956@1227} physReg:NA Preferences=[rax] Interval 35: (V52) ref (field) RefPositions {#7@8 #13@29 #82@141 #102@185 #118@211 #319@453 #383@525} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 36: (V53) int (field) RefPositions {#11@16 #69@103 #73@121 #120@219 #304@407 #310@427 #385@533} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 37: (V64) ref (field) RefPositions {#476@606 #484@621} physReg:NA Preferences=[allInt] Interval 38: (V65) int (field) RefPositions {#479@610 #486@629} physReg:NA Preferences=[allInt] Interval 39: (V66) ref (field) RefPositions {#518@658 #526@673} physReg:NA Preferences=[allInt] Interval 40: (V67) int (field) RefPositions {#521@662 #528@681} physReg:NA Preferences=[allInt] Interval 41: (V70) ref (field) RefPositions {#659@862 #670@879} physReg:NA Preferences=[allInt] Interval 42: (V71) int (field) RefPositions {#662@866 #672@887} physReg:NA Preferences=[allInt] Interval 43: (V74) byref RefPositions {#116@206 #117@211 #119@219} physReg:NA Preferences=[allInt] Interval 44: (V75) long RefPositions {#113@202 #122@223} physReg:NA Preferences=[rcx] Interval 45: (V77) byref RefPositions {#227@318 #229@323 #232@331} physReg:NA Preferences=[allInt] Interval 46: (V78) byref RefPositions {#381@520 #382@525 #384@533} physReg:NA Preferences=[allInt] Interval 47: (V79) long RefPositions {#378@516 #387@537} physReg:NA Preferences=[rcx] Interval 48: (V80) byref RefPositions {#447@574 #448@577 #451@585} physReg:NA Preferences=[allInt] Interval 49: (V81) byref RefPositions {#482@616 #483@621 #485@629} physReg:NA Preferences=[allInt] Interval 50: (V82) byref RefPositions {#524@668 #525@673 #527@681} physReg:NA Preferences=[allInt] Interval 51: (V83) byref RefPositions {#668@874 #669@879 #671@887} physReg:NA Preferences=[allInt] Interval 52: (V84) byref RefPositions {#665@870 #674@891} physReg:NA Preferences=[rcx] Interval 53: (V85) byref RefPositions {#732@952 #734@957 #737@965} physReg:NA Preferences=[allInt] Interval 54: (V87) byref RefPositions {#741@970 #743@975 #746@983} physReg:NA Preferences=[allInt] Interval 55: (V88) long RefPositions {#729@948 #749@987} physReg:NA Preferences=[rcx] Interval 56: (V89) byref RefPositions {#784@1006 #786@1011 #789@1019} physReg:NA Preferences=[allInt] Interval 57: (V90) byref RefPositions {#871@1128 #873@1133 #876@1141} physReg:NA Preferences=[allInt] Interval 58: ref RefPositions {#5@6 #6@7} physReg:NA Preferences=[allInt] RelatedInterval Interval 59: int RefPositions {#9@14 #10@15} physReg:NA Preferences=[allInt] RelatedInterval Interval 60: ref (specialPutArg) RefPositions {#18@40 #24@55} physReg:NA Preferences=[rcx] RelatedInterval Interval 61: long RefPositions {#20@46 #21@49} physReg:NA Preferences=[allInt] Interval 62: long RefPositions {#22@50 #25@55} physReg:NA Preferences=[allInt] Interval 63: long RefPositions {#34@56 #36@59} physReg:NA Preferences=[rax] Interval 64: int (constant) RefPositions {#37@62 #39@63} physReg:NA Preferences=[rax] Interval 65: ref (specialPutArg) RefPositions {#44@70 #50@85} physReg:NA Preferences=[rcx] RelatedInterval Interval 66: long RefPositions {#46@76 #47@79} physReg:NA Preferences=[allInt] Interval 67: long RefPositions {#48@80 #51@85} physReg:NA Preferences=[allInt] Interval 68: int RefPositions {#60@86 #61@89} physReg:NA Preferences=[rax] RelatedInterval Interval 69: int RefPositions {#62@90 #63@91} physReg:NA Preferences=[allInt] Interval 70: int RefPositions {#64@92 #65@95} physReg:NA Preferences=[allInt] RelatedInterval Interval 71: int RefPositions {#66@96 #67@97} physReg:NA Preferences=[allInt] RelatedInterval Interval 72: int (constant) RefPositions {#76@128 #77@129} physReg:NA Preferences=[allInt] RelatedInterval Interval 73: int RefPositions {#83@142 #84@143} physReg:NA Preferences=[allInt] RelatedInterval Interval 74: int (interfering uses) RefPositions {#97@172 #98@173} physReg:NA Preferences=[allInt] RelatedInterval Interval 75: int RefPositions {#103@186 #104@187} physReg:NA Preferences=[allInt] RelatedInterval Interval 76: int (interfering uses) RefPositions {#108@196 #109@197} physReg:NA Preferences=[allInt] RelatedInterval Interval 77: byref RefPositions {#111@200 #112@201} physReg:NA Preferences=[allInt] RelatedInterval Interval 78: byref RefPositions {#114@204 #115@205} physReg:NA Preferences=[allInt] RelatedInterval Interval 79: long RefPositions {#124@224 #140@237} physReg:NA Preferences=[rcx] Interval 80: byref RefPositions {#125@226 #127@227} physReg:NA Preferences=[rdx] Interval 81: byref RefPositions {#129@228 #142@237} physReg:NA Preferences=[rdx] Interval 82: int (specialPutArg) RefPositions {#133@232 #144@237} physReg:NA Preferences=[r9] RelatedInterval Interval 83: int (constant) RefPositions {#134@234 #136@235} physReg:NA Preferences=[r8] Interval 84: int RefPositions {#138@236 #146@237} physReg:NA Preferences=[r8] Interval 85: ref (specialPutArg) RefPositions {#159@254 #161@255} physReg:NA Preferences=[rcx] RelatedInterval Interval 86: int RefPositions {#170@256 #171@257} physReg:NA Preferences=[rax] Interval 87: long RefPositions {#172@258 #175@263} physReg:NA Preferences=[allInt] Interval 88: long RefPositions {#174@262 #176@263} physReg:NA Preferences=[allInt] Interval 89: ref (specialPutArg) RefPositions {#181@274 #187@289} physReg:NA Preferences=[rcx] RelatedInterval Interval 90: long RefPositions {#183@280 #184@283} physReg:NA Preferences=[allInt] Interval 91: long RefPositions {#185@284 #188@289} physReg:NA Preferences=[allInt] Interval 92: long RefPositions {#197@290 #199@293} physReg:NA Preferences=[rax] Interval 93: int (constant) RefPositions {#200@296 #202@297} physReg:NA Preferences=[rax] Interval 94: byref RefPositions {#204@304 #206@305} physReg:NA Preferences=[rcx] Interval 95: byref RefPositions {#208@306 #214@311} physReg:NA Preferences=[rcx] Interval 96: int RefPositions {#212@310 #216@311} physReg:NA Preferences=[rdx] Interval 97: byref RefPositions {#225@316 #226@317} physReg:NA Preferences=[allInt] RelatedInterval Interval 98: ref RefPositions {#228@322 #230@323} physReg:NA Preferences=[allInt] Interval 99: int RefPositions {#231@330 #233@331} physReg:NA Preferences=[allInt] Interval 100: byref RefPositions {#234@334 #236@335} physReg:NA Preferences=[rcx] Interval 101: byref RefPositions {#238@336 #245@341} physReg:NA Preferences=[rcx] Interval 102: long RefPositions {#239@338 #241@339} physReg:NA Preferences=[rdx] Interval 103: long RefPositions {#243@340 #247@341} physReg:NA Preferences=[rdx] Interval 104: int RefPositions {#256@342 #257@343} physReg:NA Preferences=[rax] RelatedInterval Interval 105: int RefPositions {#266@380 #268@381} physReg:NA Preferences=[r8] Interval 106: int RefPositions {#270@382 #285@395} physReg:NA Preferences=[r8] Interval 107: ref RefPositions {#271@384 #273@385} physReg:NA Preferences=[rcx] Interval 108: ref RefPositions {#275@386 #287@395} physReg:NA Preferences=[rcx] Interval 109: int RefPositions {#279@390 #289@395} physReg:NA Preferences=[rdx] Interval 110: ref RefPositions {#283@394 #291@395} physReg:NA Preferences=[r9] Interval 111: int RefPositions {#300@396 #301@397} physReg:NA Preferences=[rax] RelatedInterval Interval 112: int (interfering uses) RefPositions {#311@428 #312@429} physReg:NA Preferences=[allInt] RelatedInterval Interval 113: int RefPositions {#320@454 #321@455} physReg:NA Preferences=[allInt] Interval 114: long RefPositions {#322@456 #326@461} physReg:NA Preferences=[allInt] Interval 115: long RefPositions {#324@460 #325@461} physReg:NA Preferences=[allInt] RelatedInterval Interval 116: long (interfering uses) RefPositions {#327@462 #328@463} physReg:NA Preferences=[allInt] RelatedInterval Interval 117: ref (specialPutArg) RefPositions {#333@468 #335@469} physReg:NA Preferences=[rcx] RelatedInterval Interval 118: int RefPositions {#344@470 #345@471} physReg:NA Preferences=[rax] Interval 119: long RefPositions {#346@472 #347@475} physReg:NA Preferences=[allInt] Interval 120: ref (specialPutArg) RefPositions {#353@486 #359@501} physReg:NA Preferences=[rcx] RelatedInterval Interval 121: long RefPositions {#355@492 #356@495} physReg:NA Preferences=[allInt] Interval 122: long RefPositions {#357@496 #360@501} physReg:NA Preferences=[allInt] Interval 123: long RefPositions {#369@502 #371@505} physReg:NA Preferences=[rax] Interval 124: int (constant) RefPositions {#372@508 #374@509} physReg:NA Preferences=[rax] Interval 125: byref RefPositions {#376@514 #377@515} physReg:NA Preferences=[allInt] RelatedInterval Interval 126: byref RefPositions {#379@518 #380@519} physReg:NA Preferences=[allInt] RelatedInterval Interval 127: long RefPositions {#389@538 #404@551} physReg:NA Preferences=[rcx] Interval 128: byref RefPositions {#390@540 #392@541} physReg:NA Preferences=[rdx] Interval 129: byref RefPositions {#394@542 #406@551} physReg:NA Preferences=[rdx] Interval 130: int RefPositions {#398@546 #408@551} physReg:NA Preferences=[r8] Interval 131: int RefPositions {#402@550 #410@551} physReg:NA Preferences=[r9] Interval 132: long (constant) RefPositions {#418@556 #420@557} physReg:NA Preferences=[rcx] Interval 133: long RefPositions {#422@558 #429@563} physReg:NA Preferences=[rcx] Interval 134: int (constant) RefPositions {#423@560 #425@561} physReg:NA Preferences=[rdx] Interval 135: int RefPositions {#427@562 #431@563} physReg:NA Preferences=[rdx] Interval 136: long RefPositions {#440@564} physReg:NA Preferences=[rax] Interval 137: long (constant) RefPositions {#441@566 #442@567} physReg:NA Preferences=[allInt] Interval 138: ref RefPositions {#443@568 #444@571} physReg:NA Preferences=[allInt] RelatedInterval Interval 139: byref RefPositions {#445@572 #446@573} physReg:NA Preferences=[allInt] RelatedInterval Interval 140: ref RefPositions {#449@578 #450@579} physReg:NA Preferences=[allInt] Interval 141: int RefPositions {#452@586 #453@587} physReg:NA Preferences=[allInt] Interval 142: byref RefPositions {#454@592 #456@593} physReg:NA Preferences=[rcx] Interval 143: byref RefPositions {#458@594 #464@599} physReg:NA Preferences=[rcx] Interval 144: int RefPositions {#462@598 #466@599} physReg:NA Preferences=[rdx] Interval 145: ref RefPositions {#474@604 #475@605} physReg:NA Preferences=[allInt] RelatedInterval Interval 146: int RefPositions {#477@608 #478@609} physReg:NA Preferences=[allInt] RelatedInterval Interval 147: byref RefPositions {#480@614 #481@615} physReg:NA Preferences=[allInt] RelatedInterval Interval 148: byref RefPositions {#487@632 #489@633} physReg:NA Preferences=[rcx] Interval 149: byref RefPositions {#491@634 #498@639} physReg:NA Preferences=[rcx] Interval 150: long RefPositions {#492@636 #494@637} physReg:NA Preferences=[rdx] Interval 151: long RefPositions {#496@638 #500@639} physReg:NA Preferences=[rdx] Interval 152: int RefPositions {#509@640 #510@641} physReg:NA Preferences=[rax] RelatedInterval Interval 153: ref (constant) RefPositions {#512@646 #513@647} physReg:NA Preferences=[allInt] Interval 154: ref RefPositions {#516@656 #517@657} physReg:NA Preferences=[allInt] RelatedInterval Interval 155: int RefPositions {#519@660 #520@661} physReg:NA Preferences=[allInt] RelatedInterval Interval 156: byref RefPositions {#522@666 #523@667} physReg:NA Preferences=[allInt] RelatedInterval Interval 157: byref RefPositions {#529@684 #531@685} physReg:NA Preferences=[rcx] Interval 158: byref RefPositions {#533@686 #540@691} physReg:NA Preferences=[rcx] Interval 159: long RefPositions {#534@688 #536@689} physReg:NA Preferences=[rdx] Interval 160: long RefPositions {#538@690 #542@691} physReg:NA Preferences=[rdx] Interval 161: int RefPositions {#551@692 #552@693} physReg:NA Preferences=[rax] RelatedInterval Interval 162: ref (constant) RefPositions {#554@698 #555@699} physReg:NA Preferences=[allInt] Interval 163: int (constant) RefPositions {#561@720 #562@721} physReg:NA Preferences=[allInt] RelatedInterval Interval 164: int (interfering uses) RefPositions {#567@732 #568@733} physReg:NA Preferences=[allInt] RelatedInterval Interval 165: byref RefPositions {#575@756 #577@757} physReg:NA Preferences=[rcx] Interval 166: byref RefPositions {#579@758 #585@763} physReg:NA Preferences=[rcx] Interval 167: int (specialPutArg) RefPositions {#583@762 #587@763} physReg:NA Preferences=[rdx] RelatedInterval Interval 168: int (interfering uses) RefPositions {#598@774 #599@775} physReg:NA Preferences=[allInt] RelatedInterval Interval 169: int (constant) RefPositions {#609@814 #611@815} physReg:NA Preferences=[r8] Interval 170: int RefPositions {#613@816 #628@829} physReg:NA Preferences=[r8] Interval 171: ref RefPositions {#614@818 #616@819} physReg:NA Preferences=[rcx] Interval 172: ref RefPositions {#618@820 #630@829} physReg:NA Preferences=[rcx] Interval 173: int RefPositions {#622@824 #632@829} physReg:NA Preferences=[rdx] Interval 174: ref RefPositions {#626@828 #634@829} physReg:NA Preferences=[r9] Interval 175: int RefPositions {#643@830 #644@831} physReg:NA Preferences=[rax] RelatedInterval Interval 176: int (interfering uses) RefPositions {#649@842 #650@843} physReg:NA Preferences=[allInt] RelatedInterval Interval 177: ref RefPositions {#653@850 #654@851} physReg:NA Preferences=[allInt] Interval 178: int RefPositions {#655@854 #656@855} physReg:NA Preferences=[allInt] Interval 179: ref RefPositions {#657@860 #658@861} physReg:NA Preferences=[allInt] RelatedInterval Interval 180: int RefPositions {#660@864 #661@865} physReg:NA Preferences=[allInt] RelatedInterval Interval 181: byref RefPositions {#663@868 #664@869} physReg:NA Preferences=[allInt] RelatedInterval Interval 182: byref RefPositions {#666@872 #667@873} physReg:NA Preferences=[allInt] RelatedInterval Interval 183: byref RefPositions {#676@892 #683@897} physReg:NA Preferences=[rcx] Interval 184: byref RefPositions {#677@894 #679@895} physReg:NA Preferences=[rdx] Interval 185: byref RefPositions {#681@896 #685@897} physReg:NA Preferences=[rdx] Interval 186: int RefPositions {#694@898 #695@901} physReg:NA Preferences=[rax] Interval 187: int RefPositions {#701@922 #702@923} physReg:NA Preferences=[allInt] RelatedInterval Interval 188: byref RefPositions {#707@934 #709@935} physReg:NA Preferences=[rcx] Interval 189: byref RefPositions {#711@936 #717@941} physReg:NA Preferences=[rcx] Interval 190: int RefPositions {#715@940 #719@941} physReg:NA Preferences=[rdx] Interval 191: byref RefPositions {#727@946 #728@947} physReg:NA Preferences=[allInt] RelatedInterval Interval 192: byref RefPositions {#730@950 #731@951} physReg:NA Preferences=[allInt] RelatedInterval Interval 193: ref RefPositions {#733@956 #735@957} physReg:NA Preferences=[allInt] Interval 194: int RefPositions {#736@964 #738@965} physReg:NA Preferences=[allInt] Interval 195: byref RefPositions {#739@968 #740@969} physReg:NA Preferences=[allInt] RelatedInterval Interval 196: ref RefPositions {#742@974 #744@975} physReg:NA Preferences=[allInt] Interval 197: int RefPositions {#745@982 #747@983} physReg:NA Preferences=[allInt] Interval 198: long RefPositions {#751@988 #768@1001} physReg:NA Preferences=[rcx] Interval 199: byref RefPositions {#752@990 #754@991} physReg:NA Preferences=[rdx] Interval 200: byref RefPositions {#756@992 #770@1001} physReg:NA Preferences=[rdx] Interval 201: byref RefPositions {#757@994 #759@995} physReg:NA Preferences=[r8] Interval 202: byref RefPositions {#761@996 #772@1001} physReg:NA Preferences=[r8] Interval 203: byref RefPositions {#762@998 #764@999} physReg:NA Preferences=[r9] Interval 204: byref RefPositions {#766@1000 #774@1001} physReg:NA Preferences=[r9] Interval 205: byref RefPositions {#782@1004 #783@1005} physReg:NA Preferences=[allInt] RelatedInterval Interval 206: ref RefPositions {#785@1010 #787@1011} physReg:NA Preferences=[allInt] Interval 207: int RefPositions {#788@1018 #790@1019} physReg:NA Preferences=[allInt] Interval 208: byref RefPositions {#791@1022 #793@1023} physReg:NA Preferences=[rcx] Interval 209: byref RefPositions {#795@1024 #797@1025} physReg:NA Preferences=[rcx] Interval 210: long RefPositions {#806@1026 #807@1027} physReg:NA Preferences=[rax] RelatedInterval Interval 211: int RefPositions {#809@1034 #810@1035} physReg:NA Preferences=[allInt] RelatedInterval Interval 212: long (specialPutArg) RefPositions {#815@1040 #817@1041} physReg:NA Preferences=[rcx] RelatedInterval Interval 213: int RefPositions {#826@1042 #827@1043} physReg:NA Preferences=[rax] RelatedInterval Interval 214: int (interfering uses) RefPositions {#834@1064 #835@1065} physReg:NA Preferences=[allInt] RelatedInterval Interval 215: long (constant) RefPositions {#839@1086 #840@1087} physReg:NA Preferences=[rax rdx rbx rbp rsi rdi r8-r15] RelatedInterval Interval 216: long (interfering uses) RefPositions {#844@1088 #845@1091} physReg:NA Preferences=[rax rdx rbx rbp rsi rdi r8-r15] RelatedInterval Interval 217: long RefPositions {#846@1092 #848@1093} physReg:NA Preferences=[allInt] Interval 218: int RefPositions {#849@1094 #850@1095} physReg:NA Preferences=[allInt] RelatedInterval Interval 219: int (constant) RefPositions {#853@1102 #854@1103} physReg:NA Preferences=[allInt] RelatedInterval Interval 220: int RefPositions {#858@1110 #859@1111} physReg:NA Preferences=[allInt] RelatedInterval Interval 221: long (interfering uses) RefPositions {#865@1120 #866@1121} physReg:NA Preferences=[rax rdx rbx rbp rsi rdi r8-r15] RelatedInterval Interval 222: byref RefPositions {#869@1126 #870@1127} physReg:NA Preferences=[allInt] RelatedInterval Interval 223: ref RefPositions {#872@1132 #874@1133} physReg:NA Preferences=[allInt] Interval 224: int RefPositions {#875@1140 #877@1141} physReg:NA Preferences=[allInt] Interval 225: byref RefPositions {#878@1144 #880@1145} physReg:NA Preferences=[rcx] Interval 226: byref RefPositions {#882@1146 #884@1147} physReg:NA Preferences=[rcx] Interval 227: long RefPositions {#893@1148 #894@1151} physReg:NA Preferences=[rax] RelatedInterval Interval 228: long (interfering uses) RefPositions {#898@1152 #899@1155} physReg:NA Preferences=[rax rdx rbx rbp rsi rdi r8-r15] RelatedInterval Interval 229: long RefPositions {#901@1156 #902@1157} physReg:NA Preferences=[allInt] RelatedInterval Interval 230: int RefPositions {#907@1176 #908@1179} physReg:NA Preferences=[allInt] RelatedInterval Interval 231: int RefPositions {#909@1180 #910@1181} physReg:NA Preferences=[allInt] RelatedInterval Interval 232: int RefPositions {#914@1192 #915@1193} physReg:NA Preferences=[allInt] RelatedInterval Interval 233: ref RefPositions {#922@1206 #936@1219} physReg:NA Preferences=[rcx] Interval 234: long RefPositions {#926@1210 #938@1219} physReg:NA Preferences=[rdx] Interval 235: int RefPositions {#930@1214 #940@1219} physReg:NA Preferences=[r8] Interval 236: int RefPositions {#934@1218 #942@1219} physReg:NA Preferences=[r9] Interval 237: int RefPositions {#951@1220 #952@1221} physReg:NA Preferences=[rax] RelatedInterval ------------ REFPOSITIONS BEFORE VALIDATING INTERVALS: ------------ BB00 regmask=[rdx] minReg=1 fixed regOptional> BB00 regmask=[rcx] minReg=1 fixed regOptional> BB00 regmask=[r8] minReg=1 fixed regOptional> LCL_VAR BB01 regmask=[allInt] minReg=1> IND BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> IND BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1> BB03 regmask=[rcx] minReg=1> LCL_VAR BB03 regmask=[rcx] minReg=1 fixed> BB03 regmask=[rcx] minReg=1> PUTARG_REG BB03 regmask=[rcx] minReg=1 fixed> LCL_VAR BB03 regmask=[allInt] minReg=1 last> IND BB03 regmask=[allInt] minReg=1> BB03 regmask=[allInt] minReg=1 last> IND BB03 regmask=[allInt] minReg=1> BB03 regmask=[rcx] minReg=1> BB03 regmask=[rcx] minReg=1 last fixed> BB03 regmask=[allInt] minReg=1 last> BB03 regmask=[rax] minReg=1 last> BB03 regmask=[rcx] minReg=1 last> BB03 regmask=[rdx] minReg=1 last> BB03 regmask=[r8] minReg=1 last> BB03 regmask=[r9] minReg=1 last> BB03 regmask=[r10] minReg=1 last> BB03 regmask=[r11] minReg=1 last> BB03 regmask=[rax] minReg=1> CALL BB03 regmask=[rax] minReg=1 fixed> LCL_VAR BB03 regmask=[allInt] minReg=1 last> BB03 regmask=[allInt] minReg=1 last> CNS_INT BB03 regmask=[rax] minReg=1> BB03 regmask=[rax] minReg=1> BB03 regmask=[rax] minReg=1 last fixed> BB04 regmask=[rcx] minReg=1> LCL_VAR BB04 regmask=[rcx] minReg=1 fixed> BB04 regmask=[rcx] minReg=1> PUTARG_REG BB04 regmask=[rcx] minReg=1 fixed> LCL_VAR BB04 regmask=[allInt] minReg=1> IND BB04 regmask=[allInt] minReg=1> BB04 regmask=[allInt] minReg=1 last> IND BB04 regmask=[allInt] minReg=1> BB04 regmask=[rcx] minReg=1> BB04 regmask=[rcx] minReg=1 last fixed> BB04 regmask=[allInt] minReg=1 last> BB04 regmask=[rax] minReg=1 last> BB04 regmask=[rcx] minReg=1 last> BB04 regmask=[rdx] minReg=1 last> BB04 regmask=[r8] minReg=1 last> BB04 regmask=[r9] minReg=1 last> BB04 regmask=[r10] minReg=1 last> BB04 regmask=[r11] minReg=1 last> BB04 regmask=[rax] minReg=1> CALL BB04 regmask=[rax] minReg=1 fixed> BB04 regmask=[allInt] minReg=1 last> ADD BB04 regmask=[allInt] minReg=1> BB04 regmask=[allInt] minReg=1 last> CAST BB04 regmask=[allInt] minReg=1> BB04 regmask=[allInt] minReg=1 last> ADD BB04 regmask=[allInt] minReg=1> BB04 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1> LCL_VAR BB04 regmask=[allInt] minReg=1> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1> LCL_VAR BB04 regmask=[allInt] minReg=1 last regOptional> LCL_VAR BB05 regmask=[allInt] minReg=1> STORE_LCL_VAR BB05 regmask=[allInt] minReg=1> CNS_INT BB06 regmask=[allInt] minReg=1> BB06 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1> LCL_VAR BB07 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB07 regmask=[allInt] minReg=1> LCL_VAR BB07 regmask=[allInt] minReg=1> IND BB07 regmask=[allInt] minReg=1> BB07 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB07 regmask=[allInt] minReg=1> LCL_VAR BB07 regmask=[allInt] minReg=1> LCL_VAR BB07 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB08 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB08 regmask=[allInt] minReg=1> LCL_VAR BB09 regmask=[allInt] minReg=1> STORE_LCL_VAR BB09 regmask=[allInt] minReg=1> LCL_VAR BB10 regmask=[allInt] minReg=1 last> LCL_VAR BB10 regmask=[allInt] minReg=1 delay regOptional> SUB BB10 regmask=[allInt] minReg=1> BB10 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR BB10 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR BB10 regmask=[allInt] minReg=1> IND BB10 regmask=[allInt] minReg=1> BB10 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR BB10 regmask=[allInt] minReg=1 delay regOptional> SUB BB10 regmask=[allInt] minReg=1> BB10 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR_ADDR BB10 regmask=[allInt] minReg=1> BB10 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR_ADDR BB10 regmask=[allInt] minReg=1> BB10 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR BB10 regmask=[allInt] minReg=1 last> LCL_VAR BB10 regmask=[allInt] minReg=1> BB10 regmask=[rcx] minReg=1> LCL_VAR BB10 regmask=[rcx] minReg=1 last fixed> BB10 regmask=[rcx] minReg=1> PUTARG_REG BB10 regmask=[rcx] minReg=1 fixed> LCL_VAR_ADDR BB10 regmask=[rdx] minReg=1> BB10 regmask=[rdx] minReg=1> BB10 regmask=[rdx] minReg=1 last fixed> BB10 regmask=[rdx] minReg=1> PUTARG_REG BB10 regmask=[rdx] minReg=1 fixed> BB10 regmask=[r9] minReg=1> LCL_VAR BB10 regmask=[r9] minReg=1 fixed> BB10 regmask=[r9] minReg=1> PUTARG_REG BB10 regmask=[r9] minReg=1 fixed> CNS_INT BB10 regmask=[r8] minReg=1> BB10 regmask=[r8] minReg=1> BB10 regmask=[r8] minReg=1 last fixed> BB10 regmask=[r8] minReg=1> PUTARG_REG BB10 regmask=[r8] minReg=1 fixed> BB10 regmask=[rcx] minReg=1> BB10 regmask=[rcx] minReg=1 last fixed> BB10 regmask=[rdx] minReg=1> BB10 regmask=[rdx] minReg=1 last fixed> BB10 regmask=[r9] minReg=1> BB10 regmask=[r9] minReg=1 last fixed> BB10 regmask=[r8] minReg=1> BB10 regmask=[r8] minReg=1 last fixed> BB10 regmask=[rax] minReg=1 last> BB10 regmask=[rcx] minReg=1 last> BB10 regmask=[rdx] minReg=1 last> BB10 regmask=[r8] minReg=1 last> BB10 regmask=[r9] minReg=1 last> BB10 regmask=[r10] minReg=1 last> BB10 regmask=[r11] minReg=1 last> LCL_VAR BB10 regmask=[allInt] minReg=1 regOptional> BB11 regmask=[rcx] minReg=1> LCL_VAR BB11 regmask=[rcx] minReg=1 fixed> BB11 regmask=[rcx] minReg=1> PUTARG_REG BB11 regmask=[rcx] minReg=1 fixed> BB11 regmask=[rcx] minReg=1> BB11 regmask=[rcx] minReg=1 last fixed> BB11 regmask=[rax] minReg=1 last> BB11 regmask=[rcx] minReg=1 last> BB11 regmask=[rdx] minReg=1 last> BB11 regmask=[r8] minReg=1 last> BB11 regmask=[r9] minReg=1 last> BB11 regmask=[r10] minReg=1 last> BB11 regmask=[r11] minReg=1 last> BB11 regmask=[rax] minReg=1> CALL BB11 regmask=[rax] minReg=1 fixed> BB11 regmask=[allInt] minReg=1 last> CAST BB11 regmask=[allInt] minReg=1> LCL_VAR BB11 regmask=[allInt] minReg=1> CAST BB11 regmask=[allInt] minReg=1> BB11 regmask=[allInt] minReg=1 last regOptional> BB11 regmask=[allInt] minReg=1 last> BB12 regmask=[rcx] minReg=1> LCL_VAR BB12 regmask=[rcx] minReg=1 fixed> BB12 regmask=[rcx] minReg=1> PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed> LCL_VAR BB12 regmask=[allInt] minReg=1 last> IND BB12 regmask=[allInt] minReg=1> BB12 regmask=[allInt] minReg=1 last> IND BB12 regmask=[allInt] minReg=1> BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> BB12 regmask=[allInt] minReg=1 last> BB12 regmask=[rax] minReg=1 last> BB12 regmask=[rcx] minReg=1 last> BB12 regmask=[rdx] minReg=1 last> BB12 regmask=[r8] minReg=1 last> BB12 regmask=[r9] minReg=1 last> BB12 regmask=[r10] minReg=1 last> BB12 regmask=[r11] minReg=1 last> BB12 regmask=[rax] minReg=1> CALL BB12 regmask=[rax] minReg=1 fixed> LCL_VAR BB12 regmask=[allInt] minReg=1 last> BB12 regmask=[allInt] minReg=1 last> CNS_INT BB12 regmask=[rax] minReg=1> BB12 regmask=[rax] minReg=1> BB12 regmask=[rax] minReg=1 last fixed> LCL_VAR_ADDR BB13 regmask=[rcx] minReg=1> BB13 regmask=[rcx] minReg=1> BB13 regmask=[rcx] minReg=1 last fixed> BB13 regmask=[rcx] minReg=1> PUTARG_REG BB13 regmask=[rcx] minReg=1 fixed> BB13 regmask=[rdx] minReg=1> LCL_VAR BB13 regmask=[rdx] minReg=1 last fixed> BB13 regmask=[rdx] minReg=1> PUTARG_REG BB13 regmask=[rdx] minReg=1 fixed> BB13 regmask=[rcx] minReg=1> BB13 regmask=[rcx] minReg=1 last fixed> BB13 regmask=[rdx] minReg=1> BB13 regmask=[rdx] minReg=1 last fixed> BB13 regmask=[rax] minReg=1 last> BB13 regmask=[rcx] minReg=1 last> BB13 regmask=[rdx] minReg=1 last> BB13 regmask=[r8] minReg=1 last> BB13 regmask=[r9] minReg=1 last> BB13 regmask=[r10] minReg=1 last> BB13 regmask=[r11] minReg=1 last> LCL_VAR_ADDR BB14 regmask=[allInt] minReg=1> BB14 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1> BB14 regmask=[allInt] minReg=1 last> LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1 last> BB14 regmask=[allInt] minReg=1 last> LCL_VAR_ADDR BB14 regmask=[rcx] minReg=1> BB14 regmask=[rcx] minReg=1> BB14 regmask=[rcx] minReg=1 last fixed> BB14 regmask=[rcx] minReg=1> PUTARG_REG BB14 regmask=[rcx] minReg=1 fixed> LCL_VAR_ADDR BB14 regmask=[rdx] minReg=1> BB14 regmask=[rdx] minReg=1> BB14 regmask=[rdx] minReg=1 last fixed> BB14 regmask=[rdx] minReg=1> PUTARG_REG BB14 regmask=[rdx] minReg=1 fixed> BB14 regmask=[rcx] minReg=1> BB14 regmask=[rcx] minReg=1 last fixed> BB14 regmask=[rdx] minReg=1> BB14 regmask=[rdx] minReg=1 last fixed> BB14 regmask=[rax] minReg=1 last> BB14 regmask=[rcx] minReg=1 last> BB14 regmask=[rdx] minReg=1 last> BB14 regmask=[r8] minReg=1 last> BB14 regmask=[r9] minReg=1 last> BB14 regmask=[r10] minReg=1 last> BB14 regmask=[r11] minReg=1 last> BB14 regmask=[rax] minReg=1> CALL BB14 regmask=[rax] minReg=1 fixed> BB14 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB15 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB16 regmask=[allInt] minReg=1 last> LCL_VAR BB16 regmask=[allInt] minReg=1 last regOptional> NE BB16 regmask=[r8] minReg=1> BB16 regmask=[r8] minReg=1> BB16 regmask=[r8] minReg=1 last fixed> BB16 regmask=[r8] minReg=1> PUTARG_REG BB16 regmask=[r8] minReg=1 fixed> LCL_VAR BB16 regmask=[rcx] minReg=1> BB16 regmask=[rcx] minReg=1> BB16 regmask=[rcx] minReg=1 last fixed> BB16 regmask=[rcx] minReg=1> PUTARG_REG BB16 regmask=[rcx] minReg=1 fixed> BB16 regmask=[rdx] minReg=1> LCL_VAR BB16 regmask=[rdx] minReg=1 last fixed> BB16 regmask=[rdx] minReg=1> PUTARG_REG BB16 regmask=[rdx] minReg=1 fixed> BB16 regmask=[r9] minReg=1> LCL_VAR BB16 regmask=[r9] minReg=1 last fixed> BB16 regmask=[r9] minReg=1> PUTARG_REG BB16 regmask=[r9] minReg=1 fixed> BB16 regmask=[r8] minReg=1> BB16 regmask=[r8] minReg=1 last fixed> BB16 regmask=[rcx] minReg=1> BB16 regmask=[rcx] minReg=1 last fixed> BB16 regmask=[rdx] minReg=1> BB16 regmask=[rdx] minReg=1 last fixed> BB16 regmask=[r9] minReg=1> BB16 regmask=[r9] minReg=1 last fixed> BB16 regmask=[rax] minReg=1 last> BB16 regmask=[rcx] minReg=1 last> BB16 regmask=[rdx] minReg=1 last> BB16 regmask=[r8] minReg=1 last> BB16 regmask=[r9] minReg=1 last> BB16 regmask=[r10] minReg=1 last> BB16 regmask=[r11] minReg=1 last> BB16 regmask=[rax] minReg=1> CALL BB16 regmask=[rax] minReg=1 fixed> BB16 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB16 regmask=[allInt] minReg=1> LCL_VAR BB17 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB18 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB18 regmask=[allInt] minReg=1> LCL_VAR BB19 regmask=[allInt] minReg=1 last> LCL_VAR BB19 regmask=[allInt] minReg=1 delay regOptional> SUB BB19 regmask=[allInt] minReg=1> BB19 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB19 regmask=[allInt] minReg=1> LCL_VAR BB20 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB20 regmask=[allInt] minReg=1> LCL_VAR BB20 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB21 regmask=[allInt] minReg=1> IND BB21 regmask=[allInt] minReg=1> BB21 regmask=[allInt] minReg=1 last> CAST BB21 regmask=[allInt] minReg=1> LCL_VAR BB21 regmask=[allInt] minReg=1> CAST BB21 regmask=[allInt] minReg=1> BB21 regmask=[allInt] minReg=1 last> BB21 regmask=[allInt] minReg=1 last delay regOptional> SUB BB21 regmask=[allInt] minReg=1> BB21 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB21 regmask=[allInt] minReg=1> BB21 regmask=[rcx] minReg=1> LCL_VAR BB21 regmask=[rcx] minReg=1 fixed> BB21 regmask=[rcx] minReg=1> PUTARG_REG BB21 regmask=[rcx] minReg=1 fixed> BB21 regmask=[rcx] minReg=1> BB21 regmask=[rcx] minReg=1 last fixed> BB21 regmask=[rax] minReg=1 last> BB21 regmask=[rcx] minReg=1 last> BB21 regmask=[rdx] minReg=1 last> BB21 regmask=[r8] minReg=1 last> BB21 regmask=[r9] minReg=1 last> BB21 regmask=[r10] minReg=1 last> BB21 regmask=[r11] minReg=1 last> BB21 regmask=[rax] minReg=1> CALL BB21 regmask=[rax] minReg=1 fixed> BB21 regmask=[allInt] minReg=1 last> CAST BB21 regmask=[allInt] minReg=1> BB21 regmask=[allInt] minReg=1 last> LCL_VAR BB21 regmask=[allInt] minReg=1 last regOptional> BB22 regmask=[rcx] minReg=1> LCL_VAR BB22 regmask=[rcx] minReg=1 fixed> BB22 regmask=[rcx] minReg=1> PUTARG_REG BB22 regmask=[rcx] minReg=1 fixed> LCL_VAR BB22 regmask=[allInt] minReg=1 last> IND BB22 regmask=[allInt] minReg=1> BB22 regmask=[allInt] minReg=1 last> IND BB22 regmask=[allInt] minReg=1> BB22 regmask=[rcx] minReg=1> BB22 regmask=[rcx] minReg=1 last fixed> BB22 regmask=[allInt] minReg=1 last> BB22 regmask=[rax] minReg=1 last> BB22 regmask=[rcx] minReg=1 last> BB22 regmask=[rdx] minReg=1 last> BB22 regmask=[r8] minReg=1 last> BB22 regmask=[r9] minReg=1 last> BB22 regmask=[r10] minReg=1 last> BB22 regmask=[r11] minReg=1 last> BB22 regmask=[rax] minReg=1> CALL BB22 regmask=[rax] minReg=1 fixed> LCL_VAR BB22 regmask=[allInt] minReg=1 last> BB22 regmask=[allInt] minReg=1 last> CNS_INT BB22 regmask=[rax] minReg=1> BB22 regmask=[rax] minReg=1> BB22 regmask=[rax] minReg=1 last fixed> LCL_VAR_ADDR BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR_ADDR BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 last> LCL_VAR BB23 regmask=[allInt] minReg=1 last> LCL_VAR BB23 regmask=[allInt] minReg=1 last> BB23 regmask=[rcx] minReg=1> LCL_VAR BB23 regmask=[rcx] minReg=1 last fixed> BB23 regmask=[rcx] minReg=1> PUTARG_REG BB23 regmask=[rcx] minReg=1 fixed> LCL_VAR_ADDR BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last fixed> BB23 regmask=[rdx] minReg=1> PUTARG_REG BB23 regmask=[rdx] minReg=1 fixed> BB23 regmask=[r8] minReg=1> LCL_VAR BB23 regmask=[r8] minReg=1 last fixed> BB23 regmask=[r8] minReg=1> PUTARG_REG BB23 regmask=[r8] minReg=1 fixed> BB23 regmask=[r9] minReg=1> LCL_VAR BB23 regmask=[r9] minReg=1 last fixed> BB23 regmask=[r9] minReg=1> PUTARG_REG BB23 regmask=[r9] minReg=1 fixed> BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last fixed> BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last fixed> BB23 regmask=[r8] minReg=1> BB23 regmask=[r8] minReg=1 last fixed> BB23 regmask=[r9] minReg=1> BB23 regmask=[r9] minReg=1 last fixed> BB23 regmask=[rax] minReg=1 last> BB23 regmask=[rcx] minReg=1 last> BB23 regmask=[rdx] minReg=1 last> BB23 regmask=[r8] minReg=1 last> BB23 regmask=[r9] minReg=1 last> BB23 regmask=[r10] minReg=1 last> BB23 regmask=[r11] minReg=1 last> CNS_INT BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last fixed> BB23 regmask=[rcx] minReg=1> PUTARG_REG BB23 regmask=[rcx] minReg=1 fixed> CNS_INT BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last fixed> BB23 regmask=[rdx] minReg=1> PUTARG_REG BB23 regmask=[rdx] minReg=1 fixed> BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last fixed> BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last fixed> BB23 regmask=[rax] minReg=1 last> BB23 regmask=[rcx] minReg=1 last> BB23 regmask=[rdx] minReg=1 last> BB23 regmask=[r8] minReg=1 last> BB23 regmask=[r9] minReg=1 last> BB23 regmask=[r10] minReg=1 last> BB23 regmask=[r11] minReg=1 last> BB23 regmask=[rax] minReg=1> CALL BB23 regmask=[rax] minReg=1 last fixed local> CNS_INT BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 last> IND BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 last> ADD BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1> IND BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 last> LCL_VAR BB23 regmask=[allInt] minReg=1 last> IND BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 last> LCL_VAR_ADDR BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last fixed> BB23 regmask=[rcx] minReg=1> PUTARG_REG BB23 regmask=[rcx] minReg=1 fixed> BB23 regmask=[rdx] minReg=1> LCL_VAR BB23 regmask=[rdx] minReg=1 last fixed> BB23 regmask=[rdx] minReg=1> PUTARG_REG BB23 regmask=[rdx] minReg=1 fixed> BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last fixed> BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last fixed> BB23 regmask=[rax] minReg=1 last> BB23 regmask=[rcx] minReg=1 last> BB23 regmask=[rdx] minReg=1 last> BB23 regmask=[r8] minReg=1 last> BB23 regmask=[r9] minReg=1 last> BB23 regmask=[r10] minReg=1 last> BB23 regmask=[r11] minReg=1 last> LCL_VAR BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR_ADDR BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 last> LCL_VAR BB23 regmask=[allInt] minReg=1 last> LCL_VAR BB23 regmask=[allInt] minReg=1 last> LCL_VAR_ADDR BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last fixed> BB23 regmask=[rcx] minReg=1> PUTARG_REG BB23 regmask=[rcx] minReg=1 fixed> LCL_VAR_ADDR BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last fixed> BB23 regmask=[rdx] minReg=1> PUTARG_REG BB23 regmask=[rdx] minReg=1 fixed> BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last fixed> BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last fixed> BB23 regmask=[rax] minReg=1 last> BB23 regmask=[rcx] minReg=1 last> BB23 regmask=[rdx] minReg=1 last> BB23 regmask=[r8] minReg=1 last> BB23 regmask=[r9] minReg=1 last> BB23 regmask=[r10] minReg=1 last> BB23 regmask=[r11] minReg=1 last> BB23 regmask=[rax] minReg=1> CALL BB23 regmask=[rax] minReg=1 fixed> BB23 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> CNS_INT BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 last> LCL_VAR BB23 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR_ADDR BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 last> LCL_VAR BB23 regmask=[allInt] minReg=1 last> LCL_VAR BB23 regmask=[allInt] minReg=1 last> LCL_VAR_ADDR BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last fixed> BB23 regmask=[rcx] minReg=1> PUTARG_REG BB23 regmask=[rcx] minReg=1 fixed> LCL_VAR_ADDR BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last fixed> BB23 regmask=[rdx] minReg=1> PUTARG_REG BB23 regmask=[rdx] minReg=1 fixed> BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last fixed> BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last fixed> BB23 regmask=[rax] minReg=1 last> BB23 regmask=[rcx] minReg=1 last> BB23 regmask=[rdx] minReg=1 last> BB23 regmask=[r8] minReg=1 last> BB23 regmask=[r9] minReg=1 last> BB23 regmask=[r10] minReg=1 last> BB23 regmask=[r11] minReg=1 last> BB23 regmask=[rax] minReg=1> CALL BB23 regmask=[rax] minReg=1 fixed> BB23 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> CNS_INT BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 last> LCL_VAR BB23 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 regOptional> CNS_INT BB24 regmask=[allInt] minReg=1> BB24 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB24 regmask=[allInt] minReg=1> LCL_VAR BB25 regmask=[allInt] minReg=1 last> LCL_VAR BB25 regmask=[allInt] minReg=1 last delay regOptional> SUB BB25 regmask=[allInt] minReg=1> BB25 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB25 regmask=[allInt] minReg=1> LCL_VAR BB26 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB26 regmask=[allInt] minReg=1> LCL_VAR BB26 regmask=[allInt] minReg=1 regOptional> LCL_VAR_ADDR BB27 regmask=[rcx] minReg=1> BB27 regmask=[rcx] minReg=1> BB27 regmask=[rcx] minReg=1 last fixed> BB27 regmask=[rcx] minReg=1> PUTARG_REG BB27 regmask=[rcx] minReg=1 fixed> BB27 regmask=[rdx] minReg=1> LCL_VAR BB27 regmask=[rdx] minReg=1 fixed> BB27 regmask=[rdx] minReg=1> PUTARG_REG BB27 regmask=[rdx] minReg=1 fixed> BB27 regmask=[rcx] minReg=1> BB27 regmask=[rcx] minReg=1 last fixed> BB27 regmask=[rdx] minReg=1> BB27 regmask=[rdx] minReg=1 last fixed> BB27 regmask=[rax] minReg=1 last> BB27 regmask=[rcx] minReg=1 last> BB27 regmask=[rdx] minReg=1 last> BB27 regmask=[r8] minReg=1 last> BB27 regmask=[r9] minReg=1 last> BB27 regmask=[r10] minReg=1 last> BB27 regmask=[r11] minReg=1 last> LCL_VAR BB28 regmask=[allInt] minReg=1 last> LCL_VAR BB28 regmask=[allInt] minReg=1 delay regOptional> SUB BB28 regmask=[allInt] minReg=1> BB28 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB28 regmask=[allInt] minReg=1> LCL_VAR BB28 regmask=[allInt] minReg=1> STORE_LCL_VAR BB28 regmask=[allInt] minReg=1> LCL_VAR BB28 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB29 regmask=[allInt] minReg=1> LCL_VAR BB29 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB30 regmask=[allInt] minReg=1 last> CNS_INT BB30 regmask=[r8] minReg=1> BB30 regmask=[r8] minReg=1> BB30 regmask=[r8] minReg=1 last fixed> BB30 regmask=[r8] minReg=1> PUTARG_REG BB30 regmask=[r8] minReg=1 fixed> LCL_VAR BB30 regmask=[rcx] minReg=1> BB30 regmask=[rcx] minReg=1> BB30 regmask=[rcx] minReg=1 last fixed> BB30 regmask=[rcx] minReg=1> PUTARG_REG BB30 regmask=[rcx] minReg=1 fixed> BB30 regmask=[rdx] minReg=1> LCL_VAR BB30 regmask=[rdx] minReg=1 last fixed> BB30 regmask=[rdx] minReg=1> PUTARG_REG BB30 regmask=[rdx] minReg=1 fixed> BB30 regmask=[r9] minReg=1> LCL_VAR BB30 regmask=[r9] minReg=1 last fixed> BB30 regmask=[r9] minReg=1> PUTARG_REG BB30 regmask=[r9] minReg=1 fixed> BB30 regmask=[r8] minReg=1> BB30 regmask=[r8] minReg=1 last fixed> BB30 regmask=[rcx] minReg=1> BB30 regmask=[rcx] minReg=1 last fixed> BB30 regmask=[rdx] minReg=1> BB30 regmask=[rdx] minReg=1 last fixed> BB30 regmask=[r9] minReg=1> BB30 regmask=[r9] minReg=1 last fixed> BB30 regmask=[rax] minReg=1 last> BB30 regmask=[rcx] minReg=1 last> BB30 regmask=[rdx] minReg=1 last> BB30 regmask=[r8] minReg=1 last> BB30 regmask=[r9] minReg=1 last> BB30 regmask=[r10] minReg=1 last> BB30 regmask=[r11] minReg=1 last> BB30 regmask=[rax] minReg=1> CALL BB30 regmask=[rax] minReg=1 fixed> BB30 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB30 regmask=[allInt] minReg=1> LCL_VAR BB31 regmask=[allInt] minReg=1> LCL_VAR BB31 regmask=[allInt] minReg=1 delay regOptional> SUB BB31 regmask=[allInt] minReg=1> BB31 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB31 regmask=[allInt] minReg=1> LCL_VAR BB32 regmask=[allInt] minReg=1> BB32 regmask=[allInt] minReg=1 last> LCL_VAR BB32 regmask=[allInt] minReg=1> BB32 regmask=[allInt] minReg=1 last> LCL_VAR BB32 regmask=[allInt] minReg=1> BB32 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR BB32 regmask=[allInt] minReg=1> BB32 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR_ADDR BB32 regmask=[allInt] minReg=1> BB32 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR_ADDR BB32 regmask=[allInt] minReg=1> BB32 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR BB32 regmask=[allInt] minReg=1 last> LCL_VAR BB32 regmask=[allInt] minReg=1 last> LCL_VAR BB32 regmask=[allInt] minReg=1 last> BB32 regmask=[rcx] minReg=1> LCL_VAR BB32 regmask=[rcx] minReg=1 last fixed> BB32 regmask=[rcx] minReg=1> PUTARG_REG BB32 regmask=[rcx] minReg=1 fixed> LCL_VAR_ADDR BB32 regmask=[rdx] minReg=1> BB32 regmask=[rdx] minReg=1> BB32 regmask=[rdx] minReg=1 last fixed> BB32 regmask=[rdx] minReg=1> PUTARG_REG BB32 regmask=[rdx] minReg=1 fixed> BB32 regmask=[rcx] minReg=1> BB32 regmask=[rcx] minReg=1 last fixed> BB32 regmask=[rdx] minReg=1> BB32 regmask=[rdx] minReg=1 last fixed> BB32 regmask=[rax] minReg=1 last> BB32 regmask=[rcx] minReg=1 last> BB32 regmask=[rdx] minReg=1 last> BB32 regmask=[r8] minReg=1 last> BB32 regmask=[r9] minReg=1 last> BB32 regmask=[r10] minReg=1 last> BB32 regmask=[r11] minReg=1 last> BB32 regmask=[rax] minReg=1> CALL BB32 regmask=[rax] minReg=1 fixed> BB32 regmask=[allInt] minReg=1 last regOptional> LCL_VAR BB33 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB33 regmask=[allInt] minReg=1> LCL_VAR BB34 regmask=[allInt] minReg=1 last> ADD BB34 regmask=[allInt] minReg=1> BB34 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB34 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR_ADDR BB35 regmask=[rcx] minReg=1> BB35 regmask=[rcx] minReg=1> BB35 regmask=[rcx] minReg=1 last fixed> BB35 regmask=[rcx] minReg=1> PUTARG_REG BB35 regmask=[rcx] minReg=1 fixed> BB35 regmask=[rdx] minReg=1> LCL_VAR BB35 regmask=[rdx] minReg=1 last fixed> BB35 regmask=[rdx] minReg=1> PUTARG_REG BB35 regmask=[rdx] minReg=1 fixed> BB35 regmask=[rcx] minReg=1> BB35 regmask=[rcx] minReg=1 last fixed> BB35 regmask=[rdx] minReg=1> BB35 regmask=[rdx] minReg=1 last fixed> BB35 regmask=[rax] minReg=1 last> BB35 regmask=[rcx] minReg=1 last> BB35 regmask=[rdx] minReg=1 last> BB35 regmask=[r8] minReg=1 last> BB35 regmask=[r9] minReg=1 last> BB35 regmask=[r10] minReg=1 last> BB35 regmask=[r11] minReg=1 last> LCL_VAR_ADDR BB35 regmask=[allInt] minReg=1> BB35 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR_ADDR BB35 regmask=[allInt] minReg=1> BB35 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1> BB35 regmask=[allInt] minReg=1 last> LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1 last> BB35 regmask=[allInt] minReg=1 last> LCL_VAR_ADDR BB35 regmask=[allInt] minReg=1> BB35 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1> BB35 regmask=[allInt] minReg=1 last> LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1 last> BB35 regmask=[allInt] minReg=1 last> BB35 regmask=[rcx] minReg=1> LCL_VAR BB35 regmask=[rcx] minReg=1 last fixed> BB35 regmask=[rcx] minReg=1> PUTARG_REG BB35 regmask=[rcx] minReg=1 fixed> LCL_VAR_ADDR BB35 regmask=[rdx] minReg=1> BB35 regmask=[rdx] minReg=1> BB35 regmask=[rdx] minReg=1 last fixed> BB35 regmask=[rdx] minReg=1> PUTARG_REG BB35 regmask=[rdx] minReg=1 fixed> LCL_VAR_ADDR BB35 regmask=[r8] minReg=1> BB35 regmask=[r8] minReg=1> BB35 regmask=[r8] minReg=1 last fixed> BB35 regmask=[r8] minReg=1> PUTARG_REG BB35 regmask=[r8] minReg=1 fixed> LCL_VAR_ADDR BB35 regmask=[r9] minReg=1> BB35 regmask=[r9] minReg=1> BB35 regmask=[r9] minReg=1 last fixed> BB35 regmask=[r9] minReg=1> PUTARG_REG BB35 regmask=[r9] minReg=1 fixed> BB35 regmask=[rcx] minReg=1> BB35 regmask=[rcx] minReg=1 last fixed> BB35 regmask=[rdx] minReg=1> BB35 regmask=[rdx] minReg=1 last fixed> BB35 regmask=[r8] minReg=1> BB35 regmask=[r8] minReg=1 last fixed> BB35 regmask=[r9] minReg=1> BB35 regmask=[r9] minReg=1 last fixed> BB35 regmask=[rax] minReg=1 last> BB35 regmask=[rcx] minReg=1 last> BB35 regmask=[rdx] minReg=1 last> BB35 regmask=[r8] minReg=1 last> BB35 regmask=[r9] minReg=1 last> BB35 regmask=[r10] minReg=1 last> BB35 regmask=[r11] minReg=1 last> LCL_VAR_ADDR BB35 regmask=[allInt] minReg=1> BB35 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1> BB35 regmask=[allInt] minReg=1 last> LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1 last> BB35 regmask=[allInt] minReg=1 last> LCL_VAR_ADDR BB35 regmask=[rcx] minReg=1> BB35 regmask=[rcx] minReg=1> BB35 regmask=[rcx] minReg=1 last fixed> BB35 regmask=[rcx] minReg=1> PUTARG_REG BB35 regmask=[rcx] minReg=1 fixed> BB35 regmask=[rcx] minReg=1> BB35 regmask=[rcx] minReg=1 last fixed> BB35 regmask=[rax] minReg=1 last> BB35 regmask=[rcx] minReg=1 last> BB35 regmask=[rdx] minReg=1 last> BB35 regmask=[r8] minReg=1 last> BB35 regmask=[r9] minReg=1 last> BB35 regmask=[r10] minReg=1 last> BB35 regmask=[r11] minReg=1 last> BB35 regmask=[rax] minReg=1> CALL BB35 regmask=[rax] minReg=1 fixed> BB35 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> EQ BB35 regmask=[allInt] minReg=1> BB35 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> BB35 regmask=[rcx] minReg=1> LCL_VAR BB35 regmask=[rcx] minReg=1 fixed> BB35 regmask=[rcx] minReg=1> PUTARG_REG BB35 regmask=[rcx] minReg=1 fixed> BB35 regmask=[rcx] minReg=1> BB35 regmask=[rcx] minReg=1 last fixed> BB35 regmask=[rax] minReg=1 last> BB35 regmask=[rcx] minReg=1 last> BB35 regmask=[rdx] minReg=1 last> BB35 regmask=[r8] minReg=1 last> BB35 regmask=[r9] minReg=1 last> BB35 regmask=[r10] minReg=1 last> BB35 regmask=[r11] minReg=1 last> BB35 regmask=[rax] minReg=1> CALL BB35 regmask=[rax] minReg=1 fixed> BB35 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB36 regmask=[allInt] minReg=1 last> LCL_VAR BB36 regmask=[allInt] minReg=1 delay regOptional> SUB BB36 regmask=[allInt] minReg=1> BB36 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB36 regmask=[allInt] minReg=1> LCL_VAR BB36 regmask=[allInt] minReg=1 last regOptional> CNS_INT BB37 regmask=[rax rdx rbx rbp rsi rdi r8-r15] minReg=1> BB37 regmask=[rax rdx rbx rbp rsi rdi r8-r15] minReg=1 last> BB37 regmask=[rcx] minReg=1> LCL_VAR BB37 regmask=[rcx] minReg=1 fixed delay> BB37 regmask=[rcx] minReg=1 last> LSH BB37 regmask=[rax rdx rbx rbp rsi rdi r8-r15] minReg=1> BB37 regmask=[allInt] minReg=1 last> ADD BB37 regmask=[allInt] minReg=1> LCL_VAR BB37 regmask=[allInt] minReg=1 regOptional> BB37 regmask=[allInt] minReg=1 last> TEST_EQ BB37 regmask=[allInt] minReg=1> BB37 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB37 regmask=[allInt] minReg=1> CNS_INT BB38 regmask=[allInt] minReg=1> BB38 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB38 regmask=[allInt] minReg=1> LCL_VAR BB39 regmask=[allInt] minReg=1 last> CAST BB39 regmask=[allInt] minReg=1> BB39 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB39 regmask=[allInt] minReg=1> LCL_VAR BB39 regmask=[rax rdx rbx rbp rsi rdi r8-r15] minReg=1 last> BB39 regmask=[rcx] minReg=1> LCL_VAR BB39 regmask=[rcx] minReg=1 last fixed delay> BB39 regmask=[rcx] minReg=1 last> RSZ BB39 regmask=[rax rdx rbx rbp rsi rdi r8-r15] minReg=1> BB39 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB39 regmask=[allInt] minReg=1> LCL_VAR_ADDR BB40 regmask=[allInt] minReg=1> BB40 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB40 regmask=[allInt] minReg=1> LCL_VAR BB40 regmask=[allInt] minReg=1> LCL_VAR BB40 regmask=[allInt] minReg=1> BB40 regmask=[allInt] minReg=1 last> LCL_VAR BB40 regmask=[allInt] minReg=1> LCL_VAR BB40 regmask=[allInt] minReg=1 last> BB40 regmask=[allInt] minReg=1 last> LCL_VAR_ADDR BB40 regmask=[rcx] minReg=1> BB40 regmask=[rcx] minReg=1> BB40 regmask=[rcx] minReg=1 last fixed> BB40 regmask=[rcx] minReg=1> PUTARG_REG BB40 regmask=[rcx] minReg=1 fixed> BB40 regmask=[rcx] minReg=1> BB40 regmask=[rcx] minReg=1 last fixed> BB40 regmask=[rax] minReg=1 last> BB40 regmask=[rcx] minReg=1 last> BB40 regmask=[rdx] minReg=1 last> BB40 regmask=[r8] minReg=1 last> BB40 regmask=[r9] minReg=1 last> BB40 regmask=[r10] minReg=1 last> BB40 regmask=[r11] minReg=1 last> BB40 regmask=[rax] minReg=1> CALL BB40 regmask=[rax] minReg=1 fixed> BB40 regmask=[rax rdx rbx rbp rsi rdi r8-r15] minReg=1 last> BB40 regmask=[rcx] minReg=1> LCL_VAR BB40 regmask=[rcx] minReg=1 last fixed delay> BB40 regmask=[rcx] minReg=1 last> LSH BB40 regmask=[rax rdx rbx rbp rsi rdi r8-r15] minReg=1> BB40 regmask=[allInt] minReg=1 last> LCL_VAR BB40 regmask=[allInt] minReg=1 last regOptional> ADD BB40 regmask=[allInt] minReg=1> BB40 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB40 regmask=[allInt] minReg=1> LCL_VAR BB40 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB41 regmask=[allInt] minReg=1 last> NEG BB41 regmask=[allInt] minReg=1> BB41 regmask=[allInt] minReg=1 last> ADD BB41 regmask=[allInt] minReg=1> BB41 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB41 regmask=[allInt] minReg=1> LCL_VAR BB42 regmask=[allInt] minReg=1 last> ADD BB42 regmask=[allInt] minReg=1> BB42 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB42 regmask=[allInt] minReg=1> LCL_VAR BB43 regmask=[allInt] minReg=1 last> BB43 regmask=[rcx] minReg=1> LCL_VAR BB43 regmask=[rcx] minReg=1 last fixed> BB43 regmask=[rcx] minReg=1> PUTARG_REG BB43 regmask=[rcx] minReg=1 fixed> BB43 regmask=[rdx] minReg=1> LCL_VAR BB43 regmask=[rdx] minReg=1 last fixed> BB43 regmask=[rdx] minReg=1> PUTARG_REG BB43 regmask=[rdx] minReg=1 fixed> BB43 regmask=[r8] minReg=1> LCL_VAR BB43 regmask=[r8] minReg=1 last fixed> BB43 regmask=[r8] minReg=1> PUTARG_REG BB43 regmask=[r8] minReg=1 fixed> BB43 regmask=[r9] minReg=1> LCL_VAR BB43 regmask=[r9] minReg=1 last fixed> BB43 regmask=[r9] minReg=1> PUTARG_REG BB43 regmask=[r9] minReg=1 fixed> BB43 regmask=[rcx] minReg=1> BB43 regmask=[rcx] minReg=1 last fixed> BB43 regmask=[rdx] minReg=1> BB43 regmask=[rdx] minReg=1 last fixed> BB43 regmask=[r8] minReg=1> BB43 regmask=[r8] minReg=1 last fixed> BB43 regmask=[r9] minReg=1> BB43 regmask=[r9] minReg=1 last fixed> BB43 regmask=[rax] minReg=1 last> BB43 regmask=[rcx] minReg=1 last> BB43 regmask=[rdx] minReg=1 last> BB43 regmask=[r8] minReg=1 last> BB43 regmask=[r9] minReg=1 last> BB43 regmask=[r10] minReg=1 last> BB43 regmask=[r11] minReg=1 last> BB43 regmask=[rax] minReg=1> CALL BB43 regmask=[rax] minReg=1 fixed> BB43 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB43 regmask=[allInt] minReg=1> BB44 regmask=[rax] minReg=1> LCL_VAR BB44 regmask=[rax] minReg=1 last fixed> ----------------- BB00 regmask=[rdx] minReg=1 fixed regOptional> LCL_VAR BB03 regmask=[rcx] minReg=1 fixed> LCL_VAR BB03 regmask=[allInt] minReg=1 last> LCL_VAR BB04 regmask=[rcx] minReg=1 fixed> ConvertDecimalToFloatingPointBits: LocalVar V01: undefined use at 69 LCL_VAR BB04 regmask=[allInt] minReg=1> ConvertDecimalToFloatingPointBits: LocalVar V01: undefined use at 75 LCL_VAR BB11 regmask=[rcx] minReg=1 fixed> ConvertDecimalToFloatingPointBits: LocalVar V01: undefined use at 253 LCL_VAR BB12 regmask=[rcx] minReg=1 fixed> ConvertDecimalToFloatingPointBits: LocalVar V01: undefined use at 273 LCL_VAR BB12 regmask=[allInt] minReg=1 last> ConvertDecimalToFloatingPointBits: LocalVar V01: undefined use at 279 LCL_VAR BB16 regmask=[r9] minReg=1 last fixed> ConvertDecimalToFloatingPointBits: LocalVar V01: undefined use at 393 LCL_VAR BB21 regmask=[rcx] minReg=1 fixed> ConvertDecimalToFloatingPointBits: LocalVar V01: undefined use at 467 LCL_VAR BB22 regmask=[rcx] minReg=1 fixed> ConvertDecimalToFloatingPointBits: LocalVar V01: undefined use at 485 LCL_VAR BB22 regmask=[allInt] minReg=1 last> ConvertDecimalToFloatingPointBits: LocalVar V01: undefined use at 491 LCL_VAR BB30 regmask=[r9] minReg=1 last fixed> ConvertDecimalToFloatingPointBits: LocalVar V01: undefined use at 827 LCL_VAR BB43 regmask=[rcx] minReg=1 last fixed> ConvertDecimalToFloatingPointBits: LocalVar V01: undefined use at 1205 ----------------- BB00 regmask=[rcx] minReg=1 fixed regOptional> LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> ----------------- BB00 regmask=[r8] minReg=1 fixed regOptional> LCL_VAR BB03 regmask=[allInt] minReg=1 last> LCL_VAR BB12 regmask=[allInt] minReg=1 last> ConvertDecimalToFloatingPointBits: LocalVar V02: undefined use at 293 LCL_VAR BB16 regmask=[allInt] minReg=1 last> ConvertDecimalToFloatingPointBits: LocalVar V02: undefined use at 373 LCL_VAR BB22 regmask=[allInt] minReg=1 last> ConvertDecimalToFloatingPointBits: LocalVar V02: undefined use at 505 LCL_VAR BB30 regmask=[allInt] minReg=1 last> ConvertDecimalToFloatingPointBits: LocalVar V02: undefined use at 811 LCL_VAR BB43 regmask=[allInt] minReg=1 last> ConvertDecimalToFloatingPointBits: LocalVar V02: undefined use at 1201 ----------------- STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB16 regmask=[rdx] minReg=1 last fixed> LCL_VAR BB20 regmask=[allInt] minReg=1 regOptional> ConvertDecimalToFloatingPointBits: LocalVar V13: undefined use at 443 LCL_VAR BB28 regmask=[allInt] minReg=1 delay regOptional> ConvertDecimalToFloatingPointBits: LocalVar V13: undefined use at 773 LCL_VAR BB28 regmask=[allInt] minReg=1 regOptional> ConvertDecimalToFloatingPointBits: LocalVar V13: undefined use at 789 LCL_VAR BB30 regmask=[rdx] minReg=1 last fixed> ConvertDecimalToFloatingPointBits: LocalVar V13: undefined use at 823 LCL_VAR BB40 regmask=[allInt] minReg=1 regOptional> ConvertDecimalToFloatingPointBits: LocalVar V13: undefined use at 1165 LCL_VAR BB42 regmask=[allInt] minReg=1 last> ConvertDecimalToFloatingPointBits: LocalVar V13: undefined use at 1191 ----------------- STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB07 regmask=[allInt] minReg=1> LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR BB21 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB04 regmask=[allInt] minReg=1> LCL_VAR BB05 regmask=[allInt] minReg=1> LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR BB17 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB19 regmask=[allInt] minReg=1 delay regOptional> LCL_VAR BB23 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB07 regmask=[allInt] minReg=1> LCL_VAR BB07 regmask=[allInt] minReg=1> LCL_VAR BB09 regmask=[allInt] minReg=1> LCL_VAR BB10 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB16 regmask=[allInt] minReg=1> STORE_LCL_VAR BB30 regmask=[allInt] minReg=1> STORE_LCL_VAR BB43 regmask=[allInt] minReg=1> LCL_VAR BB44 regmask=[rax] minReg=1 last fixed> ----------------- STORE_LCL_VAR BB26 regmask=[allInt] minReg=1> LCL_VAR BB26 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB27 regmask=[rdx] minReg=1 fixed> LCL_VAR BB29 regmask=[allInt] minReg=1> LCL_VAR BB31 regmask=[allInt] minReg=1 delay regOptional> LCL_VAR BB33 regmask=[allInt] minReg=1 last> LCL_VAR BB34 regmask=[allInt] minReg=1 last> ConvertDecimalToFloatingPointBits: LocalVar V19: undefined use at 921 ----------------- STORE_LCL_VAR BB28 regmask=[allInt] minReg=1> LCL_VAR BB28 regmask=[allInt] minReg=1> LCL_VAR BB29 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB31 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB36 regmask=[allInt] minReg=1 delay regOptional> LCL_VAR BB40 regmask=[rcx] minReg=1 last fixed delay> ----------------- STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[rcx] minReg=1 fixed> LCL_VAR BB37 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB39 regmask=[rax rdx rbx rbp rsi rdi r8-r15] minReg=1 last> STORE_LCL_VAR BB39 regmask=[allInt] minReg=1> LCL_VAR BB40 regmask=[allInt] minReg=1 last regOptional> ----------------- STORE_LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR BB10 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR BB32 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB40 regmask=[allInt] minReg=1> LCL_VAR BB40 regmask=[allInt] minReg=1> LCL_VAR BB40 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB07 regmask=[allInt] minReg=1> LCL_VAR BB07 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB08 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR BB15 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB16 regmask=[allInt] minReg=1 last regOptional> LCL_VAR BB18 regmask=[allInt] minReg=1 last> ConvertDecimalToFloatingPointBits: LocalVar V10: undefined use at 417 LCL_VAR BB19 regmask=[allInt] minReg=1 last> ConvertDecimalToFloatingPointBits: LocalVar V10: undefined use at 427 ----------------- STORE_LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR BB10 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB11 regmask=[allInt] minReg=1> LCL_VAR BB13 regmask=[rdx] minReg=1 last fixed> ----------------- STORE_LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR BB10 regmask=[allInt] minReg=1 delay regOptional> LCL_VAR BB10 regmask=[r9] minReg=1 fixed> LCL_VAR BB23 regmask=[r8] minReg=1 last fixed> ----------------- STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB36 regmask=[allInt] minReg=1 last regOptional> STORE_LCL_VAR BB39 regmask=[allInt] minReg=1> LCL_VAR BB43 regmask=[r9] minReg=1 last fixed> ----------------- STORE_LCL_VAR BB08 regmask=[allInt] minReg=1> STORE_LCL_VAR BB09 regmask=[allInt] minReg=1> LCL_VAR BB10 regmask=[allInt] minReg=1 delay regOptional> LCL_VAR BB10 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR BB32 regmask=[rcx] minReg=1 last fixed> ----------------- STORE_LCL_VAR BB21 regmask=[allInt] minReg=1> LCL_VAR BB21 regmask=[allInt] minReg=1 last regOptional> ----------------- STORE_LCL_VAR BB04 regmask=[allInt] minReg=1> LCL_VAR BB04 regmask=[allInt] minReg=1 last regOptional> ----------------- STORE_LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR BB10 regmask=[rcx] minReg=1 last fixed> ----------------- STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[rcx] minReg=1 last fixed> ----------------- STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[rcx] minReg=1 last fixed> ----------------- STORE_LCL_VAR BB04 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB28 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[r9] minReg=1 last fixed> ----------------- STORE_LCL_VAR BB20 regmask=[allInt] minReg=1> LCL_VAR BB21 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[rdx] minReg=1 last fixed> ----------------- STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB25 regmask=[allInt] minReg=1 last delay regOptional> ----------------- STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB25 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB28 regmask=[allInt] minReg=1> STORE_LCL_VAR BB31 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[rdx] minReg=1 last fixed> ----------------- STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB36 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB36 regmask=[allInt] minReg=1> LCL_VAR BB37 regmask=[rcx] minReg=1 fixed delay> LCL_VAR BB39 regmask=[rcx] minReg=1 last fixed delay> ----------------- STORE_LCL_VAR BB18 regmask=[allInt] minReg=1> STORE_LCL_VAR BB19 regmask=[allInt] minReg=1> LCL_VAR BB20 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB24 regmask=[allInt] minReg=1> STORE_LCL_VAR BB25 regmask=[allInt] minReg=1> LCL_VAR BB26 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB33 regmask=[allInt] minReg=1> STORE_LCL_VAR BB34 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB41 regmask=[allInt] minReg=1> STORE_LCL_VAR BB42 regmask=[allInt] minReg=1> LCL_VAR BB43 regmask=[r8] minReg=1 last fixed> ----------------- STORE_LCL_VAR BB37 regmask=[allInt] minReg=1> STORE_LCL_VAR BB38 regmask=[allInt] minReg=1> LCL_VAR BB39 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB05 regmask=[allInt] minReg=1> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1> LCL_VAR BB07 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR BB32 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB41 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB40 regmask=[allInt] minReg=1> LCL_VAR BB43 regmask=[rdx] minReg=1 last fixed> ----------------- STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR BB32 regmask=[allInt] minReg=1 last> TUPLE STYLE DUMP WITH REF POSITIONS Incoming Parameters: V01 V00 V02 BB01 [???..???), preds={} succs={BB02} ===== N003. V00(L0) N005. IND Use:(#4) Def:(#5) Pref: N007. V52(L35) Use:(#6) * Def:(#7) N009. V00(L0) N011. LEA(b+8) N013. IND Use:(#8) * Def:(#9) Pref: N015. V53(L36) Use:(#10) * Def:(#11) BB02 [000..00D) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ===== N019. IL_OFFSET IL offset: 0x0 N021. V52(L35) N023. LEA(b+8) N025. IND N027. CNS_INT 0 N029. NE Use:(#13) N031. JTRUE BB03 [00D..017) (return), preds={BB02} succs={} ===== N035. IL_OFFSET IL offset: 0xd N037. V01(L1) N039. PUTARG_REG Use:(#16) Fixed:rcx(#15) Def:(#18) rcx Pref: N041. V01(L1) N043. LEA(b+0) N045. IND Use:(#19) * Def:(#20) N047. LEA(b+80) N049. IND Use:(#21) * Def:(#22) N051. LEA(b+0) N053. IND N055. CALLV ind Use:(#24) Fixed:rcx(#23) * Use:(#25) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#34) rax N057. V02(L2) N059. STOREIND Use:(#35) * Use:(#36) * N061. CNS_INT 1 Def:(#37) N063. RETURN Use:(#39) Fixed:rax(#38) * BB04 [017..065) -> BB06 (cond), preds={BB02} succs={BB05,BB06} ===== N067. V01(L1) N069. PUTARG_REG Use:(#42) Fixed:rcx(#41) Def:(#44) rcx Pref: N071. V01(L1) N073. LEA(b+0) N075. IND Use:(#45) Def:(#46) N077. LEA(b+72) N079. IND Use:(#47) * Def:(#48) N081. LEA(b+32) N083. IND N085. CALLV ind Use:(#50) Fixed:rcx(#49) * Use:(#51) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#60) rax Pref: N087. CNS_INT 1 N089. ADD Use:(#61) * Def:(#62) N091. CAST Use:(#63) * Def:(#64) Pref: N093. CNS_INT 1 N095. ADD Use:(#65) * Def:(#66) Pref: N097. V03(L3) Use:(#67) * Def:(#68) Pref: N099. IL_OFFSET IL offset: 0x20 N101. V53(L36) N103. V40(L29) Use:(#69) Def:(#70) N105. IL_OFFSET IL offset: 0x20 N107. V40(L29) N109. CNS_INT 0 N111. LE Use:(#71) * N113. JTRUE BB05 [020..021) -> BB07 (always), preds={BB04} succs={BB07} ===== N117. IL_OFFSET IL offset: 0x20 N119. V53(L36) N121. V39(L28) Use:(#73) Def:(#74) Pref: BB06 [020..021), preds={BB04} succs={BB07} ===== N125. IL_OFFSET IL offset: 0x20 N127. CNS_INT 0 Def:(#76) Pref: N129. V39(L28) Use:(#77) * Def:(#78) Pref: BB07 [000..000) -> BB09 (cond), preds={BB05,BB06} succs={BB08,BB09} ===== N133. V39(L28) N135. V31(L21) Use:(#80) * Def:(#81) Pref: N137. V52(L35) N139. LEA(b+8) N141. IND Use:(#82) Def:(#83) Pref: N143. V42(L31) Use:(#84) * Def:(#85) Pref: N145. V31(L21) N147. V42(L31) N149. LE Use:(#86) Use:(#87) N151. JTRUE BB08 [000..000) -> BB10 (always), preds={BB07} succs={BB10} ===== N155. V42(L31) N157. V41(L30) Use:(#89) * Def:(#90) Pref: BB09 [000..000), preds={BB07} succs={BB10} ===== N161. V31(L21) N163. V41(L30) Use:(#92) Def:(#93) Pref: BB10 [???..???) -> BB14 (cond), preds={BB08,BB09} succs={BB11,BB14} ===== N167. V31(L21) N169. V41(L30) N171. SUB Use:(#95) * Use:(#96) Def:(#97) Pref: N173. V05(L4) Use:(#98) * Def:(#99) N175. IL_OFFSET IL offset: 0x42 N177. V41(L30) N179. V08(L5) Use:(#100) * Def:(#101) N181. V52(L35) N183. LEA(b+8) N185. IND Use:(#102) Def:(#103) Pref: N187. V09(L6) Use:(#104) * Def:(#105) N189. IL_OFFSET IL offset: 0x4f N191. V09(L6) N193. V08(L5) N195. SUB Use:(#106) Use:(#107) Def:(#108) Pref: N197. V10(L7) Use:(#109) * Def:(#110) Pref: N199. LCL_VAR_ADDR V11 loc8 NA ref V11._bits (offs=0x00) -> V54 tmp24 int V11._sign (offs=0x08) -> V55 tmp25 Def:(#111) Pref: N201. V75(L44) Use:(#112) * Def:(#113) N203. LCL_VAR_ADDR V73 tmp43 NA Def:(#114) Pref: N205. V74(L43) Use:(#115) * Def:(#116) N207. V74(L43) N209. V52(L35) N211. STOREIND Use:(#117) Use:(#118) N213. V74(L43) N215. LEA(b+8) N217. V53(L36) N219. STOREIND Use:(#119) * Use:(#120) N221. V75(L44) N223. PUTARG_REG Use:(#122) Fixed:rcx(#121) * Def:(#124) rcx N225. LCL_VAR_ADDR V73 tmp43 NA Def:(#125) N227. PUTARG_REG Use:(#127) Fixed:rdx(#126) * Def:(#129) rdx N229. V08(L5) N231. PUTARG_REG Use:(#131) Fixed:r9(#130) Def:(#133) r9 Pref: N233. CNS_INT 0 Def:(#134) N235. PUTARG_REG Use:(#136) Fixed:r8(#135) * Def:(#138) r8 N237. CALL Use:(#140) Fixed:rcx(#139) * Use:(#142) Fixed:rdx(#141) * Use:(#144) Fixed:r9(#143) * Use:(#146) Fixed:r8(#145) * Kill: rax rcx rdx r8 r9 r10 r11 N239. IL_OFFSET IL offset: 0x61 N241. V05(L4) N243. CNS_INT 0 N245. EQ Use:(#154) N247. JTRUE BB11 [065..070) -> BB13 (cond), preds={BB10} succs={BB12,BB13} ===== N251. V01(L1) N253. PUTARG_REG Use:(#157) Fixed:rcx(#156) Def:(#159) rcx Pref: N255. CALL Use:(#161) Fixed:rcx(#160) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#170) rax N257. CAST Use:(#171) * Def:(#172) N259. V05(L4) N261. CAST Use:(#173) Def:(#174) N263. GE Use:(#175) * Use:(#176) * N265. JTRUE BB12 [070..07A) (return), preds={BB11} succs={} ===== N269. IL_OFFSET IL offset: 0x70 N271. V01(L1) N273. PUTARG_REG Use:(#179) Fixed:rcx(#178) Def:(#181) rcx Pref: N275. V01(L1) N277. LEA(b+0) N279. IND Use:(#182) * Def:(#183) N281. LEA(b+80) N283. IND Use:(#184) * Def:(#185) N285. LEA(b+8) N287. IND N289. CALLV ind Use:(#187) Fixed:rcx(#186) * Use:(#188) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#197) rax N291. V02(L2) N293. STOREIND Use:(#198) * Use:(#199) * N295. CNS_INT 3 Def:(#200) N297. RETURN Use:(#202) Fixed:rax(#201) * BB13 [07A..082), preds={BB11} succs={BB14} ===== N301. IL_OFFSET IL offset: 0x7a N303. LCL_VAR_ADDR V11 loc8 NA ref V11._bits (offs=0x00) -> V54 tmp24 int V11._sign (offs=0x08) -> V55 tmp25 Def:(#204) N305. PUTARG_REG Use:(#206) Fixed:rcx(#205) * Def:(#208) rcx N307. V05(L4) N309. PUTARG_REG Use:(#210) Fixed:rdx(#209) * Def:(#212) rdx N311. CALL Use:(#214) Fixed:rcx(#213) * Use:(#216) Fixed:rdx(#215) * Kill: rax rcx rdx r8 r9 r10 r11 BB14 [082..092) -> BB16 (cond), preds={BB10,BB13} succs={BB15,BB16} ===== N315. LCL_VAR_ADDR V76 tmp46 NA Def:(#225) Pref: N317. V77(L45) Use:(#226) * Def:(#227) N319. V77(L45) N321. V54 MEM Def:(#228) N323. STOREIND Use:(#229) Use:(#230) * N325. V77(L45) N327. LEA(b+8) N329. V55 MEM Def:(#231) N331. STOREIND Use:(#232) * Use:(#233) * N333. LCL_VAR_ADDR V76 tmp46 NA Def:(#234) N335. PUTARG_REG Use:(#236) Fixed:rcx(#235) * Def:(#238) rcx N337. LCL_VAR_ADDR V12 loc9 NA Def:(#239) N339. PUTARG_REG Use:(#241) Fixed:rdx(#240) * Def:(#243) rdx N341. CALL Use:(#245) Fixed:rcx(#244) * Use:(#247) Fixed:rdx(#246) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#256) rax Pref: N343. V13(L8) Use:(#257) * Def:(#258) Pref: N345. IL_OFFSET IL offset: 0x8d N347. V13(L8) N349. V03(L3) N351. GE Use:(#259) Use:(#260) N353. JTRUE BB15 [092..096) -> BB17 (cond), preds={BB14} succs={BB16,BB17} ===== N357. IL_OFFSET IL offset: 0x92 N359. V10(L7) N361. CNS_INT 0 N363. NE Use:(#262) N365. JTRUE BB16 [096..0A7) -> BB44 (always), preds={BB14,BB15} succs={BB44} ===== N369. IL_OFFSET IL offset: 0x96 N371. V02(L2) N373. PUTARG_STK [+0x20] Use:(#264) * N375. V10(L7) N377. CNS_INT 0 N379. NE Use:(#265) * Def:(#266) N381. PUTARG_REG Use:(#268) Fixed:r8(#267) * Def:(#270) r8 N383. V12 MEM Def:(#271) N385. PUTARG_REG Use:(#273) Fixed:rcx(#272) * Def:(#275) rcx N387. V13(L8) N389. PUTARG_REG Use:(#277) Fixed:rdx(#276) * Def:(#279) rdx N391. V01(L1) N393. PUTARG_REG Use:(#281) Fixed:r9(#280) * Def:(#283) r9 N395. CALL Use:(#285) Fixed:r8(#284) * Use:(#287) Fixed:rcx(#286) * Use:(#289) Fixed:rdx(#288) * Use:(#291) Fixed:r9(#290) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#300) rax Pref: N397. V51(L34) Use:(#301) * Def:(#302) BB17 [0A7..0B0) -> BB19 (cond), preds={BB15} succs={BB18,BB19} ===== N401. IL_OFFSET IL offset: 0xa7 N403. V53(L36) N405. CNS_INT 0 N407. LT Use:(#304) N409. JTRUE BB18 [0B0..0B4) -> BB20 (always), preds={BB17} succs={BB20} ===== N413. IL_OFFSET IL offset: 0xb0 N415. V10(L7) N417. V32(L22) Use:(#306) * Def:(#307) Pref: BB19 [0B4..0BE), preds={BB17} succs={BB20} ===== N421. IL_OFFSET IL offset: 0xb4 N423. V10(L7) N425. V53(L36) N427. SUB Use:(#309) * Use:(#310) Def:(#311) Pref: N429. V32(L22) Use:(#312) * Def:(#313) Pref: BB20 [0BE..0C4) -> BB23 (cond), preds={BB18,BB19} succs={BB21,BB23} ===== N433. V32(L22) N435. V14(L9) Use:(#315) * Def:(#316) N437. IL_OFFSET IL offset: 0xc0 N439. V13(L8) N441. CNS_INT 0 N443. NE Use:(#317) N445. JTRUE BB21 [0C4..0D9) -> BB23 (cond), preds={BB20} succs={BB22,BB23} ===== N449. V52(L35) N451. LEA(b+8) N453. IND Use:(#319) Def:(#320) N455. CAST Use:(#321) * Def:(#322) N457. V14(L9) N459. CAST Use:(#323) Def:(#324) Pref: N461. SUB Use:(#325) * Use:(#326) * Def:(#327) Pref: N463. V38(L27) Use:(#328) * Def:(#329) N465. V01(L1) N467. PUTARG_REG Use:(#331) Fixed:rcx(#330) Def:(#333) rcx Pref: N469. CALL Use:(#335) Fixed:rcx(#334) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#344) rax N471. CAST Use:(#345) * Def:(#346) N473. V38(L27) N475. GE Use:(#347) * Use:(#348) * N477. JTRUE BB22 [0D9..0E3) (return), preds={BB21} succs={} ===== N481. IL_OFFSET IL offset: 0xd9 N483. V01(L1) N485. PUTARG_REG Use:(#351) Fixed:rcx(#350) Def:(#353) rcx Pref: N487. V01(L1) N489. LEA(b+0) N491. IND Use:(#354) * Def:(#355) N493. LEA(b+80) N495. IND Use:(#356) * Def:(#357) N497. LEA(b+0) N499. IND N501. CALLV ind Use:(#359) Fixed:rcx(#358) * Use:(#360) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#369) rax N503. V02(L2) N505. STOREIND Use:(#370) * Use:(#371) * N507. CNS_INT 2 Def:(#372) N509. RETURN Use:(#374) Fixed:rax(#373) * BB23 [0E3..117) -> BB25 (cond), preds={BB20,BB21} succs={BB24,BB25} ===== N513. LCL_VAR_ADDR V15 loc12 NA ref V15._bits (offs=0x00) -> V56 tmp26 int V15._sign (offs=0x08) -> V57 tmp27 Def:(#376) Pref: N515. V79(L47) Use:(#377) * Def:(#378) N517. LCL_VAR_ADDR V73 tmp43 NA Def:(#379) Pref: N519. V78(L46) Use:(#380) * Def:(#381) N521. V78(L46) N523. V52(L35) N525. STOREIND Use:(#382) Use:(#383) * N527. V78(L46) N529. LEA(b+8) N531. V53(L36) N533. STOREIND Use:(#384) * Use:(#385) * N535. V79(L47) N537. PUTARG_REG Use:(#387) Fixed:rcx(#386) * Def:(#389) rcx N539. LCL_VAR_ADDR V73 tmp43 NA Def:(#390) N541. PUTARG_REG Use:(#392) Fixed:rdx(#391) * Def:(#394) rdx N543. V08(L5) N545. PUTARG_REG Use:(#396) Fixed:r8(#395) * Def:(#398) r8 N547. V09(L6) N549. PUTARG_REG Use:(#400) Fixed:r9(#399) * Def:(#402) r9 N551. CALL Use:(#404) Fixed:rcx(#403) * Use:(#406) Fixed:rdx(#405) * Use:(#408) Fixed:r8(#407) * Use:(#410) Fixed:r9(#409) * Kill: rax rcx rdx r8 r9 r10 r11 N553. IL_OFFSET IL offset: 0xef N555. CNS_INT 0x7ff815262aa0 Def:(#418) N557. PUTARG_REG Use:(#420) Fixed:rcx(#419) * Def:(#422) rcx N559. CNS_INT 173 Def:(#423) N561. PUTARG_REG Use:(#425) Fixed:rdx(#424) * Def:(#427) rdx N563. CALL help Use:(#429) Fixed:rcx(#428) * Use:(#431) Fixed:rdx(#430) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#440) rax LocalDefUse * N565. CNS_INT(h) 0xd1ffab1e static Fseq[BigOne] Def:(#441) N567. IND Use:(#442) * Def:(#443) Pref: N569. CNS_INT 8 Fseq[#FirstElem] N571. ADD Use:(#444) * Def:(#445) Pref: N573. V80(L48) Use:(#446) * Def:(#447) N575. V80(L48) N577. IND Use:(#448) Def:(#449) N579. V58 MEM Use:(#450) * N581. V80(L48) N583. LEA(b+8) N585. IND Use:(#451) * Def:(#452) N587. V59 MEM Use:(#453) * N589. IL_OFFSET IL offset: 0xf6 N591. LCL_VAR_ADDR V16 loc13 NA ref V16._bits (offs=0x00) -> V58 tmp28 int V16._sign (offs=0x08) -> V59 tmp29 Def:(#454) N593. PUTARG_REG Use:(#456) Fixed:rcx(#455) * Def:(#458) rcx N595. V14(L9) N597. PUTARG_REG Use:(#460) Fixed:rdx(#459) * Def:(#462) rdx N599. CALL Use:(#464) Fixed:rcx(#463) * Use:(#466) Fixed:rdx(#465) * Kill: rax rcx rdx r8 r9 r10 r11 N601. IL_OFFSET IL offset: 0xff N603. V56 MEM Def:(#474) Pref: N605. V64(L37) Use:(#475) * Def:(#476) N607. V57 MEM Def:(#477) Pref: N609. V65(L38) Use:(#478) * Def:(#479) N611. IL_OFFSET IL offset: 0xff N613. LCL_VAR_ADDR V76 tmp46 NA Def:(#480) Pref: N615. V81(L49) Use:(#481) * Def:(#482) N617. V81(L49) N619. V64(L37) N621. STOREIND Use:(#483) Use:(#484) * N623. V81(L49) N625. LEA(b+8) N627. V65(L38) N629. STOREIND Use:(#485) * Use:(#486) * N631. LCL_VAR_ADDR V76 tmp46 NA Def:(#487) N633. PUTARG_REG Use:(#489) Fixed:rcx(#488) * Def:(#491) rcx N635. LCL_VAR_ADDR V45 tmp15 NA Def:(#492) N637. PUTARG_REG Use:(#494) Fixed:rdx(#493) * Def:(#496) rdx N639. CALL Use:(#498) Fixed:rcx(#497) * Use:(#500) Fixed:rdx(#499) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#509) rax Pref: N641. V43(L32) Use:(#510) * Def:(#511) Pref: N643. IL_OFFSET IL offset: 0xff N645. CNS_INT null Def:(#512) N647. V45 MEM Use:(#513) * N649. V43(L32) N651. V17(L10) Use:(#514) * Def:(#515) N653. IL_OFFSET IL offset: 0x108 N655. V58 MEM Def:(#516) Pref: N657. V66(L39) Use:(#517) * Def:(#518) N659. V59 MEM Def:(#519) Pref: N661. V67(L40) Use:(#520) * Def:(#521) N663. IL_OFFSET IL offset: 0x108 N665. LCL_VAR_ADDR V76 tmp46 NA Def:(#522) Pref: N667. V82(L50) Use:(#523) * Def:(#524) N669. V82(L50) N671. V66(L39) N673. STOREIND Use:(#525) Use:(#526) * N675. V82(L50) N677. LEA(b+8) N679. V67(L40) N681. STOREIND Use:(#527) * Use:(#528) * N683. LCL_VAR_ADDR V76 tmp46 NA Def:(#529) N685. PUTARG_REG Use:(#531) Fixed:rcx(#530) * Def:(#533) rcx N687. LCL_VAR_ADDR V48 tmp18 NA Def:(#534) N689. PUTARG_REG Use:(#536) Fixed:rdx(#535) * Def:(#538) rdx N691. CALL Use:(#540) Fixed:rcx(#539) * Use:(#542) Fixed:rdx(#541) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#551) rax Pref: N693. V46(L33) Use:(#552) * Def:(#553) Pref: N695. IL_OFFSET IL offset: 0x108 N697. CNS_INT null Def:(#554) N699. V48 MEM Use:(#555) * N701. V46(L33) N703. V18(L11) Use:(#556) * Def:(#557) Pref: N705. IL_OFFSET IL offset: 0x111 N707. V18(L11) N709. V17(L10) N711. GT Use:(#558) Use:(#559) N713. JTRUE BB24 [117..11A) -> BB26 (always), preds={BB23} succs={BB26} ===== N717. IL_OFFSET IL offset: 0x117 N719. CNS_INT 0 Def:(#561) Pref: N721. V33(L23) Use:(#562) * Def:(#563) Pref: BB25 [11A..11F), preds={BB23} succs={BB26} ===== N725. IL_OFFSET IL offset: 0x11a N727. V18(L11) N729. V17(L10) N731. SUB Use:(#565) * Use:(#566) * Def:(#567) Pref: N733. V33(L23) Use:(#568) * Def:(#569) Pref: BB26 [11F..126) -> BB28 (cond), preds={BB24,BB25} succs={BB27,BB28} ===== N737. V33(L23) N739. V19(L12) Use:(#571) * Def:(#572) Pref: N741. IL_OFFSET IL offset: 0x121 N743. V19(L12) N745. CNS_INT 0 N747. EQ Use:(#573) N749. JTRUE BB27 [126..12F), preds={BB26} succs={BB28} ===== N753. IL_OFFSET IL offset: 0x126 N755. LCL_VAR_ADDR V15 loc12 NA ref V15._bits (offs=0x00) -> V56 tmp26 int V15._sign (offs=0x08) -> V57 tmp27 Def:(#575) N757. PUTARG_REG Use:(#577) Fixed:rcx(#576) * Def:(#579) rcx N759. V19(L12) N761. PUTARG_REG Use:(#581) Fixed:rdx(#580) Def:(#583) rdx Pref: N763. CALL Use:(#585) Fixed:rcx(#584) * Use:(#587) Fixed:rdx(#586) * Kill: rax rcx rdx r8 r9 r10 r11 BB28 [12F..13E) -> BB32 (cond), preds={BB26,BB27} succs={BB29,BB32} ===== N767. IL_OFFSET IL offset: 0x12f N769. V03(L3) N771. V13(L8) N773. SUB Use:(#596) * Use:(#597) Def:(#598) Pref: N775. V20(L13) Use:(#599) * Def:(#600) N777. IL_OFFSET IL offset: 0x135 N779. V20(L13) N781. V21(L14) Use:(#601) Def:(#602) N783. IL_OFFSET IL offset: 0x139 N785. V13(L8) N787. CNS_INT 0 N789. EQ Use:(#603) N791. JTRUE BB29 [13E..144) -> BB31 (cond), preds={BB28} succs={BB30,BB31} ===== N795. IL_OFFSET IL offset: 0x13e N797. V19(L12) N799. V20(L13) N801. LE Use:(#605) Use:(#606) N803. JTRUE BB30 [144..155) -> BB44 (always), preds={BB29} succs={BB44} ===== N807. IL_OFFSET IL offset: 0x144 N809. V02(L2) N811. PUTARG_STK [+0x20] Use:(#608) * N813. CNS_INT 1 Def:(#609) N815. PUTARG_REG Use:(#611) Fixed:r8(#610) * Def:(#613) r8 N817. V12 MEM Def:(#614) N819. PUTARG_REG Use:(#616) Fixed:rcx(#615) * Def:(#618) rcx N821. V13(L8) N823. PUTARG_REG Use:(#620) Fixed:rdx(#619) * Def:(#622) rdx N825. V01(L1) N827. PUTARG_REG Use:(#624) Fixed:r9(#623) * Def:(#626) r9 N829. CALL Use:(#628) Fixed:r8(#627) * Use:(#630) Fixed:rcx(#629) * Use:(#632) Fixed:rdx(#631) * Use:(#634) Fixed:r9(#633) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#643) rax Pref: N831. V51(L34) Use:(#644) * Def:(#645) BB31 [155..15C), preds={BB29} succs={BB32} ===== N835. IL_OFFSET IL offset: 0x155 N837. V20(L13) N839. V19(L12) N841. SUB Use:(#647) Use:(#648) Def:(#649) Pref: N843. V21(L14) Use:(#650) * Def:(#651) BB32 [15C..167) -> BB34 (cond), preds={BB28,BB31} succs={BB33,BB34} ===== N847. IL_OFFSET IL offset: 0x15c N849. V56 MEM Def:(#653) N851. V68 MEM Use:(#654) * N853. V57 MEM Def:(#655) N855. V69 MEM Use:(#656) * N857. IL_OFFSET IL offset: 0x15c N859. V58 MEM Def:(#657) Pref: N861. V70(L41) Use:(#658) * Def:(#659) N863. V59 MEM Def:(#660) Pref: N865. V71(L42) Use:(#661) * Def:(#662) N867. LCL_VAR_ADDR V49 tmp19 NA ref V49._bits (offs=0x00) -> V68 tmp38 int V49._sign (offs=0x08) -> V69 tmp39 Def:(#663) Pref: N869. V84(L52) Use:(#664) * Def:(#665) N871. LCL_VAR_ADDR V76 tmp46 NA Def:(#666) Pref: N873. V83(L51) Use:(#667) * Def:(#668) N875. V83(L51) N877. V70(L41) N879. STOREIND Use:(#669) Use:(#670) * N881. V83(L51) N883. LEA(b+8) N885. V71(L42) N887. STOREIND Use:(#671) * Use:(#672) * N889. V84(L52) N891. PUTARG_REG Use:(#674) Fixed:rcx(#673) * Def:(#676) rcx N893. LCL_VAR_ADDR V76 tmp46 NA Def:(#677) N895. PUTARG_REG Use:(#679) Fixed:rdx(#678) * Def:(#681) rdx N897. CALL Use:(#683) Fixed:rcx(#682) * Use:(#685) Fixed:rdx(#684) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#694) rax N899. CNS_INT 0 N901. LT Use:(#695) * N903. JTRUE BB33 [167..16B) -> BB35 (always), preds={BB32} succs={BB35} ===== N907. IL_OFFSET IL offset: 0x167 N909. V19(L12) N911. V34(L24) Use:(#697) * Def:(#698) Pref: BB34 [16B..16F), preds={BB32} succs={BB35} ===== N915. IL_OFFSET IL offset: 0x16b N917. V19(L12) N919. CNS_INT 1 N921. ADD Use:(#700) * Def:(#701) Pref: N923. V34(L24) Use:(#702) * Def:(#703) Pref: BB35 [16F..1A4) -> BB40 (cond), preds={BB33,BB34} succs={BB36,BB40} ===== N927. V34(L24) N929. V22(L15) Use:(#705) * Def:(#706) N931. IL_OFFSET IL offset: 0x171 N933. LCL_VAR_ADDR V15 loc12 NA ref V15._bits (offs=0x00) -> V56 tmp26 int V15._sign (offs=0x08) -> V57 tmp27 Def:(#707) N935. PUTARG_REG Use:(#709) Fixed:rcx(#708) * Def:(#711) rcx N937. V21(L14) N939. PUTARG_REG Use:(#713) Fixed:rdx(#712) * Def:(#715) rdx N941. CALL Use:(#717) Fixed:rcx(#716) * Use:(#719) Fixed:rdx(#718) * Kill: rax rcx rdx r8 r9 r10 r11 N943. IL_OFFSET IL offset: 0x17a N945. LCL_VAR_ADDR V35 tmp5 NA ref V35._bits (offs=0x00) -> V62 tmp32 int V35._sign (offs=0x08) -> V63 tmp33 Def:(#727) Pref: N947. V88(L55) Use:(#728) * Def:(#729) N949. LCL_VAR_ADDR V76 tmp46 NA Def:(#730) Pref: N951. V85(L53) Use:(#731) * Def:(#732) N953. V85(L53) N955. V56 MEM Def:(#733) N957. STOREIND Use:(#734) Use:(#735) * N959. V85(L53) N961. LEA(b+8) N963. V57 MEM Def:(#736) N965. STOREIND Use:(#737) * Use:(#738) * N967. LCL_VAR_ADDR V86 tmp56 NA Def:(#739) Pref: N969. V87(L54) Use:(#740) * Def:(#741) N971. V87(L54) N973. V58 MEM Def:(#742) N975. STOREIND Use:(#743) Use:(#744) * N977. V87(L54) N979. LEA(b+8) N981. V59 MEM Def:(#745) N983. STOREIND Use:(#746) * Use:(#747) * N985. V88(L55) N987. PUTARG_REG Use:(#749) Fixed:rcx(#748) * Def:(#751) rcx N989. LCL_VAR_ADDR V76 tmp46 NA Def:(#752) N991. PUTARG_REG Use:(#754) Fixed:rdx(#753) * Def:(#756) rdx N993. LCL_VAR_ADDR V86 tmp56 NA Def:(#757) N995. PUTARG_REG Use:(#759) Fixed:r8(#758) * Def:(#761) r8 N997. LCL_VAR_ADDR V23 loc20 NA ref V23._bits (offs=0x00) -> V60 tmp30 int V23._sign (offs=0x08) -> V61 tmp31 Def:(#762) N999. PUTARG_REG Use:(#764) Fixed:r9(#763) * Def:(#766) r9 N1001. CALL Use:(#768) Fixed:rcx(#767) * Use:(#770) Fixed:rdx(#769) * Use:(#772) Fixed:r8(#771) * Use:(#774) Fixed:r9(#773) * Kill: rax rcx rdx r8 r9 r10 r11 N1003. LCL_VAR_ADDR V76 tmp46 NA Def:(#782) Pref: N1005. V89(L56) Use:(#783) * Def:(#784) N1007. V89(L56) N1009. V62 MEM Def:(#785) N1011. STOREIND Use:(#786) Use:(#787) * N1013. V89(L56) N1015. LEA(b+8) N1017. V63 MEM Def:(#788) N1019. STOREIND Use:(#789) * Use:(#790) * N1021. LCL_VAR_ADDR V76 tmp46 NA Def:(#791) N1023. PUTARG_REG Use:(#793) Fixed:rcx(#792) * Def:(#795) rcx N1025. CALL Use:(#797) Fixed:rcx(#796) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#806) rax Pref: N1027. V24(L16) Use:(#807) * Def:(#808) Pref: N1029. V61 MEM N1031. CNS_INT 0 N1033. EQ Def:(#809) Pref: N1035. V25(L17) Use:(#810) * Def:(#811) N1037. V24(L16) N1039. PUTARG_REG Use:(#813) Fixed:rcx(#812) Def:(#815) rcx Pref: N1041. CALL Use:(#817) Fixed:rcx(#816) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#826) rax Pref: N1043. V26(L18) Use:(#827) * Def:(#828) Pref: N1045. IL_OFFSET IL offset: 0x19e N1047. V26(L18) N1049. V20(L13) N1051. LE Use:(#829) Use:(#830) N1053. JTRUE BB36 [1A4..1AF) -> BB38 (cond), preds={BB35} succs={BB37,BB38} ===== N1057. IL_OFFSET IL offset: 0x1a4 N1059. V26(L18) N1061. V20(L13) N1063. SUB Use:(#832) * Use:(#833) Def:(#834) Pref: N1065. V29(L20) Use:(#835) * Def:(#836) N1067. IL_OFFSET IL offset: 0x1ab N1069. V25(L17) N1071. CNS_INT 0 N1073. EQ Use:(#837) * N1075. JTRUE BB37 [1AF..1C3) -> BB39 (always), preds={BB36} succs={BB39} ===== N1079. IL_OFFSET IL offset: 0x1af N1081. V24(L16) N1083. V29(L20) N1085. CNS_INT 1 Def:(#839) Pref: N1087. LSH Use:(#840) * Use:(#842) Fixed:rcx(#841) Kill: rcx Def:(#844) Pref: N1089. CNS_INT -1 N1091. ADD Use:(#845) * Def:(#846) N1093. TEST_EQ Use:(#847) Use:(#848) * Def:(#849) Pref: N1095. V37(L26) Use:(#850) * Def:(#851) BB38 [1C3..1C4), preds={BB36} succs={BB39} ===== N1099. IL_OFFSET IL offset: 0x1c3 N1101. CNS_INT 0 Def:(#853) Pref: N1103. V37(L26) Use:(#854) * Def:(#855) BB39 [1C4..1D0), preds={BB37,BB38} succs={BB40} ===== N1107. V37(L26) N1109. CAST Use:(#857) * Def:(#858) Pref: N1111. V25(L17) Use:(#859) * Def:(#860) N1113. IL_OFFSET IL offset: 0x1c6 N1115. V24(L16) N1117. V29(L20) N1119. RSZ Use:(#861) * Use:(#863) Fixed:rcx(#862) * Kill: rcx Def:(#865) Pref: N1121. V24(L16) Use:(#866) * Def:(#867) Pref: BB40 [1D0..1E7) -> BB42 (cond), preds={BB35,BB39} succs={BB41,BB42} ===== N1125. LCL_VAR_ADDR V76 tmp46 NA Def:(#869) Pref: N1127. V90(L57) Use:(#870) * Def:(#871) N1129. V90(L57) N1131. V54 MEM Def:(#872) N1133. STOREIND Use:(#873) Use:(#874) * N1135. V90(L57) N1137. LEA(b+8) N1139. V55 MEM Def:(#875) N1141. STOREIND Use:(#876) * Use:(#877) * N1143. LCL_VAR_ADDR V76 tmp46 NA Def:(#878) N1145. PUTARG_REG Use:(#880) Fixed:rcx(#879) * Def:(#882) rcx N1147. CALL Use:(#884) Fixed:rcx(#883) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#893) rax Pref: N1149. V20(L13) N1151. LSH Use:(#894) * Use:(#896) Fixed:rcx(#895) * Kill: rcx Def:(#898) Pref: N1153. V24(L16) N1155. ADD Use:(#899) * Use:(#900) * Def:(#901) Pref: N1157. V27(L19) Use:(#902) * Def:(#903) N1159. IL_OFFSET IL offset: 0x1e2 N1161. V13(L8) N1163. CNS_INT 0 N1165. NE Use:(#904) N1167. JTRUE BB41 [1E7..1EE) -> BB43 (always), preds={BB40} succs={BB43} ===== N1171. IL_OFFSET IL offset: 0x1e7 N1173. V22(L15) N1175. NEG Use:(#906) * Def:(#907) Pref: N1177. CNS_INT -1 N1179. ADD Use:(#908) * Def:(#909) Pref: N1181. V36(L25) Use:(#910) * Def:(#911) BB42 [1EE..1F2), preds={BB40} succs={BB43} ===== N1185. IL_OFFSET IL offset: 0x1ee N1187. V13(L8) N1189. CNS_INT -2 N1191. ADD Use:(#913) * Def:(#914) Pref: N1193. V36(L25) Use:(#915) * Def:(#916) BB43 [1F2..202), preds={BB41,BB42} succs={BB44} ===== N1197. IL_OFFSET IL offset: 0x1f4 N1199. V02(L2) N1201. PUTARG_STK [+0x20] Use:(#918) * N1203. V01(L1) N1205. PUTARG_REG Use:(#920) Fixed:rcx(#919) * Def:(#922) rcx N1207. V27(L19) N1209. PUTARG_REG Use:(#924) Fixed:rdx(#923) * Def:(#926) rdx N1211. V36(L25) N1213. PUTARG_REG Use:(#928) Fixed:r8(#927) * Def:(#930) r8 N1215. V25(L17) N1217. PUTARG_REG Use:(#932) Fixed:r9(#931) * Def:(#934) r9 N1219. CALL Use:(#936) Fixed:rcx(#935) * Use:(#938) Fixed:rdx(#937) * Use:(#940) Fixed:r8(#939) * Use:(#942) Fixed:r9(#941) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#951) rax Pref: N1221. V51(L34) Use:(#952) * Def:(#953) BB44 [???..???) (return), preds={BB16,BB30,BB43} succs={} ===== N1225. V51(L34) N1227. RETURN Use:(#956) Fixed:rax(#955) * Linear scan intervals after buildIntervals: Interval 0: (V00) byref RefPositions {#1@0 #4@5 #8@13} physReg:rcx Preferences=[rcx] Interval 1: (V01) ref RefPositions {#0@0 #16@39 #19@45 #42@69 #45@75 #157@253 #179@273 #182@279 #281@393 #331@467 #351@485 #354@491 #624@827 #920@1205} physReg:rdx Preferences=[rbx rbp rsi rdi r12-r15] Interval 2: (V02) byref RefPositions {#2@0 #35@59 #198@293 #264@373 #370@505 #608@811 #918@1201} physReg:r8 Preferences=[rbx rbp rsi rdi r12-r15] Interval 3: (V03) int RefPositions {#68@98 #260@351 #596@773} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval Interval 4: (V05) int RefPositions {#99@174 #154@245 #173@261 #210@309} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 5: (V08) int RefPositions {#101@180 #107@195 #131@231 #396@545} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 6: (V09) int RefPositions {#105@188 #106@195 #400@549} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 7: (V10) int RefPositions {#110@198 #262@363 #265@379 #306@417 #309@427} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval Interval 8: (V13) int RefPositions {#258@344 #259@351 #277@389 #317@443 #597@773 #603@789 #620@823 #904@1165 #913@1191} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval Interval 9: (V14) int RefPositions {#316@436 #323@459 #460@597} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 10: (V17) int RefPositions {#515@652 #559@711 #566@731} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 11: (V18) int RefPositions {#557@704 #558@711 #565@731} physReg:NA Preferences=[allInt] RelatedInterval Interval 12: (V19) int RefPositions {#572@740 #573@747 #581@761 #605@801 #648@841 #697@911 #700@921} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval Interval 13: (V20) int RefPositions {#600@776 #601@781 #606@801 #647@841 #830@1051 #833@1063 #896@1151} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 14: (V21) int RefPositions {#602@782 #651@844 #713@939} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 15: (V22) int RefPositions {#706@930 #906@1175} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 16: (V24) long RefPositions {#808@1028 #813@1039 #847@1093 #861@1119 #867@1122 #900@1155} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval Interval 17: (V25) int RefPositions {#811@1036 #837@1073 #860@1112 #932@1217} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 18: (V26) int RefPositions {#828@1044 #829@1051 #832@1063} physReg:NA Preferences=[allInt] RelatedInterval Interval 19: (V27) long RefPositions {#903@1158 #924@1209} physReg:NA Preferences=[rdx] Interval 20: (V29) int RefPositions {#836@1066 #842@1087 #863@1119} physReg:NA Preferences=[rax rdx rbx rbp rsi rdi r8-r15] Interval 21: (V31) int RefPositions {#81@136 #86@149 #92@163 #95@171} physReg:NA Preferences=[allInt] RelatedInterval Interval 22: (V32) int RefPositions {#307@418 #313@430 #315@435} physReg:NA Preferences=[allInt] RelatedInterval Interval 23: (V33) int RefPositions {#563@722 #569@734 #571@739} physReg:NA Preferences=[allInt] RelatedInterval Interval 24: (V34) int RefPositions {#698@912 #703@924 #705@929} physReg:NA Preferences=[allInt] RelatedInterval Interval 25: (V36) int RefPositions {#911@1182 #916@1194 #928@1213} physReg:NA Preferences=[r8] Interval 26: (V37) int RefPositions {#851@1096 #855@1104 #857@1109} physReg:NA Preferences=[allInt] Interval 27: (V38) long RefPositions {#329@464 #348@475} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 28: (V39) int RefPositions {#74@122 #78@130 #80@135} physReg:NA Preferences=[allInt] RelatedInterval Interval 29: (V40) int RefPositions {#70@104 #71@111} physReg:NA Preferences=[allInt] Interval 30: (V41) int RefPositions {#90@158 #93@164 #96@171 #100@179} physReg:NA Preferences=[allInt] RelatedInterval Interval 31: (V42) int RefPositions {#85@144 #87@149 #89@157} physReg:NA Preferences=[allInt] RelatedInterval Interval 32: (V43) int RefPositions {#511@642 #514@651} physReg:NA Preferences=[allInt] RelatedInterval Interval 33: (V46) int RefPositions {#553@694 #556@703} physReg:NA Preferences=[allInt] RelatedInterval Interval 34: (V51) int RefPositions {#302@398 #645@832 #953@1222 #956@1227} physReg:NA Preferences=[rax] Interval 35: (V52) ref (field) RefPositions {#7@8 #13@29 #82@141 #102@185 #118@211 #319@453 #383@525} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 36: (V53) int (field) RefPositions {#11@16 #69@103 #73@121 #120@219 #304@407 #310@427 #385@533} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 37: (V64) ref (field) RefPositions {#476@606 #484@621} physReg:NA Preferences=[allInt] Interval 38: (V65) int (field) RefPositions {#479@610 #486@629} physReg:NA Preferences=[allInt] Interval 39: (V66) ref (field) RefPositions {#518@658 #526@673} physReg:NA Preferences=[allInt] Interval 40: (V67) int (field) RefPositions {#521@662 #528@681} physReg:NA Preferences=[allInt] Interval 41: (V70) ref (field) RefPositions {#659@862 #670@879} physReg:NA Preferences=[allInt] Interval 42: (V71) int (field) RefPositions {#662@866 #672@887} physReg:NA Preferences=[allInt] Interval 43: (V74) byref RefPositions {#116@206 #117@211 #119@219} physReg:NA Preferences=[allInt] Interval 44: (V75) long RefPositions {#113@202 #122@223} physReg:NA Preferences=[rcx] Interval 45: (V77) byref RefPositions {#227@318 #229@323 #232@331} physReg:NA Preferences=[allInt] Interval 46: (V78) byref RefPositions {#381@520 #382@525 #384@533} physReg:NA Preferences=[allInt] Interval 47: (V79) long RefPositions {#378@516 #387@537} physReg:NA Preferences=[rcx] Interval 48: (V80) byref RefPositions {#447@574 #448@577 #451@585} physReg:NA Preferences=[allInt] Interval 49: (V81) byref RefPositions {#482@616 #483@621 #485@629} physReg:NA Preferences=[allInt] Interval 50: (V82) byref RefPositions {#524@668 #525@673 #527@681} physReg:NA Preferences=[allInt] Interval 51: (V83) byref RefPositions {#668@874 #669@879 #671@887} physReg:NA Preferences=[allInt] Interval 52: (V84) byref RefPositions {#665@870 #674@891} physReg:NA Preferences=[rcx] Interval 53: (V85) byref RefPositions {#732@952 #734@957 #737@965} physReg:NA Preferences=[allInt] Interval 54: (V87) byref RefPositions {#741@970 #743@975 #746@983} physReg:NA Preferences=[allInt] Interval 55: (V88) long RefPositions {#729@948 #749@987} physReg:NA Preferences=[rcx] Interval 56: (V89) byref RefPositions {#784@1006 #786@1011 #789@1019} physReg:NA Preferences=[allInt] Interval 57: (V90) byref RefPositions {#871@1128 #873@1133 #876@1141} physReg:NA Preferences=[allInt] Interval 58: ref RefPositions {#5@6 #6@7} physReg:NA Preferences=[allInt] RelatedInterval Interval 59: int RefPositions {#9@14 #10@15} physReg:NA Preferences=[allInt] RelatedInterval Interval 60: ref (specialPutArg) RefPositions {#18@40 #24@55} physReg:NA Preferences=[rcx] RelatedInterval Interval 61: long RefPositions {#20@46 #21@49} physReg:NA Preferences=[allInt] Interval 62: long RefPositions {#22@50 #25@55} physReg:NA Preferences=[allInt] Interval 63: long RefPositions {#34@56 #36@59} physReg:NA Preferences=[rax] Interval 64: int (constant) RefPositions {#37@62 #39@63} physReg:NA Preferences=[rax] Interval 65: ref (specialPutArg) RefPositions {#44@70 #50@85} physReg:NA Preferences=[rcx] RelatedInterval Interval 66: long RefPositions {#46@76 #47@79} physReg:NA Preferences=[allInt] Interval 67: long RefPositions {#48@80 #51@85} physReg:NA Preferences=[allInt] Interval 68: int RefPositions {#60@86 #61@89} physReg:NA Preferences=[rax] RelatedInterval Interval 69: int RefPositions {#62@90 #63@91} physReg:NA Preferences=[allInt] Interval 70: int RefPositions {#64@92 #65@95} physReg:NA Preferences=[allInt] RelatedInterval Interval 71: int RefPositions {#66@96 #67@97} physReg:NA Preferences=[allInt] RelatedInterval Interval 72: int (constant) RefPositions {#76@128 #77@129} physReg:NA Preferences=[allInt] RelatedInterval Interval 73: int RefPositions {#83@142 #84@143} physReg:NA Preferences=[allInt] RelatedInterval Interval 74: int (interfering uses) RefPositions {#97@172 #98@173} physReg:NA Preferences=[allInt] RelatedInterval Interval 75: int RefPositions {#103@186 #104@187} physReg:NA Preferences=[allInt] RelatedInterval Interval 76: int (interfering uses) RefPositions {#108@196 #109@197} physReg:NA Preferences=[allInt] RelatedInterval Interval 77: byref RefPositions {#111@200 #112@201} physReg:NA Preferences=[allInt] RelatedInterval Interval 78: byref RefPositions {#114@204 #115@205} physReg:NA Preferences=[allInt] RelatedInterval Interval 79: long RefPositions {#124@224 #140@237} physReg:NA Preferences=[rcx] Interval 80: byref RefPositions {#125@226 #127@227} physReg:NA Preferences=[rdx] Interval 81: byref RefPositions {#129@228 #142@237} physReg:NA Preferences=[rdx] Interval 82: int (specialPutArg) RefPositions {#133@232 #144@237} physReg:NA Preferences=[r9] RelatedInterval Interval 83: int (constant) RefPositions {#134@234 #136@235} physReg:NA Preferences=[r8] Interval 84: int RefPositions {#138@236 #146@237} physReg:NA Preferences=[r8] Interval 85: ref (specialPutArg) RefPositions {#159@254 #161@255} physReg:NA Preferences=[rcx] RelatedInterval Interval 86: int RefPositions {#170@256 #171@257} physReg:NA Preferences=[rax] Interval 87: long RefPositions {#172@258 #175@263} physReg:NA Preferences=[allInt] Interval 88: long RefPositions {#174@262 #176@263} physReg:NA Preferences=[allInt] Interval 89: ref (specialPutArg) RefPositions {#181@274 #187@289} physReg:NA Preferences=[rcx] RelatedInterval Interval 90: long RefPositions {#183@280 #184@283} physReg:NA Preferences=[allInt] Interval 91: long RefPositions {#185@284 #188@289} physReg:NA Preferences=[allInt] Interval 92: long RefPositions {#197@290 #199@293} physReg:NA Preferences=[rax] Interval 93: int (constant) RefPositions {#200@296 #202@297} physReg:NA Preferences=[rax] Interval 94: byref RefPositions {#204@304 #206@305} physReg:NA Preferences=[rcx] Interval 95: byref RefPositions {#208@306 #214@311} physReg:NA Preferences=[rcx] Interval 96: int RefPositions {#212@310 #216@311} physReg:NA Preferences=[rdx] Interval 97: byref RefPositions {#225@316 #226@317} physReg:NA Preferences=[allInt] RelatedInterval Interval 98: ref RefPositions {#228@322 #230@323} physReg:NA Preferences=[allInt] Interval 99: int RefPositions {#231@330 #233@331} physReg:NA Preferences=[allInt] Interval 100: byref RefPositions {#234@334 #236@335} physReg:NA Preferences=[rcx] Interval 101: byref RefPositions {#238@336 #245@341} physReg:NA Preferences=[rcx] Interval 102: long RefPositions {#239@338 #241@339} physReg:NA Preferences=[rdx] Interval 103: long RefPositions {#243@340 #247@341} physReg:NA Preferences=[rdx] Interval 104: int RefPositions {#256@342 #257@343} physReg:NA Preferences=[rax] RelatedInterval Interval 105: int RefPositions {#266@380 #268@381} physReg:NA Preferences=[r8] Interval 106: int RefPositions {#270@382 #285@395} physReg:NA Preferences=[r8] Interval 107: ref RefPositions {#271@384 #273@385} physReg:NA Preferences=[rcx] Interval 108: ref RefPositions {#275@386 #287@395} physReg:NA Preferences=[rcx] Interval 109: int RefPositions {#279@390 #289@395} physReg:NA Preferences=[rdx] Interval 110: ref RefPositions {#283@394 #291@395} physReg:NA Preferences=[r9] Interval 111: int RefPositions {#300@396 #301@397} physReg:NA Preferences=[rax] RelatedInterval Interval 112: int (interfering uses) RefPositions {#311@428 #312@429} physReg:NA Preferences=[allInt] RelatedInterval Interval 113: int RefPositions {#320@454 #321@455} physReg:NA Preferences=[allInt] Interval 114: long RefPositions {#322@456 #326@461} physReg:NA Preferences=[allInt] Interval 115: long RefPositions {#324@460 #325@461} physReg:NA Preferences=[allInt] RelatedInterval Interval 116: long (interfering uses) RefPositions {#327@462 #328@463} physReg:NA Preferences=[allInt] RelatedInterval Interval 117: ref (specialPutArg) RefPositions {#333@468 #335@469} physReg:NA Preferences=[rcx] RelatedInterval Interval 118: int RefPositions {#344@470 #345@471} physReg:NA Preferences=[rax] Interval 119: long RefPositions {#346@472 #347@475} physReg:NA Preferences=[allInt] Interval 120: ref (specialPutArg) RefPositions {#353@486 #359@501} physReg:NA Preferences=[rcx] RelatedInterval Interval 121: long RefPositions {#355@492 #356@495} physReg:NA Preferences=[allInt] Interval 122: long RefPositions {#357@496 #360@501} physReg:NA Preferences=[allInt] Interval 123: long RefPositions {#369@502 #371@505} physReg:NA Preferences=[rax] Interval 124: int (constant) RefPositions {#372@508 #374@509} physReg:NA Preferences=[rax] Interval 125: byref RefPositions {#376@514 #377@515} physReg:NA Preferences=[allInt] RelatedInterval Interval 126: byref RefPositions {#379@518 #380@519} physReg:NA Preferences=[allInt] RelatedInterval Interval 127: long RefPositions {#389@538 #404@551} physReg:NA Preferences=[rcx] Interval 128: byref RefPositions {#390@540 #392@541} physReg:NA Preferences=[rdx] Interval 129: byref RefPositions {#394@542 #406@551} physReg:NA Preferences=[rdx] Interval 130: int RefPositions {#398@546 #408@551} physReg:NA Preferences=[r8] Interval 131: int RefPositions {#402@550 #410@551} physReg:NA Preferences=[r9] Interval 132: long (constant) RefPositions {#418@556 #420@557} physReg:NA Preferences=[rcx] Interval 133: long RefPositions {#422@558 #429@563} physReg:NA Preferences=[rcx] Interval 134: int (constant) RefPositions {#423@560 #425@561} physReg:NA Preferences=[rdx] Interval 135: int RefPositions {#427@562 #431@563} physReg:NA Preferences=[rdx] Interval 136: long RefPositions {#440@564} physReg:NA Preferences=[rax] Interval 137: long (constant) RefPositions {#441@566 #442@567} physReg:NA Preferences=[allInt] Interval 138: ref RefPositions {#443@568 #444@571} physReg:NA Preferences=[allInt] RelatedInterval Interval 139: byref RefPositions {#445@572 #446@573} physReg:NA Preferences=[allInt] RelatedInterval Interval 140: ref RefPositions {#449@578 #450@579} physReg:NA Preferences=[allInt] Interval 141: int RefPositions {#452@586 #453@587} physReg:NA Preferences=[allInt] Interval 142: byref RefPositions {#454@592 #456@593} physReg:NA Preferences=[rcx] Interval 143: byref RefPositions {#458@594 #464@599} physReg:NA Preferences=[rcx] Interval 144: int RefPositions {#462@598 #466@599} physReg:NA Preferences=[rdx] Interval 145: ref RefPositions {#474@604 #475@605} physReg:NA Preferences=[allInt] RelatedInterval Interval 146: int RefPositions {#477@608 #478@609} physReg:NA Preferences=[allInt] RelatedInterval Interval 147: byref RefPositions {#480@614 #481@615} physReg:NA Preferences=[allInt] RelatedInterval Interval 148: byref RefPositions {#487@632 #489@633} physReg:NA Preferences=[rcx] Interval 149: byref RefPositions {#491@634 #498@639} physReg:NA Preferences=[rcx] Interval 150: long RefPositions {#492@636 #494@637} physReg:NA Preferences=[rdx] Interval 151: long RefPositions {#496@638 #500@639} physReg:NA Preferences=[rdx] Interval 152: int RefPositions {#509@640 #510@641} physReg:NA Preferences=[rax] RelatedInterval Interval 153: ref (constant) RefPositions {#512@646 #513@647} physReg:NA Preferences=[allInt] Interval 154: ref RefPositions {#516@656 #517@657} physReg:NA Preferences=[allInt] RelatedInterval Interval 155: int RefPositions {#519@660 #520@661} physReg:NA Preferences=[allInt] RelatedInterval Interval 156: byref RefPositions {#522@666 #523@667} physReg:NA Preferences=[allInt] RelatedInterval Interval 157: byref RefPositions {#529@684 #531@685} physReg:NA Preferences=[rcx] Interval 158: byref RefPositions {#533@686 #540@691} physReg:NA Preferences=[rcx] Interval 159: long RefPositions {#534@688 #536@689} physReg:NA Preferences=[rdx] Interval 160: long RefPositions {#538@690 #542@691} physReg:NA Preferences=[rdx] Interval 161: int RefPositions {#551@692 #552@693} physReg:NA Preferences=[rax] RelatedInterval Interval 162: ref (constant) RefPositions {#554@698 #555@699} physReg:NA Preferences=[allInt] Interval 163: int (constant) RefPositions {#561@720 #562@721} physReg:NA Preferences=[allInt] RelatedInterval Interval 164: int (interfering uses) RefPositions {#567@732 #568@733} physReg:NA Preferences=[allInt] RelatedInterval Interval 165: byref RefPositions {#575@756 #577@757} physReg:NA Preferences=[rcx] Interval 166: byref RefPositions {#579@758 #585@763} physReg:NA Preferences=[rcx] Interval 167: int (specialPutArg) RefPositions {#583@762 #587@763} physReg:NA Preferences=[rdx] RelatedInterval Interval 168: int (interfering uses) RefPositions {#598@774 #599@775} physReg:NA Preferences=[allInt] RelatedInterval Interval 169: int (constant) RefPositions {#609@814 #611@815} physReg:NA Preferences=[r8] Interval 170: int RefPositions {#613@816 #628@829} physReg:NA Preferences=[r8] Interval 171: ref RefPositions {#614@818 #616@819} physReg:NA Preferences=[rcx] Interval 172: ref RefPositions {#618@820 #630@829} physReg:NA Preferences=[rcx] Interval 173: int RefPositions {#622@824 #632@829} physReg:NA Preferences=[rdx] Interval 174: ref RefPositions {#626@828 #634@829} physReg:NA Preferences=[r9] Interval 175: int RefPositions {#643@830 #644@831} physReg:NA Preferences=[rax] RelatedInterval Interval 176: int (interfering uses) RefPositions {#649@842 #650@843} physReg:NA Preferences=[allInt] RelatedInterval Interval 177: ref RefPositions {#653@850 #654@851} physReg:NA Preferences=[allInt] Interval 178: int RefPositions {#655@854 #656@855} physReg:NA Preferences=[allInt] Interval 179: ref RefPositions {#657@860 #658@861} physReg:NA Preferences=[allInt] RelatedInterval Interval 180: int RefPositions {#660@864 #661@865} physReg:NA Preferences=[allInt] RelatedInterval Interval 181: byref RefPositions {#663@868 #664@869} physReg:NA Preferences=[allInt] RelatedInterval Interval 182: byref RefPositions {#666@872 #667@873} physReg:NA Preferences=[allInt] RelatedInterval Interval 183: byref RefPositions {#676@892 #683@897} physReg:NA Preferences=[rcx] Interval 184: byref RefPositions {#677@894 #679@895} physReg:NA Preferences=[rdx] Interval 185: byref RefPositions {#681@896 #685@897} physReg:NA Preferences=[rdx] Interval 186: int RefPositions {#694@898 #695@901} physReg:NA Preferences=[rax] Interval 187: int RefPositions {#701@922 #702@923} physReg:NA Preferences=[allInt] RelatedInterval Interval 188: byref RefPositions {#707@934 #709@935} physReg:NA Preferences=[rcx] Interval 189: byref RefPositions {#711@936 #717@941} physReg:NA Preferences=[rcx] Interval 190: int RefPositions {#715@940 #719@941} physReg:NA Preferences=[rdx] Interval 191: byref RefPositions {#727@946 #728@947} physReg:NA Preferences=[allInt] RelatedInterval Interval 192: byref RefPositions {#730@950 #731@951} physReg:NA Preferences=[allInt] RelatedInterval Interval 193: ref RefPositions {#733@956 #735@957} physReg:NA Preferences=[allInt] Interval 194: int RefPositions {#736@964 #738@965} physReg:NA Preferences=[allInt] Interval 195: byref RefPositions {#739@968 #740@969} physReg:NA Preferences=[allInt] RelatedInterval Interval 196: ref RefPositions {#742@974 #744@975} physReg:NA Preferences=[allInt] Interval 197: int RefPositions {#745@982 #747@983} physReg:NA Preferences=[allInt] Interval 198: long RefPositions {#751@988 #768@1001} physReg:NA Preferences=[rcx] Interval 199: byref RefPositions {#752@990 #754@991} physReg:NA Preferences=[rdx] Interval 200: byref RefPositions {#756@992 #770@1001} physReg:NA Preferences=[rdx] Interval 201: byref RefPositions {#757@994 #759@995} physReg:NA Preferences=[r8] Interval 202: byref RefPositions {#761@996 #772@1001} physReg:NA Preferences=[r8] Interval 203: byref RefPositions {#762@998 #764@999} physReg:NA Preferences=[r9] Interval 204: byref RefPositions {#766@1000 #774@1001} physReg:NA Preferences=[r9] Interval 205: byref RefPositions {#782@1004 #783@1005} physReg:NA Preferences=[allInt] RelatedInterval Interval 206: ref RefPositions {#785@1010 #787@1011} physReg:NA Preferences=[allInt] Interval 207: int RefPositions {#788@1018 #790@1019} physReg:NA Preferences=[allInt] Interval 208: byref RefPositions {#791@1022 #793@1023} physReg:NA Preferences=[rcx] Interval 209: byref RefPositions {#795@1024 #797@1025} physReg:NA Preferences=[rcx] Interval 210: long RefPositions {#806@1026 #807@1027} physReg:NA Preferences=[rax] RelatedInterval Interval 211: int RefPositions {#809@1034 #810@1035} physReg:NA Preferences=[allInt] RelatedInterval Interval 212: long (specialPutArg) RefPositions {#815@1040 #817@1041} physReg:NA Preferences=[rcx] RelatedInterval Interval 213: int RefPositions {#826@1042 #827@1043} physReg:NA Preferences=[rax] RelatedInterval Interval 214: int (interfering uses) RefPositions {#834@1064 #835@1065} physReg:NA Preferences=[allInt] RelatedInterval Interval 215: long (constant) RefPositions {#839@1086 #840@1087} physReg:NA Preferences=[rax rdx rbx rbp rsi rdi r8-r15] RelatedInterval Interval 216: long (interfering uses) RefPositions {#844@1088 #845@1091} physReg:NA Preferences=[rax rdx rbx rbp rsi rdi r8-r15] RelatedInterval Interval 217: long RefPositions {#846@1092 #848@1093} physReg:NA Preferences=[allInt] Interval 218: int RefPositions {#849@1094 #850@1095} physReg:NA Preferences=[allInt] RelatedInterval Interval 219: int (constant) RefPositions {#853@1102 #854@1103} physReg:NA Preferences=[allInt] RelatedInterval Interval 220: int RefPositions {#858@1110 #859@1111} physReg:NA Preferences=[allInt] RelatedInterval Interval 221: long (interfering uses) RefPositions {#865@1120 #866@1121} physReg:NA Preferences=[rax rdx rbx rbp rsi rdi r8-r15] RelatedInterval Interval 222: byref RefPositions {#869@1126 #870@1127} physReg:NA Preferences=[allInt] RelatedInterval Interval 223: ref RefPositions {#872@1132 #874@1133} physReg:NA Preferences=[allInt] Interval 224: int RefPositions {#875@1140 #877@1141} physReg:NA Preferences=[allInt] Interval 225: byref RefPositions {#878@1144 #880@1145} physReg:NA Preferences=[rcx] Interval 226: byref RefPositions {#882@1146 #884@1147} physReg:NA Preferences=[rcx] Interval 227: long RefPositions {#893@1148 #894@1151} physReg:NA Preferences=[rax] RelatedInterval Interval 228: long (interfering uses) RefPositions {#898@1152 #899@1155} physReg:NA Preferences=[rax rdx rbx rbp rsi rdi r8-r15] RelatedInterval Interval 229: long RefPositions {#901@1156 #902@1157} physReg:NA Preferences=[allInt] RelatedInterval Interval 230: int RefPositions {#907@1176 #908@1179} physReg:NA Preferences=[allInt] RelatedInterval Interval 231: int RefPositions {#909@1180 #910@1181} physReg:NA Preferences=[allInt] RelatedInterval Interval 232: int RefPositions {#914@1192 #915@1193} physReg:NA Preferences=[allInt] RelatedInterval Interval 233: ref RefPositions {#922@1206 #936@1219} physReg:NA Preferences=[rcx] Interval 234: long RefPositions {#926@1210 #938@1219} physReg:NA Preferences=[rdx] Interval 235: int RefPositions {#930@1214 #940@1219} physReg:NA Preferences=[r8] Interval 236: int RefPositions {#934@1218 #942@1219} physReg:NA Preferences=[r9] Interval 237: int RefPositions {#951@1220 #952@1221} physReg:NA Preferences=[rax] RelatedInterval *************** In LinearScan::allocateRegisters() Linear scan intervals before allocateRegisters: Interval 0: (V00) byref RefPositions {#1@0 #4@5 #8@13} physReg:rcx Preferences=[rcx] Interval 1: (V01) ref RefPositions {#0@0 #16@39 #19@45 #42@69 #45@75 #157@253 #179@273 #182@279 #281@393 #331@467 #351@485 #354@491 #624@827 #920@1205} physReg:rdx Preferences=[rbx rbp rsi rdi r12-r15] Interval 2: (V02) byref RefPositions {#2@0 #35@59 #198@293 #264@373 #370@505 #608@811 #918@1201} physReg:r8 Preferences=[rbx rbp rsi rdi r12-r15] Interval 3: (V03) int RefPositions {#68@98 #260@351 #596@773} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval Interval 4: (V05) int RefPositions {#99@174 #154@245 #173@261 #210@309} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 5: (V08) int RefPositions {#101@180 #107@195 #131@231 #396@545} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 6: (V09) int RefPositions {#105@188 #106@195 #400@549} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 7: (V10) int RefPositions {#110@198 #262@363 #265@379 #306@417 #309@427} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval Interval 8: (V13) int RefPositions {#258@344 #259@351 #277@389 #317@443 #597@773 #603@789 #620@823 #904@1165 #913@1191} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval Interval 9: (V14) int RefPositions {#316@436 #323@459 #460@597} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 10: (V17) int RefPositions {#515@652 #559@711 #566@731} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 11: (V18) int RefPositions {#557@704 #558@711 #565@731} physReg:NA Preferences=[allInt] RelatedInterval Interval 12: (V19) int RefPositions {#572@740 #573@747 #581@761 #605@801 #648@841 #697@911 #700@921} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval Interval 13: (V20) int RefPositions {#600@776 #601@781 #606@801 #647@841 #830@1051 #833@1063 #896@1151} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 14: (V21) int RefPositions {#602@782 #651@844 #713@939} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 15: (V22) int RefPositions {#706@930 #906@1175} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 16: (V24) long RefPositions {#808@1028 #813@1039 #847@1093 #861@1119 #867@1122 #900@1155} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval Interval 17: (V25) int RefPositions {#811@1036 #837@1073 #860@1112 #932@1217} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 18: (V26) int RefPositions {#828@1044 #829@1051 #832@1063} physReg:NA Preferences=[allInt] RelatedInterval Interval 19: (V27) long RefPositions {#903@1158 #924@1209} physReg:NA Preferences=[rdx] Interval 20: (V29) int RefPositions {#836@1066 #842@1087 #863@1119} physReg:NA Preferences=[rax rdx rbx rbp rsi rdi r8-r15] Interval 21: (V31) int RefPositions {#81@136 #86@149 #92@163 #95@171} physReg:NA Preferences=[allInt] RelatedInterval Interval 22: (V32) int RefPositions {#307@418 #313@430 #315@435} physReg:NA Preferences=[allInt] RelatedInterval Interval 23: (V33) int RefPositions {#563@722 #569@734 #571@739} physReg:NA Preferences=[allInt] RelatedInterval Interval 24: (V34) int RefPositions {#698@912 #703@924 #705@929} physReg:NA Preferences=[allInt] RelatedInterval Interval 25: (V36) int RefPositions {#911@1182 #916@1194 #928@1213} physReg:NA Preferences=[r8] Interval 26: (V37) int RefPositions {#851@1096 #855@1104 #857@1109} physReg:NA Preferences=[allInt] Interval 27: (V38) long RefPositions {#329@464 #348@475} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 28: (V39) int RefPositions {#74@122 #78@130 #80@135} physReg:NA Preferences=[allInt] RelatedInterval Interval 29: (V40) int RefPositions {#70@104 #71@111} physReg:NA Preferences=[allInt] Interval 30: (V41) int RefPositions {#90@158 #93@164 #96@171 #100@179} physReg:NA Preferences=[allInt] RelatedInterval Interval 31: (V42) int RefPositions {#85@144 #87@149 #89@157} physReg:NA Preferences=[allInt] RelatedInterval Interval 32: (V43) int RefPositions {#511@642 #514@651} physReg:NA Preferences=[allInt] RelatedInterval Interval 33: (V46) int RefPositions {#553@694 #556@703} physReg:NA Preferences=[allInt] RelatedInterval Interval 34: (V51) int RefPositions {#302@398 #645@832 #953@1222 #956@1227} physReg:NA Preferences=[rax] Interval 35: (V52) ref (field) RefPositions {#7@8 #13@29 #82@141 #102@185 #118@211 #319@453 #383@525} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 36: (V53) int (field) RefPositions {#11@16 #69@103 #73@121 #120@219 #304@407 #310@427 #385@533} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 37: (V64) ref (field) RefPositions {#476@606 #484@621} physReg:NA Preferences=[allInt] Interval 38: (V65) int (field) RefPositions {#479@610 #486@629} physReg:NA Preferences=[allInt] Interval 39: (V66) ref (field) RefPositions {#518@658 #526@673} physReg:NA Preferences=[allInt] Interval 40: (V67) int (field) RefPositions {#521@662 #528@681} physReg:NA Preferences=[allInt] Interval 41: (V70) ref (field) RefPositions {#659@862 #670@879} physReg:NA Preferences=[allInt] Interval 42: (V71) int (field) RefPositions {#662@866 #672@887} physReg:NA Preferences=[allInt] Interval 43: (V74) byref RefPositions {#116@206 #117@211 #119@219} physReg:NA Preferences=[allInt] Interval 44: (V75) long RefPositions {#113@202 #122@223} physReg:NA Preferences=[rcx] Interval 45: (V77) byref RefPositions {#227@318 #229@323 #232@331} physReg:NA Preferences=[allInt] Interval 46: (V78) byref RefPositions {#381@520 #382@525 #384@533} physReg:NA Preferences=[allInt] Interval 47: (V79) long RefPositions {#378@516 #387@537} physReg:NA Preferences=[rcx] Interval 48: (V80) byref RefPositions {#447@574 #448@577 #451@585} physReg:NA Preferences=[allInt] Interval 49: (V81) byref RefPositions {#482@616 #483@621 #485@629} physReg:NA Preferences=[allInt] Interval 50: (V82) byref RefPositions {#524@668 #525@673 #527@681} physReg:NA Preferences=[allInt] Interval 51: (V83) byref RefPositions {#668@874 #669@879 #671@887} physReg:NA Preferences=[allInt] Interval 52: (V84) byref RefPositions {#665@870 #674@891} physReg:NA Preferences=[rcx] Interval 53: (V85) byref RefPositions {#732@952 #734@957 #737@965} physReg:NA Preferences=[allInt] Interval 54: (V87) byref RefPositions {#741@970 #743@975 #746@983} physReg:NA Preferences=[allInt] Interval 55: (V88) long RefPositions {#729@948 #749@987} physReg:NA Preferences=[rcx] Interval 56: (V89) byref RefPositions {#784@1006 #786@1011 #789@1019} physReg:NA Preferences=[allInt] Interval 57: (V90) byref RefPositions {#871@1128 #873@1133 #876@1141} physReg:NA Preferences=[allInt] Interval 58: ref RefPositions {#5@6 #6@7} physReg:NA Preferences=[allInt] RelatedInterval Interval 59: int RefPositions {#9@14 #10@15} physReg:NA Preferences=[allInt] RelatedInterval Interval 60: ref (specialPutArg) RefPositions {#18@40 #24@55} physReg:NA Preferences=[rcx] RelatedInterval Interval 61: long RefPositions {#20@46 #21@49} physReg:NA Preferences=[allInt] Interval 62: long RefPositions {#22@50 #25@55} physReg:NA Preferences=[allInt] Interval 63: long RefPositions {#34@56 #36@59} physReg:NA Preferences=[rax] Interval 64: int (constant) RefPositions {#37@62 #39@63} physReg:NA Preferences=[rax] Interval 65: ref (specialPutArg) RefPositions {#44@70 #50@85} physReg:NA Preferences=[rcx] RelatedInterval Interval 66: long RefPositions {#46@76 #47@79} physReg:NA Preferences=[allInt] Interval 67: long RefPositions {#48@80 #51@85} physReg:NA Preferences=[allInt] Interval 68: int RefPositions {#60@86 #61@89} physReg:NA Preferences=[rax] RelatedInterval Interval 69: int RefPositions {#62@90 #63@91} physReg:NA Preferences=[allInt] Interval 70: int RefPositions {#64@92 #65@95} physReg:NA Preferences=[allInt] RelatedInterval Interval 71: int RefPositions {#66@96 #67@97} physReg:NA Preferences=[allInt] RelatedInterval Interval 72: int (constant) RefPositions {#76@128 #77@129} physReg:NA Preferences=[allInt] RelatedInterval Interval 73: int RefPositions {#83@142 #84@143} physReg:NA Preferences=[allInt] RelatedInterval Interval 74: int (interfering uses) RefPositions {#97@172 #98@173} physReg:NA Preferences=[allInt] RelatedInterval Interval 75: int RefPositions {#103@186 #104@187} physReg:NA Preferences=[allInt] RelatedInterval Interval 76: int (interfering uses) RefPositions {#108@196 #109@197} physReg:NA Preferences=[allInt] RelatedInterval Interval 77: byref RefPositions {#111@200 #112@201} physReg:NA Preferences=[allInt] RelatedInterval Interval 78: byref RefPositions {#114@204 #115@205} physReg:NA Preferences=[allInt] RelatedInterval Interval 79: long RefPositions {#124@224 #140@237} physReg:NA Preferences=[rcx] Interval 80: byref RefPositions {#125@226 #127@227} physReg:NA Preferences=[rdx] Interval 81: byref RefPositions {#129@228 #142@237} physReg:NA Preferences=[rdx] Interval 82: int (specialPutArg) RefPositions {#133@232 #144@237} physReg:NA Preferences=[r9] RelatedInterval Interval 83: int (constant) RefPositions {#134@234 #136@235} physReg:NA Preferences=[r8] Interval 84: int RefPositions {#138@236 #146@237} physReg:NA Preferences=[r8] Interval 85: ref (specialPutArg) RefPositions {#159@254 #161@255} physReg:NA Preferences=[rcx] RelatedInterval Interval 86: int RefPositions {#170@256 #171@257} physReg:NA Preferences=[rax] Interval 87: long RefPositions {#172@258 #175@263} physReg:NA Preferences=[allInt] Interval 88: long RefPositions {#174@262 #176@263} physReg:NA Preferences=[allInt] Interval 89: ref (specialPutArg) RefPositions {#181@274 #187@289} physReg:NA Preferences=[rcx] RelatedInterval Interval 90: long RefPositions {#183@280 #184@283} physReg:NA Preferences=[allInt] Interval 91: long RefPositions {#185@284 #188@289} physReg:NA Preferences=[allInt] Interval 92: long RefPositions {#197@290 #199@293} physReg:NA Preferences=[rax] Interval 93: int (constant) RefPositions {#200@296 #202@297} physReg:NA Preferences=[rax] Interval 94: byref RefPositions {#204@304 #206@305} physReg:NA Preferences=[rcx] Interval 95: byref RefPositions {#208@306 #214@311} physReg:NA Preferences=[rcx] Interval 96: int RefPositions {#212@310 #216@311} physReg:NA Preferences=[rdx] Interval 97: byref RefPositions {#225@316 #226@317} physReg:NA Preferences=[allInt] RelatedInterval Interval 98: ref RefPositions {#228@322 #230@323} physReg:NA Preferences=[allInt] Interval 99: int RefPositions {#231@330 #233@331} physReg:NA Preferences=[allInt] Interval 100: byref RefPositions {#234@334 #236@335} physReg:NA Preferences=[rcx] Interval 101: byref RefPositions {#238@336 #245@341} physReg:NA Preferences=[rcx] Interval 102: long RefPositions {#239@338 #241@339} physReg:NA Preferences=[rdx] Interval 103: long RefPositions {#243@340 #247@341} physReg:NA Preferences=[rdx] Interval 104: int RefPositions {#256@342 #257@343} physReg:NA Preferences=[rax] RelatedInterval Interval 105: int RefPositions {#266@380 #268@381} physReg:NA Preferences=[r8] Interval 106: int RefPositions {#270@382 #285@395} physReg:NA Preferences=[r8] Interval 107: ref RefPositions {#271@384 #273@385} physReg:NA Preferences=[rcx] Interval 108: ref RefPositions {#275@386 #287@395} physReg:NA Preferences=[rcx] Interval 109: int RefPositions {#279@390 #289@395} physReg:NA Preferences=[rdx] Interval 110: ref RefPositions {#283@394 #291@395} physReg:NA Preferences=[r9] Interval 111: int RefPositions {#300@396 #301@397} physReg:NA Preferences=[rax] RelatedInterval Interval 112: int (interfering uses) RefPositions {#311@428 #312@429} physReg:NA Preferences=[allInt] RelatedInterval Interval 113: int RefPositions {#320@454 #321@455} physReg:NA Preferences=[allInt] Interval 114: long RefPositions {#322@456 #326@461} physReg:NA Preferences=[allInt] Interval 115: long RefPositions {#324@460 #325@461} physReg:NA Preferences=[allInt] RelatedInterval Interval 116: long (interfering uses) RefPositions {#327@462 #328@463} physReg:NA Preferences=[allInt] RelatedInterval Interval 117: ref (specialPutArg) RefPositions {#333@468 #335@469} physReg:NA Preferences=[rcx] RelatedInterval Interval 118: int RefPositions {#344@470 #345@471} physReg:NA Preferences=[rax] Interval 119: long RefPositions {#346@472 #347@475} physReg:NA Preferences=[allInt] Interval 120: ref (specialPutArg) RefPositions {#353@486 #359@501} physReg:NA Preferences=[rcx] RelatedInterval Interval 121: long RefPositions {#355@492 #356@495} physReg:NA Preferences=[allInt] Interval 122: long RefPositions {#357@496 #360@501} physReg:NA Preferences=[allInt] Interval 123: long RefPositions {#369@502 #371@505} physReg:NA Preferences=[rax] Interval 124: int (constant) RefPositions {#372@508 #374@509} physReg:NA Preferences=[rax] Interval 125: byref RefPositions {#376@514 #377@515} physReg:NA Preferences=[allInt] RelatedInterval Interval 126: byref RefPositions {#379@518 #380@519} physReg:NA Preferences=[allInt] RelatedInterval Interval 127: long RefPositions {#389@538 #404@551} physReg:NA Preferences=[rcx] Interval 128: byref RefPositions {#390@540 #392@541} physReg:NA Preferences=[rdx] Interval 129: byref RefPositions {#394@542 #406@551} physReg:NA Preferences=[rdx] Interval 130: int RefPositions {#398@546 #408@551} physReg:NA Preferences=[r8] Interval 131: int RefPositions {#402@550 #410@551} physReg:NA Preferences=[r9] Interval 132: long (constant) RefPositions {#418@556 #420@557} physReg:NA Preferences=[rcx] Interval 133: long RefPositions {#422@558 #429@563} physReg:NA Preferences=[rcx] Interval 134: int (constant) RefPositions {#423@560 #425@561} physReg:NA Preferences=[rdx] Interval 135: int RefPositions {#427@562 #431@563} physReg:NA Preferences=[rdx] Interval 136: long RefPositions {#440@564} physReg:NA Preferences=[rax] Interval 137: long (constant) RefPositions {#441@566 #442@567} physReg:NA Preferences=[allInt] Interval 138: ref RefPositions {#443@568 #444@571} physReg:NA Preferences=[allInt] RelatedInterval Interval 139: byref RefPositions {#445@572 #446@573} physReg:NA Preferences=[allInt] RelatedInterval Interval 140: ref RefPositions {#449@578 #450@579} physReg:NA Preferences=[allInt] Interval 141: int RefPositions {#452@586 #453@587} physReg:NA Preferences=[allInt] Interval 142: byref RefPositions {#454@592 #456@593} physReg:NA Preferences=[rcx] Interval 143: byref RefPositions {#458@594 #464@599} physReg:NA Preferences=[rcx] Interval 144: int RefPositions {#462@598 #466@599} physReg:NA Preferences=[rdx] Interval 145: ref RefPositions {#474@604 #475@605} physReg:NA Preferences=[allInt] RelatedInterval Interval 146: int RefPositions {#477@608 #478@609} physReg:NA Preferences=[allInt] RelatedInterval Interval 147: byref RefPositions {#480@614 #481@615} physReg:NA Preferences=[allInt] RelatedInterval Interval 148: byref RefPositions {#487@632 #489@633} physReg:NA Preferences=[rcx] Interval 149: byref RefPositions {#491@634 #498@639} physReg:NA Preferences=[rcx] Interval 150: long RefPositions {#492@636 #494@637} physReg:NA Preferences=[rdx] Interval 151: long RefPositions {#496@638 #500@639} physReg:NA Preferences=[rdx] Interval 152: int RefPositions {#509@640 #510@641} physReg:NA Preferences=[rax] RelatedInterval Interval 153: ref (constant) RefPositions {#512@646 #513@647} physReg:NA Preferences=[allInt] Interval 154: ref RefPositions {#516@656 #517@657} physReg:NA Preferences=[allInt] RelatedInterval Interval 155: int RefPositions {#519@660 #520@661} physReg:NA Preferences=[allInt] RelatedInterval Interval 156: byref RefPositions {#522@666 #523@667} physReg:NA Preferences=[allInt] RelatedInterval Interval 157: byref RefPositions {#529@684 #531@685} physReg:NA Preferences=[rcx] Interval 158: byref RefPositions {#533@686 #540@691} physReg:NA Preferences=[rcx] Interval 159: long RefPositions {#534@688 #536@689} physReg:NA Preferences=[rdx] Interval 160: long RefPositions {#538@690 #542@691} physReg:NA Preferences=[rdx] Interval 161: int RefPositions {#551@692 #552@693} physReg:NA Preferences=[rax] RelatedInterval Interval 162: ref (constant) RefPositions {#554@698 #555@699} physReg:NA Preferences=[allInt] Interval 163: int (constant) RefPositions {#561@720 #562@721} physReg:NA Preferences=[allInt] RelatedInterval Interval 164: int (interfering uses) RefPositions {#567@732 #568@733} physReg:NA Preferences=[allInt] RelatedInterval Interval 165: byref RefPositions {#575@756 #577@757} physReg:NA Preferences=[rcx] Interval 166: byref RefPositions {#579@758 #585@763} physReg:NA Preferences=[rcx] Interval 167: int (specialPutArg) RefPositions {#583@762 #587@763} physReg:NA Preferences=[rdx] RelatedInterval Interval 168: int (interfering uses) RefPositions {#598@774 #599@775} physReg:NA Preferences=[allInt] RelatedInterval Interval 169: int (constant) RefPositions {#609@814 #611@815} physReg:NA Preferences=[r8] Interval 170: int RefPositions {#613@816 #628@829} physReg:NA Preferences=[r8] Interval 171: ref RefPositions {#614@818 #616@819} physReg:NA Preferences=[rcx] Interval 172: ref RefPositions {#618@820 #630@829} physReg:NA Preferences=[rcx] Interval 173: int RefPositions {#622@824 #632@829} physReg:NA Preferences=[rdx] Interval 174: ref RefPositions {#626@828 #634@829} physReg:NA Preferences=[r9] Interval 175: int RefPositions {#643@830 #644@831} physReg:NA Preferences=[rax] RelatedInterval Interval 176: int (interfering uses) RefPositions {#649@842 #650@843} physReg:NA Preferences=[allInt] RelatedInterval Interval 177: ref RefPositions {#653@850 #654@851} physReg:NA Preferences=[allInt] Interval 178: int RefPositions {#655@854 #656@855} physReg:NA Preferences=[allInt] Interval 179: ref RefPositions {#657@860 #658@861} physReg:NA Preferences=[allInt] RelatedInterval Interval 180: int RefPositions {#660@864 #661@865} physReg:NA Preferences=[allInt] RelatedInterval Interval 181: byref RefPositions {#663@868 #664@869} physReg:NA Preferences=[allInt] RelatedInterval Interval 182: byref RefPositions {#666@872 #667@873} physReg:NA Preferences=[allInt] RelatedInterval Interval 183: byref RefPositions {#676@892 #683@897} physReg:NA Preferences=[rcx] Interval 184: byref RefPositions {#677@894 #679@895} physReg:NA Preferences=[rdx] Interval 185: byref RefPositions {#681@896 #685@897} physReg:NA Preferences=[rdx] Interval 186: int RefPositions {#694@898 #695@901} physReg:NA Preferences=[rax] Interval 187: int RefPositions {#701@922 #702@923} physReg:NA Preferences=[allInt] RelatedInterval Interval 188: byref RefPositions {#707@934 #709@935} physReg:NA Preferences=[rcx] Interval 189: byref RefPositions {#711@936 #717@941} physReg:NA Preferences=[rcx] Interval 190: int RefPositions {#715@940 #719@941} physReg:NA Preferences=[rdx] Interval 191: byref RefPositions {#727@946 #728@947} physReg:NA Preferences=[allInt] RelatedInterval Interval 192: byref RefPositions {#730@950 #731@951} physReg:NA Preferences=[allInt] RelatedInterval Interval 193: ref RefPositions {#733@956 #735@957} physReg:NA Preferences=[allInt] Interval 194: int RefPositions {#736@964 #738@965} physReg:NA Preferences=[allInt] Interval 195: byref RefPositions {#739@968 #740@969} physReg:NA Preferences=[allInt] RelatedInterval Interval 196: ref RefPositions {#742@974 #744@975} physReg:NA Preferences=[allInt] Interval 197: int RefPositions {#745@982 #747@983} physReg:NA Preferences=[allInt] Interval 198: long RefPositions {#751@988 #768@1001} physReg:NA Preferences=[rcx] Interval 199: byref RefPositions {#752@990 #754@991} physReg:NA Preferences=[rdx] Interval 200: byref RefPositions {#756@992 #770@1001} physReg:NA Preferences=[rdx] Interval 201: byref RefPositions {#757@994 #759@995} physReg:NA Preferences=[r8] Interval 202: byref RefPositions {#761@996 #772@1001} physReg:NA Preferences=[r8] Interval 203: byref RefPositions {#762@998 #764@999} physReg:NA Preferences=[r9] Interval 204: byref RefPositions {#766@1000 #774@1001} physReg:NA Preferences=[r9] Interval 205: byref RefPositions {#782@1004 #783@1005} physReg:NA Preferences=[allInt] RelatedInterval Interval 206: ref RefPositions {#785@1010 #787@1011} physReg:NA Preferences=[allInt] Interval 207: int RefPositions {#788@1018 #790@1019} physReg:NA Preferences=[allInt] Interval 208: byref RefPositions {#791@1022 #793@1023} physReg:NA Preferences=[rcx] Interval 209: byref RefPositions {#795@1024 #797@1025} physReg:NA Preferences=[rcx] Interval 210: long RefPositions {#806@1026 #807@1027} physReg:NA Preferences=[rax] RelatedInterval Interval 211: int RefPositions {#809@1034 #810@1035} physReg:NA Preferences=[allInt] RelatedInterval Interval 212: long (specialPutArg) RefPositions {#815@1040 #817@1041} physReg:NA Preferences=[rcx] RelatedInterval Interval 213: int RefPositions {#826@1042 #827@1043} physReg:NA Preferences=[rax] RelatedInterval Interval 214: int (interfering uses) RefPositions {#834@1064 #835@1065} physReg:NA Preferences=[allInt] RelatedInterval Interval 215: long (constant) RefPositions {#839@1086 #840@1087} physReg:NA Preferences=[rax rdx rbx rbp rsi rdi r8-r15] RelatedInterval Interval 216: long (interfering uses) RefPositions {#844@1088 #845@1091} physReg:NA Preferences=[rax rdx rbx rbp rsi rdi r8-r15] RelatedInterval Interval 217: long RefPositions {#846@1092 #848@1093} physReg:NA Preferences=[allInt] Interval 218: int RefPositions {#849@1094 #850@1095} physReg:NA Preferences=[allInt] RelatedInterval Interval 219: int (constant) RefPositions {#853@1102 #854@1103} physReg:NA Preferences=[allInt] RelatedInterval Interval 220: int RefPositions {#858@1110 #859@1111} physReg:NA Preferences=[allInt] RelatedInterval Interval 221: long (interfering uses) RefPositions {#865@1120 #866@1121} physReg:NA Preferences=[rax rdx rbx rbp rsi rdi r8-r15] RelatedInterval Interval 222: byref RefPositions {#869@1126 #870@1127} physReg:NA Preferences=[allInt] RelatedInterval Interval 223: ref RefPositions {#872@1132 #874@1133} physReg:NA Preferences=[allInt] Interval 224: int RefPositions {#875@1140 #877@1141} physReg:NA Preferences=[allInt] Interval 225: byref RefPositions {#878@1144 #880@1145} physReg:NA Preferences=[rcx] Interval 226: byref RefPositions {#882@1146 #884@1147} physReg:NA Preferences=[rcx] Interval 227: long RefPositions {#893@1148 #894@1151} physReg:NA Preferences=[rax] RelatedInterval Interval 228: long (interfering uses) RefPositions {#898@1152 #899@1155} physReg:NA Preferences=[rax rdx rbx rbp rsi rdi r8-r15] RelatedInterval Interval 229: long RefPositions {#901@1156 #902@1157} physReg:NA Preferences=[allInt] RelatedInterval Interval 230: int RefPositions {#907@1176 #908@1179} physReg:NA Preferences=[allInt] RelatedInterval Interval 231: int RefPositions {#909@1180 #910@1181} physReg:NA Preferences=[allInt] RelatedInterval Interval 232: int RefPositions {#914@1192 #915@1193} physReg:NA Preferences=[allInt] RelatedInterval Interval 233: ref RefPositions {#922@1206 #936@1219} physReg:NA Preferences=[rcx] Interval 234: long RefPositions {#926@1210 #938@1219} physReg:NA Preferences=[rdx] Interval 235: int RefPositions {#930@1214 #940@1219} physReg:NA Preferences=[r8] Interval 236: int RefPositions {#934@1218 #942@1219} physReg:NA Preferences=[r9] Interval 237: int RefPositions {#951@1220 #952@1221} physReg:NA Preferences=[rax] RelatedInterval ------------ REFPOSITIONS BEFORE ALLOCATION: ------------ BB00 regmask=[rdx] minReg=1 fixed regOptional> BB00 regmask=[rcx] minReg=1 fixed regOptional> BB00 regmask=[r8] minReg=1 fixed regOptional> LCL_VAR BB01 regmask=[allInt] minReg=1> IND BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> IND BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1> BB03 regmask=[rcx] minReg=1> LCL_VAR BB03 regmask=[rcx] minReg=1 fixed> BB03 regmask=[rcx] minReg=1> PUTARG_REG BB03 regmask=[rcx] minReg=1 fixed> LCL_VAR BB03 regmask=[allInt] minReg=1 last> IND BB03 regmask=[allInt] minReg=1> BB03 regmask=[allInt] minReg=1 last> IND BB03 regmask=[allInt] minReg=1> BB03 regmask=[rcx] minReg=1> BB03 regmask=[rcx] minReg=1 last fixed> BB03 regmask=[allInt] minReg=1 last> BB03 regmask=[rax] minReg=1 last> BB03 regmask=[rcx] minReg=1 last> BB03 regmask=[rdx] minReg=1 last> BB03 regmask=[r8] minReg=1 last> BB03 regmask=[r9] minReg=1 last> BB03 regmask=[r10] minReg=1 last> BB03 regmask=[r11] minReg=1 last> BB03 regmask=[rax] minReg=1> CALL BB03 regmask=[rax] minReg=1 fixed> LCL_VAR BB03 regmask=[allInt] minReg=1 last> BB03 regmask=[allInt] minReg=1 last> CNS_INT BB03 regmask=[rax] minReg=1> BB03 regmask=[rax] minReg=1> BB03 regmask=[rax] minReg=1 last fixed> BB04 regmask=[rcx] minReg=1> LCL_VAR BB04 regmask=[rcx] minReg=1 fixed> BB04 regmask=[rcx] minReg=1> PUTARG_REG BB04 regmask=[rcx] minReg=1 fixed> LCL_VAR BB04 regmask=[allInt] minReg=1> IND BB04 regmask=[allInt] minReg=1> BB04 regmask=[allInt] minReg=1 last> IND BB04 regmask=[allInt] minReg=1> BB04 regmask=[rcx] minReg=1> BB04 regmask=[rcx] minReg=1 last fixed> BB04 regmask=[allInt] minReg=1 last> BB04 regmask=[rax] minReg=1 last> BB04 regmask=[rcx] minReg=1 last> BB04 regmask=[rdx] minReg=1 last> BB04 regmask=[r8] minReg=1 last> BB04 regmask=[r9] minReg=1 last> BB04 regmask=[r10] minReg=1 last> BB04 regmask=[r11] minReg=1 last> BB04 regmask=[rax] minReg=1> CALL BB04 regmask=[rax] minReg=1 fixed> BB04 regmask=[allInt] minReg=1 last> ADD BB04 regmask=[allInt] minReg=1> BB04 regmask=[allInt] minReg=1 last> CAST BB04 regmask=[allInt] minReg=1> BB04 regmask=[allInt] minReg=1 last> ADD BB04 regmask=[allInt] minReg=1> BB04 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1> LCL_VAR BB04 regmask=[allInt] minReg=1> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1> LCL_VAR BB04 regmask=[allInt] minReg=1 last regOptional> LCL_VAR BB05 regmask=[allInt] minReg=1> STORE_LCL_VAR BB05 regmask=[allInt] minReg=1> CNS_INT BB06 regmask=[allInt] minReg=1> BB06 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1> LCL_VAR BB07 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB07 regmask=[allInt] minReg=1> LCL_VAR BB07 regmask=[allInt] minReg=1> IND BB07 regmask=[allInt] minReg=1> BB07 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB07 regmask=[allInt] minReg=1> LCL_VAR BB07 regmask=[allInt] minReg=1> LCL_VAR BB07 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB08 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB08 regmask=[allInt] minReg=1> LCL_VAR BB09 regmask=[allInt] minReg=1> STORE_LCL_VAR BB09 regmask=[allInt] minReg=1> LCL_VAR BB10 regmask=[allInt] minReg=1 last> LCL_VAR BB10 regmask=[allInt] minReg=1 delay regOptional> SUB BB10 regmask=[allInt] minReg=1> BB10 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR BB10 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR BB10 regmask=[allInt] minReg=1> IND BB10 regmask=[allInt] minReg=1> BB10 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR BB10 regmask=[allInt] minReg=1 delay regOptional> SUB BB10 regmask=[allInt] minReg=1> BB10 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR_ADDR BB10 regmask=[allInt] minReg=1> BB10 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR_ADDR BB10 regmask=[allInt] minReg=1> BB10 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR BB10 regmask=[allInt] minReg=1 last> LCL_VAR BB10 regmask=[allInt] minReg=1> BB10 regmask=[rcx] minReg=1> LCL_VAR BB10 regmask=[rcx] minReg=1 last fixed> BB10 regmask=[rcx] minReg=1> PUTARG_REG BB10 regmask=[rcx] minReg=1 fixed> LCL_VAR_ADDR BB10 regmask=[rdx] minReg=1> BB10 regmask=[rdx] minReg=1> BB10 regmask=[rdx] minReg=1 last fixed> BB10 regmask=[rdx] minReg=1> PUTARG_REG BB10 regmask=[rdx] minReg=1 fixed> BB10 regmask=[r9] minReg=1> LCL_VAR BB10 regmask=[r9] minReg=1 fixed> BB10 regmask=[r9] minReg=1> PUTARG_REG BB10 regmask=[r9] minReg=1 fixed> CNS_INT BB10 regmask=[r8] minReg=1> BB10 regmask=[r8] minReg=1> BB10 regmask=[r8] minReg=1 last fixed> BB10 regmask=[r8] minReg=1> PUTARG_REG BB10 regmask=[r8] minReg=1 fixed> BB10 regmask=[rcx] minReg=1> BB10 regmask=[rcx] minReg=1 last fixed> BB10 regmask=[rdx] minReg=1> BB10 regmask=[rdx] minReg=1 last fixed> BB10 regmask=[r9] minReg=1> BB10 regmask=[r9] minReg=1 last fixed> BB10 regmask=[r8] minReg=1> BB10 regmask=[r8] minReg=1 last fixed> BB10 regmask=[rax] minReg=1 last> BB10 regmask=[rcx] minReg=1 last> BB10 regmask=[rdx] minReg=1 last> BB10 regmask=[r8] minReg=1 last> BB10 regmask=[r9] minReg=1 last> BB10 regmask=[r10] minReg=1 last> BB10 regmask=[r11] minReg=1 last> LCL_VAR BB10 regmask=[allInt] minReg=1 regOptional> BB11 regmask=[rcx] minReg=1> LCL_VAR BB11 regmask=[rcx] minReg=1 fixed> BB11 regmask=[rcx] minReg=1> PUTARG_REG BB11 regmask=[rcx] minReg=1 fixed> BB11 regmask=[rcx] minReg=1> BB11 regmask=[rcx] minReg=1 last fixed> BB11 regmask=[rax] minReg=1 last> BB11 regmask=[rcx] minReg=1 last> BB11 regmask=[rdx] minReg=1 last> BB11 regmask=[r8] minReg=1 last> BB11 regmask=[r9] minReg=1 last> BB11 regmask=[r10] minReg=1 last> BB11 regmask=[r11] minReg=1 last> BB11 regmask=[rax] minReg=1> CALL BB11 regmask=[rax] minReg=1 fixed> BB11 regmask=[allInt] minReg=1 last> CAST BB11 regmask=[allInt] minReg=1> LCL_VAR BB11 regmask=[allInt] minReg=1> CAST BB11 regmask=[allInt] minReg=1> BB11 regmask=[allInt] minReg=1 last regOptional> BB11 regmask=[allInt] minReg=1 last> BB12 regmask=[rcx] minReg=1> LCL_VAR BB12 regmask=[rcx] minReg=1 fixed> BB12 regmask=[rcx] minReg=1> PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed> LCL_VAR BB12 regmask=[allInt] minReg=1 last> IND BB12 regmask=[allInt] minReg=1> BB12 regmask=[allInt] minReg=1 last> IND BB12 regmask=[allInt] minReg=1> BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> BB12 regmask=[allInt] minReg=1 last> BB12 regmask=[rax] minReg=1 last> BB12 regmask=[rcx] minReg=1 last> BB12 regmask=[rdx] minReg=1 last> BB12 regmask=[r8] minReg=1 last> BB12 regmask=[r9] minReg=1 last> BB12 regmask=[r10] minReg=1 last> BB12 regmask=[r11] minReg=1 last> BB12 regmask=[rax] minReg=1> CALL BB12 regmask=[rax] minReg=1 fixed> LCL_VAR BB12 regmask=[allInt] minReg=1 last> BB12 regmask=[allInt] minReg=1 last> CNS_INT BB12 regmask=[rax] minReg=1> BB12 regmask=[rax] minReg=1> BB12 regmask=[rax] minReg=1 last fixed> LCL_VAR_ADDR BB13 regmask=[rcx] minReg=1> BB13 regmask=[rcx] minReg=1> BB13 regmask=[rcx] minReg=1 last fixed> BB13 regmask=[rcx] minReg=1> PUTARG_REG BB13 regmask=[rcx] minReg=1 fixed> BB13 regmask=[rdx] minReg=1> LCL_VAR BB13 regmask=[rdx] minReg=1 last fixed> BB13 regmask=[rdx] minReg=1> PUTARG_REG BB13 regmask=[rdx] minReg=1 fixed> BB13 regmask=[rcx] minReg=1> BB13 regmask=[rcx] minReg=1 last fixed> BB13 regmask=[rdx] minReg=1> BB13 regmask=[rdx] minReg=1 last fixed> BB13 regmask=[rax] minReg=1 last> BB13 regmask=[rcx] minReg=1 last> BB13 regmask=[rdx] minReg=1 last> BB13 regmask=[r8] minReg=1 last> BB13 regmask=[r9] minReg=1 last> BB13 regmask=[r10] minReg=1 last> BB13 regmask=[r11] minReg=1 last> LCL_VAR_ADDR BB14 regmask=[allInt] minReg=1> BB14 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1> BB14 regmask=[allInt] minReg=1 last> LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1 last> BB14 regmask=[allInt] minReg=1 last> LCL_VAR_ADDR BB14 regmask=[rcx] minReg=1> BB14 regmask=[rcx] minReg=1> BB14 regmask=[rcx] minReg=1 last fixed> BB14 regmask=[rcx] minReg=1> PUTARG_REG BB14 regmask=[rcx] minReg=1 fixed> LCL_VAR_ADDR BB14 regmask=[rdx] minReg=1> BB14 regmask=[rdx] minReg=1> BB14 regmask=[rdx] minReg=1 last fixed> BB14 regmask=[rdx] minReg=1> PUTARG_REG BB14 regmask=[rdx] minReg=1 fixed> BB14 regmask=[rcx] minReg=1> BB14 regmask=[rcx] minReg=1 last fixed> BB14 regmask=[rdx] minReg=1> BB14 regmask=[rdx] minReg=1 last fixed> BB14 regmask=[rax] minReg=1 last> BB14 regmask=[rcx] minReg=1 last> BB14 regmask=[rdx] minReg=1 last> BB14 regmask=[r8] minReg=1 last> BB14 regmask=[r9] minReg=1 last> BB14 regmask=[r10] minReg=1 last> BB14 regmask=[r11] minReg=1 last> BB14 regmask=[rax] minReg=1> CALL BB14 regmask=[rax] minReg=1 fixed> BB14 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB15 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB16 regmask=[allInt] minReg=1 last> LCL_VAR BB16 regmask=[allInt] minReg=1 last regOptional> NE BB16 regmask=[r8] minReg=1> BB16 regmask=[r8] minReg=1> BB16 regmask=[r8] minReg=1 last fixed> BB16 regmask=[r8] minReg=1> PUTARG_REG BB16 regmask=[r8] minReg=1 fixed> LCL_VAR BB16 regmask=[rcx] minReg=1> BB16 regmask=[rcx] minReg=1> BB16 regmask=[rcx] minReg=1 last fixed> BB16 regmask=[rcx] minReg=1> PUTARG_REG BB16 regmask=[rcx] minReg=1 fixed> BB16 regmask=[rdx] minReg=1> LCL_VAR BB16 regmask=[rdx] minReg=1 last fixed> BB16 regmask=[rdx] minReg=1> PUTARG_REG BB16 regmask=[rdx] minReg=1 fixed> BB16 regmask=[r9] minReg=1> LCL_VAR BB16 regmask=[r9] minReg=1 last fixed> BB16 regmask=[r9] minReg=1> PUTARG_REG BB16 regmask=[r9] minReg=1 fixed> BB16 regmask=[r8] minReg=1> BB16 regmask=[r8] minReg=1 last fixed> BB16 regmask=[rcx] minReg=1> BB16 regmask=[rcx] minReg=1 last fixed> BB16 regmask=[rdx] minReg=1> BB16 regmask=[rdx] minReg=1 last fixed> BB16 regmask=[r9] minReg=1> BB16 regmask=[r9] minReg=1 last fixed> BB16 regmask=[rax] minReg=1 last> BB16 regmask=[rcx] minReg=1 last> BB16 regmask=[rdx] minReg=1 last> BB16 regmask=[r8] minReg=1 last> BB16 regmask=[r9] minReg=1 last> BB16 regmask=[r10] minReg=1 last> BB16 regmask=[r11] minReg=1 last> BB16 regmask=[rax] minReg=1> CALL BB16 regmask=[rax] minReg=1 fixed> BB16 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB16 regmask=[allInt] minReg=1> LCL_VAR BB17 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB18 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB18 regmask=[allInt] minReg=1> LCL_VAR BB19 regmask=[allInt] minReg=1 last> LCL_VAR BB19 regmask=[allInt] minReg=1 delay regOptional> SUB BB19 regmask=[allInt] minReg=1> BB19 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB19 regmask=[allInt] minReg=1> LCL_VAR BB20 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB20 regmask=[allInt] minReg=1> LCL_VAR BB20 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB21 regmask=[allInt] minReg=1> IND BB21 regmask=[allInt] minReg=1> BB21 regmask=[allInt] minReg=1 last> CAST BB21 regmask=[allInt] minReg=1> LCL_VAR BB21 regmask=[allInt] minReg=1> CAST BB21 regmask=[allInt] minReg=1> BB21 regmask=[allInt] minReg=1 last> BB21 regmask=[allInt] minReg=1 last delay regOptional> SUB BB21 regmask=[allInt] minReg=1> BB21 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB21 regmask=[allInt] minReg=1> BB21 regmask=[rcx] minReg=1> LCL_VAR BB21 regmask=[rcx] minReg=1 fixed> BB21 regmask=[rcx] minReg=1> PUTARG_REG BB21 regmask=[rcx] minReg=1 fixed> BB21 regmask=[rcx] minReg=1> BB21 regmask=[rcx] minReg=1 last fixed> BB21 regmask=[rax] minReg=1 last> BB21 regmask=[rcx] minReg=1 last> BB21 regmask=[rdx] minReg=1 last> BB21 regmask=[r8] minReg=1 last> BB21 regmask=[r9] minReg=1 last> BB21 regmask=[r10] minReg=1 last> BB21 regmask=[r11] minReg=1 last> BB21 regmask=[rax] minReg=1> CALL BB21 regmask=[rax] minReg=1 fixed> BB21 regmask=[allInt] minReg=1 last> CAST BB21 regmask=[allInt] minReg=1> BB21 regmask=[allInt] minReg=1 last> LCL_VAR BB21 regmask=[allInt] minReg=1 last regOptional> BB22 regmask=[rcx] minReg=1> LCL_VAR BB22 regmask=[rcx] minReg=1 fixed> BB22 regmask=[rcx] minReg=1> PUTARG_REG BB22 regmask=[rcx] minReg=1 fixed> LCL_VAR BB22 regmask=[allInt] minReg=1 last> IND BB22 regmask=[allInt] minReg=1> BB22 regmask=[allInt] minReg=1 last> IND BB22 regmask=[allInt] minReg=1> BB22 regmask=[rcx] minReg=1> BB22 regmask=[rcx] minReg=1 last fixed> BB22 regmask=[allInt] minReg=1 last> BB22 regmask=[rax] minReg=1 last> BB22 regmask=[rcx] minReg=1 last> BB22 regmask=[rdx] minReg=1 last> BB22 regmask=[r8] minReg=1 last> BB22 regmask=[r9] minReg=1 last> BB22 regmask=[r10] minReg=1 last> BB22 regmask=[r11] minReg=1 last> BB22 regmask=[rax] minReg=1> CALL BB22 regmask=[rax] minReg=1 fixed> LCL_VAR BB22 regmask=[allInt] minReg=1 last> BB22 regmask=[allInt] minReg=1 last> CNS_INT BB22 regmask=[rax] minReg=1> BB22 regmask=[rax] minReg=1> BB22 regmask=[rax] minReg=1 last fixed> LCL_VAR_ADDR BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR_ADDR BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 last> LCL_VAR BB23 regmask=[allInt] minReg=1 last> LCL_VAR BB23 regmask=[allInt] minReg=1 last> BB23 regmask=[rcx] minReg=1> LCL_VAR BB23 regmask=[rcx] minReg=1 last fixed> BB23 regmask=[rcx] minReg=1> PUTARG_REG BB23 regmask=[rcx] minReg=1 fixed> LCL_VAR_ADDR BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last fixed> BB23 regmask=[rdx] minReg=1> PUTARG_REG BB23 regmask=[rdx] minReg=1 fixed> BB23 regmask=[r8] minReg=1> LCL_VAR BB23 regmask=[r8] minReg=1 last fixed> BB23 regmask=[r8] minReg=1> PUTARG_REG BB23 regmask=[r8] minReg=1 fixed> BB23 regmask=[r9] minReg=1> LCL_VAR BB23 regmask=[r9] minReg=1 last fixed> BB23 regmask=[r9] minReg=1> PUTARG_REG BB23 regmask=[r9] minReg=1 fixed> BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last fixed> BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last fixed> BB23 regmask=[r8] minReg=1> BB23 regmask=[r8] minReg=1 last fixed> BB23 regmask=[r9] minReg=1> BB23 regmask=[r9] minReg=1 last fixed> BB23 regmask=[rax] minReg=1 last> BB23 regmask=[rcx] minReg=1 last> BB23 regmask=[rdx] minReg=1 last> BB23 regmask=[r8] minReg=1 last> BB23 regmask=[r9] minReg=1 last> BB23 regmask=[r10] minReg=1 last> BB23 regmask=[r11] minReg=1 last> CNS_INT BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last fixed> BB23 regmask=[rcx] minReg=1> PUTARG_REG BB23 regmask=[rcx] minReg=1 fixed> CNS_INT BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last fixed> BB23 regmask=[rdx] minReg=1> PUTARG_REG BB23 regmask=[rdx] minReg=1 fixed> BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last fixed> BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last fixed> BB23 regmask=[rax] minReg=1 last> BB23 regmask=[rcx] minReg=1 last> BB23 regmask=[rdx] minReg=1 last> BB23 regmask=[r8] minReg=1 last> BB23 regmask=[r9] minReg=1 last> BB23 regmask=[r10] minReg=1 last> BB23 regmask=[r11] minReg=1 last> BB23 regmask=[rax] minReg=1> CALL BB23 regmask=[rax] minReg=1 last fixed local> CNS_INT BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 last> IND BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 last> ADD BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1> IND BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 last> LCL_VAR BB23 regmask=[allInt] minReg=1 last> IND BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 last> LCL_VAR_ADDR BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last fixed> BB23 regmask=[rcx] minReg=1> PUTARG_REG BB23 regmask=[rcx] minReg=1 fixed> BB23 regmask=[rdx] minReg=1> LCL_VAR BB23 regmask=[rdx] minReg=1 last fixed> BB23 regmask=[rdx] minReg=1> PUTARG_REG BB23 regmask=[rdx] minReg=1 fixed> BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last fixed> BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last fixed> BB23 regmask=[rax] minReg=1 last> BB23 regmask=[rcx] minReg=1 last> BB23 regmask=[rdx] minReg=1 last> BB23 regmask=[r8] minReg=1 last> BB23 regmask=[r9] minReg=1 last> BB23 regmask=[r10] minReg=1 last> BB23 regmask=[r11] minReg=1 last> LCL_VAR BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR_ADDR BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 last> LCL_VAR BB23 regmask=[allInt] minReg=1 last> LCL_VAR BB23 regmask=[allInt] minReg=1 last> LCL_VAR_ADDR BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last fixed> BB23 regmask=[rcx] minReg=1> PUTARG_REG BB23 regmask=[rcx] minReg=1 fixed> LCL_VAR_ADDR BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last fixed> BB23 regmask=[rdx] minReg=1> PUTARG_REG BB23 regmask=[rdx] minReg=1 fixed> BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last fixed> BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last fixed> BB23 regmask=[rax] minReg=1 last> BB23 regmask=[rcx] minReg=1 last> BB23 regmask=[rdx] minReg=1 last> BB23 regmask=[r8] minReg=1 last> BB23 regmask=[r9] minReg=1 last> BB23 regmask=[r10] minReg=1 last> BB23 regmask=[r11] minReg=1 last> BB23 regmask=[rax] minReg=1> CALL BB23 regmask=[rax] minReg=1 fixed> BB23 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> CNS_INT BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 last> LCL_VAR BB23 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR_ADDR BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 last> LCL_VAR BB23 regmask=[allInt] minReg=1 last> LCL_VAR BB23 regmask=[allInt] minReg=1 last> LCL_VAR_ADDR BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last fixed> BB23 regmask=[rcx] minReg=1> PUTARG_REG BB23 regmask=[rcx] minReg=1 fixed> LCL_VAR_ADDR BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last fixed> BB23 regmask=[rdx] minReg=1> PUTARG_REG BB23 regmask=[rdx] minReg=1 fixed> BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last fixed> BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last fixed> BB23 regmask=[rax] minReg=1 last> BB23 regmask=[rcx] minReg=1 last> BB23 regmask=[rdx] minReg=1 last> BB23 regmask=[r8] minReg=1 last> BB23 regmask=[r9] minReg=1 last> BB23 regmask=[r10] minReg=1 last> BB23 regmask=[r11] minReg=1 last> BB23 regmask=[rax] minReg=1> CALL BB23 regmask=[rax] minReg=1 fixed> BB23 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> CNS_INT BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 last> LCL_VAR BB23 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 regOptional> CNS_INT BB24 regmask=[allInt] minReg=1> BB24 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB24 regmask=[allInt] minReg=1> LCL_VAR BB25 regmask=[allInt] minReg=1 last> LCL_VAR BB25 regmask=[allInt] minReg=1 last delay regOptional> SUB BB25 regmask=[allInt] minReg=1> BB25 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB25 regmask=[allInt] minReg=1> LCL_VAR BB26 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB26 regmask=[allInt] minReg=1> LCL_VAR BB26 regmask=[allInt] minReg=1 regOptional> LCL_VAR_ADDR BB27 regmask=[rcx] minReg=1> BB27 regmask=[rcx] minReg=1> BB27 regmask=[rcx] minReg=1 last fixed> BB27 regmask=[rcx] minReg=1> PUTARG_REG BB27 regmask=[rcx] minReg=1 fixed> BB27 regmask=[rdx] minReg=1> LCL_VAR BB27 regmask=[rdx] minReg=1 fixed> BB27 regmask=[rdx] minReg=1> PUTARG_REG BB27 regmask=[rdx] minReg=1 fixed> BB27 regmask=[rcx] minReg=1> BB27 regmask=[rcx] minReg=1 last fixed> BB27 regmask=[rdx] minReg=1> BB27 regmask=[rdx] minReg=1 last fixed> BB27 regmask=[rax] minReg=1 last> BB27 regmask=[rcx] minReg=1 last> BB27 regmask=[rdx] minReg=1 last> BB27 regmask=[r8] minReg=1 last> BB27 regmask=[r9] minReg=1 last> BB27 regmask=[r10] minReg=1 last> BB27 regmask=[r11] minReg=1 last> LCL_VAR BB28 regmask=[allInt] minReg=1 last> LCL_VAR BB28 regmask=[allInt] minReg=1 delay regOptional> SUB BB28 regmask=[allInt] minReg=1> BB28 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB28 regmask=[allInt] minReg=1> LCL_VAR BB28 regmask=[allInt] minReg=1> STORE_LCL_VAR BB28 regmask=[allInt] minReg=1> LCL_VAR BB28 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB29 regmask=[allInt] minReg=1> LCL_VAR BB29 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB30 regmask=[allInt] minReg=1 last> CNS_INT BB30 regmask=[r8] minReg=1> BB30 regmask=[r8] minReg=1> BB30 regmask=[r8] minReg=1 last fixed> BB30 regmask=[r8] minReg=1> PUTARG_REG BB30 regmask=[r8] minReg=1 fixed> LCL_VAR BB30 regmask=[rcx] minReg=1> BB30 regmask=[rcx] minReg=1> BB30 regmask=[rcx] minReg=1 last fixed> BB30 regmask=[rcx] minReg=1> PUTARG_REG BB30 regmask=[rcx] minReg=1 fixed> BB30 regmask=[rdx] minReg=1> LCL_VAR BB30 regmask=[rdx] minReg=1 last fixed> BB30 regmask=[rdx] minReg=1> PUTARG_REG BB30 regmask=[rdx] minReg=1 fixed> BB30 regmask=[r9] minReg=1> LCL_VAR BB30 regmask=[r9] minReg=1 last fixed> BB30 regmask=[r9] minReg=1> PUTARG_REG BB30 regmask=[r9] minReg=1 fixed> BB30 regmask=[r8] minReg=1> BB30 regmask=[r8] minReg=1 last fixed> BB30 regmask=[rcx] minReg=1> BB30 regmask=[rcx] minReg=1 last fixed> BB30 regmask=[rdx] minReg=1> BB30 regmask=[rdx] minReg=1 last fixed> BB30 regmask=[r9] minReg=1> BB30 regmask=[r9] minReg=1 last fixed> BB30 regmask=[rax] minReg=1 last> BB30 regmask=[rcx] minReg=1 last> BB30 regmask=[rdx] minReg=1 last> BB30 regmask=[r8] minReg=1 last> BB30 regmask=[r9] minReg=1 last> BB30 regmask=[r10] minReg=1 last> BB30 regmask=[r11] minReg=1 last> BB30 regmask=[rax] minReg=1> CALL BB30 regmask=[rax] minReg=1 fixed> BB30 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB30 regmask=[allInt] minReg=1> LCL_VAR BB31 regmask=[allInt] minReg=1> LCL_VAR BB31 regmask=[allInt] minReg=1 delay regOptional> SUB BB31 regmask=[allInt] minReg=1> BB31 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB31 regmask=[allInt] minReg=1> LCL_VAR BB32 regmask=[allInt] minReg=1> BB32 regmask=[allInt] minReg=1 last> LCL_VAR BB32 regmask=[allInt] minReg=1> BB32 regmask=[allInt] minReg=1 last> LCL_VAR BB32 regmask=[allInt] minReg=1> BB32 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR BB32 regmask=[allInt] minReg=1> BB32 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR_ADDR BB32 regmask=[allInt] minReg=1> BB32 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR_ADDR BB32 regmask=[allInt] minReg=1> BB32 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR BB32 regmask=[allInt] minReg=1 last> LCL_VAR BB32 regmask=[allInt] minReg=1 last> LCL_VAR BB32 regmask=[allInt] minReg=1 last> BB32 regmask=[rcx] minReg=1> LCL_VAR BB32 regmask=[rcx] minReg=1 last fixed> BB32 regmask=[rcx] minReg=1> PUTARG_REG BB32 regmask=[rcx] minReg=1 fixed> LCL_VAR_ADDR BB32 regmask=[rdx] minReg=1> BB32 regmask=[rdx] minReg=1> BB32 regmask=[rdx] minReg=1 last fixed> BB32 regmask=[rdx] minReg=1> PUTARG_REG BB32 regmask=[rdx] minReg=1 fixed> BB32 regmask=[rcx] minReg=1> BB32 regmask=[rcx] minReg=1 last fixed> BB32 regmask=[rdx] minReg=1> BB32 regmask=[rdx] minReg=1 last fixed> BB32 regmask=[rax] minReg=1 last> BB32 regmask=[rcx] minReg=1 last> BB32 regmask=[rdx] minReg=1 last> BB32 regmask=[r8] minReg=1 last> BB32 regmask=[r9] minReg=1 last> BB32 regmask=[r10] minReg=1 last> BB32 regmask=[r11] minReg=1 last> BB32 regmask=[rax] minReg=1> CALL BB32 regmask=[rax] minReg=1 fixed> BB32 regmask=[allInt] minReg=1 last regOptional> LCL_VAR BB33 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB33 regmask=[allInt] minReg=1> LCL_VAR BB34 regmask=[allInt] minReg=1 last> ADD BB34 regmask=[allInt] minReg=1> BB34 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB34 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR_ADDR BB35 regmask=[rcx] minReg=1> BB35 regmask=[rcx] minReg=1> BB35 regmask=[rcx] minReg=1 last fixed> BB35 regmask=[rcx] minReg=1> PUTARG_REG BB35 regmask=[rcx] minReg=1 fixed> BB35 regmask=[rdx] minReg=1> LCL_VAR BB35 regmask=[rdx] minReg=1 last fixed> BB35 regmask=[rdx] minReg=1> PUTARG_REG BB35 regmask=[rdx] minReg=1 fixed> BB35 regmask=[rcx] minReg=1> BB35 regmask=[rcx] minReg=1 last fixed> BB35 regmask=[rdx] minReg=1> BB35 regmask=[rdx] minReg=1 last fixed> BB35 regmask=[rax] minReg=1 last> BB35 regmask=[rcx] minReg=1 last> BB35 regmask=[rdx] minReg=1 last> BB35 regmask=[r8] minReg=1 last> BB35 regmask=[r9] minReg=1 last> BB35 regmask=[r10] minReg=1 last> BB35 regmask=[r11] minReg=1 last> LCL_VAR_ADDR BB35 regmask=[allInt] minReg=1> BB35 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR_ADDR BB35 regmask=[allInt] minReg=1> BB35 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1> BB35 regmask=[allInt] minReg=1 last> LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1 last> BB35 regmask=[allInt] minReg=1 last> LCL_VAR_ADDR BB35 regmask=[allInt] minReg=1> BB35 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1> BB35 regmask=[allInt] minReg=1 last> LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1 last> BB35 regmask=[allInt] minReg=1 last> BB35 regmask=[rcx] minReg=1> LCL_VAR BB35 regmask=[rcx] minReg=1 last fixed> BB35 regmask=[rcx] minReg=1> PUTARG_REG BB35 regmask=[rcx] minReg=1 fixed> LCL_VAR_ADDR BB35 regmask=[rdx] minReg=1> BB35 regmask=[rdx] minReg=1> BB35 regmask=[rdx] minReg=1 last fixed> BB35 regmask=[rdx] minReg=1> PUTARG_REG BB35 regmask=[rdx] minReg=1 fixed> LCL_VAR_ADDR BB35 regmask=[r8] minReg=1> BB35 regmask=[r8] minReg=1> BB35 regmask=[r8] minReg=1 last fixed> BB35 regmask=[r8] minReg=1> PUTARG_REG BB35 regmask=[r8] minReg=1 fixed> LCL_VAR_ADDR BB35 regmask=[r9] minReg=1> BB35 regmask=[r9] minReg=1> BB35 regmask=[r9] minReg=1 last fixed> BB35 regmask=[r9] minReg=1> PUTARG_REG BB35 regmask=[r9] minReg=1 fixed> BB35 regmask=[rcx] minReg=1> BB35 regmask=[rcx] minReg=1 last fixed> BB35 regmask=[rdx] minReg=1> BB35 regmask=[rdx] minReg=1 last fixed> BB35 regmask=[r8] minReg=1> BB35 regmask=[r8] minReg=1 last fixed> BB35 regmask=[r9] minReg=1> BB35 regmask=[r9] minReg=1 last fixed> BB35 regmask=[rax] minReg=1 last> BB35 regmask=[rcx] minReg=1 last> BB35 regmask=[rdx] minReg=1 last> BB35 regmask=[r8] minReg=1 last> BB35 regmask=[r9] minReg=1 last> BB35 regmask=[r10] minReg=1 last> BB35 regmask=[r11] minReg=1 last> LCL_VAR_ADDR BB35 regmask=[allInt] minReg=1> BB35 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1> BB35 regmask=[allInt] minReg=1 last> LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1 last> BB35 regmask=[allInt] minReg=1 last> LCL_VAR_ADDR BB35 regmask=[rcx] minReg=1> BB35 regmask=[rcx] minReg=1> BB35 regmask=[rcx] minReg=1 last fixed> BB35 regmask=[rcx] minReg=1> PUTARG_REG BB35 regmask=[rcx] minReg=1 fixed> BB35 regmask=[rcx] minReg=1> BB35 regmask=[rcx] minReg=1 last fixed> BB35 regmask=[rax] minReg=1 last> BB35 regmask=[rcx] minReg=1 last> BB35 regmask=[rdx] minReg=1 last> BB35 regmask=[r8] minReg=1 last> BB35 regmask=[r9] minReg=1 last> BB35 regmask=[r10] minReg=1 last> BB35 regmask=[r11] minReg=1 last> BB35 regmask=[rax] minReg=1> CALL BB35 regmask=[rax] minReg=1 fixed> BB35 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> EQ BB35 regmask=[allInt] minReg=1> BB35 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> BB35 regmask=[rcx] minReg=1> LCL_VAR BB35 regmask=[rcx] minReg=1 fixed> BB35 regmask=[rcx] minReg=1> PUTARG_REG BB35 regmask=[rcx] minReg=1 fixed> BB35 regmask=[rcx] minReg=1> BB35 regmask=[rcx] minReg=1 last fixed> BB35 regmask=[rax] minReg=1 last> BB35 regmask=[rcx] minReg=1 last> BB35 regmask=[rdx] minReg=1 last> BB35 regmask=[r8] minReg=1 last> BB35 regmask=[r9] minReg=1 last> BB35 regmask=[r10] minReg=1 last> BB35 regmask=[r11] minReg=1 last> BB35 regmask=[rax] minReg=1> CALL BB35 regmask=[rax] minReg=1 fixed> BB35 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB36 regmask=[allInt] minReg=1 last> LCL_VAR BB36 regmask=[allInt] minReg=1 delay regOptional> SUB BB36 regmask=[allInt] minReg=1> BB36 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB36 regmask=[allInt] minReg=1> LCL_VAR BB36 regmask=[allInt] minReg=1 last regOptional> CNS_INT BB37 regmask=[rax rdx rbx rbp rsi rdi r8-r15] minReg=1> BB37 regmask=[rax rdx rbx rbp rsi rdi r8-r15] minReg=1 last> BB37 regmask=[rcx] minReg=1> LCL_VAR BB37 regmask=[rcx] minReg=1 fixed delay> BB37 regmask=[rcx] minReg=1 last> LSH BB37 regmask=[rax rdx rbx rbp rsi rdi r8-r15] minReg=1> BB37 regmask=[allInt] minReg=1 last> ADD BB37 regmask=[allInt] minReg=1> LCL_VAR BB37 regmask=[allInt] minReg=1 regOptional> BB37 regmask=[allInt] minReg=1 last> TEST_EQ BB37 regmask=[allInt] minReg=1> BB37 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB37 regmask=[allInt] minReg=1> CNS_INT BB38 regmask=[allInt] minReg=1> BB38 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB38 regmask=[allInt] minReg=1> LCL_VAR BB39 regmask=[allInt] minReg=1 last> CAST BB39 regmask=[allInt] minReg=1> BB39 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB39 regmask=[allInt] minReg=1> LCL_VAR BB39 regmask=[rax rdx rbx rbp rsi rdi r8-r15] minReg=1 last> BB39 regmask=[rcx] minReg=1> LCL_VAR BB39 regmask=[rcx] minReg=1 last fixed delay> BB39 regmask=[rcx] minReg=1 last> RSZ BB39 regmask=[rax rdx rbx rbp rsi rdi r8-r15] minReg=1> BB39 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB39 regmask=[allInt] minReg=1> LCL_VAR_ADDR BB40 regmask=[allInt] minReg=1> BB40 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB40 regmask=[allInt] minReg=1> LCL_VAR BB40 regmask=[allInt] minReg=1> LCL_VAR BB40 regmask=[allInt] minReg=1> BB40 regmask=[allInt] minReg=1 last> LCL_VAR BB40 regmask=[allInt] minReg=1> LCL_VAR BB40 regmask=[allInt] minReg=1 last> BB40 regmask=[allInt] minReg=1 last> LCL_VAR_ADDR BB40 regmask=[rcx] minReg=1> BB40 regmask=[rcx] minReg=1> BB40 regmask=[rcx] minReg=1 last fixed> BB40 regmask=[rcx] minReg=1> PUTARG_REG BB40 regmask=[rcx] minReg=1 fixed> BB40 regmask=[rcx] minReg=1> BB40 regmask=[rcx] minReg=1 last fixed> BB40 regmask=[rax] minReg=1 last> BB40 regmask=[rcx] minReg=1 last> BB40 regmask=[rdx] minReg=1 last> BB40 regmask=[r8] minReg=1 last> BB40 regmask=[r9] minReg=1 last> BB40 regmask=[r10] minReg=1 last> BB40 regmask=[r11] minReg=1 last> BB40 regmask=[rax] minReg=1> CALL BB40 regmask=[rax] minReg=1 fixed> BB40 regmask=[rax rdx rbx rbp rsi rdi r8-r15] minReg=1 last> BB40 regmask=[rcx] minReg=1> LCL_VAR BB40 regmask=[rcx] minReg=1 last fixed delay> BB40 regmask=[rcx] minReg=1 last> LSH BB40 regmask=[rax rdx rbx rbp rsi rdi r8-r15] minReg=1> BB40 regmask=[allInt] minReg=1 last> LCL_VAR BB40 regmask=[allInt] minReg=1 last regOptional> ADD BB40 regmask=[allInt] minReg=1> BB40 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB40 regmask=[allInt] minReg=1> LCL_VAR BB40 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB41 regmask=[allInt] minReg=1 last> NEG BB41 regmask=[allInt] minReg=1> BB41 regmask=[allInt] minReg=1 last> ADD BB41 regmask=[allInt] minReg=1> BB41 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB41 regmask=[allInt] minReg=1> LCL_VAR BB42 regmask=[allInt] minReg=1 last> ADD BB42 regmask=[allInt] minReg=1> BB42 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB42 regmask=[allInt] minReg=1> LCL_VAR BB43 regmask=[allInt] minReg=1 last> BB43 regmask=[rcx] minReg=1> LCL_VAR BB43 regmask=[rcx] minReg=1 last fixed> BB43 regmask=[rcx] minReg=1> PUTARG_REG BB43 regmask=[rcx] minReg=1 fixed> BB43 regmask=[rdx] minReg=1> LCL_VAR BB43 regmask=[rdx] minReg=1 last fixed> BB43 regmask=[rdx] minReg=1> PUTARG_REG BB43 regmask=[rdx] minReg=1 fixed> BB43 regmask=[r8] minReg=1> LCL_VAR BB43 regmask=[r8] minReg=1 last fixed> BB43 regmask=[r8] minReg=1> PUTARG_REG BB43 regmask=[r8] minReg=1 fixed> BB43 regmask=[r9] minReg=1> LCL_VAR BB43 regmask=[r9] minReg=1 last fixed> BB43 regmask=[r9] minReg=1> PUTARG_REG BB43 regmask=[r9] minReg=1 fixed> BB43 regmask=[rcx] minReg=1> BB43 regmask=[rcx] minReg=1 last fixed> BB43 regmask=[rdx] minReg=1> BB43 regmask=[rdx] minReg=1 last fixed> BB43 regmask=[r8] minReg=1> BB43 regmask=[r8] minReg=1 last fixed> BB43 regmask=[r9] minReg=1> BB43 regmask=[r9] minReg=1 last fixed> BB43 regmask=[rax] minReg=1 last> BB43 regmask=[rcx] minReg=1 last> BB43 regmask=[rdx] minReg=1 last> BB43 regmask=[r8] minReg=1 last> BB43 regmask=[r9] minReg=1 last> BB43 regmask=[r10] minReg=1 last> BB43 regmask=[r11] minReg=1 last> BB43 regmask=[rax] minReg=1> CALL BB43 regmask=[rax] minReg=1 fixed> BB43 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB43 regmask=[allInt] minReg=1> BB44 regmask=[rax] minReg=1> LCL_VAR BB44 regmask=[rax] minReg=1 last fixed> VAR REFPOSITIONS BEFORE ALLOCATION --- V00 (Interval 0) BB00 regmask=[rcx] minReg=1 fixed regOptional> LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> --- V01 (Interval 1) BB00 regmask=[rdx] minReg=1 fixed regOptional> LCL_VAR BB03 regmask=[rcx] minReg=1 fixed> LCL_VAR BB03 regmask=[allInt] minReg=1 last> LCL_VAR BB04 regmask=[rcx] minReg=1 fixed> LCL_VAR BB04 regmask=[allInt] minReg=1> LCL_VAR BB11 regmask=[rcx] minReg=1 fixed> LCL_VAR BB12 regmask=[rcx] minReg=1 fixed> LCL_VAR BB12 regmask=[allInt] minReg=1 last> LCL_VAR BB16 regmask=[r9] minReg=1 last fixed> LCL_VAR BB21 regmask=[rcx] minReg=1 fixed> LCL_VAR BB22 regmask=[rcx] minReg=1 fixed> LCL_VAR BB22 regmask=[allInt] minReg=1 last> LCL_VAR BB30 regmask=[r9] minReg=1 last fixed> LCL_VAR BB43 regmask=[rcx] minReg=1 last fixed> --- V02 (Interval 2) BB00 regmask=[r8] minReg=1 fixed regOptional> LCL_VAR BB03 regmask=[allInt] minReg=1 last> LCL_VAR BB12 regmask=[allInt] minReg=1 last> LCL_VAR BB16 regmask=[allInt] minReg=1 last> LCL_VAR BB22 regmask=[allInt] minReg=1 last> LCL_VAR BB30 regmask=[allInt] minReg=1 last> LCL_VAR BB43 regmask=[allInt] minReg=1 last> --- V03 (Interval 3) STORE_LCL_VAR BB04 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB28 regmask=[allInt] minReg=1 last> --- V04 --- V05 (Interval 4) STORE_LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR BB10 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB11 regmask=[allInt] minReg=1> LCL_VAR BB13 regmask=[rdx] minReg=1 last fixed> --- V06 --- V07 --- V08 (Interval 5) STORE_LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR BB10 regmask=[allInt] minReg=1 delay regOptional> LCL_VAR BB10 regmask=[r9] minReg=1 fixed> LCL_VAR BB23 regmask=[r8] minReg=1 last fixed> --- V09 (Interval 6) STORE_LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[r9] minReg=1 last fixed> --- V10 (Interval 7) STORE_LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR BB15 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB16 regmask=[allInt] minReg=1 last regOptional> LCL_VAR BB18 regmask=[allInt] minReg=1 last> LCL_VAR BB19 regmask=[allInt] minReg=1 last> --- V11 --- V12 --- V13 (Interval 8) STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB16 regmask=[rdx] minReg=1 last fixed> LCL_VAR BB20 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB28 regmask=[allInt] minReg=1 delay regOptional> LCL_VAR BB28 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB30 regmask=[rdx] minReg=1 last fixed> LCL_VAR BB40 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB42 regmask=[allInt] minReg=1 last> --- V14 (Interval 9) STORE_LCL_VAR BB20 regmask=[allInt] minReg=1> LCL_VAR BB21 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[rdx] minReg=1 last fixed> --- V15 --- V16 --- V17 (Interval 10) STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB25 regmask=[allInt] minReg=1 last delay regOptional> --- V18 (Interval 11) STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB25 regmask=[allInt] minReg=1 last> --- V19 (Interval 12) STORE_LCL_VAR BB26 regmask=[allInt] minReg=1> LCL_VAR BB26 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB27 regmask=[rdx] minReg=1 fixed> LCL_VAR BB29 regmask=[allInt] minReg=1> LCL_VAR BB31 regmask=[allInt] minReg=1 delay regOptional> LCL_VAR BB33 regmask=[allInt] minReg=1 last> LCL_VAR BB34 regmask=[allInt] minReg=1 last> --- V20 (Interval 13) STORE_LCL_VAR BB28 regmask=[allInt] minReg=1> LCL_VAR BB28 regmask=[allInt] minReg=1> LCL_VAR BB29 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB31 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB36 regmask=[allInt] minReg=1 delay regOptional> LCL_VAR BB40 regmask=[rcx] minReg=1 last fixed delay> --- V21 (Interval 14) STORE_LCL_VAR BB28 regmask=[allInt] minReg=1> STORE_LCL_VAR BB31 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[rdx] minReg=1 last fixed> --- V22 (Interval 15) STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB41 regmask=[allInt] minReg=1 last> --- V23 --- V24 (Interval 16) STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[rcx] minReg=1 fixed> LCL_VAR BB37 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB39 regmask=[rax rdx rbx rbp rsi rdi r8-r15] minReg=1 last> STORE_LCL_VAR BB39 regmask=[allInt] minReg=1> LCL_VAR BB40 regmask=[allInt] minReg=1 last regOptional> --- V25 (Interval 17) STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB36 regmask=[allInt] minReg=1 last regOptional> STORE_LCL_VAR BB39 regmask=[allInt] minReg=1> LCL_VAR BB43 regmask=[r9] minReg=1 last fixed> --- V26 (Interval 18) STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB36 regmask=[allInt] minReg=1 last> --- V27 (Interval 19) STORE_LCL_VAR BB40 regmask=[allInt] minReg=1> LCL_VAR BB43 regmask=[rdx] minReg=1 last fixed> --- V28 --- V29 (Interval 20) STORE_LCL_VAR BB36 regmask=[allInt] minReg=1> LCL_VAR BB37 regmask=[rcx] minReg=1 fixed delay> LCL_VAR BB39 regmask=[rcx] minReg=1 last fixed delay> --- V30 --- V31 (Interval 21) STORE_LCL_VAR BB07 regmask=[allInt] minReg=1> LCL_VAR BB07 regmask=[allInt] minReg=1> LCL_VAR BB09 regmask=[allInt] minReg=1> LCL_VAR BB10 regmask=[allInt] minReg=1 last> --- V32 (Interval 22) STORE_LCL_VAR BB18 regmask=[allInt] minReg=1> STORE_LCL_VAR BB19 regmask=[allInt] minReg=1> LCL_VAR BB20 regmask=[allInt] minReg=1 last> --- V33 (Interval 23) STORE_LCL_VAR BB24 regmask=[allInt] minReg=1> STORE_LCL_VAR BB25 regmask=[allInt] minReg=1> LCL_VAR BB26 regmask=[allInt] minReg=1 last> --- V34 (Interval 24) STORE_LCL_VAR BB33 regmask=[allInt] minReg=1> STORE_LCL_VAR BB34 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1 last> --- V35 --- V36 (Interval 25) STORE_LCL_VAR BB41 regmask=[allInt] minReg=1> STORE_LCL_VAR BB42 regmask=[allInt] minReg=1> LCL_VAR BB43 regmask=[r8] minReg=1 last fixed> --- V37 (Interval 26) STORE_LCL_VAR BB37 regmask=[allInt] minReg=1> STORE_LCL_VAR BB38 regmask=[allInt] minReg=1> LCL_VAR BB39 regmask=[allInt] minReg=1 last> --- V38 (Interval 27) STORE_LCL_VAR BB21 regmask=[allInt] minReg=1> LCL_VAR BB21 regmask=[allInt] minReg=1 last regOptional> --- V39 (Interval 28) STORE_LCL_VAR BB05 regmask=[allInt] minReg=1> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1> LCL_VAR BB07 regmask=[allInt] minReg=1 last> --- V40 (Interval 29) STORE_LCL_VAR BB04 regmask=[allInt] minReg=1> LCL_VAR BB04 regmask=[allInt] minReg=1 last regOptional> --- V41 (Interval 30) STORE_LCL_VAR BB08 regmask=[allInt] minReg=1> STORE_LCL_VAR BB09 regmask=[allInt] minReg=1> LCL_VAR BB10 regmask=[allInt] minReg=1 delay regOptional> LCL_VAR BB10 regmask=[allInt] minReg=1 last> --- V42 (Interval 31) STORE_LCL_VAR BB07 regmask=[allInt] minReg=1> LCL_VAR BB07 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB08 regmask=[allInt] minReg=1 last> --- V43 (Interval 32) STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 last> --- V44 --- V45 --- V46 (Interval 33) STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 last> --- V47 --- V48 --- V49 --- V50 --- V51 (Interval 34) STORE_LCL_VAR BB16 regmask=[allInt] minReg=1> STORE_LCL_VAR BB30 regmask=[allInt] minReg=1> STORE_LCL_VAR BB43 regmask=[allInt] minReg=1> LCL_VAR BB44 regmask=[rax] minReg=1 last fixed> --- V52 (Interval 35) STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB07 regmask=[allInt] minReg=1> LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR BB21 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 last> --- V53 (Interval 36) STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB04 regmask=[allInt] minReg=1> LCL_VAR BB05 regmask=[allInt] minReg=1> LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR BB17 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB19 regmask=[allInt] minReg=1 delay regOptional> LCL_VAR BB23 regmask=[allInt] minReg=1 last> --- V54 --- V55 --- V56 --- V57 --- V58 --- V59 --- V60 --- V61 --- V62 --- V63 --- V64 (Interval 37) STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 last> --- V65 (Interval 38) STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 last> --- V66 (Interval 39) STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 last> --- V67 (Interval 40) STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 last> --- V68 --- V69 --- V70 (Interval 41) STORE_LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR BB32 regmask=[allInt] minReg=1 last> --- V71 (Interval 42) STORE_LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR BB32 regmask=[allInt] minReg=1 last> --- V72 --- V73 --- V74 (Interval 43) STORE_LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR BB10 regmask=[allInt] minReg=1 last> --- V75 (Interval 44) STORE_LCL_VAR BB10 regmask=[allInt] minReg=1> LCL_VAR BB10 regmask=[rcx] minReg=1 last fixed> --- V76 --- V77 (Interval 45) STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1 last> --- V78 (Interval 46) STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 last> --- V79 (Interval 47) STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[rcx] minReg=1 last fixed> --- V80 (Interval 48) STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 last> --- V81 (Interval 49) STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 last> --- V82 (Interval 50) STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 last> --- V83 (Interval 51) STORE_LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR BB32 regmask=[allInt] minReg=1 last> --- V84 (Interval 52) STORE_LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR BB32 regmask=[rcx] minReg=1 last fixed> --- V85 (Interval 53) STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1 last> --- V86 --- V87 (Interval 54) STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1 last> --- V88 (Interval 55) STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[rcx] minReg=1 last fixed> --- V89 (Interval 56) STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1 last> --- V90 (Interval 57) STORE_LCL_VAR BB40 regmask=[allInt] minReg=1> LCL_VAR BB40 regmask=[allInt] minReg=1> LCL_VAR BB40 regmask=[allInt] minReg=1 last> Allocating Registers -------------------- The following table has one or more rows for each RefPosition that is handled during allocation. The first column provides the basic information about the RefPosition, with its type (e.g. Def, Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the action taken during allocation (e.g. Alloc a new register, or Keep an existing one). The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is active, a 'p' if it is a large vector that has been partially spilled, and 'i'if it is inactive. Columns are only printed up to the last modifed register, which may increase during allocation, in which case additional columns will appear. Registers which are not marked modified have ---- in their column. ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+ | |V0 a|V1 a| | | | |V2 a| | 0.#0 V1 Parm Alloc rsi | |V0 a| | | |V1 a| |V2 a| | 0.#1 V0 Parm Keep rcx | |V0 a| | | |V1 a| |V2 a| | 0.#2 V2 Parm Alloc rdi | |V0 a| | | |V1 a|V2 a| | | 1.#3 BB1 PredBB0 | |V0 a| | | |V1 a|V2 a| | | 5.#4 V0 Use Keep rcx | |V0 a| | | |V1 a|V2 a| | | 6.#5 I58 Def Alloc rbx | |V0 a| |I58 a| |V1 a|V2 a| | | 7.#6 I58 Use * Keep rbx | |V0 a| |I58 a| |V1 a|V2 a| | | 8.#7 V52 Def Alloc rbx | |V0 a| |V52 a| |V1 a|V2 a| | | 13.#8 V0 Use * Keep rcx | |V0 a| |V52 a| |V1 a|V2 a| | | 14.#9 I59 Def Alloc rbp | | | |V52 a|I59 a|V1 a|V2 a| | | 15.#10 I59 Use * Keep rbp | | | |V52 a|I59 a|V1 a|V2 a| | | 16.#11 V53 Def Alloc rbp | | | |V52 a|V53 a|V1 a|V2 a| | | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 17.#12 BB2 PredBB1 | | | |V52 a|V53 a|V1 a|V2 a| | | 29.#13 V52 Use Keep rbx | | | |V52 a|V53 a|V1 a|V2 a| | | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 33.#14 BB3 PredBB2 | | | |V52 i|V53 i|V1 a|V2 a| | | 39.#15 rcx Fixd Keep rcx | | | |V52 i|V53 i|V1 a|V2 a| | | 39.#16 V1 Use Copy rcx | |V1 a| |V52 i|V53 i|V1 a|V2 a| | | 40.#17 rcx Fixd Keep rcx | |V1 a| |V52 i|V53 i|V1 a|V2 a| | | 40.#18 I60 Def Alloc rcx | |I60 a| |V52 i|V53 i|V1 a|V2 a| | | 45.#19 V1 Use * Keep rsi | |I60 a| |V52 i|V53 i|V1 i|V2 a| | | 46.#20 I61 Def Alloc rax |I61 a|I60 a| |V52 i|V53 i|V1 i|V2 a| | | 49.#21 I61 Use * Keep rax |I61 a|I60 a| |V52 i|V53 i|V1 i|V2 a| | | 50.#22 I62 Def Alloc rax |I62 a|I60 a| |V52 i|V53 i|V1 i|V2 a| | | 55.#23 rcx Fixd Keep rcx |I62 a|I60 a| |V52 i|V53 i|V1 i|V2 a| | | 55.#24 I60 Use * Keep rcx |I62 a|I60 a| |V52 i|V53 i|V1 i|V2 a| | | 55.#25 I62 Use * Keep rax |I62 a|I60 a| |V52 i|V53 i|V1 i|V2 a| | | 56.#26 rax Kill Keep rax | | | |V52 i|V53 i|V1 i|V2 a| | | 56.#27 rcx Kill Keep rcx | | | |V52 i|V53 i|V1 i|V2 a| | | 56.#28 rdx Kill Keep rdx | | | |V52 i|V53 i|V1 i|V2 a| | | 56.#29 r8 Kill Keep r8 | | | |V52 i|V53 i|V1 i|V2 a| | | 56.#30 r9 Kill Keep r9 | | | |V52 i|V53 i|V1 i|V2 a| | | 56.#31 r10 Kill Keep r10 | | | |V52 i|V53 i|V1 i|V2 a| | | 56.#32 r11 Kill Keep r11 | | | |V52 i|V53 i|V1 i|V2 a| | | 56.#33 rax Fixd Keep rax | | | |V52 i|V53 i|V1 i|V2 a| | | 56.#34 I63 Def Alloc rax |I63 a| | |V52 i|V53 i|V1 i|V2 a| | | 59.#35 V2 Use * Keep rdi |I63 a| | |V52 i|V53 i|V1 i|V2 i| | | 59.#36 I63 Use * Keep rax |I63 a| | |V52 i|V53 i|V1 i|V2 i| | | 62.#37 C64 Def Alloc rax |C64 a| | |V52 i|V53 i|V1 i|V2 i| | | 63.#38 rax Fixd Keep rax |C64 a| | |V52 i|V53 i|V1 i|V2 i| | | 63.#39 C64 Use * Keep rax |C64 a| | |V52 i|V53 i|V1 i|V2 i| | | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 65.#40 BB4 PredBB2 | | | |V52 a|V53 a|V1 a|V2 a| | | 69.#41 rcx Fixd Keep rcx | | | |V52 a|V53 a|V1 a|V2 a| | | 69.#42 V1 Use Copy rcx | |V1 a| |V52 a|V53 a|V1 a|V2 a| | | 70.#43 rcx Fixd Keep rcx | |V1 a| |V52 a|V53 a|V1 a|V2 a| | | 70.#44 I65 Def Alloc rcx | |I65 a| |V52 a|V53 a|V1 a|V2 a| | | 75.#45 V1 Use Keep rsi | |I65 a| |V52 a|V53 a|V1 a|V2 a| | | 76.#46 I66 Def Alloc rax |I66 a|I65 a| |V52 a|V53 a|V1 a|V2 a| | | 79.#47 I66 Use * Keep rax |I66 a|I65 a| |V52 a|V53 a|V1 a|V2 a| | | 80.#48 I67 Def Alloc rax |I67 a|I65 a| |V52 a|V53 a|V1 a|V2 a| | | 85.#49 rcx Fixd Keep rcx |I67 a|I65 a| |V52 a|V53 a|V1 a|V2 a| | | 85.#50 I65 Use * Keep rcx |I67 a|I65 a| |V52 a|V53 a|V1 a|V2 a| | | 85.#51 I67 Use * Keep rax |I67 a|I65 a| |V52 a|V53 a|V1 a|V2 a| | | 86.#52 rax Kill Keep rax | | | |V52 a|V53 a|V1 a|V2 a| | | 86.#53 rcx Kill Keep rcx | | | |V52 a|V53 a|V1 a|V2 a| | | 86.#54 rdx Kill Keep rdx | | | |V52 a|V53 a|V1 a|V2 a| | | 86.#55 r8 Kill Keep r8 | | | |V52 a|V53 a|V1 a|V2 a| | | 86.#56 r9 Kill Keep r9 | | | |V52 a|V53 a|V1 a|V2 a| | | 86.#57 r10 Kill Keep r10 | | | |V52 a|V53 a|V1 a|V2 a| | | 86.#58 r11 Kill Keep r11 | | | |V52 a|V53 a|V1 a|V2 a| | | 86.#59 rax Fixd Keep rax | | | |V52 a|V53 a|V1 a|V2 a| | | 86.#60 I68 Def Alloc rax |I68 a| | |V52 a|V53 a|V1 a|V2 a| | | 89.#61 I68 Use * Keep rax |I68 a| | |V52 a|V53 a|V1 a|V2 a| | | 90.#62 I69 Def Alloc rax |I69 a| | |V52 a|V53 a|V1 a|V2 a| | | 91.#63 I69 Use * Keep rax |I69 a| | |V52 a|V53 a|V1 a|V2 a| | | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 92.#64 I70 Def Alloc r14 | | | |V52 a|V53 a|V1 a|V2 a| | |I70 a| 95.#65 I70 Use * Keep r14 | | | |V52 a|V53 a|V1 a|V2 a| | |I70 a| 96.#66 I71 Def Alloc r14 | | | |V52 a|V53 a|V1 a|V2 a| | |I71 a| 97.#67 I71 Use * Keep r14 | | | |V52 a|V53 a|V1 a|V2 a| | |I71 a| 98.#68 V3 Def Alloc r14 | | | |V52 a|V53 a|V1 a|V2 a| | |V3 a| 103.#69 V53 Use Keep rbp | | | |V52 a|V53 a|V1 a|V2 a| | |V3 a| 104.#70 V40 Def Alloc rcx | |V40 a| |V52 a|V53 a|V1 a|V2 a| | |V3 a| 111.#71 V40 Use * Keep rcx | |V40 a| |V52 a|V53 a|V1 a|V2 a| | |V3 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 115.#72 BB5 PredBB4 | | | |V52 a|V53 a|V1 a|V2 a| | |V3 a| 121.#73 V53 Use Keep rbp | | | |V52 a|V53 a|V1 a|V2 a| | |V3 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 122.#74 V39 Def Alloc r15 | | | |V52 a|V53 a|V1 a|V2 a| | |V3 a|V39 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 123.#75 BB6 PredBB4 | | | |V52 a|V53 a|V1 a|V2 a| | |V3 a|V39 i| 128.#76 C72 Def Alloc r15 | | | |V52 a|V53 a|V1 a|V2 a| | |V3 a|C72 a| 129.#77 C72 Use * Keep r15 | | | |V52 a|V53 a|V1 a|V2 a| | |V3 a|C72 a| 130.#78 V39 Def Alloc r15 | | | |V52 a|V53 a|V1 a|V2 a| | |V3 a|V39 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 131.#79 BB7 PredBB5 | | | |V52 a|V53 a|V1 a|V2 a| | |V3 a|V39 a| 135.#80 V39 Use * Keep r15 | | | |V52 a|V53 a|V1 a|V2 a| | |V3 a|V39 a| 136.#81 V31 Def Alloc r15 | | | |V52 a|V53 a|V1 a|V2 a| | |V3 a|V31 a| 141.#82 V52 Use Keep rbx | | | |V52 a|V53 a|V1 a|V2 a| | |V3 a|V31 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 142.#83 I73 Def Alloc r12 | | | |V52 a|V53 a|V1 a|V2 a| | |I73 a|V3 a|V31 a| 143.#84 I73 Use * Keep r12 | | | |V52 a|V53 a|V1 a|V2 a| | |I73 a|V3 a|V31 a| 144.#85 V42 Def Alloc r12 | | | |V52 a|V53 a|V1 a|V2 a| | |V42 a|V3 a|V31 a| 149.#86 V31 Use Keep r15 | | | |V52 a|V53 a|V1 a|V2 a| | |V42 a|V3 a|V31 a| 149.#87 V42 Use Keep r12 | | | |V52 a|V53 a|V1 a|V2 a| | |V42 a|V3 a|V31 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 153.#88 BB8 PredBB7 | | | |V52 a|V53 a|V1 a|V2 a| | |V42 a|V3 a|V31 a| 157.#89 V42 Use * Keep r12 | | | |V52 a|V53 a|V1 a|V2 a| | |V42 a|V3 a|V31 a| 158.#90 V41 Def Alloc r12 | | | |V52 a|V53 a|V1 a|V2 a| | |V41 a|V3 a|V31 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 159.#91 BB9 PredBB7 | | | |V52 a|V53 a|V1 a|V2 a| | |V41 i|V3 a|V31 a| 163.#92 V31 Use Keep r15 | | | |V52 a|V53 a|V1 a|V2 a| | |V41 i|V3 a|V31 a| 164.#93 V41 Def Keep r12 | | | |V52 a|V53 a|V1 a|V2 a| | |V41 a|V3 a|V31 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 165.#94 BB10 PredBB8 | | | |V52 a|V53 a|V1 a|V2 a| | |V41 a|V3 a|V31 a| 171.#95 V31 Use * Keep r15 | | | |V52 a|V53 a|V1 a|V2 a| | |V41 a|V3 a|V31 a| 171.#96 V41 Use Keep r12 | | | |V52 a|V53 a|V1 a|V2 a| | |V41 a|V3 a|V31 a| 172.#97 I74 Def Alloc r15 | | | |V52 a|V53 a|V1 a|V2 a| | |V41 a|V3 a|I74 a| 173.#98 I74 Use * Keep r15 | | | |V52 a|V53 a|V1 a|V2 a| | |V41 a|V3 a|I74 a| 174.#99 V5 Def Alloc r15 | | | |V52 a|V53 a|V1 a|V2 a| | |V41 a|V3 a|V5 a| 179.#100 V41 Use * Keep r12 | | | |V52 a|V53 a|V1 a|V2 a| | |V41 a|V3 a|V5 a| 180.#101 V8 Def Alloc r12 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V3 a|V5 a| 185.#102 V52 Use Keep rbx | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 186.#103 I75 Def Alloc r13 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|I75 a|V3 a|V5 a| 187.#104 I75 Use * Keep r13 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|I75 a|V3 a|V5 a| 188.#105 V9 Def Alloc r13 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 195.#106 V9 Use Keep r13 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 195.#107 V8 Use Keep r12 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 196.#108 I76 Def Alloc rax |I76 a| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 197.#109 I76 Use * Keep rax |I76 a| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 198.#110 V10 Def Alloc rax |V10 a| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 200.#111 I77 Def Alloc rcx |V10 a|I77 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 201.#112 I77 Use * Keep rcx |V10 a|I77 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 202.#113 V75 Def Alloc rcx |V10 a|V75 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 204.#114 I78 Def Alloc rdx |V10 a|V75 a|I78 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 205.#115 I78 Use * Keep rdx |V10 a|V75 a|I78 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 206.#116 V74 Def Alloc rdx |V10 a|V75 a|V74 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 211.#117 V74 Use Keep rdx |V10 a|V75 a|V74 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 211.#118 V52 Use Keep rbx |V10 a|V75 a|V74 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 219.#119 V74 Use * Keep rdx |V10 a|V75 a|V74 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 219.#120 V53 Use Keep rbp |V10 a|V75 a|V74 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 223.#121 rcx Fixd Keep rcx |V10 a|V75 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 223.#122 V75 Use * Keep rcx |V10 a|V75 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 224.#123 rcx Fixd Keep rcx |V10 a| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 224.#124 I79 Def Alloc rcx |V10 a|I79 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 226.#125 I80 Def Alloc rdx |V10 a|I79 a|I80 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 227.#126 rdx Fixd Keep rdx |V10 a|I79 a|I80 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 227.#127 I80 Use * Keep rdx |V10 a|I79 a|I80 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 228.#128 rdx Fixd Keep rdx |V10 a|I79 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 228.#129 I81 Def Alloc rdx |V10 a|I79 a|I81 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 231.#130 r9 Fixd Keep r9 |V10 a|I79 a|I81 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 231.#131 V8 Use Copy r9 |V10 a|I79 a|I81 a|V52 a|V53 a|V1 a|V2 a| |V8 a|V8 a|V9 a|V3 a|V5 a| 232.#132 r9 Fixd Keep r9 |V10 a|I79 a|I81 a|V52 a|V53 a|V1 a|V2 a| |V8 a|V8 a|V9 a|V3 a|V5 a| 232.#133 I82 Def Alloc r9 |V10 a|I79 a|I81 a|V52 a|V53 a|V1 a|V2 a| |I82 a|V8 a|V9 a|V3 a|V5 a| 234.#134 C83 Def Alloc r8 |V10 a|I79 a|I81 a|V52 a|V53 a|V1 a|V2 a|C83 a|I82 a|V8 a|V9 a|V3 a|V5 a| 235.#135 r8 Fixd Keep r8 |V10 a|I79 a|I81 a|V52 a|V53 a|V1 a|V2 a|C83 a|I82 a|V8 a|V9 a|V3 a|V5 a| 235.#136 C83 Use * Keep r8 |V10 a|I79 a|I81 a|V52 a|V53 a|V1 a|V2 a|C83 a|I82 a|V8 a|V9 a|V3 a|V5 a| 236.#137 r8 Fixd Keep r8 |V10 a|I79 a|I81 a|V52 a|V53 a|V1 a|V2 a| |I82 a|V8 a|V9 a|V3 a|V5 a| 236.#138 I84 Def Alloc r8 |V10 a|I79 a|I81 a|V52 a|V53 a|V1 a|V2 a|I84 a|I82 a|V8 a|V9 a|V3 a|V5 a| 237.#139 rcx Fixd Keep rcx |V10 a|I79 a|I81 a|V52 a|V53 a|V1 a|V2 a|I84 a|I82 a|V8 a|V9 a|V3 a|V5 a| 237.#140 I79 Use * Keep rcx |V10 a|I79 a|I81 a|V52 a|V53 a|V1 a|V2 a|I84 a|I82 a|V8 a|V9 a|V3 a|V5 a| 237.#141 rdx Fixd Keep rdx |V10 a|I79 a|I81 a|V52 a|V53 a|V1 a|V2 a|I84 a|I82 a|V8 a|V9 a|V3 a|V5 a| 237.#142 I81 Use * Keep rdx |V10 a|I79 a|I81 a|V52 a|V53 a|V1 a|V2 a|I84 a|I82 a|V8 a|V9 a|V3 a|V5 a| 237.#143 r9 Fixd Keep r9 |V10 a|I79 a|I81 a|V52 a|V53 a|V1 a|V2 a|I84 a|I82 a|V8 a|V9 a|V3 a|V5 a| 237.#144 I82 Use * Keep r9 |V10 a|I79 a|I81 a|V52 a|V53 a|V1 a|V2 a|I84 a|I82 a|V8 a|V9 a|V3 a|V5 a| 237.#145 r8 Fixd Keep r8 |V10 a|I79 a|I81 a|V52 a|V53 a|V1 a|V2 a|I84 a|I82 a|V8 a|V9 a|V3 a|V5 a| 237.#146 I84 Use * Keep r8 |V10 a|I79 a|I81 a|V52 a|V53 a|V1 a|V2 a|I84 a|I82 a|V8 a|V9 a|V3 a|V5 a| 238.#147 rax Kill Spill rax | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| Keep rax | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 238.#148 rcx Kill Keep rcx | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 238.#149 rdx Kill Keep rdx | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 238.#150 r8 Kill Keep r8 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 238.#151 r9 Kill Keep r9 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 238.#152 r10 Kill Keep r10 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 238.#153 r11 Kill Keep r11 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 245.#154 V5 Use Keep r15 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 249.#155 BB11 PredBB10 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 253.#156 rcx Fixd Keep rcx | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 253.#157 V1 Use Copy rcx | |V1 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 254.#158 rcx Fixd Keep rcx | |V1 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 254.#159 I85 Def Alloc rcx | |I85 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 255.#160 rcx Fixd Keep rcx | |I85 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 255.#161 I85 Use * Keep rcx | |I85 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 256.#162 rax Kill Keep rax | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 256.#163 rcx Kill Keep rcx | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 256.#164 rdx Kill Keep rdx | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 256.#165 r8 Kill Keep r8 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 256.#166 r9 Kill Keep r9 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 256.#167 r10 Kill Keep r10 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 256.#168 r11 Kill Keep r11 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 256.#169 rax Fixd Keep rax | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 256.#170 I86 Def Alloc rax |I86 a| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 257.#171 I86 Use * Keep rax |I86 a| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 258.#172 I87 Def Alloc rcx | |I87 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 261.#173 V5 Use Keep r15 | |I87 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 262.#174 I88 Def Alloc rax |I88 a|I87 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 263.#175 I87 Use * Keep rcx |I88 a|I87 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 263.#176 I88 Use * Keep rax |I88 a|I87 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 267.#177 BB12 PredBB11 | | | |V52 i|V53 i|V1 a|V2 a| | |V8 i|V9 i|V3 i|V5 i| 273.#178 rcx Fixd Keep rcx | | | |V52 i|V53 i|V1 a|V2 a| | |V8 i|V9 i|V3 i|V5 i| 273.#179 V1 Use Copy rcx | |V1 a| |V52 i|V53 i|V1 a|V2 a| | |V8 i|V9 i|V3 i|V5 i| 274.#180 rcx Fixd Keep rcx | |V1 a| |V52 i|V53 i|V1 a|V2 a| | |V8 i|V9 i|V3 i|V5 i| 274.#181 I89 Def Alloc rcx | |I89 a| |V52 i|V53 i|V1 a|V2 a| | |V8 i|V9 i|V3 i|V5 i| 279.#182 V1 Use * Keep rsi | |I89 a| |V52 i|V53 i|V1 i|V2 a| | |V8 i|V9 i|V3 i|V5 i| 280.#183 I90 Def Alloc rax |I90 a|I89 a| |V52 i|V53 i|V1 i|V2 a| | |V8 i|V9 i|V3 i|V5 i| 283.#184 I90 Use * Keep rax |I90 a|I89 a| |V52 i|V53 i|V1 i|V2 a| | |V8 i|V9 i|V3 i|V5 i| 284.#185 I91 Def Alloc rax |I91 a|I89 a| |V52 i|V53 i|V1 i|V2 a| | |V8 i|V9 i|V3 i|V5 i| 289.#186 rcx Fixd Keep rcx |I91 a|I89 a| |V52 i|V53 i|V1 i|V2 a| | |V8 i|V9 i|V3 i|V5 i| 289.#187 I89 Use * Keep rcx |I91 a|I89 a| |V52 i|V53 i|V1 i|V2 a| | |V8 i|V9 i|V3 i|V5 i| 289.#188 I91 Use * Keep rax |I91 a|I89 a| |V52 i|V53 i|V1 i|V2 a| | |V8 i|V9 i|V3 i|V5 i| 290.#189 rax Kill Keep rax | | | |V52 i|V53 i|V1 i|V2 a| | |V8 i|V9 i|V3 i|V5 i| 290.#190 rcx Kill Keep rcx | | | |V52 i|V53 i|V1 i|V2 a| | |V8 i|V9 i|V3 i|V5 i| 290.#191 rdx Kill Keep rdx | | | |V52 i|V53 i|V1 i|V2 a| | |V8 i|V9 i|V3 i|V5 i| 290.#192 r8 Kill Keep r8 | | | |V52 i|V53 i|V1 i|V2 a| | |V8 i|V9 i|V3 i|V5 i| 290.#193 r9 Kill Keep r9 | | | |V52 i|V53 i|V1 i|V2 a| | |V8 i|V9 i|V3 i|V5 i| 290.#194 r10 Kill Keep r10 | | | |V52 i|V53 i|V1 i|V2 a| | |V8 i|V9 i|V3 i|V5 i| 290.#195 r11 Kill Keep r11 | | | |V52 i|V53 i|V1 i|V2 a| | |V8 i|V9 i|V3 i|V5 i| 290.#196 rax Fixd Keep rax | | | |V52 i|V53 i|V1 i|V2 a| | |V8 i|V9 i|V3 i|V5 i| 290.#197 I92 Def Alloc rax |I92 a| | |V52 i|V53 i|V1 i|V2 a| | |V8 i|V9 i|V3 i|V5 i| 293.#198 V2 Use * Keep rdi |I92 a| | |V52 i|V53 i|V1 i|V2 i| | |V8 i|V9 i|V3 i|V5 i| 293.#199 I92 Use * Keep rax |I92 a| | |V52 i|V53 i|V1 i|V2 i| | |V8 i|V9 i|V3 i|V5 i| 296.#200 C93 Def Alloc rax |C93 a| | |V52 i|V53 i|V1 i|V2 i| | |V8 i|V9 i|V3 i|V5 i| 297.#201 rax Fixd Keep rax |C93 a| | |V52 i|V53 i|V1 i|V2 i| | |V8 i|V9 i|V3 i|V5 i| 297.#202 C93 Use * Keep rax |C93 a| | |V52 i|V53 i|V1 i|V2 i| | |V8 i|V9 i|V3 i|V5 i| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 299.#203 BB13 PredBB11 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 304.#204 I94 Def Alloc rcx | |I94 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 305.#205 rcx Fixd Keep rcx | |I94 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 305.#206 I94 Use * Keep rcx | |I94 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 306.#207 rcx Fixd Keep rcx | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 306.#208 I95 Def Alloc rcx | |I95 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 309.#209 rdx Fixd Keep rdx | |I95 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 309.#210 V5 Use * Copy rdx | |I95 a|V5 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 310.#211 rdx Fixd Keep rdx | |I95 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 310.#212 I96 Def Alloc rdx | |I95 a|I96 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 311.#213 rcx Fixd Keep rcx | |I95 a|I96 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 311.#214 I95 Use * Keep rcx | |I95 a|I96 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 311.#215 rdx Fixd Keep rdx | |I95 a|I96 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 311.#216 I96 Use * Keep rdx | |I95 a|I96 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 312.#217 rax Kill Keep rax | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 312.#218 rcx Kill Keep rcx | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 312.#219 rdx Kill Keep rdx | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 312.#220 r8 Kill Keep r8 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 312.#221 r9 Kill Keep r9 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 312.#222 r10 Kill Keep r10 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 312.#223 r11 Kill Keep r11 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 313.#224 BB14 PredBB10 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 316.#225 I97 Def Alloc rcx | |I97 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 317.#226 I97 Use * Keep rcx | |I97 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 318.#227 V77 Def Alloc rcx | |V77 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 322.#228 I98 Def Alloc rdx | |V77 a|I98 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 323.#229 V77 Use Keep rcx | |V77 a|I98 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 323.#230 I98 Use * Keep rdx | |V77 a|I98 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 330.#231 I99 Def Alloc rdx | |V77 a|I99 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 331.#232 V77 Use * Keep rcx | |V77 a|I99 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 331.#233 I99 Use * Keep rdx | |V77 a|I99 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 334.#234 I100 Def Alloc rcx | |I100a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 335.#235 rcx Fixd Keep rcx | |I100a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 335.#236 I100 Use * Keep rcx | |I100a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 336.#237 rcx Fixd Keep rcx | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 336.#238 I101 Def Alloc rcx | |I101a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 338.#239 I102 Def Alloc rdx | |I101a|I102a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 339.#240 rdx Fixd Keep rdx | |I101a|I102a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 339.#241 I102 Use * Keep rdx | |I101a|I102a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 340.#242 rdx Fixd Keep rdx | |I101a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 340.#243 I103 Def Alloc rdx | |I101a|I103a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 341.#244 rcx Fixd Keep rcx | |I101a|I103a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 341.#245 I101 Use * Keep rcx | |I101a|I103a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 341.#246 rdx Fixd Keep rdx | |I101a|I103a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 341.#247 I103 Use * Keep rdx | |I101a|I103a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 342.#248 rax Kill Keep rax | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 342.#249 rcx Kill Keep rcx | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 342.#250 rdx Kill Keep rdx | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 342.#251 r8 Kill Keep r8 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 342.#252 r9 Kill Keep r9 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 342.#253 r10 Kill Keep r10 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 342.#254 r11 Kill Keep r11 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 342.#255 rax Fixd Keep rax | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 342.#256 I104 Def Alloc rax |I104a| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 343.#257 I104 Use * Keep rax |I104a| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 344.#258 V13 Def Alloc r15 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 351.#259 V13 Use Keep r15 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 351.#260 V3 Use Keep r14 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 355.#261 BB15 PredBB14 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 363.#262 V10 Use ReLod NA | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| Alloc rax |V10 a| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 367.#263 BB16 PredBB14 |V10 a| | |V52 i|V53 i|V1 a|V2 a| | |V8 i|V9 i|V3 i|V13 a| 373.#264 V2 Use * Keep rdi |V10 a| | |V52 i|V53 i|V1 a|V2 i| | |V8 i|V9 i|V3 i|V13 a| 379.#265 V10 Use * Keep rax |V10 i| | |V52 i|V53 i|V1 a|V2 i| | |V8 i|V9 i|V3 i|V13 a| 380.#266 I105 Def Alloc r8 |V10 i| | |V52 i|V53 i|V1 a|V2 i|I105a| |V8 i|V9 i|V3 i|V13 a| 381.#267 r8 Fixd Keep r8 |V10 i| | |V52 i|V53 i|V1 a|V2 i|I105a| |V8 i|V9 i|V3 i|V13 a| 381.#268 I105 Use * Keep r8 |V10 i| | |V52 i|V53 i|V1 a|V2 i|I105a| |V8 i|V9 i|V3 i|V13 a| 382.#269 r8 Fixd Keep r8 |V10 i| | |V52 i|V53 i|V1 a|V2 i| | |V8 i|V9 i|V3 i|V13 a| 382.#270 I106 Def Alloc r8 |V10 i| | |V52 i|V53 i|V1 a|V2 i|I106a| |V8 i|V9 i|V3 i|V13 a| 384.#271 I107 Def Alloc rcx |V10 i|I107a| |V52 i|V53 i|V1 a|V2 i|I106a| |V8 i|V9 i|V3 i|V13 a| 385.#272 rcx Fixd Keep rcx |V10 i|I107a| |V52 i|V53 i|V1 a|V2 i|I106a| |V8 i|V9 i|V3 i|V13 a| 385.#273 I107 Use * Keep rcx |V10 i|I107a| |V52 i|V53 i|V1 a|V2 i|I106a| |V8 i|V9 i|V3 i|V13 a| 386.#274 rcx Fixd Keep rcx |V10 i| | |V52 i|V53 i|V1 a|V2 i|I106a| |V8 i|V9 i|V3 i|V13 a| 386.#275 I108 Def Alloc rcx |V10 i|I108a| |V52 i|V53 i|V1 a|V2 i|I106a| |V8 i|V9 i|V3 i|V13 a| 389.#276 rdx Fixd Keep rdx |V10 i|I108a| |V52 i|V53 i|V1 a|V2 i|I106a| |V8 i|V9 i|V3 i|V13 a| 389.#277 V13 Use * Copy rdx |V10 i|I108a|V13 a|V52 i|V53 i|V1 a|V2 i|I106a| |V8 i|V9 i|V3 i|V13 a| 390.#278 rdx Fixd Keep rdx |V10 i|I108a|V13 i|V52 i|V53 i|V1 a|V2 i|I106a| |V8 i|V9 i|V3 i|V13 i| 390.#279 I109 Def Alloc rdx |V10 i|I108a|I109a|V52 i|V53 i|V1 a|V2 i|I106a| |V8 i|V9 i|V3 i|V13 i| 393.#280 r9 Fixd Keep r9 |V10 i|I108a|I109a|V52 i|V53 i|V1 a|V2 i|I106a| |V8 i|V9 i|V3 i|V13 i| 393.#281 V1 Use * Copy r9 |V10 i|I108a|I109a|V52 i|V53 i|V1 a|V2 i|I106a|V1 a|V8 i|V9 i|V3 i|V13 i| 394.#282 r9 Fixd Keep r9 |V10 i|I108a|I109a|V52 i|V53 i|V1 i|V2 i|I106a|V1 i|V8 i|V9 i|V3 i|V13 i| 394.#283 I110 Def Alloc r9 |V10 i|I108a|I109a|V52 i|V53 i|V1 i|V2 i|I106a|I110a|V8 i|V9 i|V3 i|V13 i| 395.#284 r8 Fixd Keep r8 |V10 i|I108a|I109a|V52 i|V53 i|V1 i|V2 i|I106a|I110a|V8 i|V9 i|V3 i|V13 i| 395.#285 I106 Use * Keep r8 |V10 i|I108a|I109a|V52 i|V53 i|V1 i|V2 i|I106a|I110a|V8 i|V9 i|V3 i|V13 i| 395.#286 rcx Fixd Keep rcx |V10 i|I108a|I109a|V52 i|V53 i|V1 i|V2 i|I106a|I110a|V8 i|V9 i|V3 i|V13 i| 395.#287 I108 Use * Keep rcx |V10 i|I108a|I109a|V52 i|V53 i|V1 i|V2 i|I106a|I110a|V8 i|V9 i|V3 i|V13 i| 395.#288 rdx Fixd Keep rdx |V10 i|I108a|I109a|V52 i|V53 i|V1 i|V2 i|I106a|I110a|V8 i|V9 i|V3 i|V13 i| 395.#289 I109 Use * Keep rdx |V10 i|I108a|I109a|V52 i|V53 i|V1 i|V2 i|I106a|I110a|V8 i|V9 i|V3 i|V13 i| 395.#290 r9 Fixd Keep r9 |V10 i|I108a|I109a|V52 i|V53 i|V1 i|V2 i|I106a|I110a|V8 i|V9 i|V3 i|V13 i| 395.#291 I110 Use * Keep r9 |V10 i|I108a|I109a|V52 i|V53 i|V1 i|V2 i|I106a|I110a|V8 i|V9 i|V3 i|V13 i| 396.#292 rax Kill Keep rax | | | |V52 i|V53 i|V1 i|V2 i| | |V8 i|V9 i|V3 i|V13 i| 396.#293 rcx Kill Keep rcx | | | |V52 i|V53 i|V1 i|V2 i| | |V8 i|V9 i|V3 i|V13 i| 396.#294 rdx Kill Keep rdx | | | |V52 i|V53 i|V1 i|V2 i| | |V8 i|V9 i|V3 i|V13 i| 396.#295 r8 Kill Keep r8 | | | |V52 i|V53 i|V1 i|V2 i| | |V8 i|V9 i|V3 i|V13 i| 396.#296 r9 Kill Keep r9 | | | |V52 i|V53 i|V1 i|V2 i| | |V8 i|V9 i|V3 i|V13 i| 396.#297 r10 Kill Keep r10 | | | |V52 i|V53 i|V1 i|V2 i| | |V8 i|V9 i|V3 i|V13 i| 396.#298 r11 Kill Keep r11 | | | |V52 i|V53 i|V1 i|V2 i| | |V8 i|V9 i|V3 i|V13 i| 396.#299 rax Fixd Keep rax | | | |V52 i|V53 i|V1 i|V2 i| | |V8 i|V9 i|V3 i|V13 i| 396.#300 I111 Def Alloc rax |I111a| | |V52 i|V53 i|V1 i|V2 i| | |V8 i|V9 i|V3 i|V13 i| 397.#301 I111 Use * Keep rax |I111a| | |V52 i|V53 i|V1 i|V2 i| | |V8 i|V9 i|V3 i|V13 i| 398.#302 V51 Def Alloc rax |V51 a| | |V52 i|V53 i|V1 i|V2 i| | |V8 i|V9 i|V3 i|V13 i| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 399.#303 BB17 PredBB14 |V51 i| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 407.#304 V53 Use Keep rbp |V51 i| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 411.#305 BB18 PredBB17 |V51 i| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 417.#306 V10 Use * ReLod NA |V51 i| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| Alloc rax |V10 i| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 418.#307 V32 Def Alloc rdx |V10 i| |V32 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 419.#308 BB19 PredBB17 |V10 a| |V32 i|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 427.#309 V10 Use * Keep rax |V10 a| |V32 i|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 427.#310 V53 Use Keep rbp |V10 a| |V32 i|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| Restr rax |V51 i| |V32 i|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 428.#311 I112 Def Alloc rdx |V51 i| |I112a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 429.#312 I112 Use * Keep rdx |V51 i| |I112a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| Restr rdx |V51 i| |V32 i|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 430.#313 V32 Def Alloc rdx |V51 i| |V32 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 431.#314 BB20 PredBB18 |V51 i| |V32 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 435.#315 V32 Use * Keep rdx |V51 i| |V32 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 436.#316 V14 Def Alloc rax |V14 a| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 443.#317 V13 Use Keep r15 |V14 a| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 447.#318 BB21 PredBB20 |V14 a| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 453.#319 V52 Use Keep rbx |V14 a| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 454.#320 I113 Def Alloc rcx |V14 a|I113a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 455.#321 I113 Use * Keep rcx |V14 a|I113a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 456.#322 I114 Def Alloc rcx |V14 a|I114a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 459.#323 V14 Use Keep rax |V14 a|I114a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 460.#324 I115 Def Alloc rdx |V14 a|I114a|I115a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 461.#325 I115 Use * Keep rdx |V14 a|I114a|I115a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 461.#326 I114 Use *D Keep rcx |V14 a|I114a|I115a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 462.#327 I116 Def Alloc rdx |V14 a|I114a|I116a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 463.#328 I116 Use * Keep rdx |V14 a| |I116a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 464.#329 V38 Def Alloc rdx |V14 a| |V38 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 467.#330 rcx Fixd Keep rcx |V14 a| |V38 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 467.#331 V1 Use Copy rcx |V14 a|V1 a|V38 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 468.#332 rcx Fixd Keep rcx |V14 a|V1 a|V38 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 468.#333 I117 Def Alloc rcx |V14 a|I117a|V38 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 469.#334 rcx Fixd Keep rcx |V14 a|I117a|V38 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 469.#335 I117 Use * Keep rcx |V14 a|I117a|V38 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 470.#336 rax Kill Spill rax | | |V38 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| Keep rax | | |V38 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 470.#337 rcx Kill Keep rcx | | |V38 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 470.#338 rdx Kill Spill rdx | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| Keep rdx | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 470.#339 r8 Kill Keep r8 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 470.#340 r9 Kill Keep r9 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 470.#341 r10 Kill Keep r10 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 470.#342 r11 Kill Keep r11 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 470.#343 rax Fixd Keep rax | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 470.#344 I118 Def Alloc rax |I118a| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 471.#345 I118 Use * Keep rax |I118a| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| Restr rax |V51 i| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 472.#346 I119 Def Alloc rcx |V51 i|I119a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 475.#347 I119 Use * Keep rcx |V51 i|I119a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 475.#348 V38 Use * ReLod NA |V51 i|I119a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| NoReg |V51 i|I119a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 479.#349 BB22 PredBB21 |V51 i| | |V52 i|V53 i|V1 a|V2 a| | |V8 i|V9 i|V3 i|V13 i| 485.#350 rcx Fixd Keep rcx |V51 i| | |V52 i|V53 i|V1 a|V2 a| | |V8 i|V9 i|V3 i|V13 i| 485.#351 V1 Use Copy rcx |V51 i|V1 a| |V52 i|V53 i|V1 a|V2 a| | |V8 i|V9 i|V3 i|V13 i| 486.#352 rcx Fixd Keep rcx |V51 i|V1 a| |V52 i|V53 i|V1 a|V2 a| | |V8 i|V9 i|V3 i|V13 i| 486.#353 I120 Def Alloc rcx |V51 i|I120a| |V52 i|V53 i|V1 a|V2 a| | |V8 i|V9 i|V3 i|V13 i| 491.#354 V1 Use * Keep rsi |V51 i|I120a| |V52 i|V53 i|V1 i|V2 a| | |V8 i|V9 i|V3 i|V13 i| 492.#355 I121 Def Alloc rax |I121a|I120a| |V52 i|V53 i|V1 i|V2 a| | |V8 i|V9 i|V3 i|V13 i| 495.#356 I121 Use * Keep rax |I121a|I120a| |V52 i|V53 i|V1 i|V2 a| | |V8 i|V9 i|V3 i|V13 i| Restr rax |V51 i|I120a| |V52 i|V53 i|V1 i|V2 a| | |V8 i|V9 i|V3 i|V13 i| 496.#357 I122 Def Alloc rax |I122a|I120a| |V52 i|V53 i|V1 i|V2 a| | |V8 i|V9 i|V3 i|V13 i| 501.#358 rcx Fixd Keep rcx |I122a|I120a| |V52 i|V53 i|V1 i|V2 a| | |V8 i|V9 i|V3 i|V13 i| 501.#359 I120 Use * Keep rcx |I122a|I120a| |V52 i|V53 i|V1 i|V2 a| | |V8 i|V9 i|V3 i|V13 i| 501.#360 I122 Use * Keep rax |I122a|I120a| |V52 i|V53 i|V1 i|V2 a| | |V8 i|V9 i|V3 i|V13 i| Restr rax |V51 i|I120a| |V52 i|V53 i|V1 i|V2 a| | |V8 i|V9 i|V3 i|V13 i| 502.#361 rax Kill Keep rax | | | |V52 i|V53 i|V1 i|V2 a| | |V8 i|V9 i|V3 i|V13 i| 502.#362 rcx Kill Keep rcx | | | |V52 i|V53 i|V1 i|V2 a| | |V8 i|V9 i|V3 i|V13 i| 502.#363 rdx Kill Keep rdx | | | |V52 i|V53 i|V1 i|V2 a| | |V8 i|V9 i|V3 i|V13 i| 502.#364 r8 Kill Keep r8 | | | |V52 i|V53 i|V1 i|V2 a| | |V8 i|V9 i|V3 i|V13 i| 502.#365 r9 Kill Keep r9 | | | |V52 i|V53 i|V1 i|V2 a| | |V8 i|V9 i|V3 i|V13 i| 502.#366 r10 Kill Keep r10 | | | |V52 i|V53 i|V1 i|V2 a| | |V8 i|V9 i|V3 i|V13 i| 502.#367 r11 Kill Keep r11 | | | |V52 i|V53 i|V1 i|V2 a| | |V8 i|V9 i|V3 i|V13 i| 502.#368 rax Fixd Keep rax | | | |V52 i|V53 i|V1 i|V2 a| | |V8 i|V9 i|V3 i|V13 i| 502.#369 I123 Def Alloc rax |I123a| | |V52 i|V53 i|V1 i|V2 a| | |V8 i|V9 i|V3 i|V13 i| 505.#370 V2 Use * Keep rdi |I123a| | |V52 i|V53 i|V1 i|V2 i| | |V8 i|V9 i|V3 i|V13 i| 505.#371 I123 Use * Keep rax |I123a| | |V52 i|V53 i|V1 i|V2 i| | |V8 i|V9 i|V3 i|V13 i| 508.#372 C124 Def Alloc rax |C124a| | |V52 i|V53 i|V1 i|V2 i| | |V8 i|V9 i|V3 i|V13 i| 509.#373 rax Fixd Keep rax |C124a| | |V52 i|V53 i|V1 i|V2 i| | |V8 i|V9 i|V3 i|V13 i| 509.#374 C124 Use * Keep rax |C124a| | |V52 i|V53 i|V1 i|V2 i| | |V8 i|V9 i|V3 i|V13 i| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 511.#375 BB23 PredBB20 |V14 a| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 514.#376 I125 Def Alloc rcx |V14 a|I125a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 515.#377 I125 Use * Keep rcx |V14 a|I125a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 516.#378 V79 Def Alloc rcx |V14 a|V79 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 518.#379 I126 Def Alloc rdx |V14 a|V79 a|I126a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 519.#380 I126 Use * Keep rdx |V14 a|V79 a|I126a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 520.#381 V78 Def Alloc rdx |V14 a|V79 a|V78 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 525.#382 V78 Use Keep rdx |V14 a|V79 a|V78 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 525.#383 V52 Use * Keep rbx |V14 a|V79 a|V78 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 533.#384 V78 Use * Keep rdx |V14 a|V79 a|V78 a| |V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 533.#385 V53 Use * Keep rbp |V14 a|V79 a|V78 a| |V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 537.#386 rcx Fixd Keep rcx |V14 a|V79 a| | | |V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 537.#387 V79 Use * Keep rcx |V14 a|V79 a| | | |V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 538.#388 rcx Fixd Keep rcx |V14 a| | | | |V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 538.#389 I127 Def Alloc rcx |V14 a|I127a| | | |V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 540.#390 I128 Def Alloc rdx |V14 a|I127a|I128a| | |V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 541.#391 rdx Fixd Keep rdx |V14 a|I127a|I128a| | |V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 541.#392 I128 Use * Keep rdx |V14 a|I127a|I128a| | |V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 542.#393 rdx Fixd Keep rdx |V14 a|I127a| | | |V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 542.#394 I129 Def Alloc rdx |V14 a|I127a|I129a| | |V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 545.#395 r8 Fixd Keep r8 |V14 a|I127a|I129a| | |V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 545.#396 V8 Use * Copy r8 |V14 a|I127a|I129a| | |V1 a|V2 a|V8 a| |V8 a|V9 a|V3 a|V13 a| 546.#397 r8 Fixd Keep r8 |V14 a|I127a|I129a| | |V1 a|V2 a| | | |V9 a|V3 a|V13 a| 546.#398 I130 Def Alloc r8 |V14 a|I127a|I129a| | |V1 a|V2 a|I130a| | |V9 a|V3 a|V13 a| 549.#399 r9 Fixd Keep r9 |V14 a|I127a|I129a| | |V1 a|V2 a|I130a| | |V9 a|V3 a|V13 a| 549.#400 V9 Use * Copy r9 |V14 a|I127a|I129a| | |V1 a|V2 a|I130a|V9 a| |V9 a|V3 a|V13 a| 550.#401 r9 Fixd Keep r9 |V14 a|I127a|I129a| | |V1 a|V2 a|I130a| | | |V3 a|V13 a| 550.#402 I131 Def Alloc r9 |V14 a|I127a|I129a| | |V1 a|V2 a|I130a|I131a| | |V3 a|V13 a| 551.#403 rcx Fixd Keep rcx |V14 a|I127a|I129a| | |V1 a|V2 a|I130a|I131a| | |V3 a|V13 a| 551.#404 I127 Use * Keep rcx |V14 a|I127a|I129a| | |V1 a|V2 a|I130a|I131a| | |V3 a|V13 a| 551.#405 rdx Fixd Keep rdx |V14 a|I127a|I129a| | |V1 a|V2 a|I130a|I131a| | |V3 a|V13 a| 551.#406 I129 Use * Keep rdx |V14 a|I127a|I129a| | |V1 a|V2 a|I130a|I131a| | |V3 a|V13 a| 551.#407 r8 Fixd Keep r8 |V14 a|I127a|I129a| | |V1 a|V2 a|I130a|I131a| | |V3 a|V13 a| 551.#408 I130 Use * Keep r8 |V14 a|I127a|I129a| | |V1 a|V2 a|I130a|I131a| | |V3 a|V13 a| 551.#409 r9 Fixd Keep r9 |V14 a|I127a|I129a| | |V1 a|V2 a|I130a|I131a| | |V3 a|V13 a| 551.#410 I131 Use * Keep r9 |V14 a|I127a|I129a| | |V1 a|V2 a|I130a|I131a| | |V3 a|V13 a| 552.#411 rax Kill Spill rax | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| Keep rax | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 552.#412 rcx Kill Keep rcx | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 552.#413 rdx Kill Keep rdx | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 552.#414 r8 Kill Keep r8 | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 552.#415 r9 Kill Keep r9 | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 552.#416 r10 Kill Keep r10 | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 552.#417 r11 Kill Keep r11 | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 556.#418 C132 Def Alloc rcx | |C132a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 557.#419 rcx Fixd Keep rcx | |C132a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 557.#420 C132 Use * Keep rcx | |C132a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 558.#421 rcx Fixd Keep rcx | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 558.#422 I133 Def Alloc rcx | |I133a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 560.#423 C134 Def Alloc rdx | |I133a|C134a| | |V1 a|V2 a| | | | |V3 a|V13 a| 561.#424 rdx Fixd Keep rdx | |I133a|C134a| | |V1 a|V2 a| | | | |V3 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 561.#425 C134 Use * Keep rdx | |I133a|C134a| | |V1 a|V2 a| | | | |V3 a|V13 a| 562.#426 rdx Fixd Keep rdx | |I133a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 562.#427 I135 Def Alloc rdx | |I133a|I135a| | |V1 a|V2 a| | | | |V3 a|V13 a| 563.#428 rcx Fixd Keep rcx | |I133a|I135a| | |V1 a|V2 a| | | | |V3 a|V13 a| 563.#429 I133 Use * Keep rcx | |I133a|I135a| | |V1 a|V2 a| | | | |V3 a|V13 a| 563.#430 rdx Fixd Keep rdx | |I133a|I135a| | |V1 a|V2 a| | | | |V3 a|V13 a| 563.#431 I135 Use * Keep rdx | |I133a|I135a| | |V1 a|V2 a| | | | |V3 a|V13 a| 564.#432 rax Kill Keep rax | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 564.#433 rcx Kill Keep rcx | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 564.#434 rdx Kill Keep rdx | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 564.#435 r8 Kill Keep r8 | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 564.#436 r9 Kill Keep r9 | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 564.#437 r10 Kill Keep r10 | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 564.#438 r11 Kill Keep r11 | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 564.#439 rax Fixd Keep rax | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 564.#440 I136 Def * Alloc rax |I136a| | | | |V1 a|V2 a| | | | |V3 a|V13 a| 566.#441 C137 Def Alloc rcx | |C137a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 567.#442 C137 Use * Keep rcx | |C137a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 568.#443 I138 Def Alloc rcx | |I138a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 571.#444 I138 Use * Keep rcx | |I138a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 572.#445 I139 Def Alloc rcx | |I139a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 573.#446 I139 Use * Keep rcx | |I139a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 574.#447 V80 Def Alloc rcx | |V80 a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 577.#448 V80 Use Keep rcx | |V80 a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 578.#449 I140 Def Alloc rdx | |V80 a|I140a| | |V1 a|V2 a| | | | |V3 a|V13 a| 579.#450 I140 Use * Keep rdx | |V80 a|I140a| | |V1 a|V2 a| | | | |V3 a|V13 a| 585.#451 V80 Use * Keep rcx | |V80 a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 586.#452 I141 Def Alloc rcx | |I141a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 587.#453 I141 Use * Keep rcx | |I141a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 592.#454 I142 Def Alloc rcx | |I142a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 593.#455 rcx Fixd Keep rcx | |I142a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 593.#456 I142 Use * Keep rcx | |I142a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 594.#457 rcx Fixd Keep rcx | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 594.#458 I143 Def Alloc rcx | |I143a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 597.#459 rdx Fixd Keep rdx | |I143a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 597.#460 V14 Use * ReLod NA | |I143a| | | |V1 a|V2 a| | | | |V3 a|V13 a| Alloc rdx | |I143a|V14 a| | |V1 a|V2 a| | | | |V3 a|V13 a| 598.#461 rdx Fixd Keep rdx | |I143a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 598.#462 I144 Def Alloc rdx | |I143a|I144a| | |V1 a|V2 a| | | | |V3 a|V13 a| 599.#463 rcx Fixd Keep rcx | |I143a|I144a| | |V1 a|V2 a| | | | |V3 a|V13 a| 599.#464 I143 Use * Keep rcx | |I143a|I144a| | |V1 a|V2 a| | | | |V3 a|V13 a| 599.#465 rdx Fixd Keep rdx | |I143a|I144a| | |V1 a|V2 a| | | | |V3 a|V13 a| 599.#466 I144 Use * Keep rdx | |I143a|I144a| | |V1 a|V2 a| | | | |V3 a|V13 a| 600.#467 rax Kill Keep rax | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 600.#468 rcx Kill Keep rcx | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 600.#469 rdx Kill Keep rdx | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 600.#470 r8 Kill Keep r8 | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 600.#471 r9 Kill Keep r9 | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 600.#472 r10 Kill Keep r10 | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 600.#473 r11 Kill Keep r11 | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 604.#474 I145 Def Alloc rcx | |I145a| | | |V1 a|V2 a| | | | |V3 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 605.#475 I145 Use * Keep rcx | |I145a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 606.#476 V64 Def Alloc rcx | |V64 a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 608.#477 I146 Def Alloc rdx | |V64 a|I146a| | |V1 a|V2 a| | | | |V3 a|V13 a| 609.#478 I146 Use * Keep rdx | |V64 a|I146a| | |V1 a|V2 a| | | | |V3 a|V13 a| 610.#479 V65 Def Alloc rdx | |V64 a|V65 a| | |V1 a|V2 a| | | | |V3 a|V13 a| 614.#480 I147 Def Alloc rax |I147a|V64 a|V65 a| | |V1 a|V2 a| | | | |V3 a|V13 a| 615.#481 I147 Use * Keep rax |I147a|V64 a|V65 a| | |V1 a|V2 a| | | | |V3 a|V13 a| 616.#482 V81 Def Alloc rax |V81 a|V64 a|V65 a| | |V1 a|V2 a| | | | |V3 a|V13 a| 621.#483 V81 Use Keep rax |V81 a|V64 a|V65 a| | |V1 a|V2 a| | | | |V3 a|V13 a| 621.#484 V64 Use * Keep rcx |V81 a|V64 a|V65 a| | |V1 a|V2 a| | | | |V3 a|V13 a| 629.#485 V81 Use * Keep rax |V81 a| |V65 a| | |V1 a|V2 a| | | | |V3 a|V13 a| 629.#486 V65 Use * Keep rdx |V81 a| |V65 a| | |V1 a|V2 a| | | | |V3 a|V13 a| 632.#487 I148 Def Alloc rcx | |I148a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 633.#488 rcx Fixd Keep rcx | |I148a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 633.#489 I148 Use * Keep rcx | |I148a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 634.#490 rcx Fixd Keep rcx | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 634.#491 I149 Def Alloc rcx | |I149a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 636.#492 I150 Def Alloc rdx | |I149a|I150a| | |V1 a|V2 a| | | | |V3 a|V13 a| 637.#493 rdx Fixd Keep rdx | |I149a|I150a| | |V1 a|V2 a| | | | |V3 a|V13 a| 637.#494 I150 Use * Keep rdx | |I149a|I150a| | |V1 a|V2 a| | | | |V3 a|V13 a| 638.#495 rdx Fixd Keep rdx | |I149a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 638.#496 I151 Def Alloc rdx | |I149a|I151a| | |V1 a|V2 a| | | | |V3 a|V13 a| 639.#497 rcx Fixd Keep rcx | |I149a|I151a| | |V1 a|V2 a| | | | |V3 a|V13 a| 639.#498 I149 Use * Keep rcx | |I149a|I151a| | |V1 a|V2 a| | | | |V3 a|V13 a| 639.#499 rdx Fixd Keep rdx | |I149a|I151a| | |V1 a|V2 a| | | | |V3 a|V13 a| 639.#500 I151 Use * Keep rdx | |I149a|I151a| | |V1 a|V2 a| | | | |V3 a|V13 a| 640.#501 rax Kill Keep rax | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 640.#502 rcx Kill Keep rcx | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 640.#503 rdx Kill Keep rdx | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 640.#504 r8 Kill Keep r8 | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 640.#505 r9 Kill Keep r9 | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 640.#506 r10 Kill Keep r10 | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 640.#507 r11 Kill Keep r11 | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 640.#508 rax Fixd Keep rax | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 640.#509 I152 Def Alloc rax |I152a| | | | |V1 a|V2 a| | | | |V3 a|V13 a| 641.#510 I152 Use * Keep rax |I152a| | | | |V1 a|V2 a| | | | |V3 a|V13 a| 642.#511 V43 Def Alloc rbx | | | |V43 a| |V1 a|V2 a| | | | |V3 a|V13 a| 646.#512 C153 Def Alloc rcx | |C153a| |V43 a| |V1 a|V2 a| | | | |V3 a|V13 a| 647.#513 C153 Use * Keep rcx | |C153a| |V43 a| |V1 a|V2 a| | | | |V3 a|V13 a| 651.#514 V43 Use * Keep rbx | |C153i| |V43 a| |V1 a|V2 a| | | | |V3 a|V13 a| 652.#515 V17 Def Alloc rbx | |C153i| |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 656.#516 I154 Def Alloc rcx | |I154a| |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 657.#517 I154 Use * Keep rcx | |I154a| |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 658.#518 V66 Def Alloc rcx | |V66 a| |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 660.#519 I155 Def Alloc rdx | |V66 a|I155a|V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 661.#520 I155 Use * Keep rdx | |V66 a|I155a|V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 662.#521 V67 Def Alloc rdx | |V66 a|V67 a|V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 666.#522 I156 Def Alloc rax |I156a|V66 a|V67 a|V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 667.#523 I156 Use * Keep rax |I156a|V66 a|V67 a|V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 668.#524 V82 Def Alloc rax |V82 a|V66 a|V67 a|V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 673.#525 V82 Use Keep rax |V82 a|V66 a|V67 a|V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 673.#526 V66 Use * Keep rcx |V82 a|V66 a|V67 a|V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 681.#527 V82 Use * Keep rax |V82 a| |V67 a|V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 681.#528 V67 Use * Keep rdx |V82 a| |V67 a|V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 684.#529 I157 Def Alloc rcx | |I157a| |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 685.#530 rcx Fixd Keep rcx | |I157a| |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 685.#531 I157 Use * Keep rcx | |I157a| |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 686.#532 rcx Fixd Keep rcx | | | |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 686.#533 I158 Def Alloc rcx | |I158a| |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 688.#534 I159 Def Alloc rdx | |I158a|I159a|V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 689.#535 rdx Fixd Keep rdx | |I158a|I159a|V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 689.#536 I159 Use * Keep rdx | |I158a|I159a|V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 690.#537 rdx Fixd Keep rdx | |I158a| |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 690.#538 I160 Def Alloc rdx | |I158a|I160a|V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 691.#539 rcx Fixd Keep rcx | |I158a|I160a|V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 691.#540 I158 Use * Keep rcx | |I158a|I160a|V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 691.#541 rdx Fixd Keep rdx | |I158a|I160a|V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 691.#542 I160 Use * Keep rdx | |I158a|I160a|V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 692.#543 rax Kill Keep rax | | | |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 692.#544 rcx Kill Keep rcx | | | |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 692.#545 rdx Kill Keep rdx | | | |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 692.#546 r8 Kill Keep r8 | | | |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 692.#547 r9 Kill Keep r9 | | | |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 692.#548 r10 Kill Keep r10 | | | |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 692.#549 r11 Kill Keep r11 | | | |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 692.#550 rax Fixd Keep rax | | | |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 692.#551 I161 Def Alloc rax |I161a| | |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 693.#552 I161 Use * Keep rax |I161a| | |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 694.#553 V46 Def Alloc rax |V46 a| | |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 698.#554 C162 Def Alloc rcx |V46 a|C162a| |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 699.#555 C162 Use * Keep rcx |V46 a|C162a| |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 703.#556 V46 Use * Keep rax |V46 a|C162i| |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 704.#557 V18 Def Alloc rax |V18 a|C162i| |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 711.#558 V18 Use Keep rax |V18 a|C162i| |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 711.#559 V17 Use Keep rbx |V18 a|C162i| |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 715.#560 BB24 PredBB23 |V18 i| | |V17 i| |V1 a|V2 a| | | | |V3 a|V13 a| 720.#561 C163 Def Alloc rbp |V18 i| | |V17 i|C163a|V1 a|V2 a| | | | |V3 a|V13 a| 721.#562 C163 Use * Keep rbp |V18 i| | |V17 i|C163a|V1 a|V2 a| | | | |V3 a|V13 a| 722.#563 V33 Def Alloc rbp |V18 i| | |V17 i|V33 a|V1 a|V2 a| | | | |V3 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 723.#564 BB25 PredBB23 |V18 a| | |V17 a|V33 i|V1 a|V2 a| | | | |V3 a|V13 a| 731.#565 V18 Use * Keep rax |V18 a| | |V17 a|V33 i|V1 a|V2 a| | | | |V3 a|V13 a| 731.#566 V17 Use *D Keep rbx |V18 a| | |V17 a|V33 i|V1 a|V2 a| | | | |V3 a|V13 a| 732.#567 I164 Def Alloc rbp | | | |V17 a|I164a|V1 a|V2 a| | | | |V3 a|V13 a| 733.#568 I164 Use * Keep rbp | | | | |I164a|V1 a|V2 a| | | | |V3 a|V13 a| 734.#569 V33 Def Alloc rbp | | | | |V33 a|V1 a|V2 a| | | | |V3 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 735.#570 BB26 PredBB24 | | | | |V33 a|V1 a|V2 a| | | | |V3 a|V13 a| 739.#571 V33 Use * Keep rbp | | | | |V33 a|V1 a|V2 a| | | | |V3 a|V13 a| 740.#572 V19 Def Alloc rbp | | | | |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 747.#573 V19 Use Keep rbp | | | | |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 751.#574 BB27 PredBB26 | | | | |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 756.#575 I165 Def Alloc rcx | |I165a| | |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 757.#576 rcx Fixd Keep rcx | |I165a| | |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 757.#577 I165 Use * Keep rcx | |I165a| | |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 758.#578 rcx Fixd Keep rcx | | | | |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 758.#579 I166 Def Alloc rcx | |I166a| | |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 761.#580 rdx Fixd Keep rdx | |I166a| | |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 761.#581 V19 Use Copy rdx | |I166a|V19 a| |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 762.#582 rdx Fixd Keep rdx | |I166a|V19 a| |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 762.#583 I167 Def Alloc rdx | |I166a|I167a| |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 763.#584 rcx Fixd Keep rcx | |I166a|I167a| |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 763.#585 I166 Use * Keep rcx | |I166a|I167a| |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 763.#586 rdx Fixd Keep rdx | |I166a|I167a| |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 763.#587 I167 Use * Keep rdx | |I166a|I167a| |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 764.#588 rax Kill Keep rax | | | | |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 764.#589 rcx Kill Keep rcx | | | | |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 764.#590 rdx Kill Keep rdx | | | | |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 764.#591 r8 Kill Keep r8 | | | | |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 764.#592 r9 Kill Keep r9 | | | | |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 764.#593 r10 Kill Keep r10 | | | | |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 764.#594 r11 Kill Keep r11 | | | | |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 765.#595 BB28 PredBB26 | | | | |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 773.#596 V3 Use * Keep r14 | | | | |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 773.#597 V13 Use Keep r15 | | | | |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 774.#598 I168 Def Alloc r14 | | | | |V19 a|V1 a|V2 a| | | | |I168a|V13 a| 775.#599 I168 Use * Keep r14 | | | | |V19 a|V1 a|V2 a| | | | |I168a|V13 a| 776.#600 V20 Def Alloc r14 | | | | |V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 781.#601 V20 Use Keep r14 | | | | |V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 782.#602 V21 Def Alloc rbx | | | |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 789.#603 V13 Use Keep r15 | | | |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 793.#604 BB29 PredBB28 | | | |V21 i|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 801.#605 V19 Use Keep rbp | | | |V21 i|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 801.#606 V20 Use Keep r14 | | | |V21 i|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 805.#607 BB30 PredBB29 | | | |V21 i|V19 i|V1 a|V2 a| | | | |V20 i|V13 a| 811.#608 V2 Use * Keep rdi | | | |V21 i|V19 i|V1 a|V2 i| | | | |V20 i|V13 a| 814.#609 C169 Def Alloc r8 | | | |V21 i|V19 i|V1 a|V2 i|C169a| | | |V20 i|V13 a| 815.#610 r8 Fixd Keep r8 | | | |V21 i|V19 i|V1 a|V2 i|C169a| | | |V20 i|V13 a| 815.#611 C169 Use * Keep r8 | | | |V21 i|V19 i|V1 a|V2 i|C169a| | | |V20 i|V13 a| 816.#612 r8 Fixd Keep r8 | | | |V21 i|V19 i|V1 a|V2 i| | | | |V20 i|V13 a| 816.#613 I170 Def Alloc r8 | | | |V21 i|V19 i|V1 a|V2 i|I170a| | | |V20 i|V13 a| 818.#614 I171 Def Alloc rcx | |I171a| |V21 i|V19 i|V1 a|V2 i|I170a| | | |V20 i|V13 a| 819.#615 rcx Fixd Keep rcx | |I171a| |V21 i|V19 i|V1 a|V2 i|I170a| | | |V20 i|V13 a| 819.#616 I171 Use * Keep rcx | |I171a| |V21 i|V19 i|V1 a|V2 i|I170a| | | |V20 i|V13 a| 820.#617 rcx Fixd Keep rcx | | | |V21 i|V19 i|V1 a|V2 i|I170a| | | |V20 i|V13 a| 820.#618 I172 Def Alloc rcx | |I172a| |V21 i|V19 i|V1 a|V2 i|I170a| | | |V20 i|V13 a| 823.#619 rdx Fixd Keep rdx | |I172a| |V21 i|V19 i|V1 a|V2 i|I170a| | | |V20 i|V13 a| 823.#620 V13 Use * Copy rdx | |I172a|V13 a|V21 i|V19 i|V1 a|V2 i|I170a| | | |V20 i|V13 a| 824.#621 rdx Fixd Keep rdx | |I172a|V13 i|V21 i|V19 i|V1 a|V2 i|I170a| | | |V20 i|V13 i| 824.#622 I173 Def Alloc rdx | |I172a|I173a|V21 i|V19 i|V1 a|V2 i|I170a| | | |V20 i|V13 i| 827.#623 r9 Fixd Keep r9 | |I172a|I173a|V21 i|V19 i|V1 a|V2 i|I170a| | | |V20 i|V13 i| 827.#624 V1 Use * Copy r9 | |I172a|I173a|V21 i|V19 i|V1 a|V2 i|I170a|V1 a| | |V20 i|V13 i| 828.#625 r9 Fixd Keep r9 | |I172a|I173a|V21 i|V19 i|V1 i|V2 i|I170a|V1 i| | |V20 i|V13 i| 828.#626 I174 Def Alloc r9 | |I172a|I173a|V21 i|V19 i|V1 i|V2 i|I170a|I174a| | |V20 i|V13 i| 829.#627 r8 Fixd Keep r8 | |I172a|I173a|V21 i|V19 i|V1 i|V2 i|I170a|I174a| | |V20 i|V13 i| 829.#628 I170 Use * Keep r8 | |I172a|I173a|V21 i|V19 i|V1 i|V2 i|I170a|I174a| | |V20 i|V13 i| 829.#629 rcx Fixd Keep rcx | |I172a|I173a|V21 i|V19 i|V1 i|V2 i|I170a|I174a| | |V20 i|V13 i| 829.#630 I172 Use * Keep rcx | |I172a|I173a|V21 i|V19 i|V1 i|V2 i|I170a|I174a| | |V20 i|V13 i| 829.#631 rdx Fixd Keep rdx | |I172a|I173a|V21 i|V19 i|V1 i|V2 i|I170a|I174a| | |V20 i|V13 i| 829.#632 I173 Use * Keep rdx | |I172a|I173a|V21 i|V19 i|V1 i|V2 i|I170a|I174a| | |V20 i|V13 i| 829.#633 r9 Fixd Keep r9 | |I172a|I173a|V21 i|V19 i|V1 i|V2 i|I170a|I174a| | |V20 i|V13 i| 829.#634 I174 Use * Keep r9 | |I172a|I173a|V21 i|V19 i|V1 i|V2 i|I170a|I174a| | |V20 i|V13 i| 830.#635 rax Kill Keep rax | | | |V21 i|V19 i|V1 i|V2 i| | | | |V20 i|V13 i| 830.#636 rcx Kill Keep rcx | | | |V21 i|V19 i|V1 i|V2 i| | | | |V20 i|V13 i| 830.#637 rdx Kill Keep rdx | | | |V21 i|V19 i|V1 i|V2 i| | | | |V20 i|V13 i| 830.#638 r8 Kill Keep r8 | | | |V21 i|V19 i|V1 i|V2 i| | | | |V20 i|V13 i| 830.#639 r9 Kill Keep r9 | | | |V21 i|V19 i|V1 i|V2 i| | | | |V20 i|V13 i| 830.#640 r10 Kill Keep r10 | | | |V21 i|V19 i|V1 i|V2 i| | | | |V20 i|V13 i| 830.#641 r11 Kill Keep r11 | | | |V21 i|V19 i|V1 i|V2 i| | | | |V20 i|V13 i| 830.#642 rax Fixd Keep rax | | | |V21 i|V19 i|V1 i|V2 i| | | | |V20 i|V13 i| 830.#643 I175 Def Alloc rax |I175a| | |V21 i|V19 i|V1 i|V2 i| | | | |V20 i|V13 i| 831.#644 I175 Use * Keep rax |I175a| | |V21 i|V19 i|V1 i|V2 i| | | | |V20 i|V13 i| 832.#645 V51 Def Alloc rax |V51 a| | |V21 i|V19 i|V1 i|V2 i| | | | |V20 i|V13 i| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 833.#646 BB31 PredBB29 |V51 i| | |V21 i|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 841.#647 V20 Use Keep r14 |V51 i| | |V21 i|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 841.#648 V19 Use Keep rbp |V51 i| | |V21 i|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 842.#649 I176 Def Alloc rbx |V51 i| | |I176a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 843.#650 I176 Use * Keep rbx |V51 i| | |I176a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| Restr rbx |V51 i| | |V21 i|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 844.#651 V21 Def Alloc rbx |V51 i| | |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 845.#652 BB32 PredBB28 |V51 i| | |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 850.#653 I177 Def Alloc rcx |V51 i|I177a| |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 851.#654 I177 Use * Keep rcx |V51 i|I177a| |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 854.#655 I178 Def Alloc rcx |V51 i|I178a| |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 855.#656 I178 Use * Keep rcx |V51 i|I178a| |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 860.#657 I179 Def Alloc rcx |V51 i|I179a| |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 861.#658 I179 Use * Keep rcx |V51 i|I179a| |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 862.#659 V70 Def Alloc rcx |V51 i|V70 a| |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 864.#660 I180 Def Alloc rdx |V51 i|V70 a|I180a|V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 865.#661 I180 Use * Keep rdx |V51 i|V70 a|I180a|V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 866.#662 V71 Def Alloc rdx |V51 i|V70 a|V71 a|V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 868.#663 I181 Def Alloc rax |I181a|V70 a|V71 a|V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 869.#664 I181 Use * Keep rax |I181a|V70 a|V71 a|V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| Restr rax |V51 i|V70 a|V71 a|V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 870.#665 V84 Def Alloc rax |V84 a|V70 a|V71 a|V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 872.#666 I182 Def Alloc r8 |V84 a|V70 a|V71 a|V21 a|V19 a|V1 a|V2 a|I182a| | | |V20 a|V13 a| 873.#667 I182 Use * Keep r8 |V84 a|V70 a|V71 a|V21 a|V19 a|V1 a|V2 a|I182a| | | |V20 a|V13 a| 874.#668 V83 Def Alloc r8 |V84 a|V70 a|V71 a|V21 a|V19 a|V1 a|V2 a|V83 a| | | |V20 a|V13 a| 879.#669 V83 Use Keep r8 |V84 a|V70 a|V71 a|V21 a|V19 a|V1 a|V2 a|V83 a| | | |V20 a|V13 a| 879.#670 V70 Use * Keep rcx |V84 a|V70 a|V71 a|V21 a|V19 a|V1 a|V2 a|V83 a| | | |V20 a|V13 a| 887.#671 V83 Use * Keep r8 |V84 a| |V71 a|V21 a|V19 a|V1 a|V2 a|V83 a| | | |V20 a|V13 a| 887.#672 V71 Use * Keep rdx |V84 a| |V71 a|V21 a|V19 a|V1 a|V2 a|V83 a| | | |V20 a|V13 a| 891.#673 rcx Fixd Keep rcx |V84 a| | |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 891.#674 V84 Use * Copy rcx |V84 a|V84 a| |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| Restr rax |V51 i|V84 i| |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 892.#675 rcx Fixd Keep rcx |V51 i| | |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 892.#676 I183 Def Alloc rcx |V51 i|I183a| |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 894.#677 I184 Def Alloc rdx |V51 i|I183a|I184a|V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 895.#678 rdx Fixd Keep rdx |V51 i|I183a|I184a|V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 895.#679 I184 Use * Keep rdx |V51 i|I183a|I184a|V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 896.#680 rdx Fixd Keep rdx |V51 i|I183a| |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 896.#681 I185 Def Alloc rdx |V51 i|I183a|I185a|V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 897.#682 rcx Fixd Keep rcx |V51 i|I183a|I185a|V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 897.#683 I183 Use * Keep rcx |V51 i|I183a|I185a|V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 897.#684 rdx Fixd Keep rdx |V51 i|I183a|I185a|V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 897.#685 I185 Use * Keep rdx |V51 i|I183a|I185a|V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 898.#686 rax Kill Keep rax | | | |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 898.#687 rcx Kill Keep rcx | | | |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 898.#688 rdx Kill Keep rdx | | | |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 898.#689 r8 Kill Keep r8 | | | |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 898.#690 r9 Kill Keep r9 | | | |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 898.#691 r10 Kill Keep r10 | | | |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 898.#692 r11 Kill Keep r11 | | | |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 898.#693 rax Fixd Keep rax | | | |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 898.#694 I186 Def Alloc rax |I186a| | |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 901.#695 I186 Use * Keep rax |I186a| | |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 905.#696 BB33 PredBB32 | | | |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 911.#697 V19 Use * Keep rbp | | | |V21 a|V19 i|V1 a|V2 a| | | | |V20 a|V13 a| 912.#698 V34 Def Alloc rbp | | | |V21 a|V34 a|V1 a|V2 a| | | | |V20 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 913.#699 BB34 PredBB32 | | | |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 921.#700 V19 Use * Keep rbp | | | |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 922.#701 I187 Def Alloc rbp | | | |V21 a|I187a|V1 a|V2 a| | | | |V20 a|V13 a| 923.#702 I187 Use * Keep rbp | | | |V21 a|I187a|V1 a|V2 a| | | | |V20 a|V13 a| 924.#703 V34 Def Alloc rbp | | | |V21 a|V34 a|V1 a|V2 a| | | | |V20 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 925.#704 BB35 PredBB33 | | | |V21 a|V34 a|V1 a|V2 a| | | | |V20 a|V13 a| 929.#705 V34 Use * Keep rbp | | | |V21 a|V34 a|V1 a|V2 a| | | | |V20 a|V13 a| 930.#706 V22 Def Alloc rbp | | | |V21 a|V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 934.#707 I188 Def Alloc rcx | |I188a| |V21 a|V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 935.#708 rcx Fixd Keep rcx | |I188a| |V21 a|V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 935.#709 I188 Use * Keep rcx | |I188a| |V21 a|V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 936.#710 rcx Fixd Keep rcx | | | |V21 a|V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 936.#711 I189 Def Alloc rcx | |I189a| |V21 a|V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 939.#712 rdx Fixd Keep rdx | |I189a| |V21 a|V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 939.#713 V21 Use * Copy rdx | |I189a|V21 a|V21 a|V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 940.#714 rdx Fixd Keep rdx | |I189a| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 940.#715 I190 Def Alloc rdx | |I189a|I190a| |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 941.#716 rcx Fixd Keep rcx | |I189a|I190a| |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 941.#717 I189 Use * Keep rcx | |I189a|I190a| |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 941.#718 rdx Fixd Keep rdx | |I189a|I190a| |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 941.#719 I190 Use * Keep rdx | |I189a|I190a| |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 942.#720 rax Kill Keep rax | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 942.#721 rcx Kill Keep rcx | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 942.#722 rdx Kill Keep rdx | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 942.#723 r8 Kill Keep r8 | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 942.#724 r9 Kill Keep r9 | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 942.#725 r10 Kill Keep r10 | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 942.#726 r11 Kill Keep r11 | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 946.#727 I191 Def Alloc rcx | |I191a| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 947.#728 I191 Use * Keep rcx | |I191a| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 948.#729 V88 Def Alloc rcx | |V88 a| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 950.#730 I192 Def Alloc rdx | |V88 a|I192a| |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 951.#731 I192 Use * Keep rdx | |V88 a|I192a| |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 952.#732 V85 Def Alloc rdx | |V88 a|V85 a| |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 956.#733 I193 Def Alloc r8 | |V88 a|V85 a| |V22 a|V1 a|V2 a|I193a| | | |V20 a|V13 a| 957.#734 V85 Use Keep rdx | |V88 a|V85 a| |V22 a|V1 a|V2 a|I193a| | | |V20 a|V13 a| 957.#735 I193 Use * Keep r8 | |V88 a|V85 a| |V22 a|V1 a|V2 a|I193a| | | |V20 a|V13 a| 964.#736 I194 Def Alloc r8 | |V88 a|V85 a| |V22 a|V1 a|V2 a|I194a| | | |V20 a|V13 a| 965.#737 V85 Use * Keep rdx | |V88 a|V85 a| |V22 a|V1 a|V2 a|I194a| | | |V20 a|V13 a| 965.#738 I194 Use * Keep r8 | |V88 a|V85 a| |V22 a|V1 a|V2 a|I194a| | | |V20 a|V13 a| 968.#739 I195 Def Alloc rdx | |V88 a|I195a| |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 969.#740 I195 Use * Keep rdx | |V88 a|I195a| |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 970.#741 V87 Def Alloc rdx | |V88 a|V87 a| |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 974.#742 I196 Def Alloc r8 | |V88 a|V87 a| |V22 a|V1 a|V2 a|I196a| | | |V20 a|V13 a| 975.#743 V87 Use Keep rdx | |V88 a|V87 a| |V22 a|V1 a|V2 a|I196a| | | |V20 a|V13 a| 975.#744 I196 Use * Keep r8 | |V88 a|V87 a| |V22 a|V1 a|V2 a|I196a| | | |V20 a|V13 a| 982.#745 I197 Def Alloc r8 | |V88 a|V87 a| |V22 a|V1 a|V2 a|I197a| | | |V20 a|V13 a| 983.#746 V87 Use * Keep rdx | |V88 a|V87 a| |V22 a|V1 a|V2 a|I197a| | | |V20 a|V13 a| 983.#747 I197 Use * Keep r8 | |V88 a|V87 a| |V22 a|V1 a|V2 a|I197a| | | |V20 a|V13 a| 987.#748 rcx Fixd Keep rcx | |V88 a| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 987.#749 V88 Use * Keep rcx | |V88 a| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 988.#750 rcx Fixd Keep rcx | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 988.#751 I198 Def Alloc rcx | |I198a| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 990.#752 I199 Def Alloc rdx | |I198a|I199a| |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 991.#753 rdx Fixd Keep rdx | |I198a|I199a| |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 991.#754 I199 Use * Keep rdx | |I198a|I199a| |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 992.#755 rdx Fixd Keep rdx | |I198a| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 992.#756 I200 Def Alloc rdx | |I198a|I200a| |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 994.#757 I201 Def Alloc r8 | |I198a|I200a| |V22 a|V1 a|V2 a|I201a| | | |V20 a|V13 a| 995.#758 r8 Fixd Keep r8 | |I198a|I200a| |V22 a|V1 a|V2 a|I201a| | | |V20 a|V13 a| 995.#759 I201 Use * Keep r8 | |I198a|I200a| |V22 a|V1 a|V2 a|I201a| | | |V20 a|V13 a| 996.#760 r8 Fixd Keep r8 | |I198a|I200a| |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 996.#761 I202 Def Alloc r8 | |I198a|I200a| |V22 a|V1 a|V2 a|I202a| | | |V20 a|V13 a| 998.#762 I203 Def Alloc r9 | |I198a|I200a| |V22 a|V1 a|V2 a|I202a|I203a| | |V20 a|V13 a| 999.#763 r9 Fixd Keep r9 | |I198a|I200a| |V22 a|V1 a|V2 a|I202a|I203a| | |V20 a|V13 a| 999.#764 I203 Use * Keep r9 | |I198a|I200a| |V22 a|V1 a|V2 a|I202a|I203a| | |V20 a|V13 a| 1000.#765 r9 Fixd Keep r9 | |I198a|I200a| |V22 a|V1 a|V2 a|I202a| | | |V20 a|V13 a| 1000.#766 I204 Def Alloc r9 | |I198a|I200a| |V22 a|V1 a|V2 a|I202a|I204a| | |V20 a|V13 a| 1001.#767 rcx Fixd Keep rcx | |I198a|I200a| |V22 a|V1 a|V2 a|I202a|I204a| | |V20 a|V13 a| 1001.#768 I198 Use * Keep rcx | |I198a|I200a| |V22 a|V1 a|V2 a|I202a|I204a| | |V20 a|V13 a| 1001.#769 rdx Fixd Keep rdx | |I198a|I200a| |V22 a|V1 a|V2 a|I202a|I204a| | |V20 a|V13 a| 1001.#770 I200 Use * Keep rdx | |I198a|I200a| |V22 a|V1 a|V2 a|I202a|I204a| | |V20 a|V13 a| 1001.#771 r8 Fixd Keep r8 | |I198a|I200a| |V22 a|V1 a|V2 a|I202a|I204a| | |V20 a|V13 a| 1001.#772 I202 Use * Keep r8 | |I198a|I200a| |V22 a|V1 a|V2 a|I202a|I204a| | |V20 a|V13 a| 1001.#773 r9 Fixd Keep r9 | |I198a|I200a| |V22 a|V1 a|V2 a|I202a|I204a| | |V20 a|V13 a| 1001.#774 I204 Use * Keep r9 | |I198a|I200a| |V22 a|V1 a|V2 a|I202a|I204a| | |V20 a|V13 a| 1002.#775 rax Kill Keep rax | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1002.#776 rcx Kill Keep rcx | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1002.#777 rdx Kill Keep rdx | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1002.#778 r8 Kill Keep r8 | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1002.#779 r9 Kill Keep r9 | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1002.#780 r10 Kill Keep r10 | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1002.#781 r11 Kill Keep r11 | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1004.#782 I205 Def Alloc rcx | |I205a| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1005.#783 I205 Use * Keep rcx | |I205a| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1006.#784 V89 Def Alloc rcx | |V89 a| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1010.#785 I206 Def Alloc rax |I206a|V89 a| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1011.#786 V89 Use Keep rcx |I206a|V89 a| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1011.#787 I206 Use * Keep rax |I206a|V89 a| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1018.#788 I207 Def Alloc rax |I207a|V89 a| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1019.#789 V89 Use * Keep rcx |I207a|V89 a| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1019.#790 I207 Use * Keep rax |I207a|V89 a| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1022.#791 I208 Def Alloc rcx | |I208a| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1023.#792 rcx Fixd Keep rcx | |I208a| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1023.#793 I208 Use * Keep rcx | |I208a| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1024.#794 rcx Fixd Keep rcx | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1024.#795 I209 Def Alloc rcx | |I209a| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1025.#796 rcx Fixd Keep rcx | |I209a| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1025.#797 I209 Use * Keep rcx | |I209a| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1026.#798 rax Kill Keep rax | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1026.#799 rcx Kill Keep rcx | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1026.#800 rdx Kill Keep rdx | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1026.#801 r8 Kill Keep r8 | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1026.#802 r9 Kill Keep r9 | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1026.#803 r10 Kill Keep r10 | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1026.#804 r11 Kill Keep r11 | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1026.#805 rax Fixd Keep rax | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1026.#806 I210 Def Alloc rax |I210a| | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1027.#807 I210 Use * Keep rax |I210a| | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1028.#808 V24 Def Alloc rbx | | | |V24 a|V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1034.#809 I211 Def Alloc r12 | | | |V24 a|V22 a|V1 a|V2 a| | |I211a| |V20 a|V13 a| 1035.#810 I211 Use * Keep r12 | | | |V24 a|V22 a|V1 a|V2 a| | |I211a| |V20 a|V13 a| 1036.#811 V25 Def Alloc r12 | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1039.#812 rcx Fixd Keep rcx | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1039.#813 V24 Use Copy rcx | |V24 a| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1040.#814 rcx Fixd Keep rcx | |V24 a| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1040.#815 I212 Def Alloc rcx | |I212a| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1041.#816 rcx Fixd Keep rcx | |I212a| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1041.#817 I212 Use * Keep rcx | |I212a| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1042.#818 rax Kill Keep rax | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1042.#819 rcx Kill Keep rcx | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1042.#820 rdx Kill Keep rdx | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1042.#821 r8 Kill Keep r8 | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1042.#822 r9 Kill Keep r9 | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1042.#823 r10 Kill Keep r10 | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1042.#824 r11 Kill Keep r11 | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1042.#825 rax Fixd Keep rax | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1042.#826 I213 Def Alloc rax |I213a| | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1043.#827 I213 Use * Keep rax |I213a| | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1044.#828 V26 Def Alloc rax |V26 a| | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1051.#829 V26 Use Keep rax |V26 a| | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1051.#830 V20 Use Keep r14 |V26 a| | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1055.#831 BB36 PredBB35 |V26 a| | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1063.#832 V26 Use * Keep rax |V26 a| | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1063.#833 V20 Use Keep r14 |V26 a| | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1064.#834 I214 Def Alloc rax |I214a| | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1065.#835 I214 Use * Keep rax |I214a| | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1066.#836 V29 Def Alloc rax |V29 a| | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1073.#837 V25 Use * Keep r12 |V29 a| | |V24 a|V22 a|V1 a|V2 a| | |V25 i| |V20 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1077.#838 BB37 PredBB36 |V29 a| | |V24 a|V22 a|V1 a|V2 a| | |V25 i| |V20 a|V13 a| 1086.#839 C215 Def Alloc rdx |V29 a| |C215a|V24 a|V22 a|V1 a|V2 a| | |V25 i| |V20 a|V13 a| 1087.#840 C215 Use * Keep rdx |V29 a| |C215a|V24 a|V22 a|V1 a|V2 a| | |V25 i| |V20 a|V13 a| 1087.#841 rcx Fixd Keep rcx |V29 a| |C215a|V24 a|V22 a|V1 a|V2 a| | |V25 i| |V20 a|V13 a| 1087.#842 V29 Use Copy rcx |V29 a|V29 a|C215a|V24 a|V22 a|V1 a|V2 a| | |V25 i| |V20 a|V13 a| 1088.#843 rcx Kill Keep rcx |V29 a| |C215i|V24 a|V22 a|V1 a|V2 a| | |V25 i| |V20 a|V13 a| 1088.#844 I216 Def Alloc rdx |V29 a| |I216a|V24 a|V22 a|V1 a|V2 a| | |V25 i| |V20 a|V13 a| 1091.#845 I216 Use * Keep rdx |V29 a| |I216a|V24 a|V22 a|V1 a|V2 a| | |V25 i| |V20 a|V13 a| 1092.#846 I217 Def Alloc rdx |V29 a| |I217a|V24 a|V22 a|V1 a|V2 a| | |V25 i| |V20 a|V13 a| 1093.#847 V24 Use Keep rbx |V29 a| |I217a|V24 a|V22 a|V1 a|V2 a| | |V25 i| |V20 a|V13 a| 1093.#848 I217 Use * Keep rdx |V29 a| |I217a|V24 a|V22 a|V1 a|V2 a| | |V25 i| |V20 a|V13 a| 1094.#849 I218 Def Alloc rcx |V29 a|I218a| |V24 a|V22 a|V1 a|V2 a| | |V25 i| |V20 a|V13 a| 1095.#850 I218 Use * Keep rcx |V29 a|I218a| |V24 a|V22 a|V1 a|V2 a| | |V25 i| |V20 a|V13 a| 1096.#851 V37 Def Alloc rcx |V29 a|V37 a| |V24 a|V22 a|V1 a|V2 a| | |V25 i| |V20 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1097.#852 BB38 PredBB36 |V29 a|V37 i| |V24 a|V22 a|V1 a|V2 a| | |V25 i| |V20 a|V13 a| 1102.#853 C219 Def Alloc rcx |V29 a|C219a| |V24 a|V22 a|V1 a|V2 a| | |V25 i| |V20 a|V13 a| 1103.#854 C219 Use * Keep rcx |V29 a|C219a| |V24 a|V22 a|V1 a|V2 a| | |V25 i| |V20 a|V13 a| 1104.#855 V37 Def Restr rcx |V29 a|V37 i| |V24 a|V22 a|V1 a|V2 a| | |V25 i| |V20 a|V13 a| Alloc rcx |V29 a|V37 a| |V24 a|V22 a|V1 a|V2 a| | |V25 i| |V20 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1105.#856 BB39 PredBB37 |V29 a|V37 a| |V24 a|V22 a|V1 a|V2 a| | |V25 i| |V20 a|V13 a| 1109.#857 V37 Use * Keep rcx |V29 a|V37 a| |V24 a|V22 a|V1 a|V2 a| | |V25 i| |V20 a|V13 a| 1110.#858 I220 Def Alloc r12 |V29 a| | |V24 a|V22 a|V1 a|V2 a| | |I220a| |V20 a|V13 a| 1111.#859 I220 Use * Keep r12 |V29 a| | |V24 a|V22 a|V1 a|V2 a| | |I220a| |V20 a|V13 a| Restr r12 |V29 a| | |V24 a|V22 a|V1 a|V2 a| | |V25 i| |V20 a|V13 a| 1112.#860 V25 Def Alloc r12 |V29 a| | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1119.#861 V24 Use * Keep rbx |V29 a| | |V24 i|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1119.#862 rcx Fixd Keep rcx |V29 a| | |V24 i|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1119.#863 V29 Use *D Copy rcx |V29 a|V29 a| |V24 i|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1120.#864 rcx Kill Keep rcx |V29 a| | |V24 i|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1120.#865 I221 Def Alloc rbx |V29 a| | |I221a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1121.#866 I221 Use * Keep rbx | | | |I221a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| Restr rbx | | | |V24 i|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1122.#867 V24 Def Alloc rbx | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1123.#868 BB40 PredBB35 | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1126.#869 I222 Def Alloc rcx | |I222a| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1127.#870 I222 Use * Keep rcx | |I222a| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1128.#871 V90 Def Alloc rcx | |V90 a| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1132.#872 I223 Def Alloc rax |I223a|V90 a| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1133.#873 V90 Use Keep rcx |I223a|V90 a| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1133.#874 I223 Use * Keep rax |I223a|V90 a| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1140.#875 I224 Def Alloc rax |I224a|V90 a| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1141.#876 V90 Use * Keep rcx |I224a|V90 a| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1141.#877 I224 Use * Keep rax |I224a|V90 a| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1144.#878 I225 Def Alloc rcx | |I225a| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1145.#879 rcx Fixd Keep rcx | |I225a| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1145.#880 I225 Use * Keep rcx | |I225a| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1146.#881 rcx Fixd Keep rcx | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1146.#882 I226 Def Alloc rcx | |I226a| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1147.#883 rcx Fixd Keep rcx | |I226a| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1147.#884 I226 Use * Keep rcx | |I226a| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1148.#885 rax Kill Keep rax | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1148.#886 rcx Kill Keep rcx | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1148.#887 rdx Kill Keep rdx | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1148.#888 r8 Kill Keep r8 | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1148.#889 r9 Kill Keep r9 | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1148.#890 r10 Kill Keep r10 | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1148.#891 r11 Kill Keep r11 | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1148.#892 rax Fixd Keep rax | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1148.#893 I227 Def Alloc rax |I227a| | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1151.#894 I227 Use * Keep rax |I227a| | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1151.#895 rcx Fixd Keep rcx |I227a| | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1151.#896 V20 Use *D Copy rcx |I227a|V20 a| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1152.#897 rcx Kill Keep rcx | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1152.#898 I228 Def Alloc rax |I228a| | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1155.#899 I228 Use * Keep rax |I228a| | |V24 a|V22 a|V1 a|V2 a| | |V25 a| | |V13 a| 1155.#900 V24 Use * Keep rbx |I228a| | |V24 a|V22 a|V1 a|V2 a| | |V25 a| | |V13 a| 1156.#901 I229 Def Alloc rdx | | |I229a| |V22 a|V1 a|V2 a| | |V25 a| | |V13 a| 1157.#902 I229 Use * Keep rdx | | |I229a| |V22 a|V1 a|V2 a| | |V25 a| | |V13 a| 1158.#903 V27 Def Alloc rdx | | |V27 a| |V22 a|V1 a|V2 a| | |V25 a| | |V13 a| 1165.#904 V13 Use Keep r15 | | |V27 a| |V22 a|V1 a|V2 a| | |V25 a| | |V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1169.#905 BB41 PredBB40 | | |V27 a| |V22 a|V1 a|V2 a| | |V25 a| | |V13 i| 1175.#906 V22 Use * Keep rbp | | |V27 a| |V22 a|V1 a|V2 a| | |V25 a| | |V13 i| 1176.#907 I230 Def Alloc r8 | | |V27 a| | |V1 a|V2 a|I230a| |V25 a| | |V13 i| 1179.#908 I230 Use * Keep r8 | | |V27 a| | |V1 a|V2 a|I230a| |V25 a| | |V13 i| 1180.#909 I231 Def Alloc r8 | | |V27 a| | |V1 a|V2 a|I231a| |V25 a| | |V13 i| 1181.#910 I231 Use * Keep r8 | | |V27 a| | |V1 a|V2 a|I231a| |V25 a| | |V13 i| 1182.#911 V36 Def Alloc r8 | | |V27 a| | |V1 a|V2 a|V36 a| |V25 a| | |V13 i| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1183.#912 BB42 PredBB40 | | |V27 a| | |V1 a|V2 a|V36 i| |V25 a| | |V13 a| 1191.#913 V13 Use * Keep r15 | | |V27 a| | |V1 a|V2 a|V36 i| |V25 a| | |V13 a| 1192.#914 I232 Def Alloc r8 | | |V27 a| | |V1 a|V2 a|I232a| |V25 a| | | | 1193.#915 I232 Use * Keep r8 | | |V27 a| | |V1 a|V2 a|I232a| |V25 a| | | | Restr r8 | | |V27 a| | |V1 a|V2 a|V36 i| |V25 a| | | | 1194.#916 V36 Def Alloc r8 | | |V27 a| | |V1 a|V2 a|V36 a| |V25 a| | | | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1195.#917 BB43 PredBB41 | | |V27 a| | |V1 a|V2 a|V36 a| |V25 a| | | | 1201.#918 V2 Use * Keep rdi | | |V27 a| | |V1 a|V2 a|V36 a| |V25 a| | | | 1205.#919 rcx Fixd Keep rcx | | |V27 a| | |V1 a| |V36 a| |V25 a| | | | 1205.#920 V1 Use * Copy rcx | |V1 a|V27 a| | |V1 a| |V36 a| |V25 a| | | | 1206.#921 rcx Fixd Keep rcx | | |V27 a| | | | |V36 a| |V25 a| | | | 1206.#922 I233 Def Alloc rcx | |I233a|V27 a| | | | |V36 a| |V25 a| | | | 1209.#923 rdx Fixd Keep rdx | |I233a|V27 a| | | | |V36 a| |V25 a| | | | 1209.#924 V27 Use * Keep rdx | |I233a|V27 a| | | | |V36 a| |V25 a| | | | 1210.#925 rdx Fixd Keep rdx | |I233a| | | | | |V36 a| |V25 a| | | | 1210.#926 I234 Def Alloc rdx | |I233a|I234a| | | | |V36 a| |V25 a| | | | 1213.#927 r8 Fixd Keep r8 | |I233a|I234a| | | | |V36 a| |V25 a| | | | 1213.#928 V36 Use * Keep r8 | |I233a|I234a| | | | |V36 a| |V25 a| | | | 1214.#929 r8 Fixd Keep r8 | |I233a|I234a| | | | | | |V25 a| | | | 1214.#930 I235 Def Alloc r8 | |I233a|I234a| | | | |I235a| |V25 a| | | | 1217.#931 r9 Fixd Keep r9 | |I233a|I234a| | | | |I235a| |V25 a| | | | 1217.#932 V25 Use * Copy r9 | |I233a|I234a| | | | |I235a|V25 a|V25 a| | | | 1218.#933 r9 Fixd Keep r9 | |I233a|I234a| | | | |I235a| | | | | | 1218.#934 I236 Def Alloc r9 | |I233a|I234a| | | | |I235a|I236a| | | | | 1219.#935 rcx Fixd Keep rcx | |I233a|I234a| | | | |I235a|I236a| | | | | 1219.#936 I233 Use * Keep rcx | |I233a|I234a| | | | |I235a|I236a| | | | | 1219.#937 rdx Fixd Keep rdx | |I233a|I234a| | | | |I235a|I236a| | | | | 1219.#938 I234 Use * Keep rdx | |I233a|I234a| | | | |I235a|I236a| | | | | 1219.#939 r8 Fixd Keep r8 | |I233a|I234a| | | | |I235a|I236a| | | | | 1219.#940 I235 Use * Keep r8 | |I233a|I234a| | | | |I235a|I236a| | | | | 1219.#941 r9 Fixd Keep r9 | |I233a|I234a| | | | |I235a|I236a| | | | | 1219.#942 I236 Use * Keep r9 | |I233a|I234a| | | | |I235a|I236a| | | | | 1220.#943 rax Kill Keep rax | | | | | | | | | | | | | | 1220.#944 rcx Kill Keep rcx | | | | | | | | | | | | | | 1220.#945 rdx Kill Keep rdx | | | | | | | | | | | | | | 1220.#946 r8 Kill Keep r8 | | | | | | | | | | | | | | 1220.#947 r9 Kill Keep r9 | | | | | | | | | | | | | | 1220.#948 r10 Kill Keep r10 | | | | | | | | | | | | | | 1220.#949 r11 Kill Keep r11 | | | | | | | | | | | | | | 1220.#950 rax Fixd Keep rax | | | | | | | | | | | | | | 1220.#951 I237 Def Alloc rax |I237a| | | | | | | | | | | | | 1221.#952 I237 Use * Keep rax |I237a| | | | | | | | | | | | | 1222.#953 V51 Def Alloc rax |V51 a| | | | | | | | | | | | | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1223.#954 BB44 PredBB16 |V51 a| | | | | | | | | | | | | 1227.#955 rax Fixd Keep rax |V51 a| | | | | | | | | | | | | 1227.#956 V51 Use * Keep rax | | | | | | | | | | | | | | ------------ REFPOSITIONS AFTER ALLOCATION: ------------ BB00 regmask=[rsi] minReg=1 fixed regOptional> BB00 regmask=[rcx] minReg=1 fixed regOptional> BB00 regmask=[rdi] minReg=1 fixed regOptional> LCL_VAR BB01 regmask=[rcx] minReg=1> IND BB01 regmask=[rbx] minReg=1> BB01 regmask=[rbx] minReg=1 last> STORE_LCL_VAR BB01 regmask=[rbx] minReg=1> LCL_VAR BB01 regmask=[rcx] minReg=1 last> IND BB01 regmask=[rbp] minReg=1> BB01 regmask=[rbp] minReg=1 last> STORE_LCL_VAR BB01 regmask=[rbp] minReg=1> LCL_VAR BB02 regmask=[rbx] minReg=1> BB03 regmask=[rcx] minReg=1> LCL_VAR BB03 regmask=[rcx] minReg=1 copy fixed> BB03 regmask=[rcx] minReg=1> PUTARG_REG BB03 regmask=[rcx] minReg=1 fixed> LCL_VAR BB03 regmask=[rsi] minReg=1 last> IND BB03 regmask=[rax] minReg=1> BB03 regmask=[rax] minReg=1 last> IND BB03 regmask=[rax] minReg=1> BB03 regmask=[rcx] minReg=1> BB03 regmask=[rcx] minReg=1 last fixed> BB03 regmask=[rax] minReg=1 last> BB03 regmask=[rax] minReg=1 last> BB03 regmask=[rcx] minReg=1 last> BB03 regmask=[rdx] minReg=1 last> BB03 regmask=[r8] minReg=1 last> BB03 regmask=[r9] minReg=1 last> BB03 regmask=[r10] minReg=1 last> BB03 regmask=[r11] minReg=1 last> BB03 regmask=[rax] minReg=1> CALL BB03 regmask=[rax] minReg=1 fixed> LCL_VAR BB03 regmask=[rdi] minReg=1 last> BB03 regmask=[rax] minReg=1 last> CNS_INT BB03 regmask=[rax] minReg=1> BB03 regmask=[rax] minReg=1> BB03 regmask=[rax] minReg=1 last fixed> BB04 regmask=[rcx] minReg=1> LCL_VAR BB04 regmask=[rcx] minReg=1 copy fixed> BB04 regmask=[rcx] minReg=1> PUTARG_REG BB04 regmask=[rcx] minReg=1 fixed> LCL_VAR BB04 regmask=[rsi] minReg=1> IND BB04 regmask=[rax] minReg=1> BB04 regmask=[rax] minReg=1 last> IND BB04 regmask=[rax] minReg=1> BB04 regmask=[rcx] minReg=1> BB04 regmask=[rcx] minReg=1 last fixed> BB04 regmask=[rax] minReg=1 last> BB04 regmask=[rax] minReg=1 last> BB04 regmask=[rcx] minReg=1 last> BB04 regmask=[rdx] minReg=1 last> BB04 regmask=[r8] minReg=1 last> BB04 regmask=[r9] minReg=1 last> BB04 regmask=[r10] minReg=1 last> BB04 regmask=[r11] minReg=1 last> BB04 regmask=[rax] minReg=1> CALL BB04 regmask=[rax] minReg=1 fixed> BB04 regmask=[rax] minReg=1 last> ADD BB04 regmask=[rax] minReg=1> BB04 regmask=[rax] minReg=1 last> CAST BB04 regmask=[r14] minReg=1> BB04 regmask=[r14] minReg=1 last> ADD BB04 regmask=[r14] minReg=1> BB04 regmask=[r14] minReg=1 last> STORE_LCL_VAR BB04 regmask=[r14] minReg=1> LCL_VAR BB04 regmask=[rbp] minReg=1> STORE_LCL_VAR BB04 regmask=[rcx] minReg=1> LCL_VAR BB04 regmask=[rcx] minReg=1 last regOptional> LCL_VAR BB05 regmask=[rbp] minReg=1> STORE_LCL_VAR BB05 regmask=[r15] minReg=1> CNS_INT BB06 regmask=[r15] minReg=1> BB06 regmask=[r15] minReg=1 last> STORE_LCL_VAR BB06 regmask=[r15] minReg=1> LCL_VAR BB07 regmask=[r15] minReg=1 last> STORE_LCL_VAR BB07 regmask=[r15] minReg=1> LCL_VAR BB07 regmask=[rbx] minReg=1> IND BB07 regmask=[r12] minReg=1> BB07 regmask=[r12] minReg=1 last> STORE_LCL_VAR BB07 regmask=[r12] minReg=1> LCL_VAR BB07 regmask=[r15] minReg=1> LCL_VAR BB07 regmask=[r12] minReg=1 regOptional> LCL_VAR BB08 regmask=[r12] minReg=1 last> STORE_LCL_VAR BB08 regmask=[r12] minReg=1> LCL_VAR BB09 regmask=[r15] minReg=1> STORE_LCL_VAR BB09 regmask=[r12] minReg=1> LCL_VAR BB10 regmask=[r15] minReg=1 last> LCL_VAR BB10 regmask=[r12] minReg=1 delay regOptional> SUB BB10 regmask=[r15] minReg=1> BB10 regmask=[r15] minReg=1 last> STORE_LCL_VAR BB10 regmask=[r15] minReg=1> LCL_VAR BB10 regmask=[r12] minReg=1 last> STORE_LCL_VAR BB10 regmask=[r12] minReg=1> LCL_VAR BB10 regmask=[rbx] minReg=1> IND BB10 regmask=[r13] minReg=1> BB10 regmask=[r13] minReg=1 last> STORE_LCL_VAR BB10 regmask=[r13] minReg=1> LCL_VAR BB10 regmask=[r13] minReg=1> LCL_VAR BB10 regmask=[r12] minReg=1 delay regOptional> SUB BB10 regmask=[rax] minReg=1> BB10 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB10 regmask=[rax] minReg=1 spillAfter> LCL_VAR_ADDR BB10 regmask=[rcx] minReg=1> BB10 regmask=[rcx] minReg=1 last> STORE_LCL_VAR BB10 regmask=[rcx] minReg=1> LCL_VAR_ADDR BB10 regmask=[rdx] minReg=1> BB10 regmask=[rdx] minReg=1 last> STORE_LCL_VAR BB10 regmask=[rdx] minReg=1> LCL_VAR BB10 regmask=[rdx] minReg=1> LCL_VAR BB10 regmask=[rbx] minReg=1> LCL_VAR BB10 regmask=[rdx] minReg=1 last> LCL_VAR BB10 regmask=[rbp] minReg=1> BB10 regmask=[rcx] minReg=1> LCL_VAR BB10 regmask=[rcx] minReg=1 last fixed> BB10 regmask=[rcx] minReg=1> PUTARG_REG BB10 regmask=[rcx] minReg=1 fixed> LCL_VAR_ADDR BB10 regmask=[rdx] minReg=1> BB10 regmask=[rdx] minReg=1> BB10 regmask=[rdx] minReg=1 last fixed> BB10 regmask=[rdx] minReg=1> PUTARG_REG BB10 regmask=[rdx] minReg=1 fixed> BB10 regmask=[r9] minReg=1> LCL_VAR BB10 regmask=[r9] minReg=1 copy fixed> BB10 regmask=[r9] minReg=1> PUTARG_REG BB10 regmask=[r9] minReg=1 fixed> CNS_INT BB10 regmask=[r8] minReg=1> BB10 regmask=[r8] minReg=1> BB10 regmask=[r8] minReg=1 last fixed> BB10 regmask=[r8] minReg=1> PUTARG_REG BB10 regmask=[r8] minReg=1 fixed> BB10 regmask=[rcx] minReg=1> BB10 regmask=[rcx] minReg=1 last fixed> BB10 regmask=[rdx] minReg=1> BB10 regmask=[rdx] minReg=1 last fixed> BB10 regmask=[r9] minReg=1> BB10 regmask=[r9] minReg=1 last fixed> BB10 regmask=[r8] minReg=1> BB10 regmask=[r8] minReg=1 last fixed> BB10 regmask=[rax] minReg=1 last> BB10 regmask=[rcx] minReg=1 last> BB10 regmask=[rdx] minReg=1 last> BB10 regmask=[r8] minReg=1 last> BB10 regmask=[r9] minReg=1 last> BB10 regmask=[r10] minReg=1 last> BB10 regmask=[r11] minReg=1 last> LCL_VAR BB10 regmask=[r15] minReg=1 regOptional> BB11 regmask=[rcx] minReg=1> LCL_VAR BB11 regmask=[rcx] minReg=1 copy fixed> BB11 regmask=[rcx] minReg=1> PUTARG_REG BB11 regmask=[rcx] minReg=1 fixed> BB11 regmask=[rcx] minReg=1> BB11 regmask=[rcx] minReg=1 last fixed> BB11 regmask=[rax] minReg=1 last> BB11 regmask=[rcx] minReg=1 last> BB11 regmask=[rdx] minReg=1 last> BB11 regmask=[r8] minReg=1 last> BB11 regmask=[r9] minReg=1 last> BB11 regmask=[r10] minReg=1 last> BB11 regmask=[r11] minReg=1 last> BB11 regmask=[rax] minReg=1> CALL BB11 regmask=[rax] minReg=1 fixed> BB11 regmask=[rax] minReg=1 last> CAST BB11 regmask=[rcx] minReg=1> LCL_VAR BB11 regmask=[r15] minReg=1> CAST BB11 regmask=[rax] minReg=1> BB11 regmask=[rcx] minReg=1 last regOptional> BB11 regmask=[rax] minReg=1 last> BB12 regmask=[rcx] minReg=1> LCL_VAR BB12 regmask=[rcx] minReg=1 copy fixed> BB12 regmask=[rcx] minReg=1> PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed> LCL_VAR BB12 regmask=[rsi] minReg=1 last> IND BB12 regmask=[rax] minReg=1> BB12 regmask=[rax] minReg=1 last> IND BB12 regmask=[rax] minReg=1> BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> BB12 regmask=[rax] minReg=1 last> BB12 regmask=[rax] minReg=1 last> BB12 regmask=[rcx] minReg=1 last> BB12 regmask=[rdx] minReg=1 last> BB12 regmask=[r8] minReg=1 last> BB12 regmask=[r9] minReg=1 last> BB12 regmask=[r10] minReg=1 last> BB12 regmask=[r11] minReg=1 last> BB12 regmask=[rax] minReg=1> CALL BB12 regmask=[rax] minReg=1 fixed> LCL_VAR BB12 regmask=[rdi] minReg=1 last> BB12 regmask=[rax] minReg=1 last> CNS_INT BB12 regmask=[rax] minReg=1> BB12 regmask=[rax] minReg=1> BB12 regmask=[rax] minReg=1 last fixed> LCL_VAR_ADDR BB13 regmask=[rcx] minReg=1> BB13 regmask=[rcx] minReg=1> BB13 regmask=[rcx] minReg=1 last fixed> BB13 regmask=[rcx] minReg=1> PUTARG_REG BB13 regmask=[rcx] minReg=1 fixed> BB13 regmask=[rdx] minReg=1> LCL_VAR BB13 regmask=[rdx] minReg=1 last copy fixed> BB13 regmask=[rdx] minReg=1> PUTARG_REG BB13 regmask=[rdx] minReg=1 fixed> BB13 regmask=[rcx] minReg=1> BB13 regmask=[rcx] minReg=1 last fixed> BB13 regmask=[rdx] minReg=1> BB13 regmask=[rdx] minReg=1 last fixed> BB13 regmask=[rax] minReg=1 last> BB13 regmask=[rcx] minReg=1 last> BB13 regmask=[rdx] minReg=1 last> BB13 regmask=[r8] minReg=1 last> BB13 regmask=[r9] minReg=1 last> BB13 regmask=[r10] minReg=1 last> BB13 regmask=[r11] minReg=1 last> LCL_VAR_ADDR BB14 regmask=[rcx] minReg=1> BB14 regmask=[rcx] minReg=1 last> STORE_LCL_VAR BB14 regmask=[rcx] minReg=1> LCL_VAR BB14 regmask=[rdx] minReg=1> LCL_VAR BB14 regmask=[rcx] minReg=1> BB14 regmask=[rdx] minReg=1 last> LCL_VAR BB14 regmask=[rdx] minReg=1> LCL_VAR BB14 regmask=[rcx] minReg=1 last> BB14 regmask=[rdx] minReg=1 last> LCL_VAR_ADDR BB14 regmask=[rcx] minReg=1> BB14 regmask=[rcx] minReg=1> BB14 regmask=[rcx] minReg=1 last fixed> BB14 regmask=[rcx] minReg=1> PUTARG_REG BB14 regmask=[rcx] minReg=1 fixed> LCL_VAR_ADDR BB14 regmask=[rdx] minReg=1> BB14 regmask=[rdx] minReg=1> BB14 regmask=[rdx] minReg=1 last fixed> BB14 regmask=[rdx] minReg=1> PUTARG_REG BB14 regmask=[rdx] minReg=1 fixed> BB14 regmask=[rcx] minReg=1> BB14 regmask=[rcx] minReg=1 last fixed> BB14 regmask=[rdx] minReg=1> BB14 regmask=[rdx] minReg=1 last fixed> BB14 regmask=[rax] minReg=1 last> BB14 regmask=[rcx] minReg=1 last> BB14 regmask=[rdx] minReg=1 last> BB14 regmask=[r8] minReg=1 last> BB14 regmask=[r9] minReg=1 last> BB14 regmask=[r10] minReg=1 last> BB14 regmask=[r11] minReg=1 last> BB14 regmask=[rax] minReg=1> CALL BB14 regmask=[rax] minReg=1 fixed> BB14 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB14 regmask=[r15] minReg=1> LCL_VAR BB14 regmask=[r15] minReg=1> LCL_VAR BB14 regmask=[r14] minReg=1 regOptional> LCL_VAR BB15 regmask=[rax] minReg=1 reload regOptional> LCL_VAR BB16 regmask=[rdi] minReg=1 last> LCL_VAR BB16 regmask=[rax] minReg=1 last regOptional> NE BB16 regmask=[r8] minReg=1> BB16 regmask=[r8] minReg=1> BB16 regmask=[r8] minReg=1 last fixed> BB16 regmask=[r8] minReg=1> PUTARG_REG BB16 regmask=[r8] minReg=1 fixed> LCL_VAR BB16 regmask=[rcx] minReg=1> BB16 regmask=[rcx] minReg=1> BB16 regmask=[rcx] minReg=1 last fixed> BB16 regmask=[rcx] minReg=1> PUTARG_REG BB16 regmask=[rcx] minReg=1 fixed> BB16 regmask=[rdx] minReg=1> LCL_VAR BB16 regmask=[rdx] minReg=1 last copy fixed> BB16 regmask=[rdx] minReg=1> PUTARG_REG BB16 regmask=[rdx] minReg=1 fixed> BB16 regmask=[r9] minReg=1> LCL_VAR BB16 regmask=[r9] minReg=1 last copy fixed> BB16 regmask=[r9] minReg=1> PUTARG_REG BB16 regmask=[r9] minReg=1 fixed> BB16 regmask=[r8] minReg=1> BB16 regmask=[r8] minReg=1 last fixed> BB16 regmask=[rcx] minReg=1> BB16 regmask=[rcx] minReg=1 last fixed> BB16 regmask=[rdx] minReg=1> BB16 regmask=[rdx] minReg=1 last fixed> BB16 regmask=[r9] minReg=1> BB16 regmask=[r9] minReg=1 last fixed> BB16 regmask=[rax] minReg=1 last> BB16 regmask=[rcx] minReg=1 last> BB16 regmask=[rdx] minReg=1 last> BB16 regmask=[r8] minReg=1 last> BB16 regmask=[r9] minReg=1 last> BB16 regmask=[r10] minReg=1 last> BB16 regmask=[r11] minReg=1 last> BB16 regmask=[rax] minReg=1> CALL BB16 regmask=[rax] minReg=1 fixed> BB16 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB16 regmask=[rax] minReg=1> LCL_VAR BB17 regmask=[rbp] minReg=1 regOptional> LCL_VAR BB18 regmask=[rax] minReg=1 last reload> STORE_LCL_VAR BB18 regmask=[rdx] minReg=1> LCL_VAR BB19 regmask=[rax] minReg=1 last> LCL_VAR BB19 regmask=[rbp] minReg=1 delay regOptional> SUB BB19 regmask=[rdx] minReg=1> BB19 regmask=[rdx] minReg=1 last> STORE_LCL_VAR BB19 regmask=[rdx] minReg=1> LCL_VAR BB20 regmask=[rdx] minReg=1 last> STORE_LCL_VAR BB20 regmask=[rax] minReg=1> LCL_VAR BB20 regmask=[r15] minReg=1 regOptional> LCL_VAR BB21 regmask=[rbx] minReg=1> IND BB21 regmask=[rcx] minReg=1> BB21 regmask=[rcx] minReg=1 last> CAST BB21 regmask=[rcx] minReg=1> LCL_VAR BB21 regmask=[rax] minReg=1 spillAfter> CAST BB21 regmask=[rdx] minReg=1> BB21 regmask=[rdx] minReg=1 last> BB21 regmask=[rcx] minReg=1 last delay regOptional> SUB BB21 regmask=[rdx] minReg=1> BB21 regmask=[rdx] minReg=1 last> STORE_LCL_VAR BB21 regmask=[rdx] minReg=1 spillAfter> BB21 regmask=[rcx] minReg=1> LCL_VAR BB21 regmask=[rcx] minReg=1 copy fixed> BB21 regmask=[rcx] minReg=1> PUTARG_REG BB21 regmask=[rcx] minReg=1 fixed> BB21 regmask=[rcx] minReg=1> BB21 regmask=[rcx] minReg=1 last fixed> BB21 regmask=[rax] minReg=1 last> BB21 regmask=[rcx] minReg=1 last> BB21 regmask=[rdx] minReg=1 last> BB21 regmask=[r8] minReg=1 last> BB21 regmask=[r9] minReg=1 last> BB21 regmask=[r10] minReg=1 last> BB21 regmask=[r11] minReg=1 last> BB21 regmask=[rax] minReg=1> CALL BB21 regmask=[rax] minReg=1 fixed> BB21 regmask=[rax] minReg=1 last> CAST BB21 regmask=[rcx] minReg=1> BB21 regmask=[rcx] minReg=1 last> LCL_VAR BB21 regmask=[] minReg=1 last regOptional> BB22 regmask=[rcx] minReg=1> LCL_VAR BB22 regmask=[rcx] minReg=1 copy fixed> BB22 regmask=[rcx] minReg=1> PUTARG_REG BB22 regmask=[rcx] minReg=1 fixed> LCL_VAR BB22 regmask=[rsi] minReg=1 last> IND BB22 regmask=[rax] minReg=1> BB22 regmask=[rax] minReg=1 last> IND BB22 regmask=[rax] minReg=1> BB22 regmask=[rcx] minReg=1> BB22 regmask=[rcx] minReg=1 last fixed> BB22 regmask=[rax] minReg=1 last> BB22 regmask=[rax] minReg=1 last> BB22 regmask=[rcx] minReg=1 last> BB22 regmask=[rdx] minReg=1 last> BB22 regmask=[r8] minReg=1 last> BB22 regmask=[r9] minReg=1 last> BB22 regmask=[r10] minReg=1 last> BB22 regmask=[r11] minReg=1 last> BB22 regmask=[rax] minReg=1> CALL BB22 regmask=[rax] minReg=1 fixed> LCL_VAR BB22 regmask=[rdi] minReg=1 last> BB22 regmask=[rax] minReg=1 last> CNS_INT BB22 regmask=[rax] minReg=1> BB22 regmask=[rax] minReg=1> BB22 regmask=[rax] minReg=1 last fixed> LCL_VAR_ADDR BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last> STORE_LCL_VAR BB23 regmask=[rcx] minReg=1> LCL_VAR_ADDR BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last> STORE_LCL_VAR BB23 regmask=[rdx] minReg=1> LCL_VAR BB23 regmask=[rdx] minReg=1> LCL_VAR BB23 regmask=[rbx] minReg=1 last> LCL_VAR BB23 regmask=[rdx] minReg=1 last> LCL_VAR BB23 regmask=[rbp] minReg=1 last> BB23 regmask=[rcx] minReg=1> LCL_VAR BB23 regmask=[rcx] minReg=1 last fixed> BB23 regmask=[rcx] minReg=1> PUTARG_REG BB23 regmask=[rcx] minReg=1 fixed> LCL_VAR_ADDR BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last fixed> BB23 regmask=[rdx] minReg=1> PUTARG_REG BB23 regmask=[rdx] minReg=1 fixed> BB23 regmask=[r8] minReg=1> LCL_VAR BB23 regmask=[r8] minReg=1 last copy fixed> BB23 regmask=[r8] minReg=1> PUTARG_REG BB23 regmask=[r8] minReg=1 fixed> BB23 regmask=[r9] minReg=1> LCL_VAR BB23 regmask=[r9] minReg=1 last copy fixed> BB23 regmask=[r9] minReg=1> PUTARG_REG BB23 regmask=[r9] minReg=1 fixed> BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last fixed> BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last fixed> BB23 regmask=[r8] minReg=1> BB23 regmask=[r8] minReg=1 last fixed> BB23 regmask=[r9] minReg=1> BB23 regmask=[r9] minReg=1 last fixed> BB23 regmask=[rax] minReg=1 last> BB23 regmask=[rcx] minReg=1 last> BB23 regmask=[rdx] minReg=1 last> BB23 regmask=[r8] minReg=1 last> BB23 regmask=[r9] minReg=1 last> BB23 regmask=[r10] minReg=1 last> BB23 regmask=[r11] minReg=1 last> CNS_INT BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last fixed> BB23 regmask=[rcx] minReg=1> PUTARG_REG BB23 regmask=[rcx] minReg=1 fixed> CNS_INT BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last fixed> BB23 regmask=[rdx] minReg=1> PUTARG_REG BB23 regmask=[rdx] minReg=1 fixed> BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last fixed> BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last fixed> BB23 regmask=[rax] minReg=1 last> BB23 regmask=[rcx] minReg=1 last> BB23 regmask=[rdx] minReg=1 last> BB23 regmask=[r8] minReg=1 last> BB23 regmask=[r9] minReg=1 last> BB23 regmask=[r10] minReg=1 last> BB23 regmask=[r11] minReg=1 last> BB23 regmask=[rax] minReg=1> CALL BB23 regmask=[rax] minReg=1 last fixed local> CNS_INT BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last> IND BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last> ADD BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last> STORE_LCL_VAR BB23 regmask=[rcx] minReg=1> LCL_VAR BB23 regmask=[rcx] minReg=1> IND BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last> LCL_VAR BB23 regmask=[rcx] minReg=1 last> IND BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last> LCL_VAR_ADDR BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last fixed> BB23 regmask=[rcx] minReg=1> PUTARG_REG BB23 regmask=[rcx] minReg=1 fixed> BB23 regmask=[rdx] minReg=1> LCL_VAR BB23 regmask=[rdx] minReg=1 last reload fixed> BB23 regmask=[rdx] minReg=1> PUTARG_REG BB23 regmask=[rdx] minReg=1 fixed> BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last fixed> BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last fixed> BB23 regmask=[rax] minReg=1 last> BB23 regmask=[rcx] minReg=1 last> BB23 regmask=[rdx] minReg=1 last> BB23 regmask=[r8] minReg=1 last> BB23 regmask=[r9] minReg=1 last> BB23 regmask=[r10] minReg=1 last> BB23 regmask=[r11] minReg=1 last> LCL_VAR BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last> STORE_LCL_VAR BB23 regmask=[rcx] minReg=1> LCL_VAR BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last> STORE_LCL_VAR BB23 regmask=[rdx] minReg=1> LCL_VAR_ADDR BB23 regmask=[rax] minReg=1> BB23 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB23 regmask=[rax] minReg=1> LCL_VAR BB23 regmask=[rax] minReg=1> LCL_VAR BB23 regmask=[rcx] minReg=1 last> LCL_VAR BB23 regmask=[rax] minReg=1 last> LCL_VAR BB23 regmask=[rdx] minReg=1 last> LCL_VAR_ADDR BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last fixed> BB23 regmask=[rcx] minReg=1> PUTARG_REG BB23 regmask=[rcx] minReg=1 fixed> LCL_VAR_ADDR BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last fixed> BB23 regmask=[rdx] minReg=1> PUTARG_REG BB23 regmask=[rdx] minReg=1 fixed> BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last fixed> BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last fixed> BB23 regmask=[rax] minReg=1 last> BB23 regmask=[rcx] minReg=1 last> BB23 regmask=[rdx] minReg=1 last> BB23 regmask=[r8] minReg=1 last> BB23 regmask=[r9] minReg=1 last> BB23 regmask=[r10] minReg=1 last> BB23 regmask=[r11] minReg=1 last> BB23 regmask=[rax] minReg=1> CALL BB23 regmask=[rax] minReg=1 fixed> BB23 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB23 regmask=[rbx] minReg=1> CNS_INT BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last> LCL_VAR BB23 regmask=[rbx] minReg=1 last> STORE_LCL_VAR BB23 regmask=[rbx] minReg=1> LCL_VAR BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last> STORE_LCL_VAR BB23 regmask=[rcx] minReg=1> LCL_VAR BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last> STORE_LCL_VAR BB23 regmask=[rdx] minReg=1> LCL_VAR_ADDR BB23 regmask=[rax] minReg=1> BB23 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB23 regmask=[rax] minReg=1> LCL_VAR BB23 regmask=[rax] minReg=1> LCL_VAR BB23 regmask=[rcx] minReg=1 last> LCL_VAR BB23 regmask=[rax] minReg=1 last> LCL_VAR BB23 regmask=[rdx] minReg=1 last> LCL_VAR_ADDR BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last fixed> BB23 regmask=[rcx] minReg=1> PUTARG_REG BB23 regmask=[rcx] minReg=1 fixed> LCL_VAR_ADDR BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last fixed> BB23 regmask=[rdx] minReg=1> PUTARG_REG BB23 regmask=[rdx] minReg=1 fixed> BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last fixed> BB23 regmask=[rdx] minReg=1> BB23 regmask=[rdx] minReg=1 last fixed> BB23 regmask=[rax] minReg=1 last> BB23 regmask=[rcx] minReg=1 last> BB23 regmask=[rdx] minReg=1 last> BB23 regmask=[r8] minReg=1 last> BB23 regmask=[r9] minReg=1 last> BB23 regmask=[r10] minReg=1 last> BB23 regmask=[r11] minReg=1 last> BB23 regmask=[rax] minReg=1> CALL BB23 regmask=[rax] minReg=1 fixed> BB23 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB23 regmask=[rax] minReg=1> CNS_INT BB23 regmask=[rcx] minReg=1> BB23 regmask=[rcx] minReg=1 last> LCL_VAR BB23 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB23 regmask=[rax] minReg=1> LCL_VAR BB23 regmask=[rax] minReg=1> LCL_VAR BB23 regmask=[rbx] minReg=1 regOptional> CNS_INT BB24 regmask=[rbp] minReg=1> BB24 regmask=[rbp] minReg=1 last> STORE_LCL_VAR BB24 regmask=[rbp] minReg=1> LCL_VAR BB25 regmask=[rax] minReg=1 last> LCL_VAR BB25 regmask=[rbx] minReg=1 last delay regOptional> SUB BB25 regmask=[rbp] minReg=1> BB25 regmask=[rbp] minReg=1 last> STORE_LCL_VAR BB25 regmask=[rbp] minReg=1> LCL_VAR BB26 regmask=[rbp] minReg=1 last> STORE_LCL_VAR BB26 regmask=[rbp] minReg=1> LCL_VAR BB26 regmask=[rbp] minReg=1 regOptional> LCL_VAR_ADDR BB27 regmask=[rcx] minReg=1> BB27 regmask=[rcx] minReg=1> BB27 regmask=[rcx] minReg=1 last fixed> BB27 regmask=[rcx] minReg=1> PUTARG_REG BB27 regmask=[rcx] minReg=1 fixed> BB27 regmask=[rdx] minReg=1> LCL_VAR BB27 regmask=[rdx] minReg=1 copy fixed> BB27 regmask=[rdx] minReg=1> PUTARG_REG BB27 regmask=[rdx] minReg=1 fixed> BB27 regmask=[rcx] minReg=1> BB27 regmask=[rcx] minReg=1 last fixed> BB27 regmask=[rdx] minReg=1> BB27 regmask=[rdx] minReg=1 last fixed> BB27 regmask=[rax] minReg=1 last> BB27 regmask=[rcx] minReg=1 last> BB27 regmask=[rdx] minReg=1 last> BB27 regmask=[r8] minReg=1 last> BB27 regmask=[r9] minReg=1 last> BB27 regmask=[r10] minReg=1 last> BB27 regmask=[r11] minReg=1 last> LCL_VAR BB28 regmask=[r14] minReg=1 last> LCL_VAR BB28 regmask=[r15] minReg=1 delay regOptional> SUB BB28 regmask=[r14] minReg=1> BB28 regmask=[r14] minReg=1 last> STORE_LCL_VAR BB28 regmask=[r14] minReg=1> LCL_VAR BB28 regmask=[r14] minReg=1> STORE_LCL_VAR BB28 regmask=[rbx] minReg=1> LCL_VAR BB28 regmask=[r15] minReg=1 regOptional> LCL_VAR BB29 regmask=[rbp] minReg=1> LCL_VAR BB29 regmask=[r14] minReg=1 regOptional> LCL_VAR BB30 regmask=[rdi] minReg=1 last> CNS_INT BB30 regmask=[r8] minReg=1> BB30 regmask=[r8] minReg=1> BB30 regmask=[r8] minReg=1 last fixed> BB30 regmask=[r8] minReg=1> PUTARG_REG BB30 regmask=[r8] minReg=1 fixed> LCL_VAR BB30 regmask=[rcx] minReg=1> BB30 regmask=[rcx] minReg=1> BB30 regmask=[rcx] minReg=1 last fixed> BB30 regmask=[rcx] minReg=1> PUTARG_REG BB30 regmask=[rcx] minReg=1 fixed> BB30 regmask=[rdx] minReg=1> LCL_VAR BB30 regmask=[rdx] minReg=1 last copy fixed> BB30 regmask=[rdx] minReg=1> PUTARG_REG BB30 regmask=[rdx] minReg=1 fixed> BB30 regmask=[r9] minReg=1> LCL_VAR BB30 regmask=[r9] minReg=1 last copy fixed> BB30 regmask=[r9] minReg=1> PUTARG_REG BB30 regmask=[r9] minReg=1 fixed> BB30 regmask=[r8] minReg=1> BB30 regmask=[r8] minReg=1 last fixed> BB30 regmask=[rcx] minReg=1> BB30 regmask=[rcx] minReg=1 last fixed> BB30 regmask=[rdx] minReg=1> BB30 regmask=[rdx] minReg=1 last fixed> BB30 regmask=[r9] minReg=1> BB30 regmask=[r9] minReg=1 last fixed> BB30 regmask=[rax] minReg=1 last> BB30 regmask=[rcx] minReg=1 last> BB30 regmask=[rdx] minReg=1 last> BB30 regmask=[r8] minReg=1 last> BB30 regmask=[r9] minReg=1 last> BB30 regmask=[r10] minReg=1 last> BB30 regmask=[r11] minReg=1 last> BB30 regmask=[rax] minReg=1> CALL BB30 regmask=[rax] minReg=1 fixed> BB30 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB30 regmask=[rax] minReg=1> LCL_VAR BB31 regmask=[r14] minReg=1> LCL_VAR BB31 regmask=[rbp] minReg=1 delay regOptional> SUB BB31 regmask=[rbx] minReg=1> BB31 regmask=[rbx] minReg=1 last> STORE_LCL_VAR BB31 regmask=[rbx] minReg=1> LCL_VAR BB32 regmask=[rcx] minReg=1> BB32 regmask=[rcx] minReg=1 last> LCL_VAR BB32 regmask=[rcx] minReg=1> BB32 regmask=[rcx] minReg=1 last> LCL_VAR BB32 regmask=[rcx] minReg=1> BB32 regmask=[rcx] minReg=1 last> STORE_LCL_VAR BB32 regmask=[rcx] minReg=1> LCL_VAR BB32 regmask=[rdx] minReg=1> BB32 regmask=[rdx] minReg=1 last> STORE_LCL_VAR BB32 regmask=[rdx] minReg=1> LCL_VAR_ADDR BB32 regmask=[rax] minReg=1> BB32 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB32 regmask=[rax] minReg=1> LCL_VAR_ADDR BB32 regmask=[r8] minReg=1> BB32 regmask=[r8] minReg=1 last> STORE_LCL_VAR BB32 regmask=[r8] minReg=1> LCL_VAR BB32 regmask=[r8] minReg=1> LCL_VAR BB32 regmask=[rcx] minReg=1 last> LCL_VAR BB32 regmask=[r8] minReg=1 last> LCL_VAR BB32 regmask=[rdx] minReg=1 last> BB32 regmask=[rcx] minReg=1> LCL_VAR BB32 regmask=[rcx] minReg=1 last copy fixed> BB32 regmask=[rcx] minReg=1> PUTARG_REG BB32 regmask=[rcx] minReg=1 fixed> LCL_VAR_ADDR BB32 regmask=[rdx] minReg=1> BB32 regmask=[rdx] minReg=1> BB32 regmask=[rdx] minReg=1 last fixed> BB32 regmask=[rdx] minReg=1> PUTARG_REG BB32 regmask=[rdx] minReg=1 fixed> BB32 regmask=[rcx] minReg=1> BB32 regmask=[rcx] minReg=1 last fixed> BB32 regmask=[rdx] minReg=1> BB32 regmask=[rdx] minReg=1 last fixed> BB32 regmask=[rax] minReg=1 last> BB32 regmask=[rcx] minReg=1 last> BB32 regmask=[rdx] minReg=1 last> BB32 regmask=[r8] minReg=1 last> BB32 regmask=[r9] minReg=1 last> BB32 regmask=[r10] minReg=1 last> BB32 regmask=[r11] minReg=1 last> BB32 regmask=[rax] minReg=1> CALL BB32 regmask=[rax] minReg=1 fixed> BB32 regmask=[rax] minReg=1 last regOptional> LCL_VAR BB33 regmask=[rbp] minReg=1 last> STORE_LCL_VAR BB33 regmask=[rbp] minReg=1> LCL_VAR BB34 regmask=[rbp] minReg=1 last> ADD BB34 regmask=[rbp] minReg=1> BB34 regmask=[rbp] minReg=1 last> STORE_LCL_VAR BB34 regmask=[rbp] minReg=1> LCL_VAR BB35 regmask=[rbp] minReg=1 last> STORE_LCL_VAR BB35 regmask=[rbp] minReg=1> LCL_VAR_ADDR BB35 regmask=[rcx] minReg=1> BB35 regmask=[rcx] minReg=1> BB35 regmask=[rcx] minReg=1 last fixed> BB35 regmask=[rcx] minReg=1> PUTARG_REG BB35 regmask=[rcx] minReg=1 fixed> BB35 regmask=[rdx] minReg=1> LCL_VAR BB35 regmask=[rdx] minReg=1 last copy fixed> BB35 regmask=[rdx] minReg=1> PUTARG_REG BB35 regmask=[rdx] minReg=1 fixed> BB35 regmask=[rcx] minReg=1> BB35 regmask=[rcx] minReg=1 last fixed> BB35 regmask=[rdx] minReg=1> BB35 regmask=[rdx] minReg=1 last fixed> BB35 regmask=[rax] minReg=1 last> BB35 regmask=[rcx] minReg=1 last> BB35 regmask=[rdx] minReg=1 last> BB35 regmask=[r8] minReg=1 last> BB35 regmask=[r9] minReg=1 last> BB35 regmask=[r10] minReg=1 last> BB35 regmask=[r11] minReg=1 last> LCL_VAR_ADDR BB35 regmask=[rcx] minReg=1> BB35 regmask=[rcx] minReg=1 last> STORE_LCL_VAR BB35 regmask=[rcx] minReg=1> LCL_VAR_ADDR BB35 regmask=[rdx] minReg=1> BB35 regmask=[rdx] minReg=1 last> STORE_LCL_VAR BB35 regmask=[rdx] minReg=1> LCL_VAR BB35 regmask=[r8] minReg=1> LCL_VAR BB35 regmask=[rdx] minReg=1> BB35 regmask=[r8] minReg=1 last> LCL_VAR BB35 regmask=[r8] minReg=1> LCL_VAR BB35 regmask=[rdx] minReg=1 last> BB35 regmask=[r8] minReg=1 last> LCL_VAR_ADDR BB35 regmask=[rdx] minReg=1> BB35 regmask=[rdx] minReg=1 last> STORE_LCL_VAR BB35 regmask=[rdx] minReg=1> LCL_VAR BB35 regmask=[r8] minReg=1> LCL_VAR BB35 regmask=[rdx] minReg=1> BB35 regmask=[r8] minReg=1 last> LCL_VAR BB35 regmask=[r8] minReg=1> LCL_VAR BB35 regmask=[rdx] minReg=1 last> BB35 regmask=[r8] minReg=1 last> BB35 regmask=[rcx] minReg=1> LCL_VAR BB35 regmask=[rcx] minReg=1 last fixed> BB35 regmask=[rcx] minReg=1> PUTARG_REG BB35 regmask=[rcx] minReg=1 fixed> LCL_VAR_ADDR BB35 regmask=[rdx] minReg=1> BB35 regmask=[rdx] minReg=1> BB35 regmask=[rdx] minReg=1 last fixed> BB35 regmask=[rdx] minReg=1> PUTARG_REG BB35 regmask=[rdx] minReg=1 fixed> LCL_VAR_ADDR BB35 regmask=[r8] minReg=1> BB35 regmask=[r8] minReg=1> BB35 regmask=[r8] minReg=1 last fixed> BB35 regmask=[r8] minReg=1> PUTARG_REG BB35 regmask=[r8] minReg=1 fixed> LCL_VAR_ADDR BB35 regmask=[r9] minReg=1> BB35 regmask=[r9] minReg=1> BB35 regmask=[r9] minReg=1 last fixed> BB35 regmask=[r9] minReg=1> PUTARG_REG BB35 regmask=[r9] minReg=1 fixed> BB35 regmask=[rcx] minReg=1> BB35 regmask=[rcx] minReg=1 last fixed> BB35 regmask=[rdx] minReg=1> BB35 regmask=[rdx] minReg=1 last fixed> BB35 regmask=[r8] minReg=1> BB35 regmask=[r8] minReg=1 last fixed> BB35 regmask=[r9] minReg=1> BB35 regmask=[r9] minReg=1 last fixed> BB35 regmask=[rax] minReg=1 last> BB35 regmask=[rcx] minReg=1 last> BB35 regmask=[rdx] minReg=1 last> BB35 regmask=[r8] minReg=1 last> BB35 regmask=[r9] minReg=1 last> BB35 regmask=[r10] minReg=1 last> BB35 regmask=[r11] minReg=1 last> LCL_VAR_ADDR BB35 regmask=[rcx] minReg=1> BB35 regmask=[rcx] minReg=1 last> STORE_LCL_VAR BB35 regmask=[rcx] minReg=1> LCL_VAR BB35 regmask=[rax] minReg=1> LCL_VAR BB35 regmask=[rcx] minReg=1> BB35 regmask=[rax] minReg=1 last> LCL_VAR BB35 regmask=[rax] minReg=1> LCL_VAR BB35 regmask=[rcx] minReg=1 last> BB35 regmask=[rax] minReg=1 last> LCL_VAR_ADDR BB35 regmask=[rcx] minReg=1> BB35 regmask=[rcx] minReg=1> BB35 regmask=[rcx] minReg=1 last fixed> BB35 regmask=[rcx] minReg=1> PUTARG_REG BB35 regmask=[rcx] minReg=1 fixed> BB35 regmask=[rcx] minReg=1> BB35 regmask=[rcx] minReg=1 last fixed> BB35 regmask=[rax] minReg=1 last> BB35 regmask=[rcx] minReg=1 last> BB35 regmask=[rdx] minReg=1 last> BB35 regmask=[r8] minReg=1 last> BB35 regmask=[r9] minReg=1 last> BB35 regmask=[r10] minReg=1 last> BB35 regmask=[r11] minReg=1 last> BB35 regmask=[rax] minReg=1> CALL BB35 regmask=[rax] minReg=1 fixed> BB35 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB35 regmask=[rbx] minReg=1> EQ BB35 regmask=[r12] minReg=1> BB35 regmask=[r12] minReg=1 last> STORE_LCL_VAR BB35 regmask=[r12] minReg=1> BB35 regmask=[rcx] minReg=1> LCL_VAR BB35 regmask=[rcx] minReg=1 copy fixed> BB35 regmask=[rcx] minReg=1> PUTARG_REG BB35 regmask=[rcx] minReg=1 fixed> BB35 regmask=[rcx] minReg=1> BB35 regmask=[rcx] minReg=1 last fixed> BB35 regmask=[rax] minReg=1 last> BB35 regmask=[rcx] minReg=1 last> BB35 regmask=[rdx] minReg=1 last> BB35 regmask=[r8] minReg=1 last> BB35 regmask=[r9] minReg=1 last> BB35 regmask=[r10] minReg=1 last> BB35 regmask=[r11] minReg=1 last> BB35 regmask=[rax] minReg=1> CALL BB35 regmask=[rax] minReg=1 fixed> BB35 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB35 regmask=[rax] minReg=1> LCL_VAR BB35 regmask=[rax] minReg=1 regOptional> LCL_VAR BB35 regmask=[r14] minReg=1> LCL_VAR BB36 regmask=[rax] minReg=1 last> LCL_VAR BB36 regmask=[r14] minReg=1 delay regOptional> SUB BB36 regmask=[rax] minReg=1> BB36 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB36 regmask=[rax] minReg=1> LCL_VAR BB36 regmask=[r12] minReg=1 last regOptional> CNS_INT BB37 regmask=[rdx] minReg=1> BB37 regmask=[rdx] minReg=1 last> BB37 regmask=[rcx] minReg=1> LCL_VAR BB37 regmask=[rcx] minReg=1 copy fixed delay> BB37 regmask=[rcx] minReg=1 last> LSH BB37 regmask=[rdx] minReg=1> BB37 regmask=[rdx] minReg=1 last> ADD BB37 regmask=[rdx] minReg=1> LCL_VAR BB37 regmask=[rbx] minReg=1 regOptional> BB37 regmask=[rdx] minReg=1 last> TEST_EQ BB37 regmask=[rcx] minReg=1> BB37 regmask=[rcx] minReg=1 last> STORE_LCL_VAR BB37 regmask=[rcx] minReg=1> CNS_INT BB38 regmask=[rcx] minReg=1> BB38 regmask=[rcx] minReg=1 last> STORE_LCL_VAR BB38 regmask=[rcx] minReg=1> LCL_VAR BB39 regmask=[rcx] minReg=1 last> CAST BB39 regmask=[r12] minReg=1> BB39 regmask=[r12] minReg=1 last> STORE_LCL_VAR BB39 regmask=[r12] minReg=1> LCL_VAR BB39 regmask=[rbx] minReg=1 last> BB39 regmask=[rcx] minReg=1> LCL_VAR BB39 regmask=[rcx] minReg=1 last copy fixed delay> BB39 regmask=[rcx] minReg=1 last> RSZ BB39 regmask=[rbx] minReg=1> BB39 regmask=[rbx] minReg=1 last> STORE_LCL_VAR BB39 regmask=[rbx] minReg=1> LCL_VAR_ADDR BB40 regmask=[rcx] minReg=1> BB40 regmask=[rcx] minReg=1 last> STORE_LCL_VAR BB40 regmask=[rcx] minReg=1> LCL_VAR BB40 regmask=[rax] minReg=1> LCL_VAR BB40 regmask=[rcx] minReg=1> BB40 regmask=[rax] minReg=1 last> LCL_VAR BB40 regmask=[rax] minReg=1> LCL_VAR BB40 regmask=[rcx] minReg=1 last> BB40 regmask=[rax] minReg=1 last> LCL_VAR_ADDR BB40 regmask=[rcx] minReg=1> BB40 regmask=[rcx] minReg=1> BB40 regmask=[rcx] minReg=1 last fixed> BB40 regmask=[rcx] minReg=1> PUTARG_REG BB40 regmask=[rcx] minReg=1 fixed> BB40 regmask=[rcx] minReg=1> BB40 regmask=[rcx] minReg=1 last fixed> BB40 regmask=[rax] minReg=1 last> BB40 regmask=[rcx] minReg=1 last> BB40 regmask=[rdx] minReg=1 last> BB40 regmask=[r8] minReg=1 last> BB40 regmask=[r9] minReg=1 last> BB40 regmask=[r10] minReg=1 last> BB40 regmask=[r11] minReg=1 last> BB40 regmask=[rax] minReg=1> CALL BB40 regmask=[rax] minReg=1 fixed> BB40 regmask=[rax] minReg=1 last> BB40 regmask=[rcx] minReg=1> LCL_VAR BB40 regmask=[rcx] minReg=1 last copy fixed delay> BB40 regmask=[rcx] minReg=1 last> LSH BB40 regmask=[rax] minReg=1> BB40 regmask=[rax] minReg=1 last> LCL_VAR BB40 regmask=[rbx] minReg=1 last regOptional> ADD BB40 regmask=[rdx] minReg=1> BB40 regmask=[rdx] minReg=1 last> STORE_LCL_VAR BB40 regmask=[rdx] minReg=1> LCL_VAR BB40 regmask=[r15] minReg=1 regOptional> LCL_VAR BB41 regmask=[rbp] minReg=1 last> NEG BB41 regmask=[r8] minReg=1> BB41 regmask=[r8] minReg=1 last> ADD BB41 regmask=[r8] minReg=1> BB41 regmask=[r8] minReg=1 last> STORE_LCL_VAR BB41 regmask=[r8] minReg=1> LCL_VAR BB42 regmask=[r15] minReg=1 last> ADD BB42 regmask=[r8] minReg=1> BB42 regmask=[r8] minReg=1 last> STORE_LCL_VAR BB42 regmask=[r8] minReg=1> LCL_VAR BB43 regmask=[rdi] minReg=1 last> BB43 regmask=[rcx] minReg=1> LCL_VAR BB43 regmask=[rcx] minReg=1 last copy fixed> BB43 regmask=[rcx] minReg=1> PUTARG_REG BB43 regmask=[rcx] minReg=1 fixed> BB43 regmask=[rdx] minReg=1> LCL_VAR BB43 regmask=[rdx] minReg=1 last fixed> BB43 regmask=[rdx] minReg=1> PUTARG_REG BB43 regmask=[rdx] minReg=1 fixed> BB43 regmask=[r8] minReg=1> LCL_VAR BB43 regmask=[r8] minReg=1 last fixed> BB43 regmask=[r8] minReg=1> PUTARG_REG BB43 regmask=[r8] minReg=1 fixed> BB43 regmask=[r9] minReg=1> LCL_VAR BB43 regmask=[r9] minReg=1 last copy fixed> BB43 regmask=[r9] minReg=1> PUTARG_REG BB43 regmask=[r9] minReg=1 fixed> BB43 regmask=[rcx] minReg=1> BB43 regmask=[rcx] minReg=1 last fixed> BB43 regmask=[rdx] minReg=1> BB43 regmask=[rdx] minReg=1 last fixed> BB43 regmask=[r8] minReg=1> BB43 regmask=[r8] minReg=1 last fixed> BB43 regmask=[r9] minReg=1> BB43 regmask=[r9] minReg=1 last fixed> BB43 regmask=[rax] minReg=1 last> BB43 regmask=[rcx] minReg=1 last> BB43 regmask=[rdx] minReg=1 last> BB43 regmask=[r8] minReg=1 last> BB43 regmask=[r9] minReg=1 last> BB43 regmask=[r10] minReg=1 last> BB43 regmask=[r11] minReg=1 last> BB43 regmask=[rax] minReg=1> CALL BB43 regmask=[rax] minReg=1 fixed> BB43 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB43 regmask=[rax] minReg=1> BB44 regmask=[rax] minReg=1> LCL_VAR BB44 regmask=[rax] minReg=1 last fixed> VAR REFPOSITIONS AFTER ALLOCATION --- V00 (Interval 0) BB00 regmask=[rcx] minReg=1 fixed regOptional> LCL_VAR BB01 regmask=[rcx] minReg=1> LCL_VAR BB01 regmask=[rcx] minReg=1 last> --- V01 (Interval 1) BB00 regmask=[rsi] minReg=1 fixed regOptional> LCL_VAR BB03 regmask=[rcx] minReg=1 copy fixed> LCL_VAR BB03 regmask=[rsi] minReg=1 last> LCL_VAR BB04 regmask=[rcx] minReg=1 copy fixed> LCL_VAR BB04 regmask=[rsi] minReg=1> LCL_VAR BB11 regmask=[rcx] minReg=1 copy fixed> LCL_VAR BB12 regmask=[rcx] minReg=1 copy fixed> LCL_VAR BB12 regmask=[rsi] minReg=1 last> LCL_VAR BB16 regmask=[r9] minReg=1 last copy fixed> LCL_VAR BB21 regmask=[rcx] minReg=1 copy fixed> LCL_VAR BB22 regmask=[rcx] minReg=1 copy fixed> LCL_VAR BB22 regmask=[rsi] minReg=1 last> LCL_VAR BB30 regmask=[r9] minReg=1 last copy fixed> LCL_VAR BB43 regmask=[rcx] minReg=1 last copy fixed> --- V02 (Interval 2) BB00 regmask=[rdi] minReg=1 fixed regOptional> LCL_VAR BB03 regmask=[rdi] minReg=1 last> LCL_VAR BB12 regmask=[rdi] minReg=1 last> LCL_VAR BB16 regmask=[rdi] minReg=1 last> LCL_VAR BB22 regmask=[rdi] minReg=1 last> LCL_VAR BB30 regmask=[rdi] minReg=1 last> LCL_VAR BB43 regmask=[rdi] minReg=1 last> --- V03 (Interval 3) STORE_LCL_VAR BB04 regmask=[r14] minReg=1> LCL_VAR BB14 regmask=[r14] minReg=1 regOptional> LCL_VAR BB28 regmask=[r14] minReg=1 last> --- V04 --- V05 (Interval 4) STORE_LCL_VAR BB10 regmask=[r15] minReg=1> LCL_VAR BB10 regmask=[r15] minReg=1 regOptional> LCL_VAR BB11 regmask=[r15] minReg=1> LCL_VAR BB13 regmask=[rdx] minReg=1 last copy fixed> --- V06 --- V07 --- V08 (Interval 5) STORE_LCL_VAR BB10 regmask=[r12] minReg=1> LCL_VAR BB10 regmask=[r12] minReg=1 delay regOptional> LCL_VAR BB10 regmask=[r9] minReg=1 copy fixed> LCL_VAR BB23 regmask=[r8] minReg=1 last copy fixed> --- V09 (Interval 6) STORE_LCL_VAR BB10 regmask=[r13] minReg=1> LCL_VAR BB10 regmask=[r13] minReg=1> LCL_VAR BB23 regmask=[r9] minReg=1 last copy fixed> --- V10 (Interval 7) STORE_LCL_VAR BB10 regmask=[rax] minReg=1 spillAfter> LCL_VAR BB15 regmask=[rax] minReg=1 reload regOptional> LCL_VAR BB16 regmask=[rax] minReg=1 last regOptional> LCL_VAR BB18 regmask=[rax] minReg=1 last reload> LCL_VAR BB19 regmask=[rax] minReg=1 last> --- V11 --- V12 --- V13 (Interval 8) STORE_LCL_VAR BB14 regmask=[r15] minReg=1> LCL_VAR BB14 regmask=[r15] minReg=1> LCL_VAR BB16 regmask=[rdx] minReg=1 last copy fixed> LCL_VAR BB20 regmask=[r15] minReg=1 regOptional> LCL_VAR BB28 regmask=[r15] minReg=1 delay regOptional> LCL_VAR BB28 regmask=[r15] minReg=1 regOptional> LCL_VAR BB30 regmask=[rdx] minReg=1 last copy fixed> LCL_VAR BB40 regmask=[r15] minReg=1 regOptional> LCL_VAR BB42 regmask=[r15] minReg=1 last> --- V14 (Interval 9) STORE_LCL_VAR BB20 regmask=[rax] minReg=1> LCL_VAR BB21 regmask=[rax] minReg=1 spillAfter> LCL_VAR BB23 regmask=[rdx] minReg=1 last reload fixed> --- V15 --- V16 --- V17 (Interval 10) STORE_LCL_VAR BB23 regmask=[rbx] minReg=1> LCL_VAR BB23 regmask=[rbx] minReg=1 regOptional> LCL_VAR BB25 regmask=[rbx] minReg=1 last delay regOptional> --- V18 (Interval 11) STORE_LCL_VAR BB23 regmask=[rax] minReg=1> LCL_VAR BB23 regmask=[rax] minReg=1> LCL_VAR BB25 regmask=[rax] minReg=1 last> --- V19 (Interval 12) STORE_LCL_VAR BB26 regmask=[rbp] minReg=1> LCL_VAR BB26 regmask=[rbp] minReg=1 regOptional> LCL_VAR BB27 regmask=[rdx] minReg=1 copy fixed> LCL_VAR BB29 regmask=[rbp] minReg=1> LCL_VAR BB31 regmask=[rbp] minReg=1 delay regOptional> LCL_VAR BB33 regmask=[rbp] minReg=1 last> LCL_VAR BB34 regmask=[rbp] minReg=1 last> --- V20 (Interval 13) STORE_LCL_VAR BB28 regmask=[r14] minReg=1> LCL_VAR BB28 regmask=[r14] minReg=1> LCL_VAR BB29 regmask=[r14] minReg=1 regOptional> LCL_VAR BB31 regmask=[r14] minReg=1> LCL_VAR BB35 regmask=[r14] minReg=1> LCL_VAR BB36 regmask=[r14] minReg=1 delay regOptional> LCL_VAR BB40 regmask=[rcx] minReg=1 last copy fixed delay> --- V21 (Interval 14) STORE_LCL_VAR BB28 regmask=[rbx] minReg=1> STORE_LCL_VAR BB31 regmask=[rbx] minReg=1> LCL_VAR BB35 regmask=[rdx] minReg=1 last copy fixed> --- V22 (Interval 15) STORE_LCL_VAR BB35 regmask=[rbp] minReg=1> LCL_VAR BB41 regmask=[rbp] minReg=1 last> --- V23 --- V24 (Interval 16) STORE_LCL_VAR BB35 regmask=[rbx] minReg=1> LCL_VAR BB35 regmask=[rcx] minReg=1 copy fixed> LCL_VAR BB37 regmask=[rbx] minReg=1 regOptional> LCL_VAR BB39 regmask=[rbx] minReg=1 last> STORE_LCL_VAR BB39 regmask=[rbx] minReg=1> LCL_VAR BB40 regmask=[rbx] minReg=1 last regOptional> --- V25 (Interval 17) STORE_LCL_VAR BB35 regmask=[r12] minReg=1> LCL_VAR BB36 regmask=[r12] minReg=1 last regOptional> STORE_LCL_VAR BB39 regmask=[r12] minReg=1> LCL_VAR BB43 regmask=[r9] minReg=1 last copy fixed> --- V26 (Interval 18) STORE_LCL_VAR BB35 regmask=[rax] minReg=1> LCL_VAR BB35 regmask=[rax] minReg=1 regOptional> LCL_VAR BB36 regmask=[rax] minReg=1 last> --- V27 (Interval 19) STORE_LCL_VAR BB40 regmask=[rdx] minReg=1> LCL_VAR BB43 regmask=[rdx] minReg=1 last fixed> --- V28 --- V29 (Interval 20) STORE_LCL_VAR BB36 regmask=[rax] minReg=1> LCL_VAR BB37 regmask=[rcx] minReg=1 copy fixed delay> LCL_VAR BB39 regmask=[rcx] minReg=1 last copy fixed delay> --- V30 --- V31 (Interval 21) STORE_LCL_VAR BB07 regmask=[r15] minReg=1> LCL_VAR BB07 regmask=[r15] minReg=1> LCL_VAR BB09 regmask=[r15] minReg=1> LCL_VAR BB10 regmask=[r15] minReg=1 last> --- V32 (Interval 22) STORE_LCL_VAR BB18 regmask=[rdx] minReg=1> STORE_LCL_VAR BB19 regmask=[rdx] minReg=1> LCL_VAR BB20 regmask=[rdx] minReg=1 last> --- V33 (Interval 23) STORE_LCL_VAR BB24 regmask=[rbp] minReg=1> STORE_LCL_VAR BB25 regmask=[rbp] minReg=1> LCL_VAR BB26 regmask=[rbp] minReg=1 last> --- V34 (Interval 24) STORE_LCL_VAR BB33 regmask=[rbp] minReg=1> STORE_LCL_VAR BB34 regmask=[rbp] minReg=1> LCL_VAR BB35 regmask=[rbp] minReg=1 last> --- V35 --- V36 (Interval 25) STORE_LCL_VAR BB41 regmask=[r8] minReg=1> STORE_LCL_VAR BB42 regmask=[r8] minReg=1> LCL_VAR BB43 regmask=[r8] minReg=1 last fixed> --- V37 (Interval 26) STORE_LCL_VAR BB37 regmask=[rcx] minReg=1> STORE_LCL_VAR BB38 regmask=[rcx] minReg=1> LCL_VAR BB39 regmask=[rcx] minReg=1 last> --- V38 (Interval 27) STORE_LCL_VAR BB21 regmask=[rdx] minReg=1 spillAfter> LCL_VAR BB21 regmask=[] minReg=1 last regOptional> --- V39 (Interval 28) STORE_LCL_VAR BB05 regmask=[r15] minReg=1> STORE_LCL_VAR BB06 regmask=[r15] minReg=1> LCL_VAR BB07 regmask=[r15] minReg=1 last> --- V40 (Interval 29) STORE_LCL_VAR BB04 regmask=[rcx] minReg=1> LCL_VAR BB04 regmask=[rcx] minReg=1 last regOptional> --- V41 (Interval 30) STORE_LCL_VAR BB08 regmask=[r12] minReg=1> STORE_LCL_VAR BB09 regmask=[r12] minReg=1> LCL_VAR BB10 regmask=[r12] minReg=1 delay regOptional> LCL_VAR BB10 regmask=[r12] minReg=1 last> --- V42 (Interval 31) STORE_LCL_VAR BB07 regmask=[r12] minReg=1> LCL_VAR BB07 regmask=[r12] minReg=1 regOptional> LCL_VAR BB08 regmask=[r12] minReg=1 last> --- V43 (Interval 32) STORE_LCL_VAR BB23 regmask=[rbx] minReg=1> LCL_VAR BB23 regmask=[rbx] minReg=1 last> --- V44 --- V45 --- V46 (Interval 33) STORE_LCL_VAR BB23 regmask=[rax] minReg=1> LCL_VAR BB23 regmask=[rax] minReg=1 last> --- V47 --- V48 --- V49 --- V50 --- V51 (Interval 34) STORE_LCL_VAR BB16 regmask=[rax] minReg=1> STORE_LCL_VAR BB30 regmask=[rax] minReg=1> STORE_LCL_VAR BB43 regmask=[rax] minReg=1> LCL_VAR BB44 regmask=[rax] minReg=1 last fixed> --- V52 (Interval 35) STORE_LCL_VAR BB01 regmask=[rbx] minReg=1> LCL_VAR BB02 regmask=[rbx] minReg=1> LCL_VAR BB07 regmask=[rbx] minReg=1> LCL_VAR BB10 regmask=[rbx] minReg=1> LCL_VAR BB10 regmask=[rbx] minReg=1> LCL_VAR BB21 regmask=[rbx] minReg=1> LCL_VAR BB23 regmask=[rbx] minReg=1 last> --- V53 (Interval 36) STORE_LCL_VAR BB01 regmask=[rbp] minReg=1> LCL_VAR BB04 regmask=[rbp] minReg=1> LCL_VAR BB05 regmask=[rbp] minReg=1> LCL_VAR BB10 regmask=[rbp] minReg=1> LCL_VAR BB17 regmask=[rbp] minReg=1 regOptional> LCL_VAR BB19 regmask=[rbp] minReg=1 delay regOptional> LCL_VAR BB23 regmask=[rbp] minReg=1 last> --- V54 --- V55 --- V56 --- V57 --- V58 --- V59 --- V60 --- V61 --- V62 --- V63 --- V64 (Interval 37) STORE_LCL_VAR BB23 regmask=[rcx] minReg=1> LCL_VAR BB23 regmask=[rcx] minReg=1 last> --- V65 (Interval 38) STORE_LCL_VAR BB23 regmask=[rdx] minReg=1> LCL_VAR BB23 regmask=[rdx] minReg=1 last> --- V66 (Interval 39) STORE_LCL_VAR BB23 regmask=[rcx] minReg=1> LCL_VAR BB23 regmask=[rcx] minReg=1 last> --- V67 (Interval 40) STORE_LCL_VAR BB23 regmask=[rdx] minReg=1> LCL_VAR BB23 regmask=[rdx] minReg=1 last> --- V68 --- V69 --- V70 (Interval 41) STORE_LCL_VAR BB32 regmask=[rcx] minReg=1> LCL_VAR BB32 regmask=[rcx] minReg=1 last> --- V71 (Interval 42) STORE_LCL_VAR BB32 regmask=[rdx] minReg=1> LCL_VAR BB32 regmask=[rdx] minReg=1 last> --- V72 --- V73 --- V74 (Interval 43) STORE_LCL_VAR BB10 regmask=[rdx] minReg=1> LCL_VAR BB10 regmask=[rdx] minReg=1> LCL_VAR BB10 regmask=[rdx] minReg=1 last> --- V75 (Interval 44) STORE_LCL_VAR BB10 regmask=[rcx] minReg=1> LCL_VAR BB10 regmask=[rcx] minReg=1 last fixed> --- V76 --- V77 (Interval 45) STORE_LCL_VAR BB14 regmask=[rcx] minReg=1> LCL_VAR BB14 regmask=[rcx] minReg=1> LCL_VAR BB14 regmask=[rcx] minReg=1 last> --- V78 (Interval 46) STORE_LCL_VAR BB23 regmask=[rdx] minReg=1> LCL_VAR BB23 regmask=[rdx] minReg=1> LCL_VAR BB23 regmask=[rdx] minReg=1 last> --- V79 (Interval 47) STORE_LCL_VAR BB23 regmask=[rcx] minReg=1> LCL_VAR BB23 regmask=[rcx] minReg=1 last fixed> --- V80 (Interval 48) STORE_LCL_VAR BB23 regmask=[rcx] minReg=1> LCL_VAR BB23 regmask=[rcx] minReg=1> LCL_VAR BB23 regmask=[rcx] minReg=1 last> --- V81 (Interval 49) STORE_LCL_VAR BB23 regmask=[rax] minReg=1> LCL_VAR BB23 regmask=[rax] minReg=1> LCL_VAR BB23 regmask=[rax] minReg=1 last> --- V82 (Interval 50) STORE_LCL_VAR BB23 regmask=[rax] minReg=1> LCL_VAR BB23 regmask=[rax] minReg=1> LCL_VAR BB23 regmask=[rax] minReg=1 last> --- V83 (Interval 51) STORE_LCL_VAR BB32 regmask=[r8] minReg=1> LCL_VAR BB32 regmask=[r8] minReg=1> LCL_VAR BB32 regmask=[r8] minReg=1 last> --- V84 (Interval 52) STORE_LCL_VAR BB32 regmask=[rax] minReg=1> LCL_VAR BB32 regmask=[rcx] minReg=1 last copy fixed> --- V85 (Interval 53) STORE_LCL_VAR BB35 regmask=[rdx] minReg=1> LCL_VAR BB35 regmask=[rdx] minReg=1> LCL_VAR BB35 regmask=[rdx] minReg=1 last> --- V86 --- V87 (Interval 54) STORE_LCL_VAR BB35 regmask=[rdx] minReg=1> LCL_VAR BB35 regmask=[rdx] minReg=1> LCL_VAR BB35 regmask=[rdx] minReg=1 last> --- V88 (Interval 55) STORE_LCL_VAR BB35 regmask=[rcx] minReg=1> LCL_VAR BB35 regmask=[rcx] minReg=1 last fixed> --- V89 (Interval 56) STORE_LCL_VAR BB35 regmask=[rcx] minReg=1> LCL_VAR BB35 regmask=[rcx] minReg=1> LCL_VAR BB35 regmask=[rcx] minReg=1 last> --- V90 (Interval 57) STORE_LCL_VAR BB40 regmask=[rcx] minReg=1> LCL_VAR BB40 regmask=[rcx] minReg=1> LCL_VAR BB40 regmask=[rcx] minReg=1 last> Active intervals at end of allocation: ----------------------- RESOLVING BB BOUNDARIES ----------------------- Resolution Candidates: {V00 V01 V02 V03 V05 V08 V09 V10 V13 V14 V17 V18 V19 V20 V21 V22 V24 V25 V26 V27 V29 V31 V32 V33 V34 V36 V37 V39 V41 V42 V51 V52 V53} Has Critical Edges Prior to Resolution BB01 use def in out {V00} {V52 V53} {V00 V01 V02} {V01 V02 V52 V53} Var=Reg beg of BB01: V01=rsi V00=rcx V02=rdi Var=Reg end of BB01: V01=rsi V02=rdi V52=rbx V53=rbp BB02 use def in out {V52} {} {V01 V02 V52 V53} {V01 V02 V52 V53} Var=Reg beg of BB02: V01=rsi V02=rdi V52=rbx V53=rbp Var=Reg end of BB02: V01=rsi V02=rdi V52=rbx V53=rbp BB03 use def in out {V01 V02} {} {V01 V02} {} Var=Reg beg of BB03: V01=rsi V02=rdi Var=Reg end of BB03: none BB04 use def in out {V01 V53} {V03 V40} {V01 V02 V52 V53} {V01 V02 V03 V52 V53} Var=Reg beg of BB04: V01=rsi V02=rdi V52=rbx V53=rbp Var=Reg end of BB04: V01=rsi V02=rdi V52=rbx V53=rbp V03=r14 BB05 use def in out {V53} {V39} {V01 V02 V03 V52 V53} {V01 V02 V03 V39 V52 V53} Var=Reg beg of BB05: V01=rsi V02=rdi V52=rbx V53=rbp V03=r14 Var=Reg end of BB05: V01=rsi V02=rdi V52=rbx V53=rbp V03=r14 V39=r15 BB06 use def in out {} {V39} {V01 V02 V03 V52 V53} {V01 V02 V03 V39 V52 V53} Var=Reg beg of BB06: V01=rsi V02=rdi V52=rbx V53=rbp V03=r14 Var=Reg end of BB06: V01=rsi V02=rdi V52=rbx V53=rbp V03=r14 V39=r15 BB07 use def in out {V39 V52} {V31 V42} {V01 V02 V03 V39 V52 V53} {V01 V02 V03 V31 V42 V52 V53} Var=Reg beg of BB07: V01=rsi V02=rdi V52=rbx V53=rbp V03=r14 V39=r15 Var=Reg end of BB07: V01=rsi V02=rdi V52=rbx V53=rbp V31=r15 V42=r12 V03=r14 BB08 use def in out {V42} {V41} {V01 V02 V03 V31 V42 V52 V53} {V01 V02 V03 V31 V41 V52 V53} Var=Reg beg of BB08: V01=rsi V02=rdi V52=rbx V53=rbp V31=r15 V42=r12 V03=r14 Var=Reg end of BB08: V01=rsi V02=rdi V52=rbx V53=rbp V31=r15 V41=r12 V03=r14 BB09 use def in out {V31} {V41} {V01 V02 V03 V31 V52 V53} {V01 V02 V03 V31 V41 V52 V53} Var=Reg beg of BB09: V01=rsi V02=rdi V52=rbx V53=rbp V31=r15 V03=r14 Var=Reg end of BB09: V01=rsi V02=rdi V52=rbx V53=rbp V31=r15 V41=r12 V03=r14 BB10 use def in out {V31 V41 V52 V53} {V05 V08 V09 V10 V74 V75} {V01 V02 V03 V31 V41 V52 V53} {V01 V02 V03 V05 V08 V09 V10 V52 V53} Var=Reg beg of BB10: V01=rsi V02=rdi V52=rbx V53=rbp V31=r15 V41=r12 V03=r14 Var=Reg end of BB10: V01=rsi V02=rdi V52=rbx V53=rbp V05=r15 V08=r12 V03=r14 V09=r13 BB11 use def in out {V01 V05} {} {V01 V02 V03 V05 V08 V09 V10 V52 V53} {V01 V02 V03 V05 V08 V09 V10 V52 V53} Var=Reg beg of BB11: V01=rsi V02=rdi V52=rbx V53=rbp V05=r15 V08=r12 V03=r14 V09=r13 Var=Reg end of BB11: V01=rsi V02=rdi V52=rbx V53=rbp V05=r15 V08=r12 V03=r14 V09=r13 BB12 use def in out {V01 V02} {} {V01 V02} {} Var=Reg beg of BB12: V01=rsi V02=rdi Var=Reg end of BB12: none BB13 use def in out {V05} {} {V01 V02 V03 V05 V08 V09 V10 V52 V53} {V01 V02 V03 V08 V09 V10 V52 V53} Var=Reg beg of BB13: V01=rsi V02=rdi V52=rbx V53=rbp V05=r15 V08=r12 V03=r14 V09=r13 Var=Reg end of BB13: V01=rsi V02=rdi V52=rbx V53=rbp V08=r12 V03=r14 V09=r13 BB14 use def in out {V03} {V13 V77} {V01 V02 V03 V08 V09 V10 V52 V53} {V01 V02 V03 V08 V09 V10 V13 V52 V53} Var=Reg beg of BB14: V01=rsi V02=rdi V52=rbx V53=rbp V08=r12 V03=r14 V09=r13 Var=Reg end of BB14: V01=rsi V02=rdi V13=r15 V52=rbx V53=rbp V08=r12 V03=r14 V09=r13 BB15 use def in out {V10} {} {V01 V02 V03 V08 V09 V10 V13 V52 V53} {V01 V02 V03 V08 V09 V10 V13 V52 V53} Var=Reg beg of BB15: V01=rsi V02=rdi V13=r15 V52=rbx V53=rbp V08=r12 V03=r14 V09=r13 Var=Reg end of BB15: V01=rsi V02=rdi V13=r15 V52=rbx V53=rbp V10=rax V08=r12 V03=r14 V09=r13 BB16 use def in out {V01 V02 V10 V13} {V51} {V01 V02 V10 V13} {V51} Var=Reg beg of BB16: V01=rsi V02=rdi V13=r15 Var=Reg end of BB16: V51=rax BB17 use def in out {V53} {} {V01 V02 V03 V08 V09 V10 V13 V52 V53} {V01 V02 V03 V08 V09 V10 V13 V52 V53} Var=Reg beg of BB17: V01=rsi V02=rdi V13=r15 V52=rbx V53=rbp V08=r12 V03=r14 V09=r13 Var=Reg end of BB17: V01=rsi V02=rdi V13=r15 V52=rbx V53=rbp V08=r12 V03=r14 V09=r13 BB18 use def in out {V10} {V32} {V01 V02 V03 V08 V09 V10 V13 V52 V53} {V01 V02 V03 V08 V09 V13 V32 V52 V53} Var=Reg beg of BB18: V01=rsi V02=rdi V13=r15 V52=rbx V53=rbp V08=r12 V03=r14 V09=r13 Var=Reg end of BB18: V01=rsi V02=rdi V13=r15 V52=rbx V53=rbp V08=r12 V03=r14 V09=r13 V32=rdx BB19 use def in out {V10 V53} {V32} {V01 V02 V03 V08 V09 V10 V13 V52 V53} {V01 V02 V03 V08 V09 V13 V32 V52 V53} Var=Reg beg of BB19: V01=rsi V02=rdi V13=r15 V52=rbx V53=rbp V08=r12 V03=r14 V09=r13 Var=Reg end of BB19: V01=rsi V02=rdi V13=r15 V52=rbx V53=rbp V08=r12 V03=r14 V09=r13 V32=rdx BB20 use def in out {V13 V32} {V14} {V01 V02 V03 V08 V09 V13 V32 V52 V53} {V01 V02 V03 V08 V09 V13 V14 V52 V53} Var=Reg beg of BB20: V01=rsi V02=rdi V13=r15 V52=rbx V53=rbp V08=r12 V03=r14 V09=r13 V32=rdx Var=Reg end of BB20: V01=rsi V02=rdi V13=r15 V52=rbx V53=rbp V08=r12 V03=r14 V09=r13 V14=rax BB21 use def in out {V01 V14 V52} {V38} {V01 V02 V03 V08 V09 V13 V14 V52 V53} {V01 V02 V03 V08 V09 V13 V14 V52 V53} Var=Reg beg of BB21: V01=rsi V02=rdi V13=r15 V52=rbx V53=rbp V08=r12 V03=r14 V09=r13 V14=rax Var=Reg end of BB21: V01=rsi V02=rdi V13=r15 V52=rbx V53=rbp V08=r12 V03=r14 V09=r13 BB22 use def in out {V01 V02} {} {V01 V02} {} Var=Reg beg of BB22: V01=rsi V02=rdi Var=Reg end of BB22: none BB23 use def in out {V08 V09 V14 V52 V53} {V17 V18 V43 V46 V64 V65 V66 V67 V78 V79 V80 V81 V82} {V01 V02 V03 V08 V09 V13 V14 V52 V53} {V01 V02 V03 V13 V17 V18} Var=Reg beg of BB23: V01=rsi V02=rdi V13=r15 V52=rbx V53=rbp V08=r12 V03=r14 V09=r13 Var=Reg end of BB23: V01=rsi V02=rdi V13=r15 V03=r14 V17=rbx V18=rax BB24 use def in out {} {V33} {V01 V02 V03 V13} {V01 V02 V03 V13 V33} Var=Reg beg of BB24: V01=rsi V02=rdi V13=r15 V03=r14 Var=Reg end of BB24: V01=rsi V02=rdi V13=r15 V03=r14 V33=rbp BB25 use def in out {V17 V18} {V33} {V01 V02 V03 V13 V17 V18} {V01 V02 V03 V13 V33} Var=Reg beg of BB25: V01=rsi V02=rdi V13=r15 V03=r14 V17=rbx V18=rax Var=Reg end of BB25: V01=rsi V02=rdi V13=r15 V03=r14 V33=rbp BB26 use def in out {V33} {V19} {V01 V02 V03 V13 V33} {V01 V02 V03 V13 V19} Var=Reg beg of BB26: V01=rsi V02=rdi V13=r15 V03=r14 V33=rbp Var=Reg end of BB26: V01=rsi V02=rdi V13=r15 V19=rbp V03=r14 BB27 use def in out {V19} {} {V01 V02 V03 V13 V19} {V01 V02 V03 V13 V19} Var=Reg beg of BB27: V01=rsi V02=rdi V13=r15 V19=rbp V03=r14 Var=Reg end of BB27: V01=rsi V02=rdi V13=r15 V19=rbp V03=r14 BB28 use def in out {V03 V13} {V20 V21} {V01 V02 V03 V13 V19} {V01 V02 V13 V19 V20 V21} Var=Reg beg of BB28: V01=rsi V02=rdi V13=r15 V19=rbp V03=r14 Var=Reg end of BB28: V01=rsi V02=rdi V13=r15 V19=rbp V20=r14 V21=rbx BB29 use def in out {V19 V20} {} {V01 V02 V13 V19 V20} {V01 V02 V13 V19 V20} Var=Reg beg of BB29: V01=rsi V02=rdi V13=r15 V19=rbp V20=r14 Var=Reg end of BB29: V01=rsi V02=rdi V13=r15 V19=rbp V20=r14 BB30 use def in out {V01 V02 V13} {V51} {V01 V02 V13} {V51} Var=Reg beg of BB30: V01=rsi V02=rdi V13=r15 Var=Reg end of BB30: V51=rax BB31 use def in out {V19 V20} {V21} {V01 V02 V13 V19 V20} {V01 V02 V13 V19 V20 V21} Var=Reg beg of BB31: V01=rsi V02=rdi V13=r15 V19=rbp V20=r14 Var=Reg end of BB31: V01=rsi V02=rdi V13=r15 V19=rbp V20=r14 V21=rbx BB32 use def in out {} {V70 V71 V83 V84} {V01 V02 V13 V19 V20 V21} {V01 V02 V13 V19 V20 V21} Var=Reg beg of BB32: V01=rsi V02=rdi V13=r15 V19=rbp V20=r14 V21=rbx Var=Reg end of BB32: V01=rsi V02=rdi V13=r15 V19=rbp V20=r14 V21=rbx BB33 use def in out {V19} {V34} {V01 V02 V13 V19 V20 V21} {V01 V02 V13 V20 V21 V34} Var=Reg beg of BB33: V01=rsi V02=rdi V13=r15 V19=rbp V20=r14 V21=rbx Var=Reg end of BB33: V01=rsi V02=rdi V13=r15 V20=r14 V21=rbx V34=rbp BB34 use def in out {V19} {V34} {V01 V02 V13 V19 V20 V21} {V01 V02 V13 V20 V21 V34} Var=Reg beg of BB34: V01=rsi V02=rdi V13=r15 V19=rbp V20=r14 V21=rbx Var=Reg end of BB34: V01=rsi V02=rdi V13=r15 V20=r14 V21=rbx V34=rbp BB35 use def in out {V20 V21 V34} {V22 V24 V25 V26 V85 V87 V88 V89} {V01 V02 V13 V20 V21 V34} {V01 V02 V13 V20 V22 V24 V25 V26} Var=Reg beg of BB35: V01=rsi V02=rdi V13=r15 V20=r14 V21=rbx V34=rbp Var=Reg end of BB35: V01=rsi V02=rdi V13=r15 V20=r14 V24=rbx V25=r12 V26=rax V22=rbp BB36 use def in out {V20 V25 V26} {V29} {V01 V02 V13 V20 V22 V24 V25 V26} {V01 V02 V13 V20 V22 V24 V29} Var=Reg beg of BB36: V01=rsi V02=rdi V13=r15 V20=r14 V24=rbx V25=r12 V26=rax V22=rbp Var=Reg end of BB36: V01=rsi V02=rdi V13=r15 V20=r14 V24=rbx V29=rax V22=rbp BB37 use def in out {V24 V29} {V37} {V01 V02 V13 V20 V22 V24 V29} {V01 V02 V13 V20 V22 V24 V29 V37} Var=Reg beg of BB37: V01=rsi V02=rdi V13=r15 V20=r14 V24=rbx V29=rax V22=rbp Var=Reg end of BB37: V01=rsi V02=rdi V13=r15 V20=r14 V24=rbx V29=rax V37=rcx V22=rbp BB38 use def in out {} {V37} {V01 V02 V13 V20 V22 V24 V29} {V01 V02 V13 V20 V22 V24 V29 V37} Var=Reg beg of BB38: V01=rsi V02=rdi V13=r15 V20=r14 V24=rbx V29=rax V22=rbp Var=Reg end of BB38: V01=rsi V02=rdi V13=r15 V20=r14 V24=rbx V29=rax V37=rcx V22=rbp BB39 use def in out {V24 V29 V37} {V24 V25} {V01 V02 V13 V20 V22 V24 V29 V37} {V01 V02 V13 V20 V22 V24 V25} Var=Reg beg of BB39: V01=rsi V02=rdi V13=r15 V20=r14 V24=rbx V29=rax V37=rcx V22=rbp Var=Reg end of BB39: V01=rsi V02=rdi V13=r15 V20=r14 V24=rbx V25=r12 V22=rbp BB40 use def in out {V13 V20 V24} {V27 V90} {V01 V02 V13 V20 V22 V24 V25} {V01 V02 V13 V22 V25 V27} Var=Reg beg of BB40: V01=rsi V02=rdi V13=r15 V20=r14 V24=rbx V25=r12 V22=rbp Var=Reg end of BB40: V01=rsi V02=rdi V13=r15 V25=r12 V22=rbp V27=rdx BB41 use def in out {V22} {V36} {V01 V02 V22 V25 V27} {V01 V02 V25 V27 V36} Var=Reg beg of BB41: V01=rsi V02=rdi V25=r12 V22=rbp V27=rdx Var=Reg end of BB41: V01=rsi V02=rdi V25=r12 V36=r8 V27=rdx BB42 use def in out {V13} {V36} {V01 V02 V13 V25 V27} {V01 V02 V25 V27 V36} Var=Reg beg of BB42: V01=rsi V02=rdi V13=r15 V25=r12 V27=rdx Var=Reg end of BB42: V01=rsi V02=rdi V25=r12 V36=r8 V27=rdx BB43 use def in out {V01 V02 V25 V27 V36} {V51} {V01 V02 V25 V27 V36} {V51} Var=Reg beg of BB43: V01=rsi V02=rdi V25=r12 V36=r8 V27=rdx Var=Reg end of BB43: V51=rax BB44 use def in out {V51} {} {V51} {} Var=Reg beg of BB44: V51=rax Var=Reg end of BB44: none RESOLVING EDGES BB15 bottom: move V10 from rax to STK (SharedCritical) fgFindInsertPoint(regionIndex=0, putInTryRegion=true, startBlk=BB01, endBlk=BB00, nearBlk=BB20, jumpBlk=BB00, runRarely=false) fgNewBBinRegion(jumpKind=6, tryIndex=0, hndIndex=0, putInFilter=false, runRarely=false, insertAtEnd=false): inserting after BB22 New Basic Block BB45 [0057] created. Splitting edge from BB20 to BB23; adding BB45 BB45 bottom: move V14 from rax to STK (Critical) Set V00 argument initial register to rcx Set V01 argument initial register to rsi Set V02 argument initial register to rdi Trees after linear scan register allocator (LSRA) ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0056] 1 1 [???..???) i internal label target LIR BB02 [0000] 1 BB01 1 [000..00D)-> BB04 ( cond ) i label target idxlen LIR BB03 [0001] 1 BB02 0.50 [00D..017) (return) i hascall gcsafe LIR BB04 [0002] 1 BB02 0.50 [017..065)-> BB06 ( cond ) i label target hascall gcsafe LIR BB05 [0038] 1 BB04 0.50 [020..021)-> BB07 (always) i gcsafe LIR BB06 [0039] 1 BB04 0.50 [020..021) i label target gcsafe LIR BB07 [0040] 2 BB05,BB06 0.50 [000..000)-> BB09 ( cond ) i internal label target gcsafe idxlen LIR BB08 [0043] 1 BB07 0.50 [000..000)-> BB10 (always) i internal gcsafe LIR BB09 [0044] 1 BB07 0.50 [000..000) i internal label target gcsafe LIR BB10 [0045] 2 BB08,BB09 0.50 [???..???)-> BB14 ( cond ) i internal label target hascall gcsafe idxlen LIR BB11 [0003] 1 BB10 0.50 [065..070)-> BB13 ( cond ) i hascall gcsafe LIR BB12 [0004] 1 BB11 0.50 [070..07A) (return) i hascall gcsafe LIR BB13 [0005] 1 BB11 0.50 [07A..082) i label target hascall gcsafe LIR BB14 [0006] 2 BB10,BB13 0.50 [082..092)-> BB16 ( cond ) i label target hascall gcsafe LIR BB15 [0007] 1 BB14 0.50 [092..096)-> BB17 ( cond ) i gcsafe LIR BB16 [0008] 2 BB14,BB15 0.50 [096..0A7)-> BB44 (always) i label target hascall gcsafe LIR BB17 [0009] 1 BB15 0.50 [0A7..0B0)-> BB19 ( cond ) i label target gcsafe LIR BB18 [0010] 1 BB17 0.50 [0B0..0B4)-> BB20 (always) i gcsafe LIR BB19 [0011] 1 BB17 0.50 [0B4..0BE) i label target gcsafe LIR BB20 [0012] 2 BB18,BB19 0.50 [0BE..0C4)-> BB45 ( cond ) i label target gcsafe LIR BB21 [0013] 1 BB20 0.50 [0C4..0D9)-> BB23 ( cond ) i hascall gcsafe idxlen LIR BB22 [0014] 1 BB21 0.50 [0D9..0E3) (return) i hascall gcsafe LIR BB45 [0057] 1 BB20 0.25 [???..???)-> BB23 (always) internal target LIR BB23 [0015] 2 BB45,BB21 0.50 [0E3..117)-> BB25 ( cond ) i label target hascall gcsafe LIR BB24 [0016] 1 BB23 0.50 [117..11A)-> BB26 (always) i gcsafe LIR BB25 [0017] 1 BB23 0.50 [11A..11F) i label target gcsafe LIR BB26 [0018] 2 BB24,BB25 0.50 [11F..126)-> BB28 ( cond ) i label target gcsafe LIR BB27 [0019] 1 BB26 0.50 [126..12F) i hascall gcsafe LIR BB28 [0020] 2 BB26,BB27 0.50 [12F..13E)-> BB32 ( cond ) i label target gcsafe LIR BB29 [0021] 1 BB28 0.50 [13E..144)-> BB31 ( cond ) i gcsafe LIR BB30 [0022] 1 BB29 0.50 [144..155)-> BB44 (always) i hascall gcsafe LIR BB31 [0023] 1 BB29 0.50 [155..15C) i label target gcsafe LIR BB32 [0024] 2 BB28,BB31 0.50 [15C..167)-> BB34 ( cond ) i label target hascall gcsafe LIR BB33 [0025] 1 BB32 0.50 [167..16B)-> BB35 (always) i gcsafe LIR BB34 [0026] 1 BB32 0.50 [16B..16F) i label target gcsafe LIR BB35 [0027] 2 BB33,BB34 0.50 [16F..1A4)-> BB40 ( cond ) i label target hascall gcsafe LIR BB36 [0028] 1 BB35 0.50 [1A4..1AF)-> BB38 ( cond ) i gcsafe LIR BB37 [0029] 1 BB36 0.50 [1AF..1C3)-> BB39 (always) i gcsafe LIR BB38 [0030] 1 BB36 0.50 [1C3..1C4) i label target gcsafe LIR BB39 [0031] 2 BB37,BB38 0.50 [1C4..1D0) i label target gcsafe LIR BB40 [0032] 2 BB35,BB39 0.50 [1D0..1E7)-> BB42 ( cond ) i label target hascall gcsafe LIR BB41 [0033] 1 BB40 0.50 [1E7..1EE)-> BB43 (always) i gcsafe LIR BB42 [0034] 1 BB40 0.50 [1EE..1F2) i label target gcsafe LIR BB43 [0035] 2 BB41,BB42 0.50 [1F2..202) i label target hascall gcsafe LIR BB44 [0054] 3 BB16,BB30,BB43 0.50 [???..???) (return) keep internal target gcsafe LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} N003 ( 1, 1) [000531] ------------ t531 = LCL_VAR byref V00 arg0 u:1 rcx Zero Fseq[Mantissa] REG rcx $80 /--* t531 byref N005 ( 3, 2) [000532] n----------- t532 = * IND ref REG rbx /--* t532 ref N007 ( 3, 3) [000533] DA---------- * STORE_LCL_VAR ref V52 tmp22 d:2 rbx REG rbx N009 ( 1, 1) [000535] ------------ t535 = LCL_VAR byref V00 arg0 u:1 rcx (last use) REG rcx $80 /--* t535 byref N011 ( 2, 2) [000537] -c---------- t537 = * LEA(b+8) byref REG NA /--* t537 byref N013 ( 4, 4) [000538] n----------- t538 = * IND int REG rbp /--* t538 int N015 ( 4, 4) [000539] DA---------- * STORE_LCL_VAR int V53 tmp23 d:2 rbp REG rbp ------------ BB02 [000..00D) -> BB04 (cond), preds={BB01} succs={BB03,BB04} N019 (???,???) [000910] ------------ IL_OFFSET void IL offset: 0x0 REG NA N021 ( 1, 1) [000002] ------------ t2 = LCL_VAR ref V52 tmp22 u:2 rbx REG rbx /--* t2 ref N023 (???,???) [000988] -c---------- t988 = * LEA(b+8) ref REG NA /--* t988 ref N025 ( 3, 3) [000003] -c-XG------- t3 = * IND int REG NA N027 ( 1, 1) [000004] -c---------- t4 = CNS_INT int 0 REG NA $40 /--* t3 int +--* t4 int N029 ( 5, 5) [000005] J--XG--N---- * NE void REG NA N031 ( 7, 7) [000006] ---XG------- * JTRUE void REG NA ------------ BB03 [00D..017) (return), preds={BB02} succs={} N035 (???,???) [000911] ------------ IL_OFFSET void IL offset: 0xd REG NA N037 ( 1, 1) [000400] ------------ t400 = LCL_VAR ref V01 arg1 u:1 rsi REG rsi $c0 /--* t400 ref N039 (???,???) [000995] ------------ t995 = * PUTARG_REG ref REG rcx N041 ( 1, 1) [000996] ------------ t996 = LCL_VAR ref V01 arg1 rsi (last use) REG rsi /--* t996 ref N043 ( 2, 2) [000997] -c---------- t997 = * LEA(b+0) byref REG NA /--* t997 byref N045 ( 5, 4) [000998] ------------ t998 = * IND long REG rax /--* t998 long N047 ( 6, 5) [000999] -c---------- t999 = * LEA(b+80) long REG NA /--* t999 long N049 ( 9, 7) [001000] ------------ t1000 = * IND long REG rax /--* t1000 long N051 ( 10, 8) [001001] -c---------- t1001 = * LEA(b+0) long REG NA /--* t1001 long N053 ( 13, 10) [001002] -c---------- t1002 = * IND long REG NA /--* t995 ref this in rcx +--* t1002 long control expr N055 ( 21, 10) [000401] --CXG------- t401 = * CALLV ind long FloatingPointType.get_Zero REG rax $459 N057 ( 1, 1) [000399] ------------ t399 = LCL_VAR byref V02 arg2 u:1 rdi (last use) REG rdi $81 /--* t399 byref +--* t401 long N059 (???,???) [000912] -ACXG------- * STOREIND long REG NA N061 ( 1, 1) [000404] ------------ t404 = CNS_INT int 1 REG rax $41 /--* t404 int N063 ( 2, 2) [000520] ------------ * RETURN int REG NA $5cb ------------ BB04 [017..065) -> BB06 (cond), preds={BB02} succs={BB05,BB06} N067 ( 1, 1) [000007] ------------ t7 = LCL_VAR ref V01 arg1 u:1 rsi REG rsi $c0 /--* t7 ref N069 (???,???) [001003] ------------ t1003 = * PUTARG_REG ref REG rcx N071 ( 1, 1) [001004] ------------ t1004 = LCL_VAR ref V01 arg1 rsi REG rsi /--* t1004 ref N073 ( 2, 2) [001005] -c---------- t1005 = * LEA(b+0) byref REG NA /--* t1005 byref N075 ( 5, 4) [001006] ------------ t1006 = * IND long REG rax /--* t1006 long N077 ( 6, 5) [001007] -c---------- t1007 = * LEA(b+72) long REG NA /--* t1007 long N079 ( 9, 7) [001008] ------------ t1008 = * IND long REG rax /--* t1008 long N081 ( 10, 8) [001009] -c---------- t1009 = * LEA(b+32) long REG NA /--* t1009 long N083 ( 13, 10) [001010] -c---------- t1010 = * IND long REG NA /--* t1003 ref this in rcx +--* t1010 long control expr N085 ( 21, 10) [000406] --CXG------- t406 = * CALLV ind int FloatingPointType.get_DenormalMantissaBits REG rax $282 N087 ( 1, 1) [000407] -c---------- t407 = CNS_INT int 1 REG NA $41 /--* t406 int +--* t407 int N089 ( 23, 12) [000408] ---XG------- t408 = * ADD int REG rax $346 /--* t408 int N091 ( 24, 14) [000409] ---XG------- t409 = * CAST int <- ushort <- int REG r14 $347 N093 ( 1, 1) [000010] -c---------- t10 = CNS_INT int 1 REG NA $41 /--* t409 int +--* t10 int N095 ( 26, 16) [000011] ---XG------- t11 = * ADD int REG r14 $348 /--* t11 int N097 ( 30, 19) [000013] DA-XG------- * STORE_LCL_VAR int V03 loc0 d:2 r14 REG r14 N099 (???,???) [000913] ------------ IL_OFFSET void IL offset: 0x20 REG NA N101 ( 1, 1) [000017] ------------ t17 = LCL_VAR int V53 tmp23 u:2 rbp REG rbp /--* t17 int N103 ( 5, 4) [000424] DA--G------- * STORE_LCL_VAR int V40 tmp10 d:2 rcx REG rcx N105 (???,???) [000914] ------------ IL_OFFSET void IL offset: 0x20 REG NA N107 ( 1, 1) [000412] ------------ t412 = LCL_VAR int V40 tmp10 u:2 rcx (last use) REG rcx N109 ( 1, 1) [000411] -c---------- t411 = CNS_INT int 0 REG NA $40 /--* t412 int +--* t411 int N111 ( 3, 3) [000413] J------N---- * LE void REG NA N113 ( 5, 5) [000414] ------------ * JTRUE void REG NA ------------ BB05 [020..021) -> BB07 (always), preds={BB04} succs={BB07} N117 (???,???) [000915] ------------ IL_OFFSET void IL offset: 0x20 REG NA N119 ( 3, 2) [000419] ------------ t419 = LCL_VAR int V53 tmp23 u:2 rbp REG rbp /--* t419 int N121 ( 7, 5) [000421] DA---------- * STORE_LCL_VAR int V39 tmp9 d:4 r15 REG r15 ------------ BB06 [020..021), preds={BB04} succs={BB07} N125 (???,???) [000916] ------------ IL_OFFSET void IL offset: 0x20 REG NA N127 ( 1, 1) [000415] ------------ t415 = CNS_INT int 0 REG r15 $40 /--* t415 int N129 ( 5, 4) [000417] DA---------- * STORE_LCL_VAR int V39 tmp9 d:3 r15 REG r15 ------------ BB07 [000..000) -> BB09 (cond), preds={BB05,BB06} succs={BB08,BB09} N001 ( 0, 0) [000909] ------------ t909 = PHI_ARG int V39 tmp9 u:4 r15 N002 ( 0, 0) [000908] ------------ t908 = PHI_ARG int V39 tmp9 u:3 r15 $40 /--* t909 int +--* t908 int N003 ( 0, 0) [000885] ------------ t885 = * PHI int /--* t885 int N005 ( 0, 0) [000886] DA---------- * STORE_LCL_VAR int V39 tmp9 d:2 r15 N133 ( 3, 2) [000422] ------------ t422 = LCL_VAR int V39 tmp9 u:2 r15 (last use) REG r15 $241 /--* t422 int N135 ( 3, 3) [000021] DA---------- * STORE_LCL_VAR int V31 tmp1 d:2 r15 REG r15 N137 ( 1, 1) [000428] ------------ t428 = LCL_VAR ref V52 tmp22 u:2 rbx REG rbx /--* t428 ref N139 (???,???) [000990] -c---------- t990 = * LEA(b+8) ref REG NA /--* t990 ref N141 ( 3, 3) [000429] ---XG------- t429 = * IND int REG r12 /--* t429 int N143 ( 3, 3) [000443] DA-XG------- * STORE_LCL_VAR int V42 tmp12 d:2 r12 REG r12 N145 ( 3, 2) [000023] ------------ t23 = LCL_VAR int V31 tmp1 u:2 r15 REG r15 $241 N147 ( 1, 1) [000431] ------------ t431 = LCL_VAR int V42 tmp12 u:2 r12 REG r12 /--* t23 int +--* t431 int N149 ( 5, 4) [000432] N------N-U-- * LE void REG NA N151 ( 7, 6) [000433] ------------ * JTRUE void REG NA ------------ BB08 [000..000) -> BB10 (always), preds={BB07} succs={BB10} N155 ( 1, 1) [000438] ------------ t438 = LCL_VAR int V42 tmp12 u:2 r12 (last use) REG r12 /--* t438 int N157 ( 1, 3) [000440] DA---------- * STORE_LCL_VAR int V41 tmp11 d:4 r12 REG r12 ------------ BB09 [000..000), preds={BB07} succs={BB10} N161 ( 1, 1) [000434] ------------ t434 = LCL_VAR int V31 tmp1 u:2 r15 REG r15 $241 /--* t434 int N163 ( 1, 3) [000436] DA---------- * STORE_LCL_VAR int V41 tmp11 d:3 r12 REG r12 ------------ BB10 [???..???) -> BB14 (cond), preds={BB08,BB09} succs={BB11,BB14} N001 ( 0, 0) [000907] ------------ t907 = PHI_ARG int V41 tmp11 u:4 r12 N002 ( 0, 0) [000906] ------------ t906 = PHI_ARG int V41 tmp11 u:3 r12 $241 /--* t907 int +--* t906 int N003 ( 0, 0) [000882] ------------ t882 = * PHI int /--* t882 int N005 ( 0, 0) [000883] DA---------- * STORE_LCL_VAR int V41 tmp11 d:2 r12 N167 ( 1, 1) [000022] ------------ t22 = LCL_VAR int V31 tmp1 u:2 r15 (last use) REG r15 $241 N169 ( 1, 1) [000032] ------------ t32 = LCL_VAR int V41 tmp11 u:2 r12 REG r12 $242 /--* t22 int +--* t32 int N171 ( 3, 3) [000033] ------------ t33 = * SUB int REG r15 $34e /--* t33 int N173 ( 7, 6) [000035] DA---------- * STORE_LCL_VAR int V05 loc2 d:2 r15 REG r15 N175 (???,???) [000917] ------------ IL_OFFSET void IL offset: 0x42 REG NA N177 ( 1, 1) [000042] ------------ t42 = LCL_VAR int V41 tmp11 u:2 r12 (last use) REG r12 $242 /--* t42 int N179 ( 5, 4) [000044] DA---------- * STORE_LCL_VAR int V08 loc5 d:2 r12 REG r12 N181 ( 1, 1) [000447] ------------ t447 = LCL_VAR ref V52 tmp22 u:2 rbx REG rbx /--* t447 ref N183 (???,???) [000992] -c---------- t992 = * LEA(b+8) ref REG NA /--* t992 ref N185 ( 3, 3) [000448] ---XG------- t448 = * IND int REG r13 /--* t448 int N187 ( 7, 6) [000050] DA-XG------- * STORE_LCL_VAR int V09 loc6 d:2 r13 REG r13 N189 (???,???) [000918] ------------ IL_OFFSET void IL offset: 0x4f REG NA N191 ( 3, 2) [000051] ------------ t51 = LCL_VAR int V09 loc6 u:2 r13 REG r13 N193 ( 1, 1) [000052] ------------ t52 = LCL_VAR int V08 loc5 u:2 r12 REG r12 $242 /--* t51 int +--* t52 int N195 ( 5, 4) [000053] ------------ t53 = * SUB int REG rax /--* t53 int N197 ( 5, 4) [000055] DA---------- * STORE_LCL_VAR int V10 loc7 d:2 NA REG NA N199 ( 3, 2) [000063] -------N---- t63 = LCL_VAR_ADDR byref V11 loc8 rcx * ref V11._bits (offs=0x00) -> V54 tmp24 * int V11._sign (offs=0x08) -> V55 tmp25 REG rcx /--* t63 byref N201 ( 7, 6) [000563] DA--------L- * STORE_LCL_VAR long V75 tmp45 d:2 rcx REG rcx N203 ( 3, 2) [000547] -------N---- t547 = LCL_VAR_ADDR byref V73 tmp43 rdx REG rdx /--* t547 byref N205 ( 3, 3) [000549] DA---------- * STORE_LCL_VAR byref V74 tmp44 d:2 rdx REG rdx N207 ( 1, 1) [000550] ------------ t550 = LCL_VAR byref V74 tmp44 u:2 rdx Zero Fseq[Mantissa] REG rdx $401 N209 ( 1, 1) [000552] -------N---- t552 = LCL_VAR ref V52 tmp22 u:2 rbx REG rbx /--* t550 byref +--* t552 ref N211 (???,???) [000919] -A---------- * STOREIND ref REG NA N213 ( 1, 1) [000555] ------------ t555 = LCL_VAR byref V74 tmp44 u:2 rdx (last use) REG rdx $401 /--* t555 byref N215 ( 2, 2) [000557] -c---------- t557 = * LEA(b+8) byref REG NA N217 ( 1, 1) [000559] -------N---- t559 = LCL_VAR int V53 tmp23 u:2 rbp REG rbp /--* t557 byref +--* t559 int N219 (???,???) [000920] -A--------L- * STOREIND int REG NA N221 ( 3, 2) [000564] ------------ t564 = LCL_VAR long V75 tmp45 u:2 rcx (last use) REG rcx $400 /--* t564 long N223 (???,???) [001011] ------------ t1011 = * PUTARG_REG long REG rcx N225 ( 3, 2) [000565] -------N---- t565 = LCL_VAR_ADDR byref V73 tmp43 rdx REG rdx /--* t565 byref N227 (???,???) [001012] ------------ t1012 = * PUTARG_REG byref REG rdx N229 ( 1, 1) [000058] ------------ t58 = LCL_VAR int V08 loc5 u:2 r12 REG r12 $242 /--* t58 int N231 (???,???) [001013] ------------ t1013 = * PUTARG_REG int REG r9 N233 ( 1, 1) [000057] ------------ t57 = CNS_INT int 0 REG r8 $40 /--* t57 int N235 (???,???) [001014] ------------ t1014 = * PUTARG_REG int REG r8 /--* t1011 long arg0 in rcx +--* t1012 byref arg1 in rdx +--* t1013 int arg3 in r9 +--* t1014 int arg2 in r8 N237 ( 49, 35) [000059] S-CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger REG NA $VN.Void N239 (???,???) [000921] ------------ IL_OFFSET void IL offset: 0x61 REG NA N241 ( 3, 2) [000065] ------------ t65 = LCL_VAR int V05 loc2 u:2 r15 REG r15 $34e N243 ( 1, 1) [000066] -c---------- t66 = CNS_INT int 0 REG NA $40 /--* t65 int +--* t66 int N245 ( 5, 4) [000067] N------N---- * EQ void REG NA $351 N247 ( 7, 6) [000068] ------------ * JTRUE void REG NA ------------ BB11 [065..070) -> BB13 (cond), preds={BB10} succs={BB12,BB13} N251 ( 1, 1) [000382] ------------ t382 = LCL_VAR ref V01 arg1 u:1 rsi REG rsi $c0 /--* t382 ref N253 (???,???) [001015] ------------ t1015 = * PUTARG_REG ref REG rcx /--* t1015 ref this in rcx N255 ( 15, 8) [000383] --CXG------- t383 = * CALL int FloatingPointType.get_OverflowDecimalExponent REG rax $291 /--* t383 int N257 ( 16, 10) [000385] ---XG------- t385 = * CAST long <- int REG rcx $480 N259 ( 3, 2) [000380] ------------ t380 = LCL_VAR int V05 loc2 u:2 r15 REG r15 $34e /--* t380 int N261 ( 4, 4) [000381] ---------U-- t381 = * CAST long <- ulong <- uint REG rax $481 /--* t385 long +--* t381 long N263 ( 21, 15) [000386] J--XG--N---- * GE void REG NA $352 N265 ( 23, 17) [000387] ---XG------- * JTRUE void REG NA ------------ BB12 [070..07A) (return), preds={BB11} succs={} N269 (???,???) [000922] ------------ IL_OFFSET void IL offset: 0x70 REG NA N271 ( 1, 1) [000393] ------------ t393 = LCL_VAR ref V01 arg1 u:1 rsi REG rsi $c0 /--* t393 ref N273 (???,???) [001016] ------------ t1016 = * PUTARG_REG ref REG rcx N275 ( 1, 1) [001017] ------------ t1017 = LCL_VAR ref V01 arg1 rsi (last use) REG rsi /--* t1017 ref N277 ( 2, 2) [001018] -c---------- t1018 = * LEA(b+0) byref REG NA /--* t1018 byref N279 ( 5, 4) [001019] ------------ t1019 = * IND long REG rax /--* t1019 long N281 ( 6, 5) [001020] -c---------- t1020 = * LEA(b+80) long REG NA /--* t1020 long N283 ( 9, 7) [001021] ------------ t1021 = * IND long REG rax /--* t1021 long N285 ( 10, 8) [001022] -c---------- t1022 = * LEA(b+8) long REG NA /--* t1022 long N287 ( 13, 10) [001023] -c---------- t1023 = * IND long REG NA /--* t1016 ref this in rcx +--* t1023 long control expr N289 ( 21, 10) [000394] --CXG------- t394 = * CALLV ind long FloatingPointType.get_Infinity REG rax $458 N291 ( 1, 1) [000392] ------------ t392 = LCL_VAR byref V02 arg2 u:1 rdi (last use) REG rdi $81 /--* t392 byref +--* t394 long N293 (???,???) [000923] -ACXG------- * STOREIND long REG NA N295 ( 1, 1) [000397] ------------ t397 = CNS_INT int 3 REG rax $48 /--* t397 int N297 ( 2, 2) [000521] ------------ * RETURN int REG NA $5ca ------------ BB13 [07A..082), preds={BB11} succs={BB14} N301 (???,???) [000924] ------------ IL_OFFSET void IL offset: 0x7a REG NA N303 ( 3, 2) [000388] -------N---- t388 = LCL_VAR_ADDR byref V11 loc8 rcx * ref V11._bits (offs=0x00) -> V54 tmp24 * int V11._sign (offs=0x08) -> V55 tmp25 REG rcx /--* t388 byref N305 (???,???) [001024] ------------ t1024 = * PUTARG_REG byref REG rcx N307 ( 3, 2) [000390] ------------ t390 = LCL_VAR int V05 loc2 u:2 r15 (last use) REG r15 $34e /--* t390 int N309 (???,???) [001025] ------------ t1025 = * PUTARG_REG int REG rdx /--* t1024 byref arg0 in rcx +--* t1025 int arg1 in rdx N311 ( 20, 12) [000391] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen REG NA $VN.Void ------------ BB14 [082..092) -> BB16 (cond), preds={BB10,BB13} succs={BB15,BB16} N315 ( 3, 2) [000577] -------N---- t577 = LCL_VAR_ADDR byref V76 tmp46 rcx REG rcx /--* t577 byref N317 ( 3, 3) [000579] DA---------- * STORE_LCL_VAR byref V77 tmp47 d:2 rcx REG rcx N319 ( 1, 1) [000580] ------------ t580 = LCL_VAR byref V77 tmp47 u:2 rcx Zero Fseq[_bits] REG rcx $405 N321 ( 3, 2) [000582] -------N---- t582 = LCL_VAR ref (AX) V54 tmp24 rdx REG rdx $181 /--* t580 byref +--* t582 ref N323 (???,???) [000925] -A--G------- * STOREIND ref REG NA N325 ( 1, 1) [000585] ------------ t585 = LCL_VAR byref V77 tmp47 u:2 rcx (last use) REG rcx $405 /--* t585 byref N327 ( 2, 2) [000587] -c---------- t587 = * LEA(b+8) byref REG NA N329 ( 3, 2) [000589] -------N---- t589 = LCL_VAR int (AX) V55 tmp25 rdx REG rdx $243 /--* t587 byref +--* t589 int N331 (???,???) [000926] -A--G-----L- * STOREIND int REG NA N333 ( 3, 2) [000592] -------N---- t592 = LCL_VAR_ADDR byref V76 tmp46 rcx REG rcx /--* t592 byref N335 (???,???) [001026] ------------ t1026 = * PUTARG_REG byref REG rcx N337 ( 3, 3) [000071] ------------ t71 = LCL_VAR_ADDR long V12 loc9 rdx REG rdx $443 /--* t71 long N339 (???,???) [001027] ------------ t1027 = * PUTARG_REG long REG rdx /--* t1026 byref arg0 in rcx +--* t1027 long arg1 in rdx N341 ( 41, 28) [000072] --CXG------- t72 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits REG rax $293 /--* t72 int N343 ( 41, 28) [000077] DA-XG------- * STORE_LCL_VAR int V13 loc10 d:2 r15 REG r15 N345 (???,???) [000927] ------------ IL_OFFSET void IL offset: 0x8d REG NA N347 ( 1, 1) [000078] ------------ t78 = LCL_VAR int V13 loc10 u:2 r15 REG r15 $293 N349 ( 3, 2) [000079] ------------ t79 = LCL_VAR int V03 loc0 u:2 r14 REG r14 $348 /--* t78 int +--* t79 int N351 ( 5, 4) [000080] N------N-U-- * GE void REG NA $353 N353 ( 7, 6) [000081] ------------ * JTRUE void REG NA ------------ BB15 [092..096) -> BB17 (cond), preds={BB14} succs={BB16,BB17} N357 (???,???) [000928] ------------ IL_OFFSET void IL offset: 0x92 REG NA N359 ( 1, 1) [000091] -----------z t91 = LCL_VAR int V10 loc7 u:2 rax REG rax N361 ( 1, 1) [000092] -c---------- t92 = CNS_INT int 0 REG NA $40 /--* t91 int +--* t92 int N363 ( 3, 3) [000093] J------N---- * NE void REG NA N001 ( 3, 2) [001077] -----------Z t1077 = LCL_VAR int V10 loc7 rax REG rax N365 ( 5, 5) [000094] ------------ * JTRUE void REG NA ------------ BB16 [096..0A7) -> BB44 (always), preds={BB14,BB15} succs={BB44} N369 (???,???) [000929] ------------ IL_OFFSET void IL offset: 0x96 REG NA N371 ( 1, 1) [000088] ------------ t88 = LCL_VAR byref V02 arg2 u:1 rdi (last use) REG rdi $81 /--* t88 byref N373 (???,???) [001028] ------------ * PUTARG_STK [+0x20] void REG NA N375 ( 1, 1) [000084] -c---------- t84 = LCL_VAR int V10 loc7 u:2 NA (last use) REG NA N377 ( 1, 1) [000085] -c---------- t85 = CNS_INT int 0 REG NA $40 /--* t84 int +--* t85 int N379 ( 6, 3) [000086] N----------- t86 = * NE int REG r8 /--* t86 int N381 (???,???) [001029] ------------ t1029 = * PUTARG_REG int REG r8 N383 ( 3, 2) [000082] ------------ t82 = LCL_VAR ref (AX) V12 loc9 rcx REG rcx $18d /--* t82 ref N385 (???,???) [001030] ------------ t1030 = * PUTARG_REG ref REG rcx N387 ( 1, 1) [000083] ------------ t83 = LCL_VAR int V13 loc10 u:2 r15 (last use) REG r15 $293 /--* t83 int N389 (???,???) [001031] ------------ t1031 = * PUTARG_REG int REG rdx N391 ( 1, 1) [000087] ------------ t87 = LCL_VAR ref V01 arg1 u:1 rsi (last use) REG rsi $c0 /--* t87 ref N393 (???,???) [001032] ------------ t1032 = * PUTARG_REG ref REG r9 /--* t1029 int arg2 in r8 +--* t1030 ref arg0 in rcx +--* t1031 int arg1 in rdx +--* t1032 ref arg3 in r9 N395 ( 29, 17) [000089] --CXG------- t89 = * CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits REG rax $5c7 /--* t89 int N397 ( 29, 17) [000600] DA-XG------- * STORE_LCL_VAR int V51 tmp21 d:3 rax REG rax ------------ BB17 [0A7..0B0) -> BB19 (cond), preds={BB15} succs={BB18,BB19} N401 (???,???) [000930] ------------ IL_OFFSET void IL offset: 0xa7 REG NA N403 ( 1, 1) [000097] ------------ t97 = LCL_VAR int V53 tmp23 u:2 rbp REG rbp N405 ( 1, 1) [000098] -c---------- t98 = CNS_INT int 0 REG NA $40 /--* t97 int +--* t98 int N407 ( 3, 3) [000099] J---G--N---- * LT void REG NA N409 ( 5, 5) [000100] ----G------- * JTRUE void REG NA ------------ BB18 [0B0..0B4) -> BB20 (always), preds={BB17} succs={BB20} N413 (???,???) [000931] ------------ IL_OFFSET void IL offset: 0xb0 REG NA N415 ( 1, 1) [000376] -----------z t376 = LCL_VAR int V10 loc7 u:2 rax (last use) REG rax /--* t376 int N417 ( 5, 4) [000378] DA---------- * STORE_LCL_VAR int V32 tmp2 d:4 rdx REG rdx ------------ BB19 [0B4..0BE), preds={BB17} succs={BB20} N421 (???,???) [000932] ------------ IL_OFFSET void IL offset: 0xb4 REG NA N423 ( 1, 1) [000101] -----------z t101 = LCL_VAR int V10 loc7 u:2 rax (last use) REG rax N425 ( 1, 1) [000104] ------------ t104 = LCL_VAR int V53 tmp23 u:2 rbp REG rbp /--* t101 int +--* t104 int N427 ( 3, 3) [000106] ----G------- t106 = * SUB int REG rdx /--* t106 int N429 ( 7, 6) [000108] DA--G------- * STORE_LCL_VAR int V32 tmp2 d:3 rdx REG rdx ------------ BB20 [0BE..0C4) -> BB45 (cond), preds={BB18,BB19} succs={BB21,BB45} N001 ( 0, 0) [000905] ------------ t905 = PHI_ARG int V32 tmp2 u:4 rdx N002 ( 0, 0) [000904] ------------ t904 = PHI_ARG int V32 tmp2 u:3 rdx /--* t905 int +--* t904 int N003 ( 0, 0) [000879] ------------ t879 = * PHI int /--* t879 int N005 ( 0, 0) [000880] DA---------- * STORE_LCL_VAR int V32 tmp2 d:2 rdx N433 ( 3, 2) [000110] ------------ t110 = LCL_VAR int V32 tmp2 u:2 rdx (last use) REG rdx $244 /--* t110 int N435 ( 7, 5) [000112] DA---------- * STORE_LCL_VAR int V14 loc11 d:2 rax REG rax N437 (???,???) [000933] ------------ IL_OFFSET void IL offset: 0xc0 REG NA N439 ( 1, 1) [000113] ------------ t113 = LCL_VAR int V13 loc10 u:2 r15 REG r15 $293 N441 ( 1, 1) [000114] -c---------- t114 = CNS_INT int 0 REG NA $40 /--* t113 int +--* t114 int N443 ( 3, 3) [000115] J------N---- * NE void REG NA $35a N445 ( 5, 5) [000116] ------------ * JTRUE void REG NA ------------ BB21 [0C4..0D9) -> BB23 (cond), preds={BB20} succs={BB22,BB23} N449 ( 1, 1) [000455] ------------ t455 = LCL_VAR ref V52 tmp22 u:2 rbx REG rbx /--* t455 ref N451 (???,???) [000994] -c---------- t994 = * LEA(b+8) ref REG NA /--* t994 ref N453 ( 3, 3) [000456] ---XG------- t456 = * IND int REG rcx /--* t456 int N455 ( 4, 5) [000358] ---XG------- t358 = * CAST long <- int REG rcx N457 ( 3, 2) [000352] -----------Z t352 = LCL_VAR int V14 loc11 u:2 rax REG rax $244 /--* t352 int N459 ( 4, 4) [000353] ---------U-- t353 = * CAST long <- ulong <- uint REG rdx $486 /--* t353 long +--* t358 long N461 ( 9, 10) [000359] ---XG------- t359 = * SUB long REG rdx /--* t359 long N463 ( 13, 13) [000363] DA-XG------- * STORE_LCL_VAR long V38 tmp8 d:2 NA REG NA N465 ( 1, 1) [000360] ------------ t360 = LCL_VAR ref V01 arg1 u:1 rsi REG rsi $c0 /--* t360 ref N467 (???,???) [001033] ------------ t1033 = * PUTARG_REG ref REG rcx /--* t1033 ref this in rcx N469 ( 15, 8) [000361] --CXG------- t361 = * CALL int FloatingPointType.get_OverflowDecimalExponent REG rax $298 /--* t361 int N471 ( 16, 10) [000366] ---XG------- t366 = * CAST long <- int REG rcx $48b N473 ( 3, 2) [000364] -c---------- t364 = LCL_VAR long V38 tmp8 u:2 NA (last use) REG NA /--* t366 long +--* t364 long N475 ( 20, 13) [000367] J--XG--N---- * GE void REG NA N477 ( 22, 15) [000368] ---XG------- * JTRUE void REG NA ------------ BB22 [0D9..0E3) (return), preds={BB21} succs={} N481 (???,???) [000934] ------------ IL_OFFSET void IL offset: 0xd9 REG NA N483 ( 1, 1) [000370] ------------ t370 = LCL_VAR ref V01 arg1 u:1 rsi REG rsi $c0 /--* t370 ref N485 (???,???) [001034] ------------ t1034 = * PUTARG_REG ref REG rcx N487 ( 1, 1) [001035] ------------ t1035 = LCL_VAR ref V01 arg1 rsi (last use) REG rsi /--* t1035 ref N489 ( 2, 2) [001036] -c---------- t1036 = * LEA(b+0) byref REG NA /--* t1036 byref N491 ( 5, 4) [001037] ------------ t1037 = * IND long REG rax /--* t1037 long N493 ( 6, 5) [001038] -c---------- t1038 = * LEA(b+80) long REG NA /--* t1038 long N495 ( 9, 7) [001039] ------------ t1039 = * IND long REG rax /--* t1039 long N497 ( 10, 8) [001040] -c---------- t1040 = * LEA(b+0) long REG NA /--* t1040 long N499 ( 13, 10) [001041] -c---------- t1041 = * IND long REG NA /--* t1034 ref this in rcx +--* t1041 long control expr N501 ( 21, 10) [000371] --CXG------- t371 = * CALLV ind long FloatingPointType.get_Zero REG rax $457 N503 ( 1, 1) [000369] ------------ t369 = LCL_VAR byref V02 arg2 u:1 rdi (last use) REG rdi $81 /--* t369 byref +--* t371 long N505 (???,???) [000935] -ACXG------- * STOREIND long REG NA N507 ( 1, 1) [000374] ------------ t374 = CNS_INT int 2 REG rax $42 /--* t374 int N509 ( 2, 2) [000524] ------------ * RETURN int REG NA $5c4 ------------ BB45 [???..???) -> BB23 (always), preds={BB20} succs={BB23} N001 ( 3, 2) [001078] -----------Z t1078 = LCL_VAR int V14 loc11 rax REG rax ------------ BB23 [0E3..117) -> BB25 (cond), preds={BB45,BB21} succs={BB24,BB25} N513 ( 3, 2) [000124] -------N---- t124 = LCL_VAR_ADDR byref V15 loc12 rcx * ref V15._bits (offs=0x00) -> V56 tmp26 * int V15._sign (offs=0x08) -> V57 tmp27 REG rcx /--* t124 byref N515 ( 7, 6) [000623] DA--------L- * STORE_LCL_VAR long V79 tmp49 d:2 rcx REG rcx N517 ( 3, 2) [000607] -------N---- t607 = LCL_VAR_ADDR byref V73 tmp43 rdx REG rdx /--* t607 byref N519 ( 3, 3) [000609] DA---------- * STORE_LCL_VAR byref V78 tmp48 d:2 rdx REG rdx N521 ( 1, 1) [000610] ------------ t610 = LCL_VAR byref V78 tmp48 u:2 rdx Zero Fseq[Mantissa] REG rdx $409 N523 ( 1, 1) [000612] -------N---- t612 = LCL_VAR ref V52 tmp22 u:2 rbx (last use) REG rbx /--* t610 byref +--* t612 ref N525 (???,???) [000936] -A---------- * STOREIND ref REG NA N527 ( 1, 1) [000615] ------------ t615 = LCL_VAR byref V78 tmp48 u:2 rdx (last use) REG rdx $409 /--* t615 byref N529 ( 2, 2) [000617] -c---------- t617 = * LEA(b+8) byref REG NA N531 ( 1, 1) [000619] -------N---- t619 = LCL_VAR int V53 tmp23 u:2 rbp (last use) REG rbp /--* t617 byref +--* t619 int N533 (???,???) [000937] -A--------L- * STOREIND int REG NA N535 ( 3, 2) [000624] ------------ t624 = LCL_VAR long V79 tmp49 u:2 rcx (last use) REG rcx $408 /--* t624 long N537 (???,???) [001042] ------------ t1042 = * PUTARG_REG long REG rcx N539 ( 3, 2) [000625] -------N---- t625 = LCL_VAR_ADDR byref V73 tmp43 rdx REG rdx /--* t625 byref N541 (???,???) [001043] ------------ t1043 = * PUTARG_REG byref REG rdx N543 ( 3, 2) [000118] ------------ t118 = LCL_VAR int V08 loc5 u:2 r12 (last use) REG r12 $242 /--* t118 int N545 (???,???) [001044] ------------ t1044 = * PUTARG_REG int REG r8 N547 ( 3, 2) [000119] ------------ t119 = LCL_VAR int V09 loc6 u:2 r13 (last use) REG r13 /--* t119 int N549 (???,???) [001045] ------------ t1045 = * PUTARG_REG int REG r9 /--* t1042 long arg0 in rcx +--* t1043 byref arg1 in rdx +--* t1044 int arg2 in r8 +--* t1045 int arg3 in r9 N551 ( 53, 37) [000120] S-CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger REG NA $VN.Void N553 (???,???) [000938] ------------ IL_OFFSET void IL offset: 0xef REG NA N555 ( 2, 10) [000131] ------------ t131 = CNS_INT long 0x7ff815262aa0 REG rcx $102 /--* t131 long N557 (???,???) [001046] ------------ t1046 = * PUTARG_REG long REG rcx N559 ( 1, 4) [000132] ------------ t132 = CNS_INT int 173 REG rdx $58 /--* t132 int N561 (???,???) [001047] ------------ t1047 = * PUTARG_REG int REG rdx /--* t1046 long arg0 in rcx +--* t1047 int arg1 in rdx N563 ( 17, 21) [000133] H-CXG------- t133 = * CALL help long HELPER.CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE REG rax $48d N565 ( 2, 10) [000634] I----------- t634 = CNS_INT(h) long 0xd1ffab1e static Fseq[BigOne] REG rcx $4c2 /--* t634 long N567 ( 4, 12) [000633] n---G------- t633 = * IND ref REG rcx N569 ( 1, 1) [000635] -c---------- t635 = CNS_INT long 8 Fseq[#FirstElem] REG NA $101 /--* t633 ref +--* t635 long N571 ( 6, 14) [000632] ----G------- t632 = * ADD byref REG rcx /--* t632 byref N573 ( 6, 14) [000637] DA--G------- * STORE_LCL_VAR byref V80 tmp50 d:2 rcx REG rcx N575 ( 1, 1) [000639] ------------ t639 = LCL_VAR byref V80 tmp50 u:2 rcx Zero Fseq[_bits] REG rcx /--* t639 byref N577 ( 3, 2) [000640] ---X-------- t640 = * IND ref REG rdx /--* t640 ref N579 ( 7, 5) [000641] DA-XG------- * STORE_LCL_VAR ref (AX) V58 tmp28 NA REG NA N581 ( 1, 1) [000644] ------------ t644 = LCL_VAR byref V80 tmp50 u:2 rcx (last use) REG rcx /--* t644 byref N583 ( 2, 2) [000646] -c---------- t646 = * LEA(b+8) byref REG NA /--* t646 byref N585 ( 4, 4) [000647] ---X-------- t647 = * IND int REG rcx /--* t647 int N587 ( 8, 7) [000648] DA-XG------- * STORE_LCL_VAR int (AX) V59 tmp29 NA REG NA N589 (???,???) [000939] ------------ IL_OFFSET void IL offset: 0xf6 REG NA N591 ( 3, 2) [000138] -------N---- t138 = LCL_VAR_ADDR byref V16 loc13 rcx * ref V16._bits (offs=0x00) -> V58 tmp28 * int V16._sign (offs=0x08) -> V59 tmp29 REG rcx /--* t138 byref N593 (???,???) [001048] ------------ t1048 = * PUTARG_REG byref REG rcx N595 ( 3, 2) [000140] -----------z t140 = LCL_VAR int V14 loc11 u:2 rdx (last use) REG rdx $244 /--* t140 int N597 (???,???) [001049] ------------ t1049 = * PUTARG_REG int REG rdx /--* t1048 byref arg0 in rcx +--* t1049 int arg1 in rdx N599 ( 20, 12) [000141] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen REG NA $VN.Void N601 (???,???) [000940] ------------ IL_OFFSET void IL offset: 0xff REG NA N603 ( 3, 2) [000653] -------N---- t653 = LCL_VAR ref (AX) V56 tmp26 rcx REG rcx $184 /--* t653 ref N605 ( 7, 5) [000654] DA--G------- * STORE_LCL_VAR ref V64 tmp34 d:2 rcx REG rcx N607 ( 3, 2) [000656] -------N---- t656 = LCL_VAR int (AX) V57 tmp27 rdx REG rdx $246 /--* t656 int N609 ( 7, 5) [000657] DA--G------- * STORE_LCL_VAR int V65 tmp35 d:2 rdx REG rdx N611 (???,???) [000941] ------------ IL_OFFSET void IL offset: 0xff REG NA N613 ( 3, 2) [000663] -------N---- t663 = LCL_VAR_ADDR byref V76 tmp46 rax REG rax /--* t663 byref N615 ( 3, 3) [000665] DA---------- * STORE_LCL_VAR byref V81 tmp51 d:2 rax REG rax N617 ( 1, 1) [000666] ------------ t666 = LCL_VAR byref V81 tmp51 u:2 rax Zero Fseq[_bits] REG rax $40e N619 ( 3, 2) [000668] -------N---- t668 = LCL_VAR ref V64 tmp34 u:2 rcx (last use) REG rcx $184 /--* t666 byref +--* t668 ref N621 (???,???) [000942] -A---------- * STOREIND ref REG NA N623 ( 1, 1) [000671] ------------ t671 = LCL_VAR byref V81 tmp51 u:2 rax (last use) REG rax $40e /--* t671 byref N625 ( 2, 2) [000673] -c---------- t673 = * LEA(b+8) byref REG NA N627 ( 3, 2) [000675] -------N---- t675 = LCL_VAR int V65 tmp35 u:2 rdx (last use) REG rdx $246 /--* t673 byref +--* t675 int N629 (???,???) [000943] -A--------L- * STOREIND int REG NA N631 ( 3, 2) [000678] -------N---- t678 = LCL_VAR_ADDR byref V76 tmp46 rcx REG rcx /--* t678 byref N633 (???,???) [001050] ------------ t1050 = * PUTARG_REG byref REG rcx N635 ( 3, 3) [000462] ------------ t462 = LCL_VAR_ADDR long V45 tmp15 rdx REG rdx $449 /--* t462 long N637 (???,???) [001051] ------------ t1051 = * PUTARG_REG long REG rdx /--* t1050 byref arg0 in rcx +--* t1051 long arg1 in rdx N639 ( 41, 28) [000463] --CXG------- t463 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits REG rax $29f /--* t463 int N641 ( 45, 31) [000468] DA-XG------- * STORE_LCL_VAR int V43 tmp13 d:2 rbx REG rbx N643 (???,???) [000944] ------------ IL_OFFSET void IL offset: 0xff REG NA N645 ( 1, 1) [000473] ------------ t473 = CNS_INT ref null REG rcx $VN.Null /--* t473 ref N647 ( 5, 4) [000475] DA--G------- * STORE_LCL_VAR ref (AX) V45 tmp15 NA REG NA N649 ( 3, 2) [000469] ------------ t469 = LCL_VAR int V43 tmp13 u:2 rbx (last use) REG rbx $29f /--* t469 int N651 ( 7, 5) [000148] DA---------- * STORE_LCL_VAR int V17 loc14 d:2 rbx REG rbx N653 (???,???) [000945] ------------ IL_OFFSET void IL offset: 0x108 REG NA N655 ( 3, 2) [000682] -------N---- t682 = LCL_VAR ref (AX) V58 tmp28 rcx REG rcx $185 /--* t682 ref N657 ( 7, 5) [000683] DA--G------- * STORE_LCL_VAR ref V66 tmp36 d:2 rcx REG rcx N659 ( 3, 2) [000685] -------N---- t685 = LCL_VAR int (AX) V59 tmp29 rdx REG rdx $247 /--* t685 int N661 ( 7, 5) [000686] DA--G------- * STORE_LCL_VAR int V67 tmp37 d:2 rdx REG rdx N663 (???,???) [000946] ------------ IL_OFFSET void IL offset: 0x108 REG NA N665 ( 3, 2) [000692] -------N---- t692 = LCL_VAR_ADDR byref V76 tmp46 rax REG rax /--* t692 byref N667 ( 3, 3) [000694] DA---------- * STORE_LCL_VAR byref V82 tmp52 d:2 rax REG rax N669 ( 1, 1) [000695] ------------ t695 = LCL_VAR byref V82 tmp52 u:2 rax Zero Fseq[_bits] REG rax $411 N671 ( 3, 2) [000697] -------N---- t697 = LCL_VAR ref V66 tmp36 u:2 rcx (last use) REG rcx $185 /--* t695 byref +--* t697 ref N673 (???,???) [000947] -A---------- * STOREIND ref REG NA N675 ( 1, 1) [000700] ------------ t700 = LCL_VAR byref V82 tmp52 u:2 rax (last use) REG rax $411 /--* t700 byref N677 ( 2, 2) [000702] -c---------- t702 = * LEA(b+8) byref REG NA N679 ( 3, 2) [000704] -------N---- t704 = LCL_VAR int V67 tmp37 u:2 rdx (last use) REG rdx $247 /--* t702 byref +--* t704 int N681 (???,???) [000948] -A--------L- * STOREIND int REG NA N683 ( 3, 2) [000707] -------N---- t707 = LCL_VAR_ADDR byref V76 tmp46 rcx REG rcx /--* t707 byref N685 (???,???) [001052] ------------ t1052 = * PUTARG_REG byref REG rcx N687 ( 3, 3) [000480] ------------ t480 = LCL_VAR_ADDR long V48 tmp18 rdx REG rdx $44b /--* t480 long N689 (???,???) [001053] ------------ t1053 = * PUTARG_REG long REG rdx /--* t1052 byref arg0 in rcx +--* t1053 long arg1 in rdx N691 ( 41, 28) [000481] --CXG------- t481 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits REG rax $2a3 /--* t481 int N693 ( 45, 31) [000486] DA-XG------- * STORE_LCL_VAR int V46 tmp16 d:2 rax REG rax N695 (???,???) [000949] ------------ IL_OFFSET void IL offset: 0x108 REG NA N697 ( 1, 1) [000491] ------------ t491 = CNS_INT ref null REG rcx $VN.Null /--* t491 ref N699 ( 5, 4) [000493] DA--G------- * STORE_LCL_VAR ref (AX) V48 tmp18 NA REG NA N701 ( 3, 2) [000487] ------------ t487 = LCL_VAR int V46 tmp16 u:2 rax (last use) REG rax $2a3 /--* t487 int N703 ( 7, 5) [000155] DA---------- * STORE_LCL_VAR int V18 loc15 d:2 rax REG rax N705 (???,???) [000950] ------------ IL_OFFSET void IL offset: 0x111 REG NA N707 ( 3, 2) [000156] ------------ t156 = LCL_VAR int V18 loc15 u:2 rax REG rax $2a3 N709 ( 3, 2) [000157] ------------ t157 = LCL_VAR int V17 loc14 u:2 rbx REG rbx $29f /--* t156 int +--* t157 int N711 ( 7, 5) [000158] N------N-U-- * GT void REG NA $35f N713 ( 9, 7) [000159] ------------ * JTRUE void REG NA ------------ BB24 [117..11A) -> BB26 (always), preds={BB23} succs={BB26} N717 (???,???) [000951] ------------ IL_OFFSET void IL offset: 0x117 REG NA N719 ( 1, 1) [000348] ------------ t348 = CNS_INT int 0 REG rbp $40 /--* t348 int N721 ( 5, 4) [000350] DA---------- * STORE_LCL_VAR int V33 tmp3 d:4 rbp REG rbp ------------ BB25 [11A..11F), preds={BB23} succs={BB26} N725 (???,???) [000952] ------------ IL_OFFSET void IL offset: 0x11a REG NA N727 ( 3, 2) [000160] ------------ t160 = LCL_VAR int V18 loc15 u:2 rax (last use) REG rax $2a3 N729 ( 3, 2) [000161] ------------ t161 = LCL_VAR int V17 loc14 u:2 rbx (last use) REG rbx $29f /--* t160 int +--* t161 int N731 ( 7, 5) [000162] ------------ t162 = * SUB int REG rbp $360 /--* t162 int N733 ( 11, 8) [000164] DA---------- * STORE_LCL_VAR int V33 tmp3 d:3 rbp REG rbp ------------ BB26 [11F..126) -> BB28 (cond), preds={BB24,BB25} succs={BB27,BB28} N001 ( 0, 0) [000903] ------------ t903 = PHI_ARG int V33 tmp3 u:4 rbp $40 N002 ( 0, 0) [000902] ------------ t902 = PHI_ARG int V33 tmp3 u:3 rbp $360 /--* t903 int +--* t902 int N003 ( 0, 0) [000876] ------------ t876 = * PHI int /--* t876 int N005 ( 0, 0) [000877] DA---------- * STORE_LCL_VAR int V33 tmp3 d:2 rbp N737 ( 3, 2) [000166] ------------ t166 = LCL_VAR int V33 tmp3 u:2 rbp (last use) REG rbp $248 /--* t166 int N739 ( 3, 3) [000168] DA---------- * STORE_LCL_VAR int V19 loc16 d:2 rbp REG rbp N741 (???,???) [000953] ------------ IL_OFFSET void IL offset: 0x121 REG NA N743 ( 3, 2) [000169] ------------ t169 = LCL_VAR int V19 loc16 u:2 rbp REG rbp $248 N745 ( 1, 1) [000170] -c---------- t170 = CNS_INT int 0 REG NA $40 /--* t169 int +--* t170 int N747 ( 5, 4) [000171] N------N---- * EQ void REG NA $361 N749 ( 7, 6) [000172] ------------ * JTRUE void REG NA ------------ BB27 [126..12F), preds={BB26} succs={BB28} N753 (???,???) [000954] ------------ IL_OFFSET void IL offset: 0x126 REG NA N755 ( 3, 2) [000344] -------N---- t344 = LCL_VAR_ADDR byref V15 loc12 rcx * ref V15._bits (offs=0x00) -> V56 tmp26 * int V15._sign (offs=0x08) -> V57 tmp27 REG rcx /--* t344 byref N757 (???,???) [001054] ------------ t1054 = * PUTARG_REG byref REG rcx N759 ( 1, 1) [000346] ------------ t346 = LCL_VAR int V19 loc16 u:2 rbp REG rbp $248 /--* t346 int N761 (???,???) [001055] ------------ t1055 = * PUTARG_REG int REG rdx /--* t1054 byref arg0 in rcx +--* t1055 int arg1 in rdx N763 ( 18, 11) [000347] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft REG NA $VN.Void ------------ BB28 [12F..13E) -> BB32 (cond), preds={BB26,BB27} succs={BB29,BB32} N767 (???,???) [000955] ------------ IL_OFFSET void IL offset: 0x12f REG NA N769 ( 3, 2) [000173] ------------ t173 = LCL_VAR int V03 loc0 u:2 r14 (last use) REG r14 $348 N771 ( 1, 1) [000174] ------------ t174 = LCL_VAR int V13 loc10 u:2 r15 REG r15 $293 /--* t173 int +--* t174 int N773 ( 5, 4) [000175] ------------ t175 = * SUB int REG r14 $362 /--* t175 int N775 ( 9, 7) [000177] DA---------- * STORE_LCL_VAR int V20 loc17 d:2 r14 REG r14 N777 (???,???) [000956] ------------ IL_OFFSET void IL offset: 0x135 REG NA N779 ( 3, 2) [000178] ------------ t178 = LCL_VAR int V20 loc17 u:2 r14 REG r14 $362 /--* t178 int N781 ( 7, 5) [000180] DA---------- * STORE_LCL_VAR int V21 loc18 d:2 rbx REG rbx N783 (???,???) [000957] ------------ IL_OFFSET void IL offset: 0x139 REG NA N785 ( 1, 1) [000181] ------------ t181 = LCL_VAR int V13 loc10 u:2 r15 REG r15 $293 N787 ( 1, 1) [000182] -c---------- t182 = CNS_INT int 0 REG NA $40 /--* t181 int +--* t182 int N789 ( 3, 3) [000183] N------N---- * EQ void REG NA $363 N791 ( 5, 5) [000184] ------------ * JTRUE void REG NA ------------ BB29 [13E..144) -> BB31 (cond), preds={BB28} succs={BB30,BB31} N795 (???,???) [000958] ------------ IL_OFFSET void IL offset: 0x13e REG NA N797 ( 1, 1) [000326] ------------ t326 = LCL_VAR int V19 loc16 u:2 rbp REG rbp $248 N799 ( 3, 2) [000327] ------------ t327 = LCL_VAR int V20 loc17 u:2 r14 REG r14 $362 /--* t326 int +--* t327 int N801 ( 5, 4) [000328] N------N-U-- * LE void REG NA $364 N803 ( 7, 6) [000329] ------------ * JTRUE void REG NA ------------ BB30 [144..155) -> BB44 (always), preds={BB29} succs={BB44} N807 (???,???) [000959] ------------ IL_OFFSET void IL offset: 0x144 REG NA N809 ( 1, 1) [000341] ------------ t341 = LCL_VAR byref V02 arg2 u:1 rdi (last use) REG rdi $81 /--* t341 byref N811 (???,???) [001056] ------------ * PUTARG_STK [+0x20] void REG NA N813 ( 1, 1) [000339] ------------ t339 = CNS_INT int 1 REG r8 $41 /--* t339 int N815 (???,???) [001057] ------------ t1057 = * PUTARG_REG int REG r8 N817 ( 3, 2) [000335] ------------ t335 = LCL_VAR ref (AX) V12 loc9 rcx REG rcx $18c /--* t335 ref N819 (???,???) [001058] ------------ t1058 = * PUTARG_REG ref REG rcx N821 ( 1, 1) [000336] ------------ t336 = LCL_VAR int V13 loc10 u:2 r15 (last use) REG r15 $293 /--* t336 int N823 (???,???) [001059] ------------ t1059 = * PUTARG_REG int REG rdx N825 ( 1, 1) [000340] ------------ t340 = LCL_VAR ref V01 arg1 u:1 rsi (last use) REG rsi $c0 /--* t340 ref N827 (???,???) [001060] ------------ t1060 = * PUTARG_REG ref REG r9 /--* t1057 int arg2 in r8 +--* t1058 ref arg0 in rcx +--* t1059 int arg1 in rdx +--* t1060 ref arg3 in r9 N829 ( 24, 15) [000342] --CXG------- t342 = * CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits REG rax $5c2 /--* t342 int N831 ( 24, 15) [000717] DA-XG------- * STORE_LCL_VAR int V51 tmp21 d:5 rax REG rax ------------ BB31 [155..15C), preds={BB29} succs={BB32} N835 (???,???) [000960] ------------ IL_OFFSET void IL offset: 0x155 REG NA N837 ( 3, 2) [000330] ------------ t330 = LCL_VAR int V20 loc17 u:2 r14 REG r14 $362 N839 ( 1, 1) [000331] ------------ t331 = LCL_VAR int V19 loc16 u:2 rbp REG rbp $248 /--* t330 int +--* t331 int N841 ( 5, 4) [000332] ------------ t332 = * SUB int REG rbx $365 /--* t332 int N843 ( 9, 7) [000334] DA---------- * STORE_LCL_VAR int V21 loc18 d:4 rbx REG rbx ------------ BB32 [15C..167) -> BB34 (cond), preds={BB28,BB31} succs={BB33,BB34} N001 ( 0, 0) [000900] ------------ t900 = PHI_ARG int V21 loc18 u:4 rbx $365 N002 ( 0, 0) [000888] ------------ t888 = PHI_ARG int V21 loc18 u:2 rbx $362 /--* t900 int +--* t888 int N003 ( 0, 0) [000873] ------------ t873 = * PHI int /--* t873 int N005 ( 0, 0) [000874] DA---------- * STORE_LCL_VAR int V21 loc18 d:3 rbx N847 (???,???) [000961] ------------ IL_OFFSET void IL offset: 0x15c REG NA N849 ( 3, 2) [000719] -------N---- t719 = LCL_VAR ref (AX) V56 tmp26 rcx REG rcx $186 /--* t719 ref N851 ( 7, 5) [000720] DA--G------- * STORE_LCL_VAR ref (AX) V68 tmp38 NA REG NA N853 ( 3, 2) [000722] -------N---- t722 = LCL_VAR int (AX) V57 tmp27 rcx REG rcx $24a /--* t722 int N855 ( 7, 5) [000723] DA--G------- * STORE_LCL_VAR int (AX) V69 tmp39 NA REG NA N857 (???,???) [000962] ------------ IL_OFFSET void IL offset: 0x15c REG NA N859 ( 3, 2) [000726] -------N---- t726 = LCL_VAR ref (AX) V58 tmp28 rcx REG rcx $187 /--* t726 ref N861 ( 7, 5) [000727] DA--G------- * STORE_LCL_VAR ref V70 tmp40 d:2 rcx REG rcx N863 ( 3, 2) [000729] -------N---- t729 = LCL_VAR int (AX) V59 tmp29 rdx REG rdx $24b /--* t729 int N865 ( 7, 5) [000730] DA--G------- * STORE_LCL_VAR int V71 tmp41 d:2 rdx REG rdx N867 ( 3, 2) [000496] -------N---- t496 = LCL_VAR_ADDR byref V49 tmp19 rax * ref V49._bits (offs=0x00) -> V68 tmp38 * int V49._sign (offs=0x08) -> V69 tmp39 REG rax /--* t496 byref N869 ( 7, 6) [000752] DA--------L- * STORE_LCL_VAR byref V84 tmp54 d:2 rax REG rax N871 ( 3, 2) [000736] -------N---- t736 = LCL_VAR_ADDR byref V76 tmp46 r8 REG r8 /--* t736 byref N873 ( 3, 3) [000738] DA---------- * STORE_LCL_VAR byref V83 tmp53 d:2 r8 REG r8 N875 ( 1, 1) [000739] ------------ t739 = LCL_VAR byref V83 tmp53 u:2 r8 Zero Fseq[_bits] REG r8 $417 N877 ( 3, 2) [000741] -------N---- t741 = LCL_VAR ref V70 tmp40 u:2 rcx (last use) REG rcx $187 /--* t739 byref +--* t741 ref N879 (???,???) [000963] -A---------- * STOREIND ref REG NA N881 ( 1, 1) [000744] ------------ t744 = LCL_VAR byref V83 tmp53 u:2 r8 (last use) REG r8 $417 /--* t744 byref N883 ( 2, 2) [000746] -c---------- t746 = * LEA(b+8) byref REG NA N885 ( 3, 2) [000748] -------N---- t748 = LCL_VAR int V71 tmp41 u:2 rdx (last use) REG rdx $24b /--* t746 byref +--* t748 int N887 (???,???) [000964] -A--------L- * STOREIND int REG NA N889 ( 3, 2) [000753] ------------ t753 = LCL_VAR byref V84 tmp54 u:2 rax (last use) REG rax $415 /--* t753 byref N891 (???,???) [001061] ------------ t1061 = * PUTARG_REG byref REG rcx N893 ( 3, 2) [000754] -------N---- t754 = LCL_VAR_ADDR byref V76 tmp46 rdx REG rdx /--* t754 byref N895 (???,???) [001062] ------------ t1062 = * PUTARG_REG byref REG rdx /--* t1061 byref this in rcx +--* t1062 byref arg1 in rdx N897 ( 48, 34) [000499] --CXG------- t499 = * CALL int System.Numerics.BigInteger.CompareTo REG rax $2ae N899 ( 1, 1) [000502] -c---------- t502 = CNS_INT int 0 REG NA $40 /--* t499 int +--* t502 int N901 ( 50, 36) [000503] J--XG--N---- * LT void REG NA $367 N903 ( 52, 38) [000195] ---XG------- * JTRUE void REG NA ------------ BB33 [167..16B) -> BB35 (always), preds={BB32} succs={BB35} N907 (???,???) [000965] ------------ IL_OFFSET void IL offset: 0x167 REG NA N909 ( 1, 1) [000322] ------------ t322 = LCL_VAR int V19 loc16 u:2 rbp (last use) REG rbp $248 /--* t322 int N911 ( 5, 4) [000324] DA---------- * STORE_LCL_VAR int V34 tmp4 d:4 rbp REG rbp ------------ BB34 [16B..16F), preds={BB32} succs={BB35} N915 (???,???) [000966] ------------ IL_OFFSET void IL offset: 0x16b REG NA N917 ( 1, 1) [000196] ------------ t196 = LCL_VAR int V19 loc16 u:2 rbp (last use) REG rbp $248 N919 ( 1, 1) [000197] -c---------- t197 = CNS_INT int 1 REG NA $41 /--* t196 int +--* t197 int N921 ( 3, 3) [000198] ------------ t198 = * ADD int REG rbp $368 /--* t198 int N923 ( 7, 6) [000200] DA---------- * STORE_LCL_VAR int V34 tmp4 d:3 rbp REG rbp ------------ BB35 [16F..1A4) -> BB40 (cond), preds={BB33,BB34} succs={BB36,BB40} N001 ( 0, 0) [000899] ------------ t899 = PHI_ARG int V34 tmp4 u:4 rbp $248 N002 ( 0, 0) [000898] ------------ t898 = PHI_ARG int V34 tmp4 u:3 rbp $368 /--* t899 int +--* t898 int N003 ( 0, 0) [000870] ------------ t870 = * PHI int /--* t870 int N005 ( 0, 0) [000871] DA---------- * STORE_LCL_VAR int V34 tmp4 d:2 rbp N927 ( 3, 2) [000202] ------------ t202 = LCL_VAR int V34 tmp4 u:2 rbp (last use) REG rbp $24c /--* t202 int N929 ( 7, 5) [000204] DA---------- * STORE_LCL_VAR int V22 loc19 d:2 rbp REG rbp N931 (???,???) [000967] ------------ IL_OFFSET void IL offset: 0x171 REG NA N933 ( 3, 2) [000205] -------N---- t205 = LCL_VAR_ADDR byref V15 loc12 rcx * ref V15._bits (offs=0x00) -> V56 tmp26 * int V15._sign (offs=0x08) -> V57 tmp27 REG rcx /--* t205 byref N935 (???,???) [001063] ------------ t1063 = * PUTARG_REG byref REG rcx N937 ( 3, 2) [000207] ------------ t207 = LCL_VAR int V21 loc18 u:3 rbx (last use) REG rbx $249 /--* t207 int N939 (???,???) [001064] ------------ t1064 = * PUTARG_REG int REG rdx /--* t1063 byref arg0 in rcx +--* t1064 int arg1 in rdx N941 ( 20, 12) [000208] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft REG NA $VN.Void N943 (???,???) [000968] ------------ IL_OFFSET void IL offset: 0x17a REG NA N945 ( 3, 2) [000219] -------N---- t219 = LCL_VAR_ADDR byref V35 tmp5 rcx * ref V35._bits (offs=0x00) -> V62 tmp32 * int V35._sign (offs=0x08) -> V63 tmp33 REG rcx /--* t219 byref N947 ( 7, 6) [000797] DA--------L- * STORE_LCL_VAR long V88 tmp58 d:2 rcx REG rcx N949 ( 3, 2) [000762] -------N---- t762 = LCL_VAR_ADDR byref V76 tmp46 rdx REG rdx /--* t762 byref N951 ( 3, 3) [000764] DA---------- * STORE_LCL_VAR byref V85 tmp55 d:2 rdx REG rdx N953 ( 1, 1) [000765] ------------ t765 = LCL_VAR byref V85 tmp55 u:2 rdx Zero Fseq[_bits] REG rdx $41c N955 ( 3, 2) [000767] -------N---- t767 = LCL_VAR ref (AX) V56 tmp26 r8 REG r8 $188 /--* t765 byref +--* t767 ref N957 (???,???) [000969] -A--G------- * STOREIND ref REG NA N959 ( 1, 1) [000770] ------------ t770 = LCL_VAR byref V85 tmp55 u:2 rdx (last use) REG rdx $41c /--* t770 byref N961 ( 2, 2) [000772] -c---------- t772 = * LEA(b+8) byref REG NA N963 ( 3, 2) [000774] -------N---- t774 = LCL_VAR int (AX) V57 tmp27 r8 REG r8 $24d /--* t772 byref +--* t774 int N965 (???,???) [000970] -A--G-----L- * STOREIND int REG NA N967 ( 3, 2) [000781] -------N---- t781 = LCL_VAR_ADDR byref V86 tmp56 rdx REG rdx /--* t781 byref N969 ( 3, 3) [000783] DA---------- * STORE_LCL_VAR byref V87 tmp57 d:2 rdx REG rdx N971 ( 1, 1) [000784] ------------ t784 = LCL_VAR byref V87 tmp57 u:2 rdx Zero Fseq[_bits] REG rdx $41e N973 ( 3, 2) [000786] -------N---- t786 = LCL_VAR ref (AX) V58 tmp28 r8 REG r8 $189 /--* t784 byref +--* t786 ref N975 (???,???) [000971] -A--G------- * STOREIND ref REG NA N977 ( 1, 1) [000789] ------------ t789 = LCL_VAR byref V87 tmp57 u:2 rdx (last use) REG rdx $41e /--* t789 byref N979 ( 2, 2) [000791] -c---------- t791 = * LEA(b+8) byref REG NA N981 ( 3, 2) [000793] -------N---- t793 = LCL_VAR int (AX) V59 tmp29 r8 REG r8 $24e /--* t791 byref +--* t793 int N983 (???,???) [000972] -A--G-----L- * STOREIND int REG NA N985 ( 3, 2) [000798] ------------ t798 = LCL_VAR long V88 tmp58 u:2 rcx (last use) REG rcx $41b /--* t798 long N987 (???,???) [001065] ------------ t1065 = * PUTARG_REG long REG rcx N989 ( 3, 2) [000799] -------N---- t799 = LCL_VAR_ADDR byref V76 tmp46 rdx REG rdx /--* t799 byref N991 (???,???) [001066] ------------ t1066 = * PUTARG_REG byref REG rdx N993 ( 3, 2) [000801] -------N---- t801 = LCL_VAR_ADDR byref V86 tmp56 r8 REG r8 /--* t801 byref N995 (???,???) [001067] ------------ t1067 = * PUTARG_REG byref REG r8 N997 ( 3, 2) [000211] -------N---- t211 = LCL_VAR_ADDR byref V23 loc20 r9 * ref V23._bits (offs=0x00) -> V60 tmp30 * int V23._sign (offs=0x08) -> V61 tmp31 REG r9 /--* t211 byref N999 (???,???) [001068] ------------ t1068 = * PUTARG_REG byref REG r9 /--* t1065 long arg0 in rcx +--* t1066 byref arg1 in rdx +--* t1067 byref arg2 in r8 +--* t1068 byref arg3 in r9 N1001 ( 78, 56) [000213] S-CXG------- * CALL void System.Numerics.BigInteger.DivRem REG NA $VN.Void N1003 ( 3, 2) [000808] -------N---- t808 = LCL_VAR_ADDR byref V76 tmp46 rcx REG rcx /--* t808 byref N1005 ( 3, 3) [000810] DA---------- * STORE_LCL_VAR byref V89 tmp59 d:2 rcx REG rcx N1007 ( 1, 1) [000811] ------------ t811 = LCL_VAR byref V89 tmp59 u:2 rcx Zero Fseq[_bits] REG rcx $423 N1009 ( 3, 2) [000813] -------N---- t813 = LCL_VAR ref (AX) V62 tmp32 rax REG rax $18a /--* t811 byref +--* t813 ref N1011 (???,???) [000973] -A--G------- * STOREIND ref REG NA N1013 ( 1, 1) [000816] ------------ t816 = LCL_VAR byref V89 tmp59 u:2 rcx (last use) REG rcx $423 /--* t816 byref N1015 ( 2, 2) [000818] -c---------- t818 = * LEA(b+8) byref REG NA N1017 ( 3, 2) [000820] -------N---- t820 = LCL_VAR int (AX) V63 tmp33 rax REG rax $24f /--* t818 byref +--* t820 int N1019 (???,???) [000974] -A--G-----L- * STOREIND int REG NA N1021 ( 3, 2) [000823] -------N---- t823 = LCL_VAR_ADDR byref V76 tmp46 rcx REG rcx /--* t823 byref N1023 (???,???) [001069] ------------ t1069 = * PUTARG_REG byref REG rcx /--* t1069 byref arg0 in rcx N1025 ( 38, 24) [000218] --CXG------- t218 = * CALL long System.Numerics.BigInteger.op_Explicit REG rax $450 /--* t218 long N1027 ( 38, 24) [000226] DA-XG------- * STORE_LCL_VAR long V24 loc21 d:2 rbx REG rbx N1029 ( 3, 2) [000514] -c---------- t514 = LCL_VAR int (AX) V61 tmp31 NA REG NA $250 N1031 ( 1, 1) [000515] -c---------- t515 = CNS_INT int 0 REG NA $40 /--* t514 int +--* t515 int N1033 ( 8, 4) [000516] ----G------- t516 = * EQ int REG r12 $369 /--* t516 int N1035 ( 12, 7) [000232] DA--G------- * STORE_LCL_VAR int V25 loc22 d:2 r12 REG r12 N1037 ( 1, 1) [000233] ------------ t233 = LCL_VAR long V24 loc21 u:2 rbx REG rbx $450 /--* t233 long N1039 (???,???) [001070] ------------ t1070 = * PUTARG_REG long REG rcx /--* t1070 long arg0 in rcx N1041 ( 15, 7) [000234] --CXG------- t234 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits REG rax $2b4 /--* t234 int N1043 ( 19, 10) [000237] DA-XG------- * STORE_LCL_VAR int V26 loc23 d:2 rax REG rax N1045 (???,???) [000975] ------------ IL_OFFSET void IL offset: 0x19e REG NA N1047 ( 3, 2) [000238] ------------ t238 = LCL_VAR int V26 loc23 u:2 rax REG rax $2b4 N1049 ( 3, 2) [000239] ------------ t239 = LCL_VAR int V20 loc17 u:2 r14 REG r14 $362 /--* t238 int +--* t239 int N1051 ( 7, 5) [000240] N------N-U-- * LE void REG NA $36a N1053 ( 9, 7) [000241] ------------ * JTRUE void REG NA ------------ BB36 [1A4..1AF) -> BB38 (cond), preds={BB35} succs={BB37,BB38} N1057 (???,???) [000976] ------------ IL_OFFSET void IL offset: 0x1a4 REG NA N1059 ( 3, 2) [000282] ------------ t282 = LCL_VAR int V26 loc23 u:2 rax (last use) REG rax $2b4 N1061 ( 3, 2) [000283] ------------ t283 = LCL_VAR int V20 loc17 u:2 r14 REG r14 $362 /--* t282 int +--* t283 int N1063 ( 7, 5) [000284] ------------ t284 = * SUB int REG rax $36b /--* t284 int N1065 ( 11, 8) [000286] DA---------- * STORE_LCL_VAR int V29 loc26 d:2 rax REG rax N1067 (???,???) [000977] ------------ IL_OFFSET void IL offset: 0x1ab REG NA N1069 ( 3, 2) [000287] ------------ t287 = LCL_VAR int V25 loc22 u:2 r12 (last use) REG r12 $369 N1071 ( 1, 1) [000288] -c---------- t288 = CNS_INT int 0 REG NA $40 /--* t287 int +--* t288 int N1073 ( 5, 4) [000289] J------N---- * EQ void REG NA $36c N1075 ( 7, 6) [000290] ------------ * JTRUE void REG NA ------------ BB37 [1AF..1C3) -> BB39 (always), preds={BB36} succs={BB39} N1079 (???,???) [000978] ------------ IL_OFFSET void IL offset: 0x1af REG NA N1081 ( 1, 1) [000305] ------------ t305 = LCL_VAR long V24 loc21 u:2 rbx REG rbx $450 N1083 ( 3, 2) [000308] ------------ t308 = LCL_VAR int V29 loc26 u:2 rax REG rax $36b N1085 ( 1, 1) [000307] ------------ t307 = CNS_INT long 1 REG rdx $103 /--* t307 long +--* t308 int N1087 ( 10, 6) [000311] ------------ t311 = * LSH long REG rdx $48e N1089 ( 1, 1) [000313] -c---------- t313 = CNS_INT long -1 REG NA $104 /--* t311 long +--* t313 long N1091 ( 12, 8) [000314] ------------ t314 = * ADD long REG rdx $48f /--* t305 long +--* t314 long N1093 ( 19, 12) [000318] ------------ t318 = * TEST_EQ int REG rcx $36e /--* t318 int N1095 ( 23, 15) [000320] DA---------- * STORE_LCL_VAR int V37 tmp7 d:4 rcx REG rcx ------------ BB38 [1C3..1C4), preds={BB36} succs={BB39} N1099 (???,???) [000979] ------------ IL_OFFSET void IL offset: 0x1c3 REG NA N1101 ( 1, 1) [000291] ------------ t291 = CNS_INT int 0 REG rcx $40 /--* t291 int N1103 ( 5, 4) [000293] DA---------- * STORE_LCL_VAR int V37 tmp7 d:3 rcx REG rcx ------------ BB39 [1C4..1D0), preds={BB37,BB38} succs={BB40} N001 ( 0, 0) [000897] ------------ t897 = PHI_ARG int V37 tmp7 u:4 rcx $36e N002 ( 0, 0) [000896] ------------ t896 = PHI_ARG int V37 tmp7 u:3 rcx $40 /--* t897 int +--* t896 int N003 ( 0, 0) [000867] ------------ t867 = * PHI int /--* t867 int N005 ( 0, 0) [000868] DA---------- * STORE_LCL_VAR int V37 tmp7 d:2 rcx N1107 ( 3, 2) [000295] ------------ t295 = LCL_VAR int V37 tmp7 u:2 rcx (last use) REG rcx $251 /--* t295 int N1109 ( 4, 4) [000826] ------------ t826 = * CAST int <- bool <- int REG r12 $36f /--* t826 int N1111 ( 8, 7) [000297] DA---------- * STORE_LCL_VAR int V25 loc22 d:4 r12 REG r12 N1113 (???,???) [000980] ------------ IL_OFFSET void IL offset: 0x1c6 REG NA N1115 ( 1, 1) [000298] ------------ t298 = LCL_VAR long V24 loc21 u:2 rbx (last use) REG rbx $450 N1117 ( 3, 2) [000299] ------------ t299 = LCL_VAR int V29 loc26 u:2 rax (last use) REG rax $36b /--* t298 long +--* t299 int N1119 ( 10, 6) [000302] ------------ t302 = * RSZ long REG rbx $491 /--* t302 long N1121 ( 10, 6) [000304] DA---------- * STORE_LCL_VAR long V24 loc21 d:4 rbx REG rbx ------------ BB40 [1D0..1E7) -> BB42 (cond), preds={BB35,BB39} succs={BB41,BB42} N001 ( 0, 0) [000894] ------------ t894 = PHI_ARG bool V25 loc22 u:4 r12 $36f N002 ( 0, 0) [000889] ------------ t889 = PHI_ARG bool V25 loc22 u:2 r12 $369 /--* t894 bool +--* t889 bool N003 ( 0, 0) [000864] ------------ t864 = * PHI bool /--* t864 bool N005 ( 0, 0) [000865] DA---------- * STORE_LCL_VAR bool V25 loc22 d:3 r12 N001 ( 0, 0) [000895] ------------ t895 = PHI_ARG long V24 loc21 u:4 rbx $491 N002 ( 0, 0) [000890] ------------ t890 = PHI_ARG long V24 loc21 u:2 rbx $450 /--* t895 long +--* t890 long N003 ( 0, 0) [000861] ------------ t861 = * PHI long /--* t861 long N005 ( 0, 0) [000862] DA---------- * STORE_LCL_VAR long V24 loc21 d:3 rbx N1125 ( 3, 2) [000831] -------N---- t831 = LCL_VAR_ADDR byref V76 tmp46 rcx REG rcx /--* t831 byref N1127 ( 3, 3) [000833] DA---------- * STORE_LCL_VAR byref V90 tmp60 d:2 rcx REG rcx N1129 ( 1, 1) [000834] ------------ t834 = LCL_VAR byref V90 tmp60 u:2 rcx Zero Fseq[_bits] REG rcx $426 N1131 ( 3, 2) [000836] -------N---- t836 = LCL_VAR ref (AX) V54 tmp24 rax REG rax $18b /--* t834 byref +--* t836 ref N1133 (???,???) [000981] -A--G------- * STOREIND ref REG NA N1135 ( 1, 1) [000839] ------------ t839 = LCL_VAR byref V90 tmp60 u:2 rcx (last use) REG rcx $426 /--* t839 byref N1137 ( 2, 2) [000841] -c---------- t841 = * LEA(b+8) byref REG NA N1139 ( 3, 2) [000843] -------N---- t843 = LCL_VAR int (AX) V55 tmp25 rax REG rax $252 /--* t841 byref +--* t843 int N1141 (???,???) [000982] -A--G-----L- * STOREIND int REG NA N1143 ( 3, 2) [000846] -------N---- t846 = LCL_VAR_ADDR byref V76 tmp46 rcx REG rcx /--* t846 byref N1145 (???,???) [001071] ------------ t1071 = * PUTARG_REG byref REG rcx /--* t1071 byref arg0 in rcx N1147 ( 38, 24) [000243] --CXG------- t243 = * CALL long System.Numerics.BigInteger.op_Explicit REG rax $454 N1149 ( 3, 2) [000247] ------------ t247 = LCL_VAR int V20 loc17 u:2 r14 (last use) REG r14 $362 /--* t243 long +--* t247 int N1151 ( 47, 29) [000250] ---XG------- t250 = * LSH long REG rax $492 N1153 ( 1, 1) [000251] ------------ t251 = LCL_VAR long V24 loc21 u:3 rbx (last use) REG rbx $580 /--* t250 long +--* t251 long N1155 ( 49, 31) [000252] ---XG------- t252 = * ADD long REG rdx $493 /--* t252 long N1157 ( 53, 34) [000254] DA-XG------- * STORE_LCL_VAR long V27 loc24 d:2 rdx REG rdx N1159 (???,???) [000983] ------------ IL_OFFSET void IL offset: 0x1e2 REG NA N1161 ( 1, 1) [000255] ------------ t255 = LCL_VAR int V13 loc10 u:2 r15 REG r15 $293 N1163 ( 1, 1) [000256] -c---------- t256 = CNS_INT int 0 REG NA $40 /--* t255 int +--* t256 int N1165 ( 3, 3) [000257] N------N---- * NE void REG NA $35a N1167 ( 5, 5) [000258] ------------ * JTRUE void REG NA ------------ BB41 [1E7..1EE) -> BB43 (always), preds={BB40} succs={BB43} N1171 (???,???) [000984] ------------ IL_OFFSET void IL offset: 0x1e7 REG NA N1173 ( 3, 2) [000275] ------------ t275 = LCL_VAR int V22 loc19 u:2 rbp (last use) REG rbp $24c /--* t275 int N1175 ( 4, 3) [000276] ------------ t276 = * NEG int REG r8 $2c2 N1177 ( 1, 1) [000277] -c---------- t277 = CNS_INT int -1 REG NA $43 /--* t276 int +--* t277 int N1179 ( 6, 5) [000278] ------------ t278 = * ADD int REG r8 $372 /--* t278 int N1181 ( 10, 8) [000280] DA---------- * STORE_LCL_VAR int V36 tmp6 d:4 r8 REG r8 ------------ BB42 [1EE..1F2), preds={BB40} succs={BB43} N1185 (???,???) [000985] ------------ IL_OFFSET void IL offset: 0x1ee REG NA N1187 ( 1, 1) [000259] ------------ t259 = LCL_VAR int V13 loc10 u:2 r15 (last use) REG r15 $293 N1189 ( 1, 1) [000260] -c---------- t260 = CNS_INT int -2 REG NA $68 /--* t259 int +--* t260 int N1191 ( 3, 3) [000261] ------------ t261 = * ADD int REG r8 $371 /--* t261 int N1193 ( 7, 6) [000263] DA---------- * STORE_LCL_VAR int V36 tmp6 d:3 r8 REG r8 ------------ BB43 [1F2..202), preds={BB41,BB42} succs={BB44} N001 ( 0, 0) [000893] ------------ t893 = PHI_ARG int V36 tmp6 u:4 r8 $372 N002 ( 0, 0) [000892] ------------ t892 = PHI_ARG int V36 tmp6 u:3 r8 $371 /--* t893 int +--* t892 int N003 ( 0, 0) [000858] ------------ t858 = * PHI int /--* t858 int N005 ( 0, 0) [000859] DA---------- * STORE_LCL_VAR int V36 tmp6 d:2 r8 N1197 (???,???) [000986] ------------ IL_OFFSET void IL offset: 0x1f4 REG NA N1199 ( 1, 1) [000272] ------------ t272 = LCL_VAR byref V02 arg2 u:1 rdi (last use) REG rdi $81 /--* t272 byref N1201 (???,???) [001072] ------------ * PUTARG_STK [+0x20] void REG NA N1203 ( 1, 1) [000268] ------------ t268 = LCL_VAR ref V01 arg1 u:1 rsi (last use) REG rsi $c0 /--* t268 ref N1205 (???,???) [001073] ------------ t1073 = * PUTARG_REG ref REG rcx N1207 ( 3, 2) [000269] ------------ t269 = LCL_VAR long V27 loc24 u:2 rdx (last use) REG rdx $493 /--* t269 long N1209 (???,???) [001074] ------------ t1074 = * PUTARG_REG long REG rdx N1211 ( 3, 2) [000270] ------------ t270 = LCL_VAR int V36 tmp6 u:2 r8 (last use) REG r8 $253 /--* t270 int N1213 (???,???) [001075] ------------ t1075 = * PUTARG_REG int REG r8 N1215 ( 3, 2) [000271] ------------ t271 = LCL_VAR int V25 loc22 u:3 r12 (last use) REG r12 $540 /--* t271 int N1217 (???,???) [001076] ------------ t1076 = * PUTARG_REG int REG r9 /--* t1073 ref this in rcx +--* t1074 long arg1 in rdx +--* t1075 int arg2 in r8 +--* t1076 int arg3 in r9 N1219 ( 28, 18) [000273] --CXG------- t273 = * CALL int FloatingPointType.AssembleFloatingPointValue REG rax $2be /--* t273 int N1221 ( 28, 18) [000853] DA-XG------- * STORE_LCL_VAR int V51 tmp21 d:4 rax REG rax ------------ BB44 [???..???) (return), preds={BB16,BB30,BB43} succs={} N001 ( 0, 0) [000901] ------------ t901 = PHI_ARG int V51 tmp21 u:5 rax $5c2 N002 ( 0, 0) [000891] ------------ t891 = PHI_ARG int V51 tmp21 u:4 rax $2be N003 ( 0, 0) [000887] ------------ t887 = PHI_ARG int V51 tmp21 u:3 rax $5c7 /--* t901 int +--* t891 int +--* t887 int N004 ( 0, 0) [000855] ------------ t855 = * PHI int /--* t855 int N006 ( 0, 0) [000856] DA---------- * STORE_LCL_VAR int V51 tmp21 d:2 rax N1225 ( 1, 1) [000522] -------N---- t522 = LCL_VAR int V51 tmp21 u:2 rax (last use) REG rax $254 /--* t522 int N1227 ( 2, 2) [000523] ------------ * RETURN int REG NA $5c9 ------------------------------------------------------------------------------------------------------------------- Final allocation ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 0.#0 V1 Parm Alloc rsi | | | | | |V1 a| | | | | | | | 0.#1 V0 Parm Alloc rcx | |V0 a| | | |V1 a| | | | | | | | 0.#2 V2 Parm Alloc rdi | |V0 a| | | |V1 a|V2 a| | | | | | | 1.#3 BB1 PredBB0 | |V0 a| | | |V1 a|V2 a| | | | | | | 5.#4 V0 Use Keep rcx | |V0 a| | | |V1 a|V2 a| | | | | | | 6.#5 I58 Def Alloc rbx | |V0 a| |I58 a| |V1 a|V2 a| | | | | | | 7.#6 I58 Use * Keep rbx | |V0 a| |I58 i| |V1 a|V2 a| | | | | | | 8.#7 V52 Def Alloc rbx | |V0 a| |V52 a| |V1 a|V2 a| | | | | | | 13.#8 V0 Use * Keep rcx | |V0 i| |V52 a| |V1 a|V2 a| | | | | | | 14.#9 I59 Def Alloc rbp | | | |V52 a|I59 a|V1 a|V2 a| | | | | | | 15.#10 I59 Use * Keep rbp | | | |V52 a|I59 i|V1 a|V2 a| | | | | | | 16.#11 V53 Def Alloc rbp | | | |V52 a|V53 a|V1 a|V2 a| | | | | | | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 17.#12 BB2 PredBB1 | | | |V52 a|V53 a|V1 a|V2 a| | | | | | | 29.#13 V52 Use Keep rbx | | | |V52 a|V53 a|V1 a|V2 a| | | | | | | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 33.#14 BB3 PredBB2 | | | | | |V1 a|V2 a| | | | | | | 39.#15 rcx Fixd Keep rcx | | | | | |V1 a|V2 a| | | | | | | 39.#16 V1 Use Copy rcx | |V1 a| | | |V1 a|V2 a| | | | | | | 40.#17 rcx Fixd Keep rcx | | | | | |V1 a|V2 a| | | | | | | 40.#18 I60 Def Alloc rcx | |I60 a| | | |V1 a|V2 a| | | | | | | 45.#19 V1 Use * Keep rsi | |I60 a| | | |V1 i|V2 a| | | | | | | 46.#20 I61 Def Alloc rax |I61 a|I60 a| | | | |V2 a| | | | | | | 49.#21 I61 Use * Keep rax |I61 i|I60 a| | | | |V2 a| | | | | | | 50.#22 I62 Def Alloc rax |I62 a|I60 a| | | | |V2 a| | | | | | | 55.#23 rcx Fixd Keep rcx |I62 a|I60 a| | | | |V2 a| | | | | | | 55.#24 I60 Use * Keep rcx |I62 a|I60 i| | | | |V2 a| | | | | | | 55.#25 I62 Use * Keep rax |I62 i| | | | | |V2 a| | | | | | | 56.#26 rax Kill Keep rax | | | | | | |V2 a| | | | | | | 56.#27 rcx Kill Keep rcx | | | | | | |V2 a| | | | | | | 56.#28 rdx Kill Keep rdx | | | | | | |V2 a| | | | | | | 56.#29 r8 Kill Keep r8 | | | | | | |V2 a| | | | | | | 56.#30 r9 Kill Keep r9 | | | | | | |V2 a| | | | | | | 56.#31 r10 Kill Keep r10 | | | | | | |V2 a| | | | | | | 56.#32 r11 Kill Keep r11 | | | | | | |V2 a| | | | | | | 56.#33 rax Fixd Keep rax | | | | | | |V2 a| | | | | | | 56.#34 I63 Def Alloc rax |I63 a| | | | | |V2 a| | | | | | | 59.#35 V2 Use * Keep rdi |I63 a| | | | | |V2 i| | | | | | | 59.#36 I63 Use * Keep rax |I63 i| | | | | | | | | | | | | 62.#37 C64 Def Alloc rax |C64 a| | | | | | | | | | | | | 63.#38 rax Fixd Keep rax |C64 a| | | | | | | | | | | | | 63.#39 C64 Use * Keep rax |C64 i| | | | | | | | | | | | | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 65.#40 BB4 PredBB2 | | | |V52 a|V53 a|V1 a|V2 a| | | | | | | 69.#41 rcx Fixd Keep rcx | | | |V52 a|V53 a|V1 a|V2 a| | | | | | | 69.#42 V1 Use Copy rcx | |V1 a| |V52 a|V53 a|V1 a|V2 a| | | | | | | 70.#43 rcx Fixd Keep rcx | | | |V52 a|V53 a|V1 a|V2 a| | | | | | | 70.#44 I65 Def Alloc rcx | |I65 a| |V52 a|V53 a|V1 a|V2 a| | | | | | | 75.#45 V1 Use Keep rsi | |I65 a| |V52 a|V53 a|V1 a|V2 a| | | | | | | 76.#46 I66 Def Alloc rax |I66 a|I65 a| |V52 a|V53 a|V1 a|V2 a| | | | | | | 79.#47 I66 Use * Keep rax |I66 i|I65 a| |V52 a|V53 a|V1 a|V2 a| | | | | | | 80.#48 I67 Def Alloc rax |I67 a|I65 a| |V52 a|V53 a|V1 a|V2 a| | | | | | | 85.#49 rcx Fixd Keep rcx |I67 a|I65 a| |V52 a|V53 a|V1 a|V2 a| | | | | | | 85.#50 I65 Use * Keep rcx |I67 a|I65 i| |V52 a|V53 a|V1 a|V2 a| | | | | | | 85.#51 I67 Use * Keep rax |I67 i| | |V52 a|V53 a|V1 a|V2 a| | | | | | | 86.#52 rax Kill Keep rax | | | |V52 a|V53 a|V1 a|V2 a| | | | | | | 86.#53 rcx Kill Keep rcx | | | |V52 a|V53 a|V1 a|V2 a| | | | | | | 86.#54 rdx Kill Keep rdx | | | |V52 a|V53 a|V1 a|V2 a| | | | | | | 86.#55 r8 Kill Keep r8 | | | |V52 a|V53 a|V1 a|V2 a| | | | | | | 86.#56 r9 Kill Keep r9 | | | |V52 a|V53 a|V1 a|V2 a| | | | | | | 86.#57 r10 Kill Keep r10 | | | |V52 a|V53 a|V1 a|V2 a| | | | | | | 86.#58 r11 Kill Keep r11 | | | |V52 a|V53 a|V1 a|V2 a| | | | | | | 86.#59 rax Fixd Keep rax | | | |V52 a|V53 a|V1 a|V2 a| | | | | | | 86.#60 I68 Def Alloc rax |I68 a| | |V52 a|V53 a|V1 a|V2 a| | | | | | | 89.#61 I68 Use * Keep rax |I68 i| | |V52 a|V53 a|V1 a|V2 a| | | | | | | 90.#62 I69 Def Alloc rax |I69 a| | |V52 a|V53 a|V1 a|V2 a| | | | | | | 91.#63 I69 Use * Keep rax |I69 i| | |V52 a|V53 a|V1 a|V2 a| | | | | | | 92.#64 I70 Def Alloc r14 | | | |V52 a|V53 a|V1 a|V2 a| | | | |I70 a| | 95.#65 I70 Use * Keep r14 | | | |V52 a|V53 a|V1 a|V2 a| | | | |I70 i| | 96.#66 I71 Def Alloc r14 | | | |V52 a|V53 a|V1 a|V2 a| | | | |I71 a| | 97.#67 I71 Use * Keep r14 | | | |V52 a|V53 a|V1 a|V2 a| | | | |I71 i| | 98.#68 V3 Def Alloc r14 | | | |V52 a|V53 a|V1 a|V2 a| | | | |V3 a| | 103.#69 V53 Use Keep rbp | | | |V52 a|V53 a|V1 a|V2 a| | | | |V3 a| | 104.#70 V40 Def Alloc rcx | |V40 a| |V52 a|V53 a|V1 a|V2 a| | | | |V3 a| | 111.#71 V40 Use * Keep rcx | |V40 i| |V52 a|V53 a|V1 a|V2 a| | | | |V3 a| | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 115.#72 BB5 PredBB4 | | | |V52 a|V53 a|V1 a|V2 a| | | | |V3 a| | 121.#73 V53 Use Keep rbp | | | |V52 a|V53 a|V1 a|V2 a| | | | |V3 a| | 122.#74 V39 Def Alloc r15 | | | |V52 a|V53 a|V1 a|V2 a| | | | |V3 a|V39 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 123.#75 BB6 PredBB4 | | | |V52 a|V53 a|V1 a|V2 a| | | | |V3 a| | 128.#76 C72 Def Alloc r15 | | | |V52 a|V53 a|V1 a|V2 a| | | | |V3 a|C72 a| 129.#77 C72 Use * Keep r15 | | | |V52 a|V53 a|V1 a|V2 a| | | | |V3 a|C72 i| 130.#78 V39 Def Alloc r15 | | | |V52 a|V53 a|V1 a|V2 a| | | | |V3 a|V39 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 131.#79 BB7 PredBB5 | | | |V52 a|V53 a|V1 a|V2 a| | | | |V3 a|V39 a| 135.#80 V39 Use * Keep r15 | | | |V52 a|V53 a|V1 a|V2 a| | | | |V3 a|V39 i| 136.#81 V31 Def Alloc r15 | | | |V52 a|V53 a|V1 a|V2 a| | | | |V3 a|V31 a| 141.#82 V52 Use Keep rbx | | | |V52 a|V53 a|V1 a|V2 a| | | | |V3 a|V31 a| 142.#83 I73 Def Alloc r12 | | | |V52 a|V53 a|V1 a|V2 a| | |I73 a| |V3 a|V31 a| 143.#84 I73 Use * Keep r12 | | | |V52 a|V53 a|V1 a|V2 a| | |I73 i| |V3 a|V31 a| 144.#85 V42 Def Alloc r12 | | | |V52 a|V53 a|V1 a|V2 a| | |V42 a| |V3 a|V31 a| 149.#86 V31 Use Keep r15 | | | |V52 a|V53 a|V1 a|V2 a| | |V42 a| |V3 a|V31 a| 149.#87 V42 Use Keep r12 | | | |V52 a|V53 a|V1 a|V2 a| | |V42 a| |V3 a|V31 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 153.#88 BB8 PredBB7 | | | |V52 a|V53 a|V1 a|V2 a| | |V42 a| |V3 a|V31 a| 157.#89 V42 Use * Keep r12 | | | |V52 a|V53 a|V1 a|V2 a| | |V42 i| |V3 a|V31 a| 158.#90 V41 Def Alloc r12 | | | |V52 a|V53 a|V1 a|V2 a| | |V41 a| |V3 a|V31 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 159.#91 BB9 PredBB7 | | | |V52 a|V53 a|V1 a|V2 a| | | | |V3 a|V31 a| 163.#92 V31 Use Keep r15 | | | |V52 a|V53 a|V1 a|V2 a| | | | |V3 a|V31 a| 164.#93 V41 Def Alloc r12 | | | |V52 a|V53 a|V1 a|V2 a| | |V41 a| |V3 a|V31 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 165.#94 BB10 PredBB8 | | | |V52 a|V53 a|V1 a|V2 a| | |V41 a| |V3 a|V31 a| 171.#95 V31 Use * Keep r15 | | | |V52 a|V53 a|V1 a|V2 a| | |V41 a| |V3 a|V31 i| 171.#96 V41 Use Keep r12 | | | |V52 a|V53 a|V1 a|V2 a| | |V41 a| |V3 a| | 172.#97 I74 Def Alloc r15 | | | |V52 a|V53 a|V1 a|V2 a| | |V41 a| |V3 a|I74 a| 173.#98 I74 Use * Keep r15 | | | |V52 a|V53 a|V1 a|V2 a| | |V41 a| |V3 a|I74 i| 174.#99 V5 Def Alloc r15 | | | |V52 a|V53 a|V1 a|V2 a| | |V41 a| |V3 a|V5 a| 179.#100 V41 Use * Keep r12 | | | |V52 a|V53 a|V1 a|V2 a| | |V41 i| |V3 a|V5 a| 180.#101 V8 Def Alloc r12 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a| |V3 a|V5 a| 185.#102 V52 Use Keep rbx | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a| |V3 a|V5 a| 186.#103 I75 Def Alloc r13 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|I75 a|V3 a|V5 a| 187.#104 I75 Use * Keep r13 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|I75 i|V3 a|V5 a| 188.#105 V9 Def Alloc r13 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 195.#106 V9 Use Keep r13 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 195.#107 V8 Use Keep r12 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 196.#108 I76 Def Alloc rax |I76 a| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 197.#109 I76 Use * Keep rax |I76 i| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 198.#110 V10 Def Alloc rax | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| Spill rax | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 200.#111 I77 Def Alloc rcx | |I77 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 201.#112 I77 Use * Keep rcx | |I77 i| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 202.#113 V75 Def Alloc rcx | |V75 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 204.#114 I78 Def Alloc rdx | |V75 a|I78 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 205.#115 I78 Use * Keep rdx | |V75 a|I78 i|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 206.#116 V74 Def Alloc rdx | |V75 a|V74 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 211.#117 V74 Use Keep rdx | |V75 a|V74 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 211.#118 V52 Use Keep rbx | |V75 a|V74 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 219.#119 V74 Use * Keep rdx | |V75 a|V74 i|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 219.#120 V53 Use Keep rbp | |V75 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 223.#121 rcx Fixd Keep rcx | |V75 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 223.#122 V75 Use * Keep rcx | |V75 i| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 224.#123 rcx Fixd Keep rcx | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 224.#124 I79 Def Alloc rcx | |I79 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 226.#125 I80 Def Alloc rdx | |I79 a|I80 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 227.#126 rdx Fixd Keep rdx | |I79 a|I80 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 227.#127 I80 Use * Keep rdx | |I79 a|I80 i|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 228.#128 rdx Fixd Keep rdx | |I79 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 228.#129 I81 Def Alloc rdx | |I79 a|I81 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 231.#130 r9 Fixd Keep r9 | |I79 a|I81 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 231.#131 V8 Use Copy r9 | |I79 a|I81 a|V52 a|V53 a|V1 a|V2 a| |V8 a|V8 a|V9 a|V3 a|V5 a| 232.#132 r9 Fixd Keep r9 | |I79 a|I81 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 232.#133 I82 Def Alloc r9 | |I79 a|I81 a|V52 a|V53 a|V1 a|V2 a| |I82 a|V8 a|V9 a|V3 a|V5 a| 234.#134 C83 Def Alloc r8 | |I79 a|I81 a|V52 a|V53 a|V1 a|V2 a|C83 a|I82 a|V8 a|V9 a|V3 a|V5 a| 235.#135 r8 Fixd Keep r8 | |I79 a|I81 a|V52 a|V53 a|V1 a|V2 a|C83 a|I82 a|V8 a|V9 a|V3 a|V5 a| 235.#136 C83 Use * Keep r8 | |I79 a|I81 a|V52 a|V53 a|V1 a|V2 a|C83 i|I82 a|V8 a|V9 a|V3 a|V5 a| 236.#137 r8 Fixd Keep r8 | |I79 a|I81 a|V52 a|V53 a|V1 a|V2 a| |I82 a|V8 a|V9 a|V3 a|V5 a| 236.#138 I84 Def Alloc r8 | |I79 a|I81 a|V52 a|V53 a|V1 a|V2 a|I84 a|I82 a|V8 a|V9 a|V3 a|V5 a| 237.#139 rcx Fixd Keep rcx | |I79 a|I81 a|V52 a|V53 a|V1 a|V2 a|I84 a|I82 a|V8 a|V9 a|V3 a|V5 a| 237.#140 I79 Use * Keep rcx | |I79 i|I81 a|V52 a|V53 a|V1 a|V2 a|I84 a|I82 a|V8 a|V9 a|V3 a|V5 a| 237.#141 rdx Fixd Keep rdx | | |I81 a|V52 a|V53 a|V1 a|V2 a|I84 a|I82 a|V8 a|V9 a|V3 a|V5 a| 237.#142 I81 Use * Keep rdx | | |I81 i|V52 a|V53 a|V1 a|V2 a|I84 a|I82 a|V8 a|V9 a|V3 a|V5 a| 237.#143 r9 Fixd Keep r9 | | | |V52 a|V53 a|V1 a|V2 a|I84 a|I82 a|V8 a|V9 a|V3 a|V5 a| 237.#144 I82 Use * Keep r9 | | | |V52 a|V53 a|V1 a|V2 a|I84 a|I82 i|V8 a|V9 a|V3 a|V5 a| 237.#145 r8 Fixd Keep r8 | | | |V52 a|V53 a|V1 a|V2 a|I84 a| |V8 a|V9 a|V3 a|V5 a| 237.#146 I84 Use * Keep r8 | | | |V52 a|V53 a|V1 a|V2 a|I84 i| |V8 a|V9 a|V3 a|V5 a| 238.#147 rax Kill Keep rax | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 238.#148 rcx Kill Keep rcx | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 238.#149 rdx Kill Keep rdx | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 238.#150 r8 Kill Keep r8 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 238.#151 r9 Kill Keep r9 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 238.#152 r10 Kill Keep r10 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 238.#153 r11 Kill Keep r11 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 245.#154 V5 Use Keep r15 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 249.#155 BB11 PredBB10 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 253.#156 rcx Fixd Keep rcx | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 253.#157 V1 Use Copy rcx | |V1 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 254.#158 rcx Fixd Keep rcx | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 254.#159 I85 Def Alloc rcx | |I85 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 255.#160 rcx Fixd Keep rcx | |I85 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 255.#161 I85 Use * Keep rcx | |I85 i| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 256.#162 rax Kill Keep rax | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 256.#163 rcx Kill Keep rcx | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 256.#164 rdx Kill Keep rdx | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 256.#165 r8 Kill Keep r8 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 256.#166 r9 Kill Keep r9 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 256.#167 r10 Kill Keep r10 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 256.#168 r11 Kill Keep r11 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 256.#169 rax Fixd Keep rax | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 256.#170 I86 Def Alloc rax |I86 a| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 257.#171 I86 Use * Keep rax |I86 i| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 258.#172 I87 Def Alloc rcx | |I87 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 261.#173 V5 Use Keep r15 | |I87 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 262.#174 I88 Def Alloc rax |I88 a|I87 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 263.#175 I87 Use * Keep rcx |I88 a|I87 i| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 263.#176 I88 Use * Keep rax |I88 i| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 267.#177 BB12 PredBB11 | | | | | |V1 a|V2 a| | | | | | | 273.#178 rcx Fixd Keep rcx | | | | | |V1 a|V2 a| | | | | | | 273.#179 V1 Use Copy rcx | |V1 a| | | |V1 a|V2 a| | | | | | | 274.#180 rcx Fixd Keep rcx | | | | | |V1 a|V2 a| | | | | | | 274.#181 I89 Def Alloc rcx | |I89 a| | | |V1 a|V2 a| | | | | | | 279.#182 V1 Use * Keep rsi | |I89 a| | | |V1 i|V2 a| | | | | | | 280.#183 I90 Def Alloc rax |I90 a|I89 a| | | | |V2 a| | | | | | | 283.#184 I90 Use * Keep rax |I90 i|I89 a| | | | |V2 a| | | | | | | 284.#185 I91 Def Alloc rax |I91 a|I89 a| | | | |V2 a| | | | | | | 289.#186 rcx Fixd Keep rcx |I91 a|I89 a| | | | |V2 a| | | | | | | 289.#187 I89 Use * Keep rcx |I91 a|I89 i| | | | |V2 a| | | | | | | 289.#188 I91 Use * Keep rax |I91 i| | | | | |V2 a| | | | | | | 290.#189 rax Kill Keep rax | | | | | | |V2 a| | | | | | | 290.#190 rcx Kill Keep rcx | | | | | | |V2 a| | | | | | | 290.#191 rdx Kill Keep rdx | | | | | | |V2 a| | | | | | | 290.#192 r8 Kill Keep r8 | | | | | | |V2 a| | | | | | | 290.#193 r9 Kill Keep r9 | | | | | | |V2 a| | | | | | | 290.#194 r10 Kill Keep r10 | | | | | | |V2 a| | | | | | | 290.#195 r11 Kill Keep r11 | | | | | | |V2 a| | | | | | | 290.#196 rax Fixd Keep rax | | | | | | |V2 a| | | | | | | 290.#197 I92 Def Alloc rax |I92 a| | | | | |V2 a| | | | | | | 293.#198 V2 Use * Keep rdi |I92 a| | | | | |V2 i| | | | | | | 293.#199 I92 Use * Keep rax |I92 i| | | | | | | | | | | | | 296.#200 C93 Def Alloc rax |C93 a| | | | | | | | | | | | | 297.#201 rax Fixd Keep rax |C93 a| | | | | | | | | | | | | 297.#202 C93 Use * Keep rax |C93 i| | | | | | | | | | | | | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 299.#203 BB13 PredBB11 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 304.#204 I94 Def Alloc rcx | |I94 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 305.#205 rcx Fixd Keep rcx | |I94 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 305.#206 I94 Use * Keep rcx | |I94 i| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 306.#207 rcx Fixd Keep rcx | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 306.#208 I95 Def Alloc rcx | |I95 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 309.#209 rdx Fixd Keep rdx | |I95 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 a| 309.#210 V5 Use * Copy rdx | |I95 a|V5 i|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V5 i| 310.#211 rdx Fixd Keep rdx | |I95 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 310.#212 I96 Def Alloc rdx | |I95 a|I96 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 311.#213 rcx Fixd Keep rcx | |I95 a|I96 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 311.#214 I95 Use * Keep rcx | |I95 i|I96 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 311.#215 rdx Fixd Keep rdx | | |I96 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 311.#216 I96 Use * Keep rdx | | |I96 i|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 312.#217 rax Kill Keep rax | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 312.#218 rcx Kill Keep rcx | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 312.#219 rdx Kill Keep rdx | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 312.#220 r8 Kill Keep r8 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 312.#221 r9 Kill Keep r9 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 312.#222 r10 Kill Keep r10 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 312.#223 r11 Kill Keep r11 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 313.#224 BB14 PredBB10 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 316.#225 I97 Def Alloc rcx | |I97 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 317.#226 I97 Use * Keep rcx | |I97 i| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 318.#227 V77 Def Alloc rcx | |V77 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 322.#228 I98 Def Alloc rdx | |V77 a|I98 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 323.#229 V77 Use Keep rcx | |V77 a|I98 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 323.#230 I98 Use * Keep rdx | |V77 a|I98 i|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 330.#231 I99 Def Alloc rdx | |V77 a|I99 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 331.#232 V77 Use * Keep rcx | |V77 i|I99 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 331.#233 I99 Use * Keep rdx | | |I99 i|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 334.#234 I100 Def Alloc rcx | |I100a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 335.#235 rcx Fixd Keep rcx | |I100a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 335.#236 I100 Use * Keep rcx | |I100i| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 336.#237 rcx Fixd Keep rcx | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 336.#238 I101 Def Alloc rcx | |I101a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 338.#239 I102 Def Alloc rdx | |I101a|I102a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 339.#240 rdx Fixd Keep rdx | |I101a|I102a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 339.#241 I102 Use * Keep rdx | |I101a|I102i|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 340.#242 rdx Fixd Keep rdx | |I101a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 340.#243 I103 Def Alloc rdx | |I101a|I103a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 341.#244 rcx Fixd Keep rcx | |I101a|I103a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 341.#245 I101 Use * Keep rcx | |I101i|I103a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 341.#246 rdx Fixd Keep rdx | | |I103a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 341.#247 I103 Use * Keep rdx | | |I103i|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 342.#248 rax Kill Keep rax | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 342.#249 rcx Kill Keep rcx | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 342.#250 rdx Kill Keep rdx | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 342.#251 r8 Kill Keep r8 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 342.#252 r9 Kill Keep r9 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 342.#253 r10 Kill Keep r10 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 342.#254 r11 Kill Keep r11 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 342.#255 rax Fixd Keep rax | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 342.#256 I104 Def Alloc rax |I104a| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 343.#257 I104 Use * Keep rax |I104i| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a| | 344.#258 V13 Def Alloc r15 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 351.#259 V13 Use Keep r15 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 351.#260 V3 Use Keep r14 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 355.#261 BB15 PredBB14 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 363.#262 V10 Use ReLod rax |V10 a| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| Keep rax |V10 a| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 367.#0 V10 Move STK | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 367.#263 BB16 PredBB14 | | | | | |V1 a|V2 a| | | | | |V13 a| 373.#264 V2 Use * Keep rdi | | | | | |V1 a|V2 i| | | | | |V13 a| 379.#265 V10 Use * NoReg | | | | | |V1 a| | | | | | |V13 a| 380.#266 I105 Def Alloc r8 | | | | | |V1 a| |I105a| | | | |V13 a| 381.#267 r8 Fixd Keep r8 | | | | | |V1 a| |I105a| | | | |V13 a| 381.#268 I105 Use * Keep r8 | | | | | |V1 a| |I105i| | | | |V13 a| 382.#269 r8 Fixd Keep r8 | | | | | |V1 a| | | | | | |V13 a| 382.#270 I106 Def Alloc r8 | | | | | |V1 a| |I106a| | | | |V13 a| 384.#271 I107 Def Alloc rcx | |I107a| | | |V1 a| |I106a| | | | |V13 a| 385.#272 rcx Fixd Keep rcx | |I107a| | | |V1 a| |I106a| | | | |V13 a| 385.#273 I107 Use * Keep rcx | |I107i| | | |V1 a| |I106a| | | | |V13 a| 386.#274 rcx Fixd Keep rcx | | | | | |V1 a| |I106a| | | | |V13 a| 386.#275 I108 Def Alloc rcx | |I108a| | | |V1 a| |I106a| | | | |V13 a| 389.#276 rdx Fixd Keep rdx | |I108a| | | |V1 a| |I106a| | | | |V13 a| 389.#277 V13 Use * Copy rdx | |I108a|V13 i| | |V1 a| |I106a| | | | |V13 i| 390.#278 rdx Fixd Keep rdx | |I108a| | | |V1 a| |I106a| | | | | | 390.#279 I109 Def Alloc rdx | |I108a|I109a| | |V1 a| |I106a| | | | | | 393.#280 r9 Fixd Keep r9 | |I108a|I109a| | |V1 a| |I106a| | | | | | 393.#281 V1 Use * Copy r9 | |I108a|I109a| | |V1 i| |I106a|V1 i| | | | | 394.#282 r9 Fixd Keep r9 | |I108a|I109a| | | | |I106a| | | | | | 394.#283 I110 Def Alloc r9 | |I108a|I109a| | | | |I106a|I110a| | | | | 395.#284 r8 Fixd Keep r8 | |I108a|I109a| | | | |I106a|I110a| | | | | 395.#285 I106 Use * Keep r8 | |I108a|I109a| | | | |I106i|I110a| | | | | 395.#286 rcx Fixd Keep rcx | |I108a|I109a| | | | | |I110a| | | | | 395.#287 I108 Use * Keep rcx | |I108i|I109a| | | | | |I110a| | | | | 395.#288 rdx Fixd Keep rdx | | |I109a| | | | | |I110a| | | | | 395.#289 I109 Use * Keep rdx | | |I109i| | | | | |I110a| | | | | 395.#290 r9 Fixd Keep r9 | | | | | | | | |I110a| | | | | 395.#291 I110 Use * Keep r9 | | | | | | | | |I110i| | | | | 396.#292 rax Kill Keep rax | | | | | | | | | | | | | | 396.#293 rcx Kill Keep rcx | | | | | | | | | | | | | | 396.#294 rdx Kill Keep rdx | | | | | | | | | | | | | | 396.#295 r8 Kill Keep r8 | | | | | | | | | | | | | | 396.#296 r9 Kill Keep r9 | | | | | | | | | | | | | | 396.#297 r10 Kill Keep r10 | | | | | | | | | | | | | | 396.#298 r11 Kill Keep r11 | | | | | | | | | | | | | | 396.#299 rax Fixd Keep rax | | | | | | | | | | | | | | 396.#300 I111 Def Alloc rax |I111a| | | | | | | | | | | | | 397.#301 I111 Use * Keep rax |I111i| | | | | | | | | | | | | 398.#302 V51 Def Alloc rax |V51 a| | | | | | | | | | | | | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 399.#303 BB17 PredBB14 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 407.#304 V53 Use Keep rbp | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 411.#305 BB18 PredBB17 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 417.#306 V10 Use * ReLod rax |V10 a| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| Keep rax |V10 i| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 418.#307 V32 Def Alloc rdx | | |V32 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 419.#308 BB19 PredBB17 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 427.#309 V10 Use * ReLod rax |V10 a| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| Keep rax |V10 i| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 427.#310 V53 Use Keep rbp | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 428.#311 I112 Def Alloc rdx | | |I112a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 429.#312 I112 Use * Keep rdx | | |I112i|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 430.#313 V32 Def Alloc rdx | | |V32 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 431.#314 BB20 PredBB18 | | |V32 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 435.#315 V32 Use * Keep rdx | | |V32 i|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 436.#316 V14 Def Alloc rax |V14 a| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 443.#317 V13 Use Keep r15 |V14 a| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 447.#318 BB21 PredBB20 |V14 a| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 453.#319 V52 Use Keep rbx |V14 a| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 454.#320 I113 Def Alloc rcx |V14 a|I113a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 455.#321 I113 Use * Keep rcx |V14 a|I113i| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 456.#322 I114 Def Alloc rcx |V14 a|I114a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 459.#323 V14 Use Keep rax |V14 i|I114a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| Spill rax |V14 i|I114a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 460.#324 I115 Def Alloc rdx | |I114a|I115a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 461.#325 I115 Use * Keep rdx | |I114a|I115i|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 461.#326 I114 Use *D Keep rcx | |I114i| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 462.#327 I116 Def Alloc rdx | | |I116a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 463.#328 I116 Use * Keep rdx | | |I116i|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 464.#329 V38 Def Alloc rdx | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| Spill rdx | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 467.#330 rcx Fixd Keep rcx | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 467.#331 V1 Use Copy rcx | |V1 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 468.#332 rcx Fixd Keep rcx | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 468.#333 I117 Def Alloc rcx | |I117a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 469.#334 rcx Fixd Keep rcx | |I117a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 469.#335 I117 Use * Keep rcx | |I117i| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 470.#336 rax Kill Keep rax | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 470.#337 rcx Kill Keep rcx | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 470.#338 rdx Kill Keep rdx | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 470.#339 r8 Kill Keep r8 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 470.#340 r9 Kill Keep r9 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 470.#341 r10 Kill Keep r10 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 470.#342 r11 Kill Keep r11 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 470.#343 rax Fixd Keep rax | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 470.#344 I118 Def Alloc rax |I118a| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 471.#345 I118 Use * Keep rax |I118i| | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 472.#346 I119 Def Alloc rcx | |I119a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 475.#347 I119 Use * Keep rcx | |I119i| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 475.#348 V38 Use * NoReg | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 479.#349 BB22 PredBB21 | | | | | |V1 a|V2 a| | | | | | | 485.#350 rcx Fixd Keep rcx | | | | | |V1 a|V2 a| | | | | | | 485.#351 V1 Use Copy rcx | |V1 a| | | |V1 a|V2 a| | | | | | | 486.#352 rcx Fixd Keep rcx | | | | | |V1 a|V2 a| | | | | | | 486.#353 I120 Def Alloc rcx | |I120a| | | |V1 a|V2 a| | | | | | | 491.#354 V1 Use * Keep rsi | |I120a| | | |V1 i|V2 a| | | | | | | 492.#355 I121 Def Alloc rax |I121a|I120a| | | | |V2 a| | | | | | | 495.#356 I121 Use * Keep rax |I121i|I120a| | | | |V2 a| | | | | | | 496.#357 I122 Def Alloc rax |I122a|I120a| | | | |V2 a| | | | | | | 501.#358 rcx Fixd Keep rcx |I122a|I120a| | | | |V2 a| | | | | | | 501.#359 I120 Use * Keep rcx |I122a|I120i| | | | |V2 a| | | | | | | 501.#360 I122 Use * Keep rax |I122i| | | | | |V2 a| | | | | | | 502.#361 rax Kill Keep rax | | | | | | |V2 a| | | | | | | 502.#362 rcx Kill Keep rcx | | | | | | |V2 a| | | | | | | 502.#363 rdx Kill Keep rdx | | | | | | |V2 a| | | | | | | 502.#364 r8 Kill Keep r8 | | | | | | |V2 a| | | | | | | 502.#365 r9 Kill Keep r9 | | | | | | |V2 a| | | | | | | 502.#366 r10 Kill Keep r10 | | | | | | |V2 a| | | | | | | 502.#367 r11 Kill Keep r11 | | | | | | |V2 a| | | | | | | 502.#368 rax Fixd Keep rax | | | | | | |V2 a| | | | | | | 502.#369 I123 Def Alloc rax |I123a| | | | | |V2 a| | | | | | | 505.#370 V2 Use * Keep rdi |I123a| | | | | |V2 i| | | | | | | 505.#371 I123 Use * Keep rax |I123i| | | | | | | | | | | | | 508.#372 C124 Def Alloc rax |C124a| | | | | | | | | | | | | 509.#373 rax Fixd Keep rax |C124a| | | | | | | | | | | | | 509.#374 C124 Use * Keep rax |C124i| | | | | | | | | | | | | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 511.#375 BB23 PredBB20 | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 514.#376 I125 Def Alloc rcx | |I125a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 515.#377 I125 Use * Keep rcx | |I125i| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 516.#378 V79 Def Alloc rcx | |V79 a| |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 518.#379 I126 Def Alloc rdx | |V79 a|I126a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 519.#380 I126 Use * Keep rdx | |V79 a|I126i|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 520.#381 V78 Def Alloc rdx | |V79 a|V78 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 525.#382 V78 Use Keep rdx | |V79 a|V78 a|V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 525.#383 V52 Use * Keep rbx | |V79 a|V78 a|V52 i|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 533.#384 V78 Use * Keep rdx | |V79 a|V78 i| |V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 533.#385 V53 Use * Keep rbp | |V79 a| | |V53 i|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 537.#386 rcx Fixd Keep rcx | |V79 a| | | |V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 537.#387 V79 Use * Keep rcx | |V79 i| | | |V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 538.#388 rcx Fixd Keep rcx | | | | | |V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 538.#389 I127 Def Alloc rcx | |I127a| | | |V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 540.#390 I128 Def Alloc rdx | |I127a|I128a| | |V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 541.#391 rdx Fixd Keep rdx | |I127a|I128a| | |V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 541.#392 I128 Use * Keep rdx | |I127a|I128i| | |V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 542.#393 rdx Fixd Keep rdx | |I127a| | | |V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 542.#394 I129 Def Alloc rdx | |I127a|I129a| | |V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 545.#395 r8 Fixd Keep r8 | |I127a|I129a| | |V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| 545.#396 V8 Use * Copy r8 | |I127a|I129a| | |V1 a|V2 a|V8 i| |V8 i|V9 a|V3 a|V13 a| 546.#397 r8 Fixd Keep r8 | |I127a|I129a| | |V1 a|V2 a| | | |V9 a|V3 a|V13 a| 546.#398 I130 Def Alloc r8 | |I127a|I129a| | |V1 a|V2 a|I130a| | |V9 a|V3 a|V13 a| 549.#399 r9 Fixd Keep r9 | |I127a|I129a| | |V1 a|V2 a|I130a| | |V9 a|V3 a|V13 a| 549.#400 V9 Use * Copy r9 | |I127a|I129a| | |V1 a|V2 a|I130a|V9 i| |V9 i|V3 a|V13 a| 550.#401 r9 Fixd Keep r9 | |I127a|I129a| | |V1 a|V2 a|I130a| | | |V3 a|V13 a| 550.#402 I131 Def Alloc r9 | |I127a|I129a| | |V1 a|V2 a|I130a|I131a| | |V3 a|V13 a| 551.#403 rcx Fixd Keep rcx | |I127a|I129a| | |V1 a|V2 a|I130a|I131a| | |V3 a|V13 a| 551.#404 I127 Use * Keep rcx | |I127i|I129a| | |V1 a|V2 a|I130a|I131a| | |V3 a|V13 a| 551.#405 rdx Fixd Keep rdx | | |I129a| | |V1 a|V2 a|I130a|I131a| | |V3 a|V13 a| 551.#406 I129 Use * Keep rdx | | |I129i| | |V1 a|V2 a|I130a|I131a| | |V3 a|V13 a| 551.#407 r8 Fixd Keep r8 | | | | | |V1 a|V2 a|I130a|I131a| | |V3 a|V13 a| 551.#408 I130 Use * Keep r8 | | | | | |V1 a|V2 a|I130i|I131a| | |V3 a|V13 a| 551.#409 r9 Fixd Keep r9 | | | | | |V1 a|V2 a| |I131a| | |V3 a|V13 a| 551.#410 I131 Use * Keep r9 | | | | | |V1 a|V2 a| |I131i| | |V3 a|V13 a| 552.#411 rax Kill Keep rax | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 552.#412 rcx Kill Keep rcx | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 552.#413 rdx Kill Keep rdx | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 552.#414 r8 Kill Keep r8 | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 552.#415 r9 Kill Keep r9 | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 552.#416 r10 Kill Keep r10 | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 552.#417 r11 Kill Keep r11 | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 556.#418 C132 Def Alloc rcx | |C132a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 557.#419 rcx Fixd Keep rcx | |C132a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 557.#420 C132 Use * Keep rcx | |C132i| | | |V1 a|V2 a| | | | |V3 a|V13 a| 558.#421 rcx Fixd Keep rcx | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 558.#422 I133 Def Alloc rcx | |I133a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 560.#423 C134 Def Alloc rdx | |I133a|C134a| | |V1 a|V2 a| | | | |V3 a|V13 a| 561.#424 rdx Fixd Keep rdx | |I133a|C134a| | |V1 a|V2 a| | | | |V3 a|V13 a| 561.#425 C134 Use * Keep rdx | |I133a|C134i| | |V1 a|V2 a| | | | |V3 a|V13 a| 562.#426 rdx Fixd Keep rdx | |I133a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 562.#427 I135 Def Alloc rdx | |I133a|I135a| | |V1 a|V2 a| | | | |V3 a|V13 a| 563.#428 rcx Fixd Keep rcx | |I133a|I135a| | |V1 a|V2 a| | | | |V3 a|V13 a| 563.#429 I133 Use * Keep rcx | |I133i|I135a| | |V1 a|V2 a| | | | |V3 a|V13 a| 563.#430 rdx Fixd Keep rdx | | |I135a| | |V1 a|V2 a| | | | |V3 a|V13 a| 563.#431 I135 Use * Keep rdx | | |I135i| | |V1 a|V2 a| | | | |V3 a|V13 a| 564.#432 rax Kill Keep rax | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 564.#433 rcx Kill Keep rcx | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 564.#434 rdx Kill Keep rdx | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 564.#435 r8 Kill Keep r8 | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 564.#436 r9 Kill Keep r9 | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 564.#437 r10 Kill Keep r10 | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 564.#438 r11 Kill Keep r11 | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 564.#439 rax Fixd Keep rax | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 564.#440 I136 Def * Alloc rax |I136i| | | | |V1 a|V2 a| | | | |V3 a|V13 a| 566.#441 C137 Def Alloc rcx | |C137a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 567.#442 C137 Use * Keep rcx | |C137i| | | |V1 a|V2 a| | | | |V3 a|V13 a| 568.#443 I138 Def Alloc rcx | |I138a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 571.#444 I138 Use * Keep rcx | |I138i| | | |V1 a|V2 a| | | | |V3 a|V13 a| 572.#445 I139 Def Alloc rcx | |I139a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 573.#446 I139 Use * Keep rcx | |I139i| | | |V1 a|V2 a| | | | |V3 a|V13 a| 574.#447 V80 Def Alloc rcx | |V80 a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 577.#448 V80 Use Keep rcx | |V80 a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 578.#449 I140 Def Alloc rdx | |V80 a|I140a| | |V1 a|V2 a| | | | |V3 a|V13 a| 579.#450 I140 Use * Keep rdx | |V80 a|I140i| | |V1 a|V2 a| | | | |V3 a|V13 a| 585.#451 V80 Use * Keep rcx | |V80 i| | | |V1 a|V2 a| | | | |V3 a|V13 a| 586.#452 I141 Def Alloc rcx | |I141a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 587.#453 I141 Use * Keep rcx | |I141i| | | |V1 a|V2 a| | | | |V3 a|V13 a| 592.#454 I142 Def Alloc rcx | |I142a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 593.#455 rcx Fixd Keep rcx | |I142a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 593.#456 I142 Use * Keep rcx | |I142i| | | |V1 a|V2 a| | | | |V3 a|V13 a| 594.#457 rcx Fixd Keep rcx | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 594.#458 I143 Def Alloc rcx | |I143a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 597.#459 rdx Fixd Keep rdx | |I143a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 597.#460 V14 Use * ReLod rdx | |I143a|V14 a| | |V1 a|V2 a| | | | |V3 a|V13 a| Keep rdx | |I143a|V14 i| | |V1 a|V2 a| | | | |V3 a|V13 a| 598.#461 rdx Fixd Keep rdx | |I143a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 598.#462 I144 Def Alloc rdx | |I143a|I144a| | |V1 a|V2 a| | | | |V3 a|V13 a| 599.#463 rcx Fixd Keep rcx | |I143a|I144a| | |V1 a|V2 a| | | | |V3 a|V13 a| 599.#464 I143 Use * Keep rcx | |I143i|I144a| | |V1 a|V2 a| | | | |V3 a|V13 a| 599.#465 rdx Fixd Keep rdx | | |I144a| | |V1 a|V2 a| | | | |V3 a|V13 a| 599.#466 I144 Use * Keep rdx | | |I144i| | |V1 a|V2 a| | | | |V3 a|V13 a| 600.#467 rax Kill Keep rax | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 600.#468 rcx Kill Keep rcx | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 600.#469 rdx Kill Keep rdx | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 600.#470 r8 Kill Keep r8 | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 600.#471 r9 Kill Keep r9 | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 600.#472 r10 Kill Keep r10 | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 600.#473 r11 Kill Keep r11 | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 604.#474 I145 Def Alloc rcx | |I145a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 605.#475 I145 Use * Keep rcx | |I145i| | | |V1 a|V2 a| | | | |V3 a|V13 a| 606.#476 V64 Def Alloc rcx | |V64 a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 608.#477 I146 Def Alloc rdx | |V64 a|I146a| | |V1 a|V2 a| | | | |V3 a|V13 a| 609.#478 I146 Use * Keep rdx | |V64 a|I146i| | |V1 a|V2 a| | | | |V3 a|V13 a| 610.#479 V65 Def Alloc rdx | |V64 a|V65 a| | |V1 a|V2 a| | | | |V3 a|V13 a| 614.#480 I147 Def Alloc rax |I147a|V64 a|V65 a| | |V1 a|V2 a| | | | |V3 a|V13 a| 615.#481 I147 Use * Keep rax |I147i|V64 a|V65 a| | |V1 a|V2 a| | | | |V3 a|V13 a| 616.#482 V81 Def Alloc rax |V81 a|V64 a|V65 a| | |V1 a|V2 a| | | | |V3 a|V13 a| 621.#483 V81 Use Keep rax |V81 a|V64 a|V65 a| | |V1 a|V2 a| | | | |V3 a|V13 a| 621.#484 V64 Use * Keep rcx |V81 a|V64 i|V65 a| | |V1 a|V2 a| | | | |V3 a|V13 a| 629.#485 V81 Use * Keep rax |V81 i| |V65 a| | |V1 a|V2 a| | | | |V3 a|V13 a| 629.#486 V65 Use * Keep rdx | | |V65 i| | |V1 a|V2 a| | | | |V3 a|V13 a| 632.#487 I148 Def Alloc rcx | |I148a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 633.#488 rcx Fixd Keep rcx | |I148a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 633.#489 I148 Use * Keep rcx | |I148i| | | |V1 a|V2 a| | | | |V3 a|V13 a| 634.#490 rcx Fixd Keep rcx | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 634.#491 I149 Def Alloc rcx | |I149a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 636.#492 I150 Def Alloc rdx | |I149a|I150a| | |V1 a|V2 a| | | | |V3 a|V13 a| 637.#493 rdx Fixd Keep rdx | |I149a|I150a| | |V1 a|V2 a| | | | |V3 a|V13 a| 637.#494 I150 Use * Keep rdx | |I149a|I150i| | |V1 a|V2 a| | | | |V3 a|V13 a| 638.#495 rdx Fixd Keep rdx | |I149a| | | |V1 a|V2 a| | | | |V3 a|V13 a| 638.#496 I151 Def Alloc rdx | |I149a|I151a| | |V1 a|V2 a| | | | |V3 a|V13 a| 639.#497 rcx Fixd Keep rcx | |I149a|I151a| | |V1 a|V2 a| | | | |V3 a|V13 a| 639.#498 I149 Use * Keep rcx | |I149i|I151a| | |V1 a|V2 a| | | | |V3 a|V13 a| 639.#499 rdx Fixd Keep rdx | | |I151a| | |V1 a|V2 a| | | | |V3 a|V13 a| 639.#500 I151 Use * Keep rdx | | |I151i| | |V1 a|V2 a| | | | |V3 a|V13 a| 640.#501 rax Kill Keep rax | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 640.#502 rcx Kill Keep rcx | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 640.#503 rdx Kill Keep rdx | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 640.#504 r8 Kill Keep r8 | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 640.#505 r9 Kill Keep r9 | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 640.#506 r10 Kill Keep r10 | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 640.#507 r11 Kill Keep r11 | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 640.#508 rax Fixd Keep rax | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 640.#509 I152 Def Alloc rax |I152a| | | | |V1 a|V2 a| | | | |V3 a|V13 a| 641.#510 I152 Use * Keep rax |I152i| | | | |V1 a|V2 a| | | | |V3 a|V13 a| 642.#511 V43 Def Alloc rbx | | | |V43 a| |V1 a|V2 a| | | | |V3 a|V13 a| 646.#512 C153 Def Alloc rcx | |C153a| |V43 a| |V1 a|V2 a| | | | |V3 a|V13 a| 647.#513 C153 Use * Keep rcx | |C153i| |V43 a| |V1 a|V2 a| | | | |V3 a|V13 a| 651.#514 V43 Use * Keep rbx | | | |V43 i| |V1 a|V2 a| | | | |V3 a|V13 a| 652.#515 V17 Def Alloc rbx | | | |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 656.#516 I154 Def Alloc rcx | |I154a| |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 657.#517 I154 Use * Keep rcx | |I154i| |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 658.#518 V66 Def Alloc rcx | |V66 a| |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 660.#519 I155 Def Alloc rdx | |V66 a|I155a|V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 661.#520 I155 Use * Keep rdx | |V66 a|I155i|V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 662.#521 V67 Def Alloc rdx | |V66 a|V67 a|V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 666.#522 I156 Def Alloc rax |I156a|V66 a|V67 a|V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 667.#523 I156 Use * Keep rax |I156i|V66 a|V67 a|V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 668.#524 V82 Def Alloc rax |V82 a|V66 a|V67 a|V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 673.#525 V82 Use Keep rax |V82 a|V66 a|V67 a|V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 673.#526 V66 Use * Keep rcx |V82 a|V66 i|V67 a|V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 681.#527 V82 Use * Keep rax |V82 i| |V67 a|V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 681.#528 V67 Use * Keep rdx | | |V67 i|V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 684.#529 I157 Def Alloc rcx | |I157a| |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 685.#530 rcx Fixd Keep rcx | |I157a| |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 685.#531 I157 Use * Keep rcx | |I157i| |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 686.#532 rcx Fixd Keep rcx | | | |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 686.#533 I158 Def Alloc rcx | |I158a| |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 688.#534 I159 Def Alloc rdx | |I158a|I159a|V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 689.#535 rdx Fixd Keep rdx | |I158a|I159a|V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 689.#536 I159 Use * Keep rdx | |I158a|I159i|V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 690.#537 rdx Fixd Keep rdx | |I158a| |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 690.#538 I160 Def Alloc rdx | |I158a|I160a|V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 691.#539 rcx Fixd Keep rcx | |I158a|I160a|V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 691.#540 I158 Use * Keep rcx | |I158i|I160a|V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 691.#541 rdx Fixd Keep rdx | | |I160a|V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 691.#542 I160 Use * Keep rdx | | |I160i|V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 692.#543 rax Kill Keep rax | | | |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 692.#544 rcx Kill Keep rcx | | | |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 692.#545 rdx Kill Keep rdx | | | |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 692.#546 r8 Kill Keep r8 | | | |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 692.#547 r9 Kill Keep r9 | | | |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 692.#548 r10 Kill Keep r10 | | | |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 692.#549 r11 Kill Keep r11 | | | |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 692.#550 rax Fixd Keep rax | | | |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 692.#551 I161 Def Alloc rax |I161a| | |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 693.#552 I161 Use * Keep rax |I161i| | |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 694.#553 V46 Def Alloc rax |V46 a| | |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 698.#554 C162 Def Alloc rcx |V46 a|C162a| |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 699.#555 C162 Use * Keep rcx |V46 a|C162i| |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 703.#556 V46 Use * Keep rax |V46 i| | |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 704.#557 V18 Def Alloc rax |V18 a| | |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 711.#558 V18 Use Keep rax |V18 a| | |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 711.#559 V17 Use Keep rbx |V18 a| | |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 715.#560 BB24 PredBB23 | | | | | |V1 a|V2 a| | | | |V3 a|V13 a| 720.#561 C163 Def Alloc rbp | | | | |C163a|V1 a|V2 a| | | | |V3 a|V13 a| 721.#562 C163 Use * Keep rbp | | | | |C163i|V1 a|V2 a| | | | |V3 a|V13 a| 722.#563 V33 Def Alloc rbp | | | | |V33 a|V1 a|V2 a| | | | |V3 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 723.#564 BB25 PredBB23 |V18 a| | |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 731.#565 V18 Use * Keep rax |V18 i| | |V17 a| |V1 a|V2 a| | | | |V3 a|V13 a| 731.#566 V17 Use *D Keep rbx | | | |V17 i| |V1 a|V2 a| | | | |V3 a|V13 a| 732.#567 I164 Def Alloc rbp | | | | |I164a|V1 a|V2 a| | | | |V3 a|V13 a| 733.#568 I164 Use * Keep rbp | | | | |I164i|V1 a|V2 a| | | | |V3 a|V13 a| 734.#569 V33 Def Alloc rbp | | | | |V33 a|V1 a|V2 a| | | | |V3 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 735.#570 BB26 PredBB24 | | | | |V33 a|V1 a|V2 a| | | | |V3 a|V13 a| 739.#571 V33 Use * Keep rbp | | | | |V33 i|V1 a|V2 a| | | | |V3 a|V13 a| 740.#572 V19 Def Alloc rbp | | | | |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 747.#573 V19 Use Keep rbp | | | | |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 751.#574 BB27 PredBB26 | | | | |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 756.#575 I165 Def Alloc rcx | |I165a| | |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 757.#576 rcx Fixd Keep rcx | |I165a| | |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 757.#577 I165 Use * Keep rcx | |I165i| | |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 758.#578 rcx Fixd Keep rcx | | | | |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 758.#579 I166 Def Alloc rcx | |I166a| | |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 761.#580 rdx Fixd Keep rdx | |I166a| | |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 761.#581 V19 Use Copy rdx | |I166a|V19 a| |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 762.#582 rdx Fixd Keep rdx | |I166a| | |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 762.#583 I167 Def Alloc rdx | |I166a|I167a| |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 763.#584 rcx Fixd Keep rcx | |I166a|I167a| |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 763.#585 I166 Use * Keep rcx | |I166i|I167a| |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 763.#586 rdx Fixd Keep rdx | | |I167a| |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 763.#587 I167 Use * Keep rdx | | |I167i| |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 764.#588 rax Kill Keep rax | | | | |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 764.#589 rcx Kill Keep rcx | | | | |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 764.#590 rdx Kill Keep rdx | | | | |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 764.#591 r8 Kill Keep r8 | | | | |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 764.#592 r9 Kill Keep r9 | | | | |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 764.#593 r10 Kill Keep r10 | | | | |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 764.#594 r11 Kill Keep r11 | | | | |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 765.#595 BB28 PredBB26 | | | | |V19 a|V1 a|V2 a| | | | |V3 a|V13 a| 773.#596 V3 Use * Keep r14 | | | | |V19 a|V1 a|V2 a| | | | |V3 i|V13 a| 773.#597 V13 Use Keep r15 | | | | |V19 a|V1 a|V2 a| | | | | |V13 a| 774.#598 I168 Def Alloc r14 | | | | |V19 a|V1 a|V2 a| | | | |I168a|V13 a| 775.#599 I168 Use * Keep r14 | | | | |V19 a|V1 a|V2 a| | | | |I168i|V13 a| 776.#600 V20 Def Alloc r14 | | | | |V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 781.#601 V20 Use Keep r14 | | | | |V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 782.#602 V21 Def Alloc rbx | | | |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 789.#603 V13 Use Keep r15 | | | |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 793.#604 BB29 PredBB28 | | | | |V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 801.#605 V19 Use Keep rbp | | | | |V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 801.#606 V20 Use Keep r14 | | | | |V19 a|V1 a|V2 a| | | | |V20 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 805.#607 BB30 PredBB29 | | | | | |V1 a|V2 a| | | | | |V13 a| 811.#608 V2 Use * Keep rdi | | | | | |V1 a|V2 i| | | | | |V13 a| 814.#609 C169 Def Alloc r8 | | | | | |V1 a| |C169a| | | | |V13 a| 815.#610 r8 Fixd Keep r8 | | | | | |V1 a| |C169a| | | | |V13 a| 815.#611 C169 Use * Keep r8 | | | | | |V1 a| |C169i| | | | |V13 a| 816.#612 r8 Fixd Keep r8 | | | | | |V1 a| | | | | | |V13 a| 816.#613 I170 Def Alloc r8 | | | | | |V1 a| |I170a| | | | |V13 a| 818.#614 I171 Def Alloc rcx | |I171a| | | |V1 a| |I170a| | | | |V13 a| 819.#615 rcx Fixd Keep rcx | |I171a| | | |V1 a| |I170a| | | | |V13 a| 819.#616 I171 Use * Keep rcx | |I171i| | | |V1 a| |I170a| | | | |V13 a| 820.#617 rcx Fixd Keep rcx | | | | | |V1 a| |I170a| | | | |V13 a| 820.#618 I172 Def Alloc rcx | |I172a| | | |V1 a| |I170a| | | | |V13 a| 823.#619 rdx Fixd Keep rdx | |I172a| | | |V1 a| |I170a| | | | |V13 a| 823.#620 V13 Use * Copy rdx | |I172a|V13 i| | |V1 a| |I170a| | | | |V13 i| 824.#621 rdx Fixd Keep rdx | |I172a| | | |V1 a| |I170a| | | | | | 824.#622 I173 Def Alloc rdx | |I172a|I173a| | |V1 a| |I170a| | | | | | 827.#623 r9 Fixd Keep r9 | |I172a|I173a| | |V1 a| |I170a| | | | | | 827.#624 V1 Use * Copy r9 | |I172a|I173a| | |V1 i| |I170a|V1 i| | | | | 828.#625 r9 Fixd Keep r9 | |I172a|I173a| | | | |I170a| | | | | | 828.#626 I174 Def Alloc r9 | |I172a|I173a| | | | |I170a|I174a| | | | | 829.#627 r8 Fixd Keep r8 | |I172a|I173a| | | | |I170a|I174a| | | | | 829.#628 I170 Use * Keep r8 | |I172a|I173a| | | | |I170i|I174a| | | | | 829.#629 rcx Fixd Keep rcx | |I172a|I173a| | | | | |I174a| | | | | 829.#630 I172 Use * Keep rcx | |I172i|I173a| | | | | |I174a| | | | | 829.#631 rdx Fixd Keep rdx | | |I173a| | | | | |I174a| | | | | 829.#632 I173 Use * Keep rdx | | |I173i| | | | | |I174a| | | | | 829.#633 r9 Fixd Keep r9 | | | | | | | | |I174a| | | | | 829.#634 I174 Use * Keep r9 | | | | | | | | |I174i| | | | | 830.#635 rax Kill Keep rax | | | | | | | | | | | | | | 830.#636 rcx Kill Keep rcx | | | | | | | | | | | | | | 830.#637 rdx Kill Keep rdx | | | | | | | | | | | | | | 830.#638 r8 Kill Keep r8 | | | | | | | | | | | | | | 830.#639 r9 Kill Keep r9 | | | | | | | | | | | | | | 830.#640 r10 Kill Keep r10 | | | | | | | | | | | | | | 830.#641 r11 Kill Keep r11 | | | | | | | | | | | | | | 830.#642 rax Fixd Keep rax | | | | | | | | | | | | | | 830.#643 I175 Def Alloc rax |I175a| | | | | | | | | | | | | 831.#644 I175 Use * Keep rax |I175i| | | | | | | | | | | | | 832.#645 V51 Def Alloc rax |V51 a| | | | | | | | | | | | | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 833.#646 BB31 PredBB29 | | | | |V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 841.#647 V20 Use Keep r14 | | | | |V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 841.#648 V19 Use Keep rbp | | | | |V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 842.#649 I176 Def Alloc rbx | | | |I176a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 843.#650 I176 Use * Keep rbx | | | |I176i|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 844.#651 V21 Def Alloc rbx | | | |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 845.#652 BB32 PredBB28 | | | |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 850.#653 I177 Def Alloc rcx | |I177a| |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 851.#654 I177 Use * Keep rcx | |I177i| |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 854.#655 I178 Def Alloc rcx | |I178a| |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 855.#656 I178 Use * Keep rcx | |I178i| |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 860.#657 I179 Def Alloc rcx | |I179a| |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 861.#658 I179 Use * Keep rcx | |I179i| |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 862.#659 V70 Def Alloc rcx | |V70 a| |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 864.#660 I180 Def Alloc rdx | |V70 a|I180a|V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 865.#661 I180 Use * Keep rdx | |V70 a|I180i|V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 866.#662 V71 Def Alloc rdx | |V70 a|V71 a|V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 868.#663 I181 Def Alloc rax |I181a|V70 a|V71 a|V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 869.#664 I181 Use * Keep rax |I181i|V70 a|V71 a|V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 870.#665 V84 Def Alloc rax |V84 a|V70 a|V71 a|V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 872.#666 I182 Def Alloc r8 |V84 a|V70 a|V71 a|V21 a|V19 a|V1 a|V2 a|I182a| | | |V20 a|V13 a| 873.#667 I182 Use * Keep r8 |V84 a|V70 a|V71 a|V21 a|V19 a|V1 a|V2 a|I182i| | | |V20 a|V13 a| 874.#668 V83 Def Alloc r8 |V84 a|V70 a|V71 a|V21 a|V19 a|V1 a|V2 a|V83 a| | | |V20 a|V13 a| 879.#669 V83 Use Keep r8 |V84 a|V70 a|V71 a|V21 a|V19 a|V1 a|V2 a|V83 a| | | |V20 a|V13 a| 879.#670 V70 Use * Keep rcx |V84 a|V70 i|V71 a|V21 a|V19 a|V1 a|V2 a|V83 a| | | |V20 a|V13 a| 887.#671 V83 Use * Keep r8 |V84 a| |V71 a|V21 a|V19 a|V1 a|V2 a|V83 i| | | |V20 a|V13 a| 887.#672 V71 Use * Keep rdx |V84 a| |V71 i|V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 891.#673 rcx Fixd Keep rcx |V84 a| | |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 891.#674 V84 Use * Copy rcx |V84 i|V84 i| |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 892.#675 rcx Fixd Keep rcx | | | |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 892.#676 I183 Def Alloc rcx | |I183a| |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 894.#677 I184 Def Alloc rdx | |I183a|I184a|V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 895.#678 rdx Fixd Keep rdx | |I183a|I184a|V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 895.#679 I184 Use * Keep rdx | |I183a|I184i|V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 896.#680 rdx Fixd Keep rdx | |I183a| |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 896.#681 I185 Def Alloc rdx | |I183a|I185a|V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 897.#682 rcx Fixd Keep rcx | |I183a|I185a|V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 897.#683 I183 Use * Keep rcx | |I183i|I185a|V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 897.#684 rdx Fixd Keep rdx | | |I185a|V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 897.#685 I185 Use * Keep rdx | | |I185i|V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 898.#686 rax Kill Keep rax | | | |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 898.#687 rcx Kill Keep rcx | | | |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 898.#688 rdx Kill Keep rdx | | | |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 898.#689 r8 Kill Keep r8 | | | |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 898.#690 r9 Kill Keep r9 | | | |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 898.#691 r10 Kill Keep r10 | | | |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 898.#692 r11 Kill Keep r11 | | | |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 898.#693 rax Fixd Keep rax | | | |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 898.#694 I186 Def Alloc rax |I186a| | |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 901.#695 I186 Use * Keep rax |I186i| | |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 905.#696 BB33 PredBB32 | | | |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 911.#697 V19 Use * Keep rbp | | | |V21 a|V19 i|V1 a|V2 a| | | | |V20 a|V13 a| 912.#698 V34 Def Alloc rbp | | | |V21 a|V34 a|V1 a|V2 a| | | | |V20 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 913.#699 BB34 PredBB32 | | | |V21 a|V19 a|V1 a|V2 a| | | | |V20 a|V13 a| 921.#700 V19 Use * Keep rbp | | | |V21 a|V19 i|V1 a|V2 a| | | | |V20 a|V13 a| 922.#701 I187 Def Alloc rbp | | | |V21 a|I187a|V1 a|V2 a| | | | |V20 a|V13 a| 923.#702 I187 Use * Keep rbp | | | |V21 a|I187i|V1 a|V2 a| | | | |V20 a|V13 a| 924.#703 V34 Def Alloc rbp | | | |V21 a|V34 a|V1 a|V2 a| | | | |V20 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 925.#704 BB35 PredBB33 | | | |V21 a|V34 a|V1 a|V2 a| | | | |V20 a|V13 a| 929.#705 V34 Use * Keep rbp | | | |V21 a|V34 i|V1 a|V2 a| | | | |V20 a|V13 a| 930.#706 V22 Def Alloc rbp | | | |V21 a|V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 934.#707 I188 Def Alloc rcx | |I188a| |V21 a|V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 935.#708 rcx Fixd Keep rcx | |I188a| |V21 a|V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 935.#709 I188 Use * Keep rcx | |I188i| |V21 a|V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 936.#710 rcx Fixd Keep rcx | | | |V21 a|V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 936.#711 I189 Def Alloc rcx | |I189a| |V21 a|V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 939.#712 rdx Fixd Keep rdx | |I189a| |V21 a|V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 939.#713 V21 Use * Copy rdx | |I189a|V21 i|V21 i|V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 940.#714 rdx Fixd Keep rdx | |I189a| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 940.#715 I190 Def Alloc rdx | |I189a|I190a| |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 941.#716 rcx Fixd Keep rcx | |I189a|I190a| |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 941.#717 I189 Use * Keep rcx | |I189i|I190a| |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 941.#718 rdx Fixd Keep rdx | | |I190a| |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 941.#719 I190 Use * Keep rdx | | |I190i| |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 942.#720 rax Kill Keep rax | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 942.#721 rcx Kill Keep rcx | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 942.#722 rdx Kill Keep rdx | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 942.#723 r8 Kill Keep r8 | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 942.#724 r9 Kill Keep r9 | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 942.#725 r10 Kill Keep r10 | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 942.#726 r11 Kill Keep r11 | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 946.#727 I191 Def Alloc rcx | |I191a| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 947.#728 I191 Use * Keep rcx | |I191i| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 948.#729 V88 Def Alloc rcx | |V88 a| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 950.#730 I192 Def Alloc rdx | |V88 a|I192a| |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 951.#731 I192 Use * Keep rdx | |V88 a|I192i| |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 952.#732 V85 Def Alloc rdx | |V88 a|V85 a| |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 956.#733 I193 Def Alloc r8 | |V88 a|V85 a| |V22 a|V1 a|V2 a|I193a| | | |V20 a|V13 a| 957.#734 V85 Use Keep rdx | |V88 a|V85 a| |V22 a|V1 a|V2 a|I193a| | | |V20 a|V13 a| 957.#735 I193 Use * Keep r8 | |V88 a|V85 a| |V22 a|V1 a|V2 a|I193i| | | |V20 a|V13 a| 964.#736 I194 Def Alloc r8 | |V88 a|V85 a| |V22 a|V1 a|V2 a|I194a| | | |V20 a|V13 a| 965.#737 V85 Use * Keep rdx | |V88 a|V85 i| |V22 a|V1 a|V2 a|I194a| | | |V20 a|V13 a| 965.#738 I194 Use * Keep r8 | |V88 a| | |V22 a|V1 a|V2 a|I194i| | | |V20 a|V13 a| 968.#739 I195 Def Alloc rdx | |V88 a|I195a| |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 969.#740 I195 Use * Keep rdx | |V88 a|I195i| |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 970.#741 V87 Def Alloc rdx | |V88 a|V87 a| |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 974.#742 I196 Def Alloc r8 | |V88 a|V87 a| |V22 a|V1 a|V2 a|I196a| | | |V20 a|V13 a| 975.#743 V87 Use Keep rdx | |V88 a|V87 a| |V22 a|V1 a|V2 a|I196a| | | |V20 a|V13 a| 975.#744 I196 Use * Keep r8 | |V88 a|V87 a| |V22 a|V1 a|V2 a|I196i| | | |V20 a|V13 a| 982.#745 I197 Def Alloc r8 | |V88 a|V87 a| |V22 a|V1 a|V2 a|I197a| | | |V20 a|V13 a| 983.#746 V87 Use * Keep rdx | |V88 a|V87 i| |V22 a|V1 a|V2 a|I197a| | | |V20 a|V13 a| 983.#747 I197 Use * Keep r8 | |V88 a| | |V22 a|V1 a|V2 a|I197i| | | |V20 a|V13 a| 987.#748 rcx Fixd Keep rcx | |V88 a| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 987.#749 V88 Use * Keep rcx | |V88 i| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 988.#750 rcx Fixd Keep rcx | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 988.#751 I198 Def Alloc rcx | |I198a| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 990.#752 I199 Def Alloc rdx | |I198a|I199a| |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 991.#753 rdx Fixd Keep rdx | |I198a|I199a| |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 991.#754 I199 Use * Keep rdx | |I198a|I199i| |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 992.#755 rdx Fixd Keep rdx | |I198a| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 992.#756 I200 Def Alloc rdx | |I198a|I200a| |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 994.#757 I201 Def Alloc r8 | |I198a|I200a| |V22 a|V1 a|V2 a|I201a| | | |V20 a|V13 a| 995.#758 r8 Fixd Keep r8 | |I198a|I200a| |V22 a|V1 a|V2 a|I201a| | | |V20 a|V13 a| 995.#759 I201 Use * Keep r8 | |I198a|I200a| |V22 a|V1 a|V2 a|I201i| | | |V20 a|V13 a| 996.#760 r8 Fixd Keep r8 | |I198a|I200a| |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 996.#761 I202 Def Alloc r8 | |I198a|I200a| |V22 a|V1 a|V2 a|I202a| | | |V20 a|V13 a| 998.#762 I203 Def Alloc r9 | |I198a|I200a| |V22 a|V1 a|V2 a|I202a|I203a| | |V20 a|V13 a| 999.#763 r9 Fixd Keep r9 | |I198a|I200a| |V22 a|V1 a|V2 a|I202a|I203a| | |V20 a|V13 a| 999.#764 I203 Use * Keep r9 | |I198a|I200a| |V22 a|V1 a|V2 a|I202a|I203i| | |V20 a|V13 a| 1000.#765 r9 Fixd Keep r9 | |I198a|I200a| |V22 a|V1 a|V2 a|I202a| | | |V20 a|V13 a| 1000.#766 I204 Def Alloc r9 | |I198a|I200a| |V22 a|V1 a|V2 a|I202a|I204a| | |V20 a|V13 a| 1001.#767 rcx Fixd Keep rcx | |I198a|I200a| |V22 a|V1 a|V2 a|I202a|I204a| | |V20 a|V13 a| 1001.#768 I198 Use * Keep rcx | |I198i|I200a| |V22 a|V1 a|V2 a|I202a|I204a| | |V20 a|V13 a| 1001.#769 rdx Fixd Keep rdx | | |I200a| |V22 a|V1 a|V2 a|I202a|I204a| | |V20 a|V13 a| 1001.#770 I200 Use * Keep rdx | | |I200i| |V22 a|V1 a|V2 a|I202a|I204a| | |V20 a|V13 a| 1001.#771 r8 Fixd Keep r8 | | | | |V22 a|V1 a|V2 a|I202a|I204a| | |V20 a|V13 a| 1001.#772 I202 Use * Keep r8 | | | | |V22 a|V1 a|V2 a|I202i|I204a| | |V20 a|V13 a| 1001.#773 r9 Fixd Keep r9 | | | | |V22 a|V1 a|V2 a| |I204a| | |V20 a|V13 a| 1001.#774 I204 Use * Keep r9 | | | | |V22 a|V1 a|V2 a| |I204i| | |V20 a|V13 a| 1002.#775 rax Kill Keep rax | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1002.#776 rcx Kill Keep rcx | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1002.#777 rdx Kill Keep rdx | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1002.#778 r8 Kill Keep r8 | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1002.#779 r9 Kill Keep r9 | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1002.#780 r10 Kill Keep r10 | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1002.#781 r11 Kill Keep r11 | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1004.#782 I205 Def Alloc rcx | |I205a| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1005.#783 I205 Use * Keep rcx | |I205i| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1006.#784 V89 Def Alloc rcx | |V89 a| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1010.#785 I206 Def Alloc rax |I206a|V89 a| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1011.#786 V89 Use Keep rcx |I206a|V89 a| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1011.#787 I206 Use * Keep rax |I206i|V89 a| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1018.#788 I207 Def Alloc rax |I207a|V89 a| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1019.#789 V89 Use * Keep rcx |I207a|V89 i| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1019.#790 I207 Use * Keep rax |I207i| | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1022.#791 I208 Def Alloc rcx | |I208a| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1023.#792 rcx Fixd Keep rcx | |I208a| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1023.#793 I208 Use * Keep rcx | |I208i| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1024.#794 rcx Fixd Keep rcx | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1024.#795 I209 Def Alloc rcx | |I209a| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1025.#796 rcx Fixd Keep rcx | |I209a| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1025.#797 I209 Use * Keep rcx | |I209i| | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1026.#798 rax Kill Keep rax | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1026.#799 rcx Kill Keep rcx | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1026.#800 rdx Kill Keep rdx | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1026.#801 r8 Kill Keep r8 | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1026.#802 r9 Kill Keep r9 | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1026.#803 r10 Kill Keep r10 | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1026.#804 r11 Kill Keep r11 | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1026.#805 rax Fixd Keep rax | | | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1026.#806 I210 Def Alloc rax |I210a| | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1027.#807 I210 Use * Keep rax |I210i| | | |V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1028.#808 V24 Def Alloc rbx | | | |V24 a|V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1034.#809 I211 Def Alloc r12 | | | |V24 a|V22 a|V1 a|V2 a| | |I211a| |V20 a|V13 a| 1035.#810 I211 Use * Keep r12 | | | |V24 a|V22 a|V1 a|V2 a| | |I211i| |V20 a|V13 a| 1036.#811 V25 Def Alloc r12 | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1039.#812 rcx Fixd Keep rcx | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1039.#813 V24 Use Copy rcx | |V24 a| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1040.#814 rcx Fixd Keep rcx | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1040.#815 I212 Def Alloc rcx | |I212a| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1041.#816 rcx Fixd Keep rcx | |I212a| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1041.#817 I212 Use * Keep rcx | |I212i| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1042.#818 rax Kill Keep rax | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1042.#819 rcx Kill Keep rcx | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1042.#820 rdx Kill Keep rdx | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1042.#821 r8 Kill Keep r8 | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1042.#822 r9 Kill Keep r9 | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1042.#823 r10 Kill Keep r10 | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1042.#824 r11 Kill Keep r11 | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1042.#825 rax Fixd Keep rax | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1042.#826 I213 Def Alloc rax |I213a| | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1043.#827 I213 Use * Keep rax |I213i| | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1044.#828 V26 Def Alloc rax |V26 a| | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1051.#829 V26 Use Keep rax |V26 a| | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1051.#830 V20 Use Keep r14 |V26 a| | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1055.#831 BB36 PredBB35 |V26 a| | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1063.#832 V26 Use * Keep rax |V26 i| | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1063.#833 V20 Use Keep r14 | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1064.#834 I214 Def Alloc rax |I214a| | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1065.#835 I214 Use * Keep rax |I214i| | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1066.#836 V29 Def Alloc rax |V29 a| | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1073.#837 V25 Use * Keep r12 |V29 a| | |V24 a|V22 a|V1 a|V2 a| | |V25 i| |V20 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1077.#838 BB37 PredBB36 |V29 a| | |V24 a|V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1086.#839 C215 Def Alloc rdx |V29 a| |C215a|V24 a|V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1087.#840 C215 Use * Keep rdx |V29 a| |C215i|V24 a|V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1087.#841 rcx Fixd Keep rcx |V29 a| | |V24 a|V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1087.#842 V29 Use Copy rcx |V29 a|V29 a| |V24 a|V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1088.#843 rcx Kill Keep rcx |V29 a| | |V24 a|V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1088.#844 I216 Def Alloc rdx |V29 a| |I216a|V24 a|V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1091.#845 I216 Use * Keep rdx |V29 a| |I216i|V24 a|V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1092.#846 I217 Def Alloc rdx |V29 a| |I217a|V24 a|V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1093.#847 V24 Use Keep rbx |V29 a| |I217a|V24 a|V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1093.#848 I217 Use * Keep rdx |V29 a| |I217i|V24 a|V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1094.#849 I218 Def Alloc rcx |V29 a|I218a| |V24 a|V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1095.#850 I218 Use * Keep rcx |V29 a|I218i| |V24 a|V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1096.#851 V37 Def Alloc rcx |V29 a|V37 a| |V24 a|V22 a|V1 a|V2 a| | | | |V20 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1097.#852 BB38 PredBB36 |V29 a| | |V24 a|V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1102.#853 C219 Def Alloc rcx |V29 a|C219a| |V24 a|V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1103.#854 C219 Use * Keep rcx |V29 a|C219i| |V24 a|V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1104.#855 V37 Def Alloc rcx |V29 a|V37 a| |V24 a|V22 a|V1 a|V2 a| | | | |V20 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1105.#856 BB39 PredBB37 |V29 a|V37 a| |V24 a|V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1109.#857 V37 Use * Keep rcx |V29 a|V37 i| |V24 a|V22 a|V1 a|V2 a| | | | |V20 a|V13 a| 1110.#858 I220 Def Alloc r12 |V29 a| | |V24 a|V22 a|V1 a|V2 a| | |I220a| |V20 a|V13 a| 1111.#859 I220 Use * Keep r12 |V29 a| | |V24 a|V22 a|V1 a|V2 a| | |I220i| |V20 a|V13 a| 1112.#860 V25 Def Alloc r12 |V29 a| | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1119.#861 V24 Use * Keep rbx |V29 a| | |V24 i|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1119.#862 rcx Fixd Keep rcx |V29 a| | | |V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1119.#863 V29 Use *D Copy rcx |V29 i|V29 i| | |V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1120.#864 rcx Kill Keep rcx | | | | |V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1120.#865 I221 Def Alloc rbx | | | |I221a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1121.#866 I221 Use * Keep rbx | | | |I221i|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1122.#867 V24 Def Alloc rbx | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1123.#868 BB40 PredBB35 | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1126.#869 I222 Def Alloc rcx | |I222a| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1127.#870 I222 Use * Keep rcx | |I222i| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1128.#871 V90 Def Alloc rcx | |V90 a| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1132.#872 I223 Def Alloc rax |I223a|V90 a| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1133.#873 V90 Use Keep rcx |I223a|V90 a| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1133.#874 I223 Use * Keep rax |I223i|V90 a| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1140.#875 I224 Def Alloc rax |I224a|V90 a| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1141.#876 V90 Use * Keep rcx |I224a|V90 i| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1141.#877 I224 Use * Keep rax |I224i| | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1144.#878 I225 Def Alloc rcx | |I225a| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1145.#879 rcx Fixd Keep rcx | |I225a| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1145.#880 I225 Use * Keep rcx | |I225i| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1146.#881 rcx Fixd Keep rcx | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1146.#882 I226 Def Alloc rcx | |I226a| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1147.#883 rcx Fixd Keep rcx | |I226a| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1147.#884 I226 Use * Keep rcx | |I226i| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1148.#885 rax Kill Keep rax | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1148.#886 rcx Kill Keep rcx | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1148.#887 rdx Kill Keep rdx | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1148.#888 r8 Kill Keep r8 | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1148.#889 r9 Kill Keep r9 | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1148.#890 r10 Kill Keep r10 | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1148.#891 r11 Kill Keep r11 | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1148.#892 rax Fixd Keep rax | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1148.#893 I227 Def Alloc rax |I227a| | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1151.#894 I227 Use * Keep rax |I227i| | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1151.#895 rcx Fixd Keep rcx | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 a|V13 a| 1151.#896 V20 Use *D Copy rcx | |V20 i| |V24 a|V22 a|V1 a|V2 a| | |V25 a| |V20 i|V13 a| 1152.#897 rcx Kill Keep rcx | | | |V24 a|V22 a|V1 a|V2 a| | |V25 a| | |V13 a| 1152.#898 I228 Def Alloc rax |I228a| | |V24 a|V22 a|V1 a|V2 a| | |V25 a| | |V13 a| 1155.#899 I228 Use * Keep rax |I228i| | |V24 a|V22 a|V1 a|V2 a| | |V25 a| | |V13 a| 1155.#900 V24 Use * Keep rbx | | | |V24 i|V22 a|V1 a|V2 a| | |V25 a| | |V13 a| 1156.#901 I229 Def Alloc rdx | | |I229a| |V22 a|V1 a|V2 a| | |V25 a| | |V13 a| 1157.#902 I229 Use * Keep rdx | | |I229i| |V22 a|V1 a|V2 a| | |V25 a| | |V13 a| 1158.#903 V27 Def Alloc rdx | | |V27 a| |V22 a|V1 a|V2 a| | |V25 a| | |V13 a| 1165.#904 V13 Use Keep r15 | | |V27 a| |V22 a|V1 a|V2 a| | |V25 a| | |V13 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1169.#905 BB41 PredBB40 | | |V27 a| |V22 a|V1 a|V2 a| | |V25 a| | | | 1175.#906 V22 Use * Keep rbp | | |V27 a| |V22 i|V1 a|V2 a| | |V25 a| | | | 1176.#907 I230 Def Alloc r8 | | |V27 a| | |V1 a|V2 a|I230a| |V25 a| | | | 1179.#908 I230 Use * Keep r8 | | |V27 a| | |V1 a|V2 a|I230i| |V25 a| | | | 1180.#909 I231 Def Alloc r8 | | |V27 a| | |V1 a|V2 a|I231a| |V25 a| | | | 1181.#910 I231 Use * Keep r8 | | |V27 a| | |V1 a|V2 a|I231i| |V25 a| | | | 1182.#911 V36 Def Alloc r8 | | |V27 a| | |V1 a|V2 a|V36 a| |V25 a| | | | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1183.#912 BB42 PredBB40 | | |V27 a| | |V1 a|V2 a| | |V25 a| | |V13 a| 1191.#913 V13 Use * Keep r15 | | |V27 a| | |V1 a|V2 a| | |V25 a| | |V13 i| 1192.#914 I232 Def Alloc r8 | | |V27 a| | |V1 a|V2 a|I232a| |V25 a| | | | 1193.#915 I232 Use * Keep r8 | | |V27 a| | |V1 a|V2 a|I232i| |V25 a| | | | 1194.#916 V36 Def Alloc r8 | | |V27 a| | |V1 a|V2 a|V36 a| |V25 a| | | | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1195.#917 BB43 PredBB41 | | |V27 a| | |V1 a|V2 a|V36 a| |V25 a| | | | 1201.#918 V2 Use * Keep rdi | | |V27 a| | |V1 a|V2 i|V36 a| |V25 a| | | | 1205.#919 rcx Fixd Keep rcx | | |V27 a| | |V1 a| |V36 a| |V25 a| | | | 1205.#920 V1 Use * Copy rcx | |V1 i|V27 a| | |V1 i| |V36 a| |V25 a| | | | 1206.#921 rcx Fixd Keep rcx | | |V27 a| | | | |V36 a| |V25 a| | | | 1206.#922 I233 Def Alloc rcx | |I233a|V27 a| | | | |V36 a| |V25 a| | | | 1209.#923 rdx Fixd Keep rdx | |I233a|V27 a| | | | |V36 a| |V25 a| | | | 1209.#924 V27 Use * Keep rdx | |I233a|V27 i| | | | |V36 a| |V25 a| | | | 1210.#925 rdx Fixd Keep rdx | |I233a| | | | | |V36 a| |V25 a| | | | 1210.#926 I234 Def Alloc rdx | |I233a|I234a| | | | |V36 a| |V25 a| | | | 1213.#927 r8 Fixd Keep r8 | |I233a|I234a| | | | |V36 a| |V25 a| | | | 1213.#928 V36 Use * Keep r8 | |I233a|I234a| | | | |V36 i| |V25 a| | | | 1214.#929 r8 Fixd Keep r8 | |I233a|I234a| | | | | | |V25 a| | | | 1214.#930 I235 Def Alloc r8 | |I233a|I234a| | | | |I235a| |V25 a| | | | 1217.#931 r9 Fixd Keep r9 | |I233a|I234a| | | | |I235a| |V25 a| | | | 1217.#932 V25 Use * Copy r9 | |I233a|I234a| | | | |I235a|V25 i|V25 i| | | | 1218.#933 r9 Fixd Keep r9 | |I233a|I234a| | | | |I235a| | | | | | 1218.#934 I236 Def Alloc r9 | |I233a|I234a| | | | |I235a|I236a| | | | | 1219.#935 rcx Fixd Keep rcx | |I233a|I234a| | | | |I235a|I236a| | | | | 1219.#936 I233 Use * Keep rcx | |I233i|I234a| | | | |I235a|I236a| | | | | 1219.#937 rdx Fixd Keep rdx | | |I234a| | | | |I235a|I236a| | | | | 1219.#938 I234 Use * Keep rdx | | |I234i| | | | |I235a|I236a| | | | | 1219.#939 r8 Fixd Keep r8 | | | | | | | |I235a|I236a| | | | | 1219.#940 I235 Use * Keep r8 | | | | | | | |I235i|I236a| | | | | 1219.#941 r9 Fixd Keep r9 | | | | | | | | |I236a| | | | | 1219.#942 I236 Use * Keep r9 | | | | | | | | |I236i| | | | | 1220.#943 rax Kill Keep rax | | | | | | | | | | | | | | 1220.#944 rcx Kill Keep rcx | | | | | | | | | | | | | | 1220.#945 rdx Kill Keep rdx | | | | | | | | | | | | | | 1220.#946 r8 Kill Keep r8 | | | | | | | | | | | | | | 1220.#947 r9 Kill Keep r9 | | | | | | | | | | | | | | 1220.#948 r10 Kill Keep r10 | | | | | | | | | | | | | | 1220.#949 r11 Kill Keep r11 | | | | | | | | | | | | | | 1220.#950 rax Fixd Keep rax | | | | | | | | | | | | | | 1220.#951 I237 Def Alloc rax |I237a| | | | | | | | | | | | | 1221.#952 I237 Use * Keep rax |I237i| | | | | | | | | | | | | 1222.#953 V51 Def Alloc rax |V51 a| | | | | | | | | | | | | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1223.#954 BB44 PredBB16 |V51 a| | | | | | | | | | | | | 1227.#955 rax Fixd Keep rax |V51 a| | | | | | | | | | | | | 1227.#956 V51 Use * Keep rax |V51 i| | | | | | | | | | | | | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 0.#0 BB45 PredBB20 | | | | | | | | | | | | | | 1227.#0 V14 Move STK | | | |V52 a|V53 a|V1 a|V2 a| | |V8 a|V9 a|V3 a|V13 a| Recording the maximum number of concurrent spills: ---------- LSRA Stats ---------- BB10 [ 50]: SpillCount = 1, ResolutionMovs = 0, SplitEdges = 0, CopyReg = 0 BB15 [ 50]: SpillCount = 0, ResolutionMovs = 1, SplitEdges = 0, CopyReg = 0 BB20 [ 50]: SpillCount = 0, ResolutionMovs = 0, SplitEdges = 1, CopyReg = 0 BB21 [ 50]: SpillCount = 3, ResolutionMovs = 0, SplitEdges = 0, CopyReg = 0 Total Tracked Vars: 58 Total Reg Cand Vars: 58 Total number of Intervals: 237 Total number of RefPositions: 956 Total Spill Count: 4 Weighted: 200 Total CopyReg Count: 0 Weighted: 0 Total ResolutionMov Count: 1 Weighted: 50 Total number of split edges: 1 Total Number of spill temps created: 0 TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS Incoming Parameters: V01(rdx=>rsi) V00(rcx) V02(r8=>rdi) BB01 [???..???), preds={} succs={BB02} ===== N003. V00(rcx) N005. rbx = IND ; rcx * N007. V52(rbx); rbx N009. V00(rcx*) N011. STK = LEA(b+8) ; rcx* N013. rbp = IND ; STK * N015. V53(rbp); rbp Var=Reg end of BB01: V01=rsi V02=rdi V52=rbx V53=rbp BB02 [000..00D) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ===== Predecessor for variable locations: BB01 Var=Reg beg of BB02: V01=rsi V02=rdi V52=rbx V53=rbp N019. IL_OFFSET IL offset: 0x0 N021. V52(rbx) N023. STK = LEA(b+8) ; rbx N025. STK = IND ; STK N027. CNS_INT 0 N029. NE ; STK N031. JTRUE Var=Reg end of BB02: V01=rsi V02=rdi V52=rbx V53=rbp BB03 [00D..017) (return), preds={BB02} succs={} ===== Predecessor for variable locations: BB02 Var=Reg beg of BB03: V01=rsi V02=rdi N035. IL_OFFSET IL offset: 0xd N037. V01(rsi) N039. rcx = PUTARG_REG; rsi N041. V01(rsi*) N043. STK = LEA(b+0) ; rsi* N045. rax = IND ; STK N047. STK = LEA(b+80); rax N049. rax = IND ; STK N051. STK = LEA(b+0) ; rax N053. STK = IND ; STK N055. rax = CALLV ind; rcx,STK N057. V02(rdi*) N059. STOREIND ; rdi*,rax N061. rax = CNS_INT 1 N063. RETURN ; rax Var=Reg end of BB03: none BB04 [017..065) -> BB06 (cond), preds={BB02} succs={BB05,BB06} ===== Predecessor for variable locations: BB02 Var=Reg beg of BB04: V01=rsi V02=rdi V52=rbx V53=rbp N067. V01(rsi) N069. rcx = PUTARG_REG; rsi N071. V01(rsi) N073. STK = LEA(b+0) ; rsi N075. rax = IND ; STK N077. STK = LEA(b+72); rax N079. rax = IND ; STK N081. STK = LEA(b+32); rax N083. STK = IND ; STK N085. rax = CALLV ind; rcx,STK N087. CNS_INT 1 N089. rax = ADD ; rax N091. r14 = CAST ; rax N093. CNS_INT 1 N095. r14 = ADD ; r14 * N097. V03(r14); r14 N099. IL_OFFSET IL offset: 0x20 N101. V53(rbp) * N103. V40(rcx); rbp N105. IL_OFFSET IL offset: 0x20 N107. V40(rcx*) N109. CNS_INT 0 N111. LE ; rcx* N113. JTRUE Var=Reg end of BB04: V01=rsi V02=rdi V52=rbx V53=rbp V03=r14 BB05 [020..021) -> BB07 (always), preds={BB04} succs={BB07} ===== Predecessor for variable locations: BB04 Var=Reg beg of BB05: V01=rsi V02=rdi V52=rbx V53=rbp V03=r14 N117. IL_OFFSET IL offset: 0x20 N119. V53(rbp) * N121. V39(r15); rbp Var=Reg end of BB05: V01=rsi V02=rdi V52=rbx V53=rbp V03=r14 V39=r15 BB06 [020..021), preds={BB04} succs={BB07} ===== Predecessor for variable locations: BB04 Var=Reg beg of BB06: V01=rsi V02=rdi V52=rbx V53=rbp V03=r14 N125. IL_OFFSET IL offset: 0x20 N127. r15 = CNS_INT 0 * N129. V39(r15); r15 Var=Reg end of BB06: V01=rsi V02=rdi V52=rbx V53=rbp V03=r14 V39=r15 BB07 [000..000) -> BB09 (cond), preds={BB05,BB06} succs={BB08,BB09} ===== Predecessor for variable locations: BB05 Var=Reg beg of BB07: V01=rsi V02=rdi V52=rbx V53=rbp V03=r14 V39=r15 N133. V39(r15*) * N135. V31(r15); r15* N137. V52(rbx) N139. STK = LEA(b+8) ; rbx N141. r12 = IND ; STK * N143. V42(r12); r12 N145. V31(r15) N147. V42(r12) N149. LE ; r15,r12 N151. JTRUE Var=Reg end of BB07: V01=rsi V02=rdi V52=rbx V53=rbp V31=r15 V42=r12 V03=r14 BB08 [000..000) -> BB10 (always), preds={BB07} succs={BB10} ===== Predecessor for variable locations: BB07 Var=Reg beg of BB08: V01=rsi V02=rdi V52=rbx V53=rbp V31=r15 V42=r12 V03=r14 N155. V42(r12*) * N157. V41(r12); r12* Var=Reg end of BB08: V01=rsi V02=rdi V52=rbx V53=rbp V31=r15 V41=r12 V03=r14 BB09 [000..000), preds={BB07} succs={BB10} ===== Predecessor for variable locations: BB07 Var=Reg beg of BB09: V01=rsi V02=rdi V52=rbx V53=rbp V31=r15 V03=r14 N161. V31(r15) * N163. V41(r12); r15 Var=Reg end of BB09: V01=rsi V02=rdi V52=rbx V53=rbp V31=r15 V41=r12 V03=r14 BB10 [???..???) -> BB14 (cond), preds={BB08,BB09} succs={BB11,BB14} ===== Predecessor for variable locations: BB08 Var=Reg beg of BB10: V01=rsi V02=rdi V52=rbx V53=rbp V31=r15 V41=r12 V03=r14 N167. V31(r15*) N169. V41(r12) N171. r15 = SUB ; r15*,r12 * N173. V05(r15); r15 N175. IL_OFFSET IL offset: 0x42 N177. V41(r12*) * N179. V08(r12); r12* N181. V52(rbx) N183. STK = LEA(b+8) ; rbx N185. r13 = IND ; STK * N187. V09(r13); r13 N189. IL_OFFSET IL offset: 0x4f N191. V09(r13) N193. V08(r12) N195. rax = SUB ; r13,r12 N197. V10(STK); rax N199. rcx = LCL_VAR_ADDR V11 loc8 rcx ref V11._bits (offs=0x00) -> V54 tmp24 int V11._sign (offs=0x08) -> V55 tmp25 * N201. V75(rcx); rcx N203. rdx = LCL_VAR_ADDR V73 tmp43 rdx * N205. V74(rdx); rdx N207. V74(rdx) N209. V52(rbx) N211. STOREIND ; rdx,rbx N213. V74(rdx*) N215. STK = LEA(b+8) ; rdx* N217. V53(rbp) N219. STOREIND ; STK,rbp N221. V75(rcx*) N223. rcx = PUTARG_REG; rcx* N225. rdx = LCL_VAR_ADDR V73 tmp43 rdx N227. rdx = PUTARG_REG; rdx N229. V08(r12) N231. r9 = PUTARG_REG; r12 N233. r8 = CNS_INT 0 N235. r8 = PUTARG_REG; r8 N237. CALL ; rcx,rdx,r9,r8 N239. IL_OFFSET IL offset: 0x61 N241. V05(r15) N243. CNS_INT 0 N245. EQ ; r15 N247. JTRUE Var=Reg end of BB10: V01=rsi V02=rdi V52=rbx V53=rbp V05=r15 V08=r12 V03=r14 V09=r13 BB11 [065..070) -> BB13 (cond), preds={BB10} succs={BB12,BB13} ===== Predecessor for variable locations: BB10 Var=Reg beg of BB11: V01=rsi V02=rdi V52=rbx V53=rbp V05=r15 V08=r12 V03=r14 V09=r13 N251. V01(rsi) N253. rcx = PUTARG_REG; rsi N255. rax = CALL ; rcx N257. rcx = CAST ; rax N259. V05(r15) N261. rax = CAST ; r15 N263. GE ; rcx,rax N265. JTRUE Var=Reg end of BB11: V01=rsi V02=rdi V52=rbx V53=rbp V05=r15 V08=r12 V03=r14 V09=r13 BB12 [070..07A) (return), preds={BB11} succs={} ===== Predecessor for variable locations: BB11 Var=Reg beg of BB12: V01=rsi V02=rdi N269. IL_OFFSET IL offset: 0x70 N271. V01(rsi) N273. rcx = PUTARG_REG; rsi N275. V01(rsi*) N277. STK = LEA(b+0) ; rsi* N279. rax = IND ; STK N281. STK = LEA(b+80); rax N283. rax = IND ; STK N285. STK = LEA(b+8) ; rax N287. STK = IND ; STK N289. rax = CALLV ind; rcx,STK N291. V02(rdi*) N293. STOREIND ; rdi*,rax N295. rax = CNS_INT 3 N297. RETURN ; rax Var=Reg end of BB12: none BB13 [07A..082), preds={BB11} succs={BB14} ===== Predecessor for variable locations: BB11 Var=Reg beg of BB13: V01=rsi V02=rdi V52=rbx V53=rbp V05=r15 V08=r12 V03=r14 V09=r13 N301. IL_OFFSET IL offset: 0x7a N303. rcx = LCL_VAR_ADDR V11 loc8 rcx ref V11._bits (offs=0x00) -> V54 tmp24 int V11._sign (offs=0x08) -> V55 tmp25 N305. rcx = PUTARG_REG; rcx N307. V05(r15*) N309. rdx = PUTARG_REG; r15* N311. CALL ; rcx,rdx Var=Reg end of BB13: V01=rsi V02=rdi V52=rbx V53=rbp V08=r12 V03=r14 V09=r13 BB14 [082..092) -> BB16 (cond), preds={BB10,BB13} succs={BB15,BB16} ===== Predecessor for variable locations: BB10 Var=Reg beg of BB14: V01=rsi V02=rdi V52=rbx V53=rbp V08=r12 V03=r14 V09=r13 N315. rcx = LCL_VAR_ADDR V76 tmp46 rcx * N317. V77(rcx); rcx N319. V77(rcx) N321. rdx = V54 MEM N323. STOREIND ; rcx,rdx N325. V77(rcx*) N327. STK = LEA(b+8) ; rcx* N329. rdx = V55 MEM N331. STOREIND ; STK,rdx N333. rcx = LCL_VAR_ADDR V76 tmp46 rcx N335. rcx = PUTARG_REG; rcx N337. rdx = LCL_VAR_ADDR V12 loc9 rdx N339. rdx = PUTARG_REG; rdx N341. rax = CALL ; rcx,rdx * N343. V13(r15); rax N345. IL_OFFSET IL offset: 0x8d N347. V13(r15) N349. V03(r14) N351. GE ; r15,r14 N353. JTRUE Var=Reg end of BB14: V01=rsi V02=rdi V13=r15 V52=rbx V53=rbp V08=r12 V03=r14 V09=r13 BB15 [092..096) -> BB17 (cond), preds={BB14} succs={BB16,BB17} ===== Predecessor for variable locations: BB14 Var=Reg beg of BB15: V01=rsi V02=rdi V13=r15 V52=rbx V53=rbp V08=r12 V03=r14 V09=r13 N357. IL_OFFSET IL offset: 0x92 N359. V10(rax)R N361. CNS_INT 0 N363. NE ; rax $ N001. V10(rax) N365. JTRUE Var=Reg end of BB15: V01=rsi V02=rdi V13=r15 V52=rbx V53=rbp V08=r12 V03=r14 V09=r13 BB16 [096..0A7) -> BB44 (always), preds={BB14,BB15} succs={BB44} ===== Predecessor for variable locations: BB14 Var=Reg beg of BB16: V01=rsi V02=rdi V13=r15 N369. IL_OFFSET IL offset: 0x96 N371. V02(rdi*) N373. PUTARG_STK [+0x20]; rdi* N375. V10(STK*) N377. CNS_INT 0 N379. r8 = NE N381. r8 = PUTARG_REG; r8 N383. rcx = V12 MEM N385. rcx = PUTARG_REG; rcx N387. V13(r15*) N389. rdx = PUTARG_REG; r15* N391. V01(rsi*) N393. r9 = PUTARG_REG; rsi* N395. rax = CALL ; r8,rcx,rdx,r9 * N397. V51(rax); rax Var=Reg end of BB16: V51=rax BB17 [0A7..0B0) -> BB19 (cond), preds={BB15} succs={BB18,BB19} ===== Predecessor for variable locations: BB14 Var=Reg beg of BB17: V01=rsi V02=rdi V13=r15 V52=rbx V53=rbp V08=r12 V03=r14 V09=r13 N401. IL_OFFSET IL offset: 0xa7 N403. V53(rbp) N405. CNS_INT 0 N407. LT ; rbp N409. JTRUE Var=Reg end of BB17: V01=rsi V02=rdi V13=r15 V52=rbx V53=rbp V08=r12 V03=r14 V09=r13 BB18 [0B0..0B4) -> BB20 (always), preds={BB17} succs={BB20} ===== Predecessor for variable locations: BB17 Var=Reg beg of BB18: V01=rsi V02=rdi V13=r15 V52=rbx V53=rbp V08=r12 V03=r14 V09=r13 N413. IL_OFFSET IL offset: 0xb0 N415. V10(rax*)R * N417. V32(rdx); rax* Var=Reg end of BB18: V01=rsi V02=rdi V13=r15 V52=rbx V53=rbp V08=r12 V03=r14 V09=r13 V32=rdx BB19 [0B4..0BE), preds={BB17} succs={BB20} ===== Predecessor for variable locations: BB17 Var=Reg beg of BB19: V01=rsi V02=rdi V13=r15 V52=rbx V53=rbp V08=r12 V03=r14 V09=r13 N421. IL_OFFSET IL offset: 0xb4 N423. V10(rax*)R N425. V53(rbp) N427. rdx = SUB ; rax*,rbp * N429. V32(rdx); rdx Var=Reg end of BB19: V01=rsi V02=rdi V13=r15 V52=rbx V53=rbp V08=r12 V03=r14 V09=r13 V32=rdx BB20 [0BE..0C4) -> BB45 (cond), preds={BB18,BB19} succs={BB21,BB45} ===== Predecessor for variable locations: BB18 Var=Reg beg of BB20: V01=rsi V02=rdi V13=r15 V52=rbx V53=rbp V08=r12 V03=r14 V09=r13 V32=rdx N433. V32(rdx*) * N435. V14(rax); rdx* N437. IL_OFFSET IL offset: 0xc0 N439. V13(r15) N441. CNS_INT 0 N443. NE ; r15 N445. JTRUE Var=Reg end of BB20: V01=rsi V02=rdi V13=r15 V52=rbx V53=rbp V08=r12 V03=r14 V09=r13 V14=rax BB21 [0C4..0D9) -> BB23 (cond), preds={BB20} succs={BB22,BB23} ===== Predecessor for variable locations: BB20 Var=Reg beg of BB21: V01=rsi V02=rdi V13=r15 V52=rbx V53=rbp V08=r12 V03=r14 V09=r13 V14=rax N449. V52(rbx) N451. STK = LEA(b+8) ; rbx N453. rcx = IND ; STK N455. rcx = CAST ; rcx S N457. V14(rax) N459. rdx = CAST ; rax N461. rdx = SUB ; rdx,rcx N463. V38(STK); rdx N465. V01(rsi) N467. rcx = PUTARG_REG; rsi N469. rax = CALL ; rcx N471. rcx = CAST ; rax N473. V38(STK*) N475. GE ; rcx N477. JTRUE Var=Reg end of BB21: V01=rsi V02=rdi V13=r15 V52=rbx V53=rbp V08=r12 V03=r14 V09=r13 BB22 [0D9..0E3) (return), preds={BB21} succs={} ===== Predecessor for variable locations: BB21 Var=Reg beg of BB22: V01=rsi V02=rdi N481. IL_OFFSET IL offset: 0xd9 N483. V01(rsi) N485. rcx = PUTARG_REG; rsi N487. V01(rsi*) N489. STK = LEA(b+0) ; rsi* N491. rax = IND ; STK N493. STK = LEA(b+80); rax N495. rax = IND ; STK N497. STK = LEA(b+0) ; rax N499. STK = IND ; STK N501. rax = CALLV ind; rcx,STK N503. V02(rdi*) N505. STOREIND ; rdi*,rax N507. rax = CNS_INT 2 N509. RETURN ; rax Var=Reg end of BB22: none BB23 [0E3..117) -> BB25 (cond), preds={BB45,BB21} succs={BB24,BB25} ===== Predecessor for variable locations: BB20 Var=Reg beg of BB23: V01=rsi V02=rdi V13=r15 V52=rbx V53=rbp V08=r12 V03=r14 V09=r13 N513. rcx = LCL_VAR_ADDR V15 loc12 rcx ref V15._bits (offs=0x00) -> V56 tmp26 int V15._sign (offs=0x08) -> V57 tmp27 * N515. V79(rcx); rcx N517. rdx = LCL_VAR_ADDR V73 tmp43 rdx * N519. V78(rdx); rdx N521. V78(rdx) N523. V52(rbx*) N525. STOREIND ; rdx,rbx* N527. V78(rdx*) N529. STK = LEA(b+8) ; rdx* N531. V53(rbp*) N533. STOREIND ; STK,rbp* N535. V79(rcx*) N537. rcx = PUTARG_REG; rcx* N539. rdx = LCL_VAR_ADDR V73 tmp43 rdx N541. rdx = PUTARG_REG; rdx N543. V08(r12*) N545. r8 = PUTARG_REG; r12* N547. V09(r13*) N549. r9 = PUTARG_REG; r13* N551. CALL ; rcx,rdx,r8,r9 N553. IL_OFFSET IL offset: 0xef N555. rcx = CNS_INT 0x7ff815262aa0 N557. rcx = PUTARG_REG; rcx N559. rdx = CNS_INT 173 N561. rdx = PUTARG_REG; rdx * N563. rax = CALL help; rcx,rdx N565. rcx = CNS_INT(h) 0xd1ffab1e static Fseq[BigOne] N567. rcx = IND ; rcx N569. CNS_INT 8 Fseq[#FirstElem] N571. rcx = ADD ; rcx * N573. V80(rcx); rcx N575. V80(rcx) N577. rdx = IND ; rcx N579. V58 MEM; rdx N581. V80(rcx*) N583. STK = LEA(b+8) ; rcx* N585. rcx = IND ; STK N587. V59 MEM; rcx N589. IL_OFFSET IL offset: 0xf6 N591. rcx = LCL_VAR_ADDR V16 loc13 rcx ref V16._bits (offs=0x00) -> V58 tmp28 int V16._sign (offs=0x08) -> V59 tmp29 N593. rcx = PUTARG_REG; rcx N595. V14(rdx*)R N597. rdx = PUTARG_REG; rdx* N599. CALL ; rcx,rdx N601. IL_OFFSET IL offset: 0xff N603. rcx = V56 MEM * N605. V64(rcx); rcx N607. rdx = V57 MEM * N609. V65(rdx); rdx N611. IL_OFFSET IL offset: 0xff N613. rax = LCL_VAR_ADDR V76 tmp46 rax * N615. V81(rax); rax N617. V81(rax) N619. V64(rcx*) N621. STOREIND ; rax,rcx* N623. V81(rax*) N625. STK = LEA(b+8) ; rax* N627. V65(rdx*) N629. STOREIND ; STK,rdx* N631. rcx = LCL_VAR_ADDR V76 tmp46 rcx N633. rcx = PUTARG_REG; rcx N635. rdx = LCL_VAR_ADDR V45 tmp15 rdx N637. rdx = PUTARG_REG; rdx N639. rax = CALL ; rcx,rdx * N641. V43(rbx); rax N643. IL_OFFSET IL offset: 0xff N645. rcx = CNS_INT null N647. V45 MEM; rcx N649. V43(rbx*) * N651. V17(rbx); rbx* N653. IL_OFFSET IL offset: 0x108 N655. rcx = V58 MEM * N657. V66(rcx); rcx N659. rdx = V59 MEM * N661. V67(rdx); rdx N663. IL_OFFSET IL offset: 0x108 N665. rax = LCL_VAR_ADDR V76 tmp46 rax * N667. V82(rax); rax N669. V82(rax) N671. V66(rcx*) N673. STOREIND ; rax,rcx* N675. V82(rax*) N677. STK = LEA(b+8) ; rax* N679. V67(rdx*) N681. STOREIND ; STK,rdx* N683. rcx = LCL_VAR_ADDR V76 tmp46 rcx N685. rcx = PUTARG_REG; rcx N687. rdx = LCL_VAR_ADDR V48 tmp18 rdx N689. rdx = PUTARG_REG; rdx N691. rax = CALL ; rcx,rdx * N693. V46(rax); rax N695. IL_OFFSET IL offset: 0x108 N697. rcx = CNS_INT null N699. V48 MEM; rcx N701. V46(rax*) * N703. V18(rax); rax* N705. IL_OFFSET IL offset: 0x111 N707. V18(rax) N709. V17(rbx) N711. GT ; rax,rbx N713. JTRUE Var=Reg end of BB23: V01=rsi V02=rdi V13=r15 V03=r14 V17=rbx V18=rax BB24 [117..11A) -> BB26 (always), preds={BB23} succs={BB26} ===== Predecessor for variable locations: BB23 Var=Reg beg of BB24: V01=rsi V02=rdi V13=r15 V03=r14 N717. IL_OFFSET IL offset: 0x117 N719. rbp = CNS_INT 0 * N721. V33(rbp); rbp Var=Reg end of BB24: V01=rsi V02=rdi V13=r15 V03=r14 V33=rbp BB25 [11A..11F), preds={BB23} succs={BB26} ===== Predecessor for variable locations: BB23 Var=Reg beg of BB25: V01=rsi V02=rdi V13=r15 V03=r14 V17=rbx V18=rax N725. IL_OFFSET IL offset: 0x11a N727. V18(rax*) N729. V17(rbx*) N731. rbp = SUB ; rax*,rbx* * N733. V33(rbp); rbp Var=Reg end of BB25: V01=rsi V02=rdi V13=r15 V03=r14 V33=rbp BB26 [11F..126) -> BB28 (cond), preds={BB24,BB25} succs={BB27,BB28} ===== Predecessor for variable locations: BB24 Var=Reg beg of BB26: V01=rsi V02=rdi V13=r15 V03=r14 V33=rbp N737. V33(rbp*) * N739. V19(rbp); rbp* N741. IL_OFFSET IL offset: 0x121 N743. V19(rbp) N745. CNS_INT 0 N747. EQ ; rbp N749. JTRUE Var=Reg end of BB26: V01=rsi V02=rdi V13=r15 V19=rbp V03=r14 BB27 [126..12F), preds={BB26} succs={BB28} ===== Predecessor for variable locations: BB26 Var=Reg beg of BB27: V01=rsi V02=rdi V13=r15 V19=rbp V03=r14 N753. IL_OFFSET IL offset: 0x126 N755. rcx = LCL_VAR_ADDR V15 loc12 rcx ref V15._bits (offs=0x00) -> V56 tmp26 int V15._sign (offs=0x08) -> V57 tmp27 N757. rcx = PUTARG_REG; rcx N759. V19(rbp) N761. rdx = PUTARG_REG; rbp N763. CALL ; rcx,rdx Var=Reg end of BB27: V01=rsi V02=rdi V13=r15 V19=rbp V03=r14 BB28 [12F..13E) -> BB32 (cond), preds={BB26,BB27} succs={BB29,BB32} ===== Predecessor for variable locations: BB26 Var=Reg beg of BB28: V01=rsi V02=rdi V13=r15 V19=rbp V03=r14 N767. IL_OFFSET IL offset: 0x12f N769. V03(r14*) N771. V13(r15) N773. r14 = SUB ; r14*,r15 * N775. V20(r14); r14 N777. IL_OFFSET IL offset: 0x135 N779. V20(r14) * N781. V21(rbx); r14 N783. IL_OFFSET IL offset: 0x139 N785. V13(r15) N787. CNS_INT 0 N789. EQ ; r15 N791. JTRUE Var=Reg end of BB28: V01=rsi V02=rdi V13=r15 V19=rbp V20=r14 V21=rbx BB29 [13E..144) -> BB31 (cond), preds={BB28} succs={BB30,BB31} ===== Predecessor for variable locations: BB28 Var=Reg beg of BB29: V01=rsi V02=rdi V13=r15 V19=rbp V20=r14 N795. IL_OFFSET IL offset: 0x13e N797. V19(rbp) N799. V20(r14) N801. LE ; rbp,r14 N803. JTRUE Var=Reg end of BB29: V01=rsi V02=rdi V13=r15 V19=rbp V20=r14 BB30 [144..155) -> BB44 (always), preds={BB29} succs={BB44} ===== Predecessor for variable locations: BB29 Var=Reg beg of BB30: V01=rsi V02=rdi V13=r15 N807. IL_OFFSET IL offset: 0x144 N809. V02(rdi*) N811. PUTARG_STK [+0x20]; rdi* N813. r8 = CNS_INT 1 N815. r8 = PUTARG_REG; r8 N817. rcx = V12 MEM N819. rcx = PUTARG_REG; rcx N821. V13(r15*) N823. rdx = PUTARG_REG; r15* N825. V01(rsi*) N827. r9 = PUTARG_REG; rsi* N829. rax = CALL ; r8,rcx,rdx,r9 * N831. V51(rax); rax Var=Reg end of BB30: V51=rax BB31 [155..15C), preds={BB29} succs={BB32} ===== Predecessor for variable locations: BB29 Var=Reg beg of BB31: V01=rsi V02=rdi V13=r15 V19=rbp V20=r14 N835. IL_OFFSET IL offset: 0x155 N837. V20(r14) N839. V19(rbp) N841. rbx = SUB ; r14,rbp * N843. V21(rbx); rbx Var=Reg end of BB31: V01=rsi V02=rdi V13=r15 V19=rbp V20=r14 V21=rbx BB32 [15C..167) -> BB34 (cond), preds={BB28,BB31} succs={BB33,BB34} ===== Predecessor for variable locations: BB28 Var=Reg beg of BB32: V01=rsi V02=rdi V13=r15 V19=rbp V20=r14 V21=rbx N847. IL_OFFSET IL offset: 0x15c N849. rcx = V56 MEM N851. V68 MEM; rcx N853. rcx = V57 MEM N855. V69 MEM; rcx N857. IL_OFFSET IL offset: 0x15c N859. rcx = V58 MEM * N861. V70(rcx); rcx N863. rdx = V59 MEM * N865. V71(rdx); rdx N867. rax = LCL_VAR_ADDR V49 tmp19 rax ref V49._bits (offs=0x00) -> V68 tmp38 int V49._sign (offs=0x08) -> V69 tmp39 * N869. V84(rax); rax N871. r8 = LCL_VAR_ADDR V76 tmp46 r8 * N873. V83(r8); r8 N875. V83(r8) N877. V70(rcx*) N879. STOREIND ; r8,rcx* N881. V83(r8*) N883. STK = LEA(b+8) ; r8* N885. V71(rdx*) N887. STOREIND ; STK,rdx* N889. V84(rax*) N891. rcx = PUTARG_REG; rax* N893. rdx = LCL_VAR_ADDR V76 tmp46 rdx N895. rdx = PUTARG_REG; rdx N897. rax = CALL ; rcx,rdx N899. CNS_INT 0 N901. LT ; rax N903. JTRUE Var=Reg end of BB32: V01=rsi V02=rdi V13=r15 V19=rbp V20=r14 V21=rbx BB33 [167..16B) -> BB35 (always), preds={BB32} succs={BB35} ===== Predecessor for variable locations: BB32 Var=Reg beg of BB33: V01=rsi V02=rdi V13=r15 V19=rbp V20=r14 V21=rbx N907. IL_OFFSET IL offset: 0x167 N909. V19(rbp*) * N911. V34(rbp); rbp* Var=Reg end of BB33: V01=rsi V02=rdi V13=r15 V20=r14 V21=rbx V34=rbp BB34 [16B..16F), preds={BB32} succs={BB35} ===== Predecessor for variable locations: BB32 Var=Reg beg of BB34: V01=rsi V02=rdi V13=r15 V19=rbp V20=r14 V21=rbx N915. IL_OFFSET IL offset: 0x16b N917. V19(rbp*) N919. CNS_INT 1 N921. rbp = ADD ; rbp* * N923. V34(rbp); rbp Var=Reg end of BB34: V01=rsi V02=rdi V13=r15 V20=r14 V21=rbx V34=rbp BB35 [16F..1A4) -> BB40 (cond), preds={BB33,BB34} succs={BB36,BB40} ===== Predecessor for variable locations: BB33 Var=Reg beg of BB35: V01=rsi V02=rdi V13=r15 V20=r14 V21=rbx V34=rbp N927. V34(rbp*) * N929. V22(rbp); rbp* N931. IL_OFFSET IL offset: 0x171 N933. rcx = LCL_VAR_ADDR V15 loc12 rcx ref V15._bits (offs=0x00) -> V56 tmp26 int V15._sign (offs=0x08) -> V57 tmp27 N935. rcx = PUTARG_REG; rcx N937. V21(rbx*) N939. rdx = PUTARG_REG; rbx* N941. CALL ; rcx,rdx N943. IL_OFFSET IL offset: 0x17a N945. rcx = LCL_VAR_ADDR V35 tmp5 rcx ref V35._bits (offs=0x00) -> V62 tmp32 int V35._sign (offs=0x08) -> V63 tmp33 * N947. V88(rcx); rcx N949. rdx = LCL_VAR_ADDR V76 tmp46 rdx * N951. V85(rdx); rdx N953. V85(rdx) N955. r8 = V56 MEM N957. STOREIND ; rdx,r8 N959. V85(rdx*) N961. STK = LEA(b+8) ; rdx* N963. r8 = V57 MEM N965. STOREIND ; STK,r8 N967. rdx = LCL_VAR_ADDR V86 tmp56 rdx * N969. V87(rdx); rdx N971. V87(rdx) N973. r8 = V58 MEM N975. STOREIND ; rdx,r8 N977. V87(rdx*) N979. STK = LEA(b+8) ; rdx* N981. r8 = V59 MEM N983. STOREIND ; STK,r8 N985. V88(rcx*) N987. rcx = PUTARG_REG; rcx* N989. rdx = LCL_VAR_ADDR V76 tmp46 rdx N991. rdx = PUTARG_REG; rdx N993. r8 = LCL_VAR_ADDR V86 tmp56 r8 N995. r8 = PUTARG_REG; r8 N997. r9 = LCL_VAR_ADDR V23 loc20 r9 ref V23._bits (offs=0x00) -> V60 tmp30 int V23._sign (offs=0x08) -> V61 tmp31 N999. r9 = PUTARG_REG; r9 N1001. CALL ; rcx,rdx,r8,r9 N1003. rcx = LCL_VAR_ADDR V76 tmp46 rcx * N1005. V89(rcx); rcx N1007. V89(rcx) N1009. rax = V62 MEM N1011. STOREIND ; rcx,rax N1013. V89(rcx*) N1015. STK = LEA(b+8) ; rcx* N1017. rax = V63 MEM N1019. STOREIND ; STK,rax N1021. rcx = LCL_VAR_ADDR V76 tmp46 rcx N1023. rcx = PUTARG_REG; rcx N1025. rax = CALL ; rcx * N1027. V24(rbx); rax N1029. V61 MEM N1031. CNS_INT 0 N1033. r12 = EQ * N1035. V25(r12); r12 N1037. V24(rbx) N1039. rcx = PUTARG_REG; rbx N1041. rax = CALL ; rcx * N1043. V26(rax); rax N1045. IL_OFFSET IL offset: 0x19e N1047. V26(rax) N1049. V20(r14) N1051. LE ; rax,r14 N1053. JTRUE Var=Reg end of BB35: V01=rsi V02=rdi V13=r15 V20=r14 V24=rbx V25=r12 V26=rax V22=rbp BB36 [1A4..1AF) -> BB38 (cond), preds={BB35} succs={BB37,BB38} ===== Predecessor for variable locations: BB35 Var=Reg beg of BB36: V01=rsi V02=rdi V13=r15 V20=r14 V24=rbx V25=r12 V26=rax V22=rbp N1057. IL_OFFSET IL offset: 0x1a4 N1059. V26(rax*) N1061. V20(r14) N1063. rax = SUB ; rax*,r14 * N1065. V29(rax); rax N1067. IL_OFFSET IL offset: 0x1ab N1069. V25(r12*) N1071. CNS_INT 0 N1073. EQ ; r12* N1075. JTRUE Var=Reg end of BB36: V01=rsi V02=rdi V13=r15 V20=r14 V24=rbx V29=rax V22=rbp BB37 [1AF..1C3) -> BB39 (always), preds={BB36} succs={BB39} ===== Predecessor for variable locations: BB36 Var=Reg beg of BB37: V01=rsi V02=rdi V13=r15 V20=r14 V24=rbx V29=rax V22=rbp N1079. IL_OFFSET IL offset: 0x1af N1081. V24(rbx) N1083. V29(rax) N1085. rdx = CNS_INT 1 N1087. rdx = LSH ; rdx,rax N1089. CNS_INT -1 N1091. rdx = ADD ; rdx N1093. rcx = TEST_EQ ; rbx,rdx * N1095. V37(rcx); rcx Var=Reg end of BB37: V01=rsi V02=rdi V13=r15 V20=r14 V24=rbx V29=rax V37=rcx V22=rbp BB38 [1C3..1C4), preds={BB36} succs={BB39} ===== Predecessor for variable locations: BB36 Var=Reg beg of BB38: V01=rsi V02=rdi V13=r15 V20=r14 V24=rbx V29=rax V22=rbp N1099. IL_OFFSET IL offset: 0x1c3 N1101. rcx = CNS_INT 0 * N1103. V37(rcx); rcx Var=Reg end of BB38: V01=rsi V02=rdi V13=r15 V20=r14 V24=rbx V29=rax V37=rcx V22=rbp BB39 [1C4..1D0), preds={BB37,BB38} succs={BB40} ===== Predecessor for variable locations: BB37 Var=Reg beg of BB39: V01=rsi V02=rdi V13=r15 V20=r14 V24=rbx V29=rax V37=rcx V22=rbp N1107. V37(rcx*) N1109. r12 = CAST ; rcx* * N1111. V25(r12); r12 N1113. IL_OFFSET IL offset: 0x1c6 N1115. V24(rbx*) N1117. V29(rax*) N1119. rbx = RSZ ; rbx*,rax* * N1121. V24(rbx); rbx Var=Reg end of BB39: V01=rsi V02=rdi V13=r15 V20=r14 V24=rbx V25=r12 V22=rbp BB40 [1D0..1E7) -> BB42 (cond), preds={BB35,BB39} succs={BB41,BB42} ===== Predecessor for variable locations: BB35 Var=Reg beg of BB40: V01=rsi V02=rdi V13=r15 V20=r14 V24=rbx V25=r12 V22=rbp N1125. rcx = LCL_VAR_ADDR V76 tmp46 rcx * N1127. V90(rcx); rcx N1129. V90(rcx) N1131. rax = V54 MEM N1133. STOREIND ; rcx,rax N1135. V90(rcx*) N1137. STK = LEA(b+8) ; rcx* N1139. rax = V55 MEM N1141. STOREIND ; STK,rax N1143. rcx = LCL_VAR_ADDR V76 tmp46 rcx N1145. rcx = PUTARG_REG; rcx N1147. rax = CALL ; rcx N1149. V20(r14*) N1151. rax = LSH ; rax,r14* N1153. V24(rbx*) N1155. rdx = ADD ; rax,rbx* * N1157. V27(rdx); rdx N1159. IL_OFFSET IL offset: 0x1e2 N1161. V13(r15) N1163. CNS_INT 0 N1165. NE ; r15 N1167. JTRUE Var=Reg end of BB40: V01=rsi V02=rdi V13=r15 V25=r12 V22=rbp V27=rdx BB41 [1E7..1EE) -> BB43 (always), preds={BB40} succs={BB43} ===== Predecessor for variable locations: BB40 Var=Reg beg of BB41: V01=rsi V02=rdi V25=r12 V22=rbp V27=rdx N1171. IL_OFFSET IL offset: 0x1e7 N1173. V22(rbp*) N1175. r8 = NEG ; rbp* N1177. CNS_INT -1 N1179. r8 = ADD ; r8 * N1181. V36(r8); r8 Var=Reg end of BB41: V01=rsi V02=rdi V25=r12 V36=r8 V27=rdx BB42 [1EE..1F2), preds={BB40} succs={BB43} ===== Predecessor for variable locations: BB40 Var=Reg beg of BB42: V01=rsi V02=rdi V13=r15 V25=r12 V27=rdx N1185. IL_OFFSET IL offset: 0x1ee N1187. V13(r15*) N1189. CNS_INT -2 N1191. r8 = ADD ; r15* * N1193. V36(r8); r8 Var=Reg end of BB42: V01=rsi V02=rdi V25=r12 V36=r8 V27=rdx BB43 [1F2..202), preds={BB41,BB42} succs={BB44} ===== Predecessor for variable locations: BB41 Var=Reg beg of BB43: V01=rsi V02=rdi V25=r12 V36=r8 V27=rdx N1197. IL_OFFSET IL offset: 0x1f4 N1199. V02(rdi*) N1201. PUTARG_STK [+0x20]; rdi* N1203. V01(rsi*) N1205. rcx = PUTARG_REG; rsi* N1207. V27(rdx*) N1209. rdx = PUTARG_REG; rdx* N1211. V36(r8*) N1213. r8 = PUTARG_REG; r8* N1215. V25(r12*) N1217. r9 = PUTARG_REG; r12* N1219. rax = CALL ; rcx,rdx,r8,r9 * N1221. V51(rax); rax Var=Reg end of BB43: V51=rax BB44 [???..???) (return), preds={BB16,BB30,BB43} succs={} ===== Predecessor for variable locations: BB16 Var=Reg beg of BB44: V51=rax N1225. V51(rax*) N1227. RETURN ; rax* Var=Reg end of BB44: none *************** Finishing PHASE Linear scan register alloc *************** In genGenerateCode() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0056] 1 1 [???..???) i internal label target LIR BB02 [0000] 1 BB01 1 [000..00D)-> BB04 ( cond ) i label target idxlen LIR BB03 [0001] 1 BB02 0.50 [00D..017) (return) i hascall gcsafe LIR BB04 [0002] 1 BB02 0.50 [017..065)-> BB06 ( cond ) i label target hascall gcsafe LIR BB05 [0038] 1 BB04 0.50 [020..021)-> BB07 (always) i gcsafe LIR BB06 [0039] 1 BB04 0.50 [020..021) i label target gcsafe LIR BB07 [0040] 2 BB05,BB06 0.50 [000..000)-> BB09 ( cond ) i internal label target gcsafe idxlen LIR BB08 [0043] 1 BB07 0.50 [000..000)-> BB10 (always) i internal gcsafe LIR BB09 [0044] 1 BB07 0.50 [000..000) i internal label target gcsafe LIR BB10 [0045] 2 BB08,BB09 0.50 [???..???)-> BB14 ( cond ) i internal label target hascall gcsafe idxlen LIR BB11 [0003] 1 BB10 0.50 [065..070)-> BB13 ( cond ) i hascall gcsafe LIR BB12 [0004] 1 BB11 0.50 [070..07A) (return) i hascall gcsafe LIR BB13 [0005] 1 BB11 0.50 [07A..082) i label target hascall gcsafe LIR BB14 [0006] 2 BB10,BB13 0.50 [082..092)-> BB16 ( cond ) i label target hascall gcsafe LIR BB15 [0007] 1 BB14 0.50 [092..096)-> BB17 ( cond ) i gcsafe LIR BB16 [0008] 2 BB14,BB15 0.50 [096..0A7)-> BB44 (always) i label target hascall gcsafe LIR BB17 [0009] 1 BB15 0.50 [0A7..0B0)-> BB19 ( cond ) i label target gcsafe LIR BB18 [0010] 1 BB17 0.50 [0B0..0B4)-> BB20 (always) i gcsafe LIR BB19 [0011] 1 BB17 0.50 [0B4..0BE) i label target gcsafe LIR BB20 [0012] 2 BB18,BB19 0.50 [0BE..0C4)-> BB45 ( cond ) i label target gcsafe LIR BB21 [0013] 1 BB20 0.50 [0C4..0D9)-> BB23 ( cond ) i hascall gcsafe idxlen LIR BB22 [0014] 1 BB21 0.50 [0D9..0E3) (return) i hascall gcsafe LIR BB45 [0057] 1 BB20 0.25 [???..???)-> BB23 (always) internal target LIR BB23 [0015] 2 BB45,BB21 0.50 [0E3..117)-> BB25 ( cond ) i label target hascall gcsafe LIR BB24 [0016] 1 BB23 0.50 [117..11A)-> BB26 (always) i gcsafe LIR BB25 [0017] 1 BB23 0.50 [11A..11F) i label target gcsafe LIR BB26 [0018] 2 BB24,BB25 0.50 [11F..126)-> BB28 ( cond ) i label target gcsafe LIR BB27 [0019] 1 BB26 0.50 [126..12F) i hascall gcsafe LIR BB28 [0020] 2 BB26,BB27 0.50 [12F..13E)-> BB32 ( cond ) i label target gcsafe LIR BB29 [0021] 1 BB28 0.50 [13E..144)-> BB31 ( cond ) i gcsafe LIR BB30 [0022] 1 BB29 0.50 [144..155)-> BB44 (always) i hascall gcsafe LIR BB31 [0023] 1 BB29 0.50 [155..15C) i label target gcsafe LIR BB32 [0024] 2 BB28,BB31 0.50 [15C..167)-> BB34 ( cond ) i label target hascall gcsafe LIR BB33 [0025] 1 BB32 0.50 [167..16B)-> BB35 (always) i gcsafe LIR BB34 [0026] 1 BB32 0.50 [16B..16F) i label target gcsafe LIR BB35 [0027] 2 BB33,BB34 0.50 [16F..1A4)-> BB40 ( cond ) i label target hascall gcsafe LIR BB36 [0028] 1 BB35 0.50 [1A4..1AF)-> BB38 ( cond ) i gcsafe LIR BB37 [0029] 1 BB36 0.50 [1AF..1C3)-> BB39 (always) i gcsafe LIR BB38 [0030] 1 BB36 0.50 [1C3..1C4) i label target gcsafe LIR BB39 [0031] 2 BB37,BB38 0.50 [1C4..1D0) i label target gcsafe LIR BB40 [0032] 2 BB35,BB39 0.50 [1D0..1E7)-> BB42 ( cond ) i label target hascall gcsafe LIR BB41 [0033] 1 BB40 0.50 [1E7..1EE)-> BB43 (always) i gcsafe LIR BB42 [0034] 1 BB40 0.50 [1EE..1F2) i label target gcsafe LIR BB43 [0035] 2 BB41,BB42 0.50 [1F2..202) i label target hascall gcsafe LIR BB44 [0054] 3 BB16,BB30,BB43 0.50 [???..???) (return) keep internal target gcsafe LIR ----------------------------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Generate code *************** In fgDebugCheckBBlist Finalizing stack frame Recording Var Locations at start of BB01 V01(rsi) V00(rcx) V02(rdi) Modified regs: [rax rcx rdx rbx rbp rsi rdi r8-r15] Callee-saved registers pushed: 8 [rbx rbp rsi rdi r12-r15] *************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT) Assign V10 loc7, size=4, stkOffs=-0x4c Pad V11 loc8, size=16, stkOffs=-0x50, pad=4 Assign V11 loc8, size=16, stkOffs=-0x60 Assign V12 loc9, size=8, stkOffs=-0x68 Assign V14 loc11, size=4, stkOffs=-0x6c Pad V15 loc12, size=16, stkOffs=-0x70, pad=4 Assign V15 loc12, size=16, stkOffs=-0x80 Assign V16 loc13, size=16, stkOffs=-0x90 Assign V23 loc20, size=16, stkOffs=-0xa0 Assign V35 tmp5, size=16, stkOffs=-0xb0 Assign V38 tmp8, size=8, stkOffs=-0xb8 Assign V45 tmp15, size=8, stkOffs=-0xc0 Assign V48 tmp18, size=8, stkOffs=-0xc8 Assign V49 tmp19, size=16, stkOffs=-0xd8 Assign V73 tmp43, size=16, stkOffs=-0xe8 Assign V76 tmp46, size=16, stkOffs=-0xf8 Assign V86 tmp56, size=16, stkOffs=-0x108 Assign V30 OutArgs, size=40, stkOffs=-0x130 --- delta bump 8 for RA --- delta bump 296 for RSP frame --- virtual stack offset to actual stack offset delta is 304 -- V00 was 0, now 304 -- V01 was 8, now 312 -- V02 was 16, now 320 -- V10 was -76, now 228 -- V11 was -96, now 208 -- V12 was -104, now 200 -- V14 was -108, now 196 -- V15 was -128, now 176 -- V16 was -144, now 160 -- V23 was -160, now 144 -- V30 was -304, now 0 -- V35 was -176, now 128 -- V38 was -184, now 120 -- V45 was -192, now 112 -- V48 was -200, now 104 -- V49 was -216, now 88 -- V73 was -232, now 72 -- V76 was -248, now 56 -- V86 was -264, now 40 ; Final local variable assignments ; ; V00 arg0 [V00,T01] ( 4, 8 ) byref -> rcx ld-addr-op ; V01 arg1 [V01,T00] ( 15, 8.50) ref -> rsi class-hnd ; V02 arg2 [V02,T02] ( 8, 5 ) byref -> rdi ; V03 loc0 [V03,T34] ( 3, 1.50) int -> r14 ;* V04 loc1 [V04 ] ( 0, 0 ) int -> zero-ref ; V05 loc2 [V05,T24] ( 4, 2 ) int -> r15 ;* V06 loc3 [V06 ] ( 0, 0 ) int -> zero-ref ;* V07 loc4 [V07 ] ( 0, 0 ) int -> zero-ref ; V08 loc5 [V08,T25] ( 4, 2 ) int -> r12 ; V09 loc6 [V09,T35] ( 3, 1.50) int -> r13 ; V10 loc7 [V10,T23] ( 5, 2.50) int -> [rsp+0xE4] ; V11 loc8 [V11 ] ( 6, 3 ) struct (16) [rsp+0xD0] do-not-enreg[XS] must-init addr-exposed ld-addr-op ; V12 loc9 [V12 ] ( 3, 1.50) ref -> [rsp+0xC8] do-not-enreg[X] must-init addr-exposed ld-addr-op class-hnd ; V13 loc10 [V13,T03] ( 9, 4.50) int -> r15 ; V14 loc11 [V14,T36] ( 3, 1.50) int -> [rsp+0xC4] ; V15 loc12 [V15 ] ( 9, 4.50) struct (16) [rsp+0xB0] do-not-enreg[XS] must-init addr-exposed ld-addr-op ; V16 loc13 [V16 ] ( 9, 4.50) struct (16) [rsp+0xA0] do-not-enreg[XS] must-init addr-exposed ld-addr-op ; V17 loc14 [V17,T37] ( 3, 1.50) int -> rbx ; V18 loc15 [V18,T38] ( 3, 1.50) int -> rax ; V19 loc16 [V19,T08] ( 7, 3.50) int -> rbp ; V20 loc17 [V20,T09] ( 7, 3.50) int -> r14 ; V21 loc18 [V21,T39] ( 3, 1.50) int -> rbx ; V22 loc19 [V22,T51] ( 2, 1 ) int -> rbp ; V23 loc20 [V23 ] ( 2, 1 ) struct (16) [rsp+0x90] do-not-enreg[XS] must-init addr-exposed ld-addr-op ; V24 loc21 [V24,T10] ( 6, 3 ) long -> rbx ; V25 loc22 [V25,T26] ( 4, 2 ) bool -> r12 ; V26 loc23 [V26,T40] ( 3, 1.50) int -> rax ; V27 loc24 [V27,T52] ( 2, 1 ) long -> rdx ;* V28 loc25 [V28 ] ( 0, 0 ) int -> zero-ref ; V29 loc26 [V29,T41] ( 3, 1.50) int -> rax ; V30 OutArgs [V30 ] ( 1, 1 ) lclBlk (40) [rsp+0x00] "OutgoingArgSpace" ; V31 tmp1 [V31,T06] ( 4, 4 ) int -> r15 "dup spill" ; V32 tmp2 [V32,T42] ( 3, 1.50) int -> rdx ; V33 tmp3 [V33,T43] ( 3, 1.50) int -> rbp ; V34 tmp4 [V34,T44] ( 3, 1.50) int -> rbp ; V35 tmp5 [V35 ] ( 3, 3 ) struct (16) [rsp+0x80] do-not-enreg[XS] must-init addr-exposed "struct address for call/obj" ; V36 tmp6 [V36,T45] ( 3, 1.50) int -> r8 ; V37 tmp7 [V37,T46] ( 3, 1.50) int -> rcx ; V38 tmp8 [V38,T29] ( 2, 2 ) long -> [rsp+0x78] "impAppendStmt" ; V39 tmp9 [V39,T47] ( 3, 1.50) int -> r15 "Inline return value spill temp" ; V40 tmp10 [V40,T30] ( 2, 2 ) int -> rcx "Inlining Arg" ; V41 tmp11 [V41,T27] ( 4, 2 ) int -> r12 "Inline return value spill temp" ; V42 tmp12 [V42,T22] ( 3, 3 ) int -> r12 "Inlining Arg" ; V43 tmp13 [V43,T53] ( 2, 1 ) int -> rbx "Inline return value spill temp" ;* V44 tmp14 [V44 ] ( 0, 0 ) struct (16) zero-ref "Inlining Arg" ; V45 tmp15 [V45 ] ( 2, 1 ) ref -> [rsp+0x70] do-not-enreg[X] must-init addr-exposed ld-addr-op class-hnd "Inline ldloca(s) first use temp" ; V46 tmp16 [V46,T54] ( 2, 1 ) int -> rax "Inline return value spill temp" ;* V47 tmp17 [V47 ] ( 0, 0 ) struct (16) zero-ref "Inlining Arg" ; V48 tmp18 [V48 ] ( 2, 1 ) ref -> [rsp+0x68] do-not-enreg[X] must-init addr-exposed ld-addr-op class-hnd "Inline ldloca(s) first use temp" ; V49 tmp19 [V49 ] ( 3, 3 ) struct (16) [rsp+0x58] do-not-enreg[XS] must-init addr-exposed ld-addr-op "Inlining Arg" ;* V50 tmp20 [V50 ] ( 0, 0 ) struct (16) zero-ref "Inlining Arg" ; V51 tmp21 [V51,T07] ( 4, 4 ) int -> rax "Single return block return value" ; V52 tmp22 [V52,T04] ( 7, 4.50) ref -> rbx V72.Mantissa(offs=0x00) P-INDEP "field V00.Mantissa (fldOffset=0x0)" ; V53 tmp23 [V53,T05] ( 7, 4 ) int -> rbp V72.Exponent(offs=0x08) P-INDEP "field V00.Exponent (fldOffset=0x8)" ; V54 tmp24 [V54 ] ( 4, 2 ) ref -> [rsp+0xD0] do-not-enreg[X] addr-exposed V11._bits(offs=0x00) P-DEP "field V11._bits (fldOffset=0x0)" ; V55 tmp25 [V55 ] ( 4, 2 ) int -> [rsp+0xD8] do-not-enreg[X] addr-exposed V11._sign(offs=0x08) P-DEP "field V11._sign (fldOffset=0x8)" ; V56 tmp26 [V56 ] ( 6, 3 ) ref -> [rsp+0xB0] do-not-enreg[X] addr-exposed V15._bits(offs=0x00) P-DEP "field V15._bits (fldOffset=0x0)" ; V57 tmp27 [V57 ] ( 6, 3 ) int -> [rsp+0xB8] do-not-enreg[X] addr-exposed V15._sign(offs=0x08) P-DEP "field V15._sign (fldOffset=0x8)" ; V58 tmp28 [V58 ] ( 5, 2.50) ref -> [rsp+0xA0] do-not-enreg[X] addr-exposed V16._bits(offs=0x00) P-DEP "field V16._bits (fldOffset=0x0)" ; V59 tmp29 [V59 ] ( 5, 2.50) int -> [rsp+0xA8] do-not-enreg[X] addr-exposed V16._sign(offs=0x08) P-DEP "field V16._sign (fldOffset=0x8)" ; V60 tmp30 [V60 ] ( 1, 0.50) ref -> [rsp+0x90] do-not-enreg[X] addr-exposed V23._bits(offs=0x00) P-DEP "field V23._bits (fldOffset=0x0)" ; V61 tmp31 [V61 ] ( 2, 1 ) int -> [rsp+0x98] do-not-enreg[X] addr-exposed V23._sign(offs=0x08) P-DEP "field V23._sign (fldOffset=0x8)" ; V62 tmp32 [V62 ] ( 2, 1.50) ref -> [rsp+0x80] do-not-enreg[X] addr-exposed V35._bits(offs=0x00) P-DEP "field V35._bits (fldOffset=0x0)" ; V63 tmp33 [V63 ] ( 2, 1.50) int -> [rsp+0x88] do-not-enreg[X] addr-exposed V35._sign(offs=0x08) P-DEP "field V35._sign (fldOffset=0x8)" ; V64 tmp34 [V64,T48] ( 2, 1 ) ref -> rcx V44._bits(offs=0x00) P-INDEP "field V44._bits (fldOffset=0x0)" ; V65 tmp35 [V65,T55] ( 2, 1 ) int -> rdx V44._sign(offs=0x08) P-INDEP "field V44._sign (fldOffset=0x8)" ; V66 tmp36 [V66,T49] ( 2, 1 ) ref -> rcx V47._bits(offs=0x00) P-INDEP "field V47._bits (fldOffset=0x0)" ; V67 tmp37 [V67,T56] ( 2, 1 ) int -> rdx V47._sign(offs=0x08) P-INDEP "field V47._sign (fldOffset=0x8)" ; V68 tmp38 [V68 ] ( 2, 1.50) ref -> [rsp+0x58] do-not-enreg[X] addr-exposed V49._bits(offs=0x00) P-DEP "field V49._bits (fldOffset=0x0)" ; V69 tmp39 [V69 ] ( 2, 1.50) int -> [rsp+0x60] do-not-enreg[X] addr-exposed V49._sign(offs=0x08) P-DEP "field V49._sign (fldOffset=0x8)" ; V70 tmp40 [V70,T50] ( 2, 1 ) ref -> rcx V50._bits(offs=0x00) P-INDEP "field V50._bits (fldOffset=0x0)" ; V71 tmp41 [V71,T57] ( 2, 1 ) int -> rdx V50._sign(offs=0x08) P-INDEP "field V50._sign (fldOffset=0x8)" ;* V72 tmp42 [V72 ] ( 0, 0 ) struct (16) zero-ref "Promoted implicit byref" ; V73 tmp43 [V73 ] ( 4, 4 ) struct (16) [rsp+0x48] do-not-enreg[XSB] must-init addr-exposed "by-value struct argument" ; V74 tmp44 [V74,T11] ( 3, 3 ) byref -> rdx stack-byref "BlockOp address local" ; V75 tmp45 [V75,T31] ( 2, 2 ) long -> rcx "argument with side effect" ; V76 tmp46 [V76 ] ( 14, 14 ) struct (16) [rsp+0x38] do-not-enreg[XSB] must-init addr-exposed "by-value struct argument" ; V77 tmp47 [V77,T12] ( 3, 3 ) byref -> rcx stack-byref "BlockOp address local" ; V78 tmp48 [V78,T13] ( 3, 3 ) byref -> rdx stack-byref "BlockOp address local" ; V79 tmp49 [V79,T32] ( 2, 2 ) long -> rcx "argument with side effect" ; V80 tmp50 [V80,T14] ( 3, 3 ) byref -> rcx "BlockOp address local" ; V81 tmp51 [V81,T15] ( 3, 3 ) byref -> rax stack-byref "BlockOp address local" ; V82 tmp52 [V82,T16] ( 3, 3 ) byref -> rax stack-byref "BlockOp address local" ; V83 tmp53 [V83,T17] ( 3, 3 ) byref -> r8 stack-byref "BlockOp address local" ; V84 tmp54 [V84,T28] ( 2, 2 ) byref -> rax "argument with side effect" ; V85 tmp55 [V85,T18] ( 3, 3 ) byref -> rdx stack-byref "BlockOp address local" ; V86 tmp56 [V86 ] ( 2, 2 ) struct (16) [rsp+0x28] do-not-enreg[XSB] must-init addr-exposed "by-value struct argument" ; V87 tmp57 [V87,T19] ( 3, 3 ) byref -> rdx stack-byref "BlockOp address local" ; V88 tmp58 [V88,T33] ( 2, 2 ) long -> rcx "argument with side effect" ; V89 tmp59 [V89,T20] ( 3, 3 ) byref -> rcx stack-byref "BlockOp address local" ; V90 tmp60 [V90,T21] ( 3, 3 ) byref -> rcx stack-byref "BlockOp address local" ; ; Lcl frame size = 232 Setting stack level from -572662307 to 0 =============== Generating BB01 [???..???), preds={} succs={BB02} flags=0x00000000.40030060: i internal label target LIR BB01 IN (3)={V01 V00 V02 } + ByrefExposed + GcHeap OUT(4)={V01 V02 V52 V53} + ByrefExposed + GcHeap Recording Var Locations at start of BB01 V01(rsi) V00(rcx) V02(rdi) Change life 0000000000000000 {} -> 0000000000000007 {V00 V01 V02} V01 in reg rsi is becoming live [------] Live regs: 00000000 {} => 00000040 {rsi} V00 in reg rcx is becoming live [------] Live regs: 00000040 {rsi} => 00000042 {rcx rsi} V02 in reg rdi is becoming live [------] Live regs: 00000042 {rcx rsi} => 000000C2 {rcx rsi rdi} Live regs: (unchanged) 000000C2 {rcx rsi rdi} GC regs: (unchanged) 00000040 {rsi} Byref regs: (unchanged) 00000082 {rcx rdi} L_M6661_BB01: Label: IG02, GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000082 {rcx rdi} Scope info: begin block BB01, IL range [???..???) Scope info: ignoring block beginning Generating: N003 ( 1, 1) [000531] ------------ t531 = LCL_VAR byref V00 arg0 u:1 rcx Zero Fseq[Mantissa] REG rcx $80 /--* t531 byref Generating: N005 ( 3, 2) [000532] n----------- t532 = * IND ref REG rbx IN0001: mov rbx, gword ptr [rcx] GC regs: 00000040 {rsi} => 00000048 {rbx rsi} /--* t532 ref Generating: N007 ( 3, 3) [000533] DA---------- * STORE_LCL_VAR ref V52 tmp22 d:2 rbx REG rbx GC regs: 00000048 {rbx rsi} => 00000040 {rsi} V52 in reg rbx is becoming live [000533] Live regs: 000000C2 {rcx rsi rdi} => 000000CA {rcx rbx rsi rdi} Live vars: {V00 V01 V02} => {V00 V01 V02 V52} GC regs: 00000040 {rsi} => 00000048 {rbx rsi} Generating: N009 ( 1, 1) [000535] ------------ t535 = LCL_VAR byref V00 arg0 u:1 rcx (last use) REG rcx $80 /--* t535 byref Generating: N011 ( 2, 2) [000537] -c---------- t537 = * LEA(b+8) byref REG NA /--* t537 byref Generating: N013 ( 4, 4) [000538] n----------- t538 = * IND int REG rbp V00 in reg rcx is becoming dead [000535] Live regs: 000000CA {rcx rbx rsi rdi} => 000000C8 {rbx rsi rdi} Live vars: {V00 V01 V02 V52} => {V01 V02 V52} Byref regs: 00000082 {rcx rdi} => 00000080 {rdi} IN0002: mov ebp, dword ptr [rcx+8] /--* t538 int Generating: N015 ( 4, 4) [000539] DA---------- * STORE_LCL_VAR int V53 tmp23 d:2 rbp REG rbp V53 in reg rbp is becoming live [000539] Live regs: 000000C8 {rbx rsi rdi} => 000000E8 {rbx rbp rsi rdi} Live vars: {V01 V02 V52} => {V01 V02 V52 V53} Scope info: end block BB01, IL range [???..???) Scope info: ignoring block end =============== Generating BB02 [000..00D) -> BB04 (cond), preds={BB01} succs={BB03,BB04} flags=0x00000000.40230020: i label target idxlen LIR BB02 IN (4)={V01 V02 V52 V53} + ByrefExposed + GcHeap OUT(4)={V01 V02 V52 V53} + ByrefExposed + GcHeap Recording Var Locations at start of BB02 V01(rsi) V02(rdi) V52(rbx) V53(rbp) Liveness not changing: 0000000000000035 {V01 V02 V52 V53} Live regs: 00000000 {} => 000000E8 {rbx rbp rsi rdi} GC regs: 00000000 {} => 00000048 {rbx rsi} Byref regs: 00000000 {} => 00000080 {rdi} L_M6661_BB02: G_M6661_IG02: ; offs=000000H, funclet=00, bbWeight=1 Label: IG03, GCvars=0000000000000000 {}, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi} Scope info: begin block BB02, IL range [000..00D) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) Added IP mapping: 0x0000 STACK_EMPTY (G_M6661_IG03,ins#0,ofs#0) label Generating: N019 (???,???) [000910] ------------ IL_OFFSET void IL offset: 0x0 REG NA Generating: N021 ( 1, 1) [000002] ------------ t2 = LCL_VAR ref V52 tmp22 u:2 rbx REG rbx /--* t2 ref Generating: N023 (???,???) [000988] -c---------- t988 = * LEA(b+8) ref REG NA /--* t988 ref Generating: N025 ( 3, 3) [000003] -c-XG------- t3 = * IND int REG NA Generating: N027 ( 1, 1) [000004] -c---------- t4 = CNS_INT int 0 REG NA $40 /--* t3 int +--* t4 int Generating: N029 ( 5, 5) [000005] J--XG--N---- * NE void REG NA IN0003: cmp dword ptr [rbx+8], 0 Generating: N031 ( 7, 7) [000006] ---XG------- * JTRUE void REG NA IN0004: jne L_M6661_BB04 Scope info: end block BB02, IL range [000..00D) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) =============== Generating BB03 [00D..017) (return), preds={BB02} succs={} flags=0x00000004.40080020: i hascall gcsafe LIR BB03 IN (2)={V01 V02} + ByrefExposed + GcHeap OUT(0)={ } Recording Var Locations at start of BB03 V01(rsi) V02(rdi) Change life 0000000000000035 {V01 V02 V52 V53} -> 0000000000000005 {V01 V02} V52 in reg rbx is becoming dead [------] Live regs: (unchanged) 00000000 {} V53 in reg rbp is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: 00000000 {} => 000000C0 {rsi rdi} GC regs: 00000000 {} => 00000040 {rsi} Byref regs: 00000000 {} => 00000080 {rdi} L_M6661_BB03: G_M6661_IG03: ; offs=000006H, funclet=00, bbWeight=1 Label: IG04, GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi} Scope info: begin block BB03, IL range [00D..017) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) Added IP mapping: 0x000D STACK_EMPTY (G_M6661_IG04,ins#0,ofs#0) label Generating: N035 (???,???) [000911] ------------ IL_OFFSET void IL offset: 0xd REG NA Generating: N037 ( 1, 1) [000400] ------------ t400 = LCL_VAR ref V01 arg1 u:1 rsi REG rsi $c0 /--* t400 ref Generating: N039 (???,???) [000995] ------------ t995 = * PUTARG_REG ref REG rcx IN0005: mov rcx, rsi GC regs: 00000040 {rsi} => 00000042 {rcx rsi} Generating: N041 ( 1, 1) [000996] ------------ t996 = LCL_VAR ref V01 arg1 rsi (last use) REG rsi /--* t996 ref Generating: N043 ( 2, 2) [000997] -c---------- t997 = * LEA(b+0) byref REG NA /--* t997 byref Generating: N045 ( 5, 4) [000998] ------------ t998 = * IND long REG rax V01 in reg rsi is becoming dead [000996] Live regs: 000000C0 {rsi rdi} => 00000080 {rdi} Live vars: {V01 V02} => {V02} GC regs: 00000042 {rcx rsi} => 00000002 {rcx} IN0006: mov rax, qword ptr [rsi] /--* t998 long Generating: N047 ( 6, 5) [000999] -c---------- t999 = * LEA(b+80) long REG NA /--* t999 long Generating: N049 ( 9, 7) [001000] ------------ t1000 = * IND long REG rax IN0007: mov rax, qword ptr [rax+80] /--* t1000 long Generating: N051 ( 10, 8) [001001] -c---------- t1001 = * LEA(b+0) long REG NA /--* t1001 long Generating: N053 ( 13, 10) [001002] -c---------- t1002 = * IND long REG NA /--* t995 ref this in rcx +--* t1002 long control expr Generating: N055 ( 21, 10) [000401] --CXG------- t401 = * CALLV ind long FloatingPointType.get_Zero REG rax $459 GC regs: 00000002 {rcx} => 00000000 {} Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000080 {rdi} IN0008: call qword ptr [rax]FloatingPointType:get_Zero():long:this Generating: N057 ( 1, 1) [000399] ------------ t399 = LCL_VAR byref V02 arg2 u:1 rdi (last use) REG rdi $81 /--* t399 byref +--* t401 long Generating: N059 (???,???) [000912] -ACXG------- * STOREIND long REG NA V02 in reg rdi is becoming dead [000399] Live regs: 00000080 {rdi} => 00000000 {} Live vars: {V02} => {} Byref regs: 00000080 {rdi} => 00000000 {} IN0009: mov qword ptr [rdi], rax Generating: N061 ( 1, 1) [000404] ------------ t404 = CNS_INT int 1 REG rax $41 IN000a: mov eax, 1 /--* t404 int Generating: N063 ( 2, 2) [000520] ------------ * RETURN int REG NA $5cb Scope info: end block BB03, IL range [00D..017) Scope info: open scopes = Added IP mapping: EPILOG STACK_EMPTY (G_M6661_IG04,ins#6,ofs#20) label Reserving epilog IG for block BB03 G_M6661_IG04: ; offs=000010H, funclet=00, bbWeight=0.50 *************** After placeholder IG creation G_M6661_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG G_M6661_IG02: ; offs=000000H, size=0006H, gcrefRegs=00000040 {rsi}, byrefRegs=00000082 {rcx rdi}, byref G_M6661_IG03: ; offs=000006H, size=000AH, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG04: ; offs=000010H, size=0014H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG05: ; epilog placeholder, next placeholder=, BB03 [0001], epilog, extend <-- First placeholder <-- Last placeholder ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000048 {rbx rsi}, PrevByrefRegs=00000080 {rdi} ; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000040 {rsi}, InitByrefRegs=00000080 {rdi} G_M6661_IG06: ; offs=000124H, size=0000H, gcrefRegs=00000000 {} <-- Current IG =============== Generating BB04 [017..065) -> BB06 (cond), preds={BB02} succs={BB05,BB06} flags=0x00000004.400b0020: i label target hascall gcsafe LIR BB04 IN (4)={V01 V02 V52 V53 } + ByrefExposed + GcHeap OUT(5)={V01 V02 V52 V53 V03} + ByrefExposed + GcHeap Recording Var Locations at start of BB04 V01(rsi) V02(rdi) V52(rbx) V53(rbp) Change life 0000000000000000 {} -> 0000000000000035 {V01 V02 V52 V53} V01 in reg rsi is becoming live [------] Live regs: 00000000 {} => 00000040 {rsi} V02 in reg rdi is becoming live [------] Live regs: 00000040 {rsi} => 000000C0 {rsi rdi} V52 in reg rbx is becoming live [------] Live regs: 000000C0 {rsi rdi} => 000000C8 {rbx rsi rdi} V53 in reg rbp is becoming live [------] Live regs: 000000C8 {rbx rsi rdi} => 000000E8 {rbx rbp rsi rdi} Live regs: (unchanged) 000000E8 {rbx rbp rsi rdi} GC regs: (unchanged) 00000048 {rbx rsi} Byref regs: (unchanged) 00000080 {rdi} L_M6661_BB04: Label: IG06, GCvars=0000000000000000 {}, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi} Scope info: begin block BB04, IL range [017..065) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) Generating: N067 ( 1, 1) [000007] ------------ t7 = LCL_VAR ref V01 arg1 u:1 rsi REG rsi $c0 /--* t7 ref Generating: N069 (???,???) [001003] ------------ t1003 = * PUTARG_REG ref REG rcx IN000b: mov rcx, rsi GC regs: 00000048 {rbx rsi} => 0000004A {rcx rbx rsi} Generating: N071 ( 1, 1) [001004] ------------ t1004 = LCL_VAR ref V01 arg1 rsi REG rsi /--* t1004 ref Generating: N073 ( 2, 2) [001005] -c---------- t1005 = * LEA(b+0) byref REG NA /--* t1005 byref Generating: N075 ( 5, 4) [001006] ------------ t1006 = * IND long REG rax IN000c: mov rax, qword ptr [rsi] /--* t1006 long Generating: N077 ( 6, 5) [001007] -c---------- t1007 = * LEA(b+72) long REG NA /--* t1007 long Generating: N079 ( 9, 7) [001008] ------------ t1008 = * IND long REG rax IN000d: mov rax, qword ptr [rax+72] /--* t1008 long Generating: N081 ( 10, 8) [001009] -c---------- t1009 = * LEA(b+32) long REG NA /--* t1009 long Generating: N083 ( 13, 10) [001010] -c---------- t1010 = * IND long REG NA /--* t1003 ref this in rcx +--* t1010 long control expr Generating: N085 ( 21, 10) [000406] --CXG------- t406 = * CALLV ind int FloatingPointType.get_DenormalMantissaBits REG rax $282 GC regs: 0000004A {rcx rbx rsi} => 00000048 {rbx rsi} Call: GCvars=0000000000000000 {}, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi} IN000e: call qword ptr [rax+32]FloatingPointType:get_DenormalMantissaBits():ushort:this Generating: N087 ( 1, 1) [000407] -c---------- t407 = CNS_INT int 1 REG NA $41 /--* t406 int +--* t407 int Generating: N089 ( 23, 12) [000408] ---XG------- t408 = * ADD int REG rax $346 IN000f: inc eax /--* t408 int Generating: N091 ( 24, 14) [000409] ---XG------- t409 = * CAST int <- ushort <- int REG r14 $347 IN0010: movzx r14, ax Generating: N093 ( 1, 1) [000010] -c---------- t10 = CNS_INT int 1 REG NA $41 /--* t409 int +--* t10 int Generating: N095 ( 26, 16) [000011] ---XG------- t11 = * ADD int REG r14 $348 IN0011: inc r14d /--* t11 int Generating: N097 ( 30, 19) [000013] DA-XG------- * STORE_LCL_VAR int V03 loc0 d:2 r14 REG r14 V03 in reg r14 is becoming live [000013] Live regs: 000000E8 {rbx rbp rsi rdi} => 000040E8 {rbx rbp rsi rdi r14} Live vars: {V01 V02 V52 V53} => {V01 V02 V03 V52 V53} Added IP mapping: 0x0020 STACK_EMPTY (G_M6661_IG06,ins#7,ofs#22) label Generating: N099 (???,???) [000913] ------------ IL_OFFSET void IL offset: 0x20 REG NA Generating: N101 ( 1, 1) [000017] ------------ t17 = LCL_VAR int V53 tmp23 u:2 rbp REG rbp /--* t17 int Generating: N103 ( 5, 4) [000424] DA--G------- * STORE_LCL_VAR int V40 tmp10 d:2 rcx REG rcx IN0012: mov ecx, ebp V40 in reg rcx is becoming live [000424] Live regs: 000040E8 {rbx rbp rsi rdi r14} => 000040EA {rcx rbx rbp rsi rdi r14} Live vars: {V01 V02 V03 V52 V53} => {V01 V02 V03 V40 V52 V53} genIPmappingAdd: ignoring duplicate IL offset 0x20 Generating: N105 (???,???) [000914] ------------ IL_OFFSET void IL offset: 0x20 REG NA Generating: N107 ( 1, 1) [000412] ------------ t412 = LCL_VAR int V40 tmp10 u:2 rcx (last use) REG rcx Generating: N109 ( 1, 1) [000411] -c---------- t411 = CNS_INT int 0 REG NA $40 /--* t412 int +--* t411 int Generating: N111 ( 3, 3) [000413] J------N---- * LE void REG NA V40 in reg rcx is becoming dead [000412] Live regs: 000040EA {rcx rbx rbp rsi rdi r14} => 000040E8 {rbx rbp rsi rdi r14} Live vars: {V01 V02 V03 V40 V52 V53} => {V01 V02 V03 V52 V53} IN0013: test ecx, ecx Generating: N113 ( 5, 5) [000414] ------------ * JTRUE void REG NA IN0014: jle L_M6661_BB06 Scope info: end block BB04, IL range [017..065) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) =============== Generating BB05 [020..021) -> BB07 (always), preds={BB04} succs={BB07} flags=0x00000000.40080020: i gcsafe LIR BB05 IN (5)={V01 V02 V52 V53 V03 } + ByrefExposed + GcHeap OUT(6)={V01 V02 V52 V53 V03 V39} + ByrefExposed + GcHeap Recording Var Locations at start of BB05 V01(rsi) V02(rdi) V52(rbx) V53(rbp) V03(r14) Liveness not changing: 0000000400000035 {V01 V02 V03 V52 V53} Live regs: 00000000 {} => 000040E8 {rbx rbp rsi rdi r14} GC regs: 00000000 {} => 00000048 {rbx rsi} Byref regs: 00000000 {} => 00000080 {rdi} L_M6661_BB05: Scope info: begin block BB05, IL range [020..021) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 3 (V03 loc0) [000..202) genIPmappingAdd: ignoring duplicate IL offset 0x20 Generating: N117 (???,???) [000915] ------------ IL_OFFSET void IL offset: 0x20 REG NA Generating: N119 ( 3, 2) [000419] ------------ t419 = LCL_VAR int V53 tmp23 u:2 rbp REG rbp /--* t419 int Generating: N121 ( 7, 5) [000421] DA---------- * STORE_LCL_VAR int V39 tmp9 d:4 r15 REG r15 IN0015: mov r15d, ebp V39 in reg r15 is becoming live [000421] Live regs: 000040E8 {rbx rbp rsi rdi r14} => 0000C0E8 {rbx rbp rsi rdi r14 r15} Live vars: {V01 V02 V03 V52 V53} => {V01 V02 V03 V39 V52 V53} Scope info: end block BB05, IL range [020..021) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 3 (V03 loc0) [000..202) IN0016: jmp L_M6661_BB07 =============== Generating BB06 [020..021), preds={BB04} succs={BB07} flags=0x00000000.400b0020: i label target gcsafe LIR BB06 IN (5)={V01 V02 V52 V53 V03 } + ByrefExposed + GcHeap OUT(6)={V01 V02 V52 V53 V03 V39} + ByrefExposed + GcHeap Recording Var Locations at start of BB06 V01(rsi) V02(rdi) V52(rbx) V53(rbp) V03(r14) Change life 0000800400000035 {V01 V02 V03 V39 V52 V53} -> 0000000400000035 {V01 V02 V03 V52 V53} V39 in reg r15 is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: 00000000 {} => 000040E8 {rbx rbp rsi rdi r14} GC regs: 00000000 {} => 00000048 {rbx rsi} Byref regs: 00000000 {} => 00000080 {rdi} L_M6661_BB06: G_M6661_IG06: ; offs=000124H, funclet=00, bbWeight=0.50 Label: IG07, GCvars=0000000000000000 {}, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi} Scope info: begin block BB06, IL range [020..021) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 3 (V03 loc0) [000..202) genIPmappingAdd: ignoring duplicate IL offset 0x20 Generating: N125 (???,???) [000916] ------------ IL_OFFSET void IL offset: 0x20 REG NA Generating: N127 ( 1, 1) [000415] ------------ t415 = CNS_INT int 0 REG r15 $40 IN0017: xor r15d, r15d /--* t415 int Generating: N129 ( 5, 4) [000417] DA---------- * STORE_LCL_VAR int V39 tmp9 d:3 r15 REG r15 V39 in reg r15 is becoming live [000417] Live regs: 000040E8 {rbx rbp rsi rdi r14} => 0000C0E8 {rbx rbp rsi rdi r14 r15} Live vars: {V01 V02 V03 V52 V53} => {V01 V02 V03 V39 V52 V53} Scope info: end block BB06, IL range [020..021) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 3 (V03 loc0) [000..202) =============== Generating BB07 [000..000) -> BB09 (cond), preds={BB05,BB06} succs={BB08,BB09} flags=0x00000000.402b0060: i internal label target gcsafe idxlen LIR BB07 IN (6)={V01 V02 V52 V53 V03 V39} + ByrefExposed + GcHeap OUT(7)={V01 V02 V52 V53 V31 V42 V03 } + ByrefExposed + GcHeap Recording Var Locations at start of BB07 V01(rsi) V02(rdi) V52(rbx) V53(rbp) V03(r14) V39(r15) Liveness not changing: 0000800400000035 {V01 V02 V03 V39 V52 V53} Live regs: 00000000 {} => 0000C0E8 {rbx rbp rsi rdi r14 r15} GC regs: 00000000 {} => 00000048 {rbx rsi} Byref regs: 00000000 {} => 00000080 {rdi} L_M6661_BB07: G_M6661_IG07: ; offs=00014CH, funclet=00, bbWeight=0.50 Label: IG08, GCvars=0000000000000000 {}, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi} Scope info: begin block BB07, IL range [000..000) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 3 (V03 loc0) [000..202) Added IP mapping: NO_MAP STACK_EMPTY (G_M6661_IG08,ins#0,ofs#0) label Generating: N133 ( 3, 2) [000422] ------------ t422 = LCL_VAR int V39 tmp9 u:2 r15 (last use) REG r15 $241 /--* t422 int Generating: N135 ( 3, 3) [000021] DA---------- * STORE_LCL_VAR int V31 tmp1 d:2 r15 REG r15 V39 in reg r15 is becoming dead [000422] Live regs: 0000C0E8 {rbx rbp rsi rdi r14 r15} => 000040E8 {rbx rbp rsi rdi r14} Live vars: {V01 V02 V03 V39 V52 V53} => {V01 V02 V03 V52 V53} V31 in reg r15 is becoming live [000021] Live regs: 000040E8 {rbx rbp rsi rdi r14} => 0000C0E8 {rbx rbp rsi rdi r14 r15} Live vars: {V01 V02 V03 V52 V53} => {V01 V02 V03 V31 V52 V53} Generating: N137 ( 1, 1) [000428] ------------ t428 = LCL_VAR ref V52 tmp22 u:2 rbx REG rbx /--* t428 ref Generating: N139 (???,???) [000990] -c---------- t990 = * LEA(b+8) ref REG NA /--* t990 ref Generating: N141 ( 3, 3) [000429] ---XG------- t429 = * IND int REG r12 IN0018: mov r12d, dword ptr [rbx+8] /--* t429 int Generating: N143 ( 3, 3) [000443] DA-XG------- * STORE_LCL_VAR int V42 tmp12 d:2 r12 REG r12 V42 in reg r12 is becoming live [000443] Live regs: 0000C0E8 {rbx rbp rsi rdi r14 r15} => 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} Live vars: {V01 V02 V03 V31 V52 V53} => {V01 V02 V03 V31 V42 V52 V53} Generating: N145 ( 3, 2) [000023] ------------ t23 = LCL_VAR int V31 tmp1 u:2 r15 REG r15 $241 Generating: N147 ( 1, 1) [000431] ------------ t431 = LCL_VAR int V42 tmp12 u:2 r12 REG r12 /--* t23 int +--* t431 int Generating: N149 ( 5, 4) [000432] N------N-U-- * LE void REG NA IN0019: cmp r15d, r12d Generating: N151 ( 7, 6) [000433] ------------ * JTRUE void REG NA IN001a: jbe L_M6661_BB09 Scope info: end block BB07, IL range [000..000) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 3 (V03 loc0) [000..202) =============== Generating BB08 [000..000) -> BB10 (always), preds={BB07} succs={BB10} flags=0x00000000.40080060: i internal gcsafe LIR BB08 IN (7)={V01 V02 V52 V53 V31 V42 V03} + ByrefExposed + GcHeap OUT(7)={V01 V02 V52 V53 V31 V41 V03} + ByrefExposed + GcHeap Recording Var Locations at start of BB08 V01(rsi) V02(rdi) V52(rbx) V53(rbp) V31(r15) V42(r12) V03(r14) Liveness not changing: 0000000400400075 {V01 V02 V03 V31 V42 V52 V53} Live regs: 00000000 {} => 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} GC regs: 00000000 {} => 00000048 {rbx rsi} Byref regs: 00000000 {} => 00000080 {rdi} L_M6661_BB08: Scope info: begin block BB08, IL range [000..000) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 3 (V03 loc0) [000..202) genIPmappingAdd: ignoring duplicate IL offset 0xffffffff Generating: N155 ( 1, 1) [000438] ------------ t438 = LCL_VAR int V42 tmp12 u:2 r12 (last use) REG r12 /--* t438 int Generating: N157 ( 1, 3) [000440] DA---------- * STORE_LCL_VAR int V41 tmp11 d:4 r12 REG r12 V42 in reg r12 is becoming dead [000438] Live regs: 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} => 0000C0E8 {rbx rbp rsi rdi r14 r15} Live vars: {V01 V02 V03 V31 V42 V52 V53} => {V01 V02 V03 V31 V52 V53} V41 in reg r12 is becoming live [000440] Live regs: 0000C0E8 {rbx rbp rsi rdi r14 r15} => 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} Live vars: {V01 V02 V03 V31 V52 V53} => {V01 V02 V03 V31 V41 V52 V53} Scope info: end block BB08, IL range [000..000) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 3 (V03 loc0) [000..202) IN001b: jmp L_M6661_BB10 =============== Generating BB09 [000..000), preds={BB07} succs={BB10} flags=0x00000000.400b0060: i internal label target gcsafe LIR BB09 IN (6)={V01 V02 V52 V53 V31 V03} + ByrefExposed + GcHeap OUT(7)={V01 V02 V52 V53 V31 V41 V03} + ByrefExposed + GcHeap Recording Var Locations at start of BB09 V01(rsi) V02(rdi) V52(rbx) V53(rbp) V31(r15) V03(r14) Change life 0000000408000075 {V01 V02 V03 V31 V41 V52 V53} -> 0000000400000075 {V01 V02 V03 V31 V52 V53} V41 in reg r12 is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: 00000000 {} => 0000C0E8 {rbx rbp rsi rdi r14 r15} GC regs: 00000000 {} => 00000048 {rbx rsi} Byref regs: 00000000 {} => 00000080 {rdi} L_M6661_BB09: G_M6661_IG08: ; offs=00014FH, funclet=00, bbWeight=0.50 Label: IG09, GCvars=0000000000000000 {}, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi} Scope info: begin block BB09, IL range [000..000) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 3 (V03 loc0) [000..202) genIPmappingAdd: ignoring duplicate IL offset 0xffffffff Generating: N161 ( 1, 1) [000434] ------------ t434 = LCL_VAR int V31 tmp1 u:2 r15 REG r15 $241 /--* t434 int Generating: N163 ( 1, 3) [000436] DA---------- * STORE_LCL_VAR int V41 tmp11 d:3 r12 REG r12 IN001c: mov r12d, r15d V41 in reg r12 is becoming live [000436] Live regs: 0000C0E8 {rbx rbp rsi rdi r14 r15} => 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} Live vars: {V01 V02 V03 V31 V52 V53} => {V01 V02 V03 V31 V41 V52 V53} Scope info: end block BB09, IL range [000..000) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 3 (V03 loc0) [000..202) =============== Generating BB10 [???..???) -> BB14 (cond), preds={BB08,BB09} succs={BB11,BB14} flags=0x00000004.402b0060: i internal label target hascall gcsafe idxlen LIR BB10 IN (7)={V01 V02 V52 V53 V31 V41 V03 } + ByrefExposed + GcHeap OUT(9)={V01 V02 V52 V53 V10 V05 V08 V03 V09} + ByrefExposed + GcHeap Recording Var Locations at start of BB10 V01(rsi) V02(rdi) V52(rbx) V53(rbp) V31(r15) V41(r12) V03(r14) Liveness not changing: 0000000408000075 {V01 V02 V03 V31 V41 V52 V53} Live regs: 00000000 {} => 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} GC regs: 00000000 {} => 00000048 {rbx rsi} Byref regs: 00000000 {} => 00000080 {rdi} L_M6661_BB10: G_M6661_IG09: ; offs=000161H, funclet=00, bbWeight=0.50 Label: IG10, GCvars=0000000000000000 {}, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi} Scope info: begin block BB10, IL range [???..???) Scope info: ignoring block beginning genIPmappingAdd: ignoring duplicate IL offset 0xffffffff Generating: N167 ( 1, 1) [000022] ------------ t22 = LCL_VAR int V31 tmp1 u:2 r15 (last use) REG r15 $241 Generating: N169 ( 1, 1) [000032] ------------ t32 = LCL_VAR int V41 tmp11 u:2 r12 REG r12 $242 /--* t22 int +--* t32 int Generating: N171 ( 3, 3) [000033] ------------ t33 = * SUB int REG r15 $34e V31 in reg r15 is becoming dead [000022] Live regs: 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} => 000050E8 {rbx rbp rsi rdi r12 r14} Live vars: {V01 V02 V03 V31 V41 V52 V53} => {V01 V02 V03 V41 V52 V53} IN001d: sub r15d, r12d /--* t33 int Generating: N173 ( 7, 6) [000035] DA---------- * STORE_LCL_VAR int V05 loc2 d:2 r15 REG r15 V05 in reg r15 is becoming live [000035] Live regs: 000050E8 {rbx rbp rsi rdi r12 r14} => 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} Live vars: {V01 V02 V03 V41 V52 V53} => {V01 V02 V03 V05 V41 V52 V53} Added IP mapping: 0x0042 STACK_EMPTY (G_M6661_IG10,ins#1,ofs#3) label Generating: N175 (???,???) [000917] ------------ IL_OFFSET void IL offset: 0x42 REG NA Generating: N177 ( 1, 1) [000042] ------------ t42 = LCL_VAR int V41 tmp11 u:2 r12 (last use) REG r12 $242 /--* t42 int Generating: N179 ( 5, 4) [000044] DA---------- * STORE_LCL_VAR int V08 loc5 d:2 r12 REG r12 V41 in reg r12 is becoming dead [000042] Live regs: 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} => 0000C0E8 {rbx rbp rsi rdi r14 r15} Live vars: {V01 V02 V03 V05 V41 V52 V53} => {V01 V02 V03 V05 V52 V53} V08 in reg r12 is becoming live [000044] Live regs: 0000C0E8 {rbx rbp rsi rdi r14 r15} => 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} Live vars: {V01 V02 V03 V05 V52 V53} => {V01 V02 V03 V05 V08 V52 V53} Generating: N181 ( 1, 1) [000447] ------------ t447 = LCL_VAR ref V52 tmp22 u:2 rbx REG rbx /--* t447 ref Generating: N183 (???,???) [000992] -c---------- t992 = * LEA(b+8) ref REG NA /--* t992 ref Generating: N185 ( 3, 3) [000448] ---XG------- t448 = * IND int REG r13 IN001e: mov r13d, dword ptr [rbx+8] /--* t448 int Generating: N187 ( 7, 6) [000050] DA-XG------- * STORE_LCL_VAR int V09 loc6 d:2 r13 REG r13 V09 in reg r13 is becoming live [000050] Live regs: 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V01 V02 V03 V05 V08 V52 V53} => {V01 V02 V03 V05 V08 V09 V52 V53} Added IP mapping: 0x004F STACK_EMPTY (G_M6661_IG10,ins#2,ofs#7) Generating: N189 (???,???) [000918] ------------ IL_OFFSET void IL offset: 0x4f REG NA Generating: N191 ( 3, 2) [000051] ------------ t51 = LCL_VAR int V09 loc6 u:2 r13 REG r13 Generating: N193 ( 1, 1) [000052] ------------ t52 = LCL_VAR int V08 loc5 u:2 r12 REG r12 $242 /--* t51 int +--* t52 int Generating: N195 ( 5, 4) [000053] ------------ t53 = * SUB int REG rax IN001f: mov eax, r13d IN0020: sub eax, r12d /--* t53 int Generating: N197 ( 5, 4) [000055] DA---------- * STORE_LCL_VAR int V10 loc7 d:2 NA REG NA IN0021: mov dword ptr [V10 rsp+E4H], eax Live vars: {V01 V02 V03 V05 V08 V09 V52 V53} => {V01 V02 V03 V05 V08 V09 V10 V52 V53} Generating: N199 ( 3, 2) [000063] -------N---- t63 = LCL_VAR_ADDR byref V11 loc8 rcx * ref V11._bits (offs=0x00) -> V54 tmp24 * int V11._sign (offs=0x08) -> V55 tmp25 REG rcx IN0022: lea rcx, bword ptr [V11 rsp+D0H] Byref regs: 00000080 {rdi} => 00000082 {rcx rdi} /--* t63 byref Generating: N201 ( 7, 6) [000563] DA--------L- * STORE_LCL_VAR long V75 tmp45 d:2 rcx REG rcx Byref regs: 00000082 {rcx rdi} => 00000080 {rdi} V75 in reg rcx is becoming live [000563] Live regs: 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V01 V02 V03 V05 V08 V09 V10 V52 V53} => {V01 V02 V03 V05 V08 V09 V10 V52 V53 V75} Generating: N203 ( 3, 2) [000547] -------N---- t547 = LCL_VAR_ADDR byref V73 tmp43 rdx REG rdx IN0023: lea rdx, bword ptr [V73 rsp+48H] Byref regs: 00000080 {rdi} => 00000084 {rdx rdi} /--* t547 byref Generating: N205 ( 3, 3) [000549] DA---------- * STORE_LCL_VAR byref V74 tmp44 d:2 rdx REG rdx Byref regs: 00000084 {rdx rdi} => 00000080 {rdi} V74 in reg rdx is becoming live [000549] Live regs: 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0EE {rcx rdx rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V01 V02 V03 V05 V08 V09 V10 V52 V53 V75} => {V01 V02 V03 V05 V08 V09 V10 V52 V53 V74 V75} Byref regs: 00000080 {rdi} => 00000084 {rdx rdi} Generating: N207 ( 1, 1) [000550] ------------ t550 = LCL_VAR byref V74 tmp44 u:2 rdx Zero Fseq[Mantissa] REG rdx $401 Generating: N209 ( 1, 1) [000552] -------N---- t552 = LCL_VAR ref V52 tmp22 u:2 rbx REG rbx /--* t550 byref +--* t552 ref Generating: N211 (???,???) [000919] -A---------- * STOREIND ref REG NA IN0024: mov gword ptr [rdx], rbx Generating: N213 ( 1, 1) [000555] ------------ t555 = LCL_VAR byref V74 tmp44 u:2 rdx (last use) REG rdx $401 /--* t555 byref Generating: N215 ( 2, 2) [000557] -c---------- t557 = * LEA(b+8) byref REG NA Generating: N217 ( 1, 1) [000559] -------N---- t559 = LCL_VAR int V53 tmp23 u:2 rbp REG rbp /--* t557 byref +--* t559 int Generating: N219 (???,???) [000920] -A--------L- * STOREIND int REG NA V74 in reg rdx is becoming dead [000555] Live regs: 0000F0EE {rcx rdx rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V01 V02 V03 V05 V08 V09 V10 V52 V53 V74 V75} => {V01 V02 V03 V05 V08 V09 V10 V52 V53 V75} Byref regs: 00000084 {rdx rdi} => 00000080 {rdi} IN0025: mov dword ptr [rdx+8], ebp Generating: N221 ( 3, 2) [000564] ------------ t564 = LCL_VAR long V75 tmp45 u:2 rcx (last use) REG rcx $400 /--* t564 long Generating: N223 (???,???) [001011] ------------ t1011 = * PUTARG_REG long REG rcx V75 in reg rcx is becoming dead [000564] Live regs: 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V01 V02 V03 V05 V08 V09 V10 V52 V53 V75} => {V01 V02 V03 V05 V08 V09 V10 V52 V53} Generating: N225 ( 3, 2) [000565] -------N---- t565 = LCL_VAR_ADDR byref V73 tmp43 rdx REG rdx IN0026: lea rdx, bword ptr [V73 rsp+48H] Byref regs: 00000080 {rdi} => 00000084 {rdx rdi} /--* t565 byref Generating: N227 (???,???) [001012] ------------ t1012 = * PUTARG_REG byref REG rdx Byref regs: 00000084 {rdx rdi} => 00000080 {rdi} Byref regs: 00000080 {rdi} => 00000084 {rdx rdi} Generating: N229 ( 1, 1) [000058] ------------ t58 = LCL_VAR int V08 loc5 u:2 r12 REG r12 $242 /--* t58 int Generating: N231 (???,???) [001013] ------------ t1013 = * PUTARG_REG int REG r9 IN0027: mov r9d, r12d Generating: N233 ( 1, 1) [000057] ------------ t57 = CNS_INT int 0 REG r8 $40 IN0028: xor r8d, r8d /--* t57 int Generating: N235 (???,???) [001014] ------------ t1014 = * PUTARG_REG int REG r8 /--* t1011 long arg0 in rcx +--* t1012 byref arg1 in rdx +--* t1013 int arg3 in r9 +--* t1014 int arg2 in r8 Generating: N237 ( 49, 35) [000059] S-CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger REG NA $VN.Void Byref regs: 00000084 {rdx rdi} => 00000080 {rdi} Call: GCvars=0000000000000000 {}, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi} IN0029: call Microsoft.CodeAnalysis.RealParser:AccumulateDecimalDigitsIntoBigInteger(DecimalFloatingPointString,int,int):System.Numerics.BigInteger Added IP mapping: 0x0061 STACK_EMPTY (G_M6661_IG10,ins#13,ofs#55) Generating: N239 (???,???) [000921] ------------ IL_OFFSET void IL offset: 0x61 REG NA Generating: N241 ( 3, 2) [000065] ------------ t65 = LCL_VAR int V05 loc2 u:2 r15 REG r15 $34e Generating: N243 ( 1, 1) [000066] -c---------- t66 = CNS_INT int 0 REG NA $40 /--* t65 int +--* t66 int Generating: N245 ( 5, 4) [000067] N------N---- * EQ void REG NA $351 IN002a: test r15d, r15d Generating: N247 ( 7, 6) [000068] ------------ * JTRUE void REG NA IN002b: je L_M6661_BB14 Scope info: end block BB10, IL range [???..???) Scope info: ignoring block end =============== Generating BB11 [065..070) -> BB13 (cond), preds={BB10} succs={BB12,BB13} flags=0x00000004.40080020: i hascall gcsafe LIR BB11 IN (9)={V01 V02 V52 V53 V10 V05 V08 V03 V09} + ByrefExposed + GcHeap OUT(9)={V01 V02 V52 V53 V10 V05 V08 V03 V09} + ByrefExposed + GcHeap Recording Var Locations at start of BB11 V01(rsi) V02(rdi) V52(rbx) V53(rbp) V05(r15) V08(r12) V03(r14) V09(r13) Liveness not changing: 0000000C03800035 {V01 V02 V03 V05 V08 V09 V10 V52 V53} Live regs: 00000000 {} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} GC regs: 00000000 {} => 00000048 {rbx rsi} Byref regs: 00000000 {} => 00000080 {rdi} L_M6661_BB11: Scope info: begin block BB11, IL range [065..070) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 3 (V03 loc0) [000..202) 10 (V10 loc7) [000..202) 5 (V05 loc2) [000..202) 8 (V08 loc5) [000..202) 9 (V09 loc6) [000..202) Generating: N251 ( 1, 1) [000382] ------------ t382 = LCL_VAR ref V01 arg1 u:1 rsi REG rsi $c0 /--* t382 ref Generating: N253 (???,???) [001015] ------------ t1015 = * PUTARG_REG ref REG rcx IN002c: mov rcx, rsi GC regs: 00000048 {rbx rsi} => 0000004A {rcx rbx rsi} /--* t1015 ref this in rcx Generating: N255 ( 15, 8) [000383] --CXG------- t383 = * CALL int FloatingPointType.get_OverflowDecimalExponent REG rax $291 GC regs: 0000004A {rcx rbx rsi} => 00000048 {rbx rsi} Call: GCvars=0000000000000000 {}, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi} IN002d: call FloatingPointType:get_OverflowDecimalExponent():int:this /--* t383 int Generating: N257 ( 16, 10) [000385] ---XG------- t385 = * CAST long <- int REG rcx $480 IN002e: movsxd rcx, eax Generating: N259 ( 3, 2) [000380] ------------ t380 = LCL_VAR int V05 loc2 u:2 r15 REG r15 $34e /--* t380 int Generating: N261 ( 4, 4) [000381] ---------U-- t381 = * CAST long <- ulong <- uint REG rax $481 IN002f: mov eax, r15d /--* t385 long +--* t381 long Generating: N263 ( 21, 15) [000386] J--XG--N---- * GE void REG NA $352 IN0030: cmp rcx, rax Generating: N265 ( 23, 17) [000387] ---XG------- * JTRUE void REG NA IN0031: jge L_M6661_BB13 Scope info: end block BB11, IL range [065..070) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 3 (V03 loc0) [000..202) 10 (V10 loc7) [000..202) 5 (V05 loc2) [000..202) 8 (V08 loc5) [000..202) 9 (V09 loc6) [000..202) =============== Generating BB12 [070..07A) (return), preds={BB11} succs={} flags=0x00000004.40080020: i hascall gcsafe LIR BB12 IN (2)={V01 V02} + ByrefExposed + GcHeap OUT(0)={ } Recording Var Locations at start of BB12 V01(rsi) V02(rdi) Change life 0000000C03800035 {V01 V02 V03 V05 V08 V09 V10 V52 V53} -> 0000000000000005 {V01 V02} V52 in reg rbx is becoming dead [------] Live regs: (unchanged) 00000000 {} V53 in reg rbp is becoming dead [------] Live regs: (unchanged) 00000000 {} V05 in reg r15 is becoming dead [------] Live regs: (unchanged) 00000000 {} V08 in reg r12 is becoming dead [------] Live regs: (unchanged) 00000000 {} V03 in reg r14 is becoming dead [------] Live regs: (unchanged) 00000000 {} V09 in reg r13 is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: 00000000 {} => 000000C0 {rsi rdi} GC regs: 00000000 {} => 00000040 {rsi} Byref regs: 00000000 {} => 00000080 {rdi} L_M6661_BB12: Scope info: begin block BB12, IL range [070..07A) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) Added IP mapping: 0x0070 STACK_EMPTY (G_M6661_IG10,ins#21,ofs#87) label Generating: N269 (???,???) [000922] ------------ IL_OFFSET void IL offset: 0x70 REG NA Generating: N271 ( 1, 1) [000393] ------------ t393 = LCL_VAR ref V01 arg1 u:1 rsi REG rsi $c0 /--* t393 ref Generating: N273 (???,???) [001016] ------------ t1016 = * PUTARG_REG ref REG rcx IN0032: mov rcx, rsi GC regs: 00000040 {rsi} => 00000042 {rcx rsi} Generating: N275 ( 1, 1) [001017] ------------ t1017 = LCL_VAR ref V01 arg1 rsi (last use) REG rsi /--* t1017 ref Generating: N277 ( 2, 2) [001018] -c---------- t1018 = * LEA(b+0) byref REG NA /--* t1018 byref Generating: N279 ( 5, 4) [001019] ------------ t1019 = * IND long REG rax V01 in reg rsi is becoming dead [001017] Live regs: 000000C0 {rsi rdi} => 00000080 {rdi} Live vars: {V01 V02} => {V02} GC regs: 00000042 {rcx rsi} => 00000002 {rcx} IN0033: mov rax, qword ptr [rsi] /--* t1019 long Generating: N281 ( 6, 5) [001020] -c---------- t1020 = * LEA(b+80) long REG NA /--* t1020 long Generating: N283 ( 9, 7) [001021] ------------ t1021 = * IND long REG rax IN0034: mov rax, qword ptr [rax+80] /--* t1021 long Generating: N285 ( 10, 8) [001022] -c---------- t1022 = * LEA(b+8) long REG NA /--* t1022 long Generating: N287 ( 13, 10) [001023] -c---------- t1023 = * IND long REG NA /--* t1016 ref this in rcx +--* t1023 long control expr Generating: N289 ( 21, 10) [000394] --CXG------- t394 = * CALLV ind long FloatingPointType.get_Infinity REG rax $458 GC regs: 00000002 {rcx} => 00000000 {} Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000080 {rdi} IN0035: call qword ptr [rax+8]FloatingPointType:get_Infinity():long:this Generating: N291 ( 1, 1) [000392] ------------ t392 = LCL_VAR byref V02 arg2 u:1 rdi (last use) REG rdi $81 /--* t392 byref +--* t394 long Generating: N293 (???,???) [000923] -ACXG------- * STOREIND long REG NA V02 in reg rdi is becoming dead [000392] Live regs: 00000080 {rdi} => 00000000 {} Live vars: {V02} => {} Byref regs: 00000080 {rdi} => 00000000 {} IN0036: mov qword ptr [rdi], rax Generating: N295 ( 1, 1) [000397] ------------ t397 = CNS_INT int 3 REG rax $48 IN0037: mov eax, 3 /--* t397 int Generating: N297 ( 2, 2) [000521] ------------ * RETURN int REG NA $5ca Scope info: end block BB12, IL range [070..07A) Scope info: open scopes = Added IP mapping: EPILOG STACK_EMPTY (G_M6661_IG10,ins#27,ofs#108) label Reserving epilog IG for block BB12 G_M6661_IG10: ; offs=000164H, funclet=00, bbWeight=0.50 *************** After placeholder IG creation G_M6661_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG G_M6661_IG02: ; offs=000000H, size=0006H, gcrefRegs=00000040 {rsi}, byrefRegs=00000082 {rcx rdi}, byref G_M6661_IG03: ; offs=000006H, size=000AH, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG04: ; offs=000010H, size=0014H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG05: ; epilog placeholder, next placeholder=IG11 , BB03 [0001], epilog, extend <-- First placeholder ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000048 {rbx rsi}, PrevByrefRegs=00000080 {rdi} ; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000040 {rsi}, InitByrefRegs=00000080 {rdi} G_M6661_IG06: ; offs=000124H, size=0028H, gcVars=0000000000000000 {}, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, gcvars, byref G_M6661_IG07: ; offs=00014CH, size=0003H, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG08: ; offs=00014FH, size=0012H, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG09: ; offs=000161H, size=0003H, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG10: ; offs=000164H, size=006CH, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG11: ; epilog placeholder, next placeholder=, BB12 [0004], epilog, extend <-- Last placeholder ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000048 {rbx rsi}, PrevByrefRegs=00000080 {rdi} ; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000048 {rbx rsi}, InitByrefRegs=00000080 {rdi} G_M6661_IG12: ; offs=0002D0H, size=0000H, gcrefRegs=00000000 {} <-- Current IG =============== Generating BB13 [07A..082), preds={BB11} succs={BB14} flags=0x00000004.400b0020: i label target hascall gcsafe LIR BB13 IN (9)={V01 V02 V52 V53 V10 V05 V08 V03 V09} + ByrefExposed + GcHeap OUT(8)={V01 V02 V52 V53 V10 V08 V03 V09} + ByrefExposed + GcHeap Recording Var Locations at start of BB13 V01(rsi) V02(rdi) V52(rbx) V53(rbp) V05(r15) V08(r12) V03(r14) V09(r13) Change life 0000000000000000 {} -> 0000000C03800035 {V01 V02 V03 V05 V08 V09 V10 V52 V53} V01 in reg rsi is becoming live [------] Live regs: 00000000 {} => 00000040 {rsi} V02 in reg rdi is becoming live [------] Live regs: 00000040 {rsi} => 000000C0 {rsi rdi} V52 in reg rbx is becoming live [------] Live regs: 000000C0 {rsi rdi} => 000000C8 {rbx rsi rdi} V53 in reg rbp is becoming live [------] Live regs: 000000C8 {rbx rsi rdi} => 000000E8 {rbx rbp rsi rdi} V05 in reg r15 is becoming live [------] Live regs: 000000E8 {rbx rbp rsi rdi} => 000080E8 {rbx rbp rsi rdi r15} V08 in reg r12 is becoming live [------] Live regs: 000080E8 {rbx rbp rsi rdi r15} => 000090E8 {rbx rbp rsi rdi r12 r15} V03 in reg r14 is becoming live [------] Live regs: 000090E8 {rbx rbp rsi rdi r12 r15} => 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} V09 in reg r13 is becoming live [------] Live regs: 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} Live regs: (unchanged) 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} GC regs: (unchanged) 00000048 {rbx rsi} Byref regs: (unchanged) 00000080 {rdi} L_M6661_BB13: Label: IG12, GCvars=0000000000000000 {}, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi} Scope info: begin block BB13, IL range [07A..082) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 10 (V10 loc7) [000..202) 5 (V05 loc2) [000..202) 8 (V08 loc5) [000..202) 3 (V03 loc0) [000..202) 9 (V09 loc6) [000..202) Added IP mapping: 0x007A STACK_EMPTY (G_M6661_IG12,ins#0,ofs#0) label Generating: N301 (???,???) [000924] ------------ IL_OFFSET void IL offset: 0x7a REG NA Generating: N303 ( 3, 2) [000388] -------N---- t388 = LCL_VAR_ADDR byref V11 loc8 rcx * ref V11._bits (offs=0x00) -> V54 tmp24 * int V11._sign (offs=0x08) -> V55 tmp25 REG rcx IN0038: lea rcx, bword ptr [V11 rsp+D0H] Byref regs: 00000080 {rdi} => 00000082 {rcx rdi} /--* t388 byref Generating: N305 (???,???) [001024] ------------ t1024 = * PUTARG_REG byref REG rcx Byref regs: 00000082 {rcx rdi} => 00000080 {rdi} Byref regs: 00000080 {rdi} => 00000082 {rcx rdi} Generating: N307 ( 3, 2) [000390] ------------ t390 = LCL_VAR int V05 loc2 u:2 r15 (last use) REG r15 $34e /--* t390 int Generating: N309 (???,???) [001025] ------------ t1025 = * PUTARG_REG int REG rdx V05 in reg r15 is becoming dead [000390] Live regs: 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} => 000070E8 {rbx rbp rsi rdi r12 r13 r14} Live vars: {V01 V02 V03 V05 V08 V09 V10 V52 V53} => {V01 V02 V03 V08 V09 V10 V52 V53} IN0039: mov edx, r15d /--* t1024 byref arg0 in rcx +--* t1025 int arg1 in rdx Generating: N311 ( 20, 12) [000391] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen REG NA $VN.Void Byref regs: 00000082 {rcx rdi} => 00000080 {rdi} Call: GCvars=0000000000000000 {}, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi} IN003a: call Microsoft.CodeAnalysis.RealParser:MultiplyByPowerOfTen(byref,int) Scope info: end block BB13, IL range [07A..082) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 10 (V10 loc7) [000..202) 8 (V08 loc5) [000..202) 3 (V03 loc0) [000..202) 9 (V09 loc6) [000..202) =============== Generating BB14 [082..092) -> BB16 (cond), preds={BB10,BB13} succs={BB15,BB16} flags=0x00000004.400b0020: i label target hascall gcsafe LIR BB14 IN (8)={V01 V02 V52 V53 V10 V08 V03 V09} + ByrefExposed + GcHeap OUT(9)={V01 V02 V13 V52 V53 V10 V08 V03 V09} + ByrefExposed + GcHeap Recording Var Locations at start of BB14 V01(rsi) V02(rdi) V52(rbx) V53(rbp) V08(r12) V03(r14) V09(r13) Liveness not changing: 0000000C02800035 {V01 V02 V03 V08 V09 V10 V52 V53} Live regs: 00000000 {} => 000070E8 {rbx rbp rsi rdi r12 r13 r14} GC regs: 00000000 {} => 00000048 {rbx rsi} Byref regs: 00000000 {} => 00000080 {rdi} L_M6661_BB14: G_M6661_IG12: ; offs=0002D0H, funclet=00, bbWeight=0.50 Label: IG13, GCvars=0000000000000000 {}, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi} Scope info: begin block BB14, IL range [082..092) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 10 (V10 loc7) [000..202) 8 (V08 loc5) [000..202) 3 (V03 loc0) [000..202) 9 (V09 loc6) [000..202) Generating: N315 ( 3, 2) [000577] -------N---- t577 = LCL_VAR_ADDR byref V76 tmp46 rcx REG rcx IN003b: lea rcx, bword ptr [V76 rsp+38H] Byref regs: 00000080 {rdi} => 00000082 {rcx rdi} /--* t577 byref Generating: N317 ( 3, 3) [000579] DA---------- * STORE_LCL_VAR byref V77 tmp47 d:2 rcx REG rcx Byref regs: 00000082 {rcx rdi} => 00000080 {rdi} V77 in reg rcx is becoming live [000579] Live regs: 000070E8 {rbx rbp rsi rdi r12 r13 r14} => 000070EA {rcx rbx rbp rsi rdi r12 r13 r14} Live vars: {V01 V02 V03 V08 V09 V10 V52 V53} => {V01 V02 V03 V08 V09 V10 V52 V53 V77} Byref regs: 00000080 {rdi} => 00000082 {rcx rdi} Generating: N319 ( 1, 1) [000580] ------------ t580 = LCL_VAR byref V77 tmp47 u:2 rcx Zero Fseq[_bits] REG rcx $405 Generating: N321 ( 3, 2) [000582] -------N---- t582 = LCL_VAR ref (AX) V54 tmp24 rdx REG rdx $181 IN003c: mov rdx, gword ptr [V54 rsp+D0H] GC regs: 00000048 {rbx rsi} => 0000004C {rdx rbx rsi} /--* t580 byref +--* t582 ref Generating: N323 (???,???) [000925] -A--G------- * STOREIND ref REG NA GC regs: 0000004C {rdx rbx rsi} => 00000048 {rbx rsi} IN003d: mov gword ptr [rcx], rdx Generating: N325 ( 1, 1) [000585] ------------ t585 = LCL_VAR byref V77 tmp47 u:2 rcx (last use) REG rcx $405 /--* t585 byref Generating: N327 ( 2, 2) [000587] -c---------- t587 = * LEA(b+8) byref REG NA Generating: N329 ( 3, 2) [000589] -------N---- t589 = LCL_VAR int (AX) V55 tmp25 rdx REG rdx $243 IN003e: mov edx, dword ptr [V55 rsp+D8H] /--* t587 byref +--* t589 int Generating: N331 (???,???) [000926] -A--G-----L- * STOREIND int REG NA V77 in reg rcx is becoming dead [000585] Live regs: 000070EA {rcx rbx rbp rsi rdi r12 r13 r14} => 000070E8 {rbx rbp rsi rdi r12 r13 r14} Live vars: {V01 V02 V03 V08 V09 V10 V52 V53 V77} => {V01 V02 V03 V08 V09 V10 V52 V53} Byref regs: 00000082 {rcx rdi} => 00000080 {rdi} IN003f: mov dword ptr [rcx+8], edx Generating: N333 ( 3, 2) [000592] -------N---- t592 = LCL_VAR_ADDR byref V76 tmp46 rcx REG rcx IN0040: lea rcx, bword ptr [V76 rsp+38H] Byref regs: 00000080 {rdi} => 00000082 {rcx rdi} /--* t592 byref Generating: N335 (???,???) [001026] ------------ t1026 = * PUTARG_REG byref REG rcx Byref regs: 00000082 {rcx rdi} => 00000080 {rdi} Byref regs: 00000080 {rdi} => 00000082 {rcx rdi} Generating: N337 ( 3, 3) [000071] ------------ t71 = LCL_VAR_ADDR long V12 loc9 rdx REG rdx $443 IN0041: lea rdx, [V12 rsp+C8H] /--* t71 long Generating: N339 (???,???) [001027] ------------ t1027 = * PUTARG_REG long REG rdx /--* t1026 byref arg0 in rcx +--* t1027 long arg1 in rdx Generating: N341 ( 41, 28) [000072] --CXG------- t72 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits REG rax $293 Byref regs: 00000082 {rcx rdi} => 00000080 {rdi} Call: GCvars=0000000000000000 {}, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi} IN0042: call Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger,byref):int /--* t72 int Generating: N343 ( 41, 28) [000077] DA-XG------- * STORE_LCL_VAR int V13 loc10 d:2 r15 REG r15 IN0043: mov r15d, eax V13 in reg r15 is becoming live [000077] Live regs: 000070E8 {rbx rbp rsi rdi r12 r13 r14} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V01 V02 V03 V08 V09 V10 V52 V53} => {V01 V02 V03 V08 V09 V10 V13 V52 V53} Added IP mapping: 0x008D STACK_EMPTY (G_M6661_IG13,ins#9,ofs#47) label Generating: N345 (???,???) [000927] ------------ IL_OFFSET void IL offset: 0x8d REG NA Generating: N347 ( 1, 1) [000078] ------------ t78 = LCL_VAR int V13 loc10 u:2 r15 REG r15 $293 Generating: N349 ( 3, 2) [000079] ------------ t79 = LCL_VAR int V03 loc0 u:2 r14 REG r14 $348 /--* t78 int +--* t79 int Generating: N351 ( 5, 4) [000080] N------N-U-- * GE void REG NA $353 IN0044: cmp r15d, r14d Generating: N353 ( 7, 6) [000081] ------------ * JTRUE void REG NA IN0045: jae L_M6661_BB16 Scope info: end block BB14, IL range [082..092) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 10 (V10 loc7) [000..202) 8 (V08 loc5) [000..202) 3 (V03 loc0) [000..202) 9 (V09 loc6) [000..202) =============== Generating BB15 [092..096) -> BB17 (cond), preds={BB14} succs={BB16,BB17} flags=0x00000000.40080020: i gcsafe LIR BB15 IN (9)={V01 V02 V13 V52 V53 V10 V08 V03 V09} + ByrefExposed + GcHeap OUT(9)={V01 V02 V13 V52 V53 V10 V08 V03 V09} + ByrefExposed + GcHeap Recording Var Locations at start of BB15 V01(rsi) V02(rdi) V13(r15) V52(rbx) V53(rbp) V08(r12) V03(r14) V09(r13) Liveness not changing: 0000000C0280003D {V01 V02 V03 V08 V09 V10 V13 V52 V53} Live regs: 00000000 {} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} GC regs: 00000000 {} => 00000048 {rbx rsi} Byref regs: 00000000 {} => 00000080 {rdi} L_M6661_BB15: Scope info: begin block BB15, IL range [092..096) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 10 (V10 loc7) [000..202) 8 (V08 loc5) [000..202) 3 (V03 loc0) [000..202) 9 (V09 loc6) [000..202) 13 (V13 loc10) [000..202) Added IP mapping: 0x0092 STACK_EMPTY (G_M6661_IG13,ins#11,ofs#56) label Generating: N357 (???,???) [000928] ------------ IL_OFFSET void IL offset: 0x92 REG NA Generating: N359 ( 1, 1) [000091] -----------z t91 = LCL_VAR int V10 loc7 u:2 rax REG rax Generating: N361 ( 1, 1) [000092] -c---------- t92 = CNS_INT int 0 REG NA $40 /--* t91 int +--* t92 int Generating: N363 ( 3, 3) [000093] J------N---- * NE void REG NA IN0046: mov eax, dword ptr [V10 rsp+E4H] V10 in reg rax is becoming live [000091] Live regs: 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0E9 {rax rbx rbp rsi rdi r12 r13 r14 r15} IN0047: test eax, eax Generating: N001 ( 3, 2) [001077] -----------Z t1077 = LCL_VAR int V10 loc7 rax REG rax IN0048: mov dword ptr [V10 rsp+E4H], eax V10 in reg rax is becoming dead [001077] Live regs: 0000F0E9 {rax rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} Generating: N365 ( 5, 5) [000094] ------------ * JTRUE void REG NA IN0049: jne L_M6661_BB17 Scope info: end block BB15, IL range [092..096) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 10 (V10 loc7) [000..202) 8 (V08 loc5) [000..202) 3 (V03 loc0) [000..202) 9 (V09 loc6) [000..202) 13 (V13 loc10) [000..202) =============== Generating BB16 [096..0A7) -> BB44 (always), preds={BB14,BB15} succs={BB44} flags=0x00000004.400b0020: i label target hascall gcsafe LIR BB16 IN (4)={V01 V02 V13 V10} + ByrefExposed + GcHeap OUT(1)={ V51 } Recording Var Locations at start of BB16 V01(rsi) V02(rdi) V13(r15) Change life 0000000C0280003D {V01 V02 V03 V08 V09 V10 V13 V52 V53} -> 000000000080000D {V01 V02 V10 V13} V52 in reg rbx is becoming dead [------] Live regs: (unchanged) 00000000 {} V53 in reg rbp is becoming dead [------] Live regs: (unchanged) 00000000 {} V08 in reg r12 is becoming dead [------] Live regs: (unchanged) 00000000 {} V03 in reg r14 is becoming dead [------] Live regs: (unchanged) 00000000 {} V09 in reg r13 is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: 00000000 {} => 000080C0 {rsi rdi r15} GC regs: 00000000 {} => 00000040 {rsi} Byref regs: 00000000 {} => 00000080 {rdi} L_M6661_BB16: G_M6661_IG13: ; offs=0002E0H, funclet=00, bbWeight=0.50 Label: IG14, GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi} Scope info: begin block BB16, IL range [096..0A7) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 10 (V10 loc7) [000..202) 13 (V13 loc10) [000..202) Added IP mapping: 0x0096 STACK_EMPTY (G_M6661_IG14,ins#0,ofs#0) label Generating: N369 (???,???) [000929] ------------ IL_OFFSET void IL offset: 0x96 REG NA Generating: N371 ( 1, 1) [000088] ------------ t88 = LCL_VAR byref V02 arg2 u:1 rdi (last use) REG rdi $81 /--* t88 byref Generating: N373 (???,???) [001028] ------------ * PUTARG_STK [+0x20] void REG NA V02 in reg rdi is becoming dead [000088] Live regs: 000080C0 {rsi rdi r15} => 00008040 {rsi r15} Live vars: {V01 V02 V10 V13} => {V01 V10 V13} Byref regs: 00000080 {rdi} => 00000000 {} IN004a: mov bword ptr [V30+0x20 rsp+20H], rdi Generating: N375 ( 1, 1) [000084] -c---------- t84 = LCL_VAR int V10 loc7 u:2 NA (last use) REG NA Generating: N377 ( 1, 1) [000085] -c---------- t85 = CNS_INT int 0 REG NA $40 /--* t84 int +--* t85 int Generating: N379 ( 6, 3) [000086] N----------- t86 = * NE int REG r8 Live vars: {V01 V10 V13} => {V01 V13} IN004b: cmp dword ptr [V10 rsp+E4H], 0 IN004c: setne r8b IN004d: movzx r8, r8b /--* t86 int Generating: N381 (???,???) [001029] ------------ t1029 = * PUTARG_REG int REG r8 Generating: N383 ( 3, 2) [000082] ------------ t82 = LCL_VAR ref (AX) V12 loc9 rcx REG rcx $18d IN004e: mov rcx, gword ptr [V12 rsp+C8H] GC regs: 00000040 {rsi} => 00000042 {rcx rsi} /--* t82 ref Generating: N385 (???,???) [001030] ------------ t1030 = * PUTARG_REG ref REG rcx GC regs: 00000042 {rcx rsi} => 00000040 {rsi} GC regs: 00000040 {rsi} => 00000042 {rcx rsi} Generating: N387 ( 1, 1) [000083] ------------ t83 = LCL_VAR int V13 loc10 u:2 r15 (last use) REG r15 $293 /--* t83 int Generating: N389 (???,???) [001031] ------------ t1031 = * PUTARG_REG int REG rdx V13 in reg r15 is becoming dead [000083] Live regs: 00008040 {rsi r15} => 00000040 {rsi} Live vars: {V01 V13} => {V01} IN004f: mov edx, r15d Generating: N391 ( 1, 1) [000087] ------------ t87 = LCL_VAR ref V01 arg1 u:1 rsi (last use) REG rsi $c0 /--* t87 ref Generating: N393 (???,???) [001032] ------------ t1032 = * PUTARG_REG ref REG r9 V01 in reg rsi is becoming dead [000087] Live regs: 00000040 {rsi} => 00000000 {} Live vars: {V01} => {} GC regs: 00000042 {rcx rsi} => 00000002 {rcx} IN0050: mov r9, rsi GC regs: 00000002 {rcx} => 00000202 {rcx r9} /--* t1029 int arg2 in r8 +--* t1030 ref arg0 in rcx +--* t1031 int arg1 in rdx +--* t1032 ref arg3 in r9 Generating: N395 ( 29, 17) [000089] --CXG------- t89 = * CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits REG rax $5c7 GC regs: 00000202 {rcx r9} => 00000200 {r9} GC regs: 00000200 {r9} => 00000000 {} Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN0051: call Microsoft.CodeAnalysis.RealParser:ConvertBigIntegerToFloatingPointBits(System.Byte[],int,bool,FloatingPointType,byref):int /--* t89 int Generating: N397 ( 29, 17) [000600] DA-XG------- * STORE_LCL_VAR int V51 tmp21 d:3 rax REG rax V51 in reg rax is becoming live [000600] Live regs: 00000000 {} => 00000001 {rax} Live vars: {} => {V51} Scope info: end block BB16, IL range [096..0A7) Scope info: open scopes = IN0052: jmp L_M6661_BB44 =============== Generating BB17 [0A7..0B0) -> BB19 (cond), preds={BB15} succs={BB18,BB19} flags=0x00000000.400b0020: i label target gcsafe LIR BB17 IN (9)={V01 V02 V13 V52 V53 V10 V08 V03 V09} + ByrefExposed + GcHeap OUT(9)={V01 V02 V13 V52 V53 V10 V08 V03 V09} + ByrefExposed + GcHeap Recording Var Locations at start of BB17 V01(rsi) V02(rdi) V13(r15) V52(rbx) V53(rbp) V08(r12) V03(r14) V09(r13) Change life 0000000000000080 {V51} -> 0000000C0280003D {V01 V02 V03 V08 V09 V10 V13 V52 V53} V51 in reg rax is becoming dead [------] Live regs: (unchanged) 00000000 {} V01 in reg rsi is becoming live [------] Live regs: 00000000 {} => 00000040 {rsi} V02 in reg rdi is becoming live [------] Live regs: 00000040 {rsi} => 000000C0 {rsi rdi} V13 in reg r15 is becoming live [------] Live regs: 000000C0 {rsi rdi} => 000080C0 {rsi rdi r15} V52 in reg rbx is becoming live [------] Live regs: 000080C0 {rsi rdi r15} => 000080C8 {rbx rsi rdi r15} V53 in reg rbp is becoming live [------] Live regs: 000080C8 {rbx rsi rdi r15} => 000080E8 {rbx rbp rsi rdi r15} V08 in reg r12 is becoming live [------] Live regs: 000080E8 {rbx rbp rsi rdi r15} => 000090E8 {rbx rbp rsi rdi r12 r15} V03 in reg r14 is becoming live [------] Live regs: 000090E8 {rbx rbp rsi rdi r12 r15} => 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} V09 in reg r13 is becoming live [------] Live regs: 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} Live regs: (unchanged) 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} GC regs: (unchanged) 00000048 {rbx rsi} Byref regs: (unchanged) 00000080 {rdi} L_M6661_BB17: G_M6661_IG14: ; offs=00032EH, funclet=00, bbWeight=0.50 Label: IG15, GCvars=0000000000000000 {}, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi} Scope info: begin block BB17, IL range [0A7..0B0) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 10 (V10 loc7) [000..202) 8 (V08 loc5) [000..202) 3 (V03 loc0) [000..202) 9 (V09 loc6) [000..202) Added IP mapping: 0x00A7 STACK_EMPTY (G_M6661_IG15,ins#0,ofs#0) label Generating: N401 (???,???) [000930] ------------ IL_OFFSET void IL offset: 0xa7 REG NA Generating: N403 ( 1, 1) [000097] ------------ t97 = LCL_VAR int V53 tmp23 u:2 rbp REG rbp Generating: N405 ( 1, 1) [000098] -c---------- t98 = CNS_INT int 0 REG NA $40 /--* t97 int +--* t98 int Generating: N407 ( 3, 3) [000099] J---G--N---- * LT void REG NA IN0053: test ebp, ebp Generating: N409 ( 5, 5) [000100] ----G------- * JTRUE void REG NA IN0054: jl L_M6661_BB19 Scope info: end block BB17, IL range [0A7..0B0) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 10 (V10 loc7) [000..202) 8 (V08 loc5) [000..202) 3 (V03 loc0) [000..202) 9 (V09 loc6) [000..202) =============== Generating BB18 [0B0..0B4) -> BB20 (always), preds={BB17} succs={BB20} flags=0x00000000.40080020: i gcsafe LIR BB18 IN (9)={V01 V02 V13 V52 V53 V10 V08 V03 V09 } + ByrefExposed + GcHeap OUT(9)={V01 V02 V13 V52 V53 V08 V03 V09 V32} + ByrefExposed + GcHeap Recording Var Locations at start of BB18 V01(rsi) V02(rdi) V13(r15) V52(rbx) V53(rbp) V08(r12) V03(r14) V09(r13) Liveness not changing: 0000000C0280003D {V01 V02 V03 V08 V09 V10 V13 V52 V53} Live regs: 00000000 {} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} GC regs: 00000000 {} => 00000048 {rbx rsi} Byref regs: 00000000 {} => 00000080 {rdi} L_M6661_BB18: Scope info: begin block BB18, IL range [0B0..0B4) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 10 (V10 loc7) [000..202) 8 (V08 loc5) [000..202) 3 (V03 loc0) [000..202) 9 (V09 loc6) [000..202) Added IP mapping: 0x00B0 STACK_EMPTY (G_M6661_IG15,ins#2,ofs#8) label Generating: N413 (???,???) [000931] ------------ IL_OFFSET void IL offset: 0xb0 REG NA Generating: N415 ( 1, 1) [000376] -----------z t376 = LCL_VAR int V10 loc7 u:2 rax (last use) REG rax /--* t376 int Generating: N417 ( 5, 4) [000378] DA---------- * STORE_LCL_VAR int V32 tmp2 d:4 rdx REG rdx IN0055: mov eax, dword ptr [V10 rsp+E4H] V10 in reg rax is becoming live [000376] Live regs: 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0E9 {rax rbx rbp rsi rdi r12 r13 r14 r15} V10 in reg rax is becoming dead [000376] Live regs: 0000F0E9 {rax rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V01 V02 V03 V08 V09 V10 V13 V52 V53} => {V01 V02 V03 V08 V09 V13 V52 V53} IN0056: mov edx, eax V32 in reg rdx is becoming live [000378] Live regs: 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0EC {rdx rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V01 V02 V03 V08 V09 V13 V52 V53} => {V01 V02 V03 V08 V09 V13 V32 V52 V53} Scope info: end block BB18, IL range [0B0..0B4) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 8 (V08 loc5) [000..202) 3 (V03 loc0) [000..202) 9 (V09 loc6) [000..202) IN0057: jmp L_M6661_BB20 =============== Generating BB19 [0B4..0BE), preds={BB17} succs={BB20} flags=0x00000000.400b0020: i label target gcsafe LIR BB19 IN (9)={V01 V02 V13 V52 V53 V10 V08 V03 V09 } + ByrefExposed + GcHeap OUT(9)={V01 V02 V13 V52 V53 V08 V03 V09 V32} + ByrefExposed + GcHeap Recording Var Locations at start of BB19 V01(rsi) V02(rdi) V13(r15) V52(rbx) V53(rbp) V10(rax->STK) V08(r12) V03(r14) V09(r13) Change life 0000040C0200003D {V01 V02 V03 V08 V09 V13 V32 V52 V53} -> 0000000C0280003D {V01 V02 V03 V08 V09 V10 V13 V52 V53} V32 in reg rdx is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: 00000000 {} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} GC regs: 00000000 {} => 00000048 {rbx rsi} Byref regs: 00000000 {} => 00000080 {rdi} L_M6661_BB19: G_M6661_IG15: ; offs=00035BH, funclet=00, bbWeight=0.50 Label: IG16, GCvars=0000000000000000 {}, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi} Scope info: begin block BB19, IL range [0B4..0BE) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 8 (V08 loc5) [000..202) 3 (V03 loc0) [000..202) 9 (V09 loc6) [000..202) 10 (V10 loc7) [000..202) Added IP mapping: 0x00B4 STACK_EMPTY (G_M6661_IG16,ins#0,ofs#0) label Generating: N421 (???,???) [000932] ------------ IL_OFFSET void IL offset: 0xb4 REG NA Generating: N423 ( 1, 1) [000101] -----------z t101 = LCL_VAR int V10 loc7 u:2 rax (last use) REG rax Generating: N425 ( 1, 1) [000104] ------------ t104 = LCL_VAR int V53 tmp23 u:2 rbp REG rbp /--* t101 int +--* t104 int Generating: N427 ( 3, 3) [000106] ----G------- t106 = * SUB int REG rdx IN0058: mov eax, dword ptr [V10 rsp+E4H] V10 in reg rax is becoming live [000101] Live regs: 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0E9 {rax rbx rbp rsi rdi r12 r13 r14 r15} V10 in reg rax is becoming dead [000101] Live regs: 0000F0E9 {rax rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V01 V02 V03 V08 V09 V10 V13 V52 V53} => {V01 V02 V03 V08 V09 V13 V52 V53} IN0059: mov edx, eax IN005a: sub edx, ebp /--* t106 int Generating: N429 ( 7, 6) [000108] DA--G------- * STORE_LCL_VAR int V32 tmp2 d:3 rdx REG rdx V32 in reg rdx is becoming live [000108] Live regs: 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0EC {rdx rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V01 V02 V03 V08 V09 V13 V52 V53} => {V01 V02 V03 V08 V09 V13 V32 V52 V53} Scope info: end block BB19, IL range [0B4..0BE) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 8 (V08 loc5) [000..202) 3 (V03 loc0) [000..202) 9 (V09 loc6) [000..202) =============== Generating BB20 [0BE..0C4) -> BB45 (cond), preds={BB18,BB19} succs={BB21,BB45} flags=0x00000000.400b0020: i label target gcsafe LIR BB20 IN (9)={V01 V02 V13 V52 V53 V08 V03 V09 V32} + ByrefExposed + GcHeap OUT(9)={V01 V02 V13 V52 V53 V08 V03 V09 V14 } + ByrefExposed + GcHeap Recording Var Locations at start of BB20 V01(rsi) V02(rdi) V13(r15) V52(rbx) V53(rbp) V08(r12) V03(r14) V09(r13) V32(rdx) Liveness not changing: 0000040C0200003D {V01 V02 V03 V08 V09 V13 V32 V52 V53} Live regs: 00000000 {} => 0000F0EC {rdx rbx rbp rsi rdi r12 r13 r14 r15} GC regs: 00000000 {} => 00000048 {rbx rsi} Byref regs: 00000000 {} => 00000080 {rdi} L_M6661_BB20: G_M6661_IG16: ; offs=000371H, funclet=00, bbWeight=0.50 Label: IG17, GCvars=0000000000000000 {}, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi} Scope info: begin block BB20, IL range [0BE..0C4) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 8 (V08 loc5) [000..202) 3 (V03 loc0) [000..202) 9 (V09 loc6) [000..202) Generating: N433 ( 3, 2) [000110] ------------ t110 = LCL_VAR int V32 tmp2 u:2 rdx (last use) REG rdx $244 /--* t110 int Generating: N435 ( 7, 5) [000112] DA---------- * STORE_LCL_VAR int V14 loc11 d:2 rax REG rax V32 in reg rdx is becoming dead [000110] Live regs: 0000F0EC {rdx rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V01 V02 V03 V08 V09 V13 V32 V52 V53} => {V01 V02 V03 V08 V09 V13 V52 V53} IN005b: mov eax, edx V14 in reg rax is becoming live [000112] Live regs: 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0E9 {rax rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V01 V02 V03 V08 V09 V13 V52 V53} => {V01 V02 V03 V08 V09 V13 V14 V52 V53} Added IP mapping: 0x00C0 STACK_EMPTY (G_M6661_IG17,ins#1,ofs#2) label Generating: N437 (???,???) [000933] ------------ IL_OFFSET void IL offset: 0xc0 REG NA Generating: N439 ( 1, 1) [000113] ------------ t113 = LCL_VAR int V13 loc10 u:2 r15 REG r15 $293 Generating: N441 ( 1, 1) [000114] -c---------- t114 = CNS_INT int 0 REG NA $40 /--* t113 int +--* t114 int Generating: N443 ( 3, 3) [000115] J------N---- * NE void REG NA $35a IN005c: test r15d, r15d Generating: N445 ( 5, 5) [000116] ------------ * JTRUE void REG NA IN005d: jne L_M6661_BB45 Scope info: end block BB20, IL range [0BE..0C4) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 8 (V08 loc5) [000..202) 3 (V03 loc0) [000..202) 9 (V09 loc6) [000..202) =============== Generating BB21 [0C4..0D9) -> BB23 (cond), preds={BB20} succs={BB22,BB23} flags=0x00000004.40280020: i hascall gcsafe idxlen LIR BB21 IN (9)={V01 V02 V13 V52 V53 V08 V03 V09 V14} + ByrefExposed + GcHeap OUT(9)={V01 V02 V13 V52 V53 V08 V03 V09 V14} + ByrefExposed + GcHeap Recording Var Locations at start of BB21 V01(rsi) V02(rdi) V13(r15) V52(rbx) V53(rbp) V08(r12) V03(r14) V09(r13) V14(rax) Liveness not changing: 0000001C0200003D {V01 V02 V03 V08 V09 V13 V14 V52 V53} Live regs: 00000000 {} => 0000F0E9 {rax rbx rbp rsi rdi r12 r13 r14 r15} GC regs: 00000000 {} => 00000048 {rbx rsi} Byref regs: 00000000 {} => 00000080 {rdi} L_M6661_BB21: Scope info: begin block BB21, IL range [0C4..0D9) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 8 (V08 loc5) [000..202) 3 (V03 loc0) [000..202) 9 (V09 loc6) [000..202) 14 (V14 loc11) [000..202) Generating: N449 ( 1, 1) [000455] ------------ t455 = LCL_VAR ref V52 tmp22 u:2 rbx REG rbx /--* t455 ref Generating: N451 (???,???) [000994] -c---------- t994 = * LEA(b+8) ref REG NA /--* t994 ref Generating: N453 ( 3, 3) [000456] ---XG------- t456 = * IND int REG rcx IN005e: mov ecx, dword ptr [rbx+8] /--* t456 int Generating: N455 ( 4, 5) [000358] ---XG------- t358 = * CAST long <- int REG rcx IN005f: movsxd rcx, ecx Generating: N457 ( 3, 2) [000352] -----------Z t352 = LCL_VAR int V14 loc11 u:2 rax REG rax $244 /--* t352 int Generating: N459 ( 4, 4) [000353] ---------U-- t353 = * CAST long <- ulong <- uint REG rdx $486 IN0060: mov dword ptr [V14 rsp+C4H], eax V14 in reg rax is becoming dead [000352] Live regs: 0000F0E9 {rax rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} IN0061: mov edx, eax /--* t353 long +--* t358 long Generating: N461 ( 9, 10) [000359] ---XG------- t359 = * SUB long REG rdx IN0062: sub rdx, rcx /--* t359 long Generating: N463 ( 13, 13) [000363] DA-XG------- * STORE_LCL_VAR long V38 tmp8 d:2 NA REG NA IN0063: mov qword ptr [V38 rsp+78H], rdx Live vars: {V01 V02 V03 V08 V09 V13 V14 V52 V53} => {V01 V02 V03 V08 V09 V13 V14 V38 V52 V53} Generating: N465 ( 1, 1) [000360] ------------ t360 = LCL_VAR ref V01 arg1 u:1 rsi REG rsi $c0 /--* t360 ref Generating: N467 (???,???) [001033] ------------ t1033 = * PUTARG_REG ref REG rcx IN0064: mov rcx, rsi GC regs: 00000048 {rbx rsi} => 0000004A {rcx rbx rsi} /--* t1033 ref this in rcx Generating: N469 ( 15, 8) [000361] --CXG------- t361 = * CALL int FloatingPointType.get_OverflowDecimalExponent REG rax $298 GC regs: 0000004A {rcx rbx rsi} => 00000048 {rbx rsi} Call: GCvars=0000000000000000 {}, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi} IN0065: call FloatingPointType:get_OverflowDecimalExponent():int:this /--* t361 int Generating: N471 ( 16, 10) [000366] ---XG------- t366 = * CAST long <- int REG rcx $48b IN0066: movsxd rcx, eax Generating: N473 ( 3, 2) [000364] -c---------- t364 = LCL_VAR long V38 tmp8 u:2 NA (last use) REG NA /--* t366 long +--* t364 long Generating: N475 ( 20, 13) [000367] J--XG--N---- * GE void REG NA Live vars: {V01 V02 V03 V08 V09 V13 V14 V38 V52 V53} => {V01 V02 V03 V08 V09 V13 V14 V52 V53} IN0067: cmp rcx, qword ptr [V38 rsp+78H] Generating: N477 ( 22, 15) [000368] ---XG------- * JTRUE void REG NA IN0068: jge L_M6661_BB23 Scope info: end block BB21, IL range [0C4..0D9) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 8 (V08 loc5) [000..202) 3 (V03 loc0) [000..202) 9 (V09 loc6) [000..202) 14 (V14 loc11) [000..202) =============== Generating BB22 [0D9..0E3) (return), preds={BB21} succs={} flags=0x00000004.40080020: i hascall gcsafe LIR BB22 IN (2)={V01 V02} + ByrefExposed + GcHeap OUT(0)={ } Recording Var Locations at start of BB22 V01(rsi) V02(rdi) Change life 0000001C0200003D {V01 V02 V03 V08 V09 V13 V14 V52 V53} -> 0000000000000005 {V01 V02} V13 in reg r15 is becoming dead [------] Live regs: (unchanged) 00000000 {} V52 in reg rbx is becoming dead [------] Live regs: (unchanged) 00000000 {} V53 in reg rbp is becoming dead [------] Live regs: (unchanged) 00000000 {} V08 in reg r12 is becoming dead [------] Live regs: (unchanged) 00000000 {} V03 in reg r14 is becoming dead [------] Live regs: (unchanged) 00000000 {} V09 in reg r13 is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: 00000000 {} => 000000C0 {rsi rdi} GC regs: 00000000 {} => 00000040 {rsi} Byref regs: 00000000 {} => 00000080 {rdi} L_M6661_BB22: Scope info: begin block BB22, IL range [0D9..0E3) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) Added IP mapping: 0x00D9 STACK_EMPTY (G_M6661_IG17,ins#14,ofs#56) label Generating: N481 (???,???) [000934] ------------ IL_OFFSET void IL offset: 0xd9 REG NA Generating: N483 ( 1, 1) [000370] ------------ t370 = LCL_VAR ref V01 arg1 u:1 rsi REG rsi $c0 /--* t370 ref Generating: N485 (???,???) [001034] ------------ t1034 = * PUTARG_REG ref REG rcx IN0069: mov rcx, rsi GC regs: 00000040 {rsi} => 00000042 {rcx rsi} Generating: N487 ( 1, 1) [001035] ------------ t1035 = LCL_VAR ref V01 arg1 rsi (last use) REG rsi /--* t1035 ref Generating: N489 ( 2, 2) [001036] -c---------- t1036 = * LEA(b+0) byref REG NA /--* t1036 byref Generating: N491 ( 5, 4) [001037] ------------ t1037 = * IND long REG rax V01 in reg rsi is becoming dead [001035] Live regs: 000000C0 {rsi rdi} => 00000080 {rdi} Live vars: {V01 V02} => {V02} GC regs: 00000042 {rcx rsi} => 00000002 {rcx} IN006a: mov rax, qword ptr [rsi] /--* t1037 long Generating: N493 ( 6, 5) [001038] -c---------- t1038 = * LEA(b+80) long REG NA /--* t1038 long Generating: N495 ( 9, 7) [001039] ------------ t1039 = * IND long REG rax IN006b: mov rax, qword ptr [rax+80] /--* t1039 long Generating: N497 ( 10, 8) [001040] -c---------- t1040 = * LEA(b+0) long REG NA /--* t1040 long Generating: N499 ( 13, 10) [001041] -c---------- t1041 = * IND long REG NA /--* t1034 ref this in rcx +--* t1041 long control expr Generating: N501 ( 21, 10) [000371] --CXG------- t371 = * CALLV ind long FloatingPointType.get_Zero REG rax $457 GC regs: 00000002 {rcx} => 00000000 {} Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000080 {rdi} IN006c: call qword ptr [rax]FloatingPointType:get_Zero():long:this Generating: N503 ( 1, 1) [000369] ------------ t369 = LCL_VAR byref V02 arg2 u:1 rdi (last use) REG rdi $81 /--* t369 byref +--* t371 long Generating: N505 (???,???) [000935] -ACXG------- * STOREIND long REG NA V02 in reg rdi is becoming dead [000369] Live regs: 00000080 {rdi} => 00000000 {} Live vars: {V02} => {} Byref regs: 00000080 {rdi} => 00000000 {} IN006d: mov qword ptr [rdi], rax Generating: N507 ( 1, 1) [000374] ------------ t374 = CNS_INT int 2 REG rax $42 IN006e: mov eax, 2 /--* t374 int Generating: N509 ( 2, 2) [000524] ------------ * RETURN int REG NA $5c4 Scope info: end block BB22, IL range [0D9..0E3) Scope info: open scopes = Added IP mapping: EPILOG STACK_EMPTY (G_M6661_IG17,ins#20,ofs#76) label Reserving epilog IG for block BB22 G_M6661_IG17: ; offs=00037CH, funclet=00, bbWeight=0.50 *************** After placeholder IG creation G_M6661_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG G_M6661_IG02: ; offs=000000H, size=0006H, gcrefRegs=00000040 {rsi}, byrefRegs=00000082 {rcx rdi}, byref G_M6661_IG03: ; offs=000006H, size=000AH, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG04: ; offs=000010H, size=0014H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG05: ; epilog placeholder, next placeholder=IG11 , BB03 [0001], epilog, extend <-- First placeholder ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000048 {rbx rsi}, PrevByrefRegs=00000080 {rdi} ; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000040 {rsi}, InitByrefRegs=00000080 {rdi} G_M6661_IG06: ; offs=000124H, size=0028H, gcVars=0000000000000000 {}, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, gcvars, byref G_M6661_IG07: ; offs=00014CH, size=0003H, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG08: ; offs=00014FH, size=0012H, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG09: ; offs=000161H, size=0003H, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG10: ; offs=000164H, size=006CH, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG11: ; epilog placeholder, next placeholder=IG18 , BB12 [0004], epilog, extend ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000048 {rbx rsi}, PrevByrefRegs=00000080 {rdi} ; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000048 {rbx rsi}, InitByrefRegs=00000080 {rdi} G_M6661_IG12: ; offs=0002D0H, size=0010H, gcVars=0000000000000000 {}, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, gcvars, byref G_M6661_IG13: ; offs=0002E0H, size=004EH, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG14: ; offs=00032EH, size=002DH, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG15: ; offs=00035BH, size=0016H, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG16: ; offs=000371H, size=000BH, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG17: ; offs=00037CH, size=004CH, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG18: ; epilog placeholder, next placeholder=, BB22 [0014], epilog, extend <-- Last placeholder ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000048 {rbx rsi}, PrevByrefRegs=00000080 {rdi} ; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000048 {rbx rsi}, InitByrefRegs=00000080 {rdi} G_M6661_IG19: ; offs=0004C8H, size=0000H, gcrefRegs=00000000 {} <-- Current IG =============== Generating BB45 [???..???) -> BB23 (always), preds={BB20} succs={BB23} flags=0x00000000.40020040: internal target LIR BB45 IN (9)={V01 V02 V13 V52 V53 V08 V03 V09 V14} OUT(9)={V01 V02 V13 V52 V53 V08 V03 V09 V14} Recording Var Locations at start of BB45 V01(rsi) V02(rdi) V13(r15) V52(rbx) V53(rbp) V08(r12) V03(r14) V09(r13) V14(STK->rax) Change life 0000000000000000 {} -> 0000001C0200003D {V01 V02 V03 V08 V09 V13 V14 V52 V53} V01 in reg rsi is becoming live [------] Live regs: 00000000 {} => 00000040 {rsi} V02 in reg rdi is becoming live [------] Live regs: 00000040 {rsi} => 000000C0 {rsi rdi} V13 in reg r15 is becoming live [------] Live regs: 000000C0 {rsi rdi} => 000080C0 {rsi rdi r15} V52 in reg rbx is becoming live [------] Live regs: 000080C0 {rsi rdi r15} => 000080C8 {rbx rsi rdi r15} V53 in reg rbp is becoming live [------] Live regs: 000080C8 {rbx rsi rdi r15} => 000080E8 {rbx rbp rsi rdi r15} V08 in reg r12 is becoming live [------] Live regs: 000080E8 {rbx rbp rsi rdi r15} => 000090E8 {rbx rbp rsi rdi r12 r15} V03 in reg r14 is becoming live [------] Live regs: 000090E8 {rbx rbp rsi rdi r12 r15} => 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} V09 in reg r13 is becoming live [------] Live regs: 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} V14 in reg rax is becoming live [------] Live regs: 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0E9 {rax rbx rbp rsi rdi r12 r13 r14 r15} Live regs: (unchanged) 0000F0E9 {rax rbx rbp rsi rdi r12 r13 r14 r15} GC regs: (unchanged) 00000048 {rbx rsi} Byref regs: (unchanged) 00000080 {rdi} L_M6661_BB45: Label: IG19, GCvars=0000000000000000 {}, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi} Scope info: begin block BB45, IL range [???..???) Scope info: ignoring block beginning Added IP mapping: NO_MAP STACK_EMPTY (G_M6661_IG19,ins#0,ofs#0) label Generating: N001 ( 3, 2) [001078] -----------Z t1078 = LCL_VAR int V14 loc11 rax REG rax IN006f: mov dword ptr [V14 rsp+C4H], eax V14 in reg rax is becoming dead [001078] Live regs: 0000F0E9 {rax rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} Scope info: end block BB45, IL range [???..???) Scope info: ignoring block end IN0070: jmp L_M6661_BB23 =============== Generating BB23 [0E3..117) -> BB25 (cond), preds={BB45,BB21} succs={BB24,BB25} flags=0x00000004.400b0020: i label target hascall gcsafe LIR BB23 IN (9)={V01 V02 V13 V52 V53 V08 V03 V09 V14 } + ByrefExposed + GcHeap OUT(6)={V01 V02 V13 V03 V17 V18} + ByrefExposed + GcHeap Recording Var Locations at start of BB23 V01(rsi) V02(rdi) V13(r15) V52(rbx) V53(rbp) V08(r12) V03(r14) V09(r13) Liveness not changing: 0000001C0200003D {V01 V02 V03 V08 V09 V13 V14 V52 V53} Live regs: 00000000 {} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} GC regs: 00000000 {} => 00000048 {rbx rsi} Byref regs: 00000000 {} => 00000080 {rdi} L_M6661_BB23: G_M6661_IG19: ; offs=0004C8H, funclet=00, bbWeight=0.25 Label: IG20, GCvars=0000000000000000 {}, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi} Scope info: begin block BB23, IL range [0E3..117) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 8 (V08 loc5) [000..202) 3 (V03 loc0) [000..202) 9 (V09 loc6) [000..202) 14 (V14 loc11) [000..202) Generating: N513 ( 3, 2) [000124] -------N---- t124 = LCL_VAR_ADDR byref V15 loc12 rcx * ref V15._bits (offs=0x00) -> V56 tmp26 * int V15._sign (offs=0x08) -> V57 tmp27 REG rcx IN0071: lea rcx, bword ptr [V15 rsp+B0H] Byref regs: 00000080 {rdi} => 00000082 {rcx rdi} /--* t124 byref Generating: N515 ( 7, 6) [000623] DA--------L- * STORE_LCL_VAR long V79 tmp49 d:2 rcx REG rcx Byref regs: 00000082 {rcx rdi} => 00000080 {rdi} V79 in reg rcx is becoming live [000623] Live regs: 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V01 V02 V03 V08 V09 V13 V14 V52 V53} => {V01 V02 V03 V08 V09 V13 V14 V52 V53 V79} Generating: N517 ( 3, 2) [000607] -------N---- t607 = LCL_VAR_ADDR byref V73 tmp43 rdx REG rdx IN0072: lea rdx, bword ptr [V73 rsp+48H] Byref regs: 00000080 {rdi} => 00000084 {rdx rdi} /--* t607 byref Generating: N519 ( 3, 3) [000609] DA---------- * STORE_LCL_VAR byref V78 tmp48 d:2 rdx REG rdx Byref regs: 00000084 {rdx rdi} => 00000080 {rdi} V78 in reg rdx is becoming live [000609] Live regs: 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0EE {rcx rdx rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V01 V02 V03 V08 V09 V13 V14 V52 V53 V79} => {V01 V02 V03 V08 V09 V13 V14 V52 V53 V78 V79} Byref regs: 00000080 {rdi} => 00000084 {rdx rdi} Generating: N521 ( 1, 1) [000610] ------------ t610 = LCL_VAR byref V78 tmp48 u:2 rdx Zero Fseq[Mantissa] REG rdx $409 Generating: N523 ( 1, 1) [000612] -------N---- t612 = LCL_VAR ref V52 tmp22 u:2 rbx (last use) REG rbx /--* t610 byref +--* t612 ref Generating: N525 (???,???) [000936] -A---------- * STOREIND ref REG NA V52 in reg rbx is becoming dead [000612] Live regs: 0000F0EE {rcx rdx rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0E6 {rcx rdx rbp rsi rdi r12 r13 r14 r15} Live vars: {V01 V02 V03 V08 V09 V13 V14 V52 V53 V78 V79} => {V01 V02 V03 V08 V09 V13 V14 V53 V78 V79} GC regs: 00000048 {rbx rsi} => 00000040 {rsi} IN0073: mov gword ptr [rdx], rbx Generating: N527 ( 1, 1) [000615] ------------ t615 = LCL_VAR byref V78 tmp48 u:2 rdx (last use) REG rdx $409 /--* t615 byref Generating: N529 ( 2, 2) [000617] -c---------- t617 = * LEA(b+8) byref REG NA Generating: N531 ( 1, 1) [000619] -------N---- t619 = LCL_VAR int V53 tmp23 u:2 rbp (last use) REG rbp /--* t617 byref +--* t619 int Generating: N533 (???,???) [000937] -A--------L- * STOREIND int REG NA V78 in reg rdx is becoming dead [000615] Live regs: 0000F0E6 {rcx rdx rbp rsi rdi r12 r13 r14 r15} => 0000F0E2 {rcx rbp rsi rdi r12 r13 r14 r15} Live vars: {V01 V02 V03 V08 V09 V13 V14 V53 V78 V79} => {V01 V02 V03 V08 V09 V13 V14 V53 V79} Byref regs: 00000084 {rdx rdi} => 00000080 {rdi} V53 in reg rbp is becoming dead [000619] Live regs: 0000F0E2 {rcx rbp rsi rdi r12 r13 r14 r15} => 0000F0C2 {rcx rsi rdi r12 r13 r14 r15} Live vars: {V01 V02 V03 V08 V09 V13 V14 V53 V79} => {V01 V02 V03 V08 V09 V13 V14 V79} IN0074: mov dword ptr [rdx+8], ebp Generating: N535 ( 3, 2) [000624] ------------ t624 = LCL_VAR long V79 tmp49 u:2 rcx (last use) REG rcx $408 /--* t624 long Generating: N537 (???,???) [001042] ------------ t1042 = * PUTARG_REG long REG rcx V79 in reg rcx is becoming dead [000624] Live regs: 0000F0C2 {rcx rsi rdi r12 r13 r14 r15} => 0000F0C0 {rsi rdi r12 r13 r14 r15} Live vars: {V01 V02 V03 V08 V09 V13 V14 V79} => {V01 V02 V03 V08 V09 V13 V14} Generating: N539 ( 3, 2) [000625] -------N---- t625 = LCL_VAR_ADDR byref V73 tmp43 rdx REG rdx IN0075: lea rdx, bword ptr [V73 rsp+48H] Byref regs: 00000080 {rdi} => 00000084 {rdx rdi} /--* t625 byref Generating: N541 (???,???) [001043] ------------ t1043 = * PUTARG_REG byref REG rdx Byref regs: 00000084 {rdx rdi} => 00000080 {rdi} Byref regs: 00000080 {rdi} => 00000084 {rdx rdi} Generating: N543 ( 3, 2) [000118] ------------ t118 = LCL_VAR int V08 loc5 u:2 r12 (last use) REG r12 $242 /--* t118 int Generating: N545 (???,???) [001044] ------------ t1044 = * PUTARG_REG int REG r8 V08 in reg r12 is becoming dead [000118] Live regs: 0000F0C0 {rsi rdi r12 r13 r14 r15} => 0000E0C0 {rsi rdi r13 r14 r15} Live vars: {V01 V02 V03 V08 V09 V13 V14} => {V01 V02 V03 V09 V13 V14} IN0076: mov r8d, r12d Generating: N547 ( 3, 2) [000119] ------------ t119 = LCL_VAR int V09 loc6 u:2 r13 (last use) REG r13 /--* t119 int Generating: N549 (???,???) [001045] ------------ t1045 = * PUTARG_REG int REG r9 V09 in reg r13 is becoming dead [000119] Live regs: 0000E0C0 {rsi rdi r13 r14 r15} => 0000C0C0 {rsi rdi r14 r15} Live vars: {V01 V02 V03 V09 V13 V14} => {V01 V02 V03 V13 V14} IN0077: mov r9d, r13d /--* t1042 long arg0 in rcx +--* t1043 byref arg1 in rdx +--* t1044 int arg2 in r8 +--* t1045 int arg3 in r9 Generating: N551 ( 53, 37) [000120] S-CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.AccumulateDecimalDigitsIntoBigInteger REG NA $VN.Void Byref regs: 00000084 {rdx rdi} => 00000080 {rdi} Call: GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi} IN0078: call Microsoft.CodeAnalysis.RealParser:AccumulateDecimalDigitsIntoBigInteger(DecimalFloatingPointString,int,int):System.Numerics.BigInteger Added IP mapping: 0x00EF STACK_EMPTY (G_M6661_IG20,ins#8,ofs#35) label Generating: N553 (???,???) [000938] ------------ IL_OFFSET void IL offset: 0xef REG NA Generating: N555 ( 2, 10) [000131] ------------ t131 = CNS_INT long 0x7ff815262aa0 REG rcx $102 IN0079: mov rcx, 0xD1FFAB1E /--* t131 long Generating: N557 (???,???) [001046] ------------ t1046 = * PUTARG_REG long REG rcx Generating: N559 ( 1, 4) [000132] ------------ t132 = CNS_INT int 173 REG rdx $58 IN007a: mov edx, 173 /--* t132 int Generating: N561 (???,???) [001047] ------------ t1047 = * PUTARG_REG int REG rdx /--* t1046 long arg0 in rcx +--* t1047 int arg1 in rdx Generating: N563 ( 17, 21) [000133] H-CXG------- t133 = * CALL help long HELPER.CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE REG rax $48d Call: GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi} IN007b: call CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE Generating: N565 ( 2, 10) [000634] I----------- t634 = CNS_INT(h) long 0xd1ffab1e static Fseq[BigOne] REG rcx $4c2 IN007c: mov rcx, 0xD1FFAB1E /--* t634 long Generating: N567 ( 4, 12) [000633] n---G------- t633 = * IND ref REG rcx IN007d: mov rcx, gword ptr [rcx] GC regs: 00000040 {rsi} => 00000042 {rcx rsi} Generating: N569 ( 1, 1) [000635] -c---------- t635 = CNS_INT long 8 Fseq[#FirstElem] REG NA $101 /--* t633 ref +--* t635 long Generating: N571 ( 6, 14) [000632] ----G------- t632 = * ADD byref REG rcx GC regs: 00000042 {rcx rsi} => 00000040 {rsi} IN007e: add rcx, 8 Byref regs: 00000080 {rdi} => 00000082 {rcx rdi} /--* t632 byref Generating: N573 ( 6, 14) [000637] DA--G------- * STORE_LCL_VAR byref V80 tmp50 d:2 rcx REG rcx Byref regs: 00000082 {rcx rdi} => 00000080 {rdi} V80 in reg rcx is becoming live [000637] Live regs: 0000C0C0 {rsi rdi r14 r15} => 0000C0C2 {rcx rsi rdi r14 r15} Live vars: {V01 V02 V03 V13 V14} => {V01 V02 V03 V13 V14 V80} Byref regs: 00000080 {rdi} => 00000082 {rcx rdi} Generating: N575 ( 1, 1) [000639] ------------ t639 = LCL_VAR byref V80 tmp50 u:2 rcx Zero Fseq[_bits] REG rcx /--* t639 byref Generating: N577 ( 3, 2) [000640] ---X-------- t640 = * IND ref REG rdx IN007f: mov rdx, gword ptr [rcx] GC regs: 00000040 {rsi} => 00000044 {rdx rsi} /--* t640 ref Generating: N579 ( 7, 5) [000641] DA-XG------- * STORE_LCL_VAR ref (AX) V58 tmp28 NA REG NA GC regs: 00000044 {rdx rsi} => 00000040 {rsi} IN0080: mov gword ptr [V58 rsp+A0H], rdx Generating: N581 ( 1, 1) [000644] ------------ t644 = LCL_VAR byref V80 tmp50 u:2 rcx (last use) REG rcx /--* t644 byref Generating: N583 ( 2, 2) [000646] -c---------- t646 = * LEA(b+8) byref REG NA /--* t646 byref Generating: N585 ( 4, 4) [000647] ---X-------- t647 = * IND int REG rcx V80 in reg rcx is becoming dead [000644] Live regs: 0000C0C2 {rcx rsi rdi r14 r15} => 0000C0C0 {rsi rdi r14 r15} Live vars: {V01 V02 V03 V13 V14 V80} => {V01 V02 V03 V13 V14} Byref regs: 00000082 {rcx rdi} => 00000080 {rdi} IN0081: mov ecx, dword ptr [rcx+8] /--* t647 int Generating: N587 ( 8, 7) [000648] DA-XG------- * STORE_LCL_VAR int (AX) V59 tmp29 NA REG NA IN0082: mov dword ptr [V59 rsp+A8H], ecx Added IP mapping: 0x00F6 STACK_EMPTY (G_M6661_IG20,ins#18,ofs#93) Generating: N589 (???,???) [000939] ------------ IL_OFFSET void IL offset: 0xf6 REG NA Generating: N591 ( 3, 2) [000138] -------N---- t138 = LCL_VAR_ADDR byref V16 loc13 rcx * ref V16._bits (offs=0x00) -> V58 tmp28 * int V16._sign (offs=0x08) -> V59 tmp29 REG rcx IN0083: lea rcx, bword ptr [V16 rsp+A0H] Byref regs: 00000080 {rdi} => 00000082 {rcx rdi} /--* t138 byref Generating: N593 (???,???) [001048] ------------ t1048 = * PUTARG_REG byref REG rcx Byref regs: 00000082 {rcx rdi} => 00000080 {rdi} Byref regs: 00000080 {rdi} => 00000082 {rcx rdi} Generating: N595 ( 3, 2) [000140] -----------z t140 = LCL_VAR int V14 loc11 u:2 rdx (last use) REG rdx $244 /--* t140 int Generating: N597 (???,???) [001049] ------------ t1049 = * PUTARG_REG int REG rdx IN0084: mov edx, dword ptr [V14 rsp+C4H] V14 in reg rdx is becoming live [000140] Live regs: 0000C0C0 {rsi rdi r14 r15} => 0000C0C4 {rdx rsi rdi r14 r15} V14 in reg rdx is becoming dead [000140] Live regs: 0000C0C4 {rdx rsi rdi r14 r15} => 0000C0C0 {rsi rdi r14 r15} Live vars: {V01 V02 V03 V13 V14} => {V01 V02 V03 V13} /--* t1048 byref arg0 in rcx +--* t1049 int arg1 in rdx Generating: N599 ( 20, 12) [000141] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.MultiplyByPowerOfTen REG NA $VN.Void Byref regs: 00000082 {rcx rdi} => 00000080 {rdi} Call: GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi} IN0085: call Microsoft.CodeAnalysis.RealParser:MultiplyByPowerOfTen(byref,int) Added IP mapping: 0x00FF STACK_EMPTY (G_M6661_IG20,ins#21,ofs#113) Generating: N601 (???,???) [000940] ------------ IL_OFFSET void IL offset: 0xff REG NA Generating: N603 ( 3, 2) [000653] -------N---- t653 = LCL_VAR ref (AX) V56 tmp26 rcx REG rcx $184 IN0086: mov rcx, gword ptr [V56 rsp+B0H] GC regs: 00000040 {rsi} => 00000042 {rcx rsi} /--* t653 ref Generating: N605 ( 7, 5) [000654] DA--G------- * STORE_LCL_VAR ref V64 tmp34 d:2 rcx REG rcx GC regs: 00000042 {rcx rsi} => 00000040 {rsi} V64 in reg rcx is becoming live [000654] Live regs: 0000C0C0 {rsi rdi r14 r15} => 0000C0C2 {rcx rsi rdi r14 r15} Live vars: {V01 V02 V03 V13} => {V01 V02 V03 V13 V64} GC regs: 00000040 {rsi} => 00000042 {rcx rsi} Generating: N607 ( 3, 2) [000656] -------N---- t656 = LCL_VAR int (AX) V57 tmp27 rdx REG rdx $246 IN0087: mov edx, dword ptr [V57 rsp+B8H] /--* t656 int Generating: N609 ( 7, 5) [000657] DA--G------- * STORE_LCL_VAR int V65 tmp35 d:2 rdx REG rdx V65 in reg rdx is becoming live [000657] Live regs: 0000C0C2 {rcx rsi rdi r14 r15} => 0000C0C6 {rcx rdx rsi rdi r14 r15} Live vars: {V01 V02 V03 V13 V64} => {V01 V02 V03 V13 V64 V65} genIPmappingAdd: ignoring duplicate IL offset 0xff Generating: N611 (???,???) [000941] ------------ IL_OFFSET void IL offset: 0xff REG NA Generating: N613 ( 3, 2) [000663] -------N---- t663 = LCL_VAR_ADDR byref V76 tmp46 rax REG rax IN0088: lea rax, bword ptr [V76 rsp+38H] Byref regs: 00000080 {rdi} => 00000081 {rax rdi} /--* t663 byref Generating: N615 ( 3, 3) [000665] DA---------- * STORE_LCL_VAR byref V81 tmp51 d:2 rax REG rax Byref regs: 00000081 {rax rdi} => 00000080 {rdi} V81 in reg rax is becoming live [000665] Live regs: 0000C0C6 {rcx rdx rsi rdi r14 r15} => 0000C0C7 {rax rcx rdx rsi rdi r14 r15} Live vars: {V01 V02 V03 V13 V64 V65} => {V01 V02 V03 V13 V64 V65 V81} Byref regs: 00000080 {rdi} => 00000081 {rax rdi} Generating: N617 ( 1, 1) [000666] ------------ t666 = LCL_VAR byref V81 tmp51 u:2 rax Zero Fseq[_bits] REG rax $40e Generating: N619 ( 3, 2) [000668] -------N---- t668 = LCL_VAR ref V64 tmp34 u:2 rcx (last use) REG rcx $184 /--* t666 byref +--* t668 ref Generating: N621 (???,???) [000942] -A---------- * STOREIND ref REG NA V64 in reg rcx is becoming dead [000668] Live regs: 0000C0C7 {rax rcx rdx rsi rdi r14 r15} => 0000C0C5 {rax rdx rsi rdi r14 r15} Live vars: {V01 V02 V03 V13 V64 V65 V81} => {V01 V02 V03 V13 V65 V81} GC regs: 00000042 {rcx rsi} => 00000040 {rsi} IN0089: mov gword ptr [rax], rcx Generating: N623 ( 1, 1) [000671] ------------ t671 = LCL_VAR byref V81 tmp51 u:2 rax (last use) REG rax $40e /--* t671 byref Generating: N625 ( 2, 2) [000673] -c---------- t673 = * LEA(b+8) byref REG NA Generating: N627 ( 3, 2) [000675] -------N---- t675 = LCL_VAR int V65 tmp35 u:2 rdx (last use) REG rdx $246 /--* t673 byref +--* t675 int Generating: N629 (???,???) [000943] -A--------L- * STOREIND int REG NA V81 in reg rax is becoming dead [000671] Live regs: 0000C0C5 {rax rdx rsi rdi r14 r15} => 0000C0C4 {rdx rsi rdi r14 r15} Live vars: {V01 V02 V03 V13 V65 V81} => {V01 V02 V03 V13 V65} Byref regs: 00000081 {rax rdi} => 00000080 {rdi} V65 in reg rdx is becoming dead [000675] Live regs: 0000C0C4 {rdx rsi rdi r14 r15} => 0000C0C0 {rsi rdi r14 r15} Live vars: {V01 V02 V03 V13 V65} => {V01 V02 V03 V13} IN008a: mov dword ptr [rax+8], edx Generating: N631 ( 3, 2) [000678] -------N---- t678 = LCL_VAR_ADDR byref V76 tmp46 rcx REG rcx IN008b: lea rcx, bword ptr [V76 rsp+38H] Byref regs: 00000080 {rdi} => 00000082 {rcx rdi} /--* t678 byref Generating: N633 (???,???) [001050] ------------ t1050 = * PUTARG_REG byref REG rcx Byref regs: 00000082 {rcx rdi} => 00000080 {rdi} Byref regs: 00000080 {rdi} => 00000082 {rcx rdi} Generating: N635 ( 3, 3) [000462] ------------ t462 = LCL_VAR_ADDR long V45 tmp15 rdx REG rdx $449 IN008c: lea rdx, [V45 rsp+70H] /--* t462 long Generating: N637 (???,???) [001051] ------------ t1051 = * PUTARG_REG long REG rdx /--* t1050 byref arg0 in rcx +--* t1051 long arg1 in rdx Generating: N639 ( 41, 28) [000463] --CXG------- t463 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits REG rax $29f Byref regs: 00000082 {rcx rdi} => 00000080 {rdi} Call: GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi} IN008d: call Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger,byref):int /--* t463 int Generating: N641 ( 45, 31) [000468] DA-XG------- * STORE_LCL_VAR int V43 tmp13 d:2 rbx REG rbx IN008e: mov ebx, eax V43 in reg rbx is becoming live [000468] Live regs: 0000C0C0 {rsi rdi r14 r15} => 0000C0C8 {rbx rsi rdi r14 r15} Live vars: {V01 V02 V03 V13} => {V01 V02 V03 V13 V43} genIPmappingAdd: ignoring duplicate IL offset 0xff Generating: N643 (???,???) [000944] ------------ IL_OFFSET void IL offset: 0xff REG NA Generating: N645 ( 1, 1) [000473] ------------ t473 = CNS_INT ref null REG rcx $VN.Null IN008f: xor rcx, rcx GC regs: 00000040 {rsi} => 00000042 {rcx rsi} /--* t473 ref Generating: N647 ( 5, 4) [000475] DA--G------- * STORE_LCL_VAR ref (AX) V45 tmp15 NA REG NA GC regs: 00000042 {rcx rsi} => 00000040 {rsi} IN0090: mov gword ptr [V45 rsp+70H], rcx Generating: N649 ( 3, 2) [000469] ------------ t469 = LCL_VAR int V43 tmp13 u:2 rbx (last use) REG rbx $29f /--* t469 int Generating: N651 ( 7, 5) [000148] DA---------- * STORE_LCL_VAR int V17 loc14 d:2 rbx REG rbx V43 in reg rbx is becoming dead [000469] Live regs: 0000C0C8 {rbx rsi rdi r14 r15} => 0000C0C0 {rsi rdi r14 r15} Live vars: {V01 V02 V03 V13 V43} => {V01 V02 V03 V13} V17 in reg rbx is becoming live [000148] Live regs: 0000C0C0 {rsi rdi r14 r15} => 0000C0C8 {rbx rsi rdi r14 r15} Live vars: {V01 V02 V03 V13} => {V01 V02 V03 V13 V17} Added IP mapping: 0x0108 STACK_EMPTY (G_M6661_IG20,ins#32,ofs#163) Generating: N653 (???,???) [000945] ------------ IL_OFFSET void IL offset: 0x108 REG NA Generating: N655 ( 3, 2) [000682] -------N---- t682 = LCL_VAR ref (AX) V58 tmp28 rcx REG rcx $185 IN0091: mov rcx, gword ptr [V58 rsp+A0H] GC regs: 00000040 {rsi} => 00000042 {rcx rsi} /--* t682 ref Generating: N657 ( 7, 5) [000683] DA--G------- * STORE_LCL_VAR ref V66 tmp36 d:2 rcx REG rcx GC regs: 00000042 {rcx rsi} => 00000040 {rsi} V66 in reg rcx is becoming live [000683] Live regs: 0000C0C8 {rbx rsi rdi r14 r15} => 0000C0CA {rcx rbx rsi rdi r14 r15} Live vars: {V01 V02 V03 V13 V17} => {V01 V02 V03 V13 V17 V66} GC regs: 00000040 {rsi} => 00000042 {rcx rsi} Generating: N659 ( 3, 2) [000685] -------N---- t685 = LCL_VAR int (AX) V59 tmp29 rdx REG rdx $247 IN0092: mov edx, dword ptr [V59 rsp+A8H] /--* t685 int Generating: N661 ( 7, 5) [000686] DA--G------- * STORE_LCL_VAR int V67 tmp37 d:2 rdx REG rdx V67 in reg rdx is becoming live [000686] Live regs: 0000C0CA {rcx rbx rsi rdi r14 r15} => 0000C0CE {rcx rdx rbx rsi rdi r14 r15} Live vars: {V01 V02 V03 V13 V17 V66} => {V01 V02 V03 V13 V17 V66 V67} genIPmappingAdd: ignoring duplicate IL offset 0x108 Generating: N663 (???,???) [000946] ------------ IL_OFFSET void IL offset: 0x108 REG NA Generating: N665 ( 3, 2) [000692] -------N---- t692 = LCL_VAR_ADDR byref V76 tmp46 rax REG rax IN0093: lea rax, bword ptr [V76 rsp+38H] Byref regs: 00000080 {rdi} => 00000081 {rax rdi} /--* t692 byref Generating: N667 ( 3, 3) [000694] DA---------- * STORE_LCL_VAR byref V82 tmp52 d:2 rax REG rax Byref regs: 00000081 {rax rdi} => 00000080 {rdi} V82 in reg rax is becoming live [000694] Live regs: 0000C0CE {rcx rdx rbx rsi rdi r14 r15} => 0000C0CF {rax rcx rdx rbx rsi rdi r14 r15} Live vars: {V01 V02 V03 V13 V17 V66 V67} => {V01 V02 V03 V13 V17 V66 V67 V82} Byref regs: 00000080 {rdi} => 00000081 {rax rdi} Generating: N669 ( 1, 1) [000695] ------------ t695 = LCL_VAR byref V82 tmp52 u:2 rax Zero Fseq[_bits] REG rax $411 Generating: N671 ( 3, 2) [000697] -------N---- t697 = LCL_VAR ref V66 tmp36 u:2 rcx (last use) REG rcx $185 /--* t695 byref +--* t697 ref Generating: N673 (???,???) [000947] -A---------- * STOREIND ref REG NA V66 in reg rcx is becoming dead [000697] Live regs: 0000C0CF {rax rcx rdx rbx rsi rdi r14 r15} => 0000C0CD {rax rdx rbx rsi rdi r14 r15} Live vars: {V01 V02 V03 V13 V17 V66 V67 V82} => {V01 V02 V03 V13 V17 V67 V82} GC regs: 00000042 {rcx rsi} => 00000040 {rsi} IN0094: mov gword ptr [rax], rcx Generating: N675 ( 1, 1) [000700] ------------ t700 = LCL_VAR byref V82 tmp52 u:2 rax (last use) REG rax $411 /--* t700 byref Generating: N677 ( 2, 2) [000702] -c---------- t702 = * LEA(b+8) byref REG NA Generating: N679 ( 3, 2) [000704] -------N---- t704 = LCL_VAR int V67 tmp37 u:2 rdx (last use) REG rdx $247 /--* t702 byref +--* t704 int Generating: N681 (???,???) [000948] -A--------L- * STOREIND int REG NA V82 in reg rax is becoming dead [000700] Live regs: 0000C0CD {rax rdx rbx rsi rdi r14 r15} => 0000C0CC {rdx rbx rsi rdi r14 r15} Live vars: {V01 V02 V03 V13 V17 V67 V82} => {V01 V02 V03 V13 V17 V67} Byref regs: 00000081 {rax rdi} => 00000080 {rdi} V67 in reg rdx is becoming dead [000704] Live regs: 0000C0CC {rdx rbx rsi rdi r14 r15} => 0000C0C8 {rbx rsi rdi r14 r15} Live vars: {V01 V02 V03 V13 V17 V67} => {V01 V02 V03 V13 V17} IN0095: mov dword ptr [rax+8], edx Generating: N683 ( 3, 2) [000707] -------N---- t707 = LCL_VAR_ADDR byref V76 tmp46 rcx REG rcx IN0096: lea rcx, bword ptr [V76 rsp+38H] Byref regs: 00000080 {rdi} => 00000082 {rcx rdi} /--* t707 byref Generating: N685 (???,???) [001052] ------------ t1052 = * PUTARG_REG byref REG rcx Byref regs: 00000082 {rcx rdi} => 00000080 {rdi} Byref regs: 00000080 {rdi} => 00000082 {rcx rdi} Generating: N687 ( 3, 3) [000480] ------------ t480 = LCL_VAR_ADDR long V48 tmp18 rdx REG rdx $44b IN0097: lea rdx, [V48 rsp+68H] /--* t480 long Generating: N689 (???,???) [001053] ------------ t1053 = * PUTARG_REG long REG rdx /--* t1052 byref arg0 in rcx +--* t1053 long arg1 in rdx Generating: N691 ( 41, 28) [000481] --CXG------- t481 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits REG rax $2a3 Byref regs: 00000082 {rcx rdi} => 00000080 {rdi} Call: GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi} IN0098: call Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger,byref):int /--* t481 int Generating: N693 ( 45, 31) [000486] DA-XG------- * STORE_LCL_VAR int V46 tmp16 d:2 rax REG rax V46 in reg rax is becoming live [000486] Live regs: 0000C0C8 {rbx rsi rdi r14 r15} => 0000C0C9 {rax rbx rsi rdi r14 r15} Live vars: {V01 V02 V03 V13 V17} => {V01 V02 V03 V13 V17 V46} genIPmappingAdd: ignoring duplicate IL offset 0x108 Generating: N695 (???,???) [000949] ------------ IL_OFFSET void IL offset: 0x108 REG NA Generating: N697 ( 1, 1) [000491] ------------ t491 = CNS_INT ref null REG rcx $VN.Null IN0099: xor rcx, rcx GC regs: 00000040 {rsi} => 00000042 {rcx rsi} /--* t491 ref Generating: N699 ( 5, 4) [000493] DA--G------- * STORE_LCL_VAR ref (AX) V48 tmp18 NA REG NA GC regs: 00000042 {rcx rsi} => 00000040 {rsi} IN009a: mov gword ptr [V48 rsp+68H], rcx Generating: N701 ( 3, 2) [000487] ------------ t487 = LCL_VAR int V46 tmp16 u:2 rax (last use) REG rax $2a3 /--* t487 int Generating: N703 ( 7, 5) [000155] DA---------- * STORE_LCL_VAR int V18 loc15 d:2 rax REG rax V46 in reg rax is becoming dead [000487] Live regs: 0000C0C9 {rax rbx rsi rdi r14 r15} => 0000C0C8 {rbx rsi rdi r14 r15} Live vars: {V01 V02 V03 V13 V17 V46} => {V01 V02 V03 V13 V17} V18 in reg rax is becoming live [000155] Live regs: 0000C0C8 {rbx rsi rdi r14 r15} => 0000C0C9 {rax rbx rsi rdi r14 r15} Live vars: {V01 V02 V03 V13 V17} => {V01 V02 V03 V13 V17 V18} Added IP mapping: 0x0111 STACK_EMPTY (G_M6661_IG20,ins#42,ofs#211) Generating: N705 (???,???) [000950] ------------ IL_OFFSET void IL offset: 0x111 REG NA Generating: N707 ( 3, 2) [000156] ------------ t156 = LCL_VAR int V18 loc15 u:2 rax REG rax $2a3 Generating: N709 ( 3, 2) [000157] ------------ t157 = LCL_VAR int V17 loc14 u:2 rbx REG rbx $29f /--* t156 int +--* t157 int Generating: N711 ( 7, 5) [000158] N------N-U-- * GT void REG NA $35f IN009b: cmp eax, ebx Generating: N713 ( 9, 7) [000159] ------------ * JTRUE void REG NA IN009c: ja L_M6661_BB25 Scope info: end block BB23, IL range [0E3..117) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 3 (V03 loc0) [000..202) =============== Generating BB24 [117..11A) -> BB26 (always), preds={BB23} succs={BB26} flags=0x00000000.40080020: i gcsafe LIR BB24 IN (4)={V01 V02 V13 V03 } + ByrefExposed + GcHeap OUT(5)={V01 V02 V13 V03 V33} + ByrefExposed + GcHeap Recording Var Locations at start of BB24 V01(rsi) V02(rdi) V13(r15) V03(r14) Change life 000000640000000D {V01 V02 V03 V13 V17 V18} -> 000000040000000D {V01 V02 V03 V13} V17 in reg rbx is becoming dead [------] Live regs: (unchanged) 00000000 {} V18 in reg rax is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: 00000000 {} => 0000C0C0 {rsi rdi r14 r15} GC regs: 00000000 {} => 00000040 {rsi} Byref regs: 00000000 {} => 00000080 {rdi} L_M6661_BB24: Scope info: begin block BB24, IL range [117..11A) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 3 (V03 loc0) [000..202) Added IP mapping: 0x0117 STACK_EMPTY (G_M6661_IG20,ins#44,ofs#219) label Generating: N717 (???,???) [000951] ------------ IL_OFFSET void IL offset: 0x117 REG NA Generating: N719 ( 1, 1) [000348] ------------ t348 = CNS_INT int 0 REG rbp $40 IN009d: xor ebp, ebp /--* t348 int Generating: N721 ( 5, 4) [000350] DA---------- * STORE_LCL_VAR int V33 tmp3 d:4 rbp REG rbp V33 in reg rbp is becoming live [000350] Live regs: 0000C0C0 {rsi rdi r14 r15} => 0000C0E0 {rbp rsi rdi r14 r15} Live vars: {V01 V02 V03 V13} => {V01 V02 V03 V13 V33} Scope info: end block BB24, IL range [117..11A) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 3 (V03 loc0) [000..202) IN009e: jmp L_M6661_BB26 =============== Generating BB25 [11A..11F), preds={BB23} succs={BB26} flags=0x00000000.400b0020: i label target gcsafe LIR BB25 IN (6)={V01 V02 V13 V03 V17 V18 } + ByrefExposed + GcHeap OUT(5)={V01 V02 V13 V03 V33} + ByrefExposed + GcHeap Recording Var Locations at start of BB25 V01(rsi) V02(rdi) V13(r15) V03(r14) V17(rbx) V18(rax) Change life 000008040000000D {V01 V02 V03 V13 V33} -> 000000640000000D {V01 V02 V03 V13 V17 V18} V33 in reg rbp is becoming dead [------] Live regs: (unchanged) 00000000 {} V17 in reg rbx is becoming live [------] Live regs: 00000000 {} => 00000008 {rbx} V18 in reg rax is becoming live [------] Live regs: 00000008 {rbx} => 00000009 {rax rbx} Live regs: 00000009 {rax rbx} => 0000C0C9 {rax rbx rsi rdi r14 r15} GC regs: 00000000 {} => 00000040 {rsi} Byref regs: 00000000 {} => 00000080 {rdi} L_M6661_BB25: G_M6661_IG20: ; offs=0004D4H, funclet=00, bbWeight=0.50 Label: IG21, GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi} Scope info: begin block BB25, IL range [11A..11F) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 3 (V03 loc0) [000..202) 17 (V17 loc14) [000..202) 18 (V18 loc15) [000..202) Added IP mapping: 0x011A STACK_EMPTY (G_M6661_IG21,ins#0,ofs#0) label Generating: N725 (???,???) [000952] ------------ IL_OFFSET void IL offset: 0x11a REG NA Generating: N727 ( 3, 2) [000160] ------------ t160 = LCL_VAR int V18 loc15 u:2 rax (last use) REG rax $2a3 Generating: N729 ( 3, 2) [000161] ------------ t161 = LCL_VAR int V17 loc14 u:2 rbx (last use) REG rbx $29f /--* t160 int +--* t161 int Generating: N731 ( 7, 5) [000162] ------------ t162 = * SUB int REG rbp $360 V18 in reg rax is becoming dead [000160] Live regs: 0000C0C9 {rax rbx rsi rdi r14 r15} => 0000C0C8 {rbx rsi rdi r14 r15} Live vars: {V01 V02 V03 V13 V17 V18} => {V01 V02 V03 V13 V17} V17 in reg rbx is becoming dead [000161] Live regs: 0000C0C8 {rbx rsi rdi r14 r15} => 0000C0C0 {rsi rdi r14 r15} Live vars: {V01 V02 V03 V13 V17} => {V01 V02 V03 V13} IN009f: mov ebp, eax IN00a0: sub ebp, ebx /--* t162 int Generating: N733 ( 11, 8) [000164] DA---------- * STORE_LCL_VAR int V33 tmp3 d:3 rbp REG rbp V33 in reg rbp is becoming live [000164] Live regs: 0000C0C0 {rsi rdi r14 r15} => 0000C0E0 {rbp rsi rdi r14 r15} Live vars: {V01 V02 V03 V13} => {V01 V02 V03 V13 V33} Scope info: end block BB25, IL range [11A..11F) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 3 (V03 loc0) [000..202) =============== Generating BB26 [11F..126) -> BB28 (cond), preds={BB24,BB25} succs={BB27,BB28} flags=0x00000000.400b0020: i label target gcsafe LIR BB26 IN (5)={V01 V02 V13 V03 V33} + ByrefExposed + GcHeap OUT(5)={V01 V02 V13 V19 V03 } + ByrefExposed + GcHeap Recording Var Locations at start of BB26 V01(rsi) V02(rdi) V13(r15) V03(r14) V33(rbp) Liveness not changing: 000008040000000D {V01 V02 V03 V13 V33} Live regs: 00000000 {} => 0000C0E0 {rbp rsi rdi r14 r15} GC regs: 00000000 {} => 00000040 {rsi} Byref regs: 00000000 {} => 00000080 {rdi} L_M6661_BB26: G_M6661_IG21: ; offs=0005B6H, funclet=00, bbWeight=0.50 Label: IG22, GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi} Scope info: begin block BB26, IL range [11F..126) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 3 (V03 loc0) [000..202) Generating: N737 ( 3, 2) [000166] ------------ t166 = LCL_VAR int V33 tmp3 u:2 rbp (last use) REG rbp $248 /--* t166 int Generating: N739 ( 3, 3) [000168] DA---------- * STORE_LCL_VAR int V19 loc16 d:2 rbp REG rbp V33 in reg rbp is becoming dead [000166] Live regs: 0000C0E0 {rbp rsi rdi r14 r15} => 0000C0C0 {rsi rdi r14 r15} Live vars: {V01 V02 V03 V13 V33} => {V01 V02 V03 V13} V19 in reg rbp is becoming live [000168] Live regs: 0000C0C0 {rsi rdi r14 r15} => 0000C0E0 {rbp rsi rdi r14 r15} Live vars: {V01 V02 V03 V13} => {V01 V02 V03 V13 V19} Added IP mapping: 0x0121 STACK_EMPTY (G_M6661_IG22,ins#0,ofs#0) label Generating: N741 (???,???) [000953] ------------ IL_OFFSET void IL offset: 0x121 REG NA Generating: N743 ( 3, 2) [000169] ------------ t169 = LCL_VAR int V19 loc16 u:2 rbp REG rbp $248 Generating: N745 ( 1, 1) [000170] -c---------- t170 = CNS_INT int 0 REG NA $40 /--* t169 int +--* t170 int Generating: N747 ( 5, 4) [000171] N------N---- * EQ void REG NA $361 IN00a1: test ebp, ebp Generating: N749 ( 7, 6) [000172] ------------ * JTRUE void REG NA IN00a2: je L_M6661_BB28 Scope info: end block BB26, IL range [11F..126) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 3 (V03 loc0) [000..202) =============== Generating BB27 [126..12F), preds={BB26} succs={BB28} flags=0x00000004.40080020: i hascall gcsafe LIR BB27 IN (5)={V01 V02 V13 V19 V03} + ByrefExposed + GcHeap OUT(5)={V01 V02 V13 V19 V03} + ByrefExposed + GcHeap Recording Var Locations at start of BB27 V01(rsi) V02(rdi) V13(r15) V19(rbp) V03(r14) Liveness not changing: 000000040000010D {V01 V02 V03 V13 V19} Live regs: 00000000 {} => 0000C0E0 {rbp rsi rdi r14 r15} GC regs: 00000000 {} => 00000040 {rsi} Byref regs: 00000000 {} => 00000080 {rdi} L_M6661_BB27: Scope info: begin block BB27, IL range [126..12F) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 3 (V03 loc0) [000..202) 19 (V19 loc16) [000..202) Added IP mapping: 0x0126 STACK_EMPTY (G_M6661_IG22,ins#2,ofs#8) label Generating: N753 (???,???) [000954] ------------ IL_OFFSET void IL offset: 0x126 REG NA Generating: N755 ( 3, 2) [000344] -------N---- t344 = LCL_VAR_ADDR byref V15 loc12 rcx * ref V15._bits (offs=0x00) -> V56 tmp26 * int V15._sign (offs=0x08) -> V57 tmp27 REG rcx IN00a3: lea rcx, bword ptr [V15 rsp+B0H] Byref regs: 00000080 {rdi} => 00000082 {rcx rdi} /--* t344 byref Generating: N757 (???,???) [001054] ------------ t1054 = * PUTARG_REG byref REG rcx Byref regs: 00000082 {rcx rdi} => 00000080 {rdi} Byref regs: 00000080 {rdi} => 00000082 {rcx rdi} Generating: N759 ( 1, 1) [000346] ------------ t346 = LCL_VAR int V19 loc16 u:2 rbp REG rbp $248 /--* t346 int Generating: N761 (???,???) [001055] ------------ t1055 = * PUTARG_REG int REG rdx IN00a4: mov edx, ebp /--* t1054 byref arg0 in rcx +--* t1055 int arg1 in rdx Generating: N763 ( 18, 11) [000347] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft REG NA $VN.Void Byref regs: 00000082 {rcx rdi} => 00000080 {rdi} Call: GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi} IN00a5: call Microsoft.CodeAnalysis.RealParser:ShiftLeft(byref,int) Scope info: end block BB27, IL range [126..12F) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 3 (V03 loc0) [000..202) 19 (V19 loc16) [000..202) =============== Generating BB28 [12F..13E) -> BB32 (cond), preds={BB26,BB27} succs={BB29,BB32} flags=0x00000000.400b0020: i label target gcsafe LIR BB28 IN (5)={V01 V02 V13 V19 V03 } + ByrefExposed + GcHeap OUT(6)={V01 V02 V13 V19 V20 V21} + ByrefExposed + GcHeap Recording Var Locations at start of BB28 V01(rsi) V02(rdi) V13(r15) V19(rbp) V03(r14) Liveness not changing: 000000040000010D {V01 V02 V03 V13 V19} Live regs: 00000000 {} => 0000C0E0 {rbp rsi rdi r14 r15} GC regs: 00000000 {} => 00000040 {rsi} Byref regs: 00000000 {} => 00000080 {rdi} L_M6661_BB28: G_M6661_IG22: ; offs=0005BAH, funclet=00, bbWeight=0.50 Label: IG23, GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi} Scope info: begin block BB28, IL range [12F..13E) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 3 (V03 loc0) [000..202) 19 (V19 loc16) [000..202) Added IP mapping: 0x012F STACK_EMPTY (G_M6661_IG23,ins#0,ofs#0) label Generating: N767 (???,???) [000955] ------------ IL_OFFSET void IL offset: 0x12f REG NA Generating: N769 ( 3, 2) [000173] ------------ t173 = LCL_VAR int V03 loc0 u:2 r14 (last use) REG r14 $348 Generating: N771 ( 1, 1) [000174] ------------ t174 = LCL_VAR int V13 loc10 u:2 r15 REG r15 $293 /--* t173 int +--* t174 int Generating: N773 ( 5, 4) [000175] ------------ t175 = * SUB int REG r14 $362 V03 in reg r14 is becoming dead [000173] Live regs: 0000C0E0 {rbp rsi rdi r14 r15} => 000080E0 {rbp rsi rdi r15} Live vars: {V01 V02 V03 V13 V19} => {V01 V02 V13 V19} IN00a6: sub r14d, r15d /--* t175 int Generating: N775 ( 9, 7) [000177] DA---------- * STORE_LCL_VAR int V20 loc17 d:2 r14 REG r14 V20 in reg r14 is becoming live [000177] Live regs: 000080E0 {rbp rsi rdi r15} => 0000C0E0 {rbp rsi rdi r14 r15} Live vars: {V01 V02 V13 V19} => {V01 V02 V13 V19 V20} Added IP mapping: 0x0135 STACK_EMPTY (G_M6661_IG23,ins#1,ofs#3) Generating: N777 (???,???) [000956] ------------ IL_OFFSET void IL offset: 0x135 REG NA Generating: N779 ( 3, 2) [000178] ------------ t178 = LCL_VAR int V20 loc17 u:2 r14 REG r14 $362 /--* t178 int Generating: N781 ( 7, 5) [000180] DA---------- * STORE_LCL_VAR int V21 loc18 d:2 rbx REG rbx IN00a7: mov ebx, r14d V21 in reg rbx is becoming live [000180] Live regs: 0000C0E0 {rbp rsi rdi r14 r15} => 0000C0E8 {rbx rbp rsi rdi r14 r15} Live vars: {V01 V02 V13 V19 V20} => {V01 V02 V13 V19 V20 V21} Added IP mapping: 0x0139 STACK_EMPTY (G_M6661_IG23,ins#2,ofs#6) Generating: N783 (???,???) [000957] ------------ IL_OFFSET void IL offset: 0x139 REG NA Generating: N785 ( 1, 1) [000181] ------------ t181 = LCL_VAR int V13 loc10 u:2 r15 REG r15 $293 Generating: N787 ( 1, 1) [000182] -c---------- t182 = CNS_INT int 0 REG NA $40 /--* t181 int +--* t182 int Generating: N789 ( 3, 3) [000183] N------N---- * EQ void REG NA $363 IN00a8: test r15d, r15d Generating: N791 ( 5, 5) [000184] ------------ * JTRUE void REG NA IN00a9: je L_M6661_BB32 Scope info: end block BB28, IL range [12F..13E) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 19 (V19 loc16) [000..202) =============== Generating BB29 [13E..144) -> BB31 (cond), preds={BB28} succs={BB30,BB31} flags=0x00000000.40080020: i gcsafe LIR BB29 IN (5)={V01 V02 V13 V19 V20} + ByrefExposed + GcHeap OUT(5)={V01 V02 V13 V19 V20} + ByrefExposed + GcHeap Recording Var Locations at start of BB29 V01(rsi) V02(rdi) V13(r15) V19(rbp) V20(r14) Change life 000000800000030D {V01 V02 V13 V19 V20 V21} -> 000000000000030D {V01 V02 V13 V19 V20} V21 in reg rbx is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: 00000000 {} => 0000C0E0 {rbp rsi rdi r14 r15} GC regs: 00000000 {} => 00000040 {rsi} Byref regs: 00000000 {} => 00000080 {rdi} L_M6661_BB29: Scope info: begin block BB29, IL range [13E..144) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 19 (V19 loc16) [000..202) 20 (V20 loc17) [000..202) Added IP mapping: 0x013E STACK_EMPTY (G_M6661_IG23,ins#4,ofs#15) label Generating: N795 (???,???) [000958] ------------ IL_OFFSET void IL offset: 0x13e REG NA Generating: N797 ( 1, 1) [000326] ------------ t326 = LCL_VAR int V19 loc16 u:2 rbp REG rbp $248 Generating: N799 ( 3, 2) [000327] ------------ t327 = LCL_VAR int V20 loc17 u:2 r14 REG r14 $362 /--* t326 int +--* t327 int Generating: N801 ( 5, 4) [000328] N------N-U-- * LE void REG NA $364 IN00aa: cmp ebp, r14d Generating: N803 ( 7, 6) [000329] ------------ * JTRUE void REG NA IN00ab: jbe L_M6661_BB31 Scope info: end block BB29, IL range [13E..144) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 19 (V19 loc16) [000..202) 20 (V20 loc17) [000..202) =============== Generating BB30 [144..155) -> BB44 (always), preds={BB29} succs={BB44} flags=0x00000004.40080020: i hascall gcsafe LIR BB30 IN (3)={V01 V02 V13 } + ByrefExposed + GcHeap OUT(1)={ V51} Recording Var Locations at start of BB30 V01(rsi) V02(rdi) V13(r15) Change life 000000000000030D {V01 V02 V13 V19 V20} -> 000000000000000D {V01 V02 V13} V19 in reg rbp is becoming dead [------] Live regs: (unchanged) 00000000 {} V20 in reg r14 is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: 00000000 {} => 000080C0 {rsi rdi r15} GC regs: 00000000 {} => 00000040 {rsi} Byref regs: 00000000 {} => 00000080 {rdi} L_M6661_BB30: Scope info: begin block BB30, IL range [144..155) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) Added IP mapping: 0x0144 STACK_EMPTY (G_M6661_IG23,ins#6,ofs#24) label Generating: N807 (???,???) [000959] ------------ IL_OFFSET void IL offset: 0x144 REG NA Generating: N809 ( 1, 1) [000341] ------------ t341 = LCL_VAR byref V02 arg2 u:1 rdi (last use) REG rdi $81 /--* t341 byref Generating: N811 (???,???) [001056] ------------ * PUTARG_STK [+0x20] void REG NA V02 in reg rdi is becoming dead [000341] Live regs: 000080C0 {rsi rdi r15} => 00008040 {rsi r15} Live vars: {V01 V02 V13} => {V01 V13} Byref regs: 00000080 {rdi} => 00000000 {} IN00ac: mov bword ptr [V30+0x20 rsp+20H], rdi Generating: N813 ( 1, 1) [000339] ------------ t339 = CNS_INT int 1 REG r8 $41 IN00ad: mov r8d, 1 /--* t339 int Generating: N815 (???,???) [001057] ------------ t1057 = * PUTARG_REG int REG r8 Generating: N817 ( 3, 2) [000335] ------------ t335 = LCL_VAR ref (AX) V12 loc9 rcx REG rcx $18c IN00ae: mov rcx, gword ptr [V12 rsp+C8H] GC regs: 00000040 {rsi} => 00000042 {rcx rsi} /--* t335 ref Generating: N819 (???,???) [001058] ------------ t1058 = * PUTARG_REG ref REG rcx GC regs: 00000042 {rcx rsi} => 00000040 {rsi} GC regs: 00000040 {rsi} => 00000042 {rcx rsi} Generating: N821 ( 1, 1) [000336] ------------ t336 = LCL_VAR int V13 loc10 u:2 r15 (last use) REG r15 $293 /--* t336 int Generating: N823 (???,???) [001059] ------------ t1059 = * PUTARG_REG int REG rdx V13 in reg r15 is becoming dead [000336] Live regs: 00008040 {rsi r15} => 00000040 {rsi} Live vars: {V01 V13} => {V01} IN00af: mov edx, r15d Generating: N825 ( 1, 1) [000340] ------------ t340 = LCL_VAR ref V01 arg1 u:1 rsi (last use) REG rsi $c0 /--* t340 ref Generating: N827 (???,???) [001060] ------------ t1060 = * PUTARG_REG ref REG r9 V01 in reg rsi is becoming dead [000340] Live regs: 00000040 {rsi} => 00000000 {} Live vars: {V01} => {} GC regs: 00000042 {rcx rsi} => 00000002 {rcx} IN00b0: mov r9, rsi GC regs: 00000002 {rcx} => 00000202 {rcx r9} /--* t1057 int arg2 in r8 +--* t1058 ref arg0 in rcx +--* t1059 int arg1 in rdx +--* t1060 ref arg3 in r9 Generating: N829 ( 24, 15) [000342] --CXG------- t342 = * CALL int Microsoft.CodeAnalysis.RealParser.ConvertBigIntegerToFloatingPointBits REG rax $5c2 GC regs: 00000202 {rcx r9} => 00000200 {r9} GC regs: 00000200 {r9} => 00000000 {} Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN00b1: call Microsoft.CodeAnalysis.RealParser:ConvertBigIntegerToFloatingPointBits(System.Byte[],int,bool,FloatingPointType,byref):int /--* t342 int Generating: N831 ( 24, 15) [000717] DA-XG------- * STORE_LCL_VAR int V51 tmp21 d:5 rax REG rax V51 in reg rax is becoming live [000717] Live regs: 00000000 {} => 00000001 {rax} Live vars: {} => {V51} Scope info: end block BB30, IL range [144..155) Scope info: open scopes = IN00b2: jmp L_M6661_BB44 =============== Generating BB31 [155..15C), preds={BB29} succs={BB32} flags=0x00000000.400b0020: i label target gcsafe LIR BB31 IN (5)={V01 V02 V13 V19 V20 } + ByrefExposed + GcHeap OUT(6)={V01 V02 V13 V19 V20 V21} + ByrefExposed + GcHeap Recording Var Locations at start of BB31 V01(rsi) V02(rdi) V13(r15) V19(rbp) V20(r14) Change life 0000000000000080 {V51} -> 000000000000030D {V01 V02 V13 V19 V20} V51 in reg rax is becoming dead [------] Live regs: (unchanged) 00000000 {} V01 in reg rsi is becoming live [------] Live regs: 00000000 {} => 00000040 {rsi} V02 in reg rdi is becoming live [------] Live regs: 00000040 {rsi} => 000000C0 {rsi rdi} V13 in reg r15 is becoming live [------] Live regs: 000000C0 {rsi rdi} => 000080C0 {rsi rdi r15} V19 in reg rbp is becoming live [------] Live regs: 000080C0 {rsi rdi r15} => 000080E0 {rbp rsi rdi r15} V20 in reg r14 is becoming live [------] Live regs: 000080E0 {rbp rsi rdi r15} => 0000C0E0 {rbp rsi rdi r14 r15} Live regs: (unchanged) 0000C0E0 {rbp rsi rdi r14 r15} GC regs: (unchanged) 00000040 {rsi} Byref regs: (unchanged) 00000080 {rdi} L_M6661_BB31: G_M6661_IG23: ; offs=0005D1H, funclet=00, bbWeight=0.50 Label: IG24, GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi} Scope info: begin block BB31, IL range [155..15C) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 19 (V19 loc16) [000..202) 20 (V20 loc17) [000..202) Added IP mapping: 0x0155 STACK_EMPTY (G_M6661_IG24,ins#0,ofs#0) label Generating: N835 (???,???) [000960] ------------ IL_OFFSET void IL offset: 0x155 REG NA Generating: N837 ( 3, 2) [000330] ------------ t330 = LCL_VAR int V20 loc17 u:2 r14 REG r14 $362 Generating: N839 ( 1, 1) [000331] ------------ t331 = LCL_VAR int V19 loc16 u:2 rbp REG rbp $248 /--* t330 int +--* t331 int Generating: N841 ( 5, 4) [000332] ------------ t332 = * SUB int REG rbx $365 IN00b3: mov ebx, r14d IN00b4: sub ebx, ebp /--* t332 int Generating: N843 ( 9, 7) [000334] DA---------- * STORE_LCL_VAR int V21 loc18 d:4 rbx REG rbx V21 in reg rbx is becoming live [000334] Live regs: 0000C0E0 {rbp rsi rdi r14 r15} => 0000C0E8 {rbx rbp rsi rdi r14 r15} Live vars: {V01 V02 V13 V19 V20} => {V01 V02 V13 V19 V20 V21} Scope info: end block BB31, IL range [155..15C) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 19 (V19 loc16) [000..202) 20 (V20 loc17) [000..202) =============== Generating BB32 [15C..167) -> BB34 (cond), preds={BB28,BB31} succs={BB33,BB34} flags=0x00000004.400b0020: i label target hascall gcsafe LIR BB32 IN (6)={V01 V02 V13 V19 V20 V21} + ByrefExposed + GcHeap OUT(6)={V01 V02 V13 V19 V20 V21} + ByrefExposed + GcHeap Recording Var Locations at start of BB32 V01(rsi) V02(rdi) V13(r15) V19(rbp) V20(r14) V21(rbx) Liveness not changing: 000000800000030D {V01 V02 V13 V19 V20 V21} Live regs: 00000000 {} => 0000C0E8 {rbx rbp rsi rdi r14 r15} GC regs: 00000000 {} => 00000040 {rsi} Byref regs: 00000000 {} => 00000080 {rdi} L_M6661_BB32: G_M6661_IG24: ; offs=00060CH, funclet=00, bbWeight=0.50 Label: IG25, GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi} Scope info: begin block BB32, IL range [15C..167) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 19 (V19 loc16) [000..202) 20 (V20 loc17) [000..202) 21 (V21 loc18) [000..202) Added IP mapping: 0x015C STACK_EMPTY (G_M6661_IG25,ins#0,ofs#0) label Generating: N847 (???,???) [000961] ------------ IL_OFFSET void IL offset: 0x15c REG NA Generating: N849 ( 3, 2) [000719] -------N---- t719 = LCL_VAR ref (AX) V56 tmp26 rcx REG rcx $186 IN00b5: mov rcx, gword ptr [V56 rsp+B0H] GC regs: 00000040 {rsi} => 00000042 {rcx rsi} /--* t719 ref Generating: N851 ( 7, 5) [000720] DA--G------- * STORE_LCL_VAR ref (AX) V68 tmp38 NA REG NA GC regs: 00000042 {rcx rsi} => 00000040 {rsi} IN00b6: mov gword ptr [V68 rsp+58H], rcx Generating: N853 ( 3, 2) [000722] -------N---- t722 = LCL_VAR int (AX) V57 tmp27 rcx REG rcx $24a IN00b7: mov ecx, dword ptr [V57 rsp+B8H] /--* t722 int Generating: N855 ( 7, 5) [000723] DA--G------- * STORE_LCL_VAR int (AX) V69 tmp39 NA REG NA IN00b8: mov dword ptr [V69 rsp+60H], ecx genIPmappingAdd: ignoring duplicate IL offset 0x15c Generating: N857 (???,???) [000962] ------------ IL_OFFSET void IL offset: 0x15c REG NA Generating: N859 ( 3, 2) [000726] -------N---- t726 = LCL_VAR ref (AX) V58 tmp28 rcx REG rcx $187 IN00b9: mov rcx, gword ptr [V58 rsp+A0H] GC regs: 00000040 {rsi} => 00000042 {rcx rsi} /--* t726 ref Generating: N861 ( 7, 5) [000727] DA--G------- * STORE_LCL_VAR ref V70 tmp40 d:2 rcx REG rcx GC regs: 00000042 {rcx rsi} => 00000040 {rsi} V70 in reg rcx is becoming live [000727] Live regs: 0000C0E8 {rbx rbp rsi rdi r14 r15} => 0000C0EA {rcx rbx rbp rsi rdi r14 r15} Live vars: {V01 V02 V13 V19 V20 V21} => {V01 V02 V13 V19 V20 V21 V70} GC regs: 00000040 {rsi} => 00000042 {rcx rsi} Generating: N863 ( 3, 2) [000729] -------N---- t729 = LCL_VAR int (AX) V59 tmp29 rdx REG rdx $24b IN00ba: mov edx, dword ptr [V59 rsp+A8H] /--* t729 int Generating: N865 ( 7, 5) [000730] DA--G------- * STORE_LCL_VAR int V71 tmp41 d:2 rdx REG rdx V71 in reg rdx is becoming live [000730] Live regs: 0000C0EA {rcx rbx rbp rsi rdi r14 r15} => 0000C0EE {rcx rdx rbx rbp rsi rdi r14 r15} Live vars: {V01 V02 V13 V19 V20 V21 V70} => {V01 V02 V13 V19 V20 V21 V70 V71} Generating: N867 ( 3, 2) [000496] -------N---- t496 = LCL_VAR_ADDR byref V49 tmp19 rax * ref V49._bits (offs=0x00) -> V68 tmp38 * int V49._sign (offs=0x08) -> V69 tmp39 REG rax IN00bb: lea rax, bword ptr [V49 rsp+58H] Byref regs: 00000080 {rdi} => 00000081 {rax rdi} /--* t496 byref Generating: N869 ( 7, 6) [000752] DA--------L- * STORE_LCL_VAR byref V84 tmp54 d:2 rax REG rax Byref regs: 00000081 {rax rdi} => 00000080 {rdi} V84 in reg rax is becoming live [000752] Live regs: 0000C0EE {rcx rdx rbx rbp rsi rdi r14 r15} => 0000C0EF {rax rcx rdx rbx rbp rsi rdi r14 r15} Live vars: {V01 V02 V13 V19 V20 V21 V70 V71} => {V01 V02 V13 V19 V20 V21 V70 V71 V84} Byref regs: 00000080 {rdi} => 00000081 {rax rdi} Generating: N871 ( 3, 2) [000736] -------N---- t736 = LCL_VAR_ADDR byref V76 tmp46 r8 REG r8 IN00bc: lea r8, bword ptr [V76 rsp+38H] Byref regs: 00000081 {rax rdi} => 00000181 {rax rdi r8} /--* t736 byref Generating: N873 ( 3, 3) [000738] DA---------- * STORE_LCL_VAR byref V83 tmp53 d:2 r8 REG r8 Byref regs: 00000181 {rax rdi r8} => 00000081 {rax rdi} V83 in reg r8 is becoming live [000738] Live regs: 0000C0EF {rax rcx rdx rbx rbp rsi rdi r14 r15} => 0000C1EF {rax rcx rdx rbx rbp rsi rdi r8 r14 r15} Live vars: {V01 V02 V13 V19 V20 V21 V70 V71 V84} => {V01 V02 V13 V19 V20 V21 V70 V71 V83 V84} Byref regs: 00000081 {rax rdi} => 00000181 {rax rdi r8} Generating: N875 ( 1, 1) [000739] ------------ t739 = LCL_VAR byref V83 tmp53 u:2 r8 Zero Fseq[_bits] REG r8 $417 Generating: N877 ( 3, 2) [000741] -------N---- t741 = LCL_VAR ref V70 tmp40 u:2 rcx (last use) REG rcx $187 /--* t739 byref +--* t741 ref Generating: N879 (???,???) [000963] -A---------- * STOREIND ref REG NA V70 in reg rcx is becoming dead [000741] Live regs: 0000C1EF {rax rcx rdx rbx rbp rsi rdi r8 r14 r15} => 0000C1ED {rax rdx rbx rbp rsi rdi r8 r14 r15} Live vars: {V01 V02 V13 V19 V20 V21 V70 V71 V83 V84} => {V01 V02 V13 V19 V20 V21 V71 V83 V84} GC regs: 00000042 {rcx rsi} => 00000040 {rsi} IN00bd: mov gword ptr [r8], rcx Generating: N881 ( 1, 1) [000744] ------------ t744 = LCL_VAR byref V83 tmp53 u:2 r8 (last use) REG r8 $417 /--* t744 byref Generating: N883 ( 2, 2) [000746] -c---------- t746 = * LEA(b+8) byref REG NA Generating: N885 ( 3, 2) [000748] -------N---- t748 = LCL_VAR int V71 tmp41 u:2 rdx (last use) REG rdx $24b /--* t746 byref +--* t748 int Generating: N887 (???,???) [000964] -A--------L- * STOREIND int REG NA V83 in reg r8 is becoming dead [000744] Live regs: 0000C1ED {rax rdx rbx rbp rsi rdi r8 r14 r15} => 0000C0ED {rax rdx rbx rbp rsi rdi r14 r15} Live vars: {V01 V02 V13 V19 V20 V21 V71 V83 V84} => {V01 V02 V13 V19 V20 V21 V71 V84} Byref regs: 00000181 {rax rdi r8} => 00000081 {rax rdi} V71 in reg rdx is becoming dead [000748] Live regs: 0000C0ED {rax rdx rbx rbp rsi rdi r14 r15} => 0000C0E9 {rax rbx rbp rsi rdi r14 r15} Live vars: {V01 V02 V13 V19 V20 V21 V71 V84} => {V01 V02 V13 V19 V20 V21 V84} IN00be: mov dword ptr [r8+8], edx Generating: N889 ( 3, 2) [000753] ------------ t753 = LCL_VAR byref V84 tmp54 u:2 rax (last use) REG rax $415 /--* t753 byref Generating: N891 (???,???) [001061] ------------ t1061 = * PUTARG_REG byref REG rcx V84 in reg rax is becoming dead [000753] Live regs: 0000C0E9 {rax rbx rbp rsi rdi r14 r15} => 0000C0E8 {rbx rbp rsi rdi r14 r15} Live vars: {V01 V02 V13 V19 V20 V21 V84} => {V01 V02 V13 V19 V20 V21} Byref regs: 00000081 {rax rdi} => 00000080 {rdi} IN00bf: mov rcx, rax Byref regs: 00000080 {rdi} => 00000082 {rcx rdi} Generating: N893 ( 3, 2) [000754] -------N---- t754 = LCL_VAR_ADDR byref V76 tmp46 rdx REG rdx IN00c0: lea rdx, bword ptr [V76 rsp+38H] Byref regs: 00000082 {rcx rdi} => 00000086 {rcx rdx rdi} /--* t754 byref Generating: N895 (???,???) [001062] ------------ t1062 = * PUTARG_REG byref REG rdx Byref regs: 00000086 {rcx rdx rdi} => 00000082 {rcx rdi} Byref regs: 00000082 {rcx rdi} => 00000086 {rcx rdx rdi} /--* t1061 byref this in rcx +--* t1062 byref arg1 in rdx Generating: N897 ( 48, 34) [000499] --CXG------- t499 = * CALL int System.Numerics.BigInteger.CompareTo REG rax $2ae Byref regs: 00000086 {rcx rdx rdi} => 00000084 {rdx rdi} Byref regs: 00000084 {rdx rdi} => 00000080 {rdi} Call: GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi} IN00c1: call System.Numerics.BigInteger:CompareTo(System.Numerics.BigInteger):int:this Generating: N899 ( 1, 1) [000502] -c---------- t502 = CNS_INT int 0 REG NA $40 /--* t499 int +--* t502 int Generating: N901 ( 50, 36) [000503] J--XG--N---- * LT void REG NA $367 IN00c2: test eax, eax Generating: N903 ( 52, 38) [000195] ---XG------- * JTRUE void REG NA IN00c3: jl L_M6661_BB34 Scope info: end block BB32, IL range [15C..167) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 19 (V19 loc16) [000..202) 20 (V20 loc17) [000..202) 21 (V21 loc18) [000..202) =============== Generating BB33 [167..16B) -> BB35 (always), preds={BB32} succs={BB35} flags=0x00000000.40080020: i gcsafe LIR BB33 IN (6)={V01 V02 V13 V19 V20 V21 } + ByrefExposed + GcHeap OUT(6)={V01 V02 V13 V20 V21 V34} + ByrefExposed + GcHeap Recording Var Locations at start of BB33 V01(rsi) V02(rdi) V13(r15) V19(rbp) V20(r14) V21(rbx) Liveness not changing: 000000800000030D {V01 V02 V13 V19 V20 V21} Live regs: 00000000 {} => 0000C0E8 {rbx rbp rsi rdi r14 r15} GC regs: 00000000 {} => 00000040 {rsi} Byref regs: 00000000 {} => 00000080 {rdi} L_M6661_BB33: Scope info: begin block BB33, IL range [167..16B) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 19 (V19 loc16) [000..202) 20 (V20 loc17) [000..202) 21 (V21 loc18) [000..202) Added IP mapping: 0x0167 STACK_EMPTY (G_M6661_IG25,ins#15,ofs#77) label Generating: N907 (???,???) [000965] ------------ IL_OFFSET void IL offset: 0x167 REG NA Generating: N909 ( 1, 1) [000322] ------------ t322 = LCL_VAR int V19 loc16 u:2 rbp (last use) REG rbp $248 /--* t322 int Generating: N911 ( 5, 4) [000324] DA---------- * STORE_LCL_VAR int V34 tmp4 d:4 rbp REG rbp V19 in reg rbp is becoming dead [000322] Live regs: 0000C0E8 {rbx rbp rsi rdi r14 r15} => 0000C0C8 {rbx rsi rdi r14 r15} Live vars: {V01 V02 V13 V19 V20 V21} => {V01 V02 V13 V20 V21} V34 in reg rbp is becoming live [000324] Live regs: 0000C0C8 {rbx rsi rdi r14 r15} => 0000C0E8 {rbx rbp rsi rdi r14 r15} Live vars: {V01 V02 V13 V20 V21} => {V01 V02 V13 V20 V21 V34} Scope info: end block BB33, IL range [167..16B) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 20 (V20 loc17) [000..202) 21 (V21 loc18) [000..202) IN00c4: jmp L_M6661_BB35 =============== Generating BB34 [16B..16F), preds={BB32} succs={BB35} flags=0x00000000.400b0020: i label target gcsafe LIR BB34 IN (6)={V01 V02 V13 V19 V20 V21 } + ByrefExposed + GcHeap OUT(6)={V01 V02 V13 V20 V21 V34} + ByrefExposed + GcHeap Recording Var Locations at start of BB34 V01(rsi) V02(rdi) V13(r15) V19(rbp) V20(r14) V21(rbx) Change life 000010800000020D {V01 V02 V13 V20 V21 V34} -> 000000800000030D {V01 V02 V13 V19 V20 V21} V34 in reg rbp is becoming dead [------] Live regs: (unchanged) 00000000 {} V19 in reg rbp is becoming live [------] Live regs: 00000000 {} => 00000020 {rbp} Live regs: 00000020 {rbp} => 0000C0E8 {rbx rbp rsi rdi r14 r15} GC regs: 00000000 {} => 00000040 {rsi} Byref regs: 00000000 {} => 00000080 {rdi} L_M6661_BB34: G_M6661_IG25: ; offs=000611H, funclet=00, bbWeight=0.50 Label: IG26, GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi} Scope info: begin block BB34, IL range [16B..16F) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 20 (V20 loc17) [000..202) 21 (V21 loc18) [000..202) 19 (V19 loc16) [000..202) Added IP mapping: 0x016B STACK_EMPTY (G_M6661_IG26,ins#0,ofs#0) label Generating: N915 (???,???) [000966] ------------ IL_OFFSET void IL offset: 0x16b REG NA Generating: N917 ( 1, 1) [000196] ------------ t196 = LCL_VAR int V19 loc16 u:2 rbp (last use) REG rbp $248 Generating: N919 ( 1, 1) [000197] -c---------- t197 = CNS_INT int 1 REG NA $41 /--* t196 int +--* t197 int Generating: N921 ( 3, 3) [000198] ------------ t198 = * ADD int REG rbp $368 V19 in reg rbp is becoming dead [000196] Live regs: 0000C0E8 {rbx rbp rsi rdi r14 r15} => 0000C0C8 {rbx rsi rdi r14 r15} Live vars: {V01 V02 V13 V19 V20 V21} => {V01 V02 V13 V20 V21} IN00c5: inc ebp /--* t198 int Generating: N923 ( 7, 6) [000200] DA---------- * STORE_LCL_VAR int V34 tmp4 d:3 rbp REG rbp V34 in reg rbp is becoming live [000200] Live regs: 0000C0C8 {rbx rsi rdi r14 r15} => 0000C0E8 {rbx rbp rsi rdi r14 r15} Live vars: {V01 V02 V13 V20 V21} => {V01 V02 V13 V20 V21 V34} Scope info: end block BB34, IL range [16B..16F) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 20 (V20 loc17) [000..202) 21 (V21 loc18) [000..202) =============== Generating BB35 [16F..1A4) -> BB40 (cond), preds={BB33,BB34} succs={BB36,BB40} flags=0x00000004.400b0020: i label target hascall gcsafe LIR BB35 IN (6)={V01 V02 V13 V20 V21 V34 } + ByrefExposed + GcHeap OUT(8)={V01 V02 V13 V20 V24 V25 V26 V22} + ByrefExposed + GcHeap Recording Var Locations at start of BB35 V01(rsi) V02(rdi) V13(r15) V20(r14) V21(rbx) V34(rbp) Liveness not changing: 000010800000020D {V01 V02 V13 V20 V21 V34} Live regs: 00000000 {} => 0000C0E8 {rbx rbp rsi rdi r14 r15} GC regs: 00000000 {} => 00000040 {rsi} Byref regs: 00000000 {} => 00000080 {rdi} L_M6661_BB35: G_M6661_IG26: ; offs=000663H, funclet=00, bbWeight=0.50 Label: IG27, GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi} Scope info: begin block BB35, IL range [16F..1A4) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 20 (V20 loc17) [000..202) 21 (V21 loc18) [000..202) Generating: N927 ( 3, 2) [000202] ------------ t202 = LCL_VAR int V34 tmp4 u:2 rbp (last use) REG rbp $24c /--* t202 int Generating: N929 ( 7, 5) [000204] DA---------- * STORE_LCL_VAR int V22 loc19 d:2 rbp REG rbp V34 in reg rbp is becoming dead [000202] Live regs: 0000C0E8 {rbx rbp rsi rdi r14 r15} => 0000C0C8 {rbx rsi rdi r14 r15} Live vars: {V01 V02 V13 V20 V21 V34} => {V01 V02 V13 V20 V21} V22 in reg rbp is becoming live [000204] Live regs: 0000C0C8 {rbx rsi rdi r14 r15} => 0000C0E8 {rbx rbp rsi rdi r14 r15} Live vars: {V01 V02 V13 V20 V21} => {V01 V02 V13 V20 V21 V22} Added IP mapping: 0x0171 STACK_EMPTY (G_M6661_IG27,ins#0,ofs#0) label Generating: N931 (???,???) [000967] ------------ IL_OFFSET void IL offset: 0x171 REG NA Generating: N933 ( 3, 2) [000205] -------N---- t205 = LCL_VAR_ADDR byref V15 loc12 rcx * ref V15._bits (offs=0x00) -> V56 tmp26 * int V15._sign (offs=0x08) -> V57 tmp27 REG rcx IN00c6: lea rcx, bword ptr [V15 rsp+B0H] Byref regs: 00000080 {rdi} => 00000082 {rcx rdi} /--* t205 byref Generating: N935 (???,???) [001063] ------------ t1063 = * PUTARG_REG byref REG rcx Byref regs: 00000082 {rcx rdi} => 00000080 {rdi} Byref regs: 00000080 {rdi} => 00000082 {rcx rdi} Generating: N937 ( 3, 2) [000207] ------------ t207 = LCL_VAR int V21 loc18 u:3 rbx (last use) REG rbx $249 /--* t207 int Generating: N939 (???,???) [001064] ------------ t1064 = * PUTARG_REG int REG rdx V21 in reg rbx is becoming dead [000207] Live regs: 0000C0E8 {rbx rbp rsi rdi r14 r15} => 0000C0E0 {rbp rsi rdi r14 r15} Live vars: {V01 V02 V13 V20 V21 V22} => {V01 V02 V13 V20 V22} IN00c7: mov edx, ebx /--* t1063 byref arg0 in rcx +--* t1064 int arg1 in rdx Generating: N941 ( 20, 12) [000208] --CXG------- * CALL void Microsoft.CodeAnalysis.RealParser.ShiftLeft REG NA $VN.Void Byref regs: 00000082 {rcx rdi} => 00000080 {rdi} Call: GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi} IN00c8: call Microsoft.CodeAnalysis.RealParser:ShiftLeft(byref,int) Added IP mapping: 0x017A STACK_EMPTY (G_M6661_IG27,ins#3,ofs#15) Generating: N943 (???,???) [000968] ------------ IL_OFFSET void IL offset: 0x17a REG NA Generating: N945 ( 3, 2) [000219] -------N---- t219 = LCL_VAR_ADDR byref V35 tmp5 rcx * ref V35._bits (offs=0x00) -> V62 tmp32 * int V35._sign (offs=0x08) -> V63 tmp33 REG rcx IN00c9: lea rcx, bword ptr [V35 rsp+80H] Byref regs: 00000080 {rdi} => 00000082 {rcx rdi} /--* t219 byref Generating: N947 ( 7, 6) [000797] DA--------L- * STORE_LCL_VAR long V88 tmp58 d:2 rcx REG rcx Byref regs: 00000082 {rcx rdi} => 00000080 {rdi} V88 in reg rcx is becoming live [000797] Live regs: 0000C0E0 {rbp rsi rdi r14 r15} => 0000C0E2 {rcx rbp rsi rdi r14 r15} Live vars: {V01 V02 V13 V20 V22} => {V01 V02 V13 V20 V22 V88} Generating: N949 ( 3, 2) [000762] -------N---- t762 = LCL_VAR_ADDR byref V76 tmp46 rdx REG rdx IN00ca: lea rdx, bword ptr [V76 rsp+38H] Byref regs: 00000080 {rdi} => 00000084 {rdx rdi} /--* t762 byref Generating: N951 ( 3, 3) [000764] DA---------- * STORE_LCL_VAR byref V85 tmp55 d:2 rdx REG rdx Byref regs: 00000084 {rdx rdi} => 00000080 {rdi} V85 in reg rdx is becoming live [000764] Live regs: 0000C0E2 {rcx rbp rsi rdi r14 r15} => 0000C0E6 {rcx rdx rbp rsi rdi r14 r15} Live vars: {V01 V02 V13 V20 V22 V88} => {V01 V02 V13 V20 V22 V85 V88} Byref regs: 00000080 {rdi} => 00000084 {rdx rdi} Generating: N953 ( 1, 1) [000765] ------------ t765 = LCL_VAR byref V85 tmp55 u:2 rdx Zero Fseq[_bits] REG rdx $41c Generating: N955 ( 3, 2) [000767] -------N---- t767 = LCL_VAR ref (AX) V56 tmp26 r8 REG r8 $188 IN00cb: mov r8, gword ptr [V56 rsp+B0H] GC regs: 00000040 {rsi} => 00000140 {rsi r8} /--* t765 byref +--* t767 ref Generating: N957 (???,???) [000969] -A--G------- * STOREIND ref REG NA GC regs: 00000140 {rsi r8} => 00000040 {rsi} IN00cc: mov gword ptr [rdx], r8 Generating: N959 ( 1, 1) [000770] ------------ t770 = LCL_VAR byref V85 tmp55 u:2 rdx (last use) REG rdx $41c /--* t770 byref Generating: N961 ( 2, 2) [000772] -c---------- t772 = * LEA(b+8) byref REG NA Generating: N963 ( 3, 2) [000774] -------N---- t774 = LCL_VAR int (AX) V57 tmp27 r8 REG r8 $24d IN00cd: mov r8d, dword ptr [V57 rsp+B8H] /--* t772 byref +--* t774 int Generating: N965 (???,???) [000970] -A--G-----L- * STOREIND int REG NA V85 in reg rdx is becoming dead [000770] Live regs: 0000C0E6 {rcx rdx rbp rsi rdi r14 r15} => 0000C0E2 {rcx rbp rsi rdi r14 r15} Live vars: {V01 V02 V13 V20 V22 V85 V88} => {V01 V02 V13 V20 V22 V88} Byref regs: 00000084 {rdx rdi} => 00000080 {rdi} IN00ce: mov dword ptr [rdx+8], r8d Generating: N967 ( 3, 2) [000781] -------N---- t781 = LCL_VAR_ADDR byref V86 tmp56 rdx REG rdx IN00cf: lea rdx, bword ptr [V86 rsp+28H] Byref regs: 00000080 {rdi} => 00000084 {rdx rdi} /--* t781 byref Generating: N969 ( 3, 3) [000783] DA---------- * STORE_LCL_VAR byref V87 tmp57 d:2 rdx REG rdx Byref regs: 00000084 {rdx rdi} => 00000080 {rdi} V87 in reg rdx is becoming live [000783] Live regs: 0000C0E2 {rcx rbp rsi rdi r14 r15} => 0000C0E6 {rcx rdx rbp rsi rdi r14 r15} Live vars: {V01 V02 V13 V20 V22 V88} => {V01 V02 V13 V20 V22 V87 V88} Byref regs: 00000080 {rdi} => 00000084 {rdx rdi} Generating: N971 ( 1, 1) [000784] ------------ t784 = LCL_VAR byref V87 tmp57 u:2 rdx Zero Fseq[_bits] REG rdx $41e Generating: N973 ( 3, 2) [000786] -------N---- t786 = LCL_VAR ref (AX) V58 tmp28 r8 REG r8 $189 IN00d0: mov r8, gword ptr [V58 rsp+A0H] GC regs: 00000040 {rsi} => 00000140 {rsi r8} /--* t784 byref +--* t786 ref Generating: N975 (???,???) [000971] -A--G------- * STOREIND ref REG NA GC regs: 00000140 {rsi r8} => 00000040 {rsi} IN00d1: mov gword ptr [rdx], r8 Generating: N977 ( 1, 1) [000789] ------------ t789 = LCL_VAR byref V87 tmp57 u:2 rdx (last use) REG rdx $41e /--* t789 byref Generating: N979 ( 2, 2) [000791] -c---------- t791 = * LEA(b+8) byref REG NA Generating: N981 ( 3, 2) [000793] -------N---- t793 = LCL_VAR int (AX) V59 tmp29 r8 REG r8 $24e IN00d2: mov r8d, dword ptr [V59 rsp+A8H] /--* t791 byref +--* t793 int Generating: N983 (???,???) [000972] -A--G-----L- * STOREIND int REG NA V87 in reg rdx is becoming dead [000789] Live regs: 0000C0E6 {rcx rdx rbp rsi rdi r14 r15} => 0000C0E2 {rcx rbp rsi rdi r14 r15} Live vars: {V01 V02 V13 V20 V22 V87 V88} => {V01 V02 V13 V20 V22 V88} Byref regs: 00000084 {rdx rdi} => 00000080 {rdi} IN00d3: mov dword ptr [rdx+8], r8d Generating: N985 ( 3, 2) [000798] ------------ t798 = LCL_VAR long V88 tmp58 u:2 rcx (last use) REG rcx $41b /--* t798 long Generating: N987 (???,???) [001065] ------------ t1065 = * PUTARG_REG long REG rcx V88 in reg rcx is becoming dead [000798] Live regs: 0000C0E2 {rcx rbp rsi rdi r14 r15} => 0000C0E0 {rbp rsi rdi r14 r15} Live vars: {V01 V02 V13 V20 V22 V88} => {V01 V02 V13 V20 V22} Generating: N989 ( 3, 2) [000799] -------N---- t799 = LCL_VAR_ADDR byref V76 tmp46 rdx REG rdx IN00d4: lea rdx, bword ptr [V76 rsp+38H] Byref regs: 00000080 {rdi} => 00000084 {rdx rdi} /--* t799 byref Generating: N991 (???,???) [001066] ------------ t1066 = * PUTARG_REG byref REG rdx Byref regs: 00000084 {rdx rdi} => 00000080 {rdi} Byref regs: 00000080 {rdi} => 00000084 {rdx rdi} Generating: N993 ( 3, 2) [000801] -------N---- t801 = LCL_VAR_ADDR byref V86 tmp56 r8 REG r8 IN00d5: lea r8, bword ptr [V86 rsp+28H] Byref regs: 00000084 {rdx rdi} => 00000184 {rdx rdi r8} /--* t801 byref Generating: N995 (???,???) [001067] ------------ t1067 = * PUTARG_REG byref REG r8 Byref regs: 00000184 {rdx rdi r8} => 00000084 {rdx rdi} Byref regs: 00000084 {rdx rdi} => 00000184 {rdx rdi r8} Generating: N997 ( 3, 2) [000211] -------N---- t211 = LCL_VAR_ADDR byref V23 loc20 r9 * ref V23._bits (offs=0x00) -> V60 tmp30 * int V23._sign (offs=0x08) -> V61 tmp31 REG r9 IN00d6: lea r9, bword ptr [V23 rsp+90H] Byref regs: 00000184 {rdx rdi r8} => 00000384 {rdx rdi r8 r9} /--* t211 byref Generating: N999 (???,???) [001068] ------------ t1068 = * PUTARG_REG byref REG r9 Byref regs: 00000384 {rdx rdi r8 r9} => 00000184 {rdx rdi r8} Byref regs: 00000184 {rdx rdi r8} => 00000384 {rdx rdi r8 r9} /--* t1065 long arg0 in rcx +--* t1066 byref arg1 in rdx +--* t1067 byref arg2 in r8 +--* t1068 byref arg3 in r9 Generating: N1001 ( 78, 56) [000213] S-CXG------- * CALL void System.Numerics.BigInteger.DivRem REG NA $VN.Void Byref regs: 00000384 {rdx rdi r8 r9} => 00000380 {rdi r8 r9} Byref regs: 00000380 {rdi r8 r9} => 00000280 {rdi r9} Byref regs: 00000280 {rdi r9} => 00000080 {rdi} Call: GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi} IN00d7: call System.Numerics.BigInteger:DivRem(System.Numerics.BigInteger,System.Numerics.BigInteger,byref):System.Numerics.BigInteger Generating: N1003 ( 3, 2) [000808] -------N---- t808 = LCL_VAR_ADDR byref V76 tmp46 rcx REG rcx IN00d8: lea rcx, bword ptr [V76 rsp+38H] Byref regs: 00000080 {rdi} => 00000082 {rcx rdi} /--* t808 byref Generating: N1005 ( 3, 3) [000810] DA---------- * STORE_LCL_VAR byref V89 tmp59 d:2 rcx REG rcx Byref regs: 00000082 {rcx rdi} => 00000080 {rdi} V89 in reg rcx is becoming live [000810] Live regs: 0000C0E0 {rbp rsi rdi r14 r15} => 0000C0E2 {rcx rbp rsi rdi r14 r15} Live vars: {V01 V02 V13 V20 V22} => {V01 V02 V13 V20 V22 V89} Byref regs: 00000080 {rdi} => 00000082 {rcx rdi} Generating: N1007 ( 1, 1) [000811] ------------ t811 = LCL_VAR byref V89 tmp59 u:2 rcx Zero Fseq[_bits] REG rcx $423 Generating: N1009 ( 3, 2) [000813] -------N---- t813 = LCL_VAR ref (AX) V62 tmp32 rax REG rax $18a IN00d9: mov rax, gword ptr [V62 rsp+80H] GC regs: 00000040 {rsi} => 00000041 {rax rsi} /--* t811 byref +--* t813 ref Generating: N1011 (???,???) [000973] -A--G------- * STOREIND ref REG NA GC regs: 00000041 {rax rsi} => 00000040 {rsi} IN00da: mov gword ptr [rcx], rax Generating: N1013 ( 1, 1) [000816] ------------ t816 = LCL_VAR byref V89 tmp59 u:2 rcx (last use) REG rcx $423 /--* t816 byref Generating: N1015 ( 2, 2) [000818] -c---------- t818 = * LEA(b+8) byref REG NA Generating: N1017 ( 3, 2) [000820] -------N---- t820 = LCL_VAR int (AX) V63 tmp33 rax REG rax $24f IN00db: mov eax, dword ptr [V63 rsp+88H] /--* t818 byref +--* t820 int Generating: N1019 (???,???) [000974] -A--G-----L- * STOREIND int REG NA V89 in reg rcx is becoming dead [000816] Live regs: 0000C0E2 {rcx rbp rsi rdi r14 r15} => 0000C0E0 {rbp rsi rdi r14 r15} Live vars: {V01 V02 V13 V20 V22 V89} => {V01 V02 V13 V20 V22} Byref regs: 00000082 {rcx rdi} => 00000080 {rdi} IN00dc: mov dword ptr [rcx+8], eax Generating: N1021 ( 3, 2) [000823] -------N---- t823 = LCL_VAR_ADDR byref V76 tmp46 rcx REG rcx IN00dd: lea rcx, bword ptr [V76 rsp+38H] Byref regs: 00000080 {rdi} => 00000082 {rcx rdi} /--* t823 byref Generating: N1023 (???,???) [001069] ------------ t1069 = * PUTARG_REG byref REG rcx Byref regs: 00000082 {rcx rdi} => 00000080 {rdi} Byref regs: 00000080 {rdi} => 00000082 {rcx rdi} /--* t1069 byref arg0 in rcx Generating: N1025 ( 38, 24) [000218] --CXG------- t218 = * CALL long System.Numerics.BigInteger.op_Explicit REG rax $450 Byref regs: 00000082 {rcx rdi} => 00000080 {rdi} Call: GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi} IN00de: call System.Numerics.BigInteger:op_Explicit(System.Numerics.BigInteger):long /--* t218 long Generating: N1027 ( 38, 24) [000226] DA-XG------- * STORE_LCL_VAR long V24 loc21 d:2 rbx REG rbx IN00df: mov rbx, rax V24 in reg rbx is becoming live [000226] Live regs: 0000C0E0 {rbp rsi rdi r14 r15} => 0000C0E8 {rbx rbp rsi rdi r14 r15} Live vars: {V01 V02 V13 V20 V22} => {V01 V02 V13 V20 V22 V24} Generating: N1029 ( 3, 2) [000514] -c---------- t514 = LCL_VAR int (AX) V61 tmp31 NA REG NA $250 Generating: N1031 ( 1, 1) [000515] -c---------- t515 = CNS_INT int 0 REG NA $40 /--* t514 int +--* t515 int Generating: N1033 ( 8, 4) [000516] ----G------- t516 = * EQ int REG r12 $369 IN00e0: cmp dword ptr [V61 rsp+98H], 0 IN00e1: sete r12b IN00e2: movzx r12, r12b /--* t516 int Generating: N1035 ( 12, 7) [000232] DA--G------- * STORE_LCL_VAR int V25 loc22 d:2 r12 REG r12 V25 in reg r12 is becoming live [000232] Live regs: 0000C0E8 {rbx rbp rsi rdi r14 r15} => 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} Live vars: {V01 V02 V13 V20 V22 V24} => {V01 V02 V13 V20 V22 V24 V25} Generating: N1037 ( 1, 1) [000233] ------------ t233 = LCL_VAR long V24 loc21 u:2 rbx REG rbx $450 /--* t233 long Generating: N1039 (???,???) [001070] ------------ t1070 = * PUTARG_REG long REG rcx IN00e3: mov rcx, rbx /--* t1070 long arg0 in rcx Generating: N1041 ( 15, 7) [000234] --CXG------- t234 = * CALL int Microsoft.CodeAnalysis.RealParser.CountSignificantBits REG rax $2b4 Call: GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi} IN00e4: call Microsoft.CodeAnalysis.RealParser:CountSignificantBits(long):int /--* t234 int Generating: N1043 ( 19, 10) [000237] DA-XG------- * STORE_LCL_VAR int V26 loc23 d:2 rax REG rax V26 in reg rax is becoming live [000237] Live regs: 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} => 0000D0E9 {rax rbx rbp rsi rdi r12 r14 r15} Live vars: {V01 V02 V13 V20 V22 V24 V25} => {V01 V02 V13 V20 V22 V24 V25 V26} Added IP mapping: 0x019E STACK_EMPTY (G_M6661_IG27,ins#31,ofs#165) Generating: N1045 (???,???) [000975] ------------ IL_OFFSET void IL offset: 0x19e REG NA Generating: N1047 ( 3, 2) [000238] ------------ t238 = LCL_VAR int V26 loc23 u:2 rax REG rax $2b4 Generating: N1049 ( 3, 2) [000239] ------------ t239 = LCL_VAR int V20 loc17 u:2 r14 REG r14 $362 /--* t238 int +--* t239 int Generating: N1051 ( 7, 5) [000240] N------N-U-- * LE void REG NA $36a IN00e5: cmp eax, r14d Generating: N1053 ( 9, 7) [000241] ------------ * JTRUE void REG NA IN00e6: jbe L_M6661_BB40 Scope info: end block BB35, IL range [16F..1A4) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 20 (V20 loc17) [000..202) =============== Generating BB36 [1A4..1AF) -> BB38 (cond), preds={BB35} succs={BB37,BB38} flags=0x00000000.40080020: i gcsafe LIR BB36 IN (8)={V01 V02 V13 V20 V24 V25 V26 V22} + ByrefExposed + GcHeap OUT(7)={V01 V02 V13 V20 V24 V29 V22} + ByrefExposed + GcHeap Recording Var Locations at start of BB36 V01(rsi) V02(rdi) V13(r15) V20(r14) V24(rbx) V25(r12) V26(rax) V22(rbp) Liveness not changing: 000801000400060D {V01 V02 V13 V20 V22 V24 V25 V26} Live regs: 00000000 {} => 0000D0E9 {rax rbx rbp rsi rdi r12 r14 r15} GC regs: 00000000 {} => 00000040 {rsi} Byref regs: 00000000 {} => 00000080 {rdi} L_M6661_BB36: Scope info: begin block BB36, IL range [1A4..1AF) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 20 (V20 loc17) [000..202) 24 (V24 loc21) [000..202) 25 (V25 loc22) [000..202) 26 (V26 loc23) [000..202) 22 (V22 loc19) [000..202) Added IP mapping: 0x01A4 STACK_EMPTY (G_M6661_IG27,ins#33,ofs#174) label Generating: N1057 (???,???) [000976] ------------ IL_OFFSET void IL offset: 0x1a4 REG NA Generating: N1059 ( 3, 2) [000282] ------------ t282 = LCL_VAR int V26 loc23 u:2 rax (last use) REG rax $2b4 Generating: N1061 ( 3, 2) [000283] ------------ t283 = LCL_VAR int V20 loc17 u:2 r14 REG r14 $362 /--* t282 int +--* t283 int Generating: N1063 ( 7, 5) [000284] ------------ t284 = * SUB int REG rax $36b V26 in reg rax is becoming dead [000282] Live regs: 0000D0E9 {rax rbx rbp rsi rdi r12 r14 r15} => 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} Live vars: {V01 V02 V13 V20 V22 V24 V25 V26} => {V01 V02 V13 V20 V22 V24 V25} IN00e7: sub eax, r14d /--* t284 int Generating: N1065 ( 11, 8) [000286] DA---------- * STORE_LCL_VAR int V29 loc26 d:2 rax REG rax V29 in reg rax is becoming live [000286] Live regs: 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} => 0000D0E9 {rax rbx rbp rsi rdi r12 r14 r15} Live vars: {V01 V02 V13 V20 V22 V24 V25} => {V01 V02 V13 V20 V22 V24 V25 V29} Added IP mapping: 0x01AB STACK_EMPTY (G_M6661_IG27,ins#34,ofs#177) Generating: N1067 (???,???) [000977] ------------ IL_OFFSET void IL offset: 0x1ab REG NA Generating: N1069 ( 3, 2) [000287] ------------ t287 = LCL_VAR int V25 loc22 u:2 r12 (last use) REG r12 $369 Generating: N1071 ( 1, 1) [000288] -c---------- t288 = CNS_INT int 0 REG NA $40 /--* t287 int +--* t288 int Generating: N1073 ( 5, 4) [000289] J------N---- * EQ void REG NA $36c V25 in reg r12 is becoming dead [000287] Live regs: 0000D0E9 {rax rbx rbp rsi rdi r12 r14 r15} => 0000C0E9 {rax rbx rbp rsi rdi r14 r15} Live vars: {V01 V02 V13 V20 V22 V24 V25 V29} => {V01 V02 V13 V20 V22 V24 V29} IN00e8: test r12d, r12d Generating: N1075 ( 7, 6) [000290] ------------ * JTRUE void REG NA IN00e9: je L_M6661_BB38 Scope info: end block BB36, IL range [1A4..1AF) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 20 (V20 loc17) [000..202) 24 (V24 loc21) [000..202) 22 (V22 loc19) [000..202) =============== Generating BB37 [1AF..1C3) -> BB39 (always), preds={BB36} succs={BB39} flags=0x00000000.40080020: i gcsafe LIR BB37 IN (7)={V01 V02 V13 V20 V24 V29 V22} + ByrefExposed + GcHeap OUT(8)={V01 V02 V13 V20 V24 V29 V37 V22} + ByrefExposed + GcHeap Recording Var Locations at start of BB37 V01(rsi) V02(rdi) V13(r15) V20(r14) V24(rbx) V29(rax) V22(rbp) Liveness not changing: 000802000000060D {V01 V02 V13 V20 V22 V24 V29} Live regs: 00000000 {} => 0000C0E9 {rax rbx rbp rsi rdi r14 r15} GC regs: 00000000 {} => 00000040 {rsi} Byref regs: 00000000 {} => 00000080 {rdi} L_M6661_BB37: Scope info: begin block BB37, IL range [1AF..1C3) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 20 (V20 loc17) [000..202) 24 (V24 loc21) [000..202) 22 (V22 loc19) [000..202) 29 (V29 loc26) [000..202) Added IP mapping: 0x01AF STACK_EMPTY (G_M6661_IG27,ins#36,ofs#186) label Generating: N1079 (???,???) [000978] ------------ IL_OFFSET void IL offset: 0x1af REG NA Generating: N1081 ( 1, 1) [000305] ------------ t305 = LCL_VAR long V24 loc21 u:2 rbx REG rbx $450 Generating: N1083 ( 3, 2) [000308] ------------ t308 = LCL_VAR int V29 loc26 u:2 rax REG rax $36b Generating: N1085 ( 1, 1) [000307] ------------ t307 = CNS_INT long 1 REG rdx $103 IN00ea: mov edx, 1 /--* t307 long +--* t308 int Generating: N1087 ( 10, 6) [000311] ------------ t311 = * LSH long REG rdx $48e IN00eb: mov ecx, eax IN00ec: shl rdx, cl Generating: N1089 ( 1, 1) [000313] -c---------- t313 = CNS_INT long -1 REG NA $104 /--* t311 long +--* t313 long Generating: N1091 ( 12, 8) [000314] ------------ t314 = * ADD long REG rdx $48f IN00ed: dec rdx /--* t305 long +--* t314 long Generating: N1093 ( 19, 12) [000318] ------------ t318 = * TEST_EQ int REG rcx $36e IN00ee: test rbx, rdx IN00ef: sete cl IN00f0: movzx rcx, cl /--* t318 int Generating: N1095 ( 23, 15) [000320] DA---------- * STORE_LCL_VAR int V37 tmp7 d:4 rcx REG rcx V37 in reg rcx is becoming live [000320] Live regs: 0000C0E9 {rax rbx rbp rsi rdi r14 r15} => 0000C0EB {rax rcx rbx rbp rsi rdi r14 r15} Live vars: {V01 V02 V13 V20 V22 V24 V29} => {V01 V02 V13 V20 V22 V24 V29 V37} Scope info: end block BB37, IL range [1AF..1C3) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 20 (V20 loc17) [000..202) 24 (V24 loc21) [000..202) 22 (V22 loc19) [000..202) 29 (V29 loc26) [000..202) IN00f1: jmp L_M6661_BB39 =============== Generating BB38 [1C3..1C4), preds={BB36} succs={BB39} flags=0x00000000.400b0020: i label target gcsafe LIR BB38 IN (7)={V01 V02 V13 V20 V24 V29 V22} + ByrefExposed + GcHeap OUT(8)={V01 V02 V13 V20 V24 V29 V37 V22} + ByrefExposed + GcHeap Recording Var Locations at start of BB38 V01(rsi) V02(rdi) V13(r15) V20(r14) V24(rbx) V29(rax) V22(rbp) Change life 000842000000060D {V01 V02 V13 V20 V22 V24 V29 V37} -> 000802000000060D {V01 V02 V13 V20 V22 V24 V29} V37 in reg rcx is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: 00000000 {} => 0000C0E9 {rax rbx rbp rsi rdi r14 r15} GC regs: 00000000 {} => 00000040 {rsi} Byref regs: 00000000 {} => 00000080 {rdi} L_M6661_BB38: G_M6661_IG27: ; offs=000665H, funclet=00, bbWeight=0.50 Label: IG28, GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi} Scope info: begin block BB38, IL range [1C3..1C4) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 20 (V20 loc17) [000..202) 24 (V24 loc21) [000..202) 22 (V22 loc19) [000..202) 29 (V29 loc26) [000..202) Added IP mapping: 0x01C3 STACK_EMPTY (G_M6661_IG28,ins#0,ofs#0) label Generating: N1099 (???,???) [000979] ------------ IL_OFFSET void IL offset: 0x1c3 REG NA Generating: N1101 ( 1, 1) [000291] ------------ t291 = CNS_INT int 0 REG rcx $40 IN00f2: xor ecx, ecx /--* t291 int Generating: N1103 ( 5, 4) [000293] DA---------- * STORE_LCL_VAR int V37 tmp7 d:3 rcx REG rcx V37 in reg rcx is becoming live [000293] Live regs: 0000C0E9 {rax rbx rbp rsi rdi r14 r15} => 0000C0EB {rax rcx rbx rbp rsi rdi r14 r15} Live vars: {V01 V02 V13 V20 V22 V24 V29} => {V01 V02 V13 V20 V22 V24 V29 V37} Scope info: end block BB38, IL range [1C3..1C4) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 20 (V20 loc17) [000..202) 24 (V24 loc21) [000..202) 22 (V22 loc19) [000..202) 29 (V29 loc26) [000..202) =============== Generating BB39 [1C4..1D0), preds={BB37,BB38} succs={BB40} flags=0x00000000.400b0020: i label target gcsafe LIR BB39 IN (8)={V01 V02 V13 V20 V24 V29 V37 V22} + ByrefExposed + GcHeap OUT(7)={V01 V02 V13 V20 V24 V25 V22} + ByrefExposed + GcHeap Recording Var Locations at start of BB39 V01(rsi) V02(rdi) V13(r15) V20(r14) V24(rbx) V29(rax) V37(rcx) V22(rbp) Liveness not changing: 000842000000060D {V01 V02 V13 V20 V22 V24 V29 V37} Live regs: 00000000 {} => 0000C0EB {rax rcx rbx rbp rsi rdi r14 r15} GC regs: 00000000 {} => 00000040 {rsi} Byref regs: 00000000 {} => 00000080 {rdi} L_M6661_BB39: G_M6661_IG28: ; offs=00073AH, funclet=00, bbWeight=0.50 Label: IG29, GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi} Scope info: begin block BB39, IL range [1C4..1D0) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 20 (V20 loc17) [000..202) 24 (V24 loc21) [000..202) 22 (V22 loc19) [000..202) 29 (V29 loc26) [000..202) Generating: N1107 ( 3, 2) [000295] ------------ t295 = LCL_VAR int V37 tmp7 u:2 rcx (last use) REG rcx $251 /--* t295 int Generating: N1109 ( 4, 4) [000826] ------------ t826 = * CAST int <- bool <- int REG r12 $36f V37 in reg rcx is becoming dead [000295] Live regs: 0000C0EB {rax rcx rbx rbp rsi rdi r14 r15} => 0000C0E9 {rax rbx rbp rsi rdi r14 r15} Live vars: {V01 V02 V13 V20 V22 V24 V29 V37} => {V01 V02 V13 V20 V22 V24 V29} IN00f3: movzx r12, cl /--* t826 int Generating: N1111 ( 8, 7) [000297] DA---------- * STORE_LCL_VAR int V25 loc22 d:4 r12 REG r12 V25 in reg r12 is becoming live [000297] Live regs: 0000C0E9 {rax rbx rbp rsi rdi r14 r15} => 0000D0E9 {rax rbx rbp rsi rdi r12 r14 r15} Live vars: {V01 V02 V13 V20 V22 V24 V29} => {V01 V02 V13 V20 V22 V24 V25 V29} Added IP mapping: 0x01C6 STACK_EMPTY (G_M6661_IG29,ins#1,ofs#4) label Generating: N1113 (???,???) [000980] ------------ IL_OFFSET void IL offset: 0x1c6 REG NA Generating: N1115 ( 1, 1) [000298] ------------ t298 = LCL_VAR long V24 loc21 u:2 rbx (last use) REG rbx $450 Generating: N1117 ( 3, 2) [000299] ------------ t299 = LCL_VAR int V29 loc26 u:2 rax (last use) REG rax $36b /--* t298 long +--* t299 int Generating: N1119 ( 10, 6) [000302] ------------ t302 = * RSZ long REG rbx $491 V24 in reg rbx is becoming dead [000298] Live regs: 0000D0E9 {rax rbx rbp rsi rdi r12 r14 r15} => 0000D0E1 {rax rbp rsi rdi r12 r14 r15} Live vars: {V01 V02 V13 V20 V22 V24 V25 V29} => {V01 V02 V13 V20 V22 V25 V29} V29 in reg rax is becoming dead [000299] Live regs: 0000D0E1 {rax rbp rsi rdi r12 r14 r15} => 0000D0E0 {rbp rsi rdi r12 r14 r15} Live vars: {V01 V02 V13 V20 V22 V25 V29} => {V01 V02 V13 V20 V22 V25} IN00f4: mov ecx, eax IN00f5: shr rbx, cl /--* t302 long Generating: N1121 ( 10, 6) [000304] DA---------- * STORE_LCL_VAR long V24 loc21 d:4 rbx REG rbx V24 in reg rbx is becoming live [000304] Live regs: 0000D0E0 {rbp rsi rdi r12 r14 r15} => 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} Live vars: {V01 V02 V13 V20 V22 V25} => {V01 V02 V13 V20 V22 V24 V25} Scope info: end block BB39, IL range [1C4..1D0) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 20 (V20 loc17) [000..202) 22 (V22 loc19) [000..202) =============== Generating BB40 [1D0..1E7) -> BB42 (cond), preds={BB35,BB39} succs={BB41,BB42} flags=0x00000004.400b0020: i label target hascall gcsafe LIR BB40 IN (7)={V01 V02 V13 V20 V24 V25 V22 } + ByrefExposed + GcHeap OUT(6)={V01 V02 V13 V25 V22 V27} + ByrefExposed + GcHeap Recording Var Locations at start of BB40 V01(rsi) V02(rdi) V13(r15) V20(r14) V24(rbx) V25(r12) V22(rbp) Liveness not changing: 000800000400060D {V01 V02 V13 V20 V22 V24 V25} Live regs: 00000000 {} => 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} GC regs: 00000000 {} => 00000040 {rsi} Byref regs: 00000000 {} => 00000080 {rdi} L_M6661_BB40: G_M6661_IG29: ; offs=00073CH, funclet=00, bbWeight=0.50 Label: IG30, GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi} Scope info: begin block BB40, IL range [1D0..1E7) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 20 (V20 loc17) [000..202) 22 (V22 loc19) [000..202) 24 (V24 loc21) [000..202) 25 (V25 loc22) [000..202) Generating: N1125 ( 3, 2) [000831] -------N---- t831 = LCL_VAR_ADDR byref V76 tmp46 rcx REG rcx IN00f6: lea rcx, bword ptr [V76 rsp+38H] Byref regs: 00000080 {rdi} => 00000082 {rcx rdi} /--* t831 byref Generating: N1127 ( 3, 3) [000833] DA---------- * STORE_LCL_VAR byref V90 tmp60 d:2 rcx REG rcx Byref regs: 00000082 {rcx rdi} => 00000080 {rdi} V90 in reg rcx is becoming live [000833] Live regs: 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} => 0000D0EA {rcx rbx rbp rsi rdi r12 r14 r15} Live vars: {V01 V02 V13 V20 V22 V24 V25} => {V01 V02 V13 V20 V22 V24 V25 V90} Byref regs: 00000080 {rdi} => 00000082 {rcx rdi} Generating: N1129 ( 1, 1) [000834] ------------ t834 = LCL_VAR byref V90 tmp60 u:2 rcx Zero Fseq[_bits] REG rcx $426 Generating: N1131 ( 3, 2) [000836] -------N---- t836 = LCL_VAR ref (AX) V54 tmp24 rax REG rax $18b IN00f7: mov rax, gword ptr [V54 rsp+D0H] GC regs: 00000040 {rsi} => 00000041 {rax rsi} /--* t834 byref +--* t836 ref Generating: N1133 (???,???) [000981] -A--G------- * STOREIND ref REG NA GC regs: 00000041 {rax rsi} => 00000040 {rsi} IN00f8: mov gword ptr [rcx], rax Generating: N1135 ( 1, 1) [000839] ------------ t839 = LCL_VAR byref V90 tmp60 u:2 rcx (last use) REG rcx $426 /--* t839 byref Generating: N1137 ( 2, 2) [000841] -c---------- t841 = * LEA(b+8) byref REG NA Generating: N1139 ( 3, 2) [000843] -------N---- t843 = LCL_VAR int (AX) V55 tmp25 rax REG rax $252 IN00f9: mov eax, dword ptr [V55 rsp+D8H] /--* t841 byref +--* t843 int Generating: N1141 (???,???) [000982] -A--G-----L- * STOREIND int REG NA V90 in reg rcx is becoming dead [000839] Live regs: 0000D0EA {rcx rbx rbp rsi rdi r12 r14 r15} => 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} Live vars: {V01 V02 V13 V20 V22 V24 V25 V90} => {V01 V02 V13 V20 V22 V24 V25} Byref regs: 00000082 {rcx rdi} => 00000080 {rdi} IN00fa: mov dword ptr [rcx+8], eax Generating: N1143 ( 3, 2) [000846] -------N---- t846 = LCL_VAR_ADDR byref V76 tmp46 rcx REG rcx IN00fb: lea rcx, bword ptr [V76 rsp+38H] Byref regs: 00000080 {rdi} => 00000082 {rcx rdi} /--* t846 byref Generating: N1145 (???,???) [001071] ------------ t1071 = * PUTARG_REG byref REG rcx Byref regs: 00000082 {rcx rdi} => 00000080 {rdi} Byref regs: 00000080 {rdi} => 00000082 {rcx rdi} /--* t1071 byref arg0 in rcx Generating: N1147 ( 38, 24) [000243] --CXG------- t243 = * CALL long System.Numerics.BigInteger.op_Explicit REG rax $454 Byref regs: 00000082 {rcx rdi} => 00000080 {rdi} Call: GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi} IN00fc: call System.Numerics.BigInteger:op_Explicit(System.Numerics.BigInteger):long Generating: N1149 ( 3, 2) [000247] ------------ t247 = LCL_VAR int V20 loc17 u:2 r14 (last use) REG r14 $362 /--* t243 long +--* t247 int Generating: N1151 ( 47, 29) [000250] ---XG------- t250 = * LSH long REG rax $492 V20 in reg r14 is becoming dead [000247] Live regs: 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} => 000090E8 {rbx rbp rsi rdi r12 r15} Live vars: {V01 V02 V13 V20 V22 V24 V25} => {V01 V02 V13 V22 V24 V25} IN00fd: mov ecx, r14d IN00fe: shl rax, cl Generating: N1153 ( 1, 1) [000251] ------------ t251 = LCL_VAR long V24 loc21 u:3 rbx (last use) REG rbx $580 /--* t250 long +--* t251 long Generating: N1155 ( 49, 31) [000252] ---XG------- t252 = * ADD long REG rdx $493 V24 in reg rbx is becoming dead [000251] Live regs: 000090E8 {rbx rbp rsi rdi r12 r15} => 000090E0 {rbp rsi rdi r12 r15} Live vars: {V01 V02 V13 V22 V24 V25} => {V01 V02 V13 V22 V25} IN00ff: lea rdx, [rax+rbx] /--* t252 long Generating: N1157 ( 53, 34) [000254] DA-XG------- * STORE_LCL_VAR long V27 loc24 d:2 rdx REG rdx V27 in reg rdx is becoming live [000254] Live regs: 000090E0 {rbp rsi rdi r12 r15} => 000090E4 {rdx rbp rsi rdi r12 r15} Live vars: {V01 V02 V13 V22 V25} => {V01 V02 V13 V22 V25 V27} Added IP mapping: 0x01E2 STACK_EMPTY (G_M6661_IG30,ins#10,ofs#46) label Generating: N1159 (???,???) [000983] ------------ IL_OFFSET void IL offset: 0x1e2 REG NA Generating: N1161 ( 1, 1) [000255] ------------ t255 = LCL_VAR int V13 loc10 u:2 r15 REG r15 $293 Generating: N1163 ( 1, 1) [000256] -c---------- t256 = CNS_INT int 0 REG NA $40 /--* t255 int +--* t256 int Generating: N1165 ( 3, 3) [000257] N------N---- * NE void REG NA $35a IN0100: test r15d, r15d Generating: N1167 ( 5, 5) [000258] ------------ * JTRUE void REG NA IN0101: jne L_M6661_BB42 Scope info: end block BB40, IL range [1D0..1E7) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 13 (V13 loc10) [000..202) 22 (V22 loc19) [000..202) 25 (V25 loc22) [000..202) =============== Generating BB41 [1E7..1EE) -> BB43 (always), preds={BB40} succs={BB43} flags=0x00000000.40080020: i gcsafe LIR BB41 IN (5)={V01 V02 V25 V22 V27} + ByrefExposed + GcHeap OUT(5)={V01 V02 V25 V36 V27} + ByrefExposed + GcHeap Recording Var Locations at start of BB41 V01(rsi) V02(rdi) V25(r12) V22(rbp) V27(rdx) Change life 001800000400000D {V01 V02 V13 V22 V25 V27} -> 0018000004000005 {V01 V02 V22 V25 V27} V13 in reg r15 is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: 00000000 {} => 000010E4 {rdx rbp rsi rdi r12} GC regs: 00000000 {} => 00000040 {rsi} Byref regs: 00000000 {} => 00000080 {rdi} L_M6661_BB41: Scope info: begin block BB41, IL range [1E7..1EE) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 22 (V22 loc19) [000..202) 25 (V25 loc22) [000..202) 27 (V27 loc24) [000..202) Added IP mapping: 0x01E7 STACK_EMPTY (G_M6661_IG30,ins#12,ofs#55) label Generating: N1171 (???,???) [000984] ------------ IL_OFFSET void IL offset: 0x1e7 REG NA Generating: N1173 ( 3, 2) [000275] ------------ t275 = LCL_VAR int V22 loc19 u:2 rbp (last use) REG rbp $24c /--* t275 int Generating: N1175 ( 4, 3) [000276] ------------ t276 = * NEG int REG r8 $2c2 V22 in reg rbp is becoming dead [000275] Live regs: 000010E4 {rdx rbp rsi rdi r12} => 000010C4 {rdx rsi rdi r12} Live vars: {V01 V02 V22 V25 V27} => {V01 V02 V25 V27} IN0102: mov r8d, ebp IN0103: neg r8d Generating: N1177 ( 1, 1) [000277] -c---------- t277 = CNS_INT int -1 REG NA $43 /--* t276 int +--* t277 int Generating: N1179 ( 6, 5) [000278] ------------ t278 = * ADD int REG r8 $372 IN0104: dec r8d /--* t278 int Generating: N1181 ( 10, 8) [000280] DA---------- * STORE_LCL_VAR int V36 tmp6 d:4 r8 REG r8 V36 in reg r8 is becoming live [000280] Live regs: 000010C4 {rdx rsi rdi r12} => 000011C4 {rdx rsi rdi r8 r12} Live vars: {V01 V02 V25 V27} => {V01 V02 V25 V27 V36} Scope info: end block BB41, IL range [1E7..1EE) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 25 (V25 loc22) [000..202) 27 (V27 loc24) [000..202) IN0105: jmp L_M6661_BB43 =============== Generating BB42 [1EE..1F2), preds={BB40} succs={BB43} flags=0x00000000.400b0020: i label target gcsafe LIR BB42 IN (5)={V01 V02 V13 V25 V27} + ByrefExposed + GcHeap OUT(5)={V01 V02 V25 V36 V27} + ByrefExposed + GcHeap Recording Var Locations at start of BB42 V01(rsi) V02(rdi) V13(r15) V25(r12) V27(rdx) Change life 0010200004000005 {V01 V02 V25 V27 V36} -> 001000000400000D {V01 V02 V13 V25 V27} V36 in reg r8 is becoming dead [------] Live regs: (unchanged) 00000000 {} V13 in reg r15 is becoming live [------] Live regs: 00000000 {} => 00008000 {r15} Live regs: 00008000 {r15} => 000090C4 {rdx rsi rdi r12 r15} GC regs: 00000000 {} => 00000040 {rsi} Byref regs: 00000000 {} => 00000080 {rdi} L_M6661_BB42: G_M6661_IG30: ; offs=000745H, funclet=00, bbWeight=0.50 Label: IG31, GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi} Scope info: begin block BB42, IL range [1EE..1F2) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 25 (V25 loc22) [000..202) 27 (V27 loc24) [000..202) 13 (V13 loc10) [000..202) Added IP mapping: 0x01EE STACK_EMPTY (G_M6661_IG31,ins#0,ofs#0) label Generating: N1185 (???,???) [000985] ------------ IL_OFFSET void IL offset: 0x1ee REG NA Generating: N1187 ( 1, 1) [000259] ------------ t259 = LCL_VAR int V13 loc10 u:2 r15 (last use) REG r15 $293 Generating: N1189 ( 1, 1) [000260] -c---------- t260 = CNS_INT int -2 REG NA $68 /--* t259 int +--* t260 int Generating: N1191 ( 3, 3) [000261] ------------ t261 = * ADD int REG r8 $371 V13 in reg r15 is becoming dead [000259] Live regs: 000090C4 {rdx rsi rdi r12 r15} => 000010C4 {rdx rsi rdi r12} Live vars: {V01 V02 V13 V25 V27} => {V01 V02 V25 V27} IN0106: lea r8d, [r15-2] /--* t261 int Generating: N1193 ( 7, 6) [000263] DA---------- * STORE_LCL_VAR int V36 tmp6 d:3 r8 REG r8 V36 in reg r8 is becoming live [000263] Live regs: 000010C4 {rdx rsi rdi r12} => 000011C4 {rdx rsi rdi r8 r12} Live vars: {V01 V02 V25 V27} => {V01 V02 V25 V27 V36} Scope info: end block BB42, IL range [1EE..1F2) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 25 (V25 loc22) [000..202) 27 (V27 loc24) [000..202) =============== Generating BB43 [1F2..202), preds={BB41,BB42} succs={BB44} flags=0x00000004.400b0020: i label target hascall gcsafe LIR BB43 IN (5)={V01 V02 V25 V36 V27} + ByrefExposed + GcHeap OUT(1)={ V51 } Recording Var Locations at start of BB43 V01(rsi) V02(rdi) V25(r12) V36(r8) V27(rdx) Liveness not changing: 0010200004000005 {V01 V02 V25 V27 V36} Live regs: 00000000 {} => 000011C4 {rdx rsi rdi r8 r12} GC regs: 00000000 {} => 00000040 {rsi} Byref regs: 00000000 {} => 00000080 {rdi} L_M6661_BB43: G_M6661_IG31: ; offs=00078AH, funclet=00, bbWeight=0.50 Label: IG32, GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi} Scope info: begin block BB43, IL range [1F2..202) Scope info: open scopes = 1 (V01 arg1) [000..202) 2 (V02 arg2) [000..202) 25 (V25 loc22) [000..202) 27 (V27 loc24) [000..202) Added IP mapping: 0x01F4 STACK_EMPTY (G_M6661_IG32,ins#0,ofs#0) label Generating: N1197 (???,???) [000986] ------------ IL_OFFSET void IL offset: 0x1f4 REG NA Generating: N1199 ( 1, 1) [000272] ------------ t272 = LCL_VAR byref V02 arg2 u:1 rdi (last use) REG rdi $81 /--* t272 byref Generating: N1201 (???,???) [001072] ------------ * PUTARG_STK [+0x20] void REG NA V02 in reg rdi is becoming dead [000272] Live regs: 000011C4 {rdx rsi rdi r8 r12} => 00001144 {rdx rsi r8 r12} Live vars: {V01 V02 V25 V27 V36} => {V01 V25 V27 V36} Byref regs: 00000080 {rdi} => 00000000 {} IN0107: mov bword ptr [V30+0x20 rsp+20H], rdi Generating: N1203 ( 1, 1) [000268] ------------ t268 = LCL_VAR ref V01 arg1 u:1 rsi (last use) REG rsi $c0 /--* t268 ref Generating: N1205 (???,???) [001073] ------------ t1073 = * PUTARG_REG ref REG rcx V01 in reg rsi is becoming dead [000268] Live regs: 00001144 {rdx rsi r8 r12} => 00001104 {rdx r8 r12} Live vars: {V01 V25 V27 V36} => {V25 V27 V36} GC regs: 00000040 {rsi} => 00000000 {} IN0108: mov rcx, rsi GC regs: 00000000 {} => 00000002 {rcx} Generating: N1207 ( 3, 2) [000269] ------------ t269 = LCL_VAR long V27 loc24 u:2 rdx (last use) REG rdx $493 /--* t269 long Generating: N1209 (???,???) [001074] ------------ t1074 = * PUTARG_REG long REG rdx V27 in reg rdx is becoming dead [000269] Live regs: 00001104 {rdx r8 r12} => 00001100 {r8 r12} Live vars: {V25 V27 V36} => {V25 V36} Generating: N1211 ( 3, 2) [000270] ------------ t270 = LCL_VAR int V36 tmp6 u:2 r8 (last use) REG r8 $253 /--* t270 int Generating: N1213 (???,???) [001075] ------------ t1075 = * PUTARG_REG int REG r8 V36 in reg r8 is becoming dead [000270] Live regs: 00001100 {r8 r12} => 00001000 {r12} Live vars: {V25 V36} => {V25} Generating: N1215 ( 3, 2) [000271] ------------ t271 = LCL_VAR int V25 loc22 u:3 r12 (last use) REG r12 $540 /--* t271 int Generating: N1217 (???,???) [001076] ------------ t1076 = * PUTARG_REG int REG r9 V25 in reg r12 is becoming dead [000271] Live regs: 00001000 {r12} => 00000000 {} Live vars: {V25} => {} IN0109: mov r9d, r12d /--* t1073 ref this in rcx +--* t1074 long arg1 in rdx +--* t1075 int arg2 in r8 +--* t1076 int arg3 in r9 Generating: N1219 ( 28, 18) [000273] --CXG------- t273 = * CALL int FloatingPointType.AssembleFloatingPointValue REG rax $2be GC regs: 00000002 {rcx} => 00000000 {} Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN010a: call FloatingPointType:AssembleFloatingPointValue(long,int,bool,byref):int:this /--* t273 int Generating: N1221 ( 28, 18) [000853] DA-XG------- * STORE_LCL_VAR int V51 tmp21 d:4 rax REG rax V51 in reg rax is becoming live [000853] Live regs: 00000000 {} => 00000001 {rax} Live vars: {} => {V51} Scope info: end block BB43, IL range [1F2..202) Scope info: ending scope, LVnum=0 [000..202) Scope info: ending scope, LVnum=1 [000..202) Scope info: ending scope, LVnum=2 [000..202) Scope info: ending scope, LVnum=3 [000..202) Scope info: ending scope, LVnum=4 [000..202) siEndScope: Failed to end scope for V04 Scope info: ending scope, LVnum=5 [000..202) Scope info: ending scope, LVnum=6 [000..202) siEndScope: Failed to end scope for V06 Scope info: ending scope, LVnum=7 [000..202) siEndScope: Failed to end scope for V07 Scope info: ending scope, LVnum=8 [000..202) Scope info: ending scope, LVnum=9 [000..202) Scope info: ending scope, LVnum=10 [000..202) Scope info: ending scope, LVnum=11 [000..202) siEndScope: Failed to end scope for V11 Scope info: ending scope, LVnum=12 [000..202) siEndScope: Failed to end scope for V12 Scope info: ending scope, LVnum=13 [000..202) Scope info: ending scope, LVnum=14 [000..202) Scope info: ending scope, LVnum=15 [000..202) siEndScope: Failed to end scope for V15 Scope info: ending scope, LVnum=16 [000..202) siEndScope: Failed to end scope for V16 Scope info: ending scope, LVnum=17 [000..202) Scope info: ending scope, LVnum=18 [000..202) Scope info: ending scope, LVnum=19 [000..202) Scope info: ending scope, LVnum=20 [000..202) Scope info: ending scope, LVnum=21 [000..202) Scope info: ending scope, LVnum=22 [000..202) Scope info: ending scope, LVnum=23 [000..202) siEndScope: Failed to end scope for V23 Scope info: ending scope, LVnum=24 [000..202) Scope info: ending scope, LVnum=25 [000..202) Scope info: ending scope, LVnum=26 [000..202) Scope info: ending scope, LVnum=27 [000..202) Scope info: ending scope, LVnum=28 [000..202) siEndScope: Failed to end scope for V28 Scope info: ending scope, LVnum=29 [000..202) Scope info: open scopes = =============== Generating BB44 [???..???) (return), preds={BB16,BB30,BB43} succs={} flags=0x00000000.400a0050: keep internal target gcsafe LIR BB44 IN (1)={V51} OUT(0)={ } Recording Var Locations at start of BB44 V51(rax) Liveness not changing: 0000000000000080 {V51} Live regs: 00000000 {} => 00000001 {rax} GC regs: (unchanged) 00000000 {} Byref regs: (unchanged) 00000000 {} L_M6661_BB44: G_M6661_IG32: ; offs=00078EH, funclet=00, bbWeight=0.50 Label: IG33, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} Scope info: begin block BB44, IL range [???..???) Scope info: ignoring block beginning Added IP mapping: NO_MAP STACK_EMPTY (G_M6661_IG33,ins#0,ofs#0) label Generating: N1225 ( 1, 1) [000522] -------N---- t522 = LCL_VAR int V51 tmp21 u:2 rax (last use) REG rax $254 /--* t522 int Generating: N1227 ( 2, 2) [000523] ------------ * RETURN int REG NA $5c9 V51 in reg rax is becoming dead [000522] Live regs: 00000001 {rax} => 00000000 {} Live vars: {V51} => {} Scope info: end block BB44, IL range [???..???) Scope info: ignoring block end Added IP mapping: EPILOG STACK_EMPTY (G_M6661_IG33,ins#0,ofs#0) label Reserving epilog IG for block BB44 IN010b: nop G_M6661_IG33: ; offs=00079EH, funclet=00, bbWeight=0.50 *************** After placeholder IG creation G_M6661_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG G_M6661_IG02: ; offs=000000H, size=0006H, gcrefRegs=00000040 {rsi}, byrefRegs=00000082 {rcx rdi}, byref G_M6661_IG03: ; offs=000006H, size=000AH, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG04: ; offs=000010H, size=0014H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG05: ; epilog placeholder, next placeholder=IG11 , BB03 [0001], epilog, extend <-- First placeholder ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000048 {rbx rsi}, PrevByrefRegs=00000080 {rdi} ; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000040 {rsi}, InitByrefRegs=00000080 {rdi} G_M6661_IG06: ; offs=000124H, size=0028H, gcVars=0000000000000000 {}, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, gcvars, byref G_M6661_IG07: ; offs=00014CH, size=0003H, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG08: ; offs=00014FH, size=0012H, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG09: ; offs=000161H, size=0003H, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG10: ; offs=000164H, size=006CH, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG11: ; epilog placeholder, next placeholder=IG18 , BB12 [0004], epilog, extend ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000048 {rbx rsi}, PrevByrefRegs=00000080 {rdi} ; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000048 {rbx rsi}, InitByrefRegs=00000080 {rdi} G_M6661_IG12: ; offs=0002D0H, size=0010H, gcVars=0000000000000000 {}, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, gcvars, byref G_M6661_IG13: ; offs=0002E0H, size=004EH, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG14: ; offs=00032EH, size=002DH, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG15: ; offs=00035BH, size=0016H, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG16: ; offs=000371H, size=000BH, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG17: ; offs=00037CH, size=004CH, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG18: ; epilog placeholder, next placeholder=IG34 , BB22 [0014], epilog, extend ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000048 {rbx rsi}, PrevByrefRegs=00000080 {rdi} ; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000048 {rbx rsi}, InitByrefRegs=00000080 {rdi} G_M6661_IG19: ; offs=0004C8H, size=000CH, gcVars=0000000000000000 {}, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, gcvars, byref G_M6661_IG20: ; offs=0004D4H, size=00E2H, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG21: ; offs=0005B6H, size=0004H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG22: ; offs=0005BAH, size=0017H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG23: ; offs=0005D1H, size=003BH, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG24: ; offs=00060CH, size=0005H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG25: ; offs=000611H, size=0052H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG26: ; offs=000663H, size=0002H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG27: ; offs=000665H, size=00D5H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG28: ; offs=00073AH, size=0002H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG29: ; offs=00073CH, size=0009H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG30: ; offs=000745H, size=0045H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG31: ; offs=00078AH, size=0004H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG32: ; offs=00078EH, size=0010H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG33: ; offs=00079EH, size=0001H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M6661_IG34: ; epilog placeholder, next placeholder=, BB44 [0054], epilog, extend <-- Last placeholder ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {} ; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {} Liveness not changing: 0000000000000000 {} # compCycleEstimate = 1242, compSizeEstimate = 901 Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int ; Final local variable assignments ; ; V00 arg0 [V00,T01] ( 4, 8 ) byref -> rcx ld-addr-op ; V01 arg1 [V01,T00] ( 15, 8.50) ref -> rsi class-hnd ; V02 arg2 [V02,T02] ( 8, 5 ) byref -> rdi ; V03 loc0 [V03,T34] ( 3, 1.50) int -> r14 ;* V04 loc1 [V04 ] ( 0, 0 ) int -> zero-ref ; V05 loc2 [V05,T24] ( 4, 2 ) int -> r15 ;* V06 loc3 [V06 ] ( 0, 0 ) int -> zero-ref ;* V07 loc4 [V07 ] ( 0, 0 ) int -> zero-ref ; V08 loc5 [V08,T25] ( 4, 2 ) int -> r12 ; V09 loc6 [V09,T35] ( 3, 1.50) int -> r13 ; V10 loc7 [V10,T23] ( 5, 2.50) int -> [rsp+0xE4] ; V11 loc8 [V11 ] ( 6, 3 ) struct (16) [rsp+0xD0] do-not-enreg[XS] must-init addr-exposed ld-addr-op ; V12 loc9 [V12 ] ( 3, 1.50) ref -> [rsp+0xC8] do-not-enreg[X] must-init addr-exposed ld-addr-op class-hnd ; V13 loc10 [V13,T03] ( 9, 4.50) int -> r15 ; V14 loc11 [V14,T36] ( 3, 1.50) int -> [rsp+0xC4] ; V15 loc12 [V15 ] ( 9, 4.50) struct (16) [rsp+0xB0] do-not-enreg[XS] must-init addr-exposed ld-addr-op ; V16 loc13 [V16 ] ( 9, 4.50) struct (16) [rsp+0xA0] do-not-enreg[XS] must-init addr-exposed ld-addr-op ; V17 loc14 [V17,T37] ( 3, 1.50) int -> rbx ; V18 loc15 [V18,T38] ( 3, 1.50) int -> rax ; V19 loc16 [V19,T08] ( 7, 3.50) int -> rbp ; V20 loc17 [V20,T09] ( 7, 3.50) int -> r14 ; V21 loc18 [V21,T39] ( 3, 1.50) int -> rbx ; V22 loc19 [V22,T51] ( 2, 1 ) int -> rbp ; V23 loc20 [V23 ] ( 2, 1 ) struct (16) [rsp+0x90] do-not-enreg[XS] must-init addr-exposed ld-addr-op ; V24 loc21 [V24,T10] ( 6, 3 ) long -> rbx ; V25 loc22 [V25,T26] ( 4, 2 ) bool -> r12 ; V26 loc23 [V26,T40] ( 3, 1.50) int -> rax ; V27 loc24 [V27,T52] ( 2, 1 ) long -> rdx ;* V28 loc25 [V28 ] ( 0, 0 ) int -> zero-ref ; V29 loc26 [V29,T41] ( 3, 1.50) int -> rax ; V30 OutArgs [V30 ] ( 1, 1 ) lclBlk (40) [rsp+0x00] "OutgoingArgSpace" ; V31 tmp1 [V31,T06] ( 4, 4 ) int -> r15 "dup spill" ; V32 tmp2 [V32,T42] ( 3, 1.50) int -> rdx ; V33 tmp3 [V33,T43] ( 3, 1.50) int -> rbp ; V34 tmp4 [V34,T44] ( 3, 1.50) int -> rbp ; V35 tmp5 [V35 ] ( 3, 3 ) struct (16) [rsp+0x80] do-not-enreg[XS] must-init addr-exposed "struct address for call/obj" ; V36 tmp6 [V36,T45] ( 3, 1.50) int -> r8 ; V37 tmp7 [V37,T46] ( 3, 1.50) int -> rcx ; V38 tmp8 [V38,T29] ( 2, 2 ) long -> [rsp+0x78] "impAppendStmt" ; V39 tmp9 [V39,T47] ( 3, 1.50) int -> r15 "Inline return value spill temp" ; V40 tmp10 [V40,T30] ( 2, 2 ) int -> rcx "Inlining Arg" ; V41 tmp11 [V41,T27] ( 4, 2 ) int -> r12 "Inline return value spill temp" ; V42 tmp12 [V42,T22] ( 3, 3 ) int -> r12 "Inlining Arg" ; V43 tmp13 [V43,T53] ( 2, 1 ) int -> rbx "Inline return value spill temp" ;* V44 tmp14 [V44 ] ( 0, 0 ) struct (16) zero-ref "Inlining Arg" ; V45 tmp15 [V45 ] ( 2, 1 ) ref -> [rsp+0x70] do-not-enreg[X] must-init addr-exposed ld-addr-op class-hnd "Inline ldloca(s) first use temp" ; V46 tmp16 [V46,T54] ( 2, 1 ) int -> rax "Inline return value spill temp" ;* V47 tmp17 [V47 ] ( 0, 0 ) struct (16) zero-ref "Inlining Arg" ; V48 tmp18 [V48 ] ( 2, 1 ) ref -> [rsp+0x68] do-not-enreg[X] must-init addr-exposed ld-addr-op class-hnd "Inline ldloca(s) first use temp" ; V49 tmp19 [V49 ] ( 3, 3 ) struct (16) [rsp+0x58] do-not-enreg[XS] must-init addr-exposed ld-addr-op "Inlining Arg" ;* V50 tmp20 [V50 ] ( 0, 0 ) struct (16) zero-ref "Inlining Arg" ; V51 tmp21 [V51,T07] ( 4, 4 ) int -> rax "Single return block return value" ; V52 tmp22 [V52,T04] ( 7, 4.50) ref -> rbx V72.Mantissa(offs=0x00) P-INDEP "field V00.Mantissa (fldOffset=0x0)" ; V53 tmp23 [V53,T05] ( 7, 4 ) int -> rbp V72.Exponent(offs=0x08) P-INDEP "field V00.Exponent (fldOffset=0x8)" ; V54 tmp24 [V54 ] ( 4, 2 ) ref -> [rsp+0xD0] do-not-enreg[X] addr-exposed V11._bits(offs=0x00) P-DEP "field V11._bits (fldOffset=0x0)" ; V55 tmp25 [V55 ] ( 4, 2 ) int -> [rsp+0xD8] do-not-enreg[X] addr-exposed V11._sign(offs=0x08) P-DEP "field V11._sign (fldOffset=0x8)" ; V56 tmp26 [V56 ] ( 6, 3 ) ref -> [rsp+0xB0] do-not-enreg[X] addr-exposed V15._bits(offs=0x00) P-DEP "field V15._bits (fldOffset=0x0)" ; V57 tmp27 [V57 ] ( 6, 3 ) int -> [rsp+0xB8] do-not-enreg[X] addr-exposed V15._sign(offs=0x08) P-DEP "field V15._sign (fldOffset=0x8)" ; V58 tmp28 [V58 ] ( 5, 2.50) ref -> [rsp+0xA0] do-not-enreg[X] addr-exposed V16._bits(offs=0x00) P-DEP "field V16._bits (fldOffset=0x0)" ; V59 tmp29 [V59 ] ( 5, 2.50) int -> [rsp+0xA8] do-not-enreg[X] addr-exposed V16._sign(offs=0x08) P-DEP "field V16._sign (fldOffset=0x8)" ; V60 tmp30 [V60 ] ( 1, 0.50) ref -> [rsp+0x90] do-not-enreg[X] addr-exposed V23._bits(offs=0x00) P-DEP "field V23._bits (fldOffset=0x0)" ; V61 tmp31 [V61 ] ( 2, 1 ) int -> [rsp+0x98] do-not-enreg[X] addr-exposed V23._sign(offs=0x08) P-DEP "field V23._sign (fldOffset=0x8)" ; V62 tmp32 [V62 ] ( 2, 1.50) ref -> [rsp+0x80] do-not-enreg[X] addr-exposed V35._bits(offs=0x00) P-DEP "field V35._bits (fldOffset=0x0)" ; V63 tmp33 [V63 ] ( 2, 1.50) int -> [rsp+0x88] do-not-enreg[X] addr-exposed V35._sign(offs=0x08) P-DEP "field V35._sign (fldOffset=0x8)" ; V64 tmp34 [V64,T48] ( 2, 1 ) ref -> rcx V44._bits(offs=0x00) P-INDEP "field V44._bits (fldOffset=0x0)" ; V65 tmp35 [V65,T55] ( 2, 1 ) int -> rdx V44._sign(offs=0x08) P-INDEP "field V44._sign (fldOffset=0x8)" ; V66 tmp36 [V66,T49] ( 2, 1 ) ref -> rcx V47._bits(offs=0x00) P-INDEP "field V47._bits (fldOffset=0x0)" ; V67 tmp37 [V67,T56] ( 2, 1 ) int -> rdx V47._sign(offs=0x08) P-INDEP "field V47._sign (fldOffset=0x8)" ; V68 tmp38 [V68 ] ( 2, 1.50) ref -> [rsp+0x58] do-not-enreg[X] addr-exposed V49._bits(offs=0x00) P-DEP "field V49._bits (fldOffset=0x0)" ; V69 tmp39 [V69 ] ( 2, 1.50) int -> [rsp+0x60] do-not-enreg[X] addr-exposed V49._sign(offs=0x08) P-DEP "field V49._sign (fldOffset=0x8)" ; V70 tmp40 [V70,T50] ( 2, 1 ) ref -> rcx V50._bits(offs=0x00) P-INDEP "field V50._bits (fldOffset=0x0)" ; V71 tmp41 [V71,T57] ( 2, 1 ) int -> rdx V50._sign(offs=0x08) P-INDEP "field V50._sign (fldOffset=0x8)" ;* V72 tmp42 [V72 ] ( 0, 0 ) struct (16) zero-ref "Promoted implicit byref" ; V73 tmp43 [V73 ] ( 4, 4 ) struct (16) [rsp+0x48] do-not-enreg[XSB] must-init addr-exposed "by-value struct argument" ; V74 tmp44 [V74,T11] ( 3, 3 ) byref -> rdx stack-byref "BlockOp address local" ; V75 tmp45 [V75,T31] ( 2, 2 ) long -> rcx "argument with side effect" ; V76 tmp46 [V76 ] ( 14, 14 ) struct (16) [rsp+0x38] do-not-enreg[XSB] must-init addr-exposed "by-value struct argument" ; V77 tmp47 [V77,T12] ( 3, 3 ) byref -> rcx stack-byref "BlockOp address local" ; V78 tmp48 [V78,T13] ( 3, 3 ) byref -> rdx stack-byref "BlockOp address local" ; V79 tmp49 [V79,T32] ( 2, 2 ) long -> rcx "argument with side effect" ; V80 tmp50 [V80,T14] ( 3, 3 ) byref -> rcx "BlockOp address local" ; V81 tmp51 [V81,T15] ( 3, 3 ) byref -> rax stack-byref "BlockOp address local" ; V82 tmp52 [V82,T16] ( 3, 3 ) byref -> rax stack-byref "BlockOp address local" ; V83 tmp53 [V83,T17] ( 3, 3 ) byref -> r8 stack-byref "BlockOp address local" ; V84 tmp54 [V84,T28] ( 2, 2 ) byref -> rax "argument with side effect" ; V85 tmp55 [V85,T18] ( 3, 3 ) byref -> rdx stack-byref "BlockOp address local" ; V86 tmp56 [V86 ] ( 2, 2 ) struct (16) [rsp+0x28] do-not-enreg[XSB] must-init addr-exposed "by-value struct argument" ; V87 tmp57 [V87,T19] ( 3, 3 ) byref -> rdx stack-byref "BlockOp address local" ; V88 tmp58 [V88,T33] ( 2, 2 ) long -> rcx "argument with side effect" ; V89 tmp59 [V89,T20] ( 3, 3 ) byref -> rcx stack-byref "BlockOp address local" ; V90 tmp60 [V90,T21] ( 3, 3 ) byref -> rcx stack-byref "BlockOp address local" ; ; Lcl frame size = 232 *************** Before prolog / epilog generation G_M6661_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG G_M6661_IG02: ; offs=000000H, size=0006H, gcrefRegs=00000040 {rsi}, byrefRegs=00000082 {rcx rdi}, byref G_M6661_IG03: ; offs=000006H, size=000AH, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG04: ; offs=000010H, size=0014H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG05: ; epilog placeholder, next placeholder=IG11 , BB03 [0001], epilog, extend <-- First placeholder ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000048 {rbx rsi}, PrevByrefRegs=00000080 {rdi} ; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000040 {rsi}, InitByrefRegs=00000080 {rdi} G_M6661_IG06: ; offs=000124H, size=0028H, gcVars=0000000000000000 {}, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, gcvars, byref G_M6661_IG07: ; offs=00014CH, size=0003H, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG08: ; offs=00014FH, size=0012H, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG09: ; offs=000161H, size=0003H, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG10: ; offs=000164H, size=006CH, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG11: ; epilog placeholder, next placeholder=IG18 , BB12 [0004], epilog, extend ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000048 {rbx rsi}, PrevByrefRegs=00000080 {rdi} ; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000048 {rbx rsi}, InitByrefRegs=00000080 {rdi} G_M6661_IG12: ; offs=0002D0H, size=0010H, gcVars=0000000000000000 {}, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, gcvars, byref G_M6661_IG13: ; offs=0002E0H, size=004EH, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG14: ; offs=00032EH, size=002DH, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG15: ; offs=00035BH, size=0016H, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG16: ; offs=000371H, size=000BH, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG17: ; offs=00037CH, size=004CH, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG18: ; epilog placeholder, next placeholder=IG34 , BB22 [0014], epilog, extend ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000048 {rbx rsi}, PrevByrefRegs=00000080 {rdi} ; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000048 {rbx rsi}, InitByrefRegs=00000080 {rdi} G_M6661_IG19: ; offs=0004C8H, size=000CH, gcVars=0000000000000000 {}, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, gcvars, byref G_M6661_IG20: ; offs=0004D4H, size=00E2H, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG21: ; offs=0005B6H, size=0004H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG22: ; offs=0005BAH, size=0017H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG23: ; offs=0005D1H, size=003BH, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG24: ; offs=00060CH, size=0005H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG25: ; offs=000611H, size=0052H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG26: ; offs=000663H, size=0002H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG27: ; offs=000665H, size=00D5H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG28: ; offs=00073AH, size=0002H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG29: ; offs=00073CH, size=0009H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG30: ; offs=000745H, size=0045H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG31: ; offs=00078AH, size=0004H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG32: ; offs=00078EH, size=0010H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG33: ; offs=00079EH, size=0001H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M6661_IG34: ; epilog placeholder, next placeholder=, BB44 [0054], epilog, extend <-- Last placeholder ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {} ; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {} Recording Var Locations at start of BB01 V01(rsi) V00(rcx) V02(rdi) *************** In genFnProlog() Added IP mapping to front: PROLOG STACK_EMPTY (G_M6661_IG01,ins#0,ofs#0) label __prolog: Found 42 lvMustInit int-sized stack slots, frame offsets -40 through -224 IN010c: push r15 IN010d: push r14 IN010e: push r13 IN010f: push r12 IN0110: push rdi IN0111: push rsi IN0112: push rbp IN0113: push rbx IN0114: sub rsp, 232 Notify VM instruction set (AVX2) must be supported. IN0115: xor rax, rax IN0116: mov qword ptr [rsp+28H], rax IN0117: vxorps xmm4, xmm4 IN0118: vmovdqa xmmword ptr [rsp+30H], xmm4 IN0119: vmovdqa xmmword ptr [rsp+40H], xmm4 IN011a: mov rax, -144 IN011b: vmovdqa xmmword ptr [rsp+rax+E0H], xmm4 IN011c: vmovdqa xmmword ptr [rsp+rax+F0H], xmm4 IN011d: vmovdqa xmmword ptr [rsp+rax+100H], xmm4 IN011e: add rax, 48 IN011f: jne SHORT -5 instr *************** In genFnPrologCalleeRegArgs() for int regs IN0120: mov rsi, rdx IN0121: mov rdi, r8 *************** In genEnregisterIncomingStackArgs() G_M6661_IG01: ; offs=000000H, funclet=00, bbWeight=1 *************** In genFnEpilog() __epilog: gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=00000040 {rsi}, gcRegByrefSetCur=00000080 {rdi} IN0122: add rsp, 232 IN0123: pop rbx IN0124: pop rbp IN0125: pop rsi IN0126: pop rdi IN0127: pop r12 IN0128: pop r13 IN0129: pop r14 IN012a: pop r15 IN012b: ret G_M6661_IG05: ; offs=000024H, funclet=00, bbWeight=0.50 *************** In genFnEpilog() __epilog: gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=00000048 {rbx rsi}, gcRegByrefSetCur=00000080 {rdi} IN012c: add rsp, 232 IN012d: pop rbx IN012e: pop rbp IN012f: pop rsi IN0130: pop rdi IN0131: pop r12 IN0132: pop r13 IN0133: pop r14 IN0134: pop r15 IN0135: ret G_M6661_IG11: ; offs=0001D0H, funclet=00, bbWeight=0.50 *************** In genFnEpilog() __epilog: gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=00000048 {rbx rsi}, gcRegByrefSetCur=00000080 {rdi} IN0136: add rsp, 232 IN0137: pop rbx IN0138: pop rbp IN0139: pop rsi IN013a: pop rdi IN013b: pop r12 IN013c: pop r13 IN013d: pop r14 IN013e: pop r15 IN013f: ret G_M6661_IG18: ; offs=0003C8H, funclet=00, bbWeight=0.50 *************** In genFnEpilog() __epilog: gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=00000000 {}, gcRegByrefSetCur=00000000 {} IN0140: add rsp, 232 IN0141: pop rbx IN0142: pop rbp IN0143: pop rsi IN0144: pop rdi IN0145: pop r12 IN0146: pop r13 IN0147: pop r14 IN0148: pop r15 IN0149: ret G_M6661_IG34: ; offs=00079FH, funclet=00, bbWeight=0.50 0 prologs, 4 epilogs, 0 funclet prologs, 0 funclet epilogs *************** After prolog / epilog generation G_M6661_IG01: ; func=00, offs=000000H, size=0061H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG G_M6661_IG02: ; offs=000061H, size=0006H, gcrefRegs=00000040 {rsi}, byrefRegs=00000082 {rcx rdi}, byref G_M6661_IG03: ; offs=000067H, size=000AH, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG04: ; offs=000071H, size=0014H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG05: ; offs=000085H, size=0014H, epilog, nogc, extend G_M6661_IG06: ; offs=000099H, size=0028H, gcVars=0000000000000000 {}, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, gcvars, byref G_M6661_IG07: ; offs=0000C1H, size=0003H, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG08: ; offs=0000C4H, size=0012H, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG09: ; offs=0000D6H, size=0003H, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG10: ; offs=0000D9H, size=006CH, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG11: ; offs=000145H, size=0014H, epilog, nogc, extend G_M6661_IG12: ; offs=000159H, size=0010H, gcVars=0000000000000000 {}, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, gcvars, byref G_M6661_IG13: ; offs=000169H, size=004EH, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG14: ; offs=0001B7H, size=002DH, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG15: ; offs=0001E4H, size=0016H, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG16: ; offs=0001FAH, size=000BH, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG17: ; offs=000205H, size=004CH, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG18: ; offs=000251H, size=0014H, epilog, nogc, extend G_M6661_IG19: ; offs=000265H, size=000CH, gcVars=0000000000000000 {}, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, gcvars, byref G_M6661_IG20: ; offs=000271H, size=00E2H, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG21: ; offs=000353H, size=0004H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG22: ; offs=000357H, size=0017H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG23: ; offs=00036EH, size=003BH, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG24: ; offs=0003A9H, size=0005H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG25: ; offs=0003AEH, size=0052H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG26: ; offs=000400H, size=0002H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG27: ; offs=000402H, size=00D5H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG28: ; offs=0004D7H, size=0002H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG29: ; offs=0004D9H, size=0009H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG30: ; offs=0004E2H, size=0045H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG31: ; offs=000527H, size=0004H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG32: ; offs=00052BH, size=0010H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref G_M6661_IG33: ; offs=00053BH, size=0001H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M6661_IG34: ; offs=00053CH, size=0014H, epilog, nogc, extend *************** In emitJumpDistBind() Adjusted offset of BB02 from 0061 to 0061 Adjusted offset of BB03 from 0067 to 0067 Binding: IN0004: 000000 jne L_M6661_BB04 Binding L_M6661_BB04 to G_M6661_IG06 Estimate of fwd jump [D1FFAB1E/004]: 006B -> 0099 = 002C Shrinking jump [D1FFAB1E/004] Adjusted offset of BB04 from 0071 to 006D Adjusted offset of BB05 from 0085 to 0081 Adjusted offset of BB06 from 0099 to 0095 Binding: IN0014: 000000 jle L_M6661_BB06 Binding L_M6661_BB06 to G_M6661_IG07 Estimate of fwd jump [D1FFAB1E/020]: 00AF -> 00BD = 000C Shrinking jump [D1FFAB1E/020] Binding: IN0016: 000000 jmp L_M6661_BB07 Binding L_M6661_BB07 to G_M6661_IG08 Estimate of fwd jump [D1FFAB1E/022]: 00B4 -> 00BC = 0006 Shrinking jump [D1FFAB1E/022] Adjusted offset of BB07 from 00C1 to 00B6 Adjusted offset of BB08 from 00C4 to 00B9 Binding: IN001a: 000000 jbe L_M6661_BB09 Binding L_M6661_BB09 to G_M6661_IG09 Estimate of fwd jump [D1FFAB1E/026]: 00C0 -> 00CB = 0009 Shrinking jump [D1FFAB1E/026] Binding: IN001b: 000000 jmp L_M6661_BB10 Binding L_M6661_BB10 to G_M6661_IG10 Estimate of fwd jump [D1FFAB1E/027]: 00C2 -> 00CA = 0006 Shrinking jump [D1FFAB1E/027] Adjusted offset of BB09 from 00D6 to 00C4 Adjusted offset of BB10 from 00D9 to 00C7 Binding: IN002b: 000000 je L_M6661_BB14 Binding L_M6661_BB14 to G_M6661_IG13 Estimate of fwd jump [D1FFAB1E/043]: 0101 -> 0157 = 0054 Shrinking jump [D1FFAB1E/043] Binding: IN0031: 000000 jge L_M6661_BB13 Binding L_M6661_BB13 to G_M6661_IG12 Estimate of fwd jump [D1FFAB1E/049]: 0114 -> 0143 = 002D Shrinking jump [D1FFAB1E/049] Adjusted offset of BB11 from 0145 to 012B Adjusted offset of BB12 from 0159 to 013F Adjusted offset of BB13 from 0169 to 014F Binding: IN0045: 000000 jae L_M6661_BB16 Binding L_M6661_BB16 to G_M6661_IG14 Estimate of fwd jump [D1FFAB1E/069]: 0181 -> 019D = 001A Shrinking jump [D1FFAB1E/069] Binding: IN0049: 000000 jne L_M6661_BB17 Binding L_M6661_BB17 to G_M6661_IG15 Estimate of fwd jump [D1FFAB1E/073]: 0193 -> 01C6 = 0031 Shrinking jump [D1FFAB1E/073] Adjusted offset of BB14 from 01B7 to 0195 Binding: IN0052: 000000 jmp L_M6661_BB44 Binding L_M6661_BB44 to G_M6661_IG33 Estimate of fwd jump [D1FFAB1E/082]: 01BD -> 0519 = 035A Adjusted offset of BB15 from 01E4 to 01C2 Binding: IN0054: 000000 jl L_M6661_BB19 Binding L_M6661_BB19 to G_M6661_IG16 Estimate of fwd jump [D1FFAB1E/084]: 01C4 -> 01D8 = 0012 Shrinking jump [D1FFAB1E/084] Binding: IN0057: 000000 jmp L_M6661_BB20 Binding L_M6661_BB20 to G_M6661_IG17 Estimate of fwd jump [D1FFAB1E/087]: 01CF -> 01DF = 000E Shrinking jump [D1FFAB1E/087] Adjusted offset of BB16 from 01FA to 01D1 Adjusted offset of BB17 from 0205 to 01DC Binding: IN005d: 000000 jne L_M6661_BB45 Binding L_M6661_BB45 to G_M6661_IG19 Estimate of fwd jump [D1FFAB1E/093]: 01E1 -> 023C = 0059 Shrinking jump [D1FFAB1E/093] Binding: IN0068: 000000 jge L_M6661_BB23 Binding L_M6661_BB23 to G_M6661_IG20 Estimate of fwd jump [D1FFAB1E/104]: 020A -> 0244 = 0038 Shrinking jump [D1FFAB1E/104] Adjusted offset of BB18 from 0251 to 0220 Adjusted offset of BB19 from 0265 to 0234 Binding: IN0070: 000000 jmp L_M6661_BB23 Binding L_M6661_BB23 to G_M6661_IG20 Estimate of fwd jump [D1FFAB1E/112]: 023B -> 0240 = 0003 Shrinking jump [D1FFAB1E/112] Adjusted offset of BB20 from 0271 to 023D Binding: IN009c: 000000 ja L_M6661_BB25 Binding L_M6661_BB25 to G_M6661_IG21 Estimate of fwd jump [D1FFAB1E/156]: 0312 -> 031F = 000B Shrinking jump [D1FFAB1E/156] Binding: IN009e: 000000 jmp L_M6661_BB26 Binding L_M6661_BB26 to G_M6661_IG22 Estimate of fwd jump [D1FFAB1E/158]: 0316 -> 031F = 0007 Shrinking jump [D1FFAB1E/158] Adjusted offset of BB21 from 0353 to 0318 Adjusted offset of BB22 from 0357 to 031C Binding: IN00a2: 000000 je L_M6661_BB28 Binding L_M6661_BB28 to G_M6661_IG23 Estimate of fwd jump [D1FFAB1E/162]: 031E -> 0333 = 0013 Shrinking jump [D1FFAB1E/162] Adjusted offset of BB23 from 036E to 032F Binding: IN00a9: 000000 je L_M6661_BB32 Binding L_M6661_BB32 to G_M6661_IG25 Estimate of fwd jump [D1FFAB1E/169]: 0338 -> 036F = 0035 Shrinking jump [D1FFAB1E/169] Binding: IN00ab: 000000 jbe L_M6661_BB31 Binding L_M6661_BB31 to G_M6661_IG24 Estimate of fwd jump [D1FFAB1E/171]: 033D -> 0366 = 0027 Shrinking jump [D1FFAB1E/171] Binding: IN00b2: 000000 jmp L_M6661_BB44 Binding L_M6661_BB44 to G_M6661_IG33 Estimate of fwd jump [D1FFAB1E/178]: 035D -> 04F4 = 0195 Adjusted offset of BB24 from 03A9 to 0362 Adjusted offset of BB25 from 03AE to 0367 Binding: IN00c3: 000000 jl L_M6661_BB34 Binding L_M6661_BB34 to G_M6661_IG26 Estimate of fwd jump [D1FFAB1E/195]: 03AE -> 03B9 = 0009 Shrinking jump [D1FFAB1E/195] Binding: IN00c4: 000000 jmp L_M6661_BB35 Binding L_M6661_BB35 to G_M6661_IG27 Estimate of fwd jump [D1FFAB1E/196]: 03B0 -> 03B7 = 0005 Shrinking jump [D1FFAB1E/196] Adjusted offset of BB26 from 0400 to 03B2 Adjusted offset of BB27 from 0402 to 03B4 Binding: IN00e6: 000000 jbe L_M6661_BB40 Binding L_M6661_BB40 to G_M6661_IG30 Estimate of fwd jump [D1FFAB1E/230]: 045C -> 0494 = 0036 Shrinking jump [D1FFAB1E/230] Binding: IN00e9: 000000 je L_M6661_BB38 Binding L_M6661_BB38 to G_M6661_IG28 Estimate of fwd jump [D1FFAB1E/233]: 0464 -> 0485 = 001F Shrinking jump [D1FFAB1E/233] Binding: IN00f1: 000000 jmp L_M6661_BB39 Binding L_M6661_BB39 to G_M6661_IG29 Estimate of fwd jump [D1FFAB1E/241]: 047C -> 0483 = 0005 Shrinking jump [D1FFAB1E/241] Adjusted offset of BB28 from 04D7 to 047E Adjusted offset of BB29 from 04D9 to 0480 Adjusted offset of BB30 from 04E2 to 0489 Binding: IN0101: 000000 jne L_M6661_BB42 Binding L_M6661_BB42 to G_M6661_IG31 Estimate of fwd jump [D1FFAB1E/257]: 04BA -> 04CE = 0012 Shrinking jump [D1FFAB1E/257] Binding: IN0105: 000000 jmp L_M6661_BB43 Binding L_M6661_BB43 to G_M6661_IG32 Estimate of fwd jump [D1FFAB1E/261]: 04C5 -> 04CE = 0007 Shrinking jump [D1FFAB1E/261] Adjusted offset of BB31 from 0527 to 04C7 Adjusted offset of BB32 from 052B to 04CB Adjusted offset of BB33 from 053B to 04DB Adjusted offset of BB34 from 053C to 04DC Total shrinkage = 96, min extra jump size = 278 *************** Finishing PHASE Generate code *************** Starting PHASE Emit code Hot code size = 0x4F0 bytes Cold code size = 0x0 bytes reserveUnwindInfo(isFunclet=FALSE, isColdCode=FALSE, unwindSize=0x18) *************** In emitEndCodeGen() Converting emitMaxStackDepth from bytes (0) to elements (0) *************************************************************************** Instructions as they come out of the scheduler G_M6661_IG01: ; func=00, offs=000000H, size=0061H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG IN010c: 000000 push r15 IN010d: 000002 push r14 IN010e: 000004 push r13 IN010f: 000006 push r12 IN0110: 000008 push rdi IN0111: 000009 push rsi IN0112: 00000A push rbp IN0113: 00000B push rbx IN0114: 00000C sub rsp, 232 IN0115: 000013 xor rax, rax IN0116: 000015 mov qword ptr [rsp+28H], rax IN0117: 00001A vxorps xmm4, xmm4 (ECS:5, ACS:4) Instruction predicted size = 5, actual = 4 IN0118: 00001E vmovdqa xmmword ptr [rsp+30H], xmm4 (ECS:7, ACS:6) Instruction predicted size = 7, actual = 6 IN0119: 000024 vmovdqa xmmword ptr [rsp+40H], xmm4 (ECS:7, ACS:6) Instruction predicted size = 7, actual = 6 IN011a: 00002A mov rax, -144 IN011b: 000034 vmovdqa xmmword ptr [rsp+rax+E0H], xmm4 (ECS:10, ACS:9) Instruction predicted size = 10, actual = 9 IN011c: 00003D vmovdqa xmmword ptr [rsp+rax+F0H], xmm4 (ECS:10, ACS:9) Instruction predicted size = 10, actual = 9 IN011d: 000046 vmovdqa xmmword ptr [rsp+rax+100H], xmm4 (ECS:10, ACS:9) Instruction predicted size = 10, actual = 9 IN011e: 00004F add rax, 48 IN011f: 000053 jne SHORT -5 instr IN0120: 000055 mov rsi, rdx ; gcrRegs +[rsi] IN0121: 000058 mov rdi, r8 ; byrRegs +[rdi] ;; bbWeight=1 PerfScore 16.83 G_M6661_IG02: ; func=00, offs=000061H, size=0006H, gcrefRegs=00000040 {rsi}, byrefRegs=00000082 {rcx rdi}, byref Block predicted offs = 00000061, actual = 0000005B -> size adj = 6 ; byrRegs +[rcx] IN0001: 00005B mov rbx, gword ptr [rcx] ; gcrRegs +[rbx] IN0002: 00005E mov ebp, dword ptr [rcx+8] ;; bbWeight=1 PerfScore 4.00 G_M6661_IG03: ; func=00, offs=000067H, size=0006H, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref, isz Block predicted offs = 00000067, actual = 00000061 -> size adj = 6 ; byrRegs -[rcx] IN0003: 000061 cmp dword ptr [rbx+8], 0 IN0004: 000065 jne SHORT G_M6661_IG06 ;; bbWeight=1 PerfScore 3.00 G_M6661_IG04: ; func=00, offs=00006DH, size=0014H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref Block predicted offs = 0000006D, actual = 00000067 -> size adj = 6 ; gcrRegs -[rbx] IN0005: 000067 mov rcx, rsi ; gcrRegs +[rcx] IN0006: 00006A mov rax, qword ptr [rsi] IN0007: 00006D mov rax, qword ptr [rax+80] IN0008: 000071 call qword ptr [rax]FloatingPointType:get_Zero():long:this ; gcrRegs -[rcx rsi] ; gcr arg pop 0 IN0009: 000073 mov qword ptr [rdi], rax IN000a: 000076 mov eax, 1 ;; bbWeight=0.50 PerfScore 4.25 G_M6661_IG05: ; func=00, offs=000081H, size=0014H, epilog, nogc, extend Block predicted offs = 00000081, actual = 0000007B -> size adj = 6 IN0122: 00007B add rsp, 232 IN0123: 000082 pop rbx IN0124: 000083 pop rbp IN0125: 000084 pop rsi IN0126: 000085 pop rdi IN0127: 000086 pop r12 IN0128: 000088 pop r13 IN0129: 00008A pop r14 IN012a: 00008C pop r15 IN012b: 00008E ret ;; bbWeight=0.50 PerfScore 2.63 G_M6661_IG06: ; func=00, offs=000095H, size=0021H, gcVars=0000000000000000 {}, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, gcvars, byref, isz Block predicted offs = 00000095, actual = 0000008F -> size adj = 6 ; gcrRegs +[rbx rsi] IN000b: 00008F mov rcx, rsi ; gcrRegs +[rcx] IN000c: 000092 mov rax, qword ptr [rsi] IN000d: 000095 mov rax, qword ptr [rax+72] IN000e: 000099 call qword ptr [rax+32]FloatingPointType:get_DenormalMantissaBits():ushort:this ; gcrRegs -[rcx] ; gcr arg pop 0 IN000f: 00009C inc eax IN0010: 00009E movzx r14, ax IN0011: 0000A2 inc r14d IN0012: 0000A5 mov ecx, ebp IN0013: 0000A7 test ecx, ecx IN0014: 0000A9 jle SHORT G_M6661_IG07 IN0015: 0000AB mov r15d, ebp IN0016: 0000AE jmp SHORT G_M6661_IG08 ;; bbWeight=0.50 PerfScore 5.88 G_M6661_IG07: ; func=00, offs=0000B6H, size=0003H, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref Block predicted offs = 000000B6, actual = 000000B0 -> size adj = 6 IN0017: 0000B0 xor r15d, r15d ;; bbWeight=0.50 PerfScore 0.13 G_M6661_IG08: ; func=00, offs=0000B9H, size=000BH, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref, isz Block predicted offs = 000000B9, actual = 000000B3 -> size adj = 6 IN0018: 0000B3 mov r12d, dword ptr [rbx+8] IN0019: 0000B7 cmp r15d, r12d IN001a: 0000BA jbe SHORT G_M6661_IG09 IN001b: 0000BC jmp SHORT G_M6661_IG10 ;; bbWeight=0.50 PerfScore 2.63 G_M6661_IG09: ; func=00, offs=0000C4H, size=0003H, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref Block predicted offs = 000000C4, actual = 000000BE -> size adj = 6 IN001c: 0000BE mov r12d, r15d ;; bbWeight=0.50 PerfScore 0.13 G_M6661_IG10: ; func=00, offs=0000C7H, size=0064H, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref, isz Block predicted offs = 000000C7, actual = 000000C1 -> size adj = 6 IN001d: 0000C1 sub r15d, r12d IN001e: 0000C4 mov r13d, dword ptr [rbx+8] IN001f: 0000C8 mov eax, r13d IN0020: 0000CB sub eax, r12d IN0021: 0000CE mov dword ptr [rsp+E4H], eax IN0022: 0000D5 lea rcx, bword ptr [rsp+D0H] ; byrRegs +[rcx] IN0023: 0000DD lea rdx, bword ptr [rsp+48H] ; byrRegs +[rdx] IN0024: 0000E2 mov gword ptr [rdx], rbx IN0025: 0000E5 mov dword ptr [rdx+8], ebp IN0026: 0000E8 lea rdx, bword ptr [rsp+48H] IN0027: 0000ED mov r9d, r12d IN0028: 0000F0 xor r8d, r8d IN0029: 0000F3 call Microsoft.CodeAnalysis.RealParser:AccumulateDecimalDigitsIntoBigInteger(DecimalFloatingPointString,int,int):System.Numerics.BigInteger ; byrRegs -[rcx rdx] ; gcr arg pop 0 IN002a: 0000F8 test r15d, r15d IN002b: 0000FB je SHORT G_M6661_IG13 IN002c: 0000FD mov rcx, rsi ; gcrRegs +[rcx] IN002d: 000100 call FloatingPointType:get_OverflowDecimalExponent():int:this ; gcrRegs -[rcx] ; gcr arg pop 0 IN002e: 000105 movsxd rcx, eax IN002f: 000108 mov eax, r15d IN0030: 00010B cmp rcx, rax IN0031: 00010E jge SHORT G_M6661_IG12 IN0032: 000110 mov rcx, rsi ; gcrRegs +[rcx] IN0033: 000113 mov rax, qword ptr [rsi] IN0034: 000116 mov rax, qword ptr [rax+80] IN0035: 00011A call qword ptr [rax+8]FloatingPointType:get_Infinity():long:this ; gcrRegs -[rcx rbx rsi] ; gcr arg pop 0 IN0036: 00011D mov qword ptr [rdi], rax IN0037: 000120 mov eax, 3 ;; bbWeight=0.50 PerfScore 10.75 G_M6661_IG11: ; func=00, offs=00012BH, size=0014H, epilog, nogc, extend Block predicted offs = 0000012B, actual = 00000125 -> size adj = 6 IN012c: 000125 add rsp, 232 IN012d: 00012C pop rbx IN012e: 00012D pop rbp IN012f: 00012E pop rsi IN0130: 00012F pop rdi IN0131: 000130 pop r12 IN0132: 000132 pop r13 IN0133: 000134 pop r14 IN0134: 000136 pop r15 IN0135: 000138 ret ;; bbWeight=0.50 PerfScore 2.63 G_M6661_IG12: ; func=00, offs=00013FH, size=0010H, gcVars=0000000000000000 {}, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, gcvars, byref Block predicted offs = 0000013F, actual = 00000139 -> size adj = 6 ; gcrRegs +[rbx rsi] IN0038: 000139 lea rcx, bword ptr [rsp+D0H] ; byrRegs +[rcx] IN0039: 000141 mov edx, r15d IN003a: 000144 call Microsoft.CodeAnalysis.RealParser:MultiplyByPowerOfTen(byref,int) ; byrRegs -[rcx] ; gcr arg pop 0 ;; bbWeight=0.50 PerfScore 0.88 G_M6661_IG13: ; func=00, offs=00014FH, size=0046H, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref, isz Block predicted offs = 0000014F, actual = 00000149 -> size adj = 6 IN003b: 000149 lea rcx, bword ptr [rsp+38H] ; byrRegs +[rcx] IN003c: 00014E mov rdx, gword ptr [rsp+D0H] ; gcrRegs +[rdx] IN003d: 000156 mov gword ptr [rcx], rdx IN003e: 000159 mov edx, dword ptr [rsp+D8H] ; gcrRegs -[rdx] IN003f: 000160 mov dword ptr [rcx+8], edx IN0040: 000163 lea rcx, bword ptr [rsp+38H] IN0041: 000168 lea rdx, [rsp+C8H] IN0042: 000170 call Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger,byref):int ; byrRegs -[rcx] ; gcr arg pop 0 IN0043: 000175 mov r15d, eax IN0044: 000178 cmp r15d, r14d IN0045: 00017B jae SHORT G_M6661_IG14 IN0046: 00017D mov eax, dword ptr [rsp+E4H] IN0047: 000184 test eax, eax IN0048: 000186 mov dword ptr [rsp+E4H], eax IN0049: 00018D jne SHORT G_M6661_IG15 ;; bbWeight=0.50 PerfScore 5.63 G_M6661_IG14: ; func=00, offs=000195H, size=002DH, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref Block predicted offs = 00000195, actual = 0000018F -> size adj = 6 ; gcrRegs -[rbx] IN004a: 00018F mov bword ptr [rsp+20H], rdi ; byr arg write IN004b: 000194 cmp dword ptr [rsp+E4H], 0 IN004c: 00019C setne r8b IN004d: 0001A0 movzx r8, r8b IN004e: 0001A4 mov rcx, gword ptr [rsp+C8H] ; gcrRegs +[rcx] IN004f: 0001AC mov edx, r15d IN0050: 0001AF mov r9, rsi ; gcrRegs +[r9] IN0051: 0001B2 call Microsoft.CodeAnalysis.RealParser:ConvertBigIntegerToFloatingPointBits(System.Byte[],int,bool,FloatingPointType,byref):int ; gcrRegs -[rcx rsi r9] ; byrRegs -[rdi] ; gcr arg pop 0 IN0052: 0001B7 jmp G_M6661_IG33 ;; bbWeight=0.50 PerfScore 3.88 G_M6661_IG15: ; func=00, offs=0001C2H, size=000FH, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref, isz Block predicted offs = 000001C2, actual = 000001BC -> size adj = 6 ; gcrRegs +[rbx rsi] ; byrRegs +[rdi] IN0053: 0001BC test ebp, ebp IN0054: 0001BE jl SHORT G_M6661_IG16 IN0055: 0001C0 mov eax, dword ptr [rsp+E4H] IN0056: 0001C7 mov edx, eax IN0057: 0001C9 jmp SHORT G_M6661_IG17 ;; bbWeight=0.50 PerfScore 2.25 G_M6661_IG16: ; func=00, offs=0001D1H, size=000BH, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref Block predicted offs = 000001D1, actual = 000001CB -> size adj = 6 IN0058: 0001CB mov eax, dword ptr [rsp+E4H] IN0059: 0001D2 mov edx, eax IN005a: 0001D4 sub edx, ebp ;; bbWeight=0.50 PerfScore 0.75 G_M6661_IG17: ; func=00, offs=0001DCH, size=0044H, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref, isz Block predicted offs = 000001DC, actual = 000001D6 -> size adj = 6 IN005b: 0001D6 mov eax, edx IN005c: 0001D8 test r15d, r15d IN005d: 0001DB jne SHORT G_M6661_IG19 IN005e: 0001DD mov ecx, dword ptr [rbx+8] IN005f: 0001E0 movsxd rcx, ecx IN0060: 0001E3 mov dword ptr [rsp+C4H], eax IN0061: 0001EA mov edx, eax IN0062: 0001EC sub rdx, rcx IN0063: 0001EF mov qword ptr [rsp+78H], rdx IN0064: 0001F4 mov rcx, rsi ; gcrRegs +[rcx] IN0065: 0001F7 call FloatingPointType:get_OverflowDecimalExponent():int:this ; gcrRegs -[rcx] ; gcr arg pop 0 IN0066: 0001FC movsxd rcx, eax IN0067: 0001FF cmp rcx, qword ptr [rsp+78H] IN0068: 000204 jge SHORT G_M6661_IG20 IN0069: 000206 mov rcx, rsi ; gcrRegs +[rcx] IN006a: 000209 mov rax, qword ptr [rsi] IN006b: 00020C mov rax, qword ptr [rax+80] IN006c: 000210 call qword ptr [rax]FloatingPointType:get_Zero():long:this ; gcrRegs -[rcx rbx rsi] ; gcr arg pop 0 IN006d: 000212 mov qword ptr [rdi], rax IN006e: 000215 mov eax, 2 ;; bbWeight=0.50 PerfScore 9.13 G_M6661_IG18: ; func=00, offs=000220H, size=0014H, epilog, nogc, extend Block predicted offs = 00000220, actual = 0000021A -> size adj = 6 IN0136: 00021A add rsp, 232 IN0137: 000221 pop rbx IN0138: 000222 pop rbp IN0139: 000223 pop rsi IN013a: 000224 pop rdi IN013b: 000225 pop r12 IN013c: 000227 pop r13 IN013d: 000229 pop r14 IN013e: 00022B pop r15 IN013f: 00022D ret ;; bbWeight=0.50 PerfScore 2.63 G_M6661_IG19: ; func=00, offs=000234H, size=0009H, gcVars=0000000000000000 {}, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, gcvars, byref, isz Block predicted offs = 00000234, actual = 0000022E -> size adj = 6 ; gcrRegs +[rbx rsi] IN006f: 00022E mov dword ptr [rsp+C4H], eax IN0070: 000235 jmp SHORT G_M6661_IG20 ;; bbWeight=0.25 PerfScore 0.75 G_M6661_IG20: ; func=00, offs=00023DH, size=00DBH, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref, isz Block predicted offs = 0000023D, actual = 00000237 -> size adj = 6 IN0071: 000237 lea rcx, bword ptr [rsp+B0H] ; byrRegs +[rcx] IN0072: 00023F lea rdx, bword ptr [rsp+48H] ; byrRegs +[rdx] IN0073: 000244 mov gword ptr [rdx], rbx IN0074: 000247 mov dword ptr [rdx+8], ebp IN0075: 00024A lea rdx, bword ptr [rsp+48H] IN0076: 00024F mov r8d, r12d IN0077: 000252 mov r9d, r13d IN0078: 000255 call Microsoft.CodeAnalysis.RealParser:AccumulateDecimalDigitsIntoBigInteger(DecimalFloatingPointString,int,int):System.Numerics.BigInteger ; gcrRegs -[rbx] ; byrRegs -[rcx rdx] ; gcr arg pop 0 IN0079: 00025A mov rcx, 0xD1FFAB1E IN007a: 000264 mov edx, 173 IN007b: 000269 call CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE ; gcr arg pop 0 IN007c: 00026E mov rcx, 0xD1FFAB1E IN007d: 000278 mov rcx, gword ptr [rcx] ; gcrRegs +[rcx] IN007e: 00027B add rcx, 8 ; gcrRegs -[rcx] ; byrRegs +[rcx] IN007f: 00027F mov rdx, gword ptr [rcx] ; gcrRegs +[rdx] IN0080: 000282 mov gword ptr [rsp+A0H], rdx IN0081: 00028A mov ecx, dword ptr [rcx+8] ; byrRegs -[rcx] IN0082: 00028D mov dword ptr [rsp+A8H], ecx IN0083: 000294 lea rcx, bword ptr [rsp+A0H] ; byrRegs +[rcx] IN0084: 00029C mov edx, dword ptr [rsp+C4H] ; gcrRegs -[rdx] IN0085: 0002A3 call Microsoft.CodeAnalysis.RealParser:MultiplyByPowerOfTen(byref,int) ; byrRegs -[rcx] ; gcr arg pop 0 IN0086: 0002A8 mov rcx, gword ptr [rsp+B0H] ; gcrRegs +[rcx] IN0087: 0002B0 mov edx, dword ptr [rsp+B8H] IN0088: 0002B7 lea rax, bword ptr [rsp+38H] ; byrRegs +[rax] IN0089: 0002BC mov gword ptr [rax], rcx IN008a: 0002BF mov dword ptr [rax+8], edx IN008b: 0002C2 lea rcx, bword ptr [rsp+38H] ; gcrRegs -[rcx] ; byrRegs +[rcx] IN008c: 0002C7 lea rdx, [rsp+70H] IN008d: 0002CC call Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger,byref):int ; byrRegs -[rax rcx] ; gcr arg pop 0 IN008e: 0002D1 mov ebx, eax IN008f: 0002D3 xor rcx, rcx ; gcrRegs +[rcx] IN0090: 0002D5 mov gword ptr [rsp+70H], rcx IN0091: 0002DA mov rcx, gword ptr [rsp+A0H] IN0092: 0002E2 mov edx, dword ptr [rsp+A8H] IN0093: 0002E9 lea rax, bword ptr [rsp+38H] ; byrRegs +[rax] IN0094: 0002EE mov gword ptr [rax], rcx IN0095: 0002F1 mov dword ptr [rax+8], edx IN0096: 0002F4 lea rcx, bword ptr [rsp+38H] ; gcrRegs -[rcx] ; byrRegs +[rcx] IN0097: 0002F9 lea rdx, [rsp+68H] IN0098: 0002FE call Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger,byref):int ; byrRegs -[rax rcx] ; gcr arg pop 0 IN0099: 000303 xor rcx, rcx ; gcrRegs +[rcx] IN009a: 000305 mov gword ptr [rsp+68H], rcx IN009b: 00030A cmp eax, ebx IN009c: 00030C ja SHORT G_M6661_IG21 IN009d: 00030E xor ebp, ebp IN009e: 000310 jmp SHORT G_M6661_IG22 ;; bbWeight=0.50 PerfScore 18.38 G_M6661_IG21: ; func=00, offs=000318H, size=0004H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref Block predicted offs = 00000318, actual = 00000312 -> size adj = 6 ; gcrRegs -[rcx] IN009f: 000312 mov ebp, eax IN00a0: 000314 sub ebp, ebx ;; bbWeight=0.50 PerfScore 0.25 G_M6661_IG22: ; func=00, offs=00031CH, size=0013H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref, isz Block predicted offs = 0000031C, actual = 00000316 -> size adj = 6 IN00a1: 000316 test ebp, ebp IN00a2: 000318 je SHORT G_M6661_IG23 IN00a3: 00031A lea rcx, bword ptr [rsp+B0H] ; byrRegs +[rcx] IN00a4: 000322 mov edx, ebp IN00a5: 000324 call Microsoft.CodeAnalysis.RealParser:ShiftLeft(byref,int) ; byrRegs -[rcx] ; gcr arg pop 0 ;; bbWeight=0.50 PerfScore 1.50 G_M6661_IG23: ; func=00, offs=00032FH, size=0033H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref, isz Block predicted offs = 0000032F, actual = 00000329 -> size adj = 6 IN00a6: 000329 sub r14d, r15d IN00a7: 00032C mov ebx, r14d IN00a8: 00032F test r15d, r15d IN00a9: 000332 je SHORT G_M6661_IG25 IN00aa: 000334 cmp ebp, r14d IN00ab: 000337 jbe SHORT G_M6661_IG24 IN00ac: 000339 mov bword ptr [rsp+20H], rdi ; byr arg write IN00ad: 00033E mov r8d, 1 IN00ae: 000344 mov rcx, gword ptr [rsp+C8H] ; gcrRegs +[rcx] IN00af: 00034C mov edx, r15d IN00b0: 00034F mov r9, rsi ; gcrRegs +[r9] IN00b1: 000352 call Microsoft.CodeAnalysis.RealParser:ConvertBigIntegerToFloatingPointBits(System.Byte[],int,bool,FloatingPointType,byref):int ; gcrRegs -[rcx rsi r9] ; byrRegs -[rdi] ; gcr arg pop 0 IN00b2: 000357 jmp G_M6661_IG33 ;; bbWeight=0.50 PerfScore 4.38 G_M6661_IG24: ; func=00, offs=000362H, size=0005H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref Block predicted offs = 00000362, actual = 0000035C -> size adj = 6 ; gcrRegs +[rsi] ; byrRegs +[rdi] IN00b3: 00035C mov ebx, r14d IN00b4: 00035F sub ebx, ebp ;; bbWeight=0.50 PerfScore 0.25 G_M6661_IG25: ; func=00, offs=000367H, size=004BH, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref, isz Block predicted offs = 00000367, actual = 00000361 -> size adj = 6 IN00b5: 000361 mov rcx, gword ptr [rsp+B0H] ; gcrRegs +[rcx] IN00b6: 000369 mov gword ptr [rsp+58H], rcx IN00b7: 00036E mov ecx, dword ptr [rsp+B8H] ; gcrRegs -[rcx] IN00b8: 000375 mov dword ptr [rsp+60H], ecx IN00b9: 000379 mov rcx, gword ptr [rsp+A0H] ; gcrRegs +[rcx] IN00ba: 000381 mov edx, dword ptr [rsp+A8H] IN00bb: 000388 lea rax, bword ptr [rsp+58H] ; byrRegs +[rax] IN00bc: 00038D lea r8, bword ptr [rsp+38H] ; byrRegs +[r8] IN00bd: 000392 mov gword ptr [r8], rcx IN00be: 000395 mov dword ptr [r8+8], edx IN00bf: 000399 mov rcx, rax ; gcrRegs -[rcx] ; byrRegs +[rcx] IN00c0: 00039C lea rdx, bword ptr [rsp+38H] ; byrRegs +[rdx] IN00c1: 0003A1 call System.Numerics.BigInteger:CompareTo(System.Numerics.BigInteger):int:this ; byrRegs -[rax rcx rdx r8] ; gcr arg pop 0 IN00c2: 0003A6 test eax, eax IN00c3: 0003A8 jl SHORT G_M6661_IG26 IN00c4: 0003AA jmp SHORT G_M6661_IG27 ;; bbWeight=0.50 PerfScore 7.00 G_M6661_IG26: ; func=00, offs=0003B2H, size=0002H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref Block predicted offs = 000003B2, actual = 000003AC -> size adj = 6 IN00c5: 0003AC inc ebp ;; bbWeight=0.50 PerfScore 0.13 G_M6661_IG27: ; func=00, offs=0003B4H, size=00CAH, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref, isz Block predicted offs = 000003B4, actual = 000003AE -> size adj = 6 IN00c6: 0003AE lea rcx, bword ptr [rsp+B0H] ; byrRegs +[rcx] IN00c7: 0003B6 mov edx, ebx IN00c8: 0003B8 call Microsoft.CodeAnalysis.RealParser:ShiftLeft(byref,int) ; byrRegs -[rcx] ; gcr arg pop 0 IN00c9: 0003BD lea rcx, bword ptr [rsp+80H] ; byrRegs +[rcx] IN00ca: 0003C5 lea rdx, bword ptr [rsp+38H] ; byrRegs +[rdx] IN00cb: 0003CA mov r8, gword ptr [rsp+B0H] ; gcrRegs +[r8] IN00cc: 0003D2 mov gword ptr [rdx], r8 IN00cd: 0003D5 mov r8d, dword ptr [rsp+B8H] ; gcrRegs -[r8] IN00ce: 0003DD mov dword ptr [rdx+8], r8d IN00cf: 0003E1 lea rdx, bword ptr [rsp+28H] IN00d0: 0003E6 mov r8, gword ptr [rsp+A0H] ; gcrRegs +[r8] IN00d1: 0003EE mov gword ptr [rdx], r8 IN00d2: 0003F1 mov r8d, dword ptr [rsp+A8H] ; gcrRegs -[r8] IN00d3: 0003F9 mov dword ptr [rdx+8], r8d IN00d4: 0003FD lea rdx, bword ptr [rsp+38H] IN00d5: 000402 lea r8, bword ptr [rsp+28H] ; byrRegs +[r8] IN00d6: 000407 lea r9, bword ptr [rsp+90H] ; byrRegs +[r9] IN00d7: 00040F call System.Numerics.BigInteger:DivRem(System.Numerics.BigInteger,System.Numerics.BigInteger,byref):System.Numerics.BigInteger ; byrRegs -[rcx rdx r8-r9] ; gcr arg pop 0 IN00d8: 000414 lea rcx, bword ptr [rsp+38H] ; byrRegs +[rcx] IN00d9: 000419 mov rax, gword ptr [rsp+80H] ; gcrRegs +[rax] IN00da: 000421 mov gword ptr [rcx], rax IN00db: 000424 mov eax, dword ptr [rsp+88H] ; gcrRegs -[rax] IN00dc: 00042B mov dword ptr [rcx+8], eax IN00dd: 00042E lea rcx, bword ptr [rsp+38H] IN00de: 000433 call System.Numerics.BigInteger:op_Explicit(System.Numerics.BigInteger):long ; byrRegs -[rcx] ; gcr arg pop 0 IN00df: 000438 mov rbx, rax IN00e0: 00043B cmp dword ptr [rsp+98H], 0 IN00e1: 000443 sete r12b IN00e2: 000447 movzx r12, r12b IN00e3: 00044B mov rcx, rbx IN00e4: 00044E call Microsoft.CodeAnalysis.RealParser:CountSignificantBits(long):int ; gcr arg pop 0 IN00e5: 000453 cmp eax, r14d IN00e6: 000456 jbe SHORT G_M6661_IG30 IN00e7: 000458 sub eax, r14d IN00e8: 00045B test r12d, r12d IN00e9: 00045E je SHORT G_M6661_IG28 IN00ea: 000460 mov edx, 1 IN00eb: 000465 mov ecx, eax IN00ec: 000467 shl rdx, cl IN00ed: 00046A dec rdx IN00ee: 00046D test rbx, rdx IN00ef: 000470 sete cl IN00f0: 000473 movzx rcx, cl IN00f1: 000476 jmp SHORT G_M6661_IG29 ;; bbWeight=0.50 PerfScore 16.25 G_M6661_IG28: ; func=00, offs=00047EH, size=0002H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref Block predicted offs = 0000047E, actual = 00000478 -> size adj = 6 IN00f2: 000478 xor ecx, ecx ;; bbWeight=0.50 PerfScore 0.13 G_M6661_IG29: ; func=00, offs=000480H, size=0009H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref Block predicted offs = 00000480, actual = 0000047A -> size adj = 6 IN00f3: 00047A movzx r12, cl IN00f4: 00047E mov ecx, eax IN00f5: 000480 shr rbx, cl ;; bbWeight=0.50 PerfScore 1.25 G_M6661_IG30: ; func=00, offs=000489H, size=003EH, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref, isz Block predicted offs = 00000489, actual = 00000483 -> size adj = 6 IN00f6: 000483 lea rcx, bword ptr [rsp+38H] ; byrRegs +[rcx] IN00f7: 000488 mov rax, gword ptr [rsp+D0H] ; gcrRegs +[rax] IN00f8: 000490 mov gword ptr [rcx], rax IN00f9: 000493 mov eax, dword ptr [rsp+D8H] ; gcrRegs -[rax] IN00fa: 00049A mov dword ptr [rcx+8], eax IN00fb: 00049D lea rcx, bword ptr [rsp+38H] IN00fc: 0004A2 call System.Numerics.BigInteger:op_Explicit(System.Numerics.BigInteger):long ; byrRegs -[rcx] ; gcr arg pop 0 IN00fd: 0004A7 mov ecx, r14d IN00fe: 0004AA shl rax, cl IN00ff: 0004AD lea rdx, [rax+rbx] IN0100: 0004B1 test r15d, r15d IN0101: 0004B4 jne SHORT G_M6661_IG31 IN0102: 0004B6 mov r8d, ebp IN0103: 0004B9 neg r8d IN0104: 0004BC dec r8d IN0105: 0004BF jmp SHORT G_M6661_IG32 ;; bbWeight=0.50 PerfScore 6.38 G_M6661_IG31: ; func=00, offs=0004C7H, size=0004H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref Block predicted offs = 000004C7, actual = 000004C1 -> size adj = 6 IN0106: 0004C1 lea r8d, [r15-2] ;; bbWeight=0.50 PerfScore 0.25 G_M6661_IG32: ; func=00, offs=0004CBH, size=0010H, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref Block predicted offs = 000004CB, actual = 000004C5 -> size adj = 6 IN0107: 0004C5 mov bword ptr [rsp+20H], rdi ; byr arg write IN0108: 0004CA mov rcx, rsi ; gcrRegs +[rcx] IN0109: 0004CD mov r9d, r12d IN010a: 0004D0 call FloatingPointType:AssembleFloatingPointValue(long,int,bool,byref):int:this ; gcrRegs -[rcx rsi] ; byrRegs -[rdi] ; gcr arg pop 0 ;; bbWeight=0.50 PerfScore 1.25 G_M6661_IG33: ; func=00, offs=0004DBH, size=0001H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref Block predicted offs = 000004DB, actual = 000004D5 -> size adj = 6 IN010b: 0004D5 nop ;; bbWeight=0.50 PerfScore 0.13 G_M6661_IG34: ; func=00, offs=0004DCH, size=0014H, epilog, nogc, extend Block predicted offs = 000004DC, actual = 000004D6 -> size adj = 6 IN0140: 0004D6 add rsp, 232 IN0141: 0004DD pop rbx IN0142: 0004DE pop rbp IN0143: 0004DF pop rsi IN0144: 0004E0 pop rdi IN0145: 0004E1 pop r12 IN0146: 0004E3 pop r13 IN0147: 0004E5 pop r14 IN0148: 0004E7 pop r15 IN0149: 0004E9 ret ;; bbWeight=0.50 PerfScore 2.63Allocated method code size = 1264 , actual size = 1258 ; Total bytes of code 1258, prolog size 85, PerfScore 265.23, instruction count 329 (MethodHash=3a6fe5fa) for method Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int ; ============================================================ *************** After end code gen, before unwindEmit() G_M6661_IG01: ; func=00, offs=000000H, size=005BH, bbWeight=1 PerfScore 16.83, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc, isz <-- Prolog IG IN010c: 000000 push r15 IN010d: 000002 push r14 IN010e: 000004 push r13 IN010f: 000006 push r12 IN0110: 000008 push rdi IN0111: 000009 push rsi IN0112: 00000A push rbp IN0113: 00000B push rbx IN0114: 00000C sub rsp, 232 IN0115: 000013 xor rax, rax IN0116: 000015 mov qword ptr [rsp+28H], rax IN0117: 00001A vxorps xmm4, xmm4 IN0118: 00001E vmovdqa xmmword ptr [rsp+30H], xmm4 IN0119: 000024 vmovdqa xmmword ptr [rsp+40H], xmm4 IN011a: 00002A mov rax, -144 IN011b: 000034 vmovdqa xmmword ptr [rsp+rax+E0H], xmm4 IN011c: 00003D vmovdqa xmmword ptr [rsp+rax+F0H], xmm4 IN011d: 000046 vmovdqa xmmword ptr [rsp+rax+100H], xmm4 IN011e: 00004F add rax, 48 IN011f: 000053 jne SHORT -5 instr IN0120: 000055 mov rsi, rdx IN0121: 000058 mov rdi, r8 G_M6661_IG02: ; offs=00005BH, size=0006H, bbWeight=1 PerfScore 4.00, gcrefRegs=00000040 {rsi}, byrefRegs=00000082 {rcx rdi}, byref IN0001: 00005B mov rbx, gword ptr [rcx] IN0002: 00005E mov ebp, dword ptr [rcx+8] G_M6661_IG03: ; offs=000061H, size=0006H, bbWeight=1 PerfScore 3.00, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref, isz IN0003: 000061 cmp dword ptr [rbx+8], 0 IN0004: 000065 jne SHORT G_M6661_IG06 G_M6661_IG04: ; offs=000067H, size=0014H, bbWeight=0.50 PerfScore 4.25, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref IN0005: 000067 mov rcx, rsi IN0006: 00006A mov rax, qword ptr [rsi] IN0007: 00006D mov rax, qword ptr [rax+80] IN0008: 000071 call qword ptr [rax]FloatingPointType:get_Zero():long:this IN0009: 000073 mov qword ptr [rdi], rax IN000a: 000076 mov eax, 1 G_M6661_IG05: ; offs=00007BH, size=0014H, bbWeight=0.50 PerfScore 2.63, epilog, nogc, extend IN0122: 00007B add rsp, 232 IN0123: 000082 pop rbx IN0124: 000083 pop rbp IN0125: 000084 pop rsi IN0126: 000085 pop rdi IN0127: 000086 pop r12 IN0128: 000088 pop r13 IN0129: 00008A pop r14 IN012a: 00008C pop r15 IN012b: 00008E ret G_M6661_IG06: ; offs=00008FH, size=0021H, bbWeight=0.50 PerfScore 5.88, gcVars=0000000000000000 {}, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, gcvars, byref, isz IN000b: 00008F mov rcx, rsi IN000c: 000092 mov rax, qword ptr [rsi] IN000d: 000095 mov rax, qword ptr [rax+72] IN000e: 000099 call qword ptr [rax+32]FloatingPointType:get_DenormalMantissaBits():ushort:this IN000f: 00009C inc eax IN0010: 00009E movzx r14, ax IN0011: 0000A2 inc r14d IN0012: 0000A5 mov ecx, ebp IN0013: 0000A7 test ecx, ecx IN0014: 0000A9 jle SHORT G_M6661_IG07 IN0015: 0000AB mov r15d, ebp IN0016: 0000AE jmp SHORT G_M6661_IG08 G_M6661_IG07: ; offs=0000B0H, size=0003H, bbWeight=0.50 PerfScore 0.13, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref IN0017: 0000B0 xor r15d, r15d G_M6661_IG08: ; offs=0000B3H, size=000BH, bbWeight=0.50 PerfScore 2.63, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref, isz IN0018: 0000B3 mov r12d, dword ptr [rbx+8] IN0019: 0000B7 cmp r15d, r12d IN001a: 0000BA jbe SHORT G_M6661_IG09 IN001b: 0000BC jmp SHORT G_M6661_IG10 G_M6661_IG09: ; offs=0000BEH, size=0003H, bbWeight=0.50 PerfScore 0.13, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref IN001c: 0000BE mov r12d, r15d G_M6661_IG10: ; offs=0000C1H, size=0064H, bbWeight=0.50 PerfScore 10.75, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref, isz IN001d: 0000C1 sub r15d, r12d IN001e: 0000C4 mov r13d, dword ptr [rbx+8] IN001f: 0000C8 mov eax, r13d IN0020: 0000CB sub eax, r12d IN0021: 0000CE mov dword ptr [V10 rsp+E4H], eax IN0022: 0000D5 lea rcx, bword ptr [V11 rsp+D0H] IN0023: 0000DD lea rdx, bword ptr [V73 rsp+48H] IN0024: 0000E2 mov gword ptr [rdx], rbx IN0025: 0000E5 mov dword ptr [rdx+8], ebp IN0026: 0000E8 lea rdx, bword ptr [V73 rsp+48H] IN0027: 0000ED mov r9d, r12d IN0028: 0000F0 xor r8d, r8d IN0029: 0000F3 call Microsoft.CodeAnalysis.RealParser:AccumulateDecimalDigitsIntoBigInteger(DecimalFloatingPointString,int,int):System.Numerics.BigInteger IN002a: 0000F8 test r15d, r15d IN002b: 0000FB je SHORT G_M6661_IG13 IN002c: 0000FD mov rcx, rsi IN002d: 000100 call FloatingPointType:get_OverflowDecimalExponent():int:this IN002e: 000105 movsxd rcx, eax IN002f: 000108 mov eax, r15d IN0030: 00010B cmp rcx, rax IN0031: 00010E jge SHORT G_M6661_IG12 IN0032: 000110 mov rcx, rsi IN0033: 000113 mov rax, qword ptr [rsi] IN0034: 000116 mov rax, qword ptr [rax+80] IN0035: 00011A call qword ptr [rax+8]FloatingPointType:get_Infinity():long:this IN0036: 00011D mov qword ptr [rdi], rax IN0037: 000120 mov eax, 3 G_M6661_IG11: ; offs=000125H, size=0014H, bbWeight=0.50 PerfScore 2.63, epilog, nogc, extend IN012c: 000125 add rsp, 232 IN012d: 00012C pop rbx IN012e: 00012D pop rbp IN012f: 00012E pop rsi IN0130: 00012F pop rdi IN0131: 000130 pop r12 IN0132: 000132 pop r13 IN0133: 000134 pop r14 IN0134: 000136 pop r15 IN0135: 000138 ret G_M6661_IG12: ; offs=000139H, size=0010H, bbWeight=0.50 PerfScore 0.88, gcVars=0000000000000000 {}, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, gcvars, byref IN0038: 000139 lea rcx, bword ptr [V11 rsp+D0H] IN0039: 000141 mov edx, r15d IN003a: 000144 call Microsoft.CodeAnalysis.RealParser:MultiplyByPowerOfTen(byref,int) G_M6661_IG13: ; offs=000149H, size=0046H, bbWeight=0.50 PerfScore 5.63, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref, isz IN003b: 000149 lea rcx, bword ptr [V76 rsp+38H] IN003c: 00014E mov rdx, gword ptr [V54 rsp+D0H] IN003d: 000156 mov gword ptr [rcx], rdx IN003e: 000159 mov edx, dword ptr [V55 rsp+D8H] IN003f: 000160 mov dword ptr [rcx+8], edx IN0040: 000163 lea rcx, bword ptr [V76 rsp+38H] IN0041: 000168 lea rdx, [V12 rsp+C8H] IN0042: 000170 call Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger,byref):int IN0043: 000175 mov r15d, eax IN0044: 000178 cmp r15d, r14d IN0045: 00017B jae SHORT G_M6661_IG14 IN0046: 00017D mov eax, dword ptr [V10 rsp+E4H] IN0047: 000184 test eax, eax IN0048: 000186 mov dword ptr [V10 rsp+E4H], eax IN0049: 00018D jne SHORT G_M6661_IG15 G_M6661_IG14: ; offs=00018FH, size=002DH, bbWeight=0.50 PerfScore 3.88, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref IN004a: 00018F mov bword ptr [V30+0x20 rsp+20H], rdi IN004b: 000194 cmp dword ptr [V10 rsp+E4H], 0 IN004c: 00019C setne r8b IN004d: 0001A0 movzx r8, r8b IN004e: 0001A4 mov rcx, gword ptr [V12 rsp+C8H] IN004f: 0001AC mov edx, r15d IN0050: 0001AF mov r9, rsi IN0051: 0001B2 call Microsoft.CodeAnalysis.RealParser:ConvertBigIntegerToFloatingPointBits(System.Byte[],int,bool,FloatingPointType,byref):int IN0052: 0001B7 jmp G_M6661_IG33 G_M6661_IG15: ; offs=0001BCH, size=000FH, bbWeight=0.50 PerfScore 2.25, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref, isz IN0053: 0001BC test ebp, ebp IN0054: 0001BE jl SHORT G_M6661_IG16 IN0055: 0001C0 mov eax, dword ptr [V10 rsp+E4H] IN0056: 0001C7 mov edx, eax IN0057: 0001C9 jmp SHORT G_M6661_IG17 G_M6661_IG16: ; offs=0001CBH, size=000BH, bbWeight=0.50 PerfScore 0.75, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref IN0058: 0001CB mov eax, dword ptr [V10 rsp+E4H] IN0059: 0001D2 mov edx, eax IN005a: 0001D4 sub edx, ebp G_M6661_IG17: ; offs=0001D6H, size=0044H, bbWeight=0.50 PerfScore 9.13, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref, isz IN005b: 0001D6 mov eax, edx IN005c: 0001D8 test r15d, r15d IN005d: 0001DB jne SHORT G_M6661_IG19 IN005e: 0001DD mov ecx, dword ptr [rbx+8] IN005f: 0001E0 movsxd rcx, ecx IN0060: 0001E3 mov dword ptr [V14 rsp+C4H], eax IN0061: 0001EA mov edx, eax IN0062: 0001EC sub rdx, rcx IN0063: 0001EF mov qword ptr [V38 rsp+78H], rdx IN0064: 0001F4 mov rcx, rsi IN0065: 0001F7 call FloatingPointType:get_OverflowDecimalExponent():int:this IN0066: 0001FC movsxd rcx, eax IN0067: 0001FF cmp rcx, qword ptr [V38 rsp+78H] IN0068: 000204 jge SHORT G_M6661_IG20 IN0069: 000206 mov rcx, rsi IN006a: 000209 mov rax, qword ptr [rsi] IN006b: 00020C mov rax, qword ptr [rax+80] IN006c: 000210 call qword ptr [rax]FloatingPointType:get_Zero():long:this IN006d: 000212 mov qword ptr [rdi], rax IN006e: 000215 mov eax, 2 G_M6661_IG18: ; offs=00021AH, size=0014H, bbWeight=0.50 PerfScore 2.63, epilog, nogc, extend IN0136: 00021A add rsp, 232 IN0137: 000221 pop rbx IN0138: 000222 pop rbp IN0139: 000223 pop rsi IN013a: 000224 pop rdi IN013b: 000225 pop r12 IN013c: 000227 pop r13 IN013d: 000229 pop r14 IN013e: 00022B pop r15 IN013f: 00022D ret G_M6661_IG19: ; offs=00022EH, size=0009H, bbWeight=0.25 PerfScore 0.75, gcVars=0000000000000000 {}, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, gcvars, byref, isz IN006f: 00022E mov dword ptr [V14 rsp+C4H], eax IN0070: 000235 jmp SHORT G_M6661_IG20 G_M6661_IG20: ; offs=000237H, size=00DBH, bbWeight=0.50 PerfScore 18.38, gcrefRegs=00000048 {rbx rsi}, byrefRegs=00000080 {rdi}, byref, isz IN0071: 000237 lea rcx, bword ptr [V15 rsp+B0H] IN0072: 00023F lea rdx, bword ptr [V73 rsp+48H] IN0073: 000244 mov gword ptr [rdx], rbx IN0074: 000247 mov dword ptr [rdx+8], ebp IN0075: 00024A lea rdx, bword ptr [V73 rsp+48H] IN0076: 00024F mov r8d, r12d IN0077: 000252 mov r9d, r13d IN0078: 000255 call Microsoft.CodeAnalysis.RealParser:AccumulateDecimalDigitsIntoBigInteger(DecimalFloatingPointString,int,int):System.Numerics.BigInteger IN0079: 00025A mov rcx, 0xD1FFAB1E IN007a: 000264 mov edx, 173 IN007b: 000269 call CORINFO_HELP_GETSHARED_NONGCSTATIC_BASE IN007c: 00026E mov rcx, 0xD1FFAB1E IN007d: 000278 mov rcx, gword ptr [rcx] IN007e: 00027B add rcx, 8 IN007f: 00027F mov rdx, gword ptr [rcx] IN0080: 000282 mov gword ptr [V58 rsp+A0H], rdx IN0081: 00028A mov ecx, dword ptr [rcx+8] IN0082: 00028D mov dword ptr [V59 rsp+A8H], ecx IN0083: 000294 lea rcx, bword ptr [V16 rsp+A0H] IN0084: 00029C mov edx, dword ptr [V14 rsp+C4H] IN0085: 0002A3 call Microsoft.CodeAnalysis.RealParser:MultiplyByPowerOfTen(byref,int) IN0086: 0002A8 mov rcx, gword ptr [V56 rsp+B0H] IN0087: 0002B0 mov edx, dword ptr [V57 rsp+B8H] IN0088: 0002B7 lea rax, bword ptr [V76 rsp+38H] IN0089: 0002BC mov gword ptr [rax], rcx IN008a: 0002BF mov dword ptr [rax+8], edx IN008b: 0002C2 lea rcx, bword ptr [V76 rsp+38H] IN008c: 0002C7 lea rdx, [V45 rsp+70H] IN008d: 0002CC call Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger,byref):int IN008e: 0002D1 mov ebx, eax IN008f: 0002D3 xor rcx, rcx IN0090: 0002D5 mov gword ptr [V45 rsp+70H], rcx IN0091: 0002DA mov rcx, gword ptr [V58 rsp+A0H] IN0092: 0002E2 mov edx, dword ptr [V59 rsp+A8H] IN0093: 0002E9 lea rax, bword ptr [V76 rsp+38H] IN0094: 0002EE mov gword ptr [rax], rcx IN0095: 0002F1 mov dword ptr [rax+8], edx IN0096: 0002F4 lea rcx, bword ptr [V76 rsp+38H] IN0097: 0002F9 lea rdx, [V48 rsp+68H] IN0098: 0002FE call Microsoft.CodeAnalysis.RealParser:CountSignificantBits(System.Numerics.BigInteger,byref):int IN0099: 000303 xor rcx, rcx IN009a: 000305 mov gword ptr [V48 rsp+68H], rcx IN009b: 00030A cmp eax, ebx IN009c: 00030C ja SHORT G_M6661_IG21 IN009d: 00030E xor ebp, ebp IN009e: 000310 jmp SHORT G_M6661_IG22 G_M6661_IG21: ; offs=000312H, size=0004H, bbWeight=0.50 PerfScore 0.25, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref IN009f: 000312 mov ebp, eax IN00a0: 000314 sub ebp, ebx G_M6661_IG22: ; offs=000316H, size=0013H, bbWeight=0.50 PerfScore 1.50, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref, isz IN00a1: 000316 test ebp, ebp IN00a2: 000318 je SHORT G_M6661_IG23 IN00a3: 00031A lea rcx, bword ptr [V15 rsp+B0H] IN00a4: 000322 mov edx, ebp IN00a5: 000324 call Microsoft.CodeAnalysis.RealParser:ShiftLeft(byref,int) G_M6661_IG23: ; offs=000329H, size=0033H, bbWeight=0.50 PerfScore 4.38, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref, isz IN00a6: 000329 sub r14d, r15d IN00a7: 00032C mov ebx, r14d IN00a8: 00032F test r15d, r15d IN00a9: 000332 je SHORT G_M6661_IG25 IN00aa: 000334 cmp ebp, r14d IN00ab: 000337 jbe SHORT G_M6661_IG24 IN00ac: 000339 mov bword ptr [V30+0x20 rsp+20H], rdi IN00ad: 00033E mov r8d, 1 IN00ae: 000344 mov rcx, gword ptr [V12 rsp+C8H] IN00af: 00034C mov edx, r15d IN00b0: 00034F mov r9, rsi IN00b1: 000352 call Microsoft.CodeAnalysis.RealParser:ConvertBigIntegerToFloatingPointBits(System.Byte[],int,bool,FloatingPointType,byref):int IN00b2: 000357 jmp G_M6661_IG33 G_M6661_IG24: ; offs=00035CH, size=0005H, bbWeight=0.50 PerfScore 0.25, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref IN00b3: 00035C mov ebx, r14d IN00b4: 00035F sub ebx, ebp G_M6661_IG25: ; offs=000361H, size=004BH, bbWeight=0.50 PerfScore 7.00, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref, isz IN00b5: 000361 mov rcx, gword ptr [V56 rsp+B0H] IN00b6: 000369 mov gword ptr [V68 rsp+58H], rcx IN00b7: 00036E mov ecx, dword ptr [V57 rsp+B8H] IN00b8: 000375 mov dword ptr [V69 rsp+60H], ecx IN00b9: 000379 mov rcx, gword ptr [V58 rsp+A0H] IN00ba: 000381 mov edx, dword ptr [V59 rsp+A8H] IN00bb: 000388 lea rax, bword ptr [V49 rsp+58H] IN00bc: 00038D lea r8, bword ptr [V76 rsp+38H] IN00bd: 000392 mov gword ptr [r8], rcx IN00be: 000395 mov dword ptr [r8+8], edx IN00bf: 000399 mov rcx, rax IN00c0: 00039C lea rdx, bword ptr [V76 rsp+38H] IN00c1: 0003A1 call System.Numerics.BigInteger:CompareTo(System.Numerics.BigInteger):int:this IN00c2: 0003A6 test eax, eax IN00c3: 0003A8 jl SHORT G_M6661_IG26 IN00c4: 0003AA jmp SHORT G_M6661_IG27 G_M6661_IG26: ; offs=0003ACH, size=0002H, bbWeight=0.50 PerfScore 0.13, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref IN00c5: 0003AC inc ebp G_M6661_IG27: ; offs=0003AEH, size=00CAH, bbWeight=0.50 PerfScore 16.25, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref, isz IN00c6: 0003AE lea rcx, bword ptr [V15 rsp+B0H] IN00c7: 0003B6 mov edx, ebx IN00c8: 0003B8 call Microsoft.CodeAnalysis.RealParser:ShiftLeft(byref,int) IN00c9: 0003BD lea rcx, bword ptr [V35 rsp+80H] IN00ca: 0003C5 lea rdx, bword ptr [V76 rsp+38H] IN00cb: 0003CA mov r8, gword ptr [V56 rsp+B0H] IN00cc: 0003D2 mov gword ptr [rdx], r8 IN00cd: 0003D5 mov r8d, dword ptr [V57 rsp+B8H] IN00ce: 0003DD mov dword ptr [rdx+8], r8d IN00cf: 0003E1 lea rdx, bword ptr [V86 rsp+28H] IN00d0: 0003E6 mov r8, gword ptr [V58 rsp+A0H] IN00d1: 0003EE mov gword ptr [rdx], r8 IN00d2: 0003F1 mov r8d, dword ptr [V59 rsp+A8H] IN00d3: 0003F9 mov dword ptr [rdx+8], r8d IN00d4: 0003FD lea rdx, bword ptr [V76 rsp+38H] IN00d5: 000402 lea r8, bword ptr [V86 rsp+28H] IN00d6: 000407 lea r9, bword ptr [V23 rsp+90H] IN00d7: 00040F call System.Numerics.BigInteger:DivRem(System.Numerics.BigInteger,System.Numerics.BigInteger,byref):System.Numerics.BigInteger IN00d8: 000414 lea rcx, bword ptr [V76 rsp+38H] IN00d9: 000419 mov rax, gword ptr [V62 rsp+80H] IN00da: 000421 mov gword ptr [rcx], rax IN00db: 000424 mov eax, dword ptr [V63 rsp+88H] IN00dc: 00042B mov dword ptr [rcx+8], eax IN00dd: 00042E lea rcx, bword ptr [V76 rsp+38H] IN00de: 000433 call System.Numerics.BigInteger:op_Explicit(System.Numerics.BigInteger):long IN00df: 000438 mov rbx, rax IN00e0: 00043B cmp dword ptr [V61 rsp+98H], 0 IN00e1: 000443 sete r12b IN00e2: 000447 movzx r12, r12b IN00e3: 00044B mov rcx, rbx IN00e4: 00044E call Microsoft.CodeAnalysis.RealParser:CountSignificantBits(long):int IN00e5: 000453 cmp eax, r14d IN00e6: 000456 jbe SHORT G_M6661_IG30 IN00e7: 000458 sub eax, r14d IN00e8: 00045B test r12d, r12d IN00e9: 00045E je SHORT G_M6661_IG28 IN00ea: 000460 mov edx, 1 IN00eb: 000465 mov ecx, eax IN00ec: 000467 shl rdx, cl IN00ed: 00046A dec rdx IN00ee: 00046D test rbx, rdx IN00ef: 000470 sete cl IN00f0: 000473 movzx rcx, cl IN00f1: 000476 jmp SHORT G_M6661_IG29 G_M6661_IG28: ; offs=000478H, size=0002H, bbWeight=0.50 PerfScore 0.13, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref IN00f2: 000478 xor ecx, ecx G_M6661_IG29: ; offs=00047AH, size=0009H, bbWeight=0.50 PerfScore 1.25, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref IN00f3: 00047A movzx r12, cl IN00f4: 00047E mov ecx, eax IN00f5: 000480 shr rbx, cl G_M6661_IG30: ; offs=000483H, size=003EH, bbWeight=0.50 PerfScore 6.38, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref, isz IN00f6: 000483 lea rcx, bword ptr [V76 rsp+38H] IN00f7: 000488 mov rax, gword ptr [V54 rsp+D0H] IN00f8: 000490 mov gword ptr [rcx], rax IN00f9: 000493 mov eax, dword ptr [V55 rsp+D8H] IN00fa: 00049A mov dword ptr [rcx+8], eax IN00fb: 00049D lea rcx, bword ptr [V76 rsp+38H] IN00fc: 0004A2 call System.Numerics.BigInteger:op_Explicit(System.Numerics.BigInteger):long IN00fd: 0004A7 mov ecx, r14d IN00fe: 0004AA shl rax, cl IN00ff: 0004AD lea rdx, [rax+rbx] IN0100: 0004B1 test r15d, r15d IN0101: 0004B4 jne SHORT G_M6661_IG31 IN0102: 0004B6 mov r8d, ebp IN0103: 0004B9 neg r8d IN0104: 0004BC dec r8d IN0105: 0004BF jmp SHORT G_M6661_IG32 G_M6661_IG31: ; offs=0004C1H, size=0004H, bbWeight=0.50 PerfScore 0.25, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref IN0106: 0004C1 lea r8d, [r15-2] G_M6661_IG32: ; offs=0004C5H, size=0010H, bbWeight=0.50 PerfScore 1.25, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi}, byref IN0107: 0004C5 mov bword ptr [V30+0x20 rsp+20H], rdi IN0108: 0004CA mov rcx, rsi IN0109: 0004CD mov r9d, r12d IN010a: 0004D0 call FloatingPointType:AssembleFloatingPointValue(long,int,bool,byref):int:this G_M6661_IG33: ; offs=0004D5H, size=0001H, bbWeight=0.50 PerfScore 0.13, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref IN010b: 0004D5 nop G_M6661_IG34: ; offs=0004D6H, size=0014H, bbWeight=0.50 PerfScore 2.63, epilog, nogc, extend IN0140: 0004D6 add rsp, 232 IN0141: 0004DD pop rbx IN0142: 0004DE pop rbp IN0143: 0004DF pop rsi IN0144: 0004E0 pop rdi IN0145: 0004E1 pop r12 IN0146: 0004E3 pop r13 IN0147: 0004E5 pop r14 IN0148: 0004E7 pop r15 IN0149: 0004E9 ret *************** Finishing PHASE Emit code *************** Starting PHASE Emit GC+EH tables Unwind Info: >> Start offset : 0x000000 (not in unwind data) >> End offset : 0xd1ffab1e (not in unwind data) Version : 1 Flags : 0x00 SizeOfProlog : 0x13 CountOfUnwindCodes: 10 FrameRegister : none (0) FrameOffset : N/A (no FrameRegister) (Value=0) UnwindCodes : CodeOffset: 0x13 UnwindOp: UWOP_ALLOC_LARGE (1) OpInfo: 0 - Scaled small Size: 29 * 8 = 232 = 0x000E8 CodeOffset: 0x0C UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbx (3) CodeOffset: 0x0B UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbp (5) CodeOffset: 0x0A UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rsi (6) CodeOffset: 0x09 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rdi (7) CodeOffset: 0x08 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: r12 (12) CodeOffset: 0x06 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: r13 (13) CodeOffset: 0x04 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: r14 (14) CodeOffset: 0x02 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: r15 (15) allocUnwindInfo(pHotCode=0x00000000D1FFAB1E, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x4ea, unwindSize=0x18, pUnwindBlock=0x00000000D1FFAB1E, funKind=0 (main function)) *************** In genIPmappingGen() IP mapping count : 53 IL offs PROLOG : 0x00000000 ( STACK_EMPTY ) IL offs 0x0000 : 0x00000061 ( STACK_EMPTY ) IL offs 0x000D : 0x00000067 ( STACK_EMPTY ) IL offs EPILOG : 0x0000007B ( STACK_EMPTY ) IL offs 0x0020 : 0x000000A5 ( STACK_EMPTY ) IL offs NO_MAP : 0x000000B3 ( STACK_EMPTY ) IL offs 0x0042 : 0x000000C4 ( STACK_EMPTY ) IL offs 0x004F : 0x000000C8 ( STACK_EMPTY ) IL offs 0x0061 : 0x000000F8 ( STACK_EMPTY ) IL offs 0x0070 : 0x00000110 ( STACK_EMPTY ) IL offs EPILOG : 0x00000125 ( STACK_EMPTY ) IL offs 0x007A : 0x00000139 ( STACK_EMPTY ) IL offs 0x008D : 0x00000178 ( STACK_EMPTY ) IL offs 0x0092 : 0x0000017D ( STACK_EMPTY ) IL offs 0x0096 : 0x0000018F ( STACK_EMPTY ) IL offs 0x00A7 : 0x000001BC ( STACK_EMPTY ) IL offs 0x00B0 : 0x000001C0 ( STACK_EMPTY ) IL offs 0x00B4 : 0x000001CB ( STACK_EMPTY ) IL offs 0x00C0 : 0x000001D8 ( STACK_EMPTY ) IL offs 0x00D9 : 0x00000206 ( STACK_EMPTY ) IL offs EPILOG : 0x0000021A ( STACK_EMPTY ) IL offs NO_MAP : 0x0000022E ( STACK_EMPTY ) IL offs 0x00EF : 0x0000025A ( STACK_EMPTY ) IL offs 0x00F6 : 0x00000294 ( STACK_EMPTY ) IL offs 0x00FF : 0x000002A8 ( STACK_EMPTY ) IL offs 0x0108 : 0x000002DA ( STACK_EMPTY ) IL offs 0x0111 : 0x0000030A ( STACK_EMPTY ) IL offs 0x0117 : 0x0000030E ( STACK_EMPTY ) IL offs 0x011A : 0x00000312 ( STACK_EMPTY ) IL offs 0x0121 : 0x00000316 ( STACK_EMPTY ) IL offs 0x0126 : 0x0000031A ( STACK_EMPTY ) IL offs 0x012F : 0x00000329 ( STACK_EMPTY ) IL offs 0x0135 : 0x0000032C ( STACK_EMPTY ) IL offs 0x0139 : 0x0000032F ( STACK_EMPTY ) IL offs 0x013E : 0x00000334 ( STACK_EMPTY ) IL offs 0x0144 : 0x00000339 ( STACK_EMPTY ) IL offs 0x0155 : 0x0000035C ( STACK_EMPTY ) IL offs 0x015C : 0x00000361 ( STACK_EMPTY ) IL offs 0x0167 : 0x000003AA ( STACK_EMPTY ) IL offs 0x016B : 0x000003AC ( STACK_EMPTY ) IL offs 0x0171 : 0x000003AE ( STACK_EMPTY ) IL offs 0x017A : 0x000003BD ( STACK_EMPTY ) IL offs 0x019E : 0x00000453 ( STACK_EMPTY ) IL offs 0x01A4 : 0x00000458 ( STACK_EMPTY ) IL offs 0x01AB : 0x0000045B ( STACK_EMPTY ) IL offs 0x01AF : 0x00000460 ( STACK_EMPTY ) IL offs 0x01C3 : 0x00000478 ( STACK_EMPTY ) IL offs 0x01C6 : 0x0000047E ( STACK_EMPTY ) IL offs 0x01E2 : 0x000004B1 ( STACK_EMPTY ) IL offs 0x01E7 : 0x000004B6 ( STACK_EMPTY ) IL offs 0x01EE : 0x000004C1 ( STACK_EMPTY ) IL offs 0x01F4 : 0x000004C5 ( STACK_EMPTY ) IL offs EPILOG : 0x000004D5 ( STACK_EMPTY ) *************** In genSetScopeInfo() VarLocInfo count is 51 ; Variable debug info: 51 live range(s), 18 var(s) for method Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int 0( UNKNOWN) : From 00000000h to 0000005Bh, in rcx 1( UNKNOWN) : From 00000000h to 0000005Bh, in rdx 2( UNKNOWN) : From 00000000h to 0000005Bh, in r8 1( UNKNOWN) : From 00000061h to 0000006Ah, in rsi 2( UNKNOWN) : From 00000061h to 00000073h, in rdi 10( UNKNOWN) : From 000000FDh to 00000110h, in rax 5( UNKNOWN) : From 000000FDh to 00000110h, in r15 8( UNKNOWN) : From 000000FDh to 00000110h, in r12 3( UNKNOWN) : From 000000ABh to 00000110h, in r14 9( UNKNOWN) : From 000000FDh to 00000110h, in r13 1( UNKNOWN) : From 0000008Fh to 00000113h, in rsi 2( UNKNOWN) : From 0000008Fh to 0000011Dh, in rdi 5( UNKNOWN) : From 00000139h to 00000141h, in r15 8( UNKNOWN) : From 00000139h to 0000018Fh, in r12 3( UNKNOWN) : From 00000139h to 0000018Fh, in r14 9( UNKNOWN) : From 00000139h to 0000018Fh, in r13 2( UNKNOWN) : From 00000139h to 0000018Fh, in rdi 10( UNKNOWN) : From 00000139h to 00000194h, in rax 13( UNKNOWN) : From 0000017Dh to 000001ACh, in r15 1( UNKNOWN) : From 00000139h to 000001AFh, in rsi 10( UNKNOWN) : From 000001BCh to 000001C7h, in rax 10( UNKNOWN) : From 000001CBh to 000001D2h, in rax 13( UNKNOWN) : From 000001BCh to 00000206h, in r15 8( UNKNOWN) : From 000001BCh to 00000206h, in r12 3( UNKNOWN) : From 000001BCh to 00000206h, in r14 9( UNKNOWN) : From 000001BCh to 00000206h, in r13 14( UNKNOWN) : From 000001DDh to 00000206h, in rdx 1( UNKNOWN) : From 000001BCh to 00000209h, in rsi 2( UNKNOWN) : From 000001BCh to 00000212h, in rdi 8( UNKNOWN) : From 00000237h to 0000024Fh, in r12 9( UNKNOWN) : From 00000237h to 00000252h, in r13 14( UNKNOWN) : From 00000237h to 000002A3h, in rdx 3( UNKNOWN) : From 00000237h to 00000329h, in r14 19( UNKNOWN) : From 0000031Ah to 00000339h, in rbp 20( UNKNOWN) : From 00000334h to 00000339h, in r14 2( UNKNOWN) : From 00000237h to 00000339h, in rdi 13( UNKNOWN) : From 00000237h to 0000034Ch, in r15 1( UNKNOWN) : From 00000237h to 0000034Fh, in rsi 19( UNKNOWN) : From 0000035Ch to 000003AAh, in rbp 21( UNKNOWN) : From 00000361h to 000003B6h, in rbx 25( UNKNOWN) : From 00000458h to 0000045Bh, in r12 24( UNKNOWN) : From 00000458h to 0000047Eh, in rbx 29( UNKNOWN) : From 00000460h to 0000047Eh, in rax 20( UNKNOWN) : From 0000035Ch to 000004A7h, in r14 24( UNKNOWN) : From 00000483h to 000004ADh, in rbx 13( UNKNOWN) : From 0000035Ch to 000004B6h, in r15 22( UNKNOWN) : From 00000458h to 000004B6h, in rbp 2( UNKNOWN) : From 0000035Ch to 000004C5h, in rdi 1( UNKNOWN) : From 0000035Ch to 000004CAh, in rsi 27( UNKNOWN) : From 000004B6h to 000004CDh, in rdx 25( UNKNOWN) : From 00000483h to 000004CDh, in r12 *************** In gcInfoBlockHdrSave() Set code length to 1258. Set ReturnKind to Scalar. Set Outgoing stack arg area size to 40. Stack slot id for offset 208 (0xd0) (sp) (untracked) = 0. Stack slot id for offset 200 (0xc8) (sp) (untracked) = 1. Stack slot id for offset 176 (0xb0) (sp) (untracked) = 2. Stack slot id for offset 160 (0xa0) (sp) (untracked) = 3. Stack slot id for offset 144 (0x90) (sp) (untracked) = 4. Stack slot id for offset 128 (0x80) (sp) (untracked) = 5. Stack slot id for offset 112 (0x70) (sp) (untracked) = 6. Stack slot id for offset 104 (0x68) (sp) (untracked) = 7. Stack slot id for offset 88 (0x58) (sp) (untracked) = 8. Stack slot id for offset 72 (0x48) (sp) (untracked) = 9. Stack slot id for offset 56 (0x38) (sp) (untracked) = 10. Stack slot id for offset 40 (0x28) (sp) (untracked) = 11. Register slot id for reg rdi (byref) = 12. Register slot id for reg rbx = 13. Register slot id for reg rsi = 14. Set state of slot 12 at instr offset 0x71 to Live. Set state of slot 12 at instr offset 0x73 to Dead. Set state of slot 13 at instr offset 0x99 to Live. Set state of slot 14 at instr offset 0x99 to Live. Set state of slot 12 at instr offset 0x99 to Live. Set state of slot 13 at instr offset 0x9c to Dead. Set state of slot 14 at instr offset 0x9c to Dead. Set state of slot 12 at instr offset 0x9c to Dead. Set state of slot 13 at instr offset 0xf3 to Live. Set state of slot 14 at instr offset 0xf3 to Live. Set state of slot 12 at instr offset 0xf3 to Live. Set state of slot 13 at instr offset 0xf8 to Dead. Set state of slot 14 at instr offset 0xf8 to Dead. Set state of slot 12 at instr offset 0xf8 to Dead. Set state of slot 13 at instr offset 0x100 to Live. Set state of slot 14 at instr offset 0x100 to Live. Set state of slot 12 at instr offset 0x100 to Live. Set state of slot 13 at instr offset 0x105 to Dead. Set state of slot 14 at instr offset 0x105 to Dead. Set state of slot 12 at instr offset 0x105 to Dead. Set state of slot 12 at instr offset 0x11a to Live. Set state of slot 12 at instr offset 0x11d to Dead. Set state of slot 13 at instr offset 0x144 to Live. Set state of slot 14 at instr offset 0x144 to Live. Set state of slot 12 at instr offset 0x144 to Live. Set state of slot 13 at instr offset 0x149 to Dead. Set state of slot 14 at instr offset 0x149 to Dead. Set state of slot 12 at instr offset 0x149 to Dead. Set state of slot 13 at instr offset 0x170 to Live. Set state of slot 14 at instr offset 0x170 to Live. Set state of slot 12 at instr offset 0x170 to Live. Set state of slot 13 at instr offset 0x175 to Dead. Set state of slot 14 at instr offset 0x175 to Dead. Set state of slot 12 at instr offset 0x175 to Dead. Set state of slot 13 at instr offset 0x1f7 to Live. Set state of slot 14 at instr offset 0x1f7 to Live. Set state of slot 12 at instr offset 0x1f7 to Live. Set state of slot 13 at instr offset 0x1fc to Dead. Set state of slot 14 at instr offset 0x1fc to Dead. Set state of slot 12 at instr offset 0x1fc to Dead. Set state of slot 12 at instr offset 0x210 to Live. Set state of slot 12 at instr offset 0x212 to Dead. Set state of slot 14 at instr offset 0x255 to Live. Set state of slot 12 at instr offset 0x255 to Live. Set state of slot 14 at instr offset 0x25a to Dead. Set state of slot 12 at instr offset 0x25a to Dead. Set state of slot 14 at instr offset 0x269 to Live. Set state of slot 12 at instr offset 0x269 to Live. Set state of slot 14 at instr offset 0x26e to Dead. Set state of slot 12 at instr offset 0x26e to Dead. Set state of slot 14 at instr offset 0x2a3 to Live. Set state of slot 12 at instr offset 0x2a3 to Live. Set state of slot 14 at instr offset 0x2a8 to Dead. Set state of slot 12 at instr offset 0x2a8 to Dead. Set state of slot 14 at instr offset 0x2cc to Live. Set state of slot 12 at instr offset 0x2cc to Live. Set state of slot 14 at instr offset 0x2d1 to Dead. Set state of slot 12 at instr offset 0x2d1 to Dead. Set state of slot 14 at instr offset 0x2fe to Live. Set state of slot 12 at instr offset 0x2fe to Live. Set state of slot 14 at instr offset 0x303 to Dead. Set state of slot 12 at instr offset 0x303 to Dead. Set state of slot 14 at instr offset 0x324 to Live. Set state of slot 12 at instr offset 0x324 to Live. Set state of slot 14 at instr offset 0x329 to Dead. Set state of slot 12 at instr offset 0x329 to Dead. Set state of slot 14 at instr offset 0x3a1 to Live. Set state of slot 12 at instr offset 0x3a1 to Live. Set state of slot 14 at instr offset 0x3a6 to Dead. Set state of slot 12 at instr offset 0x3a6 to Dead. Set state of slot 14 at instr offset 0x3b8 to Live. Set state of slot 12 at instr offset 0x3b8 to Live. Set state of slot 14 at instr offset 0x3bd to Dead. Set state of slot 12 at instr offset 0x3bd to Dead. Set state of slot 14 at instr offset 0x40f to Live. Set state of slot 12 at instr offset 0x40f to Live. Set state of slot 14 at instr offset 0x414 to Dead. Set state of slot 12 at instr offset 0x414 to Dead. Set state of slot 14 at instr offset 0x433 to Live. Set state of slot 12 at instr offset 0x433 to Live. Set state of slot 14 at instr offset 0x438 to Dead. Set state of slot 12 at instr offset 0x438 to Dead. Set state of slot 14 at instr offset 0x44e to Live. Set state of slot 12 at instr offset 0x44e to Live. Set state of slot 14 at instr offset 0x453 to Dead. Set state of slot 12 at instr offset 0x453 to Dead. Set state of slot 14 at instr offset 0x4a2 to Live. Set state of slot 12 at instr offset 0x4a2 to Live. Set state of slot 14 at instr offset 0x4a7 to Dead. Set state of slot 12 at instr offset 0x4a7 to Dead. Defining 24 call sites: Offset 0x71, size 2. Offset 0x99, size 3. Offset 0xf3, size 5. Offset 0x100, size 5. Offset 0x11a, size 3. Offset 0x144, size 5. Offset 0x170, size 5. Offset 0x1b2, size 5. Offset 0x1f7, size 5. Offset 0x210, size 2. Offset 0x255, size 5. Offset 0x269, size 5. Offset 0x2a3, size 5. Offset 0x2cc, size 5. Offset 0x2fe, size 5. Offset 0x324, size 5. Offset 0x352, size 5. Offset 0x3a1, size 5. Offset 0x3b8, size 5. Offset 0x40f, size 5. Offset 0x433, size 5. Offset 0x44e, size 5. Offset 0x4a2, size 5. Offset 0x4d0, size 5. *************** Finishing PHASE Emit GC+EH tables Method code size: 1258 Allocations for Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int (MethodHash=3a6fe5fa) count: 11827, size: 747226, max = 10920 allocateMemory: 786432, nraUsed: 763720 Alloc'd bytes by kind: kind | size | pct ---------------------+------------+-------- AssertionProp | 9660 | 1.29% ASTNode | 135832 | 18.18% InstDesc | 28376 | 3.80% ImpStack | 504 | 0.07% BasicBlock | 16776 | 2.25% fgArgInfo | 3456 | 0.46% fgArgInfoPtrArr | 576 | 0.08% FlowList | 2784 | 0.37% TreeStatementList | 256 | 0.03% SiScope | 4072 | 0.54% DominatorMemory | 2160 | 0.29% LSRA | 11760 | 1.57% LSRA_Interval | 19040 | 2.55% LSRA_RefPosition | 61248 | 8.20% Reachability | 64 | 0.01% SSA | 14920 | 2.00% ValueNumber | 26605 | 3.56% LvaTable | 18484 | 2.47% UnwindInfo | 0 | 0.00% hashBv | 1896 | 0.25% bitset | 8528 | 1.14% FixedBitVect | 304 | 0.04% Generic | 16024 | 2.14% LocalAddressVisitor | 512 | 0.07% FieldSeqStore | 416 | 0.06% ZeroOffsetFieldMap | 984 | 0.13% ArrayInfoMap | 80 | 0.01% MemoryPhiArg | 192 | 0.03% CSE | 5328 | 0.71% GC | 10156 | 1.36% CorTailCallInfo | 0 | 0.00% Inlining | 17800 | 2.38% ArrayStack | 1920 | 0.26% DebugInfo | 2928 | 0.39% DebugOnly | 308443 | 41.28% Codegen | 1176 | 0.16% LoopOpt | 0 | 0.00% LoopHoist | 0 | 0.00% Unknown | 3414 | 0.46% RangeCheck | 0 | 0.00% CopyProp | 10176 | 1.36% SideEffects | 0 | 0.00% ObjectAllocator | 0 | 0.00% VariableLiveRanges | 0 | 0.00% ClassLayout | 152 | 0.02% TailMergeThrows | 0 | 0.00% EarlyProp | 0 | 0.00% ZeroInit | 224 | 0.03% ****** DONE compiling Microsoft.CodeAnalysis.RealParser:ConvertDecimalToFloatingPointBits(DecimalFloatingPointString,FloatingPointType,byref):int Completed assembly Microsoft.CodeAnalysis - #types: 1793, #methods: 14034, skipped types: 73, skipped methods: 1163