****** START compiling Runtime_49101:Main():int (MethodHash=6f90ac62)
Generating code for Windows x64
OPTIONS: compCodeOpt = BLENDED_CODE
OPTIONS: compDbgCode = false
OPTIONS: compDbgInfo = true
OPTIONS: compDbgEnC  = false
OPTIONS: compProcedureSplitting   = false
OPTIONS: compProcedureSplittingEH = false
IL to import:
IL_0000  12 00             ldloca.s     0x0
IL_0002  17                ldc.i4.1
IL_0003  7d 01 00 00 04    stfld        0x4000001
IL_0008  12 00             ldloca.s     0x0
IL_000a  18                ldc.i4.2
IL_000b  7d 02 00 00 04    stfld        0x4000002
IL_0010  12 00             ldloca.s     0x0
IL_0012  19                ldc.i4.3
IL_0013  7d 03 00 00 04    stfld        0x4000003
IL_0018  12 00             ldloca.s     0x0
IL_001a  1a                ldc.i4.4
IL_001b  7d 04 00 00 04    stfld        0x4000004
IL_0020  12 00             ldloca.s     0x0
IL_0022  1b                ldc.i4.5
IL_0023  7d 05 00 00 04    stfld        0x4000005
IL_0028  06                ldloc.0
IL_0029  28 01 00 00 06    call         0x6000001
IL_002e  06                ldloc.0
IL_002f  7b 03 00 00 04    ldfld        0x4000003
IL_0034  1f 0a             ldc.i4.s     0xA
IL_0036  33 03             bne.un.s     3 (IL_003b)
IL_0038  1f 0a             ldc.i4.s     0xA
IL_003a  2a                ret
IL_003b  06                ldloc.0
IL_003c  7b 01 00 00 04    ldfld        0x4000001
IL_0041  06                ldloc.0
IL_0042  7b 02 00 00 04    ldfld        0x4000002
IL_0047  58                add
IL_0048  06                ldloc.0
IL_0049  7b 03 00 00 04    ldfld        0x4000003
IL_004e  58                add
IL_004f  2a                ret

lvaGrabTemp returning 1 (V01 tmp0) (a long lifetime temp) called for OutgoingArgSpace.
; Initial local variable assignments
;
;  V00 loc0           struct <S, 20>
;  V01 OutArgs        lclBlk <na>  "OutgoingArgSpace"
*************** In compInitDebuggingInfo() for Runtime_49101:Main():int
getVars() returned cVars = 0, extendOthers = true
info.compVarScopesCount = 1
        VarNum  LVNum         Name      Beg     End
 0:     00h     00h       V00 loc0      000h    050h
info.compStmtOffsetsCount    = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for Runtime_49101:Main():int
Jump targets:
  IL_003b
New Basic Block BB01 [0000] created.
BB01 [000..038)
New Basic Block BB02 [0001] created.
BB02 [038..03B)
New Basic Block BB03 [0002] created.
BB03 [03B..050)
IL Code Size,Instr   80,  32, Basic Block count   3, Local Variable Num,Ref count   2, 10 for method Runtime_49101:Main():int
OPTIONS: opts.MinOpts() == false
Basic block list for 'Runtime_49101:Main():int'

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd                 weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..038)-> BB03 ( cond )   
BB02 [0001]  1                             1       [038..03B)        (return)   
BB03 [0002]  1                             1       [03B..050)        (return)   
-----------------------------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Pre-import

*************** Finishing PHASE Pre-import

*************** Starting PHASE Profile incorporation
BBOPT set, but no profile data available (hr=80004001)

*************** Finishing PHASE Profile incorporation [no changes]

*************** Starting PHASE Importation
*************** In impImport() for Runtime_49101:Main():int

impImportBlockPending for BB01

Importing BB01 (PC=000) of 'Runtime_49101:Main():int'
    [ 0]   0 (0x000) ldloca.s 0
    [ 1]   2 (0x002) ldc.i4.1 1
    [ 2]   3 (0x003) stfld 04000001

STMT00000 (IL 0x000...  ???)
               [000004] -A----------              *  ASG       int
               [000003] -------N----              +--*  FIELD     int    i1
               [000001] ------------              |  \--*  ADDR      byref
               [000000] -------N----              |     \--*  LCL_VAR   struct<S, 20> V00 loc0
               [000002] ------------              \--*  CNS_INT   int    1

    [ 0]   8 (0x008) ldloca.s 0
    [ 1]  10 (0x00a) ldc.i4.2 2
    [ 2]  11 (0x00b) stfld 04000002

STMT00001 (IL 0x008...  ???)
               [000009] -A----------              *  ASG       int
               [000008] -------N----              +--*  FIELD     int    i2
               [000006] ------------              |  \--*  ADDR      byref
               [000005] -------N----              |     \--*  LCL_VAR   struct<S, 20> V00 loc0
               [000007] ------------              \--*  CNS_INT   int    2

    [ 0]  16 (0x010) ldloca.s 0
    [ 1]  18 (0x012) ldc.i4.3 3
    [ 2]  19 (0x013) stfld 04000003

STMT00002 (IL 0x010...  ???)
               [000014] -A----------              *  ASG       int
               [000013] -------N----              +--*  FIELD     int    i3
               [000011] ------------              |  \--*  ADDR      byref
               [000010] -------N----              |     \--*  LCL_VAR   struct<S, 20> V00 loc0
               [000012] ------------              \--*  CNS_INT   int    3

    [ 0]  24 (0x018) ldloca.s 0
    [ 1]  26 (0x01a) ldc.i4.4 4
    [ 2]  27 (0x01b) stfld 04000004

STMT00003 (IL 0x018...  ???)
               [000019] -A----------              *  ASG       int
               [000018] -------N----              +--*  FIELD     int    i4
               [000016] ------------              |  \--*  ADDR      byref
               [000015] -------N----              |     \--*  LCL_VAR   struct<S, 20> V00 loc0
               [000017] ------------              \--*  CNS_INT   int    4

    [ 0]  32 (0x020) ldloca.s 0
    [ 1]  34 (0x022) ldc.i4.5 5
    [ 2]  35 (0x023) stfld 04000005

STMT00004 (IL 0x020...  ???)
               [000024] -A----------              *  ASG       int
               [000023] -------N----              +--*  FIELD     int    i5
               [000021] ------------              |  \--*  ADDR      byref
               [000020] -------N----              |     \--*  LCL_VAR   struct<S, 20> V00 loc0
               [000022] ------------              \--*  CNS_INT   int    5

    [ 0]  40 (0x028) ldloc.0
    [ 1]  41 (0x029) call 06000001
In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0
Calling impNormStructVal on:
               [000025] ------------              *  LCL_VAR   struct<S, 20> V00 loc0
resulting tree:
               [000028] n-----------              *  OBJ       struct<S, 20>
               [000027] ------------              \--*  ADDR      byref
               [000025] -------N----                 \--*  LCL_VAR   struct<S, 20> V00 loc0
INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'Runtime_49101:Main():int' calling 'Runtime_49101:Test(S)'
INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result'


STMT00005 (IL 0x028...  ???)
               [000026] --C-G-------              *  CALL      void   Runtime_49101.Test
               [000028] n----------- arg0         \--*  OBJ       struct<S, 20>
               [000027] ------------                 \--*  ADDR      byref
               [000025] -------N----                    \--*  LCL_VAR   struct<S, 20> V00 loc0

    [ 0]  46 (0x02e) ldloc.0
    [ 1]  47 (0x02f) ldfld 04000003
    [ 1]  52 (0x034) ldc.i4.s 10
    [ 2]  54 (0x036) bne.un.s

STMT00006 (IL 0x02E...  ???)
               [000034] ------------              *  JTRUE     void
               [000033] N--------U--              \--*  NE        int
               [000031] ------------                 +--*  FIELD     int    i3
               [000030] ------------                 |  \--*  ADDR      byref
               [000029] -------N----                 |     \--*  LCL_VAR   struct<S, 20> V00 loc0
               [000032] ------------                 \--*  CNS_INT   int    10

impImportBlockPending for BB02

impImportBlockPending for BB03

Importing BB03 (PC=059) of 'Runtime_49101:Main():int'
    [ 0]  59 (0x03b) ldloc.0
    [ 1]  60 (0x03c) ldfld 04000001
    [ 1]  65 (0x041) ldloc.0
    [ 2]  66 (0x042) ldfld 04000002
    [ 2]  71 (0x047) add
    [ 1]  72 (0x048) ldloc.0
    [ 2]  73 (0x049) ldfld 04000003
    [ 2]  78 (0x04e) add
    [ 1]  79 (0x04f) ret

STMT00007 (IL 0x03B...  ???)
               [000046] ------------              *  RETURN    int
               [000045] ------------              \--*  ADD       int
               [000041] ------------                 +--*  ADD       int
               [000037] ------------                 |  +--*  FIELD     int    i1
               [000036] ------------                 |  |  \--*  ADDR      byref
               [000035] -------N----                 |  |     \--*  LCL_VAR   struct<S, 20> V00 loc0
               [000040] ------------                 |  \--*  FIELD     int    i2
               [000039] ------------                 |     \--*  ADDR      byref
               [000038] -------N----                 |        \--*  LCL_VAR   struct<S, 20> V00 loc0
               [000044] ------------                 \--*  FIELD     int    i3
               [000043] ------------                    \--*  ADDR      byref
               [000042] -------N----                       \--*  LCL_VAR   struct<S, 20> V00 loc0

Importing BB02 (PC=056) of 'Runtime_49101:Main():int'
    [ 0]  56 (0x038) ldc.i4.s 10
    [ 1]  58 (0x03a) ret

STMT00008 (IL 0x038...  ???)
               [000048] ------------              *  RETURN    int
               [000047] ------------              \--*  CNS_INT   int    10

*************** Finishing PHASE Importation
Trees after Importation

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd                 weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..038)-> BB03 ( cond )                     i
BB02 [0001]  1                             1       [038..03B)        (return)                     i
BB03 [0002]  1                             1       [03B..050)        (return)                     i
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..038) -> BB03 (cond), preds={} succs={BB02,BB03}

***** BB01
STMT00000 (IL 0x000...0x003)
               [000004] -A----------              *  ASG       int
               [000003] -------N----              +--*  FIELD     int    i1
               [000001] ------------              |  \--*  ADDR      byref
               [000000] -------N----              |     \--*  LCL_VAR   struct<S, 20> V00 loc0
               [000002] ------------              \--*  CNS_INT   int    1

***** BB01
STMT00001 (IL 0x008...0x00B)
               [000009] -A----------              *  ASG       int
               [000008] -------N----              +--*  FIELD     int    i2
               [000006] ------------              |  \--*  ADDR      byref
               [000005] -------N----              |     \--*  LCL_VAR   struct<S, 20> V00 loc0
               [000007] ------------              \--*  CNS_INT   int    2

***** BB01
STMT00002 (IL 0x010...0x013)
               [000014] -A----------              *  ASG       int
               [000013] -------N----              +--*  FIELD     int    i3
               [000011] ------------              |  \--*  ADDR      byref
               [000010] -------N----              |     \--*  LCL_VAR   struct<S, 20> V00 loc0
               [000012] ------------              \--*  CNS_INT   int    3

***** BB01
STMT00003 (IL 0x018...0x01B)
               [000019] -A----------              *  ASG       int
               [000018] -------N----              +--*  FIELD     int    i4
               [000016] ------------              |  \--*  ADDR      byref
               [000015] -------N----              |     \--*  LCL_VAR   struct<S, 20> V00 loc0
               [000017] ------------              \--*  CNS_INT   int    4

***** BB01
STMT00004 (IL 0x020...0x023)
               [000024] -A----------              *  ASG       int
               [000023] -------N----              +--*  FIELD     int    i5
               [000021] ------------              |  \--*  ADDR      byref
               [000020] -------N----              |     \--*  LCL_VAR   struct<S, 20> V00 loc0
               [000022] ------------              \--*  CNS_INT   int    5

***** BB01
STMT00005 (IL 0x028...0x036)
               [000026] --C-G-------              *  CALL      void   Runtime_49101.Test
               [000028] n----------- arg0         \--*  OBJ       struct<S, 20>
               [000027] ------------                 \--*  ADDR      byref
               [000025] -------N----                    \--*  LCL_VAR   struct<S, 20> V00 loc0

***** BB01
STMT00006 (IL 0x02E...  ???)
               [000034] ------------              *  JTRUE     void
               [000033] N--------U--              \--*  NE        int
               [000031] ------------                 +--*  FIELD     int    i3
               [000030] ------------                 |  \--*  ADDR      byref
               [000029] -------N----                 |     \--*  LCL_VAR   struct<S, 20> V00 loc0
               [000032] ------------                 \--*  CNS_INT   int    10

------------ BB02 [038..03B) (return), preds={} succs={}

***** BB02
STMT00008 (IL 0x038...0x03A)
               [000048] ------------              *  RETURN    int
               [000047] ------------              \--*  CNS_INT   int    10

------------ BB03 [03B..050) (return), preds={} succs={}

***** BB03
STMT00007 (IL 0x03B...0x04F)
               [000046] ------------              *  RETURN    int
               [000045] ------------              \--*  ADD       int
               [000041] ------------                 +--*  ADD       int
               [000037] ------------                 |  +--*  FIELD     int    i1
               [000036] ------------                 |  |  \--*  ADDR      byref
               [000035] -------N----                 |  |     \--*  LCL_VAR   struct<S, 20> V00 loc0
               [000040] ------------                 |  \--*  FIELD     int    i2
               [000039] ------------                 |     \--*  ADDR      byref
               [000038] -------N----                 |        \--*  LCL_VAR   struct<S, 20> V00 loc0
               [000044] ------------                 \--*  FIELD     int    i3
               [000043] ------------                    \--*  ADDR      byref
               [000042] -------N----                       \--*  LCL_VAR   struct<S, 20> V00 loc0

-------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Indirect call transform

 -- no candidates to transform

*************** Finishing PHASE Indirect call transform [no changes]

*************** Starting PHASE Expand patchpoints

 -- no patchpoints to transform

*************** Finishing PHASE Expand patchpoints [no changes]

*************** Starting PHASE Post-import

*************** Finishing PHASE Post-import

*************** Starting PHASE Morph - Init

New BlockSet epoch 1, # of blocks (including unused BB00): 4, bitset array size: 1 (short)

*************** In fgRemoveEmptyBlocks

*************** Finishing PHASE Morph - Init
*************** In fgDebugCheckBBlist

*************** Starting PHASE Morph - Inlining
**************** Inline Tree
Inlines into 06000002 [via DefaultPolicy] Runtime_49101:Main():int
  [0 IL=0041 TR=000026 06000001] [FAILED: noinline per IL/cached result] Runtime_49101:Test(S)
Budget: initialTime=300, finalTime=300, initialBudget=3000, currentBudget=3000
Budget: initialSize=1955, finalSize=1955

*************** Finishing PHASE Morph - Inlining [no changes]

*************** Starting PHASE Allocate Objects
no newobjs in this method; punting

*************** Finishing PHASE Allocate Objects [no changes]

*************** Starting PHASE Morph - Add internal blocks

*************** After fgAddInternal()

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd                 weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..038)-> BB03 ( cond )                     i
BB02 [0001]  1                             1       [038..03B)        (return)                     i
BB03 [0002]  1                             1       [03B..050)        (return)                     i
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty

*************** Finishing PHASE Morph - Add internal blocks

*************** Starting PHASE Remove empty try

*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.

*************** Finishing PHASE Remove empty try [no changes]

*************** Starting PHASE Remove empty finally
No EH in this method, nothing to remove.

*************** Finishing PHASE Remove empty finally [no changes]

*************** Starting PHASE Merge callfinally chains
No EH in this method, nothing to merge.

*************** Finishing PHASE Merge callfinally chains [no changes]

*************** Starting PHASE Clone finally
No EH in this method, no cloning.

*************** Finishing PHASE Clone finally [no changes]

*************** Starting PHASE Compute preds

Renumbering the basic blocks for fgComputePred

*************** Before renumbering the basic blocks

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd                 weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..038)-> BB03 ( cond )                     i
BB02 [0001]  1                             1       [038..03B)        (return)                     i
BB03 [0002]  1                             1       [03B..050)        (return)                     i
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty

*************** After renumbering the basic blocks
=============== No blocks renumbered!

*************** In fgComputePreds()

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd                 weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..038)-> BB03 ( cond )                     i
BB02 [0001]  1                             1       [038..03B)        (return)                     i
BB03 [0002]  1                             1       [03B..050)        (return)                     i
-----------------------------------------------------------------------------------------------------------------------------------------


*************** After fgComputePreds()

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..038)-> BB03 ( cond )                     i label target
BB02 [0001]  1       BB01                  1       [038..03B)        (return)                     i
BB03 [0002]  1       BB01                  1       [03B..050)        (return)                     i label target
-----------------------------------------------------------------------------------------------------------------------------------------


*************** Finishing PHASE Compute preds

*************** Starting PHASE Merge throw blocks

*************** In fgTailMergeThrows
Method does not have multiple noreturn calls.

*************** Finishing PHASE Merge throw blocks [no changes]

*************** Starting PHASE Update flow graph early pass

*************** In fgUpdateFlowGraph()
Before updating the flow graph:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..038)-> BB03 ( cond )                     i label target
BB02 [0001]  1       BB01                  1       [038..03B)        (return)                     i
BB03 [0002]  1       BB01                  1       [03B..050)        (return)                     i label target
-----------------------------------------------------------------------------------------------------------------------------------------

*************** In fgDebugCheckBBlist

*************** Finishing PHASE Update flow graph early pass

*************** Starting PHASE Morph - Promote Structs

*************** In fgResetImplicitByRefRefCount()
*************** In fgPromoteStructs()

lvaTable before fgPromoteStructs
; Initial local variable assignments
;
;  V00 loc0           struct <S, 20> ld-addr-op
;  V01 OutArgs        lclBlk <na>  "OutgoingArgSpace"

lvaTable after fgPromoteStructs
; Initial local variable assignments
;
;  V00 loc0           struct <S, 20> ld-addr-op
;  V01 OutArgs        lclBlk <na>  "OutgoingArgSpace"

*************** Finishing PHASE Morph - Promote Structs

*************** Starting PHASE Morph - Structs/AddrExp

*************** In fgMarkAddressExposedLocals()
LocalAddressVisitor visiting statement:
STMT00000 (IL 0x000...0x003)
               [000004] -A----------              *  ASG       int
               [000003] -------N----              +--*  FIELD     int    i1
               [000001] ------------              |  \--*  ADDR      byref
               [000000] -------N----              |     \--*  LCL_VAR   struct<S, 20> V00 loc0
               [000002] ------------              \--*  CNS_INT   int    1

Local V00 should not be enregistered because: was accessed as a local field
LocalAddressVisitor modified statement:
STMT00000 (IL 0x000...0x003)
               [000004] -A----------              *  ASG       int
               [000003] U------N----              +--*  LCL_FLD   int    V00 loc0         [+0] Fseq[i1]
               [000002] ------------              \--*  CNS_INT   int    1

LocalAddressVisitor visiting statement:
STMT00001 (IL 0x008...0x00B)
               [000009] -A----------              *  ASG       int
               [000008] -------N----              +--*  FIELD     int    i2
               [000006] ------------              |  \--*  ADDR      byref
               [000005] -------N----              |     \--*  LCL_VAR   struct<S, 20> V00 loc0
               [000007] ------------              \--*  CNS_INT   int    2

Local V00 should not be enregistered because: was accessed as a local field
LocalAddressVisitor modified statement:
STMT00001 (IL 0x008...0x00B)
               [000009] -A----------              *  ASG       int
               [000008] U------N----              +--*  LCL_FLD   int    V00 loc0         [+4] Fseq[i2]
               [000007] ------------              \--*  CNS_INT   int    2

LocalAddressVisitor visiting statement:
STMT00002 (IL 0x010...0x013)
               [000014] -A----------              *  ASG       int
               [000013] -------N----              +--*  FIELD     int    i3
               [000011] ------------              |  \--*  ADDR      byref
               [000010] -------N----              |     \--*  LCL_VAR   struct<S, 20> V00 loc0
               [000012] ------------              \--*  CNS_INT   int    3

Local V00 should not be enregistered because: was accessed as a local field
LocalAddressVisitor modified statement:
STMT00002 (IL 0x010...0x013)
               [000014] -A----------              *  ASG       int
               [000013] U------N----              +--*  LCL_FLD   int    V00 loc0         [+8] Fseq[i3]
               [000012] ------------              \--*  CNS_INT   int    3

LocalAddressVisitor visiting statement:
STMT00003 (IL 0x018...0x01B)
               [000019] -A----------              *  ASG       int
               [000018] -------N----              +--*  FIELD     int    i4
               [000016] ------------              |  \--*  ADDR      byref
               [000015] -------N----              |     \--*  LCL_VAR   struct<S, 20> V00 loc0
               [000017] ------------              \--*  CNS_INT   int    4

Local V00 should not be enregistered because: was accessed as a local field
LocalAddressVisitor modified statement:
STMT00003 (IL 0x018...0x01B)
               [000019] -A----------              *  ASG       int
               [000018] U------N----              +--*  LCL_FLD   int    V00 loc0         [+12] Fseq[i4]
               [000017] ------------              \--*  CNS_INT   int    4

LocalAddressVisitor visiting statement:
STMT00004 (IL 0x020...0x023)
               [000024] -A----------              *  ASG       int
               [000023] -------N----              +--*  FIELD     int    i5
               [000021] ------------              |  \--*  ADDR      byref
               [000020] -------N----              |     \--*  LCL_VAR   struct<S, 20> V00 loc0
               [000022] ------------              \--*  CNS_INT   int    5

Local V00 should not be enregistered because: was accessed as a local field
LocalAddressVisitor modified statement:
STMT00004 (IL 0x020...0x023)
               [000024] -A----------              *  ASG       int
               [000023] U------N----              +--*  LCL_FLD   int    V00 loc0         [+16] Fseq[i5]
               [000022] ------------              \--*  CNS_INT   int    5

LocalAddressVisitor visiting statement:
STMT00005 (IL 0x028...0x036)
               [000026] --C-G-------              *  CALL      void   Runtime_49101.Test
               [000028] n----------- arg0         \--*  OBJ       struct<S, 20>
               [000027] ------------                 \--*  ADDR      byref
               [000025] -------N----                    \--*  LCL_VAR   struct<S, 20> V00 loc0

LocalAddressVisitor visiting statement:
STMT00006 (IL 0x02E...  ???)
               [000034] ------------              *  JTRUE     void
               [000033] N--------U--              \--*  NE        int
               [000031] ------------                 +--*  FIELD     int    i3
               [000030] ------------                 |  \--*  ADDR      byref
               [000029] -------N----                 |     \--*  LCL_VAR   struct<S, 20> V00 loc0
               [000032] ------------                 \--*  CNS_INT   int    10

Local V00 should not be enregistered because: was accessed as a local field
LocalAddressVisitor modified statement:
STMT00006 (IL 0x02E...  ???)
               [000034] ------------              *  JTRUE     void
               [000033] N--------U--              \--*  NE        int
               [000031] ------------                 +--*  LCL_FLD   int    V00 loc0         [+8] Fseq[i3]
               [000032] ------------                 \--*  CNS_INT   int    10

LocalAddressVisitor visiting statement:
STMT00008 (IL 0x038...0x03A)
               [000048] ------------              *  RETURN    int
               [000047] ------------              \--*  CNS_INT   int    10

LocalAddressVisitor visiting statement:
STMT00007 (IL 0x03B...0x04F)
               [000046] ------------              *  RETURN    int
               [000045] ------------              \--*  ADD       int
               [000041] ------------                 +--*  ADD       int
               [000037] ------------                 |  +--*  FIELD     int    i1
               [000036] ------------                 |  |  \--*  ADDR      byref
               [000035] -------N----                 |  |     \--*  LCL_VAR   struct<S, 20> V00 loc0
               [000040] ------------                 |  \--*  FIELD     int    i2
               [000039] ------------                 |     \--*  ADDR      byref
               [000038] -------N----                 |        \--*  LCL_VAR   struct<S, 20> V00 loc0
               [000044] ------------                 \--*  FIELD     int    i3
               [000043] ------------                    \--*  ADDR      byref
               [000042] -------N----                       \--*  LCL_VAR   struct<S, 20> V00 loc0

Local V00 should not be enregistered because: was accessed as a local field

Local V00 should not be enregistered because: was accessed as a local field

Local V00 should not be enregistered because: was accessed as a local field
LocalAddressVisitor modified statement:
STMT00007 (IL 0x03B...0x04F)
               [000046] ------------              *  RETURN    int
               [000045] ------------              \--*  ADD       int
               [000041] ------------                 +--*  ADD       int
               [000037] ------------                 |  +--*  LCL_FLD   int    V00 loc0         [+0] Fseq[i1]
               [000040] ------------                 |  \--*  LCL_FLD   int    V00 loc0         [+4] Fseq[i2]
               [000044] ------------                 \--*  LCL_FLD   int    V00 loc0         [+8] Fseq[i3]


*************** Finishing PHASE Morph - Structs/AddrExp

*************** Starting PHASE Morph - ByRefs

*************** In fgRetypeImplicitByRefArgs()

*************** Finishing PHASE Morph - ByRefs

*************** Starting PHASE Morph - Global

*************** In fgMorphBlocks()

Morphing BB01 of 'Runtime_49101:Main():int'

fgMorphTree BB01, STMT00000 (before)
               [000004] -A----------              *  ASG       int
               [000003] U------N----              +--*  LCL_FLD   int    V00 loc0         [+0] Fseq[i1]
               [000002] ------------              \--*  CNS_INT   int    1

fgMorphTree BB01, STMT00001 (before)
               [000009] -A----------              *  ASG       int
               [000008] U------N----              +--*  LCL_FLD   int    V00 loc0         [+4] Fseq[i2]
               [000007] ------------              \--*  CNS_INT   int    2

fgMorphTree BB01, STMT00002 (before)
               [000014] -A----------              *  ASG       int
               [000013] U------N----              +--*  LCL_FLD   int    V00 loc0         [+8] Fseq[i3]
               [000012] ------------              \--*  CNS_INT   int    3

fgMorphTree BB01, STMT00003 (before)
               [000019] -A----------              *  ASG       int
               [000018] U------N----              +--*  LCL_FLD   int    V00 loc0         [+12] Fseq[i4]
               [000017] ------------              \--*  CNS_INT   int    4

fgMorphTree BB01, STMT00004 (before)
               [000024] -A----------              *  ASG       int
               [000023] U------N----              +--*  LCL_FLD   int    V00 loc0         [+16] Fseq[i5]
               [000022] ------------              \--*  CNS_INT   int    5

fgMorphTree BB01, STMT00005 (before)
               [000026] --C-G-------              *  CALL      void   Runtime_49101.Test
               [000028] n----------- arg0         \--*  OBJ       struct<S, 20>
               [000027] ------------                 \--*  ADDR      byref
               [000025] -------N----                    \--*  LCL_VAR   struct<S, 20> V00 loc0
Initializing arg info for 26.CALL:
ArgTable for 26.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 28.OBJ struct (By ref), 1 reg: rcx, byteAlignment=8, isStruct]

Morphing args for 26.CALL:
making an outgoing copy for struct arg

lvaGrabTemp returning 2 (V02 tmp1) called for by-value struct argument.
fgMorphCopyBlock:
fgMorphBlkNode for dst tree, before:
               [000049] D------N----              *  LCL_VAR   struct<S, 20> V02 tmp1
fgMorphBlkNode after:
               [000049] D------N----              *  LCL_VAR   struct<S, 20> V02 tmp1
fgMorphBlkNode for src tree, before:
               [000025] -----+-N----              *  LCL_VAR   struct<S, 20> V00 loc0
fgMorphBlkNode after:
               [000025] -----+-N----              *  LCL_VAR   struct<S, 20> V00 loc0
block assignment to morph:
               [000050] -A----------              *  ASG       struct (copy)
               [000049] D------N----              +--*  LCL_VAR   struct<S, 20> V02 tmp1
               [000025] -----+-N----              \--*  LCL_VAR   struct<S, 20> V00 loc0
 with no promoted structs this requires a CopyBlock.

Local V02 should not be enregistered because: written in a block op

Local V00 should not be enregistered because: written in a block op

fgMorphCopyBlock (after):
               [000050] -A----------              *  ASG       struct (copy)
               [000049] D------N----              +--*  LCL_VAR   struct<S, 20> V02 tmp1
               [000025] -----+-N----              \--*  LCL_VAR   struct<S, 20> V00 loc0
argSlots=1, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32

Sorting the arguments:

Local V02 should not be enregistered because: it is address exposed

Shuffled argument table:    rcx
ArgTable for 26.CALL after fgMorphArgs:
fgArgTabEntry[arg 0 52.ADDR struct (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, tmpNum=V02, isTmp, processed, isStruct]


fgMorphTree BB01, STMT00005 (after)
               [000026] -ACXG+------              *  CALL      void   Runtime_49101.Test
               [000050] -A--------L- arg0 SETUP   +--*  ASG       struct (copy)
               [000049] D------N----              |  +--*  LCL_VAR   struct<S, 20>(AX) V02 tmp1
               [000025] -----+-N----              |  \--*  LCL_VAR   struct<S, 20> V00 loc0
               [000052] ------------ arg0 in rcx  \--*  ADDR      byref
               [000051] -------N----                 \--*  LCL_VAR   struct<S, 20>(AX) V02 tmp1

fgMorphTree BB01, STMT00006 (before)
               [000034] ------------              *  JTRUE     void
               [000033] N--------U--              \--*  NE        int
               [000031] ------------                 +--*  LCL_FLD   int    V00 loc0         [+8] Fseq[i3]
               [000032] ------------                 \--*  CNS_INT   int    10

Morphing BB02 of 'Runtime_49101:Main():int'

fgMorphTree BB02, STMT00008 (before)
               [000048] ------------              *  RETURN    int
               [000047] ------------              \--*  CNS_INT   int    10

Morphing BB03 of 'Runtime_49101:Main():int'

fgMorphTree BB03, STMT00007 (before)
               [000046] ------------              *  RETURN    int
               [000045] ------------              \--*  ADD       int
               [000041] ------------                 +--*  ADD       int
               [000037] ------------                 |  +--*  LCL_FLD   int    V00 loc0         [+0] Fseq[i1]
               [000040] ------------                 |  \--*  LCL_FLD   int    V00 loc0         [+4] Fseq[i2]
               [000044] ------------                 \--*  LCL_FLD   int    V00 loc0         [+8] Fseq[i3]

*************** Finishing PHASE Morph - Global
Trees after Morph - Global

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..038)-> BB03 ( cond )                     i label target hascall gcsafe
BB02 [0001]  1       BB01                  1       [038..03B)        (return)                     i
BB03 [0002]  1       BB01                  1       [03B..050)        (return)                     i label target
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..038) -> BB03 (cond), preds={} succs={BB02,BB03}

***** BB01
STMT00000 (IL 0x000...0x003)
               [000004] -A---+------              *  ASG       int
               [000003] U----+-N----              +--*  LCL_FLD   int    V00 loc0         [+0] Fseq[i1]
               [000002] -----+------              \--*  CNS_INT   int    1

***** BB01
STMT00001 (IL 0x008...0x00B)
               [000009] -A---+------              *  ASG       int
               [000008] U----+-N----              +--*  LCL_FLD   int    V00 loc0         [+4] Fseq[i2]
               [000007] -----+------              \--*  CNS_INT   int    2

***** BB01
STMT00002 (IL 0x010...0x013)
               [000014] -A---+------              *  ASG       int
               [000013] U----+-N----              +--*  LCL_FLD   int    V00 loc0         [+8] Fseq[i3]
               [000012] -----+------              \--*  CNS_INT   int    3

***** BB01
STMT00003 (IL 0x018...0x01B)
               [000019] -A---+------              *  ASG       int
               [000018] U----+-N----              +--*  LCL_FLD   int    V00 loc0         [+12] Fseq[i4]
               [000017] -----+------              \--*  CNS_INT   int    4

***** BB01
STMT00004 (IL 0x020...0x023)
               [000024] -A---+------              *  ASG       int
               [000023] U----+-N----              +--*  LCL_FLD   int    V00 loc0         [+16] Fseq[i5]
               [000022] -----+------              \--*  CNS_INT   int    5

***** BB01
STMT00005 (IL 0x028...0x036)
               [000026] -ACXG+------              *  CALL      void   Runtime_49101.Test
               [000050] -A--------L- arg0 SETUP   +--*  ASG       struct (copy)
               [000049] D------N----              |  +--*  LCL_VAR   struct<S, 20>(AX) V02 tmp1
               [000025] -----+-N----              |  \--*  LCL_VAR   struct<S, 20> V00 loc0
               [000052] ------------ arg0 in rcx  \--*  ADDR      byref
               [000051] -------N----                 \--*  LCL_VAR   struct<S, 20>(AX) V02 tmp1

***** BB01
STMT00006 (IL 0x02E...  ???)
               [000034] -----+------              *  JTRUE     void
               [000033] N----+-N-U--              \--*  NE        int
               [000031] -----+------                 +--*  LCL_FLD   int    V00 loc0         [+8] Fseq[i3]
               [000032] -----+------                 \--*  CNS_INT   int    10

------------ BB02 [038..03B) (return), preds={BB01} succs={}

***** BB02
STMT00008 (IL 0x038...0x03A)
               [000048] -----+------              *  RETURN    int
               [000047] -----+------              \--*  CNS_INT   int    10

------------ BB03 [03B..050) (return), preds={BB01} succs={}

***** BB03
STMT00007 (IL 0x03B...0x04F)
               [000046] -----+------              *  RETURN    int
               [000045] -----+------              \--*  ADD       int
               [000041] -----+------                 +--*  ADD       int
               [000037] -----+------                 |  +--*  LCL_FLD   int    V00 loc0         [+0] Fseq[i1]
               [000040] -----+------                 |  \--*  LCL_FLD   int    V00 loc0         [+4] Fseq[i2]
               [000044] -----+------                 \--*  LCL_FLD   int    V00 loc0         [+8] Fseq[i3]

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist

*************** Starting PHASE GS Cookie
No GS security needed

*************** Finishing PHASE GS Cookie

*************** Starting PHASE Compute edge weights (1, false)
*************** In fgComputeBlockAndEdgeWeights()

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..038)-> BB03 ( cond )                     i label target hascall gcsafe
BB02 [0001]  1       BB01                  1       [038..03B)        (return)                     i
BB03 [0002]  1       BB01                  1       [03B..050)        (return)                     i label target
-----------------------------------------------------------------------------------------------------------------------------------------

 -- no profile data, so using default called count
 -- not optimizing or no profile data, so not computing edge weights

*************** Finishing PHASE Compute edge weights (1, false)

*************** Starting PHASE Create EH funclets
*************** In fgCreateFunclets()

After fgCreateFunclets()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..038)-> BB03 ( cond )                     i label target hascall gcsafe
BB02 [0001]  1       BB01                  1       [038..03B)        (return)                     i
BB03 [0002]  1       BB01                  1       [03B..050)        (return)                     i label target
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty
*************** In fgDebugCheckBBlist

*************** Finishing PHASE Create EH funclets

*************** Starting PHASE Invert loops

*************** Finishing PHASE Invert loops
Trees after Invert loops

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..038)-> BB03 ( cond )                     i label target hascall gcsafe
BB02 [0001]  1       BB01                  1       [038..03B)        (return)                     i
BB03 [0002]  1       BB01                  1       [03B..050)        (return)                     i label target
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..038) -> BB03 (cond), preds={} succs={BB02,BB03}

***** BB01
STMT00000 (IL 0x000...0x003)
               [000004] -A---+------              *  ASG       int
               [000003] U----+-N----              +--*  LCL_FLD   int    V00 loc0         [+0] Fseq[i1]
               [000002] -----+------              \--*  CNS_INT   int    1

***** BB01
STMT00001 (IL 0x008...0x00B)
               [000009] -A---+------              *  ASG       int
               [000008] U----+-N----              +--*  LCL_FLD   int    V00 loc0         [+4] Fseq[i2]
               [000007] -----+------              \--*  CNS_INT   int    2

***** BB01
STMT00002 (IL 0x010...0x013)
               [000014] -A---+------              *  ASG       int
               [000013] U----+-N----              +--*  LCL_FLD   int    V00 loc0         [+8] Fseq[i3]
               [000012] -----+------              \--*  CNS_INT   int    3

***** BB01
STMT00003 (IL 0x018...0x01B)
               [000019] -A---+------              *  ASG       int
               [000018] U----+-N----              +--*  LCL_FLD   int    V00 loc0         [+12] Fseq[i4]
               [000017] -----+------              \--*  CNS_INT   int    4

***** BB01
STMT00004 (IL 0x020...0x023)
               [000024] -A---+------              *  ASG       int
               [000023] U----+-N----              +--*  LCL_FLD   int    V00 loc0         [+16] Fseq[i5]
               [000022] -----+------              \--*  CNS_INT   int    5

***** BB01
STMT00005 (IL 0x028...0x036)
               [000026] -ACXG+------              *  CALL      void   Runtime_49101.Test
               [000050] -A--------L- arg0 SETUP   +--*  ASG       struct (copy)
               [000049] D------N----              |  +--*  LCL_VAR   struct<S, 20>(AX) V02 tmp1
               [000025] -----+-N----              |  \--*  LCL_VAR   struct<S, 20> V00 loc0
               [000052] ------------ arg0 in rcx  \--*  ADDR      byref
               [000051] -------N----                 \--*  LCL_VAR   struct<S, 20>(AX) V02 tmp1

***** BB01
STMT00006 (IL 0x02E...  ???)
               [000034] -----+------              *  JTRUE     void
               [000033] N----+-N-U--              \--*  NE        int
               [000031] -----+------                 +--*  LCL_FLD   int    V00 loc0         [+8] Fseq[i3]
               [000032] -----+------                 \--*  CNS_INT   int    10

------------ BB02 [038..03B) (return), preds={BB01} succs={}

***** BB02
STMT00008 (IL 0x038...0x03A)
               [000048] -----+------              *  RETURN    int
               [000047] -----+------              \--*  CNS_INT   int    10

------------ BB03 [03B..050) (return), preds={BB01} succs={}

***** BB03
STMT00007 (IL 0x03B...0x04F)
               [000046] -----+------              *  RETURN    int
               [000045] -----+------              \--*  ADD       int
               [000041] -----+------                 +--*  ADD       int
               [000037] -----+------                 |  +--*  LCL_FLD   int    V00 loc0         [+0] Fseq[i1]
               [000040] -----+------                 |  \--*  LCL_FLD   int    V00 loc0         [+4] Fseq[i2]
               [000044] -----+------                 \--*  LCL_FLD   int    V00 loc0         [+8] Fseq[i3]

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist

*************** Starting PHASE Optimize layout

*************** In fgUpdateFlowGraph()
Before updating the flow graph:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..038)-> BB03 ( cond )                     i label target hascall gcsafe
BB02 [0001]  1       BB01                  1       [038..03B)        (return)                     i
BB03 [0002]  1       BB01                  1       [03B..050)        (return)                     i label target
-----------------------------------------------------------------------------------------------------------------------------------------

*************** In fgDebugCheckBBlist

*************** In fgExpandRarelyRunBlocks()
*************** In fgReorderBlocks()

Initial BasicBlocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..038)-> BB03 ( cond )                     i label target hascall gcsafe
BB02 [0001]  1       BB01                  1       [038..03B)        (return)                     i
BB03 [0002]  1       BB01                  1       [03B..050)        (return)                     i label target
-----------------------------------------------------------------------------------------------------------------------------------------


*************** In fgUpdateFlowGraph()
Before updating the flow graph:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..038)-> BB03 ( cond )                     i label target hascall gcsafe
BB02 [0001]  1       BB01                  1       [038..03B)        (return)                     i
BB03 [0002]  1       BB01                  1       [03B..050)        (return)                     i label target
-----------------------------------------------------------------------------------------------------------------------------------------

*************** In fgDebugCheckBBlist

*************** Finishing PHASE Optimize layout
Trees after Optimize layout

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..038)-> BB03 ( cond )                     i label target hascall gcsafe
BB02 [0001]  1       BB01                  1       [038..03B)        (return)                     i
BB03 [0002]  1       BB01                  1       [03B..050)        (return)                     i label target
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..038) -> BB03 (cond), preds={} succs={BB02,BB03}

***** BB01
STMT00000 (IL 0x000...0x003)
               [000004] -A---+------              *  ASG       int
               [000003] U----+-N----              +--*  LCL_FLD   int    V00 loc0         [+0] Fseq[i1]
               [000002] -----+------              \--*  CNS_INT   int    1

***** BB01
STMT00001 (IL 0x008...0x00B)
               [000009] -A---+------              *  ASG       int
               [000008] U----+-N----              +--*  LCL_FLD   int    V00 loc0         [+4] Fseq[i2]
               [000007] -----+------              \--*  CNS_INT   int    2

***** BB01
STMT00002 (IL 0x010...0x013)
               [000014] -A---+------              *  ASG       int
               [000013] U----+-N----              +--*  LCL_FLD   int    V00 loc0         [+8] Fseq[i3]
               [000012] -----+------              \--*  CNS_INT   int    3

***** BB01
STMT00003 (IL 0x018...0x01B)
               [000019] -A---+------              *  ASG       int
               [000018] U----+-N----              +--*  LCL_FLD   int    V00 loc0         [+12] Fseq[i4]
               [000017] -----+------              \--*  CNS_INT   int    4

***** BB01
STMT00004 (IL 0x020...0x023)
               [000024] -A---+------              *  ASG       int
               [000023] U----+-N----              +--*  LCL_FLD   int    V00 loc0         [+16] Fseq[i5]
               [000022] -----+------              \--*  CNS_INT   int    5

***** BB01
STMT00005 (IL 0x028...0x036)
               [000026] -ACXG+------              *  CALL      void   Runtime_49101.Test
               [000050] -A--------L- arg0 SETUP   +--*  ASG       struct (copy)
               [000049] D------N----              |  +--*  LCL_VAR   struct<S, 20>(AX) V02 tmp1
               [000025] -----+-N----              |  \--*  LCL_VAR   struct<S, 20> V00 loc0
               [000052] ------------ arg0 in rcx  \--*  ADDR      byref
               [000051] -------N----                 \--*  LCL_VAR   struct<S, 20>(AX) V02 tmp1

***** BB01
STMT00006 (IL 0x02E...  ???)
               [000034] -----+------              *  JTRUE     void
               [000033] N----+-N-U--              \--*  NE        int
               [000031] -----+------                 +--*  LCL_FLD   int    V00 loc0         [+8] Fseq[i3]
               [000032] -----+------                 \--*  CNS_INT   int    10

------------ BB02 [038..03B) (return), preds={BB01} succs={}

***** BB02
STMT00008 (IL 0x038...0x03A)
               [000048] -----+------              *  RETURN    int
               [000047] -----+------              \--*  CNS_INT   int    10

------------ BB03 [03B..050) (return), preds={BB01} succs={}

***** BB03
STMT00007 (IL 0x03B...0x04F)
               [000046] -----+------              *  RETURN    int
               [000045] -----+------              \--*  ADD       int
               [000041] -----+------                 +--*  ADD       int
               [000037] -----+------                 |  +--*  LCL_FLD   int    V00 loc0         [+0] Fseq[i1]
               [000040] -----+------                 |  \--*  LCL_FLD   int    V00 loc0         [+4] Fseq[i2]
               [000044] -----+------                 \--*  LCL_FLD   int    V00 loc0         [+8] Fseq[i3]

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist

*************** Starting PHASE Compute blocks reachability
*************** In fgComputeReachability
*************** In fgDebugCheckBBlist

Renumbering the basic blocks for fgComputeReachability pass #1

*************** Before renumbering the basic blocks

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..038)-> BB03 ( cond )                     i label target hascall gcsafe
BB02 [0001]  1       BB01                  1       [038..03B)        (return)                     i
BB03 [0002]  1       BB01                  1       [03B..050)        (return)                     i label target
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty

*************** After renumbering the basic blocks
=============== No blocks renumbered!
Enter blocks: BB01

After computing reachability sets:
------------------------------------------------
BBnum  Reachable by
------------------------------------------------
BB01 : BB01
BB02 : BB01 BB02
BB03 : BB01 BB03

After computing reachability:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..038)-> BB03 ( cond )                     i label target hascall gcsafe
BB02 [0001]  1       BB01                  1       [038..03B)        (return)                     i gcsafe
BB03 [0002]  1       BB01                  1       [03B..050)        (return)                     i label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------

*************** In fgDebugCheckBBlist
*************** In fgComputeDoms
*************** In fgDebugCheckBBlist

Dominator computation start blocks (those blocks with no incoming edges):
BB01
------------------------------------------------
BBnum  Dominated by
------------------------------------------------
BB01:  BB01
BB02:  BB02 BB01
BB03:  BB03 BB01

Inside fgBuildDomTree

After computing the Dominance Tree:
BB01 : BB03 BB02


After numbering the dominator tree:
BB01: pre=01, post=03
BB02: pre=03, post=02
BB03: pre=02, post=01

*************** Finishing PHASE Compute blocks reachability

*************** Starting PHASE Find loops
*************** In optFindLoops()

After optSetBlockWeights:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..038)-> BB03 ( cond )                     i label target hascall gcsafe
BB02 [0001]  1       BB01                  0.50    [038..03B)        (return)                     i gcsafe
BB03 [0002]  1       BB01                  0.50    [03B..050)        (return)                     i label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------

*************** In fgDebugCheckBBlist

*************** Finishing PHASE Find loops
Trees after Find loops

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..038)-> BB03 ( cond )                     i label target hascall gcsafe
BB02 [0001]  1       BB01                  0.50    [038..03B)        (return)                     i gcsafe
BB03 [0002]  1       BB01                  0.50    [03B..050)        (return)                     i label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..038) -> BB03 (cond), preds={} succs={BB02,BB03}

***** BB01
STMT00000 (IL 0x000...0x003)
               [000004] -A---+------              *  ASG       int
               [000003] U----+-N----              +--*  LCL_FLD   int    V00 loc0         [+0] Fseq[i1]
               [000002] -----+------              \--*  CNS_INT   int    1

***** BB01
STMT00001 (IL 0x008...0x00B)
               [000009] -A---+------              *  ASG       int
               [000008] U----+-N----              +--*  LCL_FLD   int    V00 loc0         [+4] Fseq[i2]
               [000007] -----+------              \--*  CNS_INT   int    2

***** BB01
STMT00002 (IL 0x010...0x013)
               [000014] -A---+------              *  ASG       int
               [000013] U----+-N----              +--*  LCL_FLD   int    V00 loc0         [+8] Fseq[i3]
               [000012] -----+------              \--*  CNS_INT   int    3

***** BB01
STMT00003 (IL 0x018...0x01B)
               [000019] -A---+------              *  ASG       int
               [000018] U----+-N----              +--*  LCL_FLD   int    V00 loc0         [+12] Fseq[i4]
               [000017] -----+------              \--*  CNS_INT   int    4

***** BB01
STMT00004 (IL 0x020...0x023)
               [000024] -A---+------              *  ASG       int
               [000023] U----+-N----              +--*  LCL_FLD   int    V00 loc0         [+16] Fseq[i5]
               [000022] -----+------              \--*  CNS_INT   int    5

***** BB01
STMT00005 (IL 0x028...0x036)
               [000026] -ACXG+------              *  CALL      void   Runtime_49101.Test
               [000050] -A--------L- arg0 SETUP   +--*  ASG       struct (copy)
               [000049] D------N----              |  +--*  LCL_VAR   struct<S, 20>(AX) V02 tmp1
               [000025] -----+-N----              |  \--*  LCL_VAR   struct<S, 20> V00 loc0
               [000052] ------------ arg0 in rcx  \--*  ADDR      byref
               [000051] -------N----                 \--*  LCL_VAR   struct<S, 20>(AX) V02 tmp1

***** BB01
STMT00006 (IL 0x02E...  ???)
               [000034] -----+------              *  JTRUE     void
               [000033] N----+-N-U--              \--*  NE        int
               [000031] -----+------                 +--*  LCL_FLD   int    V00 loc0         [+8] Fseq[i3]
               [000032] -----+------                 \--*  CNS_INT   int    10

------------ BB02 [038..03B) (return), preds={BB01} succs={}

***** BB02
STMT00008 (IL 0x038...0x03A)
               [000048] -----+------              *  RETURN    int
               [000047] -----+------              \--*  CNS_INT   int    10

------------ BB03 [03B..050) (return), preds={BB01} succs={}

***** BB03
STMT00007 (IL 0x03B...0x04F)
               [000046] -----+------              *  RETURN    int
               [000045] -----+------              \--*  ADD       int
               [000041] -----+------                 +--*  ADD       int
               [000037] -----+------                 |  +--*  LCL_FLD   int    V00 loc0         [+0] Fseq[i1]
               [000040] -----+------                 |  \--*  LCL_FLD   int    V00 loc0         [+4] Fseq[i2]
               [000044] -----+------                 \--*  LCL_FLD   int    V00 loc0         [+8] Fseq[i3]

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist

*************** Starting PHASE Clone loops

*************** In optCloneLoops()

*************** Finishing PHASE Clone loops

*************** Starting PHASE Unroll loops

*************** Finishing PHASE Unroll loops

*************** Starting PHASE Mark local vars

*************** In lvaMarkLocalVars()
*** lvaComputeRefCounts ***

*** lvaComputeRefCounts -- explicit counts ***

*** marking local variables in block BB01 (weight=1   )
STMT00000 (IL 0x000...0x003)
               [000004] -A---+------              *  ASG       int
               [000003] U----+-N----              +--*  LCL_FLD   int    V00 loc0         [+0] Fseq[i1]
               [000002] -----+------              \--*  CNS_INT   int    1
New refCnts for V00: refCnt =  1, refCntWtd = 1
STMT00001 (IL 0x008...0x00B)
               [000009] -A---+------              *  ASG       int
               [000008] U----+-N----              +--*  LCL_FLD   int    V00 loc0         [+4] Fseq[i2]
               [000007] -----+------              \--*  CNS_INT   int    2
New refCnts for V00: refCnt =  2, refCntWtd = 2
STMT00002 (IL 0x010...0x013)
               [000014] -A---+------              *  ASG       int
               [000013] U----+-N----              +--*  LCL_FLD   int    V00 loc0         [+8] Fseq[i3]
               [000012] -----+------              \--*  CNS_INT   int    3
New refCnts for V00: refCnt =  3, refCntWtd = 3
STMT00003 (IL 0x018...0x01B)
               [000019] -A---+------              *  ASG       int
               [000018] U----+-N----              +--*  LCL_FLD   int    V00 loc0         [+12] Fseq[i4]
               [000017] -----+------              \--*  CNS_INT   int    4
New refCnts for V00: refCnt =  4, refCntWtd = 4
STMT00004 (IL 0x020...0x023)
               [000024] -A---+------              *  ASG       int
               [000023] U----+-N----              +--*  LCL_FLD   int    V00 loc0         [+16] Fseq[i5]
               [000022] -----+------              \--*  CNS_INT   int    5
New refCnts for V00: refCnt =  5, refCntWtd = 5
STMT00005 (IL 0x028...0x036)
               [000026] -ACXG+------              *  CALL      void   Runtime_49101.Test
               [000050] -A--------L- arg0 SETUP   +--*  ASG       struct (copy)
               [000049] D------N----              |  +--*  LCL_VAR   struct<S, 20>(AX) V02 tmp1
               [000025] -----+-N----              |  \--*  LCL_VAR   struct<S, 20> V00 loc0
               [000052] ------------ arg0 in rcx  \--*  ADDR      byref
               [000051] -------N----                 \--*  LCL_VAR   struct<S, 20>(AX) V02 tmp1
New refCnts for V02: refCnt =  1, refCntWtd = 2
New refCnts for V00: refCnt =  6, refCntWtd = 6
New refCnts for V02: refCnt =  2, refCntWtd = 4
STMT00006 (IL 0x02E...  ???)
               [000034] -----+------              *  JTRUE     void
               [000033] N----+-N-U--              \--*  NE        int
               [000031] -----+------                 +--*  LCL_FLD   int    V00 loc0         [+8] Fseq[i3]
               [000032] -----+------                 \--*  CNS_INT   int    10
New refCnts for V00: refCnt =  7, refCntWtd = 7

*** marking local variables in block BB02 (weight=0.50)
STMT00008 (IL 0x038...0x03A)
               [000048] -----+------              *  RETURN    int
               [000047] -----+------              \--*  CNS_INT   int    10

*** marking local variables in block BB03 (weight=0.50)
STMT00007 (IL 0x03B...0x04F)
               [000046] -----+------              *  RETURN    int
               [000045] -----+------              \--*  ADD       int
               [000041] -----+------                 +--*  ADD       int
               [000037] -----+------                 |  +--*  LCL_FLD   int    V00 loc0         [+0] Fseq[i1]
               [000040] -----+------                 |  \--*  LCL_FLD   int    V00 loc0         [+4] Fseq[i2]
               [000044] -----+------                 \--*  LCL_FLD   int    V00 loc0         [+8] Fseq[i3]
New refCnts for V00: refCnt =  8, refCntWtd = 7.50
New refCnts for V00: refCnt =  9, refCntWtd = 8
New refCnts for V00: refCnt = 10, refCntWtd = 8.50

*** lvaComputeRefCounts -- implicit counts ***

*************** In optAddCopies()


*************** Finishing PHASE Mark local vars

*************** Starting PHASE Optimize bools
*************** In optOptimizeBools()
*************** In fgDebugCheckBBlist

*************** Finishing PHASE Optimize bools

*************** Starting PHASE Find oper order
*************** In fgFindOperOrder()

*************** Finishing PHASE Find oper order

*************** Starting PHASE Set block order
*************** In fgSetBlockOrder()
The biggest BB has    6 tree nodes

*************** Finishing PHASE Set block order
Trees before Build SSA representation

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..038)-> BB03 ( cond )                     i label target hascall gcsafe
BB02 [0001]  1       BB01                  0.50    [038..03B)        (return)                     i gcsafe
BB03 [0002]  1       BB01                  0.50    [03B..050)        (return)                     i label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..038) -> BB03 (cond), preds={} succs={BB02,BB03}

***** BB01
STMT00000 (IL 0x000...0x003)
N003 (  5,  6) [000004] -A------R---              *  ASG       int
N002 (  3,  4) [000003] U------N----              +--*  LCL_FLD   int    V00 loc0         [+0] Fseq[i1]
N001 (  1,  1) [000002] ------------              \--*  CNS_INT   int    1

***** BB01
STMT00001 (IL 0x008...0x00B)
N003 (  5,  6) [000009] -A------R---              *  ASG       int
N002 (  3,  4) [000008] U------N----              +--*  LCL_FLD   int    V00 loc0         [+4] Fseq[i2]
N001 (  1,  1) [000007] ------------              \--*  CNS_INT   int    2

***** BB01
STMT00002 (IL 0x010...0x013)
N003 (  5,  6) [000014] -A------R---              *  ASG       int
N002 (  3,  4) [000013] U------N----              +--*  LCL_FLD   int    V00 loc0         [+8] Fseq[i3]
N001 (  1,  1) [000012] ------------              \--*  CNS_INT   int    3

***** BB01
STMT00003 (IL 0x018...0x01B)
N003 (  5,  6) [000019] -A------R---              *  ASG       int
N002 (  3,  4) [000018] U------N----              +--*  LCL_FLD   int    V00 loc0         [+12] Fseq[i4]
N001 (  1,  1) [000017] ------------              \--*  CNS_INT   int    4

***** BB01
STMT00004 (IL 0x020...0x023)
N003 (  5,  6) [000024] -A------R---              *  ASG       int
N002 (  3,  4) [000023] U------N----              +--*  LCL_FLD   int    V00 loc0         [+16] Fseq[i5]
N001 (  1,  1) [000022] ------------              \--*  CNS_INT   int    5

***** BB01
STMT00005 (IL 0x028...0x036)
N006 ( 27, 14) [000026] -ACXG-------              *  CALL      void   Runtime_49101.Test
N003 (  7,  5) [000050] -A------R-L- arg0 SETUP   +--*  ASG       struct (copy)
N002 (  3,  2) [000049] D------N----              |  +--*  LCL_VAR   struct<S, 20>(AX) V02 tmp1
N001 (  3,  2) [000025] -------N----              |  \--*  LCL_VAR   struct<S, 20> V00 loc0
N005 (  3,  3) [000052] ------------ arg0 in rcx  \--*  ADDR      byref
N004 (  3,  2) [000051] -------N----                 \--*  LCL_VAR   struct<S, 20>(AX) V02 tmp1

***** BB01
STMT00006 (IL 0x02E...  ???)
N004 (  7,  8) [000034] ------------              *  JTRUE     void
N003 (  5,  6) [000033] N------N-U--              \--*  NE        int
N001 (  3,  4) [000031] ------------                 +--*  LCL_FLD   int    V00 loc0         [+8] Fseq[i3]
N002 (  1,  1) [000032] ------------                 \--*  CNS_INT   int    10

------------ BB02 [038..03B) (return), preds={BB01} succs={}

***** BB02
STMT00008 (IL 0x038...0x03A)
N002 (  2,  2) [000048] ------------              *  RETURN    int
N001 (  1,  1) [000047] ------------              \--*  CNS_INT   int    10

------------ BB03 [03B..050) (return), preds={BB01} succs={}

***** BB03
STMT00007 (IL 0x03B...0x04F)
N006 ( 12, 15) [000046] ------------              *  RETURN    int
N005 ( 11, 14) [000045] ------------              \--*  ADD       int
N003 (  7,  9) [000041] ------------                 +--*  ADD       int
N001 (  3,  4) [000037] ------------                 |  +--*  LCL_FLD   int    V00 loc0         [+0] Fseq[i1]
N002 (  3,  4) [000040] ------------                 |  \--*  LCL_FLD   int    V00 loc0         [+4] Fseq[i2]
N004 (  3,  4) [000044] ------------                 \--*  LCL_FLD   int    V00 loc0         [+8] Fseq[i3]

-------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Build SSA representation
*************** In SsaBuilder::Build()
[SsaBuilder] Max block count is 4.

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..038)-> BB03 ( cond )                     i label target hascall gcsafe
BB02 [0001]  1       BB01                  0.50    [038..03B)        (return)                     i gcsafe
BB03 [0002]  1       BB01                  0.50    [03B..050)        (return)                     i label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty
[SsaBuilder] Topologically sorted the graph.
[SsaBuilder::ComputeImmediateDom]

Inside fgBuildDomTree

After computing the Dominance Tree:
BB01 : BB03 BB02

*************** In fgLocalVarLiveness()
In fgLocalVarLivenessInit

Local V00 should not be enregistered because: it is a struct
Tracked variable (1 out of 3) table:
V00 loc0          [struct]: refCnt =   10, refCntWtd =   8.50

*************** In fgPerBlockLocalVarLiveness()
BB01 USE(1)={V00} + ByrefExposed + GcHeap
     DEF(1)={V00} + ByrefExposed* + GcHeap*

BB02 USE(0)={}
     DEF(0)={}

BB03 USE(1)={V00}
     DEF(0)={   }

** Memory liveness computed, GcHeap states and ByrefExposed states diverge
*************** In fgInterBlockLocalVarLiveness()

BB liveness after fgLiveVarAnalysis():

BB01 IN (1)={V00} + ByrefExposed + GcHeap
     OUT(1)={V00}

BB02 IN (0)={}
     OUT(0)={}

BB03 IN (1)={V00}
     OUT(0)={   }

*************** In optRemoveRedundantZeroInits()
*************** In SsaBuilder::InsertPhiFunctions()
Inserting phi functions:
*************** In SsaBuilder::RenameVariables()

After fgSsaBuild:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..038)-> BB03 ( cond )                     i label target hascall gcsafe
BB02 [0001]  1       BB01                  0.50    [038..03B)        (return)                     i gcsafe
BB03 [0002]  1       BB01                  0.50    [03B..050)        (return)                     i label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..038) -> BB03 (cond), preds={} succs={BB02,BB03}

***** BB01
STMT00000 (IL 0x000...0x003)
N003 (  5,  6) [000004] -A------R---              *  ASG       int
N002 (  3,  4) [000003] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:1->2[+0] Fseq[i1]
N001 (  1,  1) [000002] ------------              \--*  CNS_INT   int    1

***** BB01
STMT00001 (IL 0x008...0x00B)
N003 (  5,  6) [000009] -A------R---              *  ASG       int
N002 (  3,  4) [000008] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:2->3[+4] Fseq[i2]
N001 (  1,  1) [000007] ------------              \--*  CNS_INT   int    2

***** BB01
STMT00002 (IL 0x010...0x013)
N003 (  5,  6) [000014] -A------R---              *  ASG       int
N002 (  3,  4) [000013] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:3->4[+8] Fseq[i3]
N001 (  1,  1) [000012] ------------              \--*  CNS_INT   int    3

***** BB01
STMT00003 (IL 0x018...0x01B)
N003 (  5,  6) [000019] -A------R---              *  ASG       int
N002 (  3,  4) [000018] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:4->5[+12] Fseq[i4]
N001 (  1,  1) [000017] ------------              \--*  CNS_INT   int    4

***** BB01
STMT00004 (IL 0x020...0x023)
N003 (  5,  6) [000024] -A------R---              *  ASG       int
N002 (  3,  4) [000023] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:5->6[+16] Fseq[i5]
N001 (  1,  1) [000022] ------------              \--*  CNS_INT   int    5

***** BB01
STMT00005 (IL 0x028...0x036)
N006 ( 27, 14) [000026] -ACXG-------              *  CALL      void   Runtime_49101.Test
N003 (  7,  5) [000050] -A------R-L- arg0 SETUP   +--*  ASG       struct (copy)
N002 (  3,  2) [000049] D------N----              |  +--*  LCL_VAR   struct<S, 20>(AX) V02 tmp1
N001 (  3,  2) [000025] -------N----              |  \--*  LCL_VAR   struct<S, 20> V00 loc0         u:6
N005 (  3,  3) [000052] ------------ arg0 in rcx  \--*  ADDR      byref
N004 (  3,  2) [000051] -------N----                 \--*  LCL_VAR   struct<S, 20>(AX) V02 tmp1

***** BB01
STMT00006 (IL 0x02E...  ???)
N004 (  7,  8) [000034] ------------              *  JTRUE     void
N003 (  5,  6) [000033] N------N-U--              \--*  NE        int
N001 (  3,  4) [000031] ------------                 +--*  LCL_FLD   int    V00 loc0         u:6[+8] Fseq[i3]
N002 (  1,  1) [000032] ------------                 \--*  CNS_INT   int    10

------------ BB02 [038..03B) (return), preds={BB01} succs={}

***** BB02
STMT00008 (IL 0x038...0x03A)
N002 (  2,  2) [000048] ------------              *  RETURN    int
N001 (  1,  1) [000047] ------------              \--*  CNS_INT   int    10

------------ BB03 [03B..050) (return), preds={BB01} succs={}

***** BB03
STMT00007 (IL 0x03B...0x04F)
N006 ( 12, 15) [000046] ------------              *  RETURN    int
N005 ( 11, 14) [000045] ------------              \--*  ADD       int
N003 (  7,  9) [000041] ------------                 +--*  ADD       int
N001 (  3,  4) [000037] ------------                 |  +--*  LCL_FLD   int    V00 loc0         u:6[+0] Fseq[i1]
N002 (  3,  4) [000040] ------------                 |  \--*  LCL_FLD   int    V00 loc0         u:6[+4] Fseq[i2]
N004 (  3,  4) [000044] ------------                 \--*  LCL_FLD   int    V00 loc0         u:6[+8] Fseq[i3] (last use)

-------------------------------------------------------------------------------------------------------------------

*************** Finishing PHASE Build SSA representation
Trees after Build SSA representation

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..038)-> BB03 ( cond )                     i label target hascall gcsafe
BB02 [0001]  1       BB01                  0.50    [038..03B)        (return)                     i gcsafe
BB03 [0002]  1       BB01                  0.50    [03B..050)        (return)                     i label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..038) -> BB03 (cond), preds={} succs={BB02,BB03}

***** BB01
STMT00000 (IL 0x000...0x003)
N003 (  5,  6) [000004] -A------R---              *  ASG       int
N002 (  3,  4) [000003] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:1->2[+0] Fseq[i1]
N001 (  1,  1) [000002] ------------              \--*  CNS_INT   int    1

***** BB01
STMT00001 (IL 0x008...0x00B)
N003 (  5,  6) [000009] -A------R---              *  ASG       int
N002 (  3,  4) [000008] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:2->3[+4] Fseq[i2]
N001 (  1,  1) [000007] ------------              \--*  CNS_INT   int    2

***** BB01
STMT00002 (IL 0x010...0x013)
N003 (  5,  6) [000014] -A------R---              *  ASG       int
N002 (  3,  4) [000013] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:3->4[+8] Fseq[i3]
N001 (  1,  1) [000012] ------------              \--*  CNS_INT   int    3

***** BB01
STMT00003 (IL 0x018...0x01B)
N003 (  5,  6) [000019] -A------R---              *  ASG       int
N002 (  3,  4) [000018] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:4->5[+12] Fseq[i4]
N001 (  1,  1) [000017] ------------              \--*  CNS_INT   int    4

***** BB01
STMT00004 (IL 0x020...0x023)
N003 (  5,  6) [000024] -A------R---              *  ASG       int
N002 (  3,  4) [000023] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:5->6[+16] Fseq[i5]
N001 (  1,  1) [000022] ------------              \--*  CNS_INT   int    5

***** BB01
STMT00005 (IL 0x028...0x036)
N006 ( 27, 14) [000026] -ACXG-------              *  CALL      void   Runtime_49101.Test
N003 (  7,  5) [000050] -A------R-L- arg0 SETUP   +--*  ASG       struct (copy)
N002 (  3,  2) [000049] D------N----              |  +--*  LCL_VAR   struct<S, 20>(AX) V02 tmp1
N001 (  3,  2) [000025] -------N----              |  \--*  LCL_VAR   struct<S, 20> V00 loc0         u:6
N005 (  3,  3) [000052] ------------ arg0 in rcx  \--*  ADDR      byref
N004 (  3,  2) [000051] -------N----                 \--*  LCL_VAR   struct<S, 20>(AX) V02 tmp1

***** BB01
STMT00006 (IL 0x02E...  ???)
N004 (  7,  8) [000034] ------------              *  JTRUE     void
N003 (  5,  6) [000033] N------N-U--              \--*  NE        int
N001 (  3,  4) [000031] ------------                 +--*  LCL_FLD   int    V00 loc0         u:6[+8] Fseq[i3]
N002 (  1,  1) [000032] ------------                 \--*  CNS_INT   int    10

------------ BB02 [038..03B) (return), preds={BB01} succs={}

***** BB02
STMT00008 (IL 0x038...0x03A)
N002 (  2,  2) [000048] ------------              *  RETURN    int
N001 (  1,  1) [000047] ------------              \--*  CNS_INT   int    10

------------ BB03 [03B..050) (return), preds={BB01} succs={}

***** BB03
STMT00007 (IL 0x03B...0x04F)
N006 ( 12, 15) [000046] ------------              *  RETURN    int
N005 ( 11, 14) [000045] ------------              \--*  ADD       int
N003 (  7,  9) [000041] ------------                 +--*  ADD       int
N001 (  3,  4) [000037] ------------                 |  +--*  LCL_FLD   int    V00 loc0         u:6[+0] Fseq[i1]
N002 (  3,  4) [000040] ------------                 |  \--*  LCL_FLD   int    V00 loc0         u:6[+4] Fseq[i2]
N004 (  3,  4) [000044] ------------                 \--*  LCL_FLD   int    V00 loc0         u:6[+8] Fseq[i3] (last use)

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist

*************** Starting PHASE Early Value Propagation
*************** In optEarlyProp()

After optEarlyProp:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..038)-> BB03 ( cond )                     i label target hascall gcsafe
BB02 [0001]  1       BB01                  0.50    [038..03B)        (return)                     i gcsafe
BB03 [0002]  1       BB01                  0.50    [03B..050)        (return)                     i label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..038) -> BB03 (cond), preds={} succs={BB02,BB03}

***** BB01
STMT00000 (IL 0x000...0x003)
N003 (  5,  6) [000004] -A------R---              *  ASG       int
N002 (  3,  4) [000003] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:1->2[+0] Fseq[i1]
N001 (  1,  1) [000002] ------------              \--*  CNS_INT   int    1

***** BB01
STMT00001 (IL 0x008...0x00B)
N003 (  5,  6) [000009] -A------R---              *  ASG       int
N002 (  3,  4) [000008] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:2->3[+4] Fseq[i2]
N001 (  1,  1) [000007] ------------              \--*  CNS_INT   int    2

***** BB01
STMT00002 (IL 0x010...0x013)
N003 (  5,  6) [000014] -A------R---              *  ASG       int
N002 (  3,  4) [000013] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:3->4[+8] Fseq[i3]
N001 (  1,  1) [000012] ------------              \--*  CNS_INT   int    3

***** BB01
STMT00003 (IL 0x018...0x01B)
N003 (  5,  6) [000019] -A------R---              *  ASG       int
N002 (  3,  4) [000018] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:4->5[+12] Fseq[i4]
N001 (  1,  1) [000017] ------------              \--*  CNS_INT   int    4

***** BB01
STMT00004 (IL 0x020...0x023)
N003 (  5,  6) [000024] -A------R---              *  ASG       int
N002 (  3,  4) [000023] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:5->6[+16] Fseq[i5]
N001 (  1,  1) [000022] ------------              \--*  CNS_INT   int    5

***** BB01
STMT00005 (IL 0x028...0x036)
N006 ( 27, 14) [000026] -ACXG-------              *  CALL      void   Runtime_49101.Test
N003 (  7,  5) [000050] -A------R-L- arg0 SETUP   +--*  ASG       struct (copy)
N002 (  3,  2) [000049] D------N----              |  +--*  LCL_VAR   struct<S, 20>(AX) V02 tmp1
N001 (  3,  2) [000025] -------N----              |  \--*  LCL_VAR   struct<S, 20> V00 loc0         u:6
N005 (  3,  3) [000052] ------------ arg0 in rcx  \--*  ADDR      byref
N004 (  3,  2) [000051] -------N----                 \--*  LCL_VAR   struct<S, 20>(AX) V02 tmp1

***** BB01
STMT00006 (IL 0x02E...  ???)
N004 (  7,  8) [000034] ------------              *  JTRUE     void
N003 (  5,  6) [000033] N------N-U--              \--*  NE        int
N001 (  3,  4) [000031] ------------                 +--*  LCL_FLD   int    V00 loc0         u:6[+8] Fseq[i3]
N002 (  1,  1) [000032] ------------                 \--*  CNS_INT   int    10

------------ BB02 [038..03B) (return), preds={BB01} succs={}

***** BB02
STMT00008 (IL 0x038...0x03A)
N002 (  2,  2) [000048] ------------              *  RETURN    int
N001 (  1,  1) [000047] ------------              \--*  CNS_INT   int    10

------------ BB03 [03B..050) (return), preds={BB01} succs={}

***** BB03
STMT00007 (IL 0x03B...0x04F)
N006 ( 12, 15) [000046] ------------              *  RETURN    int
N005 ( 11, 14) [000045] ------------              \--*  ADD       int
N003 (  7,  9) [000041] ------------                 +--*  ADD       int
N001 (  3,  4) [000037] ------------                 |  +--*  LCL_FLD   int    V00 loc0         u:6[+0] Fseq[i1]
N002 (  3,  4) [000040] ------------                 |  \--*  LCL_FLD   int    V00 loc0         u:6[+4] Fseq[i2]
N004 (  3,  4) [000044] ------------                 \--*  LCL_FLD   int    V00 loc0         u:6[+8] Fseq[i3] (last use)

-------------------------------------------------------------------------------------------------------------------

*************** Finishing PHASE Early Value Propagation

*************** Starting PHASE Do value numbering

*************** In fgValueNumber()
Memory Initial Value in BB01 is: $80
The SSA definition for ByrefExposed (#1) at start of BB01 is $80 {InitVal($40)}
The SSA definition for GcHeap (#1) at start of BB01 is $80 {InitVal($40)}

***** BB01, STMT00000(before)
N003 (  5,  6) [000004] -A------R---              *  ASG       int
N002 (  3,  4) [000003] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:1->2[+0] Fseq[i1]
N001 (  1,  1) [000002] ------------              \--*  CNS_INT   int    1

N001 [000002]   CNS_INT   1 => $41 {IntCns 1}
  VNApplySelectors:
    VNForHandle(i1) is $c0, fieldType is int
    VNForMapSelect($1, $c0):int returns $42 {IntCns 0}
  VNApplySelectors:
    VNForHandle(i1) is $c0, fieldType is int
    VNForMapSelect($1, $c0):int returns $42 {IntCns 0}
N002 [000003]   LCL_FLD   V00 loc0         ud:1->2[+0] Fseq[i1] => $42 {IntCns 0}
  VNApplySelectorsAssign:
    VNForHandle(i1) is $c0, fieldType is int
    VNForMapStore($1, $c0, $41):int returns $100 {$VN.ZeroMap[$c0 := $41]}
  VNApplySelectorsAssign:
    VNForHandle(i1) is $c0, fieldType is int
    VNForMapStore($1, $c0, $41):int returns $100 {$VN.ZeroMap[$c0 := $41]}
N002 [000003]   LCL_FLD   V00 loc0         ud:1->2[+0] Fseq[i1] => $100 {$VN.ZeroMap[$c0 := $41]}
N003 [000004]   ASG       => $41 {IntCns 1}

***** BB01, STMT00000(after)
N003 (  5,  6) [000004] -A------R---              *  ASG       int    $41
N002 (  3,  4) [000003] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:1->2[+0] Fseq[i1] $100
N001 (  1,  1) [000002] ------------              \--*  CNS_INT   int    1 $41

---------

***** BB01, STMT00001(before)
N003 (  5,  6) [000009] -A------R---              *  ASG       int
N002 (  3,  4) [000008] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:2->3[+4] Fseq[i2]
N001 (  1,  1) [000007] ------------              \--*  CNS_INT   int    2

N001 [000007]   CNS_INT   2 => $43 {IntCns 2}
  VNApplySelectors:
    VNForHandle(i2) is $c1, fieldType is int
      AX2: $c1 != $c0 ==> select([$100]store($1, $c0, $41), $c1) ==> select($1, $c1).
    VNForMapSelect($100, $c1):int returns $42 {IntCns 0}
  VNApplySelectors:
    VNForHandle(i2) is $c1, fieldType is int
      AX2: $c1 != $c0 ==> select([$100]store($1, $c0, $41), $c1) ==> select($1, $c1).
    VNForMapSelect($100, $c1):int returns $42 {IntCns 0}
N002 [000008]   LCL_FLD   V00 loc0         ud:2->3[+4] Fseq[i2] => $42 {IntCns 0}
  VNApplySelectorsAssign:
    VNForHandle(i2) is $c1, fieldType is int
    VNForMapStore($100, $c1, $43):int returns $101 {$100[$c1 := $43]}
  VNApplySelectorsAssign:
    VNForHandle(i2) is $c1, fieldType is int
    VNForMapStore($100, $c1, $43):int returns $101 {$100[$c1 := $43]}
N002 [000008]   LCL_FLD   V00 loc0         ud:2->3[+4] Fseq[i2] => $101 {$100[$c1 := $43]}
N003 [000009]   ASG       => $43 {IntCns 2}

***** BB01, STMT00001(after)
N003 (  5,  6) [000009] -A------R---              *  ASG       int    $43
N002 (  3,  4) [000008] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:2->3[+4] Fseq[i2] $101
N001 (  1,  1) [000007] ------------              \--*  CNS_INT   int    2 $43

---------

***** BB01, STMT00002(before)
N003 (  5,  6) [000014] -A------R---              *  ASG       int
N002 (  3,  4) [000013] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:3->4[+8] Fseq[i3]
N001 (  1,  1) [000012] ------------              \--*  CNS_INT   int    3

N001 [000012]   CNS_INT   3 => $44 {IntCns 3}
  VNApplySelectors:
    VNForHandle(i3) is $c2, fieldType is int
      AX2: $c2 != $c1 ==> select([$101]store($100, $c1, $43), $c2) ==> select($100, $c2).
      AX2: $c2 != $c0 ==> select([$100]store($1, $c0, $41), $c2) ==> select($1, $c2).
    VNForMapSelect($101, $c2):int returns $42 {IntCns 0}
  VNApplySelectors:
    VNForHandle(i3) is $c2, fieldType is int
      AX2: $c2 != $c1 ==> select([$101]store($100, $c1, $43), $c2) ==> select($100, $c2).
      AX2: $c2 != $c0 ==> select([$100]store($1, $c0, $41), $c2) ==> select($1, $c2).
    VNForMapSelect($101, $c2):int returns $42 {IntCns 0}
N002 [000013]   LCL_FLD   V00 loc0         ud:3->4[+8] Fseq[i3] => $42 {IntCns 0}
  VNApplySelectorsAssign:
    VNForHandle(i3) is $c2, fieldType is int
    VNForMapStore($101, $c2, $44):int returns $102 {$101[$c2 := $44]}
  VNApplySelectorsAssign:
    VNForHandle(i3) is $c2, fieldType is int
    VNForMapStore($101, $c2, $44):int returns $102 {$101[$c2 := $44]}
N002 [000013]   LCL_FLD   V00 loc0         ud:3->4[+8] Fseq[i3] => $102 {$101[$c2 := $44]}
N003 [000014]   ASG       => $44 {IntCns 3}

***** BB01, STMT00002(after)
N003 (  5,  6) [000014] -A------R---              *  ASG       int    $44
N002 (  3,  4) [000013] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:3->4[+8] Fseq[i3] $102
N001 (  1,  1) [000012] ------------              \--*  CNS_INT   int    3 $44

---------

***** BB01, STMT00003(before)
N003 (  5,  6) [000019] -A------R---              *  ASG       int
N002 (  3,  4) [000018] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:4->5[+12] Fseq[i4]
N001 (  1,  1) [000017] ------------              \--*  CNS_INT   int    4

N001 [000017]   CNS_INT   4 => $45 {IntCns 4}
  VNApplySelectors:
    VNForHandle(i4) is $c3, fieldType is int
      AX2: $c3 != $c2 ==> select([$102]store($101, $c2, $44), $c3) ==> select($101, $c3).
      AX2: $c3 != $c1 ==> select([$101]store($100, $c1, $43), $c3) ==> select($100, $c3).
      AX2: $c3 != $c0 ==> select([$100]store($1, $c0, $41), $c3) ==> select($1, $c3).
    VNForMapSelect($102, $c3):int returns $42 {IntCns 0}
  VNApplySelectors:
    VNForHandle(i4) is $c3, fieldType is int
      AX2: $c3 != $c2 ==> select([$102]store($101, $c2, $44), $c3) ==> select($101, $c3).
      AX2: $c3 != $c1 ==> select([$101]store($100, $c1, $43), $c3) ==> select($100, $c3).
      AX2: $c3 != $c0 ==> select([$100]store($1, $c0, $41), $c3) ==> select($1, $c3).
    VNForMapSelect($102, $c3):int returns $42 {IntCns 0}
N002 [000018]   LCL_FLD   V00 loc0         ud:4->5[+12] Fseq[i4] => $42 {IntCns 0}
  VNApplySelectorsAssign:
    VNForHandle(i4) is $c3, fieldType is int
    VNForMapStore($102, $c3, $45):int returns $103 {$102[$c3 := $45]}
  VNApplySelectorsAssign:
    VNForHandle(i4) is $c3, fieldType is int
    VNForMapStore($102, $c3, $45):int returns $103 {$102[$c3 := $45]}
N002 [000018]   LCL_FLD   V00 loc0         ud:4->5[+12] Fseq[i4] => $103 {$102[$c3 := $45]}
N003 [000019]   ASG       => $45 {IntCns 4}

***** BB01, STMT00003(after)
N003 (  5,  6) [000019] -A------R---              *  ASG       int    $45
N002 (  3,  4) [000018] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:4->5[+12] Fseq[i4] $103
N001 (  1,  1) [000017] ------------              \--*  CNS_INT   int    4 $45

---------

***** BB01, STMT00004(before)
N003 (  5,  6) [000024] -A------R---              *  ASG       int
N002 (  3,  4) [000023] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:5->6[+16] Fseq[i5]
N001 (  1,  1) [000022] ------------              \--*  CNS_INT   int    5

N001 [000022]   CNS_INT   5 => $46 {IntCns 5}
  VNApplySelectors:
    VNForHandle(i5) is $c4, fieldType is int
      AX2: $c4 != $c3 ==> select([$103]store($102, $c3, $45), $c4) ==> select($102, $c4).
      AX2: $c4 != $c2 ==> select([$102]store($101, $c2, $44), $c4) ==> select($101, $c4).
      AX2: $c4 != $c1 ==> select([$101]store($100, $c1, $43), $c4) ==> select($100, $c4).
      AX2: $c4 != $c0 ==> select([$100]store($1, $c0, $41), $c4) ==> select($1, $c4).
    VNForMapSelect($103, $c4):int returns $42 {IntCns 0}
  VNApplySelectors:
    VNForHandle(i5) is $c4, fieldType is int
      AX2: $c4 != $c3 ==> select([$103]store($102, $c3, $45), $c4) ==> select($102, $c4).
      AX2: $c4 != $c2 ==> select([$102]store($101, $c2, $44), $c4) ==> select($101, $c4).
      AX2: $c4 != $c1 ==> select([$101]store($100, $c1, $43), $c4) ==> select($100, $c4).
      AX2: $c4 != $c0 ==> select([$100]store($1, $c0, $41), $c4) ==> select($1, $c4).
    VNForMapSelect($103, $c4):int returns $42 {IntCns 0}
N002 [000023]   LCL_FLD   V00 loc0         ud:5->6[+16] Fseq[i5] => $42 {IntCns 0}
  VNApplySelectorsAssign:
    VNForHandle(i5) is $c4, fieldType is int
    VNForMapStore($103, $c4, $46):int returns $104 {$103[$c4 := $46]}
  VNApplySelectorsAssign:
    VNForHandle(i5) is $c4, fieldType is int
    VNForMapStore($103, $c4, $46):int returns $104 {$103[$c4 := $46]}
N002 [000023]   LCL_FLD   V00 loc0         ud:5->6[+16] Fseq[i5] => $104 {$103[$c4 := $46]}
N003 [000024]   ASG       => $46 {IntCns 5}

***** BB01, STMT00004(after)
N003 (  5,  6) [000024] -A------R---              *  ASG       int    $46
N002 (  3,  4) [000023] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:5->6[+16] Fseq[i5] $104
N001 (  1,  1) [000022] ------------              \--*  CNS_INT   int    5 $46

---------

***** BB01, STMT00005(before)
N006 ( 27, 14) [000026] -ACXG-------              *  CALL      void   Runtime_49101.Test
N003 (  7,  5) [000050] -A------R-L- arg0 SETUP   +--*  ASG       struct (copy)
N002 (  3,  2) [000049] D------N----              |  +--*  LCL_VAR   struct<S, 20>(AX) V02 tmp1
N001 (  3,  2) [000025] -------N----              |  \--*  LCL_VAR   struct<S, 20> V00 loc0         u:6
N005 (  3,  3) [000052] ------------ arg0 in rcx  \--*  ADDR      byref
N004 (  3,  2) [000051] -------N----                 \--*  LCL_VAR   struct<S, 20>(AX) V02 tmp1

N001 [000025]   LCL_VAR   V00 loc0         u:6 => $104 {$103[$c4 := $46]}
  fgCurMemoryVN[ByrefExposed] assigned for COPYBLK - address-exposed local at [000050] to VN: $140.
N003 [000050]   ASG       => $VN.Void
N004 [000051]   LCL_VAR   V02 tmp1          => $1c0 {1c0}
N005 [000052]   ADDR      => $200 {200}
  fgCurMemoryVN[GcHeap] assigned for CALL at [000026] to VN: $240.
N006 [000026]   CALL      => $VN.Void

***** BB01, STMT00005(after)
N006 ( 27, 14) [000026] -ACXG-------              *  CALL      void   Runtime_49101.Test $VN.Void
N003 (  7,  5) [000050] -A------R-L- arg0 SETUP   +--*  ASG       struct (copy) $VN.Void
N002 (  3,  2) [000049] D------N----              |  +--*  LCL_VAR   struct<S, 20>(AX) V02 tmp1
N001 (  3,  2) [000025] -------N----              |  \--*  LCL_VAR   struct<S, 20> V00 loc0         u:6 $104
N005 (  3,  3) [000052] ------------ arg0 in rcx  \--*  ADDR      byref  $200
N004 (  3,  2) [000051] -------N----                 \--*  LCL_VAR   struct<S, 20>(AX) V02 tmp1          $1c0

---------

***** BB01, STMT00006(before)
N004 (  7,  8) [000034] ------------              *  JTRUE     void
N003 (  5,  6) [000033] N------N-U--              \--*  NE        int
N001 (  3,  4) [000031] ------------                 +--*  LCL_FLD   int    V00 loc0         u:6[+8] Fseq[i3]
N002 (  1,  1) [000032] ------------                 \--*  CNS_INT   int    10

  VNApplySelectors:
    VNForHandle(i3) is $c2, fieldType is int
      AX2: $c2 != $c4 ==> select([$104]store($103, $c4, $46), $c2) ==> select($103, $c2).
      AX2: $c2 != $c3 ==> select([$103]store($102, $c3, $45), $c2) ==> select($102, $c2).
      AX1: select([$101]store($102, $c2, $44), $c2) ==> $44.
    VNForMapSelect($104, $c2):int returns $44 {IntCns 3}
  VNApplySelectors:
    VNForHandle(i3) is $c2, fieldType is int
      AX2: $c2 != $c4 ==> select([$104]store($103, $c4, $46), $c2) ==> select($103, $c2).
      AX2: $c2 != $c3 ==> select([$103]store($102, $c3, $45), $c2) ==> select($102, $c2).
      AX1: select([$101]store($102, $c2, $44), $c2) ==> $44.
    VNForMapSelect($104, $c2):int returns $44 {IntCns 3}
N001 [000031]   LCL_FLD   V00 loc0         u:6[+8] Fseq[i3] => $44 {IntCns 3}
N002 [000032]   CNS_INT   10 => $47 {IntCns 10}
N003 [000033]   NE        => $41 {IntCns 1}

***** BB01, STMT00006(after)
N004 (  7,  8) [000034] ------------              *  JTRUE     void
N003 (  5,  6) [000033] N------N-U--              \--*  NE        int    $41
N001 (  3,  4) [000031] ------------                 +--*  LCL_FLD   int    V00 loc0         u:6[+8] Fseq[i3] $44
N002 (  1,  1) [000032] ------------                 \--*  CNS_INT   int    10 $47

finish(BB01).
   Succ(BB02).
     Not yet completed.
     All preds complete, adding to allDone.
   Succ(BB03).
     Not yet completed.
     All preds complete, adding to allDone.
The SSA definition for ByrefExposed (#2) at start of BB03 is $141 {141}
The SSA definition for GcHeap (#3) at start of BB03 is $240 {240}

***** BB03, STMT00007(before)
N006 ( 12, 15) [000046] ------------              *  RETURN    int
N005 ( 11, 14) [000045] ------------              \--*  ADD       int
N003 (  7,  9) [000041] ------------                 +--*  ADD       int
N001 (  3,  4) [000037] ------------                 |  +--*  LCL_FLD   int    V00 loc0         u:6[+0] Fseq[i1]
N002 (  3,  4) [000040] ------------                 |  \--*  LCL_FLD   int    V00 loc0         u:6[+4] Fseq[i2]
N004 (  3,  4) [000044] ------------                 \--*  LCL_FLD   int    V00 loc0         u:6[+8] Fseq[i3] (last use)

  VNApplySelectors:
    VNForHandle(i1) is $c0, fieldType is int
      AX2: $c0 != $c4 ==> select([$104]store($103, $c4, $46), $c0) ==> select($103, $c0).
      AX2: $c0 != $c3 ==> select([$103]store($102, $c3, $45), $c0) ==> select($102, $c0).
      AX2: $c0 != $c2 ==> select([$102]store($101, $c2, $44), $c0) ==> select($101, $c0).
      AX2: $c0 != $c1 ==> select([$101]store($100, $c1, $43), $c0) ==> select($100, $c0).
      AX1: select([$1]store($100, $c0, $41), $c0) ==> $41.
    VNForMapSelect($104, $c0):int returns $41 {IntCns 1}
  VNApplySelectors:
    VNForHandle(i1) is $c0, fieldType is int
      AX2: $c0 != $c4 ==> select([$104]store($103, $c4, $46), $c0) ==> select($103, $c0).
      AX2: $c0 != $c3 ==> select([$103]store($102, $c3, $45), $c0) ==> select($102, $c0).
      AX2: $c0 != $c2 ==> select([$102]store($101, $c2, $44), $c0) ==> select($101, $c0).
      AX2: $c0 != $c1 ==> select([$101]store($100, $c1, $43), $c0) ==> select($100, $c0).
      AX1: select([$1]store($100, $c0, $41), $c0) ==> $41.
    VNForMapSelect($104, $c0):int returns $41 {IntCns 1}
N001 [000037]   LCL_FLD   V00 loc0         u:6[+0] Fseq[i1] => $41 {IntCns 1}
  VNApplySelectors:
    VNForHandle(i2) is $c1, fieldType is int
      AX2: $c1 != $c4 ==> select([$104]store($103, $c4, $46), $c1) ==> select($103, $c1).
      AX2: $c1 != $c3 ==> select([$103]store($102, $c3, $45), $c1) ==> select($102, $c1).
      AX2: $c1 != $c2 ==> select([$102]store($101, $c2, $44), $c1) ==> select($101, $c1).
      AX1: select([$100]store($101, $c1, $43), $c1) ==> $43.
    VNForMapSelect($104, $c1):int returns $43 {IntCns 2}
  VNApplySelectors:
    VNForHandle(i2) is $c1, fieldType is int
      AX2: $c1 != $c4 ==> select([$104]store($103, $c4, $46), $c1) ==> select($103, $c1).
      AX2: $c1 != $c3 ==> select([$103]store($102, $c3, $45), $c1) ==> select($102, $c1).
      AX2: $c1 != $c2 ==> select([$102]store($101, $c2, $44), $c1) ==> select($101, $c1).
      AX1: select([$100]store($101, $c1, $43), $c1) ==> $43.
    VNForMapSelect($104, $c1):int returns $43 {IntCns 2}
N002 [000040]   LCL_FLD   V00 loc0         u:6[+4] Fseq[i2] => $43 {IntCns 2}
N003 [000041]   ADD       => $44 {IntCns 3}
  VNApplySelectors:
    VNForHandle(i3) is $c2, fieldType is int
      AX2: $c2 != $c4 ==> select([$104]store($103, $c4, $46), $c2) ==> select($103, $c2).
      AX2: $c2 != $c3 ==> select([$103]store($102, $c3, $45), $c2) ==> select($102, $c2).
      AX1: select([$101]store($102, $c2, $44), $c2) ==> $44.
    VNForMapSelect($104, $c2):int returns $44 {IntCns 3}
  VNApplySelectors:
    VNForHandle(i3) is $c2, fieldType is int
      AX2: $c2 != $c4 ==> select([$104]store($103, $c4, $46), $c2) ==> select($103, $c2).
      AX2: $c2 != $c3 ==> select([$103]store($102, $c3, $45), $c2) ==> select($102, $c2).
      AX1: select([$101]store($102, $c2, $44), $c2) ==> $44.
    VNForMapSelect($104, $c2):int returns $44 {IntCns 3}
N004 [000044]   LCL_FLD   V00 loc0         u:6[+8] Fseq[i3] (last use) => $44 {IntCns 3}
N005 [000045]   ADD       => $48 {IntCns 6}
N006 [000046]   RETURN    => $280 {280}

***** BB03, STMT00007(after)
N006 ( 12, 15) [000046] ------------              *  RETURN    int    $280
N005 ( 11, 14) [000045] ------------              \--*  ADD       int    $48
N003 (  7,  9) [000041] ------------                 +--*  ADD       int    $44
N001 (  3,  4) [000037] ------------                 |  +--*  LCL_FLD   int    V00 loc0         u:6[+0] Fseq[i1] $41
N002 (  3,  4) [000040] ------------                 |  \--*  LCL_FLD   int    V00 loc0         u:6[+4] Fseq[i2] $43
N004 (  3,  4) [000044] ------------                 \--*  LCL_FLD   int    V00 loc0         u:6[+8] Fseq[i3] (last use) $44

finish(BB03).
The SSA definition for ByrefExposed (#2) at start of BB02 is $141 {141}
The SSA definition for GcHeap (#3) at start of BB02 is $240 {240}

***** BB02, STMT00008(before)
N002 (  2,  2) [000048] ------------              *  RETURN    int
N001 (  1,  1) [000047] ------------              \--*  CNS_INT   int    10

N001 [000047]   CNS_INT   10 => $47 {IntCns 10}
N002 [000048]   RETURN    => $281 {281}

***** BB02, STMT00008(after)
N002 (  2,  2) [000048] ------------              *  RETURN    int    $281
N001 (  1,  1) [000047] ------------              \--*  CNS_INT   int    10 $47

finish(BB02).

*************** Finishing PHASE Do value numbering

*************** Starting PHASE Hoist loop code

*************** Finishing PHASE Hoist loop code

*************** Starting PHASE VN based copy prop
*************** In optVnCopyProp()
Copy Assertion for BB01
  curSsaName stack: { }

Copy Assertion for BB03
  curSsaName stack: { 0-[000023]:V00 }

                                                        Live vars: {V00} => {}
Copy Assertion for BB02
  curSsaName stack: { 0-[000023]:V00 }


*************** Finishing PHASE VN based copy prop

*************** Starting PHASE Redundant branch opts

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..038)-> BB03 ( cond )                     i label target hascall gcsafe
BB02 [0001]  1       BB01                  0.50    [038..03B)        (return)                     i gcsafe
BB03 [0002]  1       BB01                  0.50    [03B..050)        (return)                     i label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------

*************** Finishing PHASE Redundant branch opts [no changes]

*************** Starting PHASE Optimize Valnum CSEs

*************** In optOptimizeCSEs()
Blocks/Trees at start of optOptimizeCSE phase

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..038)-> BB03 ( cond )                     i label target hascall gcsafe
BB02 [0001]  1       BB01                  0.50    [038..03B)        (return)                     i gcsafe
BB03 [0002]  1       BB01                  0.50    [03B..050)        (return)                     i label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..038) -> BB03 (cond), preds={} succs={BB02,BB03}

***** BB01
STMT00000 (IL 0x000...0x003)
N003 (  5,  6) [000004] -A------R---              *  ASG       int    $41
N002 (  3,  4) [000003] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:1->2[+0] Fseq[i1] $100
N001 (  1,  1) [000002] ------------              \--*  CNS_INT   int    1 $41

***** BB01
STMT00001 (IL 0x008...0x00B)
N003 (  5,  6) [000009] -A------R---              *  ASG       int    $43
N002 (  3,  4) [000008] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:2->3[+4] Fseq[i2] $101
N001 (  1,  1) [000007] ------------              \--*  CNS_INT   int    2 $43

***** BB01
STMT00002 (IL 0x010...0x013)
N003 (  5,  6) [000014] -A------R---              *  ASG       int    $44
N002 (  3,  4) [000013] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:3->4[+8] Fseq[i3] $102
N001 (  1,  1) [000012] ------------              \--*  CNS_INT   int    3 $44

***** BB01
STMT00003 (IL 0x018...0x01B)
N003 (  5,  6) [000019] -A------R---              *  ASG       int    $45
N002 (  3,  4) [000018] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:4->5[+12] Fseq[i4] $103
N001 (  1,  1) [000017] ------------              \--*  CNS_INT   int    4 $45

***** BB01
STMT00004 (IL 0x020...0x023)
N003 (  5,  6) [000024] -A------R---              *  ASG       int    $46
N002 (  3,  4) [000023] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:5->6[+16] Fseq[i5] $104
N001 (  1,  1) [000022] ------------              \--*  CNS_INT   int    5 $46

***** BB01
STMT00005 (IL 0x028...0x036)
N006 ( 27, 14) [000026] -ACXG-------              *  CALL      void   Runtime_49101.Test $VN.Void
N003 (  7,  5) [000050] -A------R-L- arg0 SETUP   +--*  ASG       struct (copy) $VN.Void
N002 (  3,  2) [000049] D------N----              |  +--*  LCL_VAR   struct<S, 20>(AX) V02 tmp1
N001 (  3,  2) [000025] -------N----              |  \--*  LCL_VAR   struct<S, 20> V00 loc0         u:6 $104
N005 (  3,  3) [000052] ------------ arg0 in rcx  \--*  ADDR      byref  $200
N004 (  3,  2) [000051] -------N----                 \--*  LCL_VAR   struct<S, 20>(AX) V02 tmp1          $1c0

***** BB01
STMT00006 (IL 0x02E...  ???)
N004 (  7,  8) [000034] ------------              *  JTRUE     void
N003 (  5,  6) [000033] N------N-U--              \--*  NE        int    $41
N001 (  3,  4) [000031] ------------                 +--*  LCL_FLD   int    V00 loc0         u:6[+8] Fseq[i3] $44
N002 (  1,  1) [000032] ------------                 \--*  CNS_INT   int    10 $47

------------ BB02 [038..03B) (return), preds={BB01} succs={}

***** BB02
STMT00008 (IL 0x038...0x03A)
N002 (  2,  2) [000048] ------------              *  RETURN    int    $281
N001 (  1,  1) [000047] ------------              \--*  CNS_INT   int    10 $47

------------ BB03 [03B..050) (return), preds={BB01} succs={}

***** BB03
STMT00007 (IL 0x03B...0x04F)
N006 ( 12, 15) [000046] ------------              *  RETURN    int    $280
N005 ( 11, 14) [000045] ------------              \--*  ADD       int    $48
N003 (  7,  9) [000041] ------------                 +--*  ADD       int    $44
N001 (  3,  4) [000037] ------------                 |  +--*  LCL_FLD   int    V00 loc0         u:6[+0] Fseq[i1] $41
N002 (  3,  4) [000040] ------------                 |  \--*  LCL_FLD   int    V00 loc0         u:6[+4] Fseq[i2] $43
N004 (  3,  4) [000044] ------------                 \--*  LCL_FLD   int    V00 loc0         u:6[+8] Fseq[i3] (last use) $44

-------------------------------------------------------------------------------------------------------------------

*************** In optOptimizeValnumCSEs()

CSE candidate #01, key=$44 in BB03, [cost= 3, size= 4]:
N004 (  3,  4) CSE #01 (use)[000044] ------------              *  LCL_FLD   int    V00 loc0         u:6[+8] Fseq[i3] (last use) $44

Blocks that generate CSE def/uses
BB01 cseGen = 0000000000000003
BB03 cseGen = 0000000000000003

Performing DataFlow for ValnumCSE's
StartMerge BB01
  :: cseOut    = 0000000000000007
EndMerge BB01
  :: cseIn     = 0000000000000000
  :: cseGen    = 0000000000000003
  => cseOut    = 0000000000000003
  != preMerge  = 0000000000000007, => true
StartMerge BB02
  :: cseOut    = 0000000000000007
Merge BB02 and BB01
  :: cseIn     = 0000000000000007
  :: cseOut    = 0000000000000007
  => cseIn     = 0000000000000003
EndMerge BB02
  :: cseIn     = 0000000000000003
  :: cseGen    = 0000000000000000
  => cseOut    = 0000000000000003
  != preMerge  = 0000000000000007, => true
StartMerge BB03
  :: cseOut    = 0000000000000007
Merge BB03 and BB01
  :: cseIn     = 0000000000000007
  :: cseOut    = 0000000000000007
  => cseIn     = 0000000000000003
EndMerge BB03
  :: cseIn     = 0000000000000003
  :: cseGen    = 0000000000000003
  => cseOut    = 0000000000000003
  != preMerge  = 0000000000000007, => true

After performing DataFlow for ValnumCSE's
BB01 cseIn  = 0000000000000000, cseGen = 0000000000000003, cseOut = 0000000000000003
BB02 cseIn  = 0000000000000003, cseGen = 0000000000000000, cseOut = 0000000000000003
BB03 cseIn  = 0000000000000003, cseGen = 0000000000000003, cseOut = 0000000000000003

Labeling the CSEs with Use/Def information
BB01 [000031] Def of CSE #01 [weight=1   ]
BB03 [000044] Use of CSE #01 [weight=0.50]

************ Trees at start of optValnumCSE_Heuristic()

------------ BB01 [000..038) -> BB03 (cond), preds={} succs={BB02,BB03}

***** BB01
STMT00000 (IL 0x000...0x003)
N003 (  5,  6)              [000004] -A------R---              *  ASG       int    $41
N002 (  3,  4)              [000003] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:1->2[+0] Fseq[i1] $100
N001 (  1,  1)              [000002] ------------              \--*  CNS_INT   int    1 $41

***** BB01
STMT00001 (IL 0x008...0x00B)
N003 (  5,  6)              [000009] -A------R---              *  ASG       int    $43
N002 (  3,  4)              [000008] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:2->3[+4] Fseq[i2] $101
N001 (  1,  1)              [000007] ------------              \--*  CNS_INT   int    2 $43

***** BB01
STMT00002 (IL 0x010...0x013)
N003 (  5,  6)              [000014] -A------R---              *  ASG       int    $44
N002 (  3,  4)              [000013] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:3->4[+8] Fseq[i3] $102
N001 (  1,  1)              [000012] ------------              \--*  CNS_INT   int    3 $44

***** BB01
STMT00003 (IL 0x018...0x01B)
N003 (  5,  6)              [000019] -A------R---              *  ASG       int    $45
N002 (  3,  4)              [000018] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:4->5[+12] Fseq[i4] $103
N001 (  1,  1)              [000017] ------------              \--*  CNS_INT   int    4 $45

***** BB01
STMT00004 (IL 0x020...0x023)
N003 (  5,  6)              [000024] -A------R---              *  ASG       int    $46
N002 (  3,  4)              [000023] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:5->6[+16] Fseq[i5] $104
N001 (  1,  1)              [000022] ------------              \--*  CNS_INT   int    5 $46

***** BB01
STMT00005 (IL 0x028...0x036)
N006 ( 27, 14)              [000026] -ACXG-------              *  CALL      void   Runtime_49101.Test $VN.Void
N003 (  7,  5)              [000050] -A------R-L- arg0 SETUP   +--*  ASG       struct (copy) $VN.Void
N002 (  3,  2)              [000049] D------N----              |  +--*  LCL_VAR   struct<S, 20>(AX) V02 tmp1
N001 (  3,  2)              [000025] -------N----              |  \--*  LCL_VAR   struct<S, 20> V00 loc0         u:6 $104
N005 (  3,  3)              [000052] ------------ arg0 in rcx  \--*  ADDR      byref  $200
N004 (  3,  2)              [000051] -------N----                 \--*  LCL_VAR   struct<S, 20>(AX) V02 tmp1          $1c0

***** BB01
STMT00006 (IL 0x02E...  ???)
N004 (  7,  8)              [000034] ------------              *  JTRUE     void
N003 (  5,  6)              [000033] N------N-U--              \--*  NE        int    $41
N001 (  3,  4) CSE #01 (def)[000031] ------------                 +--*  LCL_FLD   int    V00 loc0         u:6[+8] Fseq[i3] $44
N002 (  1,  1)              [000032] ------------                 \--*  CNS_INT   int    10 $47

------------ BB02 [038..03B) (return), preds={BB01} succs={}

***** BB02
STMT00008 (IL 0x038...0x03A)
N002 (  2,  2)              [000048] ------------              *  RETURN    int    $281
N001 (  1,  1)              [000047] ------------              \--*  CNS_INT   int    10 $47

------------ BB03 [03B..050) (return), preds={BB01} succs={}

***** BB03
STMT00007 (IL 0x03B...0x04F)
N006 ( 12, 15)              [000046] ------------              *  RETURN    int    $280
N005 ( 11, 14)              [000045] ------------              \--*  ADD       int    $48
N003 (  7,  9)              [000041] ------------                 +--*  ADD       int    $44
N001 (  3,  4)              [000037] ------------                 |  +--*  LCL_FLD   int    V00 loc0         u:6[+0] Fseq[i1] $41
N002 (  3,  4)              [000040] ------------                 |  \--*  LCL_FLD   int    V00 loc0         u:6[+4] Fseq[i2] $43
N004 (  3,  4) CSE #01 (use)[000044] ------------                 \--*  LCL_FLD   int    V00 loc0         u:6[+8] Fseq[i3] (last use) $44

-------------------------------------------------------------------------------------------------------------------


Aggressive CSE Promotion cutoff is 200.000000
Moderate CSE Promotion cutoff is 100.000000
enregCount is 0
Framesize estimate is 0x0030
We have a small frame

Sorted CSE candidates:
CSE #01, {$44 , $4  } useCnt=1: [def=100.000000, use=50.000000, cost=  3      ]
        :: N001 (  3,  4) CSE #01 (def)[000031] ------------              *  LCL_FLD   int    V00 loc0         u:6[+8] Fseq[i3] $44


Considering CSE #01 {$44 , $4  } [def=100.000000, use=50.000000, cost=  3      ]
CSE Expression :
N001 (  3,  4) CSE #01 (def)[000031] ------------              *  LCL_FLD   int    V00 loc0         u:6[+8] Fseq[i3] $44

Aggressive CSE Promotion (250.000000 >= 200.000000)
cseRefCnt=250.000000, aggressiveRefCnt=200.000000, moderateRefCnt=100.000000
defCnt=100.000000, useCnt=50.000000, cost=3, size=4
def_cost=1, use_cost=1, extra_no_cost=6, extra_yes_cost=0
CSE cost savings check (156.000000 >= 150.000000) passes

Promoting CSE:

lvaGrabTemp returning 3 (V03 rat0) (a long lifetime temp) called for CSE - aggressive.
CSE #01 is single-def, so associated CSE temp V03 will be in SSA
New refCnts for V03: refCnt =  2, refCntWtd = 2
New refCnts for V03: refCnt =  3, refCntWtd = 2.50

CSE #01 def at [000031] replaced in BB01 with def of V03
optValnumCSE morphed tree:
N008 ( 14, 13)              [000034] -A----------              *  JTRUE     void
N007 ( 12, 11)              [000033] NA-----N-U--              \--*  NE        int    $41
N005 ( 10,  9)              [000056] -A----------                 +--*  COMMA     int    $44
N003 (  7,  7)              [000054] -A------R---                 |  +--*  ASG       int    $VN.Void
N002 (  3,  2)              [000053] D------N----                 |  |  +--*  LCL_VAR   int    V03 cse0         d:1 $44
N001 (  3,  4)              [000031] ------------                 |  |  \--*  LCL_FLD   int    V00 loc0         u:6[+8] Fseq[i3] $44
N004 (  3,  2)              [000055] ------------                 |  \--*  LCL_VAR   int    V03 cse0         u:1 $44
N006 (  1,  1)              [000032] ------------                 \--*  CNS_INT   int    10 $47


Working on the replacement of the CSE #01 use at [000044] in BB03
optValnumCSE morphed tree:
N006 ( 12, 13)              [000046] ------------              *  RETURN    int    $280
N005 ( 11, 12)              [000045] ------------              \--*  ADD       int    $48
N003 (  7,  9)              [000041] ------------                 +--*  ADD       int    $44
N001 (  3,  4)              [000037] ------------                 |  +--*  LCL_FLD   int    V00 loc0         u:6[+0] Fseq[i1] $41
N002 (  3,  4)              [000040] ------------                 |  \--*  LCL_FLD   int    V00 loc0         u:6[+4] Fseq[i2] $43
N004 (  3,  2)              [000057] ------------                 \--*  LCL_VAR   int    V03 cse0         u:1 $44


*************** Finishing PHASE Optimize Valnum CSEs

*************** Starting PHASE Assertion prop
*************** In optAssertionPropMain()
Blocks/Trees at start of phase

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..038)-> BB03 ( cond )                     i label target hascall gcsafe
BB02 [0001]  1       BB01                  0.50    [038..03B)        (return)                     i gcsafe
BB03 [0002]  1       BB01                  0.50    [03B..050)        (return)                     i label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..038) -> BB03 (cond), preds={} succs={BB02,BB03}

***** BB01
STMT00000 (IL 0x000...0x003)
N003 (  5,  6) [000004] -A------R---              *  ASG       int    $41
N002 (  3,  4) [000003] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:1->2[+0] Fseq[i1] $100
N001 (  1,  1) [000002] ------------              \--*  CNS_INT   int    1 $41

***** BB01
STMT00001 (IL 0x008...0x00B)
N003 (  5,  6) [000009] -A------R---              *  ASG       int    $43
N002 (  3,  4) [000008] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:2->3[+4] Fseq[i2] $101
N001 (  1,  1) [000007] ------------              \--*  CNS_INT   int    2 $43

***** BB01
STMT00002 (IL 0x010...0x013)
N003 (  5,  6) [000014] -A------R---              *  ASG       int    $44
N002 (  3,  4) [000013] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:3->4[+8] Fseq[i3] $102
N001 (  1,  1) [000012] ------------              \--*  CNS_INT   int    3 $44

***** BB01
STMT00003 (IL 0x018...0x01B)
N003 (  5,  6) [000019] -A------R---              *  ASG       int    $45
N002 (  3,  4) [000018] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:4->5[+12] Fseq[i4] $103
N001 (  1,  1) [000017] ------------              \--*  CNS_INT   int    4 $45

***** BB01
STMT00004 (IL 0x020...0x023)
N003 (  5,  6) [000024] -A------R---              *  ASG       int    $46
N002 (  3,  4) [000023] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:5->6[+16] Fseq[i5] $104
N001 (  1,  1) [000022] ------------              \--*  CNS_INT   int    5 $46

***** BB01
STMT00005 (IL 0x028...0x036)
N006 ( 27, 14) [000026] -ACXG-------              *  CALL      void   Runtime_49101.Test $VN.Void
N003 (  7,  5) [000050] -A------R-L- arg0 SETUP   +--*  ASG       struct (copy) $VN.Void
N002 (  3,  2) [000049] D------N----              |  +--*  LCL_VAR   struct<S, 20>(AX) V02 tmp1
N001 (  3,  2) [000025] -------N----              |  \--*  LCL_VAR   struct<S, 20> V00 loc0         u:6 $104
N005 (  3,  3) [000052] ------------ arg0 in rcx  \--*  ADDR      byref  $200
N004 (  3,  2) [000051] -------N----                 \--*  LCL_VAR   struct<S, 20>(AX) V02 tmp1          $1c0

***** BB01
STMT00006 (IL 0x02E...  ???)
N008 ( 14, 13) [000034] -A----------              *  JTRUE     void
N007 ( 12, 11) [000033] NA-----N-U--              \--*  NE        int    $41
N005 ( 10,  9) [000056] -A----------                 +--*  COMMA     int    $44
N003 (  7,  7) [000054] -A------R---                 |  +--*  ASG       int    $VN.Void
N002 (  3,  2) [000053] D------N----                 |  |  +--*  LCL_VAR   int    V03 cse0         d:1 $44
N001 (  3,  4) [000031] ------------                 |  |  \--*  LCL_FLD   int    V00 loc0         u:6[+8] Fseq[i3] $44
N004 (  3,  2) [000055] ------------                 |  \--*  LCL_VAR   int    V03 cse0         u:1 $44
N006 (  1,  1) [000032] ------------                 \--*  CNS_INT   int    10 $47

------------ BB02 [038..03B) (return), preds={BB01} succs={}

***** BB02
STMT00008 (IL 0x038...0x03A)
N002 (  2,  2) [000048] ------------              *  RETURN    int    $281
N001 (  1,  1) [000047] ------------              \--*  CNS_INT   int    10 $47

------------ BB03 [03B..050) (return), preds={BB01} succs={}

***** BB03
STMT00007 (IL 0x03B...0x04F)
N006 ( 12, 13) [000046] ------------              *  RETURN    int    $280
N005 ( 11, 12) [000045] ------------              \--*  ADD       int    $48
N003 (  7,  9) [000041] ------------                 +--*  ADD       int    $44
N001 (  3,  4) [000037] ------------                 |  +--*  LCL_FLD   int    V00 loc0         u:6[+0] Fseq[i1] $41
N002 (  3,  4) [000040] ------------                 |  \--*  LCL_FLD   int    V00 loc0         u:6[+4] Fseq[i2] $43
N004 (  3,  2) [000057] ------------                 \--*  LCL_VAR   int    V03 cse0         u:1 $44

-------------------------------------------------------------------------------------------------------------------
Compiler::optVNConstantPropOnJTrue morphed tree:
N003 (  7,  7) [000054] -A------R---              *  ASG       int    $VN.Void
N002 (  3,  2) [000053] D------N----              +--*  LCL_VAR   int    V03 cse0         d:1 $44
N001 (  3,  4) [000031] ------------              \--*  LCL_FLD   int    V00 loc0         u:6[+8] Fseq[i3] $44

After constant propagation on [000034]:
STMT00006 (IL 0x02E...  ???)
N008 ( 14, 13) [000034] -A----------              *  JTRUE     void
N007 ( 12, 11) [000033] NA-----N-U--              \--*  EQ        int    $41
               [000058] ------------                 +--*  CNS_INT   int    0 $42
               [000059] ------------                 \--*  CNS_INT   int    0 $42

Folding operator with constant nodes into a constant:
N007 ( 12, 11) [000033] N------N-U--              *  EQ        int    $41
               [000058] ------------              +--*  CNS_INT   int    0 $42
               [000059] ------------              \--*  CNS_INT   int    0 $42
Bashed to int constant:
N007 ( 12, 11) [000033] ------------              *  CNS_INT   int    1 $41

Removing statement STMT00006 (IL 0x02E...  ???)
N008 ( 14, 13) [000034] ------------              *  JTRUE     void
N007 ( 12, 11) [000033] ------------              \--*  CNS_INT   int    1 $41
 in BB01 as useless:


Conditional folded at BB01
BB01 becomes a BBJ_ALWAYS to BB03
optVNAssertionPropCurStmt removed tree:
N008 ( 14, 13) [000034] ------------              *  JTRUE     void
N007 ( 12, 11) [000033] ------------              \--*  CNS_INT   int    1 $41

After constant propagation on [000045]:
STMT00007 (IL 0x03B...0x04F)
N006 ( 12, 13) [000046] ------------              *  RETURN    int    $280
               [000060] ------------              \--*  CNS_INT   int    6 $48
optVNAssertionPropCurStmt morphed tree:
N002 (  2,  2) [000046] ------------              *  RETURN    int    $280
N001 (  1,  1) [000060] ------------              \--*  CNS_INT   int    6 $48


*************** Finishing PHASE Assertion prop

*************** Starting PHASE Optimize index checks
*************** In OptimizeRangeChecks()
Blocks/trees before phase

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..038)-> BB03 (always)                     i label target hascall gcsafe
BB02 [0001]  0                             0.50    [038..03B)        (return)                     i gcsafe
BB03 [0002]  1       BB01                  0.50    [03B..050)        (return)                     i label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..038) -> BB03 (always), preds={} succs={BB03}

***** BB01
STMT00000 (IL 0x000...0x003)
N003 (  5,  6) [000004] -A------R---              *  ASG       int    $41
N002 (  3,  4) [000003] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:1->2[+0] Fseq[i1] $100
N001 (  1,  1) [000002] ------------              \--*  CNS_INT   int    1 $41

***** BB01
STMT00001 (IL 0x008...0x00B)
N003 (  5,  6) [000009] -A------R---              *  ASG       int    $43
N002 (  3,  4) [000008] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:2->3[+4] Fseq[i2] $101
N001 (  1,  1) [000007] ------------              \--*  CNS_INT   int    2 $43

***** BB01
STMT00002 (IL 0x010...0x013)
N003 (  5,  6) [000014] -A------R---              *  ASG       int    $44
N002 (  3,  4) [000013] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:3->4[+8] Fseq[i3] $102
N001 (  1,  1) [000012] ------------              \--*  CNS_INT   int    3 $44

***** BB01
STMT00003 (IL 0x018...0x01B)
N003 (  5,  6) [000019] -A------R---              *  ASG       int    $45
N002 (  3,  4) [000018] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:4->5[+12] Fseq[i4] $103
N001 (  1,  1) [000017] ------------              \--*  CNS_INT   int    4 $45

***** BB01
STMT00004 (IL 0x020...0x023)
N003 (  5,  6) [000024] -A------R---              *  ASG       int    $46
N002 (  3,  4) [000023] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:5->6[+16] Fseq[i5] $104
N001 (  1,  1) [000022] ------------              \--*  CNS_INT   int    5 $46

***** BB01
STMT00005 (IL 0x028...0x036)
N006 ( 27, 14) [000026] -ACXG-------              *  CALL      void   Runtime_49101.Test $VN.Void
N003 (  7,  5) [000050] -A------R-L- arg0 SETUP   +--*  ASG       struct (copy) $VN.Void
N002 (  3,  2) [000049] D------N----              |  +--*  LCL_VAR   struct<S, 20>(AX) V02 tmp1
N001 (  3,  2) [000025] -------N----              |  \--*  LCL_VAR   struct<S, 20> V00 loc0         u:6 $104
N005 (  3,  3) [000052] ------------ arg0 in rcx  \--*  ADDR      byref  $200
N004 (  3,  2) [000051] -------N----                 \--*  LCL_VAR   struct<S, 20>(AX) V02 tmp1          $1c0

***** BB01
STMT00009 (IL   ???...  ???)
N003 (  7,  7) [000054] -A------R---              *  ASG       int    $VN.Void
N002 (  3,  2) [000053] D------N----              +--*  LCL_VAR   int    V03 cse0         d:1 $44
N001 (  3,  4) [000031] ------------              \--*  LCL_FLD   int    V00 loc0         u:6[+8] Fseq[i3] $44

------------ BB02 [038..03B) (return), preds={} succs={}

***** BB02
STMT00008 (IL 0x038...0x03A)
N002 (  2,  2) [000048] ------------              *  RETURN    int    $281
N001 (  1,  1) [000047] ------------              \--*  CNS_INT   int    10 $47

------------ BB03 [03B..050) (return), preds={BB01} succs={}

***** BB03
STMT00007 (IL 0x03B...0x04F)
N002 (  2,  2) [000046] ------------              *  RETURN    int    $280
N001 (  1,  1) [000060] ------------              \--*  CNS_INT   int    6 $48

-------------------------------------------------------------------------------------------------------------------

*************** Finishing PHASE Optimize index checks

*************** Starting PHASE Update flow graph opt pass

*************** In fgUpdateFlowGraph()
Before updating the flow graph:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..038)-> BB03 (always)                     i label target hascall gcsafe
BB02 [0001]  0                             0.50    [038..03B)        (return)                     i gcsafe
BB03 [0002]  1       BB01                  0.50    [03B..050)        (return)                     i label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------

fgRemoveBlock BB02

Removing unreachable BB02

Removing statement STMT00008 (IL 0x038...0x03A)
N002 (  2,  2) [000048] ------------              *  RETURN    int    $281
N001 (  1,  1) [000047] ------------              \--*  CNS_INT   int    10 $47
 in BB02 as useless:

BB02 becomes empty

Compacting blocks BB01 and BB03:
*************** In fgDebugCheckBBlist

After updating the flow graph:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..050)        (return)                     i label target hascall gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty
*************** In fgDebugCheckBBlist

*************** Finishing PHASE Update flow graph opt pass

*************** Starting PHASE Compute edge weights (2, false)
 -- not optimizing or no profile data, so not computing edge weights

*************** Finishing PHASE Compute edge weights (2, false)

*************** Starting PHASE Insert GC Polls

*************** Finishing PHASE Insert GC Polls [no changes]

*************** Starting PHASE Determine first cold block

*************** In fgDetermineFirstColdBlock()
No procedure splitting will be done for this method

*************** Finishing PHASE Determine first cold block
Trees before Rationalize IR

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..050)        (return)                     i label target hascall gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..050) (return), preds={} succs={}

***** BB01
STMT00000 (IL 0x000...0x003)
N003 (  5,  6) [000004] -A------R---              *  ASG       int    $41
N002 (  3,  4) [000003] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:1->2[+0] Fseq[i1] $100
N001 (  1,  1) [000002] ------------              \--*  CNS_INT   int    1 $41

***** BB01
STMT00001 (IL 0x008...0x00B)
N003 (  5,  6) [000009] -A------R---              *  ASG       int    $43
N002 (  3,  4) [000008] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:2->3[+4] Fseq[i2] $101
N001 (  1,  1) [000007] ------------              \--*  CNS_INT   int    2 $43

***** BB01
STMT00002 (IL 0x010...0x013)
N003 (  5,  6) [000014] -A------R---              *  ASG       int    $44
N002 (  3,  4) [000013] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:3->4[+8] Fseq[i3] $102
N001 (  1,  1) [000012] ------------              \--*  CNS_INT   int    3 $44

***** BB01
STMT00003 (IL 0x018...0x01B)
N003 (  5,  6) [000019] -A------R---              *  ASG       int    $45
N002 (  3,  4) [000018] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:4->5[+12] Fseq[i4] $103
N001 (  1,  1) [000017] ------------              \--*  CNS_INT   int    4 $45

***** BB01
STMT00004 (IL 0x020...0x023)
N003 (  5,  6) [000024] -A------R---              *  ASG       int    $46
N002 (  3,  4) [000023] U------N----              +--*  LCL_FLD   int    V00 loc0         ud:5->6[+16] Fseq[i5] $104
N001 (  1,  1) [000022] ------------              \--*  CNS_INT   int    5 $46

***** BB01
STMT00005 (IL 0x028...0x036)
N006 ( 27, 14) [000026] -ACXG-------              *  CALL      void   Runtime_49101.Test $VN.Void
N003 (  7,  5) [000050] -A------R-L- arg0 SETUP   +--*  ASG       struct (copy) $VN.Void
N002 (  3,  2) [000049] D------N----              |  +--*  LCL_VAR   struct<S, 20>(AX) V02 tmp1
N001 (  3,  2) [000025] -------N----              |  \--*  LCL_VAR   struct<S, 20> V00 loc0         u:6 $104
N005 (  3,  3) [000052] ------------ arg0 in rcx  \--*  ADDR      byref  $200
N004 (  3,  2) [000051] -------N----                 \--*  LCL_VAR   struct<S, 20>(AX) V02 tmp1          $1c0

***** BB01
STMT00009 (IL   ???...  ???)
N003 (  7,  7) [000054] -A------R---              *  ASG       int    $VN.Void
N002 (  3,  2) [000053] D------N----              +--*  LCL_VAR   int    V03 cse0         d:1 $44
N001 (  3,  4) [000031] ------------              \--*  LCL_FLD   int    V00 loc0         u:6[+8] Fseq[i3] $44

***** BB01
STMT00007 (IL 0x03B...0x04F)
N002 (  2,  2) [000046] ------------              *  RETURN    int    $280
N001 (  1,  1) [000060] ------------              \--*  CNS_INT   int    6 $48

-------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Rationalize IR
rewriting asg(LCL_FLD, X) to STORE_LCL_FLD(X)
N003 (  5,  6) [000004] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:1->0[+0] Fseq[i1]

rewriting asg(LCL_FLD, X) to STORE_LCL_FLD(X)
N003 (  5,  6) [000009] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:2->0[+4] Fseq[i2]

rewriting asg(LCL_FLD, X) to STORE_LCL_FLD(X)
N003 (  5,  6) [000014] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:3->0[+8] Fseq[i3]

rewriting asg(LCL_FLD, X) to STORE_LCL_FLD(X)
N003 (  5,  6) [000019] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:4->0[+12] Fseq[i4]

rewriting asg(LCL_FLD, X) to STORE_LCL_FLD(X)
N003 (  5,  6) [000024] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:5->0[+16] Fseq[i5]

rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 (  7,  5) [000050] DA--------L-              *  STORE_LCL_VAR struct<S, 20>(AX) V02 tmp1

Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR:
N004 (  3,  2) [000051] -------N----        t51 =    LCL_VAR_ADDR byref  V02 tmp1

rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 (  7,  7) [000054] DA----------              *  STORE_LCL_VAR int    V03 cse0         d:1


*************** Finishing PHASE Rationalize IR
Trees after Rationalize IR

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..050)        (return)                     i label target hascall gcsafe LIR
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..050) (return), preds={} succs={}
               [000061] ------------                 IL_OFFSET void   IL offset: 0x0
N001 (  1,  1) [000002] ------------         t2 =    CNS_INT   int    1 $41
                                                  /--*  t2     int
N003 (  5,  6) [000004] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:1->0[+0] Fseq[i1]
               [000062] ------------                 IL_OFFSET void   IL offset: 0x8
N001 (  1,  1) [000007] ------------         t7 =    CNS_INT   int    2 $43
                                                  /--*  t7     int
N003 (  5,  6) [000009] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:2->0[+4] Fseq[i2]
               [000063] ------------                 IL_OFFSET void   IL offset: 0x10
N001 (  1,  1) [000012] ------------        t12 =    CNS_INT   int    3 $44
                                                  /--*  t12    int
N003 (  5,  6) [000014] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:3->0[+8] Fseq[i3]
               [000064] ------------                 IL_OFFSET void   IL offset: 0x18
N001 (  1,  1) [000017] ------------        t17 =    CNS_INT   int    4 $45
                                                  /--*  t17    int
N003 (  5,  6) [000019] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:4->0[+12] Fseq[i4]
               [000065] ------------                 IL_OFFSET void   IL offset: 0x20
N001 (  1,  1) [000022] ------------        t22 =    CNS_INT   int    5 $46
                                                  /--*  t22    int
N003 (  5,  6) [000024] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:5->0[+16] Fseq[i5]
               [000066] ------------                 IL_OFFSET void   IL offset: 0x28
N001 (  3,  2) [000025] -------N----        t25 =    LCL_VAR   struct<S, 20> V00 loc0         u:6 $104
                                                  /--*  t25    struct
N003 (  7,  5) [000050] DA--------L-              *  STORE_LCL_VAR struct<S, 20>(AX) V02 tmp1
N004 (  3,  2) [000051] -------N----        t51 =    LCL_VAR_ADDR byref  V02 tmp1
                                                  /--*  t51    byref  arg0 in rcx
N006 ( 27, 14) [000026] --CXG-------              *  CALL      void   Runtime_49101.Test $VN.Void
N001 (  3,  4) [000031] ------------        t31 =    LCL_FLD   int    V00 loc0         u:6[+8] Fseq[i3] $44
                                                  /--*  t31    int
N003 (  7,  7) [000054] DA----------              *  STORE_LCL_VAR int    V03 cse0         d:1
               [000067] ------------                 IL_OFFSET void   IL offset: 0x3b
N001 (  1,  1) [000060] ------------        t60 =    CNS_INT   int    6 $48
                                                  /--*  t60    int
N002 (  2,  2) [000046] ------------              *  RETURN    int    $280

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist

*************** Starting PHASE Do 'simple' lowering
Bumping outgoingArgSpaceSize to 32 for call [000026]

*************** Finishing PHASE Do 'simple' lowering
*************** In fgDebugCheckBBlist
Trees before Lowering nodeinfo

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..050)        (return)                     i label target hascall gcsafe LIR
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..050) (return), preds={} succs={}
               [000061] ------------                 IL_OFFSET void   IL offset: 0x0
N001 (  1,  1) [000002] ------------         t2 =    CNS_INT   int    1 $41
                                                  /--*  t2     int
N003 (  5,  6) [000004] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:1->0[+0] Fseq[i1]
               [000062] ------------                 IL_OFFSET void   IL offset: 0x8
N001 (  1,  1) [000007] ------------         t7 =    CNS_INT   int    2 $43
                                                  /--*  t7     int
N003 (  5,  6) [000009] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:2->0[+4] Fseq[i2]
               [000063] ------------                 IL_OFFSET void   IL offset: 0x10
N001 (  1,  1) [000012] ------------        t12 =    CNS_INT   int    3 $44
                                                  /--*  t12    int
N003 (  5,  6) [000014] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:3->0[+8] Fseq[i3]
               [000064] ------------                 IL_OFFSET void   IL offset: 0x18
N001 (  1,  1) [000017] ------------        t17 =    CNS_INT   int    4 $45
                                                  /--*  t17    int
N003 (  5,  6) [000019] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:4->0[+12] Fseq[i4]
               [000065] ------------                 IL_OFFSET void   IL offset: 0x20
N001 (  1,  1) [000022] ------------        t22 =    CNS_INT   int    5 $46
                                                  /--*  t22    int
N003 (  5,  6) [000024] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:5->0[+16] Fseq[i5]
               [000066] ------------                 IL_OFFSET void   IL offset: 0x28
N001 (  3,  2) [000025] -------N----        t25 =    LCL_VAR   struct<S, 20> V00 loc0         u:6 $104
                                                  /--*  t25    struct
N003 (  7,  5) [000050] DA--------L-              *  STORE_LCL_VAR struct<S, 20>(AX) V02 tmp1
N004 (  3,  2) [000051] -------N----        t51 =    LCL_VAR_ADDR byref  V02 tmp1
                                                  /--*  t51    byref  arg0 in rcx
N006 ( 27, 14) [000026] --CXG-------              *  CALL      void   Runtime_49101.Test $VN.Void
N001 (  3,  4) [000031] ------------        t31 =    LCL_FLD   int    V00 loc0         u:6[+8] Fseq[i3] $44
                                                  /--*  t31    int
N003 (  7,  7) [000054] DA----------              *  STORE_LCL_VAR int    V03 cse0         d:1
               [000067] ------------                 IL_OFFSET void   IL offset: 0x3b
N001 (  1,  1) [000060] ------------        t60 =    CNS_INT   int    6 $48
                                                  /--*  t60    int
N002 (  2,  2) [000046] ------------              *  RETURN    int    $280

-------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Lowering nodeinfo
lowering store lcl var/field (before):
N001 (  1,  1) [000002] ------------         t2 =    CNS_INT   int    1 $41
                                                  /--*  t2     int
N003 (  5,  6) [000004] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:1->0[+0] Fseq[i1]

lowering store lcl var/field (after):
N001 (  1,  1) [000002] -c----------         t2 =    CNS_INT   int    1 $41
                                                  /--*  t2     int
N003 (  5,  6) [000004] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:1->0[+0] Fseq[i1]

lowering store lcl var/field (before):
N001 (  1,  1) [000007] ------------         t7 =    CNS_INT   int    2 $43
                                                  /--*  t7     int
N003 (  5,  6) [000009] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:2->0[+4] Fseq[i2]

lowering store lcl var/field (after):
N001 (  1,  1) [000007] -c----------         t7 =    CNS_INT   int    2 $43
                                                  /--*  t7     int
N003 (  5,  6) [000009] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:2->0[+4] Fseq[i2]

lowering store lcl var/field (before):
N001 (  1,  1) [000012] ------------        t12 =    CNS_INT   int    3 $44
                                                  /--*  t12    int
N003 (  5,  6) [000014] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:3->0[+8] Fseq[i3]

lowering store lcl var/field (after):
N001 (  1,  1) [000012] -c----------        t12 =    CNS_INT   int    3 $44
                                                  /--*  t12    int
N003 (  5,  6) [000014] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:3->0[+8] Fseq[i3]

lowering store lcl var/field (before):
N001 (  1,  1) [000017] ------------        t17 =    CNS_INT   int    4 $45
                                                  /--*  t17    int
N003 (  5,  6) [000019] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:4->0[+12] Fseq[i4]

lowering store lcl var/field (after):
N001 (  1,  1) [000017] -c----------        t17 =    CNS_INT   int    4 $45
                                                  /--*  t17    int
N003 (  5,  6) [000019] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:4->0[+12] Fseq[i4]

lowering store lcl var/field (before):
N001 (  1,  1) [000022] ------------        t22 =    CNS_INT   int    5 $46
                                                  /--*  t22    int
N003 (  5,  6) [000024] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:5->0[+16] Fseq[i5]

lowering store lcl var/field (after):
N001 (  1,  1) [000022] -c----------        t22 =    CNS_INT   int    5 $46
                                                  /--*  t22    int
N003 (  5,  6) [000024] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:5->0[+16] Fseq[i5]

lowering store lcl var/field (before):
N001 (  3,  2) [000025] -------N----        t25 =    LCL_VAR   struct<S, 20> V00 loc0         u:6 $104
                                                  /--*  t25    struct
N003 (  7,  5) [000050] DA--------L-              *  STORE_LCL_VAR struct<S, 20>(AX) V02 tmp1

lowering call (before):
N001 (  3,  2) [000025] -c-----N----        t25 =    LCL_VAR   struct<S, 20> V00 loc0         u:6 $104
               [000068] Dc-----N----        t68 =    LCL_VAR_ADDR byref  V02 tmp1
                                                  /--*  t68    byref
                                                  +--*  t25    struct
N003 (  7,  5) [000050] sA--------L-              *  STORE_BLK struct<S, 20> (copy) (Unroll)
N004 (  3,  2) [000051] -------N----        t51 =    LCL_VAR_ADDR byref  V02 tmp1
                                                  /--*  t51    byref  arg0 in rcx
N006 ( 27, 14) [000026] --CXG-------              *  CALL      void   Runtime_49101.Test $VN.Void

objp:
======

args:
======
lowering arg : N003 (  7,  5) [000050] sA--------L-              *  STORE_BLK struct<S, 20> (copy) (Unroll)

late:
======
lowering arg : N004 (  3,  2) [000051] -------N----              *  LCL_VAR_ADDR byref  V02 tmp1
new node is :                [000069] ------------              *  PUTARG_REG byref  REG rcx

lowering call (after):
N001 (  3,  2) [000025] -c-----N----        t25 =    LCL_VAR   struct<S, 20> V00 loc0         u:6 $104
               [000068] Dc-----N----        t68 =    LCL_VAR_ADDR byref  V02 tmp1
                                                  /--*  t68    byref
                                                  +--*  t25    struct
N003 (  7,  5) [000050] sA--------L-              *  STORE_BLK struct<S, 20> (copy) (Unroll)
N004 (  3,  2) [000051] -------N----        t51 =    LCL_VAR_ADDR byref  V02 tmp1
                                                  /--*  t51    byref
               [000069] ------------        t69 = *  PUTARG_REG byref  REG rcx
                                                  /--*  t69    byref  arg0 in rcx
N006 ( 27, 14) [000026] --CXG-------              *  CALL      void   Runtime_49101.Test $VN.Void

lowering store lcl var/field (before):
N001 (  3,  4) [000031] ------------        t31 =    LCL_FLD   int    V00 loc0         u:6[+8] Fseq[i3] $44
                                                  /--*  t31    int
N003 (  7,  7) [000054] DA----------              *  STORE_LCL_VAR int    V03 cse0         d:1

lowering store lcl var/field (after):
N001 (  3,  4) [000031] ------------        t31 =    LCL_FLD   int    V00 loc0         u:6[+8] Fseq[i3] $44
                                                  /--*  t31    int
N003 (  7,  7) [000054] DA----------              *  STORE_LCL_VAR int    V03 cse0         d:1

lowering GT_RETURN
N002 (  2,  2) [000046] ------------              *  RETURN    int    $280
============Lower has completed modifying nodes.

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..050)        (return)                     i label target hascall gcsafe LIR
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..050) (return), preds={} succs={}
               [000061] ------------                 IL_OFFSET void   IL offset: 0x0
N001 (  1,  1) [000002] -c----------         t2 =    CNS_INT   int    1 $41
                                                  /--*  t2     int
N003 (  5,  6) [000004] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:1->0[+0] Fseq[i1]
               [000062] ------------                 IL_OFFSET void   IL offset: 0x8
N001 (  1,  1) [000007] -c----------         t7 =    CNS_INT   int    2 $43
                                                  /--*  t7     int
N003 (  5,  6) [000009] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:2->0[+4] Fseq[i2]
               [000063] ------------                 IL_OFFSET void   IL offset: 0x10
N001 (  1,  1) [000012] -c----------        t12 =    CNS_INT   int    3 $44
                                                  /--*  t12    int
N003 (  5,  6) [000014] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:3->0[+8] Fseq[i3]
               [000064] ------------                 IL_OFFSET void   IL offset: 0x18
N001 (  1,  1) [000017] -c----------        t17 =    CNS_INT   int    4 $45
                                                  /--*  t17    int
N003 (  5,  6) [000019] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:4->0[+12] Fseq[i4]
               [000065] ------------                 IL_OFFSET void   IL offset: 0x20
N001 (  1,  1) [000022] -c----------        t22 =    CNS_INT   int    5 $46
                                                  /--*  t22    int
N003 (  5,  6) [000024] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:5->0[+16] Fseq[i5]
               [000066] ------------                 IL_OFFSET void   IL offset: 0x28
N001 (  3,  2) [000025] -c-----N----        t25 =    LCL_VAR   struct<S, 20> V00 loc0         u:6 $104
               [000068] Dc-----N----        t68 =    LCL_VAR_ADDR byref  V02 tmp1
                                                  /--*  t68    byref
                                                  +--*  t25    struct
N003 (  7,  5) [000050] sA--------L-              *  STORE_BLK struct<S, 20> (copy) (Unroll)
N004 (  3,  2) [000051] -------N----        t51 =    LCL_VAR_ADDR byref  V02 tmp1
                                                  /--*  t51    byref
               [000069] ------------        t69 = *  PUTARG_REG byref  REG rcx
                                                  /--*  t69    byref  arg0 in rcx
N006 ( 27, 14) [000026] --CXG-------              *  CALL      void   Runtime_49101.Test $VN.Void
N001 (  3,  4) [000031] ------------        t31 =    LCL_FLD   int    V00 loc0         u:6[+8] Fseq[i3] $44
                                                  /--*  t31    int
N003 (  7,  7) [000054] DA----------              *  STORE_LCL_VAR int    V03 cse0         d:1
               [000067] ------------                 IL_OFFSET void   IL offset: 0x3b
N001 (  1,  1) [000060] ------------        t60 =    CNS_INT   int    6 $48
                                                  /--*  t60    int
N002 (  2,  2) [000046] ------------              *  RETURN    int    $280

-------------------------------------------------------------------------------------------------------------------

*** lvaComputeRefCounts ***

*** lvaComputeRefCounts -- explicit counts ***
New refCnts for V00: refCnt =  1, refCntWtd = 1
New refCnts for V00: refCnt =  2, refCntWtd = 2
New refCnts for V00: refCnt =  3, refCntWtd = 3
New refCnts for V00: refCnt =  4, refCntWtd = 4
New refCnts for V00: refCnt =  5, refCntWtd = 5
New refCnts for V00: refCnt =  6, refCntWtd = 6
New refCnts for V02: refCnt =  1, refCntWtd = 2
New refCnts for V02: refCnt =  2, refCntWtd = 4
New refCnts for V00: refCnt =  7, refCntWtd = 7
New refCnts for V03: refCnt =  1, refCntWtd = 1

*** lvaComputeRefCounts -- implicit counts ***
*************** In fgLocalVarLiveness()
; Initial local variable assignments
;
;  V00 loc0           struct <S, 20> do-not-enreg[SFB] must-init ld-addr-op
;  V01 OutArgs        lclBlk <32>  "OutgoingArgSpace"
;  V02 tmp1           struct <S, 20> do-not-enreg[XSB] addr-exposed "by-value struct argument"
;  V03 cse0              int  "CSE - aggressive"
In fgLocalVarLivenessInit

Local V00 should not be enregistered because: it is a struct
Tracked variable (2 out of 4) table:
V00 loc0          [struct]: refCnt =    7, refCntWtd =   7
V03 cse0          [   int]: refCnt =    1, refCntWtd =   1

*************** In fgPerBlockLocalVarLiveness()
BB01 USE(1)={V00    } + ByrefExposed + GcHeap
     DEF(2)={V00 V03} + ByrefExposed* + GcHeap*

** Memory liveness computed, GcHeap states and ByrefExposed states diverge
*************** In fgInterBlockLocalVarLiveness()

BB liveness after fgLiveVarAnalysis():

BB01 IN (1)={V00} + ByrefExposed + GcHeap
     OUT(0)={   }

Removing dead store:
N003 (  7,  7) [000054] DA----------              *  STORE_LCL_VAR int    V03 cse0         d:1 (last use)
Removing dead LclVar use:
N001 (  3,  4) [000031] ------------              *  LCL_FLD   int    V00 loc0         u:6[+8] Fseq[i3] $44

*************** In fgUpdateFlowGraph()
Before updating the flow graph:

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..050)        (return)                     i label target hascall gcsafe LIR
-----------------------------------------------------------------------------------------------------------------------------------------

*************** In fgDebugCheckBBlist

*** lvaComputeRefCounts ***

*** lvaComputeRefCounts -- explicit counts ***
New refCnts for V00: refCnt =  1, refCntWtd = 1
New refCnts for V00: refCnt =  2, refCntWtd = 2
New refCnts for V00: refCnt =  3, refCntWtd = 3
New refCnts for V00: refCnt =  4, refCntWtd = 4
New refCnts for V00: refCnt =  5, refCntWtd = 5
New refCnts for V00: refCnt =  6, refCntWtd = 6
New refCnts for V02: refCnt =  1, refCntWtd = 2
New refCnts for V02: refCnt =  2, refCntWtd = 4

*** lvaComputeRefCounts -- implicit counts ***

*************** Finishing PHASE Lowering nodeinfo
Trees after Lowering nodeinfo

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..050)        (return)                     i label target hascall gcsafe LIR
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..050) (return), preds={} succs={}
               [000061] ------------                 IL_OFFSET void   IL offset: 0x0
N001 (  1,  1) [000002] -c----------         t2 =    CNS_INT   int    1 $41
                                                  /--*  t2     int
N003 (  5,  6) [000004] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:1->0[+0] Fseq[i1]
               [000062] ------------                 IL_OFFSET void   IL offset: 0x8
N001 (  1,  1) [000007] -c----------         t7 =    CNS_INT   int    2 $43
                                                  /--*  t7     int
N003 (  5,  6) [000009] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:2->0[+4] Fseq[i2]
               [000063] ------------                 IL_OFFSET void   IL offset: 0x10
N001 (  1,  1) [000012] -c----------        t12 =    CNS_INT   int    3 $44
                                                  /--*  t12    int
N003 (  5,  6) [000014] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:3->0[+8] Fseq[i3]
               [000064] ------------                 IL_OFFSET void   IL offset: 0x18
N001 (  1,  1) [000017] -c----------        t17 =    CNS_INT   int    4 $45
                                                  /--*  t17    int
N003 (  5,  6) [000019] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:4->0[+12] Fseq[i4]
               [000065] ------------                 IL_OFFSET void   IL offset: 0x20
N001 (  1,  1) [000022] -c----------        t22 =    CNS_INT   int    5 $46
                                                  /--*  t22    int
N003 (  5,  6) [000024] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:5->0[+16] Fseq[i5]
               [000066] ------------                 IL_OFFSET void   IL offset: 0x28
N001 (  3,  2) [000025] -c-----N----        t25 =    LCL_VAR   struct<S, 20> V00 loc0         u:6 (last use) $104
               [000068] Dc-----N----        t68 =    LCL_VAR_ADDR byref  V02 tmp1
                                                  /--*  t68    byref
                                                  +--*  t25    struct
N003 (  7,  5) [000050] sA--------L-              *  STORE_BLK struct<S, 20> (copy) (Unroll)
N004 (  3,  2) [000051] -------N----        t51 =    LCL_VAR_ADDR byref  V02 tmp1
                                                  /--*  t51    byref
               [000069] ------------        t69 = *  PUTARG_REG byref  REG rcx
                                                  /--*  t69    byref  arg0 in rcx
N006 ( 27, 14) [000026] --CXG-------              *  CALL      void   Runtime_49101.Test $VN.Void
               [000067] ------------                 IL_OFFSET void   IL offset: 0x3b
N001 (  1,  1) [000060] ------------        t60 =    CNS_INT   int    6 $48
                                                  /--*  t60    int
N002 (  2,  2) [000046] ------------              *  RETURN    int    $280

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Trees before Calculate stack level slots

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..050)        (return)                     i label target hascall gcsafe LIR
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..050) (return), preds={} succs={}
               [000061] ------------                 IL_OFFSET void   IL offset: 0x0
N001 (  1,  1) [000002] -c----------         t2 =    CNS_INT   int    1 $41
                                                  /--*  t2     int
N003 (  5,  6) [000004] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:1->0[+0] Fseq[i1]
               [000062] ------------                 IL_OFFSET void   IL offset: 0x8
N001 (  1,  1) [000007] -c----------         t7 =    CNS_INT   int    2 $43
                                                  /--*  t7     int
N003 (  5,  6) [000009] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:2->0[+4] Fseq[i2]
               [000063] ------------                 IL_OFFSET void   IL offset: 0x10
N001 (  1,  1) [000012] -c----------        t12 =    CNS_INT   int    3 $44
                                                  /--*  t12    int
N003 (  5,  6) [000014] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:3->0[+8] Fseq[i3]
               [000064] ------------                 IL_OFFSET void   IL offset: 0x18
N001 (  1,  1) [000017] -c----------        t17 =    CNS_INT   int    4 $45
                                                  /--*  t17    int
N003 (  5,  6) [000019] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:4->0[+12] Fseq[i4]
               [000065] ------------                 IL_OFFSET void   IL offset: 0x20
N001 (  1,  1) [000022] -c----------        t22 =    CNS_INT   int    5 $46
                                                  /--*  t22    int
N003 (  5,  6) [000024] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:5->0[+16] Fseq[i5]
               [000066] ------------                 IL_OFFSET void   IL offset: 0x28
N001 (  3,  2) [000025] -c-----N----        t25 =    LCL_VAR   struct<S, 20> V00 loc0         u:6 (last use) $104
               [000068] Dc-----N----        t68 =    LCL_VAR_ADDR byref  V02 tmp1
                                                  /--*  t68    byref
                                                  +--*  t25    struct
N003 (  7,  5) [000050] sA--------L-              *  STORE_BLK struct<S, 20> (copy) (Unroll)
N004 (  3,  2) [000051] -------N----        t51 =    LCL_VAR_ADDR byref  V02 tmp1
                                                  /--*  t51    byref
               [000069] ------------        t69 = *  PUTARG_REG byref  REG rcx
                                                  /--*  t69    byref  arg0 in rcx
N006 ( 27, 14) [000026] --CXG-------              *  CALL      void   Runtime_49101.Test $VN.Void
               [000067] ------------                 IL_OFFSET void   IL offset: 0x3b
N001 (  1,  1) [000060] ------------        t60 =    CNS_INT   int    6 $48
                                                  /--*  t60    int
N002 (  2,  2) [000046] ------------              *  RETURN    int    $280

-------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Calculate stack level slots

*************** Finishing PHASE Calculate stack level slots [no changes]

*************** Starting PHASE Linear scan register alloc
Clearing modified regs.

buildIntervals ========

-----------------
LIVENESS:
-----------------
BB01 use def in out
{V00}
{V00 V03}
{V00}
{}

Local V00 should not be enregistered because: it is a struct

FP callee save candidate vars: None

floatVarCount = 0; hasLoops = 0, singleExit = 1
TUPLE STYLE DUMP BEFORE LSRA
LSRA Block Sequence: BB01(  1   )

BB01 [000..050) (return), preds={} succs={}
=====
  N000.                    IL_OFFSET IL offset: 0x0
  N001.                    CNS_INT   1
  N003.                    V00 MEM
  N000.                    IL_OFFSET IL offset: 0x8
  N001.                    CNS_INT   2
  N003.                    V00 MEM
  N000.                    IL_OFFSET IL offset: 0x10
  N001.                    CNS_INT   3
  N003.                    V00 MEM
  N000.                    IL_OFFSET IL offset: 0x18
  N001.                    CNS_INT   4
  N003.                    V00 MEM
  N000.                    IL_OFFSET IL offset: 0x20
  N001.                    CNS_INT   5
  N003.                    V00 MEM
  N000.                    IL_OFFSET IL offset: 0x28
  N001.                    V00 MEM
  N000.                    LCL_VAR_ADDR V02 tmp1
  N003.                    STORE_BLK
  N004. t51             =  LCL_VAR_ADDR V02 tmp1
  N000. t69             =  PUTARG_REG; t51
  N006.                    CALL     ; t69
  N000.                    IL_OFFSET IL offset: 0x3b
  N001. t60             =  CNS_INT   6
  N002.                    RETURN   ; t60




buildIntervals second part ========

NEW BLOCK BB01
<RefPosition #0   @1   RefTypeBB  BB01 regmask=[] minReg=1>

DefList: {  }
N003 (???,???) [000061] ------------              *  IL_OFFSET void   IL offset: 0x0 REG NA

DefList: {  }
N005 (  1,  1) [000002] -c----------              *  CNS_INT   int    1 REG NA $41
Contained
DefList: {  }
N007 (  5,  6) [000004] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:1->0[+0] Fseq[i1] NA REG NA

DefList: {  }
N009 (???,???) [000062] ------------              *  IL_OFFSET void   IL offset: 0x8 REG NA

DefList: {  }
N011 (  1,  1) [000007] -c----------              *  CNS_INT   int    2 REG NA $43
Contained
DefList: {  }
N013 (  5,  6) [000009] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:2->0[+4] Fseq[i2] NA REG NA

DefList: {  }
N015 (???,???) [000063] ------------              *  IL_OFFSET void   IL offset: 0x10 REG NA

DefList: {  }
N017 (  1,  1) [000012] -c----------              *  CNS_INT   int    3 REG NA $44
Contained
DefList: {  }
N019 (  5,  6) [000014] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:3->0[+8] Fseq[i3] NA REG NA

DefList: {  }
N021 (???,???) [000064] ------------              *  IL_OFFSET void   IL offset: 0x18 REG NA

DefList: {  }
N023 (  1,  1) [000017] -c----------              *  CNS_INT   int    4 REG NA $45
Contained
DefList: {  }
N025 (  5,  6) [000019] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:4->0[+12] Fseq[i4] NA REG NA

DefList: {  }
N027 (???,???) [000065] ------------              *  IL_OFFSET void   IL offset: 0x20 REG NA

DefList: {  }
N029 (  1,  1) [000022] -c----------              *  CNS_INT   int    5 REG NA $46
Contained
DefList: {  }
N031 (  5,  6) [000024] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:5->0[+16] Fseq[i5] NA REG NA

DefList: {  }
N033 (???,???) [000066] ------------              *  IL_OFFSET void   IL offset: 0x28 REG NA

DefList: {  }
N035 (  3,  2) [000025] -c-----N----              *  LCL_VAR   struct<S, 20> V00 loc0         u:6 NA (last use) REG NA $104
Contained
DefList: {  }
N037 (???,???) [000068] Dc-----N----              *  LCL_VAR_ADDR byref  V02 tmp1          NA REG NA
Contained
DefList: {  }
N039 (  7,  5) [000050] sA--------L-              *  STORE_BLK struct<S, 20> (copy) (Unroll) REG NA
Interval  0: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #1   @39  RefTypeDef <Ivl:0 internal> STORE_BLK BB01 regmask=[allInt] minReg=1>
Interval  1: float RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #2   @39  RefTypeDef <Ivl:1 internal> STORE_BLK BB01 regmask=[mm0-mm5] minReg=1>
<RefPosition #3   @39  RefTypeUse <Ivl:0 internal> STORE_BLK BB01 regmask=[allInt] minReg=1 last>
<RefPosition #4   @39  RefTypeUse <Ivl:1 internal> STORE_BLK BB01 regmask=[mm0-mm5] minReg=1 last>

DefList: {  }
N041 (  3,  2) [000051] -------N----              *  LCL_VAR_ADDR byref  V02 tmp1          NA REG NA
Interval  2: byref RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #5   @42  RefTypeDef <Ivl:2> LCL_VAR_ADDR BB01 regmask=[allInt] minReg=1>

DefList: { N041.t51. LCL_VAR_ADDR }
N043 (???,???) [000069] ------------              *  PUTARG_REG byref  REG rcx
<RefPosition #6   @43  RefTypeFixedReg <Reg:rcx>  BB01 regmask=[rcx] minReg=1>
<RefPosition #7   @43  RefTypeUse <Ivl:2>  BB01 regmask=[rcx] minReg=1 last fixed>
Interval  3: byref RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #8   @44  RefTypeFixedReg <Reg:rcx>  BB01 regmask=[rcx] minReg=1>
<RefPosition #9   @44  RefTypeDef <Ivl:3> PUTARG_REG BB01 regmask=[rcx] minReg=1 fixed>

DefList: { N043.t69. PUTARG_REG }
N045 ( 27, 14) [000026] --CXG-------              *  CALL      void   Runtime_49101.Test REG NA $VN.Void
<RefPosition #10  @45  RefTypeFixedReg <Reg:rcx>  BB01 regmask=[rcx] minReg=1>
<RefPosition #11  @45  RefTypeUse <Ivl:3>  BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #12  @46  RefTypeKill <Reg:rax>  BB01 regmask=[rax] minReg=1>
<RefPosition #13  @46  RefTypeKill <Reg:rcx>  BB01 regmask=[rcx] minReg=1>
<RefPosition #14  @46  RefTypeKill <Reg:rdx>  BB01 regmask=[rdx] minReg=1>
<RefPosition #15  @46  RefTypeKill <Reg:r8 >  BB01 regmask=[r8] minReg=1>
<RefPosition #16  @46  RefTypeKill <Reg:r9 >  BB01 regmask=[r9] minReg=1>
<RefPosition #17  @46  RefTypeKill <Reg:r10>  BB01 regmask=[r10] minReg=1>
<RefPosition #18  @46  RefTypeKill <Reg:r11>  BB01 regmask=[r11] minReg=1>

DefList: {  }
N047 (???,???) [000067] ------------              *  IL_OFFSET void   IL offset: 0x3b REG NA

DefList: {  }
N049 (  1,  1) [000060] ------------              *  CNS_INT   int    6 REG NA $48
Interval  4: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #19  @50  RefTypeDef <Ivl:4> CNS_INT BB01 regmask=[allInt] minReg=1>

DefList: { N049.t60. CNS_INT }
N051 (  2,  2) [000046] ------------              *  RETURN    int    REG NA $280
<RefPosition #20  @51  RefTypeFixedReg <Reg:rax>  BB01 regmask=[rax] minReg=1>
<RefPosition #21  @51  RefTypeUse <Ivl:4>  BB01 regmask=[rax] minReg=1 last fixed>



CHECKING LAST USES for BB01, liveout={}
==============================
use: {V00}
def: {V00 V03}

Linear scan intervals BEFORE VALIDATING INTERVALS:
Interval  0: int (INTERNAL) RefPositions {#1@39 #3@39} physReg:NA Preferences=[allInt]
Interval  1: float (INTERNAL) RefPositions {#2@39 #4@39} physReg:NA Preferences=[mm0-mm5]
Interval  2: byref RefPositions {#5@42 #7@43} physReg:NA Preferences=[rcx]
Interval  3: byref RefPositions {#9@44 #11@45} physReg:NA Preferences=[rcx]
Interval  4: int (constant) RefPositions {#19@50 #21@51} physReg:NA Preferences=[rax]

------------
REFPOSITIONS BEFORE VALIDATING INTERVALS:
------------
<RefPosition #0   @1   RefTypeBB  BB01 regmask=[] minReg=1>
<RefPosition #1   @39  RefTypeDef <Ivl:0 internal> STORE_BLK BB01 regmask=[allInt] minReg=1>
<RefPosition #2   @39  RefTypeDef <Ivl:1 internal> STORE_BLK BB01 regmask=[mm0-mm5] minReg=1>
<RefPosition #3   @39  RefTypeUse <Ivl:0 internal> STORE_BLK BB01 regmask=[allInt] minReg=1 last>
<RefPosition #4   @39  RefTypeUse <Ivl:1 internal> STORE_BLK BB01 regmask=[mm0-mm5] minReg=1 last>
<RefPosition #5   @42  RefTypeDef <Ivl:2> LCL_VAR_ADDR BB01 regmask=[rcx] minReg=1>
<RefPosition #6   @43  RefTypeFixedReg <Reg:rcx>  BB01 regmask=[rcx] minReg=1>
<RefPosition #7   @43  RefTypeUse <Ivl:2>  BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #8   @44  RefTypeFixedReg <Reg:rcx>  BB01 regmask=[rcx] minReg=1>
<RefPosition #9   @44  RefTypeDef <Ivl:3> PUTARG_REG BB01 regmask=[rcx] minReg=1 fixed>
<RefPosition #10  @45  RefTypeFixedReg <Reg:rcx>  BB01 regmask=[rcx] minReg=1>
<RefPosition #11  @45  RefTypeUse <Ivl:3>  BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #12  @46  RefTypeKill <Reg:rax>  BB01 regmask=[rax] minReg=1 last>
<RefPosition #13  @46  RefTypeKill <Reg:rcx>  BB01 regmask=[rcx] minReg=1 last>
<RefPosition #14  @46  RefTypeKill <Reg:rdx>  BB01 regmask=[rdx] minReg=1 last>
<RefPosition #15  @46  RefTypeKill <Reg:r8 >  BB01 regmask=[r8] minReg=1 last>
<RefPosition #16  @46  RefTypeKill <Reg:r9 >  BB01 regmask=[r9] minReg=1 last>
<RefPosition #17  @46  RefTypeKill <Reg:r10>  BB01 regmask=[r10] minReg=1 last>
<RefPosition #18  @46  RefTypeKill <Reg:r11>  BB01 regmask=[r11] minReg=1 last>
<RefPosition #19  @50  RefTypeDef <Ivl:4> CNS_INT BB01 regmask=[rax] minReg=1>
<RefPosition #20  @51  RefTypeFixedReg <Reg:rax>  BB01 regmask=[rax] minReg=1>
<RefPosition #21  @51  RefTypeUse <Ivl:4>  BB01 regmask=[rax] minReg=1 last fixed>
TUPLE STYLE DUMP WITH REF POSITIONS
Incoming Parameters:
BB01 [000..050) (return), preds={} succs={}
=====
  N003.                    IL_OFFSET IL offset: 0x0
  N005.                    CNS_INT   1
  N007.                    V00 MEM
  N009.                    IL_OFFSET IL offset: 0x8
  N011.                    CNS_INT   2
  N013.                    V00 MEM
  N015.                    IL_OFFSET IL offset: 0x10
  N017.                    CNS_INT   3
  N019.                    V00 MEM
  N021.                    IL_OFFSET IL offset: 0x18
  N023.                    CNS_INT   4
  N025.                    V00 MEM
  N027.                    IL_OFFSET IL offset: 0x20
  N029.                    CNS_INT   5
  N031.                    V00 MEM
  N033.                    IL_OFFSET IL offset: 0x28
  N035.                    V00 MEM
  N037.                    LCL_VAR_ADDR V02 tmp1          NA
  N039.                    STORE_BLK
        Def:<T0>(#1)
        Def:<T1>(#2)
                               Use:<T0>(#3) *
                               Use:<T1>(#4) *
  N041.                    LCL_VAR_ADDR V02 tmp1          NA
        Def:<I2>(#5)
  N043.                    PUTARG_REG
                               Use:<I2>(#7) Fixed:rcx(#6) *
        Def:<I3>(#9) rcx
  N045.                    CALL
                               Use:<I3>(#11) Fixed:rcx(#10) *
        Kill: rax rcx rdx r8 r9 r10 r11
  N047.                    IL_OFFSET IL offset: 0x3b
  N049.                    CNS_INT   6
        Def:<I4>(#19)
  N051.                    RETURN
                               Use:<I4>(#21) Fixed:rax(#20) *




Linear scan intervals after buildIntervals:
Interval  0: int (INTERNAL) RefPositions {#1@39 #3@39} physReg:NA Preferences=[allInt]
Interval  1: float (INTERNAL) RefPositions {#2@39 #4@39} physReg:NA Preferences=[mm0-mm5]
Interval  2: byref RefPositions {#5@42 #7@43} physReg:NA Preferences=[rcx]
Interval  3: byref RefPositions {#9@44 #11@45} physReg:NA Preferences=[rcx]
Interval  4: int (constant) RefPositions {#19@50 #21@51} physReg:NA Preferences=[rax]

*************** In LinearScan::allocateRegisters()

Linear scan intervals before allocateRegisters:
Interval  0: int (INTERNAL) RefPositions {#1@39 #3@39} physReg:NA Preferences=[allInt]
Interval  1: float (INTERNAL) RefPositions {#2@39 #4@39} physReg:NA Preferences=[mm0-mm5]
Interval  2: byref RefPositions {#5@42 #7@43} physReg:NA Preferences=[rcx]
Interval  3: byref RefPositions {#9@44 #11@45} physReg:NA Preferences=[rcx]
Interval  4: int (constant) RefPositions {#19@50 #21@51} physReg:NA Preferences=[rax]

------------
REFPOSITIONS BEFORE ALLOCATION:
------------
<RefPosition #0   @1   RefTypeBB  BB01 regmask=[] minReg=1>
<RefPosition #1   @39  RefTypeDef <Ivl:0 internal> STORE_BLK BB01 regmask=[allInt] minReg=1>
<RefPosition #2   @39  RefTypeDef <Ivl:1 internal> STORE_BLK BB01 regmask=[mm0-mm5] minReg=1>
<RefPosition #3   @39  RefTypeUse <Ivl:0 internal> STORE_BLK BB01 regmask=[allInt] minReg=1 last>
<RefPosition #4   @39  RefTypeUse <Ivl:1 internal> STORE_BLK BB01 regmask=[mm0-mm5] minReg=1 last>
<RefPosition #5   @42  RefTypeDef <Ivl:2> LCL_VAR_ADDR BB01 regmask=[rcx] minReg=1>
<RefPosition #6   @43  RefTypeFixedReg <Reg:rcx>  BB01 regmask=[rcx] minReg=1>
<RefPosition #7   @43  RefTypeUse <Ivl:2>  BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #8   @44  RefTypeFixedReg <Reg:rcx>  BB01 regmask=[rcx] minReg=1>
<RefPosition #9   @44  RefTypeDef <Ivl:3> PUTARG_REG BB01 regmask=[rcx] minReg=1 fixed>
<RefPosition #10  @45  RefTypeFixedReg <Reg:rcx>  BB01 regmask=[rcx] minReg=1>
<RefPosition #11  @45  RefTypeUse <Ivl:3>  BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #12  @46  RefTypeKill <Reg:rax>  BB01 regmask=[rax] minReg=1 last>
<RefPosition #13  @46  RefTypeKill <Reg:rcx>  BB01 regmask=[rcx] minReg=1 last>
<RefPosition #14  @46  RefTypeKill <Reg:rdx>  BB01 regmask=[rdx] minReg=1 last>
<RefPosition #15  @46  RefTypeKill <Reg:r8 >  BB01 regmask=[r8] minReg=1 last>
<RefPosition #16  @46  RefTypeKill <Reg:r9 >  BB01 regmask=[r9] minReg=1 last>
<RefPosition #17  @46  RefTypeKill <Reg:r10>  BB01 regmask=[r10] minReg=1 last>
<RefPosition #18  @46  RefTypeKill <Reg:r11>  BB01 regmask=[r11] minReg=1 last>
<RefPosition #19  @50  RefTypeDef <Ivl:4> CNS_INT BB01 regmask=[rax] minReg=1>
<RefPosition #20  @51  RefTypeFixedReg <Reg:rax>  BB01 regmask=[rax] minReg=1>
<RefPosition #21  @51  RefTypeUse <Ivl:4>  BB01 regmask=[rax] minReg=1 last fixed>

VAR REFPOSITIONS BEFORE ALLOCATION
--- V00
--- V01
--- V02
--- V03



Allocating Registers
--------------------
The following table has one or more rows for each RefPosition that is handled during allocation.
The first column provides the basic information about the RefPosition, with its type (e.g. Def,
Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the
action taken during allocation (e.g. Alloc a new register, or Keep an existing one).
The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is
active, a 'p' if it is a large vector that has been partially spilled, and 'i'if it is inactive.
Columns are only printed up to the last modifed register, which may increase during allocation,
in which case additional columns will appear.
Registers which are not marked modified have ---- in their column.

------------------------------+----+----+----+----+----+----+----+----+----+
LocRP# Name Type  Action Reg  |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8  |r9  |
------------------------------+----+----+----+----+----+----+----+----+----+
                              |    |    |    |    |    |    |    |    |    |
 1.#0  BB1 PredBB0            |    |    |    |    |    |    |    |    |    |
39.#1  I0   Def    Alloc rcx  |    |I0 a|    |    |    |    |    |    |    |
39.#2  I1   Def    Alloc mm0  |    |I0 a|    |    |    |    |    |    |    |
39.#3  I0   Use *  Keep  rcx  |    |I0 a|    |    |    |    |    |    |    |
39.#4  I1   Use *  Keep  mm0  |    |I0 a|    |    |    |    |    |    |    |
42.#5  I2   Def    Alloc rcx  |    |I2 a|    |    |    |    |    |    |    |
43.#6  rcx  Fixd   Keep  rcx  |    |I2 a|    |    |    |    |    |    |    |
43.#7  I2   Use *  Keep  rcx  |    |I2 a|    |    |    |    |    |    |    |
44.#8  rcx  Fixd   Keep  rcx  |    |    |    |    |    |    |    |    |    |
44.#9  I3   Def    Alloc rcx  |    |I3 a|    |    |    |    |    |    |    |
45.#10 rcx  Fixd   Keep  rcx  |    |I3 a|    |    |    |    |    |    |    |
45.#11 I3   Use *  Keep  rcx  |    |I3 a|    |    |    |    |    |    |    |
46.#12 rax  Kill   Keep  rax  |    |    |    |    |    |    |    |    |    |
46.#13 rcx  Kill   Keep  rcx  |    |    |    |    |    |    |    |    |    |
46.#14 rdx  Kill   Keep  rdx  |    |    |    |    |    |    |    |    |    |
46.#15 r8   Kill   Keep  r8   |    |    |    |    |    |    |    |    |    |
46.#16 r9   Kill   Keep  r9   |    |    |    |    |    |    |    |    |    |
46.#17 r10  Kill   Keep  r10  |    |    |    |    |    |    |    |    |    |
46.#18 r11  Kill   Keep  r11  |    |    |    |    |    |    |    |    |    |
50.#19 C4   Def    Alloc rax  |C4 a|    |    |    |    |    |    |    |    |
51.#20 rax  Fixd   Keep  rax  |C4 a|    |    |    |    |    |    |    |    |
51.#21 C4   Use *  Keep  rax  |C4 i|    |    |    |    |    |    |    |    |

------------
REFPOSITIONS AFTER ALLOCATION:
------------
<RefPosition #0   @1   RefTypeBB  BB01 regmask=[] minReg=1>
<RefPosition #1   @39  RefTypeDef <Ivl:0 internal> STORE_BLK BB01 regmask=[rcx] minReg=1>
<RefPosition #2   @39  RefTypeDef <Ivl:1 internal> STORE_BLK BB01 regmask=[mm0] minReg=1>
<RefPosition #3   @39  RefTypeUse <Ivl:0 internal> STORE_BLK BB01 regmask=[rcx] minReg=1 last>
<RefPosition #4   @39  RefTypeUse <Ivl:1 internal> STORE_BLK BB01 regmask=[mm0] minReg=1 last>
<RefPosition #5   @42  RefTypeDef <Ivl:2> LCL_VAR_ADDR BB01 regmask=[rcx] minReg=1>
<RefPosition #6   @43  RefTypeFixedReg <Reg:rcx>  BB01 regmask=[rcx] minReg=1>
<RefPosition #7   @43  RefTypeUse <Ivl:2>  BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #8   @44  RefTypeFixedReg <Reg:rcx>  BB01 regmask=[rcx] minReg=1>
<RefPosition #9   @44  RefTypeDef <Ivl:3> PUTARG_REG BB01 regmask=[rcx] minReg=1 fixed>
<RefPosition #10  @45  RefTypeFixedReg <Reg:rcx>  BB01 regmask=[rcx] minReg=1>
<RefPosition #11  @45  RefTypeUse <Ivl:3>  BB01 regmask=[rcx] minReg=1 last fixed>
<RefPosition #12  @46  RefTypeKill <Reg:rax>  BB01 regmask=[rax] minReg=1 last>
<RefPosition #13  @46  RefTypeKill <Reg:rcx>  BB01 regmask=[rcx] minReg=1 last>
<RefPosition #14  @46  RefTypeKill <Reg:rdx>  BB01 regmask=[rdx] minReg=1 last>
<RefPosition #15  @46  RefTypeKill <Reg:r8 >  BB01 regmask=[r8] minReg=1 last>
<RefPosition #16  @46  RefTypeKill <Reg:r9 >  BB01 regmask=[r9] minReg=1 last>
<RefPosition #17  @46  RefTypeKill <Reg:r10>  BB01 regmask=[r10] minReg=1 last>
<RefPosition #18  @46  RefTypeKill <Reg:r11>  BB01 regmask=[r11] minReg=1 last>
<RefPosition #19  @50  RefTypeDef <Ivl:4> CNS_INT BB01 regmask=[rax] minReg=1>
<RefPosition #20  @51  RefTypeFixedReg <Reg:rax>  BB01 regmask=[rax] minReg=1>
<RefPosition #21  @51  RefTypeUse <Ivl:4>  BB01 regmask=[rax] minReg=1 last fixed>

VAR REFPOSITIONS AFTER ALLOCATION
--- V00
--- V01
--- V02
--- V03

Active intervals at end of allocation:

-----------------------
RESOLVING BB BOUNDARIES
-----------------------
Resolution Candidates: {}
Has NoCritical Edges

Prior to Resolution

BB01
use def in out
{V00}
{V00 V03}
{V00}
{}
Var=Reg beg of BB01: none
Var=Reg end of BB01: none


RESOLVING EDGES
Trees after linear scan register allocator (LSRA)

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..050)        (return)                     i label target hascall gcsafe LIR
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..050) (return), preds={} succs={}
N003 (???,???) [000061] ------------                 IL_OFFSET void   IL offset: 0x0 REG NA
N005 (  1,  1) [000002] -c----------         t2 =    CNS_INT   int    1 REG NA $41
                                                  /--*  t2     int
N007 (  5,  6) [000004] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:1->0[+0] Fseq[i1] NA REG NA
N009 (???,???) [000062] ------------                 IL_OFFSET void   IL offset: 0x8 REG NA
N011 (  1,  1) [000007] -c----------         t7 =    CNS_INT   int    2 REG NA $43
                                                  /--*  t7     int
N013 (  5,  6) [000009] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:2->0[+4] Fseq[i2] NA REG NA
N015 (???,???) [000063] ------------                 IL_OFFSET void   IL offset: 0x10 REG NA
N017 (  1,  1) [000012] -c----------        t12 =    CNS_INT   int    3 REG NA $44
                                                  /--*  t12    int
N019 (  5,  6) [000014] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:3->0[+8] Fseq[i3] NA REG NA
N021 (???,???) [000064] ------------                 IL_OFFSET void   IL offset: 0x18 REG NA
N023 (  1,  1) [000017] -c----------        t17 =    CNS_INT   int    4 REG NA $45
                                                  /--*  t17    int
N025 (  5,  6) [000019] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:4->0[+12] Fseq[i4] NA REG NA
N027 (???,???) [000065] ------------                 IL_OFFSET void   IL offset: 0x20 REG NA
N029 (  1,  1) [000022] -c----------        t22 =    CNS_INT   int    5 REG NA $46
                                                  /--*  t22    int
N031 (  5,  6) [000024] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:5->0[+16] Fseq[i5] NA REG NA
N033 (???,???) [000066] ------------                 IL_OFFSET void   IL offset: 0x28 REG NA
N035 (  3,  2) [000025] -c-----N----        t25 =    LCL_VAR   struct<S, 20> V00 loc0         u:6 NA (last use) REG NA $104
N037 (???,???) [000068] Dc-----N----        t68 =    LCL_VAR_ADDR byref  V02 tmp1          NA REG NA
                                                  /--*  t68    byref
                                                  +--*  t25    struct
N039 (  7,  5) [000050] sA--------L-              *  STORE_BLK struct<S, 20> (copy) (Unroll) REG NA
N041 (  3,  2) [000051] -------N----        t51 =    LCL_VAR_ADDR byref  V02 tmp1          rcx REG rcx
                                                  /--*  t51    byref
N043 (???,???) [000069] ------------        t69 = *  PUTARG_REG byref  REG rcx
                                                  /--*  t69    byref  arg0 in rcx
N045 ( 27, 14) [000026] --CXG-------              *  CALL      void   Runtime_49101.Test REG NA $VN.Void
N047 (???,???) [000067] ------------                 IL_OFFSET void   IL offset: 0x3b REG NA
N049 (  1,  1) [000060] ------------        t60 =    CNS_INT   int    6 REG rax $48
                                                  /--*  t60    int
N051 (  2,  2) [000046] ------------              *  RETURN    int    REG NA $280

-------------------------------------------------------------------------------------------------------------------

Final allocation
------------------------------+----+----+----+----+----+----+----+----+----+
LocRP# Name Type  Action Reg  |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8  |r9  |
------------------------------+----+----+----+----+----+----+----+----+----+
 1.#0  BB1 PredBB0            |    |    |    |    |    |    |    |    |    |
39.#1  I0   Def    Alloc rcx  |    |I0 a|    |    |    |    |    |    |    |
39.#2  I1   Def    Alloc mm0  |    |I0 a|    |    |    |    |    |    |    |
39.#3  I0   Use *  Keep  rcx  |    |I0 i|    |    |    |    |    |    |    |
39.#4  I1   Use *  Keep  mm0  |    |    |    |    |    |    |    |    |    |
42.#5  I2   Def    Alloc rcx  |    |I2 a|    |    |    |    |    |    |    |
43.#6  rcx  Fixd   Keep  rcx  |    |I2 a|    |    |    |    |    |    |    |
43.#7  I2   Use *  Keep  rcx  |    |I2 i|    |    |    |    |    |    |    |
44.#8  rcx  Fixd   Keep  rcx  |    |    |    |    |    |    |    |    |    |
44.#9  I3   Def    Alloc rcx  |    |I3 a|    |    |    |    |    |    |    |
45.#10 rcx  Fixd   Keep  rcx  |    |I3 a|    |    |    |    |    |    |    |
45.#11 I3   Use *  Keep  rcx  |    |I3 i|    |    |    |    |    |    |    |
46.#12 rax  Kill   Keep  rax  |    |    |    |    |    |    |    |    |    |
46.#13 rcx  Kill   Keep  rcx  |    |    |    |    |    |    |    |    |    |
46.#14 rdx  Kill   Keep  rdx  |    |    |    |    |    |    |    |    |    |
46.#15 r8   Kill   Keep  r8   |    |    |    |    |    |    |    |    |    |
46.#16 r9   Kill   Keep  r9   |    |    |    |    |    |    |    |    |    |
46.#17 r10  Kill   Keep  r10  |    |    |    |    |    |    |    |    |    |
46.#18 r11  Kill   Keep  r11  |    |    |    |    |    |    |    |    |    |
50.#19 C4   Def    Alloc rax  |C4 a|    |    |    |    |    |    |    |    |
51.#20 rax  Fixd   Keep  rax  |C4 a|    |    |    |    |    |    |    |    |
51.#21 C4   Use *  Keep  rax  |C4 i|    |    |    |    |    |    |    |    |

Recording the maximum number of concurrent spills:

----------
LSRA Stats
----------
Total Tracked Vars:  2
Total Reg Cand Vars: 0
Total number of Intervals: 4
Total number of RefPositions: 21
Total Spill Count: 0    Weighted: 0.000000
Total CopyReg Count: 0   Weighted: 0.000000
Total ResolutionMov Count: 0    Weighted: 0.000000
Total number of split edges: 0
Total Number of spill temps created: 0

TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
Incoming Parameters:
BB01 [000..050) (return), preds={} succs={}
=====
  N003.                    IL_OFFSET IL offset: 0x0
  N005.                    CNS_INT   1
  N007.                    V00 MEM
  N009.                    IL_OFFSET IL offset: 0x8
  N011.                    CNS_INT   2
  N013.                    V00 MEM
  N015.                    IL_OFFSET IL offset: 0x10
  N017.                    CNS_INT   3
  N019.                    V00 MEM
  N021.                    IL_OFFSET IL offset: 0x18
  N023.                    CNS_INT   4
  N025.                    V00 MEM
  N027.                    IL_OFFSET IL offset: 0x20
  N029.                    CNS_INT   5
  N031.                    V00 MEM
  N033.                    IL_OFFSET IL offset: 0x28
  N035.                    V00 MEM
  N037.                    LCL_VAR_ADDR V02 tmp1          NA
  N039.                    STORE_BLK
  N041. rcx             =  LCL_VAR_ADDR V02 tmp1          rcx
  N043. rcx             =  PUTARG_REG; rcx
  N045.                    CALL     ; rcx
  N047.                    IL_OFFSET IL offset: 0x3b
  N049. rax             =  CNS_INT   6
  N051.                    RETURN   ; rax
Var=Reg end of BB01: none




*************** Finishing PHASE Linear scan register alloc
*************** In genGenerateCode()

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..050)        (return)                     i label target hascall gcsafe LIR
-----------------------------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Generate code
*************** In fgDebugCheckBBlist
Finalizing stack frame
Recording Var Locations at start of BB01
  <none>

Modified regs: [rax rcx rdx r8-r11 mm0]
Callee-saved registers pushed: 0 []
*************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
Assign V00 loc0, size=24, stkOffs=-0x20
Assign V02 tmp1, size=24, stkOffs=-0x38
Assign V01 OutArgs, size=32, stkOffs=-0x58
--- delta bump 8 for RA
--- delta bump 88 for RSP frame
--- virtual stack offset to actual stack offset delta is 96
-- V00 was -32, now 64
-- V01 was -88, now 8
-- V02 was -56, now 40
; Final local variable assignments
;
;  V00 loc0         [V00,T00] (  6,  6   )  struct (24) [rsp+0x40]   do-not-enreg[SFB] must-init ld-addr-op
;  V01 OutArgs      [V01    ] (  1,  1   )  lclBlk (32) [rsp+0x00]   "OutgoingArgSpace"
;  V02 tmp1         [V02    ] (  2,  4   )  struct (24) [rsp+0x28]   do-not-enreg[XSB] addr-exposed "by-value struct argument"
;* V03 cse0         [V03,T01] (  0,  0   )     int  ->  zero-ref    "CSE - aggressive"
;
; Lcl frame size = 88
Setting stack level from -572662307 to 0

=============== Generating BB01 [000..050) (return), preds={} succs={} flags=0x00000002.200b0020: i label target hascall gcsafe LIR
BB01 IN (1)={V00} + ByrefExposed + GcHeap
     OUT(0)={   }

Recording Var Locations at start of BB01
  <none>

Change life 0000000000000000 {} -> 0000000000000001 {V00}
                                                        Live regs: (unchanged) 00000000 {}
                                                        GC regs: (unchanged) 00000000 {}
                                                        Byref regs: (unchanged) 00000000 {}

      L_M21405_BB01:
Label: IG02, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}

Scope info: begin block BB01, IL range [000..050)
Scope info: open scopes =
   0 (V00 loc0) [000..050)
Added IP mapping: 0x0000 STACK_EMPTY (G_M21405_IG02,ins#0,ofs#0) label
Generating: N003 (???,???) [000061] ------------                 IL_OFFSET void   IL offset: 0x0 REG NA
Generating: N005 (  1,  1) [000002] -c----------         t2 =    CNS_INT   int    1 REG NA $41
                                                              /--*  t2     int  
Generating: N007 (  5,  6) [000004] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:1->0[+0] Fseq[i1] NA REG NA
IN0001:        mov      dword ptr [V00 rsp+40H], 1
Added IP mapping: 0x0008 STACK_EMPTY (G_M21405_IG02,ins#1,ofs#8)
Generating: N009 (???,???) [000062] ------------                 IL_OFFSET void   IL offset: 0x8 REG NA
Generating: N011 (  1,  1) [000007] -c----------         t7 =    CNS_INT   int    2 REG NA $43
                                                              /--*  t7     int  
Generating: N013 (  5,  6) [000009] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:2->0[+4] Fseq[i2] NA REG NA
IN0002:        mov      dword ptr [V00+0x4 rsp+44H], 2
Added IP mapping: 0x0010 STACK_EMPTY (G_M21405_IG02,ins#2,ofs#16)
Generating: N015 (???,???) [000063] ------------                 IL_OFFSET void   IL offset: 0x10 REG NA
Generating: N017 (  1,  1) [000012] -c----------        t12 =    CNS_INT   int    3 REG NA $44
                                                              /--*  t12    int  
Generating: N019 (  5,  6) [000014] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:3->0[+8] Fseq[i3] NA REG NA
IN0003:        mov      dword ptr [V00+0x8 rsp+48H], 3
Added IP mapping: 0x0018 STACK_EMPTY (G_M21405_IG02,ins#3,ofs#24)
Generating: N021 (???,???) [000064] ------------                 IL_OFFSET void   IL offset: 0x18 REG NA
Generating: N023 (  1,  1) [000017] -c----------        t17 =    CNS_INT   int    4 REG NA $45
                                                              /--*  t17    int  
Generating: N025 (  5,  6) [000019] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:4->0[+12] Fseq[i4] NA REG NA
IN0004:        mov      dword ptr [V00+0xC rsp+4CH], 4
Added IP mapping: 0x0020 STACK_EMPTY (G_M21405_IG02,ins#4,ofs#32)
Generating: N027 (???,???) [000065] ------------                 IL_OFFSET void   IL offset: 0x20 REG NA
Generating: N029 (  1,  1) [000022] -c----------        t22 =    CNS_INT   int    5 REG NA $46
                                                              /--*  t22    int  
Generating: N031 (  5,  6) [000024] UA----------              *  STORE_LCL_FLD int    V00 loc0         ud:5->0[+16] Fseq[i5] NA REG NA
IN0005:        mov      dword ptr [V00+0x10 rsp+50H], 5
Added IP mapping: 0x0028 STACK_EMPTY (G_M21405_IG02,ins#5,ofs#40)
Generating: N033 (???,???) [000066] ------------                 IL_OFFSET void   IL offset: 0x28 REG NA
Generating: N035 (  3,  2) [000025] -c-----N----        t25 =    LCL_VAR   struct<S, 20> V00 loc0         u:6 NA (last use) REG NA $104
Generating: N037 (???,???) [000068] Dc-----N----        t68 =    LCL_VAR_ADDR byref  V02 tmp1          NA REG NA
                                                              /--*  t68    byref
                                                              +--*  t25    struct
Generating: N039 (  7,  5) [000050] sA--------L-              *  STORE_BLK struct<S, 20> (copy) (Unroll) REG NA
IN0006:        vmovdqu  xmm0, xmmword ptr [V00 rsp+40H]
IN0007:        vmovdqu  xmmword ptr [V02 rsp+28H], xmm0
IN0008:        mov      ecx, dword ptr [V00+0x10 rsp+50H]
IN0009:        mov      dword ptr [V02+0x10 rsp+38H], ecx
Generating: N041 (  3,  2) [000051] -------N----        t51 =    LCL_VAR_ADDR byref  V02 tmp1          rcx REG rcx
IN000a:        lea      rcx, bword ptr [V02 rsp+28H]
                                                        Byref regs: 00000000 {} => 00000002 {rcx}
                                                              /--*  t51    byref
Generating: N043 (???,???) [000069] ------------        t69 = *  PUTARG_REG byref  REG rcx
                                                        Byref regs: 00000002 {rcx} => 00000000 {}
                                                        Byref regs: 00000000 {} => 00000002 {rcx}
                                                              /--*  t69    byref  arg0 in rcx
Generating: N045 ( 27, 14) [000026] --CXG-------              *  CALL      void   Runtime_49101.Test REG NA $VN.Void
                                                        Byref regs: 00000002 {rcx} => 00000000 {}
                                                        Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
IN000b:        call     Runtime_49101:Test(S)
Added IP mapping: 0x003B STACK_EMPTY (G_M21405_IG02,ins#11,ofs#72)
Generating: N047 (???,???) [000067] ------------                 IL_OFFSET void   IL offset: 0x3b REG NA
Generating: N049 (  1,  1) [000060] ------------        t60 =    CNS_INT   int    6 REG rax $48
IN000c:        mov      eax, 6
                                                              /--*  t60    int  
Generating: N051 (  2,  2) [000046] ------------              *  RETURN    int    REG NA $280

Scope info: end block BB01, IL range [000..050)
Scope info: ending scope, LVnum=0 [000..050)
Scope info: open scopes =
   <none>
Added IP mapping: EPILOG STACK_EMPTY (G_M21405_IG02,ins#12,ofs#77) label
Reserving epilog IG for block BB01

      G_M21405_IG02:        ; offs=000000H, funclet=00, bbWeight=1
*************** After placeholder IG creation
G_M21405_IG01:        ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M21405_IG02:        ; offs=000000H, size=004DH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M21405_IG03:        ; epilog placeholder, next placeholder=<END>, BB01 [0000], epilog, extend <-- First placeholder <-- Last placeholder
                      ;   PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
                      ;   InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
Change life 0000000000000001 {V00} -> 0000000000000000 {}

# compCycleEstimate =     61, compSizeEstimate =    53 Runtime_49101:Main():int
; Final local variable assignments
;
;  V00 loc0         [V00,T00] (  6,  6   )  struct (24) [rsp+0x40]   do-not-enreg[SFB] must-init ld-addr-op
;  V01 OutArgs      [V01    ] (  1,  1   )  lclBlk (32) [rsp+0x00]   "OutgoingArgSpace"
;  V02 tmp1         [V02    ] (  2,  4   )  struct (24) [rsp+0x28]   do-not-enreg[XSB] addr-exposed "by-value struct argument"
;* V03 cse0         [V03,T01] (  0,  0   )     int  ->  zero-ref    "CSE - aggressive"
;
; Lcl frame size = 88
*************** Before prolog / epilog generation
G_M21405_IG01:        ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M21405_IG02:        ; offs=000000H, size=004DH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M21405_IG03:        ; epilog placeholder, next placeholder=<END>, BB01 [0000], epilog, extend <-- First placeholder <-- Last placeholder
                      ;   PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
                      ;   InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
Recording Var Locations at start of BB01
  <none>

*************** In genFnProlog()
Added IP mapping to front: PROLOG STACK_EMPTY (G_M21405_IG01,ins#0,ofs#0) label

__prolog:
Found 6 lvMustInit int-sized stack slots, frame offsets -64 through -88
IN000d:        sub      rsp, 88
IN000e:        vzeroupper
Notify VM instruction set (AVX2) must be supported.
IN000f:        vxorps   xmm4, xmm4
IN0010:        vmovdqa  xmmword ptr [rsp+40H], xmm4
IN0011:        xor      rax, rax
IN0012:        mov      qword ptr [rsp+50H], rax
*************** In genEnregisterIncomingStackArgs()


      G_M21405_IG01:        ; offs=000000H, funclet=00, bbWeight=1
*************** In genFnEpilog()

__epilog:
gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=00000000 {}, gcRegByrefSetCur=00000000 {}
IN0013:        add      rsp, 88
IN0014:        ret

      G_M21405_IG03:        ; offs=00004DH, funclet=00, bbWeight=1
0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs
*************** After prolog / epilog generation
G_M21405_IG01:        ; func=00, offs=000000H, size=001AH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
G_M21405_IG02:        ; offs=00001AH, size=004DH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M21405_IG03:        ; offs=000067H, size=0005H, epilog, nogc, extend
*************** In emitJumpDistBind()

*************** Finishing PHASE Generate code

*************** Starting PHASE Emit code

Hot  code size = 0x6C bytes
Cold code size = 0x0 bytes
reserveUnwindInfo(isFunclet=FALSE, isColdCode=FALSE, unwindSize=0x6)
*************** In emitEndCodeGen()
Converting emitMaxStackDepth from bytes (0) to elements (0)

***************************************************************************
Instructions as they come out of the scheduler


G_M21405_IG01:        ; func=00, offs=000000H, size=001AH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
IN000d: 000000 sub      rsp, 88
IN000e: 000004 vzeroupper
IN000f: 000007 vxorps   xmm4, xmm4 (ECS:5, ACS:4)
Instruction predicted size = 5, actual = 4
IN0010: 00000B vmovdqa  xmmword ptr [rsp+40H], xmm4 (ECS:7, ACS:6)
Instruction predicted size = 7, actual = 6
IN0011: 000011 xor      eax, eax
IN0012: 000013 mov      qword ptr [rsp+50H], rax
                                                ;; bbWeight=1    PerfScore 3.83
G_M21405_IG02:        ; func=00, offs=00001AH, size=004DH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
Block predicted offs = 0000001A, actual = 00000018 -> size adj = 2
IN0001: 000018 mov      dword ptr [rsp+40H], 1
IN0002: 000020 mov      dword ptr [rsp+44H], 2
IN0003: 000028 mov      dword ptr [rsp+48H], 3
IN0004: 000030 mov      dword ptr [rsp+4CH], 4
IN0005: 000038 mov      dword ptr [rsp+50H], 5
IN0006: 000040 vmovdqu  xmm0, xmmword ptr [rsp+40H] (ECS:7, ACS:6)
Instruction predicted size = 7, actual = 6
IN0007: 000046 vmovdqu  xmmword ptr [rsp+28H], xmm0 (ECS:7, ACS:6)
Instruction predicted size = 7, actual = 6
IN0008: 00004C mov      ecx, dword ptr [rsp+50H]
IN0009: 000050 mov      dword ptr [rsp+38H], ecx
IN000a: 000054 lea      rcx, bword ptr [rsp+28H]
       ; byrRegs +[rcx]
IN000b: 000059 call     Runtime_49101:Test(S)
       ; byrRegs -[rcx]
       ; gcr arg pop 0
IN000c: 00005E mov      eax, 6
                                                ;; bbWeight=1    PerfScore 10.75
G_M21405_IG03:        ; func=00, offs=000067H, size=0005H, epilog, nogc, extend
Block predicted offs = 00000067, actual = 00000063 -> size adj = 4
IN0013: 000063 add      rsp, 88
IN0014: 000067 ret
                                                ;; bbWeight=1    PerfScore 1.25Allocated method code size =  108 , actual size =  104, unused size =    4

; Total bytes of code 104, prolog size 24, PerfScore 26.63, instruction count 20, allocated bytes for code 108 (MethodHash=6f90ac62) for method Runtime_49101:Main():int
; ============================================================

*************** After end code gen, before unwindEmit()
G_M21405_IG01:        ; func=00, offs=000000H, size=0018H, bbWeight=1    PerfScore 3.83, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc, isz <-- Prolog IG

IN000d: 000000 sub      rsp, 88
IN000e: 000004 vzeroupper
IN000f: 000007 vxorps   xmm4, xmm4
IN0010: 00000B vmovdqa  xmmword ptr [rsp+40H], xmm4
IN0011: 000011 xor      eax, eax
IN0012: 000013 mov      qword ptr [rsp+50H], rax

G_M21405_IG02:        ; offs=000018H, size=004BH, bbWeight=1    PerfScore 10.75, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz

IN0001: 000018 mov      dword ptr [V00 rsp+40H], 1
IN0002: 000020 mov      dword ptr [V00+0x4 rsp+44H], 2
IN0003: 000028 mov      dword ptr [V00+0x8 rsp+48H], 3
IN0004: 000030 mov      dword ptr [V00+0xC rsp+4CH], 4
IN0005: 000038 mov      dword ptr [V00+0x10 rsp+50H], 5
IN0006: 000040 vmovdqu  xmm0, xmmword ptr [V00 rsp+40H]
IN0007: 000046 vmovdqu  xmmword ptr [V02 rsp+28H], xmm0
IN0008: 00004C mov      ecx, dword ptr [V00+0x10 rsp+50H]
IN0009: 000050 mov      dword ptr [V02+0x10 rsp+38H], ecx
IN000a: 000054 lea      rcx, bword ptr [V02 rsp+28H]
IN000b: 000059 call     Runtime_49101:Test(S)
IN000c: 00005E mov      eax, 6

G_M21405_IG03:        ; offs=000063H, size=0005H, bbWeight=1    PerfScore 1.25, epilog, nogc, extend

IN0013: 000063 add      rsp, 88
IN0014: 000067 ret


*************** Finishing PHASE Emit code

*************** Starting PHASE Emit GC+EH tables
Unwind Info:
  >> Start offset   : 0x000000 (not in unwind data)
  >>   End offset   : 0xd1ffab1e (not in unwind data)
  Version           : 1
  Flags             : 0x00
  SizeOfProlog      : 0x04
  CountOfUnwindCodes: 1
  FrameRegister     : none (0)
  FrameOffset       : N/A (no FrameRegister) (Value=0)
  UnwindCodes       :
    CodeOffset: 0x04 UnwindOp: UWOP_ALLOC_SMALL (2)     OpInfo: 10 * 8 + 8 = 88 = 0x58
allocUnwindInfo(pHotCode=0x00000000D1FFAB1E, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x68, unwindSize=0x6, pUnwindBlock=0x00000000D1FFAB1E, funKind=0 (main function))
*************** In genIPmappingGen()
IP mapping count : 9
IL offs PROLOG : 0x00000000 ( STACK_EMPTY )
IL offs 0x0000 : 0x00000018 ( STACK_EMPTY )
IL offs 0x0008 : 0x00000020 ( STACK_EMPTY )
IL offs 0x0010 : 0x00000028 ( STACK_EMPTY )
IL offs 0x0018 : 0x00000030 ( STACK_EMPTY )
IL offs 0x0020 : 0x00000038 ( STACK_EMPTY )
IL offs 0x0028 : 0x00000040 ( STACK_EMPTY )
IL offs 0x003B : 0x0000005E ( STACK_EMPTY )
IL offs EPILOG : 0x00000063 ( STACK_EMPTY )

*************** In genSetScopeInfo()
VarLocInfo count is 1
; Variable debug info: 1 live range(s), 1 var(s) for method Runtime_49101:Main():int
  0(   UNKNOWN) : From 00000018h to 00000063h, in rsp'[64] (1 slot)
*************** In gcInfoBlockHdrSave()
Set code length to 104.
Set ReturnKind to Scalar.
Set Outgoing stack arg area size to 32.
Defining 1 call sites:
    Offset 0x59, size 5.

*************** Finishing PHASE Emit GC+EH tables
Method code size: 104

Allocations for Runtime_49101:Main():int (MethodHash=6f90ac62)
count:        661, size:      61959, max =       3072
allocateMemory:      65536, nraUsed:      64632

Alloc'd bytes by kind:
                  kind |       size |     pct
  ---------------------+------------+--------
         AssertionProp |       6460 |  10.43%
               ASTNode |       9232 |  14.90%
              InstDesc |       3128 |   5.05%
              ImpStack |        384 |   0.62%
            BasicBlock |       1408 |   2.27%
             fgArgInfo |         64 |   0.10%
       fgArgInfoPtrArr |          8 |   0.01%
              FlowList |         64 |   0.10%
     TreeStatementList |         64 |   0.10%
               SiScope |         80 |   0.13%
       DominatorMemory |        192 |   0.31%
                  LSRA |       3356 |   5.42%
         LSRA_Interval |        400 |   0.65%
      LSRA_RefPosition |       1408 |   2.27%
          Reachability |         32 |   0.05%
                   SSA |        552 |   0.89%
           ValueNumber |       8148 |  13.15%
              LvaTable |       1948 |   3.14%
            UnwindInfo |          0 |   0.00%
                hashBv |        256 |   0.41%
                bitset |        152 |   0.25%
          FixedBitVect |         16 |   0.03%
               Generic |       1690 |   2.73%
   LocalAddressVisitor |          0 |   0.00%
         FieldSeqStore |        368 |   0.59%
    ZeroOffsetFieldMap |         40 |   0.06%
          ArrayInfoMap |         80 |   0.13%
          MemoryPhiArg |          0 |   0.00%
                   CSE |       1376 |   2.22%
                    GC |       1349 |   2.18%
       CorTailCallInfo |          0 |   0.00%
              Inlining |        584 |   0.94%
            ArrayStack |          0 |   0.00%
             DebugInfo |        328 |   0.53%
             DebugOnly |      17023 |  27.47%
               Codegen |       1176 |   1.90%
               LoopOpt |          0 |   0.00%
             LoopHoist |          0 |   0.00%
               Unknown |        145 |   0.23%
            RangeCheck |          0 |   0.00%
              CopyProp |        184 |   0.30%
           SideEffects |          0 |   0.00%
       ObjectAllocator |          0 |   0.00%
    VariableLiveRanges |          0 |   0.00%
           ClassLayout |         72 |   0.12%
       TailMergeThrows |          0 |   0.00%
             EarlyProp |          0 |   0.00%
              ZeroInit |        192 |   0.31%
                   Pgo |          0 |   0.00%

****** DONE compiling Runtime_49101:Main():int
Press any key to continue . . .