diff --git a/src/coreclr/jit/codegenarm64test.cpp b/src/coreclr/jit/codegenarm64test.cpp index 959a99182b27b..8c43a2972c1db 100644 --- a/src/coreclr/jit/codegenarm64test.cpp +++ b/src/coreclr/jit/codegenarm64test.cpp @@ -5717,26 +5717,12 @@ void CodeGen::genArm64EmitterUnitTestsSve() INS_OPTS_SCALABLE_H); // UMLSLB ., ., . theEmitter->emitIns_R_R_R(INS_sve_umlslt, EA_SCALABLE, REG_V21, REG_V22, REG_V23, INS_OPTS_SCALABLE_S); // UMLSLT ., ., . - - // IF_SVE_EM_3A - theEmitter->emitIns_R_R_R(INS_sve_sqrdmlah, EA_SCALABLE, REG_V0, REG_V1, REG_V2, - INS_OPTS_SCALABLE_B); // SQRDMLAH ., ., . - theEmitter->emitIns_R_R_R(INS_sve_sqrdmlah, EA_SCALABLE, REG_V3, REG_V4, REG_V5, - INS_OPTS_SCALABLE_H); // SQRDMLAH ., ., . - theEmitter->emitIns_R_R_R(INS_sve_sqrdmlsh, EA_SCALABLE, REG_V6, REG_V7, REG_V8, - INS_OPTS_SCALABLE_S); // SQRDMLSH ., ., . - theEmitter->emitIns_R_R_R(INS_sve_sqrdmlsh, EA_SCALABLE, REG_V9, REG_V10, REG_V11, - INS_OPTS_SCALABLE_D); // SQRDMLSH ., ., . - - // IF_SVE_EN_3A theEmitter->emitIns_R_R_R(INS_sve_sqdmlalbt, EA_SCALABLE, REG_V0, REG_V1, REG_V2, INS_OPTS_SCALABLE_H); // SQDMLALBT ., ., . theEmitter->emitIns_R_R_R(INS_sve_sqdmlslbt, EA_SCALABLE, REG_V3, REG_V4, REG_V5, INS_OPTS_SCALABLE_S); // SQDMLSLBT ., ., . theEmitter->emitIns_R_R_R(INS_sve_sqdmlslbt, EA_SCALABLE, REG_V6, REG_V7, REG_V8, INS_OPTS_SCALABLE_D); // SQDMLSLBT ., ., . - - // IF_SVE_EO_3A theEmitter->emitIns_R_R_R(INS_sve_sqdmlalb, EA_SCALABLE, REG_V0, REG_V1, REG_V2, INS_OPTS_SCALABLE_H); // SQDMLALB ., ., . theEmitter->emitIns_R_R_R(INS_sve_sqdmlalt, EA_SCALABLE, REG_V3, REG_V4, REG_V5, @@ -5745,6 +5731,24 @@ void CodeGen::genArm64EmitterUnitTestsSve() INS_OPTS_SCALABLE_D); // SQDMLSLB ., ., . theEmitter->emitIns_R_R_R(INS_sve_sqdmlslt, EA_SCALABLE, REG_V9, REG_V10, REG_V11, INS_OPTS_SCALABLE_H); // SQDMLSLT ., ., . + theEmitter->emitIns_R_R_R(INS_sve_sabalb, EA_SCALABLE, REG_V0, REG_V1, REG_V2, + INS_OPTS_SCALABLE_H); // SABALB ., ., . + theEmitter->emitIns_R_R_R(INS_sve_sabalt, EA_SCALABLE, REG_V3, REG_V4, REG_V5, + INS_OPTS_SCALABLE_S); // SABALT ., ., . + theEmitter->emitIns_R_R_R(INS_sve_uabalb, EA_SCALABLE, REG_V6, REG_V7, REG_V8, + INS_OPTS_SCALABLE_D); // UABALB ., ., . + theEmitter->emitIns_R_R_R(INS_sve_uabalt, EA_SCALABLE, REG_V9, REG_V10, REG_V11, + INS_OPTS_SCALABLE_H); // UABALT ., ., . + + // IF_SVE_EM_3A + theEmitter->emitIns_R_R_R(INS_sve_sqrdmlah, EA_SCALABLE, REG_V0, REG_V1, REG_V2, + INS_OPTS_SCALABLE_B); // SQRDMLAH ., ., . + theEmitter->emitIns_R_R_R(INS_sve_sqrdmlah, EA_SCALABLE, REG_V3, REG_V4, REG_V5, + INS_OPTS_SCALABLE_H); // SQRDMLAH ., ., . + theEmitter->emitIns_R_R_R(INS_sve_sqrdmlsh, EA_SCALABLE, REG_V6, REG_V7, REG_V8, + INS_OPTS_SCALABLE_S); // SQRDMLSH ., ., . + theEmitter->emitIns_R_R_R(INS_sve_sqrdmlsh, EA_SCALABLE, REG_V9, REG_V10, REG_V11, + INS_OPTS_SCALABLE_D); // SQRDMLSH ., ., . // IF_SVE_EX_3A theEmitter->emitIns_R_R_R(INS_sve_tblq, EA_SCALABLE, REG_V0, REG_V1, REG_V2, @@ -5783,6 +5787,28 @@ void CodeGen::genArm64EmitterUnitTestsSve() INS_OPTS_SCALABLE_S); // USUBLB ., ., . theEmitter->emitIns_R_R_R(INS_sve_usublt, EA_SCALABLE, REG_V1, REG_V2, REG_V3, INS_OPTS_SCALABLE_D); // USUBLT ., ., . + theEmitter->emitIns_R_R_R(INS_sve_pmullb, EA_SCALABLE, REG_V0, REG_V1, REG_V2, + INS_OPTS_SCALABLE_H); // PMULLB ., ., . + theEmitter->emitIns_R_R_R(INS_sve_pmullt, EA_SCALABLE, REG_V3, REG_V4, REG_V5, + INS_OPTS_SCALABLE_D); // PMULLT ., ., . + theEmitter->emitIns_R_R_R(INS_sve_smullb, EA_SCALABLE, REG_V6, REG_V7, REG_V8, + INS_OPTS_SCALABLE_H); // SMULLB ., ., . + theEmitter->emitIns_R_R_R(INS_sve_smullt, EA_SCALABLE, REG_V9, REG_V10, REG_V11, + INS_OPTS_SCALABLE_D); // SMULLT ., ., . + theEmitter->emitIns_R_R_R(INS_sve_sqdmullb, EA_SCALABLE, REG_V12, REG_V13, REG_V14, + INS_OPTS_SCALABLE_H); // SQDMULLB ., ., . + theEmitter->emitIns_R_R_R(INS_sve_sqdmullt, EA_SCALABLE, REG_V15, REG_V16, REG_V17, + INS_OPTS_SCALABLE_D); // SQDMULLT ., ., . + theEmitter->emitIns_R_R_R(INS_sve_umullb, EA_SCALABLE, REG_V18, REG_V19, REG_V20, + INS_OPTS_SCALABLE_H); // UMULLB ., ., . + theEmitter->emitIns_R_R_R(INS_sve_umullt, EA_SCALABLE, REG_V21, REG_V22, REG_V23, + INS_OPTS_SCALABLE_D); // UMULLT ., ., . + theEmitter->emitIns_R_R_R(INS_sve_saddlbt, EA_SCALABLE, REG_V0, REG_V1, REG_V2, + INS_OPTS_SCALABLE_H); // SADDLBT ., ., . + theEmitter->emitIns_R_R_R(INS_sve_ssublbt, EA_SCALABLE, REG_V3, REG_V4, REG_V5, + INS_OPTS_SCALABLE_S); // SSUBLBT ., ., . + theEmitter->emitIns_R_R_R(INS_sve_ssubltb, EA_SCALABLE, REG_V6, REG_V7, REG_V8, + INS_OPTS_SCALABLE_D); // SSUBLTB ., ., . // IF_SVE_FM_3A theEmitter->emitIns_R_R_R(INS_sve_saddwb, EA_SCALABLE, REG_V0, REG_V1, REG_V2, @@ -5802,24 +5828,6 @@ void CodeGen::genArm64EmitterUnitTestsSve() theEmitter->emitIns_R_R_R(INS_sve_usubwt, EA_SCALABLE, REG_V21, REG_V22, REG_V23, INS_OPTS_SCALABLE_S); // USUBWT ., ., . - // IF_SVE_FN_3A - theEmitter->emitIns_R_R_R(INS_sve_pmullb, EA_SCALABLE, REG_V0, REG_V1, REG_V2, - INS_OPTS_SCALABLE_H); // PMULLB ., ., . - theEmitter->emitIns_R_R_R(INS_sve_pmullt, EA_SCALABLE, REG_V3, REG_V4, REG_V5, - INS_OPTS_SCALABLE_D); // PMULLT ., ., . - theEmitter->emitIns_R_R_R(INS_sve_smullb, EA_SCALABLE, REG_V6, REG_V7, REG_V8, - INS_OPTS_SCALABLE_H); // SMULLB ., ., . - theEmitter->emitIns_R_R_R(INS_sve_smullt, EA_SCALABLE, REG_V9, REG_V10, REG_V11, - INS_OPTS_SCALABLE_D); // SMULLT ., ., . - theEmitter->emitIns_R_R_R(INS_sve_sqdmullb, EA_SCALABLE, REG_V12, REG_V13, REG_V14, - INS_OPTS_SCALABLE_H); // SQDMULLB ., ., . - theEmitter->emitIns_R_R_R(INS_sve_sqdmullt, EA_SCALABLE, REG_V15, REG_V16, REG_V17, - INS_OPTS_SCALABLE_D); // SQDMULLT ., ., . - theEmitter->emitIns_R_R_R(INS_sve_umullb, EA_SCALABLE, REG_V18, REG_V19, REG_V20, - INS_OPTS_SCALABLE_H); // UMULLB ., ., . - theEmitter->emitIns_R_R_R(INS_sve_umullt, EA_SCALABLE, REG_V21, REG_V22, REG_V23, - INS_OPTS_SCALABLE_D); // UMULLT ., ., . - // IF_SVE_FN_3B theEmitter->emitIns_R_R_R(INS_sve_pmullb, EA_SCALABLE, REG_V0, REG_V1, REG_V2, INS_OPTS_SCALABLE_Q); // PMULLB .Q, .D, .D @@ -5834,14 +5842,6 @@ void CodeGen::genArm64EmitterUnitTestsSve() theEmitter->emitIns_R_R_R(INS_sve_usmmla, EA_SCALABLE, REG_V6, REG_V7, REG_V8, INS_OPTS_SCALABLE_S); // USMMLA .S, .B, .B - // IF_SVE_FS_3A - theEmitter->emitIns_R_R_R(INS_sve_saddlbt, EA_SCALABLE, REG_V0, REG_V1, REG_V2, - INS_OPTS_SCALABLE_H); // SADDLBT ., ., . - theEmitter->emitIns_R_R_R(INS_sve_ssublbt, EA_SCALABLE, REG_V3, REG_V4, REG_V5, - INS_OPTS_SCALABLE_S); // SSUBLBT ., ., . - theEmitter->emitIns_R_R_R(INS_sve_ssubltb, EA_SCALABLE, REG_V6, REG_V7, REG_V8, - INS_OPTS_SCALABLE_D); // SSUBLTB ., ., . - // IF_SVE_FW_3A theEmitter->emitIns_R_R_R(INS_sve_saba, EA_SCALABLE, REG_V0, REG_V1, REG_V2, INS_OPTS_SCALABLE_B); // SABA ., ., . @@ -5852,16 +5852,6 @@ void CodeGen::genArm64EmitterUnitTestsSve() theEmitter->emitIns_R_R_R(INS_sve_uaba, EA_SCALABLE, REG_V9, REG_V10, REG_V11, INS_OPTS_SCALABLE_D); // UABA ., ., . - // IF_SVE_FX_3A - theEmitter->emitIns_R_R_R(INS_sve_sabalb, EA_SCALABLE, REG_V0, REG_V1, REG_V2, - INS_OPTS_SCALABLE_H); // SABALB ., ., . - theEmitter->emitIns_R_R_R(INS_sve_sabalt, EA_SCALABLE, REG_V3, REG_V4, REG_V5, - INS_OPTS_SCALABLE_S); // SABALT ., ., . - theEmitter->emitIns_R_R_R(INS_sve_uabalb, EA_SCALABLE, REG_V6, REG_V7, REG_V8, - INS_OPTS_SCALABLE_D); // UABALB ., ., . - theEmitter->emitIns_R_R_R(INS_sve_uabalt, EA_SCALABLE, REG_V9, REG_V10, REG_V11, - INS_OPTS_SCALABLE_H); // UABALT ., ., . - #ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED // IF_SVE_GC_3A theEmitter->emitIns_R_R_R(INS_sve_addhnb, EA_SCALABLE, REG_V0, REG_V1, REG_V2, diff --git a/src/coreclr/jit/emitarm64sve.cpp b/src/coreclr/jit/emitarm64sve.cpp index 8526b09133da7..c91b2df64fb40 100644 --- a/src/coreclr/jit/emitarm64sve.cpp +++ b/src/coreclr/jit/emitarm64sve.cpp @@ -363,9 +363,9 @@ emitter::code_t emitter::emitInsCodeSve(instruction ins, insFormat fmt) const static insFormat formatEncode3N[3] = {IF_SVE_EK_3A, IF_SVE_FB_3A, IF_SVE_FB_3B}; const static insFormat formatEncode3O[3] = {IF_SVE_EK_3A, IF_SVE_FC_3A, IF_SVE_FC_3B}; const static insFormat formatEncode3P[3] = {IF_SVE_EL_3A, IF_SVE_FG_3A, IF_SVE_FG_3B}; - const static insFormat formatEncode3Q[3] = {IF_SVE_EO_3A, IF_SVE_FJ_3A, IF_SVE_FJ_3B}; - const static insFormat formatEncode3R[3] = {IF_SVE_FE_3A, IF_SVE_FE_3B, IF_SVE_FN_3A}; - const static insFormat formatEncode3S[3] = {IF_SVE_FH_3A, IF_SVE_FH_3B, IF_SVE_FN_3A}; + const static insFormat formatEncode3Q[3] = {IF_SVE_EL_3A, IF_SVE_FJ_3A, IF_SVE_FJ_3B}; + const static insFormat formatEncode3R[3] = {IF_SVE_FE_3A, IF_SVE_FE_3B, IF_SVE_FL_3A}; + const static insFormat formatEncode3S[3] = {IF_SVE_FH_3A, IF_SVE_FH_3B, IF_SVE_FL_3A}; const static insFormat formatEncode3T[3] = {IF_SVE_GX_3C, IF_SVE_HK_3B, IF_SVE_HL_3B}; const static insFormat formatEncode3U[3] = {IF_SVE_IM_3A, IF_SVE_IN_4A, IF_SVE_IX_4A}; const static insFormat formatEncode3V[3] = {IF_SVE_JA_4A, IF_SVE_JB_4A, IF_SVE_JM_3A}; @@ -402,7 +402,7 @@ emitter::code_t emitter::emitInsCodeSve(instruction ins, insFormat fmt) const static insFormat formatEncode2BF[2] = {IF_SVE_DM_2A, IF_SVE_DN_2A}; const static insFormat formatEncode2BG[2] = {IF_SVE_DO_2A, IF_SVE_DP_2A}; const static insFormat formatEncode2BH[2] = {IF_SVE_DW_2A, IF_SVE_DW_2B}; - const static insFormat formatEncode2BI[2] = {IF_SVE_FN_3A, IF_SVE_FN_3B}; + const static insFormat formatEncode2BI[2] = {IF_SVE_FL_3A, IF_SVE_FN_3B}; const static insFormat formatEncode2BJ[2] = {IF_SVE_GQ_3A, IF_SVE_HG_2A}; const static insFormat formatEncode2BK[2] = {IF_SVE_GU_3C, IF_SVE_HU_4B}; const static insFormat formatEncode2BL[2] = {IF_SVE_GZ_3A, IF_SVE_HB_3A}; @@ -3281,7 +3281,7 @@ void emitter::emitInsSve_R_R_R(instruction ins, assert(isVectorRegister(reg2)); // nnnnn assert(isVectorRegister(reg3)); // mmmmm assert(isValidVectorElemsize(optGetSveElemsize(opt))); // xx - fmt = IF_SVE_EN_3A; + fmt = IF_SVE_EL_3A; break; case INS_sve_sqdmlalb: @@ -3293,7 +3293,7 @@ void emitter::emitInsSve_R_R_R(instruction ins, assert(isVectorRegister(reg2)); // nnnnn assert(isVectorRegister(reg3)); // mmmmm assert(isValidVectorElemsize(optGetSveElemsize(opt))); // xx - fmt = IF_SVE_EO_3A; + fmt = IF_SVE_EL_3A; break; case INS_sve_sclamp: @@ -3366,7 +3366,7 @@ void emitter::emitInsSve_R_R_R(instruction ins, assert(isVectorRegister(reg2)); // nnnnn assert(isVectorRegister(reg3)); // mmmmm assert(isValidVectorElemsize(optGetSveElemsize(opt))); // xx - fmt = IF_SVE_FN_3A; + fmt = IF_SVE_FL_3A; break; case INS_sve_pmullb: @@ -3383,7 +3383,7 @@ void emitter::emitInsSve_R_R_R(instruction ins, { assert((opt == INS_OPTS_SCALABLE_H) || (opt == INS_OPTS_SCALABLE_D)); assert(isValidVectorElemsize(optGetSveElemsize(opt))); // xx - fmt = IF_SVE_FN_3A; + fmt = IF_SVE_FL_3A; } break; @@ -3542,7 +3542,7 @@ void emitter::emitInsSve_R_R_R(instruction ins, assert(isVectorRegister(reg2)); // nnnnn assert(isVectorRegister(reg3)); // mmmmm assert(isValidVectorElemsize(optGetSveElemsize(opt))); // xx - fmt = IF_SVE_FS_3A; + fmt = IF_SVE_FL_3A; break; case INS_sve_saba: @@ -3564,7 +3564,7 @@ void emitter::emitInsSve_R_R_R(instruction ins, assert(isVectorRegister(reg2)); // nnnnn assert(isVectorRegister(reg3)); // mmmmm assert(isValidVectorElemsize(optGetSveElemsize(opt))); // xx - fmt = IF_SVE_FX_3A; + fmt = IF_SVE_EL_3A; break; case INS_sve_addhnb: @@ -10016,19 +10016,14 @@ BYTE* emitter::emitOutput_InstrSve(BYTE* dst, instrDesc* id) case IF_SVE_BZ_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE table lookup (three sources) case IF_SVE_BZ_3A_A: // ........xx.mmmmm ......nnnnnddddd -- SVE table lookup (three sources) case IF_SVE_EH_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE integer dot product (unpredicated) - case IF_SVE_EL_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 integer multiply-add long + case IF_SVE_EL_3A: // ........xx.mmmmm ......nnnnnddddd case IF_SVE_EM_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 saturating multiply-add high - case IF_SVE_EN_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 saturating multiply-add interleaved long - case IF_SVE_EO_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 saturating multiply-add long case IF_SVE_EX_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE permute vector elements (quadwords) - case IF_SVE_FL_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 integer add/subtract long + case IF_SVE_FL_3A: // ........xx.mmmmm ......nnnnnddddd case IF_SVE_FM_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 integer add/subtract wide - case IF_SVE_FN_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 integer multiply long - case IF_SVE_FS_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 integer add/subtract interleaved long case IF_SVE_FW_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 integer absolute difference and accumulate - case IF_SVE_FX_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 integer absolute difference and accumulate long - case IF_SVE_GC_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 integer add/subtract narrow high part - case IF_SVE_GF_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 histogram generation (segment) + case IF_SVE_GC_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 integer add/subtract narrow high part + case IF_SVE_GF_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 histogram generation (segment) code = emitInsCodeSve(ins, fmt); code |= insEncodeReg_V<4, 0>(id->idReg1()); // ddddd code |= insEncodeReg_V<9, 5>(id->idReg2()); // nnnnn @@ -12648,19 +12643,14 @@ void emitter::emitInsSveSanityCheck(instrDesc* id) case IF_SVE_BZ_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE table lookup (three sources) case IF_SVE_BZ_3A_A: // ........xx.mmmmm ......nnnnnddddd -- SVE table lookup (three sources) case IF_SVE_EH_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE integer dot product (unpredicated) - case IF_SVE_EL_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 integer multiply-add long + case IF_SVE_EL_3A: // ........xx.mmmmm ......nnnnnddddd case IF_SVE_EM_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 saturating multiply-add high - case IF_SVE_EN_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 saturating multiply-add interleaved long - case IF_SVE_EO_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 saturating multiply-add long case IF_SVE_EX_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE permute vector elements (quadwords) - case IF_SVE_FL_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 integer add/subtract long + case IF_SVE_FL_3A: // ........xx.mmmmm ......nnnnnddddd case IF_SVE_FM_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 integer add/subtract wide - case IF_SVE_FN_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 integer multiply long - case IF_SVE_FS_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 integer add/subtract interleaved long case IF_SVE_FW_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 integer absolute difference and accumulate - case IF_SVE_FX_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 integer absolute difference and accumulate long - case IF_SVE_GC_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 integer add/subtract narrow high part - case IF_SVE_GF_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 histogram generation (segment) + case IF_SVE_GC_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 integer add/subtract narrow high part + case IF_SVE_GF_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 histogram generation (segment) assert(insOptsScalableStandard(id->idInsOpt())); // xx assert(isVectorRegister(id->idReg1())); // ddddd assert(isVectorRegister(id->idReg2())); // nnnnn @@ -15489,14 +15479,9 @@ void emitter::emitDispInsSveHelp(instrDesc* id) } // ., ., . - case IF_SVE_EL_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 integer multiply-add long - case IF_SVE_EN_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 saturating multiply-add interleaved long - case IF_SVE_EO_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 saturating multiply-add long - case IF_SVE_FX_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 integer absolute difference and accumulate long + case IF_SVE_EL_3A: // ........xx.mmmmm ......nnnnnddddd // ., ., . - case IF_SVE_FL_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 integer add/subtract long - case IF_SVE_FN_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 integer multiply long - case IF_SVE_FS_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 integer add/subtract interleaved long + case IF_SVE_FL_3A: // ........xx.mmmmm ......nnnnnddddd // .Q, .D, .D case IF_SVE_FN_3B: // ...........mmmmm ......nnnnnddddd -- SVE2 integer multiply long { @@ -16645,23 +16630,7 @@ void emitter::getInsSveExecutionCharacteristics(instrDesc* id, insExecutionChara } break; - case IF_SVE_BR_3B: // ...........mmmmm ......nnnnnddddd -- SVE permute vector segments - case IF_SVE_BZ_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE table lookup (three sources) - case IF_SVE_BZ_3A_A: // ........xx.mmmmm ......nnnnnddddd -- SVE table lookup (three sources) - case IF_SVE_FL_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 integer add/subtract long - case IF_SVE_FM_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 integer add/subtract wide - case IF_SVE_FS_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 integer add/subtract interleaved long - case IF_SVE_GC_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 integer add/subtract narrow high part - case IF_SVE_GF_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 histogram generation (segment) - case IF_SVE_AU_3A: // ...........mmmmm ......nnnnnddddd -- SVE bitwise logical operations (unpredicated) - case IF_SVE_GI_4A: // ........xx.mmmmm ...gggnnnnnddddd -- SVE2 histogram generation (vector) - case IF_SVE_BB_2A: // ...........nnnnn .....iiiiiiddddd -- SVE stack frame adjustment - case IF_SVE_BC_1A: // ................ .....iiiiiiddddd -- SVE stack frame size - result.insThroughput = PERFSCORE_THROUGHPUT_2C; - result.insLatency = PERFSCORE_LATENCY_2C; - break; - - case IF_SVE_FN_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 integer multiply long + case IF_SVE_FL_3A: // ........xx.mmmmm ......nnnnnddddd switch (ins) { case INS_sve_smullb: @@ -16673,18 +16642,34 @@ void emitter::getInsSveExecutionCharacteristics(instrDesc* id, insExecutionChara result.insThroughput = PERFSCORE_THROUGHPUT_1C; result.insLatency = PERFSCORE_LATENCY_4C; break; + case INS_sve_pmullb: case INS_sve_pmullt: result.insThroughput = PERFSCORE_THROUGHPUT_1C; result.insLatency = PERFSCORE_LATENCY_2C; break; + default: - // all other instructions - perfScoreUnhandledInstruction(id, &result); + result.insThroughput = PERFSCORE_THROUGHPUT_2C; + result.insLatency = PERFSCORE_LATENCY_2C; break; } break; + case IF_SVE_BR_3B: // ...........mmmmm ......nnnnnddddd -- SVE permute vector segments + case IF_SVE_BZ_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE table lookup (three sources) + case IF_SVE_BZ_3A_A: // ........xx.mmmmm ......nnnnnddddd -- SVE table lookup (three sources) + case IF_SVE_FM_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 integer add/subtract wide + case IF_SVE_GC_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 integer add/subtract narrow high part + case IF_SVE_GF_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 histogram generation (segment) + case IF_SVE_AU_3A: // ...........mmmmm ......nnnnnddddd -- SVE bitwise logical operations (unpredicated) + case IF_SVE_GI_4A: // ........xx.mmmmm ...gggnnnnnddddd -- SVE2 histogram generation (vector) + case IF_SVE_BB_2A: // ...........nnnnn .....iiiiiiddddd -- SVE stack frame adjustment + case IF_SVE_BC_1A: // ................ .....iiiiiiddddd -- SVE stack frame size + result.insThroughput = PERFSCORE_THROUGHPUT_2C; + result.insLatency = PERFSCORE_LATENCY_2C; + break; + case IF_SVE_BA_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE index generation (register start, register // increment) case IF_SVE_AX_1A: // ........xx.iiiii ......iiiiiddddd -- SVE index generation (immediate start, immediate @@ -16827,11 +16812,8 @@ void emitter::getInsSveExecutionCharacteristics(instrDesc* id, insExecutionChara case IF_SVE_FJ_3A: // ...........iimmm ....i.nnnnnddddd -- SVE2 saturating multiply-add (indexed) case IF_SVE_FJ_3B: // ...........immmm ....i.nnnnnddddd -- SVE2 saturating multiply-add (indexed) case IF_SVE_EH_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE integer dot product (unpredicated) - case IF_SVE_EL_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 integer multiply-add long - case IF_SVE_EN_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 saturating multiply-add interleaved long - case IF_SVE_EO_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 saturating multiply-add long + case IF_SVE_EL_3A: // ........xx.mmmmm ......nnnnnddddd case IF_SVE_FW_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 integer absolute difference and accumulate - case IF_SVE_FX_3A: // ........xx.mmmmm ......nnnnnddddd -- SVE2 integer absolute difference and accumulate long result.insLatency = PERFSCORE_LATENCY_4C; result.insThroughput = PERFSCORE_THROUGHPUT_1C; break; diff --git a/src/coreclr/jit/emitfmtsarm64sve.h b/src/coreclr/jit/emitfmtsarm64sve.h index b78e556588bd7..91b409bc7f4fd 100644 --- a/src/coreclr/jit/emitfmtsarm64sve.h +++ b/src/coreclr/jit/emitfmtsarm64sve.h @@ -137,7 +137,8 @@ IF_DEF(SVE_2BS, IS_NONE, NONE) // Instruction has 2 possible encoding types, ty * x -- element size *****************************************************************************/ -IF_DEF(SVE_AA_3A, IS_NONE, NONE) // SVE_AA_3A ........xx...... ...gggmmmmmddddd -- SVE bitwise logical operations + SVE integer add/subtract/multiply vectors + SVE integer min/max/difference + SVE bitwise shift by vector + SVE2 integer halving add/subtract + SVE2 integer pairwise arithmetic + SVE2 saturating add/subtract + SVE2 saturating/rounding bitwise shift left (predicated) +// SVE_AA_3A ........xx...... ...gggmmmmmddddd -- SVE bitwise logical operations + SVE integer add/subtract/multiply vectors + SVE integer min/max/difference + SVE bitwise shift by vector + SVE2 integer halving add/subtract + SVE2 integer pairwise arithmetic + SVE2 saturating add/subtract + SVE2 saturating/rounding bitwise shift left (predicated) +IF_DEF(SVE_AA_3A, IS_NONE, NONE) IF_DEF(SVE_AB_3B, IS_NONE, NONE) // SVE_AB_3B ................ ...gggmmmmmddddd -- SVE integer add/subtract vectors (predicated) IF_DEF(SVE_AC_3A, IS_NONE, NONE) // SVE_AC_3A ........xx...... ...gggmmmmmddddd -- SVE integer divide vectors (predicated) IF_DEF(SVE_AF_3A, IS_NONE, NONE) // SVE_AF_3A ........xx...... ...gggnnnnnddddd -- SVE bitwise logical reduction (predicated) @@ -153,7 +154,8 @@ IF_DEF(SVE_AP_3A, IS_NONE, NONE) // SVE_AP_3A ........xx...... ...gggnnnnnddd IF_DEF(SVE_AQ_3A, IS_NONE, NONE) // SVE_AQ_3A ........xx...... ...gggnnnnnddddd -- SVE integer unary operations (predicated) IF_DEF(SVE_AR_4A, IS_NONE, NONE) // SVE_AR_4A ........xx.mmmmm ...gggnnnnnddddd -- SVE integer multiply-accumulate writing addend (predicated) IF_DEF(SVE_AS_4A, IS_NONE, NONE) // SVE_AS_4A ........xx.mmmmm ...gggaaaaaddddd -- SVE integer multiply-add writing multiplicand (predicated) -IF_DEF(SVE_AT_3A, IS_NONE, NONE) // SVE_AT_3A ........xx.mmmmm ......nnnnnddddd -- SVE integer add/subtract vectors (unpredicated) + SVE2 integer multiply vectors (unpredicated) + SVE2 signed saturating doubling multiply high (unpredicated) + SVE floating-point trig select coefficient + SVE permute vector segments + sve_int_perm_tbxquads + SVE integer clamp + SVE2 bitwise exclusive-or interleaved + SVE2 bitwise permute + SVE FP clamp + SVE floating-point arithmetic (unpredicated) +// SVE_AT_3A ........xx.mmmmm ......nnnnnddddd -- SVE integer add/subtract vectors (unpredicated) + SVE2 integer multiply vectors (unpredicated) + SVE2 signed saturating doubling multiply high (unpredicated) + SVE floating-point trig select coefficient + SVE permute vector segments + sve_int_perm_tbxquads + SVE integer clamp + SVE2 bitwise exclusive-or interleaved + SVE2 bitwise permute + SVE FP clamp + SVE floating-point arithmetic (unpredicated) +IF_DEF(SVE_AT_3A, IS_NONE, NONE) IF_DEF(SVE_AT_3B, IS_NONE, NONE) // SVE_AT_3B ...........mmmmm ......nnnnnddddd -- SVE integer add/subtract vectors (unpredicated) IF_DEF(SVE_AU_3A, IS_NONE, NONE) // SVE_AU_3A ...........mmmmm ......nnnnnddddd -- SVE bitwise logical operations (unpredicated) IF_DEF(SVE_AV_3A, IS_NONE, NONE) // SVE_AV_3A ...........mmmmm ......kkkkkddddd -- SVE2 bitwise ternary operations @@ -271,10 +273,9 @@ IF_DEF(SVE_EH_3A, IS_NONE, NONE) // SVE_EH_3A ........xx.mmmmm ......nnnnnddd IF_DEF(SVE_EI_3A, IS_NONE, NONE) // SVE_EI_3A ...........mmmmm ......nnnnnddddd -- SVE mixed sign dot product IF_DEF(SVE_EJ_3A, IS_NONE, NONE) // SVE_EJ_3A ........xx.mmmmm ....rrnnnnnddddd -- SVE2 complex integer dot product IF_DEF(SVE_EK_3A, IS_NONE, NONE) // SVE_EK_3A ........xx.mmmmm ....rrnnnnnddddd -- SVE2 complex integer multiply-add -IF_DEF(SVE_EL_3A, IS_NONE, NONE) // SVE_EL_3A ........xx.mmmmm ......nnnnnddddd -- SVE2 integer multiply-add long +// SVE_EL_3A ........xx.mmmmm ......nnnnnddddd -- SVE2 integer multiply-add long + SVE2 saturating multiply-add interleaved long + SVE2 saturating multiply-add long + SVE2 integer absolute difference and accumulate long +IF_DEF(SVE_EL_3A, IS_NONE, NONE) IF_DEF(SVE_EM_3A, IS_NONE, NONE) // SVE_EM_3A ........xx.mmmmm ......nnnnnddddd -- SVE2 saturating multiply-add high -IF_DEF(SVE_EN_3A, IS_NONE, NONE) // SVE_EN_3A ........xx.mmmmm ......nnnnnddddd -- SVE2 saturating multiply-add interleaved long -IF_DEF(SVE_EO_3A, IS_NONE, NONE) // SVE_EO_3A ........xx.mmmmm ......nnnnnddddd -- SVE2 saturating multiply-add long IF_DEF(SVE_EQ_3A, IS_NONE, NONE) // SVE_EQ_3A ........xx...... ...gggnnnnnddddd -- SVE2 integer pairwise add and accumulate long IF_DEF(SVE_ES_3A, IS_NONE, NONE) // SVE_ES_3A ........xx...... ...gggnnnnnddddd -- SVE2 integer unary operations (predicated) IF_DEF(SVE_EW_3A, IS_NONE, NONE) // SVE_EW_3A ...........mmmmm ......nnnnnddddd -- SVE2 multiply-add (checked pointer) @@ -309,18 +310,16 @@ IF_DEF(SVE_FJ_3B, IS_NONE, NONE) // SVE_FJ_3B ...........immmm ....i.nnnnnddd IF_DEF(SVE_FK_3A, IS_NONE, NONE) // SVE_FK_3A .........i.iimmm ......nnnnnddddd -- SVE2 saturating multiply-add high (indexed) IF_DEF(SVE_FK_3B, IS_NONE, NONE) // SVE_FK_3B ...........iimmm ......nnnnnddddd -- SVE2 saturating multiply-add high (indexed) IF_DEF(SVE_FK_3C, IS_NONE, NONE) // SVE_FK_3C ...........immmm ......nnnnnddddd -- SVE2 saturating multiply-add high (indexed) -IF_DEF(SVE_FL_3A, IS_NONE, NONE) // SVE_FL_3A ........xx.mmmmm ......nnnnnddddd -- SVE2 integer add/subtract long +// SVE_FL_3A ........xx.mmmmm ......nnnnnddddd -- SVE2 integer add/subtract long + SVE2 integer multiply long + SVE2 integer add/subtract interleaved long +IF_DEF(SVE_FL_3A, IS_NONE, NONE) IF_DEF(SVE_FM_3A, IS_NONE, NONE) // SVE_FM_3A ........xx.mmmmm ......nnnnnddddd -- SVE2 integer add/subtract wide -IF_DEF(SVE_FN_3A, IS_NONE, NONE) // SVE_FN_3A ........xx.mmmmm ......nnnnnddddd -- SVE2 integer multiply long IF_DEF(SVE_FN_3B, IS_NONE, NONE) // SVE_FN_3B ...........mmmmm ......nnnnnddddd -- SVE2 integer multiply long IF_DEF(SVE_FO_3A, IS_NONE, NONE) // SVE_FO_3A ...........mmmmm ......nnnnnddddd -- SVE integer matrix multiply accumulate IF_DEF(SVE_FR_2A, IS_NONE, NONE) // SVE_FR_2A .........x.xxiii ......nnnnnddddd -- SVE2 bitwise shift left long -IF_DEF(SVE_FS_3A, IS_NONE, NONE) // SVE_FS_3A ........xx.mmmmm ......nnnnnddddd -- SVE2 integer add/subtract interleaved long IF_DEF(SVE_FT_2A, IS_NONE, NONE) // SVE_FT_2A ........xx.xxiii ......nnnnnddddd -- SVE2 bitwise shift and insert IF_DEF(SVE_FU_2A, IS_NONE, NONE) // SVE_FU_2A ........xx.xxiii ......nnnnnddddd -- SVE2 bitwise shift right and accumulate IF_DEF(SVE_FV_2A, IS_NONE, NONE) // SVE_FV_2A ........xx...... .....rmmmmmddddd -- SVE2 complex integer add IF_DEF(SVE_FW_3A, IS_NONE, NONE) // SVE_FW_3A ........xx.mmmmm ......nnnnnddddd -- SVE2 integer absolute difference and accumulate -IF_DEF(SVE_FX_3A, IS_NONE, NONE) // SVE_FX_3A ........xx.mmmmm ......nnnnnddddd -- SVE2 integer absolute difference and accumulate long IF_DEF(SVE_FY_3A, IS_NONE, NONE) // SVE_FY_3A .........x.mmmmm ......nnnnnddddd -- SVE2 integer add/subtract long with carry IF_DEF(SVE_FZ_2A, IS_NONE, NONE) // SVE_FZ_2A ................ ......nnnn.ddddd -- SME2 multi-vec extract narrow IF_DEF(SVE_GA_2A, IS_NONE, NONE) // SVE_GA_2A ............iiii ......nnnn.ddddd -- SME2 multi-vec shift narrow diff --git a/src/coreclr/jit/instrsarm64sve.h b/src/coreclr/jit/instrsarm64sve.h index 210ff6b2067a9..e29899d981b6d 100644 --- a/src/coreclr/jit/instrsarm64sve.h +++ b/src/coreclr/jit/instrsarm64sve.h @@ -837,60 +837,60 @@ INST3(umlslt, "umlslt", 0, IF_SV // UMLSLT .D, .S, .S[] SVE_FG_3B 01000100111immmm 1011i1nnnnnddddd 44E0 B400 -// enum name info SVE_EO_3A SVE_FJ_3A SVE_FJ_3B +// enum name info SVE_EL_3A SVE_FJ_3A SVE_FJ_3B INST3(sqdmlalb, "sqdmlalb", 0, IF_SVE_3Q, 0x44006000, 0x44A02000, 0x44E02000 ) - // SQDMLALB ., ., . SVE_EO_3A 01000100xx0mmmmm 011000nnnnnddddd 4400 6000 + // SQDMLALB ., ., . SVE_EL_3A 01000100xx0mmmmm 011000nnnnnddddd 4400 6000 // SQDMLALB .S, .H, .H[] SVE_FJ_3A 01000100101iimmm 0010i0nnnnnddddd 44A0 2000 // SQDMLALB .D, .S, .S[] SVE_FJ_3B 01000100111immmm 0010i0nnnnnddddd 44E0 2000 INST3(sqdmlalt, "sqdmlalt", 0, IF_SVE_3Q, 0x44006400, 0x44A02400, 0x44E02400 ) - // SQDMLALT ., ., . SVE_EO_3A 01000100xx0mmmmm 011001nnnnnddddd 4400 6400 + // SQDMLALT ., ., . SVE_EL_3A 01000100xx0mmmmm 011001nnnnnddddd 4400 6400 // SQDMLALT .S, .H, .H[] SVE_FJ_3A 01000100101iimmm 0010i1nnnnnddddd 44A0 2400 // SQDMLALT .D, .S, .S[] SVE_FJ_3B 01000100111immmm 0010i1nnnnnddddd 44E0 2400 INST3(sqdmlslb, "sqdmlslb", 0, IF_SVE_3Q, 0x44006800, 0x44A03000, 0x44E03000 ) - // SQDMLSLB ., ., . SVE_EO_3A 01000100xx0mmmmm 011010nnnnnddddd 4400 6800 + // SQDMLSLB ., ., . SVE_EL_3A 01000100xx0mmmmm 011010nnnnnddddd 4400 6800 // SQDMLSLB .S, .H, .H[] SVE_FJ_3A 01000100101iimmm 0011i0nnnnnddddd 44A0 3000 // SQDMLSLB .D, .S, .S[] SVE_FJ_3B 01000100111immmm 0011i0nnnnnddddd 44E0 3000 INST3(sqdmlslt, "sqdmlslt", 0, IF_SVE_3Q, 0x44006C00, 0x44A03400, 0x44E03400 ) - // SQDMLSLT ., ., . SVE_EO_3A 01000100xx0mmmmm 011011nnnnnddddd 4400 6C00 + // SQDMLSLT ., ., . SVE_EL_3A 01000100xx0mmmmm 011011nnnnnddddd 4400 6C00 // SQDMLSLT .S, .H, .H[] SVE_FJ_3A 01000100101iimmm 0011i1nnnnnddddd 44A0 3400 // SQDMLSLT .D, .S, .S[] SVE_FJ_3B 01000100111immmm 0011i1nnnnnddddd 44E0 3400 -// enum name info SVE_FE_3A SVE_FE_3B SVE_FN_3A +// enum name info SVE_FE_3A SVE_FE_3B SVE_FL_3A INST3(smullb, "smullb", 0, IF_SVE_3R, 0x44A0C000, 0x44E0C000, 0x45007000 ) // SMULLB .S, .H, .H[] SVE_FE_3A 01000100101iimmm 1100i0nnnnnddddd 44A0 C000 // SMULLB .D, .S, .S[] SVE_FE_3B 01000100111immmm 1100i0nnnnnddddd 44E0 C000 - // SMULLB ., ., . SVE_FN_3A 01000101xx0mmmmm 011100nnnnnddddd 4500 7000 + // SMULLB ., ., . SVE_FL_3A 01000101xx0mmmmm 011100nnnnnddddd 4500 7000 INST3(smullt, "smullt", 0, IF_SVE_3R, 0x44A0C400, 0x44E0C400, 0x45007400 ) // SMULLT .S, .H, .H[] SVE_FE_3A 01000100101iimmm 1100i1nnnnnddddd 44A0 C400 // SMULLT .D, .S, .S[] SVE_FE_3B 01000100111immmm 1100i1nnnnnddddd 44E0 C400 - // SMULLT ., ., . SVE_FN_3A 01000101xx0mmmmm 011101nnnnnddddd 4500 7400 + // SMULLT ., ., . SVE_FL_3A 01000101xx0mmmmm 011101nnnnnddddd 4500 7400 INST3(umullb, "umullb", 0, IF_SVE_3R, 0x44A0D000, 0x44E0D000, 0x45007800 ) // UMULLB .S, .H, .H[] SVE_FE_3A 01000100101iimmm 1101i0nnnnnddddd 44A0 D000 // UMULLB .D, .S, .S[] SVE_FE_3B 01000100111immmm 1101i0nnnnnddddd 44E0 D000 - // UMULLB ., ., . SVE_FN_3A 01000101xx0mmmmm 011110nnnnnddddd 4500 7800 + // UMULLB ., ., . SVE_FL_3A 01000101xx0mmmmm 011110nnnnnddddd 4500 7800 INST3(umullt, "umullt", 0, IF_SVE_3R, 0x44A0D400, 0x44E0D400, 0x45007C00 ) // UMULLT .S, .H, .H[] SVE_FE_3A 01000100101iimmm 1101i1nnnnnddddd 44A0 D400 // UMULLT .D, .S, .S[] SVE_FE_3B 01000100111immmm 1101i1nnnnnddddd 44E0 D400 - // UMULLT ., ., . SVE_FN_3A 01000101xx0mmmmm 011111nnnnnddddd 4500 7C00 + // UMULLT ., ., . SVE_FL_3A 01000101xx0mmmmm 011111nnnnnddddd 4500 7C00 -// enum name info SVE_FH_3A SVE_FH_3B SVE_FN_3A +// enum name info SVE_FH_3A SVE_FH_3B SVE_FL_3A INST3(sqdmullb, "sqdmullb", 0, IF_SVE_3S, 0x44A0E000, 0x44E0E000, 0x45006000 ) // SQDMULLB .S, .H, .H[] SVE_FH_3A 01000100101iimmm 1110i0nnnnnddddd 44A0 E000 // SQDMULLB .D, .S, .S[] SVE_FH_3B 01000100111immmm 1110i0nnnnnddddd 44E0 E000 - // SQDMULLB ., ., . SVE_FN_3A 01000101xx0mmmmm 011000nnnnnddddd 4500 6000 + // SQDMULLB ., ., . SVE_FL_3A 01000101xx0mmmmm 011000nnnnnddddd 4500 6000 INST3(sqdmullt, "sqdmullt", 0, IF_SVE_3S, 0x44A0E400, 0x44E0E400, 0x45006400 ) // SQDMULLT .S, .H, .H[] SVE_FH_3A 01000100101iimmm 1110i1nnnnnddddd 44A0 E400 // SQDMULLT .D, .S, .S[] SVE_FH_3B 01000100111immmm 1110i1nnnnnddddd 44E0 E400 - // SQDMULLT ., ., . SVE_FN_3A 01000101xx0mmmmm 011001nnnnnddddd 4500 6400 + // SQDMULLT ., ., . SVE_FL_3A 01000101xx0mmmmm 011001nnnnnddddd 4500 6400 // enum name info SVE_GX_3C SVE_HK_3B SVE_HL_3B @@ -1268,13 +1268,13 @@ INST2(pext, "pext", 0, IF_SV // PEXT {., .}, [] SVE_DW_2B 00100101xx100000 0111010iNNN1DDDD 2520 7410 -// enum name info SVE_FN_3A SVE_FN_3B +// enum name info SVE_FL_3A SVE_FN_3B INST2(pmullb, "pmullb", 0, IF_SVE_2BI, 0x45006800, 0x45006800 ) - // PMULLB ., ., . SVE_FN_3A 01000101xx0mmmmm 011010nnnnnddddd 4500 6800 + // PMULLB ., ., . SVE_FL_3A 01000101xx0mmmmm 011010nnnnnddddd 4500 6800 // PMULLB .Q, .D, .D SVE_FN_3B 01000101000mmmmm 011010nnnnnddddd 4500 6800 INST2(pmullt, "pmullt", 0, IF_SVE_2BI, 0x45006C00, 0x45006C00 ) - // PMULLT ., ., . SVE_FN_3A 01000101xx0mmmmm 011011nnnnnddddd 4500 6C00 + // PMULLT ., ., . SVE_FL_3A 01000101xx0mmmmm 011011nnnnnddddd 4500 6C00 // PMULLT .Q, .D, .D SVE_FN_3B 01000101000mmmmm 011011nnnnnddddd 4500 6C00 @@ -2311,12 +2311,12 @@ INST1(fdup, "fdup", 0, IF_SV // FDUP ., # SVE_EA_1A 00100101xx111001 110iiiiiiiiddddd 2539 C000 -// enum name info SVE_EN_3A -INST1(sqdmlalbt, "sqdmlalbt", 0, IF_SVE_EN_3A, 0x44000800 ) - // SQDMLALBT ., ., . SVE_EN_3A 01000100xx0mmmmm 000010nnnnnddddd 4400 0800 +// enum name info SVE_EL_3A +INST1(sqdmlalbt, "sqdmlalbt", 0, IF_SVE_EL_3A, 0x44000800 ) + // SQDMLALBT ., ., . SVE_EL_3A 01000100xx0mmmmm 000010nnnnnddddd 4400 0800 -INST1(sqdmlslbt, "sqdmlslbt", 0, IF_SVE_EN_3A, 0x44000C00 ) - // SQDMLSLBT ., ., . SVE_EN_3A 01000100xx0mmmmm 000011nnnnnddddd 4400 0C00 +INST1(sqdmlslbt, "sqdmlslbt", 0, IF_SVE_EL_3A, 0x44000C00 ) + // SQDMLSLBT ., ., . SVE_EL_3A 01000100xx0mmmmm 000011nnnnnddddd 4400 0C00 // enum name info SVE_AT_3A @@ -2451,15 +2451,15 @@ INST1(ushllt, "ushllt", 0, IF_SV // USHLLT ., ., # SVE_FR_2A 010001010x0xxiii 101011nnnnnddddd 4500 AC00 -// enum name info SVE_FS_3A -INST1(saddlbt, "saddlbt", 0, IF_SVE_FS_3A, 0x45008000 ) - // SADDLBT ., ., . SVE_FS_3A 01000101xx0mmmmm 100000nnnnnddddd 4500 8000 +// enum name info SVE_FL_3A +INST1(saddlbt, "saddlbt", 0, IF_SVE_FL_3A, 0x45008000 ) + // SADDLBT ., ., . SVE_FL_3A 01000101xx0mmmmm 100000nnnnnddddd 4500 8000 -INST1(ssublbt, "ssublbt", 0, IF_SVE_FS_3A, 0x45008800 ) - // SSUBLBT ., ., . SVE_FS_3A 01000101xx0mmmmm 100010nnnnnddddd 4500 8800 +INST1(ssublbt, "ssublbt", 0, IF_SVE_FL_3A, 0x45008800 ) + // SSUBLBT ., ., . SVE_FL_3A 01000101xx0mmmmm 100010nnnnnddddd 4500 8800 -INST1(ssubltb, "ssubltb", 0, IF_SVE_FS_3A, 0x45008C00 ) - // SSUBLTB ., ., . SVE_FS_3A 01000101xx0mmmmm 100011nnnnnddddd 4500 8C00 +INST1(ssubltb, "ssubltb", 0, IF_SVE_FL_3A, 0x45008C00 ) + // SSUBLTB ., ., . SVE_FL_3A 01000101xx0mmmmm 100011nnnnnddddd 4500 8C00 // enum name info SVE_FV_2A @@ -2470,18 +2470,18 @@ INST1(sqcadd, "sqcadd", 0, IF_SV // SQCADD ., ., ., SVE_FV_2A 01000101xx000001 11011rmmmmmddddd 4501 D800 -// enum name info SVE_FX_3A -INST1(sabalb, "sabalb", 0, IF_SVE_FX_3A, 0x4500C000 ) - // SABALB ., ., . SVE_FX_3A 01000101xx0mmmmm 110000nnnnnddddd 4500 C000 +// enum name info SVE_EL_3A +INST1(sabalb, "sabalb", 0, IF_SVE_EL_3A, 0x4500C000 ) + // SABALB ., ., . SVE_EL_3A 01000101xx0mmmmm 110000nnnnnddddd 4500 C000 -INST1(sabalt, "sabalt", 0, IF_SVE_FX_3A, 0x4500C400 ) - // SABALT ., ., . SVE_FX_3A 01000101xx0mmmmm 110001nnnnnddddd 4500 C400 +INST1(sabalt, "sabalt", 0, IF_SVE_EL_3A, 0x4500C400 ) + // SABALT ., ., . SVE_EL_3A 01000101xx0mmmmm 110001nnnnnddddd 4500 C400 -INST1(uabalb, "uabalb", 0, IF_SVE_FX_3A, 0x4500C800 ) - // UABALB ., ., . SVE_FX_3A 01000101xx0mmmmm 110010nnnnnddddd 4500 C800 +INST1(uabalb, "uabalb", 0, IF_SVE_EL_3A, 0x4500C800 ) + // UABALB ., ., . SVE_EL_3A 01000101xx0mmmmm 110010nnnnnddddd 4500 C800 -INST1(uabalt, "uabalt", 0, IF_SVE_FX_3A, 0x4500CC00 ) - // UABALT ., ., . SVE_FX_3A 01000101xx0mmmmm 110011nnnnnddddd 4500 CC00 +INST1(uabalt, "uabalt", 0, IF_SVE_EL_3A, 0x4500CC00 ) + // UABALT ., ., . SVE_EL_3A 01000101xx0mmmmm 110011nnnnnddddd 4500 CC00 // enum name info SVE_FY_3A