diff --git a/src/coreclr/jit/compiler.h b/src/coreclr/jit/compiler.h
index 7db9f05710b22b..d8f885064d0cd5 100644
--- a/src/coreclr/jit/compiler.h
+++ b/src/coreclr/jit/compiler.h
@@ -9789,13 +9789,6 @@ class Compiler
return getBaseTypeAndSizeOfSIMDType(typeHnd, nullptr);
}
- CorInfoType getBaseJitTypeAndSizeOfSIMDType(CORINFO_CLASS_HANDLE typeHnd, unsigned* sizeBytes = nullptr);
-
- CorInfoType getBaseJitTypeOfSIMDType(CORINFO_CLASS_HANDLE typeHnd)
- {
- return getBaseJitTypeAndSizeOfSIMDType(typeHnd, nullptr);
- }
-
GenTree* impSIMDPopStack();
void setLclRelatedToSIMDIntrinsic(GenTree* tree);
diff --git a/src/coreclr/jit/gentree.cpp b/src/coreclr/jit/gentree.cpp
index 826fba0d2ce604..0e93982ed415a5 100644
--- a/src/coreclr/jit/gentree.cpp
+++ b/src/coreclr/jit/gentree.cpp
@@ -11171,7 +11171,7 @@ GenTree* Compiler::gtCloneExpr(GenTree* tree)
GenTreeHWIntrinsic(tree->TypeGet(), IntrinsicNodeBuilder(getAllocator(CMK_ASTNode), tree->AsMultiOp()),
tree->AsHWIntrinsic()->GetHWIntrinsicId(), tree->AsHWIntrinsic()->GetSimdBaseType(),
tree->AsHWIntrinsic()->GetSimdSize());
- copy->AsHWIntrinsic()->SetAuxiliaryJitType(tree->AsHWIntrinsic()->GetAuxiliaryJitType());
+ copy->AsHWIntrinsic()->SetAuxiliaryType(tree->AsHWIntrinsic()->GetAuxiliaryType());
if (tree->AsHWIntrinsic()->IsUserCall())
{
@@ -21524,17 +21524,6 @@ void GenTreeJitIntrinsic::SetMethodHandle(Compiler* com
#endif // FEATURE_READYTORUN
}
-var_types GenTreeJitIntrinsic::GetAuxiliaryType() const
-{
- CorInfoType auxiliaryJitType = GetAuxiliaryJitType();
-
- if (auxiliaryJitType == CORINFO_TYPE_UNDEF)
- {
- return TYP_UNKNOWN;
- }
- return JitType2PreciseVarType(auxiliaryJitType);
-}
-
var_types GenTreeJitIntrinsic::GetSimdBaseType() const
{
return (var_types)gtSimdBaseType;
@@ -29497,13 +29486,13 @@ bool GenTreeHWIntrinsic::OperIsMemoryLoad(GenTree** pAddr) const
case NI_AVX2_ConvertToVector256Int16:
case NI_AVX2_ConvertToVector256Int32:
case NI_AVX2_ConvertToVector256Int64:
- if (GetAuxiliaryJitType() == CORINFO_TYPE_PTR)
+ if (GetAuxiliaryType() == TYP_U_IMPL)
{
addr = Op(1);
}
else
{
- assert(GetAuxiliaryJitType() == CORINFO_TYPE_UNDEF);
+ assert(GetAuxiliaryType() == TYP_UNKNOWN);
}
break;
@@ -33855,14 +33844,13 @@ GenTree* Compiler::gtFoldExprHWIntrinsic(GenTreeHWIntrinsic* tree)
}
}
#elif defined(TARGET_ARM64)
- CorInfoType auxJitType = tree->GetAuxiliaryJitType();
- if (auxJitType != CORINFO_TYPE_UNDEF &&
- genTypeSize(JITtype2varType(auxJitType)) != genTypeSize(simdBaseType))
+ var_types auxType = tree->GetAuxiliaryType();
+ if (auxType != TYP_UNKNOWN && genTypeSize(auxType) != genTypeSize(simdBaseType))
{
// Handle the "wide elements" variant of shift, where otherNode is a vector of ulongs,
// which is looped over to read the shift values. The values can safely be narrowed
// to the result type.
- assert(auxJitType == CORINFO_TYPE_ULONG);
+ assert(auxType == TYP_ULONG);
assert(tree->TypeIs(TYP_SIMD16));
simd16_t result = {};
diff --git a/src/coreclr/jit/gentree.h b/src/coreclr/jit/gentree.h
index 5d77e2218adfbe..e596769cbb96f2 100644
--- a/src/coreclr/jit/gentree.h
+++ b/src/coreclr/jit/gentree.h
@@ -6415,7 +6415,7 @@ struct GenTreeJitIntrinsic : public GenTreeMultiOp
};
regNumberSmall gtOtherReg; // The second register for multi-reg intrinsics.
MultiRegSpillFlags gtSpillFlags; // Spill flags for multi-reg intrinsics.
- unsigned char gtAuxiliaryJitType; // For intrinsics than need another type (e.g. Avx2.Gather* or SIMD (by element))
+ unsigned char gtAuxiliaryType; // For intrinsics than need another type (e.g. Avx2.Gather* or SIMD (by element))
unsigned char gtSimdBaseType; // SIMD vector base JIT type
unsigned char gtSimdSize; // SIMD vector size in bytes, use 0 for scalar intrinsics
NamedIntrinsic gtHWIntrinsicId;
@@ -6509,19 +6509,17 @@ struct GenTreeJitIntrinsic : public GenTreeMultiOp
gtSpillFlags = SetMultiRegSpillFlagsByIdx(gtSpillFlags, flags, idx);
}
- CorInfoType GetAuxiliaryJitType() const
+ var_types GetAuxiliaryType() const
{
- return (CorInfoType)gtAuxiliaryJitType;
+ return (var_types)gtAuxiliaryType;
}
- void SetAuxiliaryJitType(CorInfoType auxiliaryJitType)
+ void SetAuxiliaryType(var_types auxiliaryType)
{
- gtAuxiliaryJitType = (unsigned char)auxiliaryJitType;
- assert(gtAuxiliaryJitType == auxiliaryJitType);
+ gtAuxiliaryType = (unsigned char)auxiliaryType;
+ assert(gtAuxiliaryType == auxiliaryType);
}
- var_types GetAuxiliaryType() const;
-
// The invariant here is that simdBaseType is a converted
// CorInfoType using JitType2PreciseVarType.
void SetSimdBaseType(var_types simdBaseType)
@@ -6555,7 +6553,7 @@ struct GenTreeJitIntrinsic : public GenTreeMultiOp
: GenTreeMultiOp(oper, type, allocator, gtInlineOperands DEBUGARG(false), operands...)
, gtOtherReg(REG_NA)
, gtSpillFlags(0)
- , gtAuxiliaryJitType(CORINFO_TYPE_UNDEF)
+ , gtAuxiliaryType(TYP_UNKNOWN)
, gtSimdBaseType((unsigned char)simdBaseType)
, gtSimdSize((unsigned char)simdSize)
, gtHWIntrinsicId(NI_Illegal)
@@ -6581,7 +6579,7 @@ struct GenTreeJitIntrinsic : public GenTreeMultiOp
gtInlineOperands DEBUGARG(false))
, gtOtherReg(REG_NA)
, gtSpillFlags(0)
- , gtAuxiliaryJitType(CORINFO_TYPE_UNDEF)
+ , gtAuxiliaryType(TYP_UNKNOWN)
, gtSimdBaseType((unsigned char)simdBaseType)
, gtSimdSize((unsigned char)simdSize)
, gtHWIntrinsicId(NI_Illegal)
diff --git a/src/coreclr/jit/hwintrinsic.cpp b/src/coreclr/jit/hwintrinsic.cpp
index b4f2821f439a90..90afc3568edb70 100644
--- a/src/coreclr/jit/hwintrinsic.cpp
+++ b/src/coreclr/jit/hwintrinsic.cpp
@@ -2344,15 +2344,15 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic,
// We want to be able to differentiate between them so lets
// just track the aux type as a ptr or undefined, depending
- CorInfoType auxiliaryType = CORINFO_TYPE_UNDEF;
+ var_types auxiliaryType = TYP_UNKNOWN;
if (!varTypeIsSIMD(op1))
{
- auxiliaryType = CORINFO_TYPE_PTR;
+ auxiliaryType = TYP_U_IMPL;
retNode->gtFlags |= (GTF_EXCEPT | GTF_GLOB_REF);
}
- retNode->AsHWIntrinsic()->SetAuxiliaryJitType(auxiliaryType);
+ retNode->AsHWIntrinsic()->SetAuxiliaryType(auxiliaryType);
break;
}
@@ -2372,7 +2372,7 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic,
case NI_Sve_ConvertToUInt64:
// Save the base type of return SIMD. It is used to contain this intrinsic inside
// ConditionalSelect.
- retNode->AsHWIntrinsic()->SetAuxiliaryJitType(getBaseJitTypeOfSIMDType(sig->retTypeSigClass));
+ retNode->AsHWIntrinsic()->SetAuxiliaryType(getBaseTypeOfSIMDType(sig->retTypeSigClass));
break;
default:
break;
@@ -2407,12 +2407,12 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic,
case NI_AdvSimd_AddWideningUpper:
case NI_AdvSimd_SubtractWideningUpper:
assert(varTypeIsSIMD(op1->TypeGet()));
- retNode->AsHWIntrinsic()->SetAuxiliaryJitType(getBaseJitTypeOfSIMDType(sigReader.op1ClsHnd));
+ retNode->AsHWIntrinsic()->SetAuxiliaryType(getBaseTypeOfSIMDType(sigReader.op1ClsHnd));
break;
case NI_AdvSimd_Arm64_AddSaturateScalar:
assert(varTypeIsSIMD(op2->TypeGet()));
- retNode->AsHWIntrinsic()->SetAuxiliaryJitType(getBaseJitTypeOfSIMDType(sigReader.op2ClsHnd));
+ retNode->AsHWIntrinsic()->SetAuxiliaryType(getBaseTypeOfSIMDType(sigReader.op2ClsHnd));
break;
case NI_ArmBase_Arm64_MultiplyHigh:
@@ -2447,13 +2447,13 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic,
case NI_Sve_CreateWhileLessThanOrEqualMaskUInt16:
case NI_Sve_CreateWhileLessThanOrEqualMaskUInt32:
case NI_Sve_CreateWhileLessThanOrEqualMaskUInt64:
- retNode->AsHWIntrinsic()->SetAuxiliaryJitType(sigReader.op1JitType);
+ retNode->AsHWIntrinsic()->SetAuxiliaryType(JitType2PreciseVarType(sigReader.op1JitType));
break;
case NI_Sve_ShiftLeftLogical:
case NI_Sve_ShiftRightArithmetic:
case NI_Sve_ShiftRightLogical:
- retNode->AsHWIntrinsic()->SetAuxiliaryJitType(getBaseJitTypeOfSIMDType(sigReader.op2ClsHnd));
+ retNode->AsHWIntrinsic()->SetAuxiliaryType(getBaseTypeOfSIMDType(sigReader.op2ClsHnd));
break;
default:
@@ -2500,7 +2500,7 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic,
case NI_AVX2_GatherVector128:
case NI_AVX2_GatherVector256:
assert(varTypeIsSIMD(op2->TypeGet()));
- retNode->AsHWIntrinsic()->SetAuxiliaryJitType(getBaseJitTypeOfSIMDType(sigReader.op2ClsHnd));
+ retNode->AsHWIntrinsic()->SetAuxiliaryType(getBaseTypeOfSIMDType(sigReader.op2ClsHnd));
break;
#elif defined(TARGET_ARM64)
@@ -2543,8 +2543,8 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic,
assert(varTypeIsSIMD(op3->TypeGet()));
if (numArgs == 3)
{
- retNode->AsHWIntrinsic()->SetAuxiliaryJitType(
- getBaseJitTypeOfSIMDType(sigReader.op3ClsHnd));
+ retNode->AsHWIntrinsic()->SetAuxiliaryType(
+ getBaseTypeOfSIMDType(sigReader.op3ClsHnd));
}
break;
#endif
@@ -2568,8 +2568,8 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic,
assert(varTypeIsSIMD(op3->TypeGet()));
if (numArgs == 4)
{
- retNode->AsHWIntrinsic()->SetAuxiliaryJitType(
- getBaseJitTypeOfSIMDType(sigReader.op3ClsHnd));
+ retNode->AsHWIntrinsic()->SetAuxiliaryType(
+ getBaseTypeOfSIMDType(sigReader.op3ClsHnd));
}
break;
#endif
diff --git a/src/coreclr/jit/hwintrinsicarm64.cpp b/src/coreclr/jit/hwintrinsicarm64.cpp
index 838e6d24b093e0..7a3eb5a26ef331 100644
--- a/src/coreclr/jit/hwintrinsicarm64.cpp
+++ b/src/coreclr/jit/hwintrinsicarm64.cpp
@@ -3179,7 +3179,7 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
CORINFO_ARG_LIST_HANDLE arg = sig->args;
arg = info.compCompHnd->getArgNext(arg);
CORINFO_CLASS_HANDLE argClass = info.compCompHnd->getArgClass(sig, arg);
- CorInfoType ptrType = getBaseJitTypeOfSIMDType(argClass);
+ CorInfoType ptrType = CORINFO_TYPE_UNDEF;
CORINFO_CLASS_HANDLE tmpClass = NO_CLASS_HANDLE;
// The size of narrowed target elements is determined from the second argument of StoreNarrowing().
@@ -3195,7 +3195,7 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
op2 = impPopStack().val;
op1 = impPopStack().val;
retNode = gtNewSimdHWIntrinsicNode(retType, op1, op2, op3, intrinsic, simdBaseType, simdSize);
- retNode->AsHWIntrinsic()->SetAuxiliaryJitType(ptrType);
+ retNode->AsHWIntrinsic()->SetAuxiliaryType(JitType2PreciseVarType(ptrType));
break;
}
@@ -3266,7 +3266,7 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg1, &argClass)));
op1 = impPopStack().val;
- CorInfoType op1BaseJitType = getBaseJitTypeOfSIMDType(argClass);
+ var_types op1BaseType = getBaseTypeOfSIMDType(argClass);
// HWInstrinsic requires a mask for op2
if (!varTypeIsMask(op2))
@@ -3277,7 +3277,7 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
retNode = gtNewSimdHWIntrinsicNode(retType, op1, op2, intrinsic, simdBaseType, simdSize);
retNode->AsHWIntrinsic()->SetSimdBaseType(simdBaseType);
- retNode->AsHWIntrinsic()->SetAuxiliaryJitType(op1BaseJitType);
+ retNode->AsHWIntrinsic()->SetAuxiliaryType(op1BaseType);
break;
}
case NI_Sve_GatherPrefetch8Bit:
@@ -3311,11 +3311,11 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
assert(HWIntrinsicInfo::isImmOp(intrinsic, op3));
op3 = addRangeCheckIfNeeded(intrinsic, op3, immLowerBound, immUpperBound);
- argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg2, &argClass)));
- op2 = getArgForHWIntrinsic(argType, argClass);
- CorInfoType op2BaseJitType = getBaseJitTypeOfSIMDType(argClass);
- argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg1, &argClass)));
- op1 = impPopStack().val;
+ argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg2, &argClass)));
+ op2 = getArgForHWIntrinsic(argType, argClass);
+ var_types op2BaseType = getBaseTypeOfSIMDType(argClass);
+ argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg1, &argClass)));
+ op1 = impPopStack().val;
#ifdef DEBUG
@@ -3330,7 +3330,7 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
}
#endif
retNode = gtNewSimdHWIntrinsicNode(retType, op1, op2, op3, intrinsic, simdBaseType, simdSize);
- retNode->AsHWIntrinsic()->SetAuxiliaryJitType(op2BaseJitType);
+ retNode->AsHWIntrinsic()->SetAuxiliaryType(op2BaseType);
}
else
{
@@ -3341,17 +3341,17 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
assert(HWIntrinsicInfo::isImmOp(intrinsic, op4));
op4 = addRangeCheckIfNeeded(intrinsic, op4, immLowerBound, immUpperBound);
- argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg3, &argClass)));
- op3 = getArgForHWIntrinsic(argType, argClass);
- CorInfoType op3BaseJitType = getBaseJitTypeOfSIMDType(argClass);
- argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg2, &argClass)));
- op2 = getArgForHWIntrinsic(argType, argClass);
- argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg1, &argClass)));
- op1 = impPopStack().val;
+ argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg3, &argClass)));
+ op3 = getArgForHWIntrinsic(argType, argClass);
+ var_types op3BaseType = getBaseTypeOfSIMDType(argClass);
+ argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg2, &argClass)));
+ op2 = getArgForHWIntrinsic(argType, argClass);
+ argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg1, &argClass)));
+ op1 = impPopStack().val;
assert(varTypeIsSIMD(op3->TypeGet()));
retNode = gtNewSimdHWIntrinsicNode(retType, op1, op2, op3, op4, intrinsic, simdBaseType, simdSize);
- retNode->AsHWIntrinsic()->SetAuxiliaryJitType(op3BaseJitType);
+ retNode->AsHWIntrinsic()->SetAuxiliaryType(op3BaseType);
}
break;
@@ -3468,7 +3468,7 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
var_types argType1 = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg1, &argClass)));
var_types argType2 = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg2, &argClass)));
- CorInfoType op1BaseJitType = getBaseJitTypeOfSIMDType(argClass);
+ var_types op1BaseType = getBaseTypeOfSIMDType(argClass);
op2 = impPopStack().val;
op1 = impPopStack().val;
@@ -3480,7 +3480,7 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
op1 = gtConvertTableOpToFieldList(op1, fieldCount);
}
retNode = gtNewSimdHWIntrinsicNode(retType, op1, op2, intrinsic, simdBaseType, simdSize);
- retNode->AsHWIntrinsic()->SetAuxiliaryJitType(op1BaseJitType);
+ retNode->AsHWIntrinsic()->SetAuxiliaryType(op1BaseType);
break;
}
@@ -3500,10 +3500,10 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
op2 = impPopStack().val;
op1 = impPopStack().val;
- CorInfoType op1BaseJitType = getBaseJitTypeOfSIMDType(argClass);
- retNode = gtNewSimdHWIntrinsicNode(retType, op1, op2, intrinsic, simdBaseType, simdSize);
+ var_types op1BaseType = getBaseTypeOfSIMDType(argClass);
+ retNode = gtNewSimdHWIntrinsicNode(retType, op1, op2, intrinsic, simdBaseType, simdSize);
retNode->AsHWIntrinsic()->SetSimdBaseType(simdBaseType);
- retNode->AsHWIntrinsic()->SetAuxiliaryJitType(op1BaseJitType);
+ retNode->AsHWIntrinsic()->SetAuxiliaryType(op1BaseType);
break;
}
@@ -3516,18 +3516,18 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
CORINFO_ARG_LIST_HANDLE arg2 = info.compCompHnd->getArgNext(arg1);
CORINFO_CLASS_HANDLE argClass = NO_CLASS_HANDLE;
- var_types argType1 = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg1, &argClass)));
- CorInfoType op1BaseJitType = getBaseJitTypeOfSIMDType(argClass);
- var_types argType2 = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg2, &argClass)));
- CorInfoType op2BaseJitType = getBaseJitTypeOfSIMDType(argClass);
- assert(JitType2PreciseVarType(op1BaseJitType) == simdBaseType);
+ var_types argType1 = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg1, &argClass)));
+ var_types op1BaseType = getBaseTypeOfSIMDType(argClass);
+ var_types argType2 = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg2, &argClass)));
+ var_types op2BaseType = getBaseTypeOfSIMDType(argClass);
+ assert(op1BaseType == simdBaseType);
op2 = impPopStack().val;
op1 = impPopStack().val;
retNode = gtNewSimdHWIntrinsicNode(retType, op1, op2, intrinsic, simdBaseType, simdSize);
retNode->AsHWIntrinsic()->SetSimdBaseType(simdBaseType);
- retNode->AsHWIntrinsic()->SetAuxiliaryJitType(op2BaseJitType);
+ retNode->AsHWIntrinsic()->SetAuxiliaryType(op2BaseType);
break;
}
diff --git a/src/coreclr/jit/hwintrinsiclistarm64.h b/src/coreclr/jit/hwintrinsiclistarm64.h
index 1c6d080b66eaba..b127b61920d4b7 100644
--- a/src/coreclr/jit/hwintrinsiclistarm64.h
+++ b/src/coreclr/jit/hwintrinsiclistarm64.h
@@ -775,8 +775,8 @@ HARDWARE_INTRINSIC(Aes, PolynomialMultiplyWideningUpper,
// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
// Base Intrinsics
#define FIRST_NI_ArmBase NI_ArmBase_LeadingZeroCount
-HARDWARE_INTRINSIC(ArmBase, LeadingZeroCount, 0, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_clz, INS_clz, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Scalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_NoFloatingPointUsed)
-HARDWARE_INTRINSIC(ArmBase, ReverseElementBits, 0, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_rbit, INS_rbit, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Scalar, HW_Flag_NoFloatingPointUsed)
+HARDWARE_INTRINSIC(ArmBase, LeadingZeroCount, 0, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_clz, INS_clz, INS_clz, INS_clz, INS_invalid, INS_invalid}, HW_Category_Scalar, HW_Flag_BaseTypeFromFirstArg|HW_Flag_NoFloatingPointUsed)
+HARDWARE_INTRINSIC(ArmBase, ReverseElementBits, 0, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_rbit, INS_rbit, INS_rbit, INS_rbit, INS_invalid, INS_invalid}, HW_Category_Scalar, HW_Flag_NoFloatingPointUsed)
HARDWARE_INTRINSIC(ArmBase, Yield, 0, 0, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Special, HW_Flag_NoFloatingPointUsed|HW_Flag_SpecialCodeGen|HW_Flag_SpecialImport|HW_Flag_SpecialSideEffect_Other)
#define LAST_NI_ArmBase NI_ArmBase_Yield
@@ -801,8 +801,8 @@ HARDWARE_INTRINSIC(ArmBase_Arm64, ReverseElementBits,
// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
// CRC32 Intrinsics
#define FIRST_NI_Crc32 NI_Crc32_ComputeCrc32
-HARDWARE_INTRINSIC(Crc32, ComputeCrc32, 0, 2, {INS_invalid, INS_crc32b, INS_invalid, INS_crc32h, INS_invalid, INS_crc32w, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Scalar, HW_Flag_BaseTypeFromSecondArg|HW_Flag_NoFloatingPointUsed|HW_Flag_SpecialCodeGen)
-HARDWARE_INTRINSIC(Crc32, ComputeCrc32C, 0, 2, {INS_invalid, INS_crc32cb, INS_invalid, INS_crc32ch, INS_invalid, INS_crc32cw, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Scalar, HW_Flag_BaseTypeFromSecondArg|HW_Flag_NoFloatingPointUsed|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Crc32, ComputeCrc32, 0, 2, {INS_invalid, INS_crc32b, INS_invalid, INS_crc32h, INS_invalid, INS_crc32w, INS_invalid, INS_crc32x, INS_invalid, INS_invalid}, HW_Category_Scalar, HW_Flag_BaseTypeFromSecondArg|HW_Flag_NoFloatingPointUsed|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Crc32, ComputeCrc32C, 0, 2, {INS_invalid, INS_crc32cb, INS_invalid, INS_crc32ch, INS_invalid, INS_crc32cw, INS_invalid, INS_crc32cx, INS_invalid, INS_invalid}, HW_Category_Scalar, HW_Flag_BaseTypeFromSecondArg|HW_Flag_NoFloatingPointUsed|HW_Flag_SpecialCodeGen)
#define LAST_NI_Crc32 NI_Crc32_ComputeCrc32C
// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
diff --git a/src/coreclr/jit/hwintrinsicxarch.cpp b/src/coreclr/jit/hwintrinsicxarch.cpp
index ec2d51c27a179b..9c57cded52e184 100644
--- a/src/coreclr/jit/hwintrinsicxarch.cpp
+++ b/src/coreclr/jit/hwintrinsicxarch.cpp
@@ -5376,9 +5376,9 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
CORINFO_ARG_LIST_HANDLE arg2 = info.compCompHnd->getArgNext(argList);
CORINFO_ARG_LIST_HANDLE arg3 = info.compCompHnd->getArgNext(arg2);
- argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg3, &argClass)));
- CorInfoType op3BaseJitType = getBaseJitTypeOfSIMDType(argClass);
- GenTree* op3 = getArgForHWIntrinsic(argType, argClass);
+ argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg3, &argClass)));
+ var_types op3BaseType = getBaseTypeOfSIMDType(argClass);
+ GenTree* op3 = getArgForHWIntrinsic(argType, argClass);
argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg2, &argClass)));
op2 = getArgForHWIntrinsic(argType, argClass);
@@ -5387,7 +5387,7 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
op1 = getArgForHWIntrinsic(argType, argClass);
retNode = gtNewSimdHWIntrinsicNode(retType, op1, op2, op3, intrinsic, simdBaseType, simdSize);
- retNode->AsHWIntrinsic()->SetAuxiliaryJitType(op3BaseJitType);
+ retNode->AsHWIntrinsic()->SetAuxiliaryType(op3BaseType);
break;
}
@@ -5478,9 +5478,9 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
GenTree* op4 = getArgForHWIntrinsic(argType, argClass);
SetOpLclRelatedToSIMDIntrinsic(op4);
- argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg3, &argClass)));
- CorInfoType indexBaseJitType = getBaseJitTypeOfSIMDType(argClass);
- GenTree* op3 = getArgForHWIntrinsic(argType, argClass);
+ argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg3, &argClass)));
+ var_types indexBaseType = getBaseTypeOfSIMDType(argClass);
+ GenTree* op3 = getArgForHWIntrinsic(argType, argClass);
SetOpLclRelatedToSIMDIntrinsic(op3);
argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg2, &argClass)));
@@ -5493,7 +5493,7 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
retNode = new (this, GT_HWINTRINSIC) GenTreeHWIntrinsic(retType, getAllocator(CMK_ASTNode), intrinsic,
simdBaseType, simdSize, op1, op2, op3, op4, op5);
- retNode->AsHWIntrinsic()->SetAuxiliaryJitType(indexBaseJitType);
+ retNode->AsHWIntrinsic()->SetAuxiliaryType(indexBaseType);
break;
}
diff --git a/src/coreclr/jit/simd.cpp b/src/coreclr/jit/simd.cpp
index 66a65af1403865..f655f330e52259 100644
--- a/src/coreclr/jit/simd.cpp
+++ b/src/coreclr/jit/simd.cpp
@@ -479,307 +479,6 @@ var_types Compiler::getBaseTypeAndSizeOfSIMDType(CORINFO_CLASS_HANDLE typeHnd, u
return simdBaseType;
}
-CorInfoType Compiler::getBaseJitTypeAndSizeOfSIMDType(CORINFO_CLASS_HANDLE typeHnd, unsigned* sizeBytes /*= nullptr */)
-{
- if (m_simdHandleCache == nullptr)
- {
- if (impInlineInfo == nullptr)
- {
- m_simdHandleCache = new (this, CMK_Generic) SIMDHandlesCache();
- }
- else
- {
- // Steal the inliner compiler's cache (create it if not available).
-
- if (impInlineInfo->InlineRoot->m_simdHandleCache == nullptr)
- {
- impInlineInfo->InlineRoot->m_simdHandleCache = new (this, CMK_Generic) SIMDHandlesCache();
- }
-
- m_simdHandleCache = impInlineInfo->InlineRoot->m_simdHandleCache;
- }
- }
-
- if (sizeBytes != nullptr)
- {
- *sizeBytes = 0;
- }
-
- if ((typeHnd == nullptr) || !isIntrinsicType(typeHnd))
- {
- return CORINFO_TYPE_UNDEF;
- }
-
- const char* namespaceName;
- const char* className = getClassNameFromMetadata(typeHnd, &namespaceName);
-
- // fast path search using cached type handles of important types
- CorInfoType simdBaseJitType = CORINFO_TYPE_UNDEF;
- unsigned size = 0;
-
- if (isNumericsNamespace(namespaceName))
- {
- switch (className[0])
- {
- case 'P':
- {
- if (strcmp(className, "Plane") != 0)
- {
- return CORINFO_TYPE_UNDEF;
- }
-
- JITDUMP(" Known type Plane\n");
- m_simdHandleCache->PlaneHandle = typeHnd;
-
- simdBaseJitType = CORINFO_TYPE_FLOAT;
- size = 4 * genTypeSize(TYP_FLOAT);
- break;
- }
-
- case 'Q':
- {
- if (strcmp(className, "Quaternion") != 0)
- {
- return CORINFO_TYPE_UNDEF;
- }
-
- JITDUMP(" Known type Quaternion\n");
- m_simdHandleCache->QuaternionHandle = typeHnd;
-
- simdBaseJitType = CORINFO_TYPE_FLOAT;
- size = 4 * genTypeSize(TYP_FLOAT);
- break;
- }
-
- case 'V':
- {
- if (strncmp(className, "Vector", 6) != 0)
- {
- return CORINFO_TYPE_UNDEF;
- }
-
- switch (className[6])
- {
- case '\0':
- {
- JITDUMP(" Found type Vector\n");
- m_simdHandleCache->VectorHandle = typeHnd;
- break;
- }
-
- case '2':
- {
- if (className[7] != '\0')
- {
- return CORINFO_TYPE_UNDEF;
- }
-
- JITDUMP(" Found Vector2\n");
- m_simdHandleCache->Vector2Handle = typeHnd;
-
- simdBaseJitType = CORINFO_TYPE_FLOAT;
- size = 2 * genTypeSize(TYP_FLOAT);
- break;
- }
-
- case '3':
- {
- if (className[7] != '\0')
- {
- return CORINFO_TYPE_UNDEF;
- }
-
- JITDUMP(" Found Vector3\n");
- m_simdHandleCache->Vector3Handle = typeHnd;
-
- simdBaseJitType = CORINFO_TYPE_FLOAT;
- size = 3 * genTypeSize(TYP_FLOAT);
- break;
- }
-
- case '4':
- {
- if (className[7] != '\0')
- {
- return CORINFO_TYPE_UNDEF;
- }
-
- JITDUMP(" Found Vector4\n");
- m_simdHandleCache->Vector4Handle = typeHnd;
-
- simdBaseJitType = CORINFO_TYPE_FLOAT;
- size = 4 * genTypeSize(TYP_FLOAT);
- break;
- }
-
- case '`':
- {
- if ((className[7] != '1') || (className[8] != '\0'))
- {
- return CORINFO_TYPE_UNDEF;
- }
-
- CORINFO_CLASS_HANDLE typeArgHnd = info.compCompHnd->getTypeInstantiationArgument(typeHnd, 0);
- simdBaseJitType = info.compCompHnd->getTypeForPrimitiveNumericClass(typeArgHnd);
-
- if ((simdBaseJitType < CORINFO_TYPE_BYTE) || (simdBaseJitType > CORINFO_TYPE_DOUBLE))
- {
- return CORINFO_TYPE_UNDEF;
- }
-
- JITDUMP(" Found Vector<%s>\n", varTypeName(JitType2PreciseVarType(simdBaseJitType)));
-
-#if defined(DEBUG) && defined(TARGET_ARM64)
- if (JitConfig.JitUseScalableVectorT() &&
- compOpportunisticallyDependsOn(InstructionSet_Sve_Arm64))
- {
- size = SIZE_UNKNOWN;
- break;
- }
-#endif
- size = getVectorTByteLength();
-
- if (size == 0)
- {
- return CORINFO_TYPE_UNDEF;
- }
- break;
- }
-
- default:
- {
- return CORINFO_TYPE_UNDEF;
- }
- }
- break;
- }
-
- default:
- {
- return CORINFO_TYPE_UNDEF;
- }
- }
- }
-#ifdef FEATURE_HW_INTRINSICS
- else
- {
- size = info.compCompHnd->getClassSize(typeHnd);
-
- switch (size)
- {
-#if defined(TARGET_ARM64)
- case 8:
- {
- if (strcmp(className, "Vector64`1") != 0)
- {
- return CORINFO_TYPE_UNDEF;
- }
-
- CORINFO_CLASS_HANDLE typeArgHnd = info.compCompHnd->getTypeInstantiationArgument(typeHnd, 0);
- simdBaseJitType = info.compCompHnd->getTypeForPrimitiveNumericClass(typeArgHnd);
-
- if ((simdBaseJitType < CORINFO_TYPE_BYTE) || (simdBaseJitType > CORINFO_TYPE_DOUBLE))
- {
- return CORINFO_TYPE_UNDEF;
- }
-
- JITDUMP(" Found Vector64<%s>\n", varTypeName(JitType2PreciseVarType(simdBaseJitType)));
- break;
- }
-#endif // TARGET_ARM64
-
- case 16:
- {
- if (strcmp(className, "Vector128`1") != 0)
- {
- return CORINFO_TYPE_UNDEF;
- }
-
- CORINFO_CLASS_HANDLE typeArgHnd = info.compCompHnd->getTypeInstantiationArgument(typeHnd, 0);
- simdBaseJitType = info.compCompHnd->getTypeForPrimitiveNumericClass(typeArgHnd);
-
- if ((simdBaseJitType < CORINFO_TYPE_BYTE) || (simdBaseJitType > CORINFO_TYPE_DOUBLE))
- {
- return CORINFO_TYPE_UNDEF;
- }
-
- JITDUMP(" Found Vector128<%s>\n", varTypeName(JitType2PreciseVarType(simdBaseJitType)));
- break;
- }
-
-#if defined(TARGET_XARCH)
- case 32:
- {
- if (strcmp(className, "Vector256`1") != 0)
- {
- return CORINFO_TYPE_UNDEF;
- }
-
- CORINFO_CLASS_HANDLE typeArgHnd = info.compCompHnd->getTypeInstantiationArgument(typeHnd, 0);
- simdBaseJitType = info.compCompHnd->getTypeForPrimitiveNumericClass(typeArgHnd);
-
- if ((simdBaseJitType < CORINFO_TYPE_BYTE) || (simdBaseJitType > CORINFO_TYPE_DOUBLE))
- {
- return CORINFO_TYPE_UNDEF;
- }
-
- if (!compOpportunisticallyDependsOn(InstructionSet_AVX))
- {
- // We must treat as a regular struct if AVX isn't supported
- return CORINFO_TYPE_UNDEF;
- }
-
- JITDUMP(" Found Vector256<%s>\n", varTypeName(JitType2PreciseVarType(simdBaseJitType)));
- break;
- }
-
- case 64:
- {
- if (strcmp(className, "Vector512`1") != 0)
- {
- return CORINFO_TYPE_UNDEF;
- }
-
- CORINFO_CLASS_HANDLE typeArgHnd = info.compCompHnd->getTypeInstantiationArgument(typeHnd, 0);
- simdBaseJitType = info.compCompHnd->getTypeForPrimitiveNumericClass(typeArgHnd);
-
- if ((simdBaseJitType < CORINFO_TYPE_BYTE) || (simdBaseJitType > CORINFO_TYPE_DOUBLE))
- {
- return CORINFO_TYPE_UNDEF;
- }
-
- if (!compOpportunisticallyDependsOn(InstructionSet_AVX512))
- {
- // We must treat as a regular struct if AVX512 isn't supported
- return CORINFO_TYPE_UNDEF;
- }
-
- JITDUMP(" Found Vector512<%s>\n", varTypeName(JitType2PreciseVarType(simdBaseJitType)));
- break;
- }
-#endif // TARGET_XARCH
-
- default:
- {
- return CORINFO_TYPE_UNDEF;
- }
- }
- }
-#endif // FEATURE_HW_INTRINSICS
-
- if (sizeBytes != nullptr)
- {
- *sizeBytes = size;
- }
-
- if (simdBaseJitType != CORINFO_TYPE_UNDEF)
- {
- assert(size == info.compCompHnd->getClassSize(typeHnd) || size == SIZE_UNKNOWN);
- setUsesSIMDTypes(true);
- }
-
- return simdBaseJitType;
-}
//------------------------------------------------------------------------
// impSIMDPopStack: Pop a SIMD value from the importer's stack.
diff --git a/src/coreclr/jit/valuenum.cpp b/src/coreclr/jit/valuenum.cpp
index 3d76fd6333b04f..99a32f5cb455bf 100644
--- a/src/coreclr/jit/valuenum.cpp
+++ b/src/coreclr/jit/valuenum.cpp
@@ -8216,14 +8216,13 @@ ValueNum ValueNumStore::EvalHWIntrinsicFunBinary(
}
}
#elif defined(TARGET_ARM64)
- CorInfoType auxJitType = tree->GetAuxiliaryJitType();
- if (auxJitType != CORINFO_TYPE_UNDEF &&
- genTypeSize(JITtype2varType(auxJitType)) != genTypeSize(baseType))
+ var_types auxType = tree->GetAuxiliaryType();
+ if (auxType != TYP_UNKNOWN && genTypeSize(auxType) != genTypeSize(baseType))
{
// Handle the "wide elements" variant of shift, where arg1 is a vector of ulongs,
// which is looped over to read the shift values. The values can safely be narrowed
// to the result type.
- assert(auxJitType == CORINFO_TYPE_ULONG);
+ assert(auxType == TYP_ULONG);
assert(tree->TypeIs(TYP_SIMD16));
simd16_t arg1 = GetConstantSimd16(arg1VN);
diff --git a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/ArmBase.PlatformNotSupported.cs b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/ArmBase.PlatformNotSupported.cs
index de1f3bcd43c57e..f4f1b6fb94f44e 100644
--- a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/ArmBase.PlatformNotSupported.cs
+++ b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/ArmBase.PlatformNotSupported.cs
@@ -37,6 +37,9 @@ internal Arm64() { }
/// A64: CLS Xd, Xn
public static int LeadingSignCount(long value) { throw new PlatformNotSupportedException(); }
+ /// A64: CLS Xd, Xn
+ public static int LeadingSignCount(nint value) { throw new PlatformNotSupportedException(); }
+
/// A64: CLZ Xd, Xn
public static int LeadingZeroCount(long value) { throw new PlatformNotSupportedException(); }
@@ -68,6 +71,18 @@ internal Arm64() { }
///
public static int LeadingZeroCount(uint value) { throw new PlatformNotSupportedException(); }
+ ///
+ /// A32: CLZ Rd, Rm
+ /// A64: CLZ Xd, Xn
+ ///
+ public static int LeadingZeroCount(nint value) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// A32: CLZ Rd, Rm
+ /// A64: CLZ Xd, Xn
+ ///
+ public static int LeadingZeroCount(nuint value) { throw new PlatformNotSupportedException(); }
+
///
/// A32: RBIT Rd, Rm
/// A64: RBIT Wd, Wn
@@ -80,6 +95,18 @@ internal Arm64() { }
///
public static uint ReverseElementBits(uint value) { throw new PlatformNotSupportedException(); }
+ ///
+ /// A32: RBIT Rd, Rm
+ /// A64: RBIT Xd, Xn
+ ///
+ public static nint ReverseElementBits(nint value) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// A32: RBIT Rd, Rm
+ /// A64: RBIT Xd, Xn
+ ///
+ public static nuint ReverseElementBits(nuint value) { throw new PlatformNotSupportedException(); }
+
///
/// A32: YIELD
/// A64: YIELD
diff --git a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/ArmBase.cs b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/ArmBase.cs
index 570d8558309764..a9df04ee7af6a6 100644
--- a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/ArmBase.cs
+++ b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/ArmBase.cs
@@ -34,6 +34,9 @@ internal Arm64() { }
/// A64: CLS Xd, Xn
public static int LeadingSignCount(long value) => LeadingSignCount(value);
+ /// A64: CLS Xd, Xn
+ public static int LeadingSignCount(nint value) => LeadingSignCount(value);
+
/// A64: CLZ Xd, Xn
public static int LeadingZeroCount(long value) => LeadingZeroCount(value);
@@ -65,6 +68,18 @@ internal Arm64() { }
///
public static int LeadingZeroCount(uint value) => LeadingZeroCount(value);
+ ///
+ /// A32: CLZ Rd, Rm
+ /// A64: CLZ Xd, Xn
+ ///
+ public static int LeadingZeroCount(nint value) => LeadingZeroCount(value);
+
+ ///
+ /// A32: CLZ Rd, Rm
+ /// A64: CLZ Xd, Xn
+ ///
+ public static int LeadingZeroCount(nuint value) => LeadingZeroCount(value);
+
///
/// A32: RBIT Rd, Rm
/// A64: RBIT Wd, Wn
@@ -77,6 +92,18 @@ internal Arm64() { }
///
public static uint ReverseElementBits(uint value) => ReverseElementBits(value);
+ ///
+ /// A32: RBIT Rd, Rm
+ /// A64: RBIT Xd, Xn
+ ///
+ public static nint ReverseElementBits(nint value) => ReverseElementBits(value);
+
+ ///
+ /// A32: RBIT Rd, Rm
+ /// A64: RBIT Xd, Xn
+ ///
+ public static nuint ReverseElementBits(nuint value) => ReverseElementBits(value);
+
///
/// A32: YIELD
/// A64: YIELD
diff --git a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Crc32.PlatformNotSupported.cs b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Crc32.PlatformNotSupported.cs
index e1cc0b5fa314d3..38d48638569f7b 100644
--- a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Crc32.PlatformNotSupported.cs
+++ b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Crc32.PlatformNotSupported.cs
@@ -80,5 +80,17 @@ internal Arm64() { }
/// A64: CRC32CW Wd, Wn, Wm
///
public static uint ComputeCrc32C(uint crc, uint data) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// A32: CRC32W Rd, Rn, Rm
+ /// A64: CRC32X Wd, Wn, Xm
+ ///
+ public static uint ComputeCrc32(uint crc, nuint data) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// A32: CRC32CW Rd, Rn, Rm
+ /// A64: CRC32CX Wd, Wn, Xm
+ ///
+ public static uint ComputeCrc32C(uint crc, nuint data) { throw new PlatformNotSupportedException(); }
}
}
diff --git a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Crc32.cs b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Crc32.cs
index 8d51183f63fe85..e62e807cb0fb7a 100644
--- a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Crc32.cs
+++ b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Crc32.cs
@@ -82,5 +82,17 @@ internal Arm64() { }
/// A64: CRC32CW Wd, Wn, Wm
///
public static uint ComputeCrc32C(uint crc, uint data) => ComputeCrc32C(crc, data);
+
+ ///
+ /// A32: CRC32W Rd, Rn, Rm
+ /// A64: CRC32X Wd, Wn, Xm
+ ///
+ public static uint ComputeCrc32(uint crc, nuint data) => ComputeCrc32(crc, data);
+
+ ///
+ /// A32: CRC32CW Rd, Rn, Rm
+ /// A64: CRC32CX Wd, Wn, Xm
+ ///
+ public static uint ComputeCrc32C(uint crc, nuint data) => ComputeCrc32C(crc, data);
}
}
diff --git a/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs b/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs
index ada0999ed91e96..de7788351ca6da 100644
--- a/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs
+++ b/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs
@@ -5004,8 +5004,12 @@ public abstract partial class ArmBase
internal ArmBase() { }
public static bool IsSupported { get { throw null; } }
public static int LeadingZeroCount(int value) { throw null; }
+ public static int LeadingZeroCount(nint value) { throw null; }
+ public static int LeadingZeroCount(nuint value) { throw null; }
public static int LeadingZeroCount(uint value) { throw null; }
public static int ReverseElementBits(int value) { throw null; }
+ public static nint ReverseElementBits(nint value) { throw null; }
+ public static nuint ReverseElementBits(nuint value) { throw null; }
public static uint ReverseElementBits(uint value) { throw null; }
public static void Yield() { throw null; }
public abstract partial class Arm64
@@ -5014,6 +5018,7 @@ internal Arm64() { }
public static bool IsSupported { get { throw null; } }
public static int LeadingSignCount(int value) { throw null; }
public static int LeadingSignCount(long value) { throw null; }
+ public static int LeadingSignCount(nint value) { throw null; }
public static int LeadingZeroCount(long value) { throw null; }
public static int LeadingZeroCount(ulong value) { throw null; }
public static long MultiplyHigh(long left, long right) { throw null; }
@@ -5028,11 +5033,13 @@ public abstract partial class Crc32 : System.Runtime.Intrinsics.Arm.ArmBase
internal Crc32() { }
public static new bool IsSupported { get { throw null; } }
public static uint ComputeCrc32(uint crc, byte data) { throw null; }
- public static uint ComputeCrc32(uint crc, ushort data) { throw null; }
+ public static uint ComputeCrc32(uint crc, nuint data) { throw null; }
public static uint ComputeCrc32(uint crc, uint data) { throw null; }
+ public static uint ComputeCrc32(uint crc, ushort data) { throw null; }
public static uint ComputeCrc32C(uint crc, byte data) { throw null; }
- public static uint ComputeCrc32C(uint crc, ushort data) { throw null; }
+ public static uint ComputeCrc32C(uint crc, nuint data) { throw null; }
public static uint ComputeCrc32C(uint crc, uint data) { throw null; }
+ public static uint ComputeCrc32C(uint crc, ushort data) { throw null; }
public new abstract partial class Arm64 : System.Runtime.Intrinsics.Arm.ArmBase.Arm64
{
internal Arm64() { }
diff --git a/src/tests/Common/GenerateHWIntrinsicTests/Arm/BaseTests.cs b/src/tests/Common/GenerateHWIntrinsicTests/Arm/BaseTests.cs
index 33b189aef9a10b..c869df3c9bd98e 100644
--- a/src/tests/Common/GenerateHWIntrinsicTests/Arm/BaseTests.cs
+++ b/src/tests/Common/GenerateHWIntrinsicTests/Arm/BaseTests.cs
@@ -10,14 +10,19 @@ static class BaseTests
[
(Templates.ScalarUnOpTest, new Dictionary { ["TestName"] = "LeadingZeroCount_Int32", ["Method"] = "LeadingZeroCount", ["RetBaseType"] = "Int32", ["Op1BaseType"] = "Int32", ["NextValueOp1"] = "TestLibrary.Generator.GetInt32()", ["ValidateResult"] = "int expectedResult = 0; for (int index = 31; (((uint)data >> index) & 1) == 0; index--) { expectedResult++; } isUnexpectedResult = (expectedResult != result);" }),
(Templates.ScalarUnOpTest, new Dictionary { ["TestName"] = "LeadingZeroCount_UInt32", ["Method"] = "LeadingZeroCount", ["RetBaseType"] = "Int32", ["Op1BaseType"] = "UInt32", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt32()", ["ValidateResult"] = "int expectedResult = 0; for (int index = 31; ((data >> index) & 1) == 0; index--) { expectedResult++; } isUnexpectedResult = (expectedResult != result);" }),
+ (Templates.ScalarUnOpTest, new Dictionary { ["TestName"] = "LeadingZeroCount_IntPtr", ["Method"] = "LeadingZeroCount", ["RetBaseType"] = "Int32", ["Op1BaseType"] = "IntPtr", ["NextValueOp1"] = "(IntPtr)TestLibrary.Generator.GetInt64()", ["ValidateResult"] = "int expectedResult = 0; int bitSize = IntPtr.Size * 8; for (int index = bitSize - 1; (((ulong)(long)data >> index) & 1) == 0; index--) { expectedResult++; } isUnexpectedResult = (expectedResult != result);" }),
+ (Templates.ScalarUnOpTest, new Dictionary { ["TestName"] = "LeadingZeroCount_UIntPtr", ["Method"] = "LeadingZeroCount", ["RetBaseType"] = "Int32", ["Op1BaseType"] = "UIntPtr", ["NextValueOp1"] = "(UIntPtr)TestLibrary.Generator.GetUInt64()", ["ValidateResult"] = "int expectedResult = 0; int bitSize = UIntPtr.Size * 8; for (int index = bitSize - 1; (((ulong)data >> index) & 1) == 0; index--) { expectedResult++; } isUnexpectedResult = (expectedResult != result);" }),
(Templates.ScalarUnOpTest, new Dictionary { ["TestName"] = "ReverseElementBits_Int32", ["Method"] = "ReverseElementBits", ["RetBaseType"] = "Int32", ["Op1BaseType"] = "Int32", ["NextValueOp1"] = "TestLibrary.Generator.GetInt32()", ["ValidateResult"] = "isUnexpectedResult = Helpers.ReverseElementBits(data) != result;" }),
(Templates.ScalarUnOpTest, new Dictionary { ["TestName"] = "ReverseElementBits_UInt32", ["Method"] = "ReverseElementBits", ["RetBaseType"] = "UInt32", ["Op1BaseType"] = "UInt32", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt32()", ["ValidateResult"] = "isUnexpectedResult = Helpers.ReverseElementBits(data) != result;" }),
+ (Templates.ScalarUnOpTest, new Dictionary { ["TestName"] = "ReverseElementBits_IntPtr", ["Method"] = "ReverseElementBits", ["RetBaseType"] = "IntPtr", ["Op1BaseType"] = "IntPtr", ["NextValueOp1"] = "(IntPtr)TestLibrary.Generator.GetInt64()", ["ValidateResult"] = "isUnexpectedResult = Helpers.ReverseElementBits(data) != result;" }),
+ (Templates.ScalarUnOpTest, new Dictionary { ["TestName"] = "ReverseElementBits_UIntPtr", ["Method"] = "ReverseElementBits", ["RetBaseType"] = "UIntPtr", ["Op1BaseType"] = "UIntPtr", ["NextValueOp1"] = "(UIntPtr)TestLibrary.Generator.GetUInt64()", ["ValidateResult"] = "isUnexpectedResult = Helpers.ReverseElementBits(data) != result;" }),
]);
public static TestGroup ArmBase_Arm64Inputs = new TestGroup(Isa:"ArmBase.Arm64", LoadIsa:null,
[
(Templates.ScalarUnOpTest, new Dictionary { ["TestName"] = "LeadingSignCount_Int32", ["Method"] = "LeadingSignCount", ["RetBaseType"] = "Int32", ["Op1BaseType"] = "Int32", ["NextValueOp1"] = "TestLibrary.Generator.GetInt32()", ["ValidateResult"] = "int expectedResult = 0; for (int index = 30; (((uint)data >> index) & 1) == (((uint)data >> 31) & 1); index--) { expectedResult++; } isUnexpectedResult = (expectedResult != result);" }),
(Templates.ScalarUnOpTest, new Dictionary { ["TestName"] = "LeadingSignCount_Int64", ["Method"] = "LeadingSignCount", ["RetBaseType"] = "Int32", ["Op1BaseType"] = "Int64", ["NextValueOp1"] = "TestLibrary.Generator.GetInt64()", ["ValidateResult"] = "int expectedResult = 0; for (int index = 62; (((ulong)data >> index) & 1) == (((ulong)data >> 63) & 1); index--) { expectedResult++; } isUnexpectedResult = (expectedResult != result);" }),
+ (Templates.ScalarUnOpTest, new Dictionary { ["TestName"] = "LeadingSignCount_IntPtr", ["Method"] = "LeadingSignCount", ["RetBaseType"] = "Int32", ["Op1BaseType"] = "IntPtr", ["NextValueOp1"] = "(IntPtr)TestLibrary.Generator.GetInt64()", ["ValidateResult"] = "int expectedResult = 0; int bitSize = IntPtr.Size * 8; long signBit = ((long)data >> (bitSize - 1)) & 1; for (int index = bitSize - 2; (((ulong)(long)data >> index) & 1) == (ulong)signBit; index--) { expectedResult++; } isUnexpectedResult = (expectedResult != result);" }),
(Templates.ScalarUnOpTest, new Dictionary { ["TestName"] = "LeadingZeroCount_Int64", ["Method"] = "LeadingZeroCount", ["RetBaseType"] = "Int32", ["Op1BaseType"] = "Int64", ["NextValueOp1"] = "TestLibrary.Generator.GetInt64()", ["ValidateResult"] = "int expectedResult = 0; for (int index = 63; (((ulong)data >> index) & 1) == 0; index--) { expectedResult++; } isUnexpectedResult = (expectedResult != result);" }),
(Templates.ScalarUnOpTest, new Dictionary { ["TestName"] = "LeadingZeroCount_UInt64", ["Method"] = "LeadingZeroCount", ["RetBaseType"] = "Int32", ["Op1BaseType"] = "UInt64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt64()", ["ValidateResult"] = "int expectedResult = 0; for (int index = 63; ((data >> index) & 1) == 0; index--) { expectedResult++; } isUnexpectedResult = (expectedResult != result);" }),
(Templates.ScalarBinOpTest, new Dictionary { ["TestName"] = "MultiplyHigh_Int64", ["Method"] = "MultiplyHigh", ["RetBaseType"] = "Int64", ["Op1BaseType"] = "Int64", ["Op2BaseType"] = "Int64", ["NextValueOp1"] = "-TestLibrary.Generator.GetInt64()", ["NextValueOp2"] = "-TestLibrary.Generator.GetInt64()", ["ValidateResult"] = "isUnexpectedResult = Helpers.MultiplyHigh(left, right) != result;" }),