issue #9964 [VHDL] - type and name of type in type-generic entity are swapped

With update:
```
Commit: 4b155ef [4b155ef]
Date: Saturday, May 20, 2023 11:21:29 AM
parser update to vhdl2017
```
the part
```
         else if(m_sharedState->generic_sec){
          outlineParser()->addVhdlType(s.data(),outlineParser()->getLine(),Entry::VARIABLE_SEC,VhdlDocGen::GENERIC,s1.data(),s1.data(),Protection::Public);
         }
```
was, accidently, removed.
Reintroduced it and corrected the type line as indicated in #9964 (comment) also the `generic_sec` was not present anymore, test thtough `parse_sec`.

Author: albert-github

vhdlparser/VhdlParser.cc

@@ -7296,14 +7296,17 @@ QCString VhdlParser::interface_incomplete_type_declaration() {QCString s="type";
     s1 = identifier();
     }
 if (m_sharedState->currP!=VhdlDocGen::COMPONENT && m_sharedState->interf_sec==false)
+    {
+      if (m_sharedState->currP==VhdlDocGen::FUNCTION || m_sharedState->currP==VhdlDocGen::PROCEDURE)
       {
-          if (m_sharedState->currP==VhdlDocGen::FUNCTION || m_sharedState->currP==VhdlDocGen::PROCEDURE)
-        {
-          outlineParser()->addProto("",s1.data(),s.data(),"","","");
-        }
-
+        outlineParser()->addProto("",s1.data(),s.data(),"","","");
+      }
+      else if(m_sharedState->parse_sec==GEN_SEC)
+      {
+        outlineParser()->addVhdlType(s.data(),outlineParser()->getLine(),Entry::VARIABLE_SEC,VhdlDocGen::GENERIC,s1.data(),"",Protection::Public);
+      }
 
-    return s+" "+s1;
+      return s+" "+s1;
     }
 assert(false);
 }