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VHDL: repetition of use/library statement crashes doxygen (assert) (Origin: bugzilla #584192) #3409

doxygen opened this Issue Jul 2, 2018 · 0 comments


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doxygen commented Jul 2, 2018

status RESOLVED severity critical in component general for ---
Reported in version 1.5.9 on platform Other
Assigned to: Dimitri van Heesch

On 2009-05-29 09:51:09 +0000, Emanuel Schmid wrote:

Steps to reproduce:
A file as inserted below lets doxygen run into the assertion posted as stack trace.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
library test_top;
use test_top.jtag_conf.all;
use test_top.jtag_pkg.all;

entity tb_jtag_gotoBackup is
end tb_jtag_gotoBackup;

architecture rtl of tb_jtag_gotoBackup is

constant header : string := "tck tdi tms";


file out_file : text open write_mode is filename;
variable outline : line;
variable Addr : string_8;
variable Data : string_array;

 tdi_delay       <= 1; 
 wait for 1 us;

-- set the sleep register

Addr    := "FFEC0004";              
Data(0) := "FFFFFFFF";              
LoadMultRegister(1, Addr, Data);

Addr    := "FFEC0018";              
Data(0) := "00000000";              
LoadMultRegister(1, Addr, Data);

Addr    := "FFEC0028";      -- PM register in RTC
Data(0) := "00000000";      -- LDO2_en = MR_en = sleep_N = 0
LoadMultRegister(1, Addr, Data);


end process;

end rtl;

library work;
configuration cfg_tb_jtag_gotoBackup of tb_jtag_gotoBackup is
for RTL
end for;
end cfg_tb_jtag_gotoBackup;

Stack trace:
ASSERT: "cd!=0 || nd!=0 || fd!=0 || gd!=0" in vhdldocgen.cpp (1814)

Other information:
I'm not really sure what causes the problem. The following patch solved the issue for me, I don't see any regression - but I don't know what I break with that.

< VhdlDocGen::writeVHDLDeclarations(ml,ol,cd,0,0,gd,theTranslator_vhdlType(VhdlDocGen::LIBRARY,FALSE),0,FALSE,VhdlDocGen::LIBRARY);
< VhdlDocGen::writeVHDLDeclarations(ml,ol,cd,0,0,gd,theTranslator_vhdlType(VhdlDocGen::USE,FALSE),0,FALSE,VhdlDocGen::USE);

< VhdlDocGen::writeVHDLDeclarations(ml,ol,cd,0,0,gd,theTranslator_vhdlType(VhdlDocGen::COMPONENT,FALSE),0,FALSE,VhdlDocGen::COMPONENT);


On 2009-06-22 20:54:45 +0000, Dimitri van Heesch wrote:

I have received a patch from Martin Klein, which should fix this issue.
I'll be included in the next subversion update.

On 2009-08-20 10:13:07 +0000, Dimitri van Heesch wrote:

This bug was previously marked ASSIGNED, which means it should be fixed in
doxygen version 1.6.0. Please verify if this is indeed the case and reopen the
bug if you think it is not fixed (include any additional information that you
think can be relevant).

@doxygen doxygen closed this Jul 2, 2018

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