[VHDL] - Generic parameter list of generic subprograms are not printed

[ktbarrett]

Describe the bug
Generic parameter list of generic subprograms are not being printed.

Expected behavior
If a subprogram has a generic parameter list, it should be printed in addition to the regular parameter list.

Screenshots

To Reproduce

library ieee;
use ieee.std_logic_1164.all;

--! An example of a regular package
--!
--! This package contains stuff... nuff said.
package a_pack is

  --! Example Generic Procedure
  --!
  --! @tparam T type of the data of the DFF
  --! @param q output of DFF
  --! @param d input of DFF
  --! @param clk clock
  --! @param rst resets back to INIT
  --! @param en DFF enable
  --! @param INIT value to set the output to when rst is asserted
  procedure MyGenericProcedure
    generic (
      type T
    )
    parameter (
      signal   q    : inout T;
      constant d    : in    T;
      signal   clk  : in    std_logic;
      constant rst  : in    std_logic;
      constant en   : in    std_logic;
      constant INIT : in    T
    );

end package a_pack;

package body a_pack is
end package body a_pack;

> doxygen -x Doxyfile
# Difference with default Doxyfile 1.9.6
OPTIMIZE_OUTPUT_VHDL   = YES
EXTRACT_ALL            = YES
RECURSIVE              = YES
GENERATE_LATEX         = NO

Version
Doxygen 1.9.6

[albert-github]

You wrote:

If a subprogram has a generic parameter list, it should be printed in addition to the regular parameter list.

what should be shown / would you like to see?
(as not a VHDL programmer / user it is probably a lack in my knowledge and hence the request is a bit unclear)

[ktbarrett]

Something like the definition, just like the current output looks like a regular subprogram definition. So if there is a generic section it might look like this:

MyGenericProcedure
  generic (type T
          )
  parameter (signal q inout T,
             constant d in T,
             signal clk in std_logic,
             constant rst in std_logic,
             constant en in std_logic;
             constant INIT in T
            )

While non-generic subprograms look like the following without the parameter section

MyProcedure (signal q inout std_logic,
             constant d in std_logic,
             signal clk in std_logic,
             constant rst in std_logic,
             constant en in std_logic;
             constant INIT in std_logic
            )

[albert-github]

It is about the missing part:

  generic (type T
          )

in C++ terms this would be more like (left the procedure parameters in VHDL terms):

template <class T> 
MyGenericProcedure (signal q inout std_logic,
             constant d in std_logic,
             signal clk in std_logic,
             constant rst in std_logic,
             constant en in std_logic;
             constant INIT in std_logic
            )

so here we could have something like:

generic<type T>
MyGenericProcedure (signal q inout std_logic,
             constant d in std_logic,
             signal clk in std_logic,
             constant rst in std_logic,
             constant en in std_logic;
             constant INIT in std_logic
            )

[ktbarrett]

It is about the missing part:

  generic (type T
          )

Yes, that's the missing part.

so here we could have something like:

generic<type T>
MyGenericProcedure (signal q inout std_logic,
             constant d in std_logic,
             signal clk in std_logic,
             constant rst in std_logic,
             constant en in std_logic;
             constant INIT in std_logic
            )

I think this would be pretty unfamiliar to VHDL programmers.

[albert-github]

A proposed patch has been pushed, pull request #10043

[albert-github]

Code has been integrated in master on GitHub (please don't close the issue as this will be done at the moment of an official release).