{"payload":{"header_redesign_enabled":false,"results":[{"id":"111804481","archived":false,"color":"#b2b7f8","followers":15,"has_funding_file":false,"hl_name":"dqi/ed25519_fpga","hl_trunc_description":"Exploring the Ed25519 (FPGA) design space.","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":111804481,"name":"ed25519_fpga","owner_id":12663751,"owner_login":"dqi","updated_at":"2017-11-23T13:14:11.893Z","has_issues":true}},"sponsorable":false,"topics":["fpga","verilog","ed25519","curve25519","hsm"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":72,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Adqi%252Fed25519_fpga%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/dqi/ed25519_fpga/star":{"post":"XBExaLzeSxhd0N4okMqCvN6xQtVwHYw0KLLO9KsnzZupqlD3aWNjqKTvwWDu243qadM7dN-cMXHukTS5-ocSnw"},"/dqi/ed25519_fpga/unstar":{"post":"hfw5gZNTOKiyS_C4BotWoNqQgbJWtA69D94J9-q6ob4l4FR_KmvGFs2Wc6CSQ35ESflMcF43A11Y6a7Agj5Mtw"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"mY7vwyB3SM_mMCh-SmjV1LNucnrpPlc09yEN_ndpoh5FYFJs7I804l45kNuuRVUUJnVBJtsRPzIZ0kBjWdWkkg"}}},"title":"Repository search results"}