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Educational load/store instruction set architecture processor simulator
Verilog C C++ Other
branch: master

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cdlsim
cdltwo
cpld/pico/machx02
drafts
fpga
vbcc
verilator
LEARNASM.txt
Makefile
README
README.cdl.txt
README.txt
README.vbcc.txt
README.verilator.txt
lsa-as.c
lsa-diss.c
lsa-isa.txt
lsa-sim.c
lsa.cdl
test.s

README

see README.txt

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