diff --git a/instructionAPI/arm_manual_parser.py b/instructionAPI/arm_manual_parser.py index d155119d0f..52df489d15 100755 --- a/instructionAPI/arm_manual_parser.py +++ b/instructionAPI/arm_manual_parser.py @@ -1045,7 +1045,7 @@ def make_instruction_table(self): insn.info['mnemonic']) entry = ' {aarch32_op_%s, "%s", %s, 0x%08x, 0x%08x}' % ( insn.id, - mnemonic.lower() + ' ' + insn.id, + mnemonic.lower(), # + ' ' + insn.id, self.join_instruction_operands(insn), int(insn.bitList), int(insn.bitList.get_mask()) @@ -1158,7 +1158,7 @@ def generate_decode_source(self): // // Static functions for use in this file only. // -#define DEBUG_AARCH32_DECODE 1 +#define DEBUG_AARCH32_DECODE 0 #if DEBUG_AARCH32_DECODE static void print_bin(FILE* fp, uint32_t insn) diff --git a/instructionAPI/src/aarch32_decoder_autogen.C b/instructionAPI/src/aarch32_decoder_autogen.C index 3bc22e2f89..886f3945ec 100644 --- a/instructionAPI/src/aarch32_decoder_autogen.C +++ b/instructionAPI/src/aarch32_decoder_autogen.C @@ -88,1118 +88,1118 @@ typedef struct Insn_Entry { } Insn_Entry_t; static Insn_Entry_t insnTable[] = { - {aarch32_op_ADC_i_A1, "adc ADC_i_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x02a00000, 0x0ff00000}, - {aarch32_op_ADCS_i_A1, "adcs ADCS_i_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x02b00000, 0x0ff00000}, - {aarch32_op_ADC_r_A1_RRX, "adc ADC_r_A1_RRX", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00a00060, 0x0ff00ff0}, - {aarch32_op_ADC_r_A1, "adc ADC_r_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00a00000, 0x0ff00010}, - {aarch32_op_ADCS_r_A1_RRX, "adcs ADCS_r_A1_RRX", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00b00060, 0x0ff00ff0}, - {aarch32_op_ADCS_r_A1, "adcs ADCS_r_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00b00000, 0x0ff00010}, - {aarch32_op_ADCS_rr_A1, "adcs ADCS_rr_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x00b00010, 0x0ff00090}, - {aarch32_op_ADC_rr_A1, "adc ADC_rr_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x00a00010, 0x0ff00090}, - {aarch32_op_ADD_ADR_A1, "add ADD_ADR_A1", {OPR_reg_Rd, OPR_imm_const}, 0x028f0000, 0x0fff0000}, - {aarch32_op_ADD_i_A1, "add ADD_i_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x02800000, 0x0ff00000}, - {aarch32_op_ADDS_i_A1, "adds ADDS_i_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x02900000, 0x0ff00000}, - {aarch32_op_ADD_r_A1_RRX, "add ADD_r_A1_RRX", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00800060, 0x0ff00ff0}, - {aarch32_op_ADD_r_A1, "add ADD_r_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00800000, 0x0ff00010}, - {aarch32_op_ADDS_r_A1_RRX, "adds ADDS_r_A1_RRX", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00900060, 0x0ff00ff0}, - {aarch32_op_ADDS_r_A1, "adds ADDS_r_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00900000, 0x0ff00010}, - {aarch32_op_ADDS_rr_A1, "adds ADDS_rr_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x00900010, 0x0ff00090}, - {aarch32_op_ADD_rr_A1, "add ADD_rr_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x00800010, 0x0ff00090}, - {aarch32_op_ADD_SP_i_A1, "add ADD_SP_i_A1", {OPR_reg_Rd, OPR_imm_const}, 0x028d0000, 0x0fff0000}, - {aarch32_op_ADDS_SP_i_A1, "adds ADDS_SP_i_A1", {OPR_reg_Rd, OPR_imm_const}, 0x029d0000, 0x0fff0000}, - {aarch32_op_ADD_SP_r_A1_RRX, "add ADD_SP_r_A1_RRX", {OPR_reg_Rd, OPR_reg_Rm}, 0x008d0060, 0x0fff0ff0}, - {aarch32_op_ADD_SP_r_A1, "add ADD_SP_r_A1", {OPR_reg_Rd, OPR_reg_Rm}, 0x008d0000, 0x0fff0010}, - {aarch32_op_ADDS_SP_r_A1_RRX, "adds ADDS_SP_r_A1_RRX", {OPR_reg_Rd, OPR_reg_Rm}, 0x009d0060, 0x0fff0ff0}, - {aarch32_op_ADDS_SP_r_A1, "adds ADDS_SP_r_A1", {OPR_reg_Rd, OPR_reg_Rm}, 0x009d0000, 0x0fff0010}, - {aarch32_op_ADR_A1, "adr ADR_A1", {OPR_reg_Rd, OPR_imm_label}, 0x028f0000, 0x0fff0000}, - {aarch32_op_ADR_A2, "adr ADR_A2", {OPR_reg_Rd, OPR_imm_label}, 0x024f0000, 0x0fff0000}, - {aarch32_op_AESD_A1, "aesd AESD_A1", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b00340, 0xffb30fd0}, - {aarch32_op_AESE_A1, "aese AESE_A1", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b00300, 0xffb30fd0}, - {aarch32_op_AESIMC_A1, "aesimc AESIMC_A1", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b003c0, 0xffb30fd0}, - {aarch32_op_AESMC_A1, "aesmc AESMC_A1", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b00380, 0xffb30fd0}, - {aarch32_op_AND_i_A1, "and AND_i_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x02000000, 0x0ff00000}, - {aarch32_op_ANDS_i_A1, "ands ANDS_i_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x02100000, 0x0ff00000}, - {aarch32_op_AND_r_A1_RRX, "and AND_r_A1_RRX", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00000060, 0x0ff00ff0}, - {aarch32_op_AND_r_A1, "and AND_r_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00000000, 0x0ff00010}, - {aarch32_op_ANDS_r_A1_RRX, "ands ANDS_r_A1_RRX", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00100060, 0x0ff00ff0}, - {aarch32_op_ANDS_r_A1, "ands ANDS_r_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00100000, 0x0ff00010}, - {aarch32_op_ANDS_rr_A1, "ands ANDS_rr_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x00100010, 0x0ff00090}, - {aarch32_op_AND_rr_A1, "and AND_rr_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x00000010, 0x0ff00090}, - {aarch32_op_ASR_MOV_r_A1, "asr ASR_MOV_r_A1", {OPR_reg_Rd, OPR_reg_Rm}, 0x01a00040, 0x0ff00070}, - {aarch32_op_ASR_MOV_rr_A1, "asr ASR_MOV_rr_A1", {OPR_reg_Rd, OPR_reg_Rm, OPR_reg_Rs}, 0x01a00050, 0x0ff000f0}, - {aarch32_op_ASRS_MOVS_r_A1, "asrs ASRS_MOVS_r_A1", {OPR_reg_Rd, OPR_reg_Rm}, 0x01b00040, 0x0ff00070}, - {aarch32_op_ASRS_MOVS_rr_A1, "asrs ASRS_MOVS_rr_A1", {OPR_reg_Rd, OPR_reg_Rm, OPR_reg_Rs}, 0x01b00050, 0x0ff000f0}, - {aarch32_op_B_A1, "b B_A1", {OPR_imm_label_2}, 0x0a000000, 0x0f000000}, - {aarch32_op_BFC_A1, "bfc BFC_A1", {OPR_reg_Rd}, 0x07c0001f, 0x0fe0007f}, - {aarch32_op_BFI_A1, "bfi BFI_A1", {OPR_reg_Rd, OPR_reg_Rn_2}, 0x07c00010, 0x0fe00070}, - {aarch32_op_BIC_i_A1, "bic BIC_i_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x03c00000, 0x0ff00000}, - {aarch32_op_BICS_i_A1, "bics BICS_i_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x03d00000, 0x0ff00000}, - {aarch32_op_BIC_r_A1_RRX, "bic BIC_r_A1_RRX", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x01c00060, 0x0ff00ff0}, - {aarch32_op_BIC_r_A1, "bic BIC_r_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x01c00000, 0x0ff00010}, - {aarch32_op_BICS_r_A1_RRX, "bics BICS_r_A1_RRX", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x01d00060, 0x0ff00ff0}, - {aarch32_op_BICS_r_A1, "bics BICS_r_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x01d00000, 0x0ff00010}, - {aarch32_op_BICS_rr_A1, "bics BICS_rr_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x01d00010, 0x0ff00090}, - {aarch32_op_BIC_rr_A1, "bic BIC_rr_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x01c00010, 0x0ff00090}, - {aarch32_op_BKPT_A1, "bkpt BKPT_A1", {}, 0x01200070, 0x0ff000f0}, - {aarch32_op_BL_i_A1, "bl BL_i_A1", {OPR_imm_label}, 0x0b000000, 0x0f000000}, - {aarch32_op_BL_i_A2, "blx BL_i_A2", {OPR_imm_label_3}, 0xfa000000, 0xfe000000}, - {aarch32_op_BLX_r_A1, "blx BLX_r_A1", {OPR_reg_Rm}, 0x01200030, 0x0ff000f0}, - {aarch32_op_BX_A1, "bx BX_A1", {OPR_reg_Rm}, 0x01200010, 0x0ff000f0}, - {aarch32_op_BXJ_A1, "bxj BXJ_A1", {OPR_reg_Rm}, 0x01200020, 0x0ff000f0}, - {aarch32_op_CLREX_A1, "clrex CLREX_A1", {}, 0xf5700010, 0xfff000f0}, - {aarch32_op_CLZ_A1, "clz CLZ_A1", {OPR_reg_Rd, OPR_reg_Rm}, 0x01600010, 0x0ff000f0}, - {aarch32_op_CMN_i_A1, "cmn CMN_i_A1", {OPR_reg_Rn, OPR_imm_const}, 0x03700000, 0x0ff00000}, - {aarch32_op_CMN_r_A1_RRX, "cmn CMN_r_A1_RRX", {OPR_reg_Rn, OPR_reg_Rm}, 0x01700060, 0x0ff00ff0}, - {aarch32_op_CMN_r_A1, "cmn CMN_r_A1", {OPR_reg_Rn, OPR_reg_Rm}, 0x01700000, 0x0ff00010}, - {aarch32_op_CMN_rr_A1, "cmn CMN_rr_A1", {OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x01700010, 0x0ff00090}, - {aarch32_op_CMP_i_A1, "cmp CMP_i_A1", {OPR_reg_Rn, OPR_imm_const}, 0x03500000, 0x0ff00000}, - {aarch32_op_CMP_r_A1_RRX, "cmp CMP_r_A1_RRX", {OPR_reg_Rn, OPR_reg_Rm}, 0x01500060, 0x0ff00ff0}, - {aarch32_op_CMP_r_A1, "cmp CMP_r_A1", {OPR_reg_Rn, OPR_reg_Rm}, 0x01500000, 0x0ff00010}, - {aarch32_op_CMP_rr_A1, "cmp CMP_rr_A1", {OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x01500010, 0x0ff00090}, - {aarch32_op_CPS_A1_AS, "cps CPS_A1_AS", {}, 0xf1020000, 0xffff0020}, - {aarch32_op_CPSID_A1_AS, "cpsid CPSID_A1_AS", {}, 0xf10c0000, 0xffff0020}, - {aarch32_op_CPSID_A1_ASM, "cpsid CPSID_A1_ASM", {}, 0xf10e0000, 0xffff0020}, - {aarch32_op_CPSIE_A1_AS, "cpsie CPSIE_A1_AS", {}, 0xf1080000, 0xffff0020}, - {aarch32_op_CPSIE_A1_ASM, "cpsie CPSIE_A1_ASM", {}, 0xf10a0000, 0xffff0020}, - {aarch32_op_CRC32B_A1, "crc32b CRC32B_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x01000040, 0x0ff002f0}, - {aarch32_op_CRC32H_A1, "crc32h CRC32H_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x01200040, 0x0ff002f0}, - {aarch32_op_CRC32W_A1, "crc32w CRC32W_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x01400040, 0x0ff002f0}, - {aarch32_op_CRC32CB_A1, "crc32cb CRC32CB_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x01000240, 0x0ff002f0}, - {aarch32_op_CRC32CH_A1, "crc32ch CRC32CH_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x01200240, 0x0ff002f0}, - {aarch32_op_CRC32CW_A1, "crc32cw CRC32CW_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x01400240, 0x0ff002f0}, - {aarch32_op_DBG_A1, "dbg DBG_A1", {}, 0x032000f0, 0x0fff00f0}, - {aarch32_op_DMB_A1, "dmb DMB_A1", {}, 0xf5700050, 0xfff000f0}, - {aarch32_op_DSB_A1, "dsb DSB_A1", {}, 0xf5700040, 0xfff000f0}, - {aarch32_op_EOR_i_A1, "eor EOR_i_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x02200000, 0x0ff00000}, - {aarch32_op_EORS_i_A1, "eors EORS_i_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x02300000, 0x0ff00000}, - {aarch32_op_EOR_r_A1_RRX, "eor EOR_r_A1_RRX", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00200060, 0x0ff00ff0}, - {aarch32_op_EOR_r_A1, "eor EOR_r_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00200000, 0x0ff00010}, - {aarch32_op_EORS_r_A1_RRX, "eors EORS_r_A1_RRX", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00300060, 0x0ff00ff0}, - {aarch32_op_EORS_r_A1, "eors EORS_r_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00300000, 0x0ff00010}, - {aarch32_op_EORS_rr_A1, "eors EORS_rr_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x00300010, 0x0ff00090}, - {aarch32_op_EOR_rr_A1, "eor EOR_rr_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x00200010, 0x0ff00090}, - {aarch32_op_ERET_A1, "eret ERET_A1", {}, 0x01600060, 0x0ff000f0}, - {aarch32_op_ESB_A1, "esb ESB_A1", {}, 0x03200010, 0x0fff00ff}, - {aarch32_op_FLDMDBX_A1, "fldmdbx FLDMDBX_A1", {OPR_reg_Rn}, 0x0d300b01, 0x0fb00f01}, - {aarch32_op_FLDMIAX_A1, "fldmiax FLDMIAX_A1", {OPR_reg_Rn}, 0x0c900b01, 0x0f900f01}, - {aarch32_op_FSTMDBX_A1, "fstmdbx FSTMDBX_A1", {OPR_reg_Rn}, 0x0d200b01, 0x0fb00f01}, - {aarch32_op_FSTMIAX_A1, "fstmiax FSTMIAX_A1", {OPR_reg_Rn}, 0x0c800b01, 0x0f900f01}, - {aarch32_op_HLT_A1, "hlt HLT_A1", {}, 0x01000070, 0x0ff000f0}, - {aarch32_op_HVC_A1, "hvc HVC_A1", {}, 0x01400070, 0x0ff000f0}, - {aarch32_op_ISB_A1, "isb ISB_A1", {}, 0xf5700060, 0xfff000f0}, - {aarch32_op_LDA_A1, "lda LDA_A1", {OPR_reg_Rt, OPR_reg_Rn}, 0x01900090, 0x0ff003f0}, - {aarch32_op_LDAB_A1, "ldab LDAB_A1", {OPR_reg_Rt, OPR_reg_Rn}, 0x01d00090, 0x0ff003f0}, - {aarch32_op_LDAEX_A1, "ldaex LDAEX_A1", {OPR_reg_Rt, OPR_reg_Rn}, 0x01900290, 0x0ff003f0}, - {aarch32_op_LDAEXB_A1, "ldaexb LDAEXB_A1", {OPR_reg_Rt, OPR_reg_Rn}, 0x01d00290, 0x0ff003f0}, - {aarch32_op_LDAEXD_A1, "ldaexd LDAEXD_A1", {OPR_reg_Rt, OPR_reg_Rt2, OPR_reg_Rn}, 0x01b00290, 0x0ff003f0}, - {aarch32_op_LDAEXH_A1, "ldaexh LDAEXH_A1", {OPR_reg_Rt, OPR_reg_Rn}, 0x01f00290, 0x0ff003f0}, - {aarch32_op_LDAH_A1, "ldah LDAH_A1", {OPR_reg_Rt, OPR_reg_Rn}, 0x01f00090, 0x0ff003f0}, - {aarch32_op_LDC_i_A1_off, "ldc LDC_i_A1_off", {OPR_reg_Rn}, 0x0d105e00, 0x0f70ff00}, - {aarch32_op_LDC_i_A1_post, "ldc LDC_i_A1_post", {OPR_reg_Rn_3}, 0x0c305e00, 0x0f70ff00}, - {aarch32_op_LDC_i_A1_pre, "ldc LDC_i_A1_pre", {OPR_reg_Rn}, 0x0d305e00, 0x0f70ff00}, - {aarch32_op_LDC_i_A1_unind, "ldc LDC_i_A1_unind", {OPR_reg_Rn}, 0x0c905e00, 0x0ff0ff00}, - {aarch32_op_LDC_l_A1, "ldc LDC_l_A1", {OPR_imm_label_4}, 0x0c1f5e00, 0x0e1fff00}, - {aarch32_op_LDM_A1, "ldm LDM_A1", {OPR_reg_Rn, OPR_reglist}, 0x08900000, 0x0fd00000}, - {aarch32_op_LDM_e_A1_AS, "ldm LDM_e_A1_AS", {OPR_reg_Rn, OPR_reglist_2}, 0x08508000, 0x0e508000}, - {aarch32_op_LDM_u_A1_AS, "ldm LDM_u_A1_AS", {OPR_reg_Rn, OPR_reglist}, 0x08500000, 0x0e508000}, - {aarch32_op_LDMDA_A1, "ldm LDMDA_A1", {OPR_reg_Rn, OPR_reglist}, 0x08100000, 0x0fd00000}, - {aarch32_op_LDMDB_A1, "ldm LDMDB_A1", {OPR_reg_Rn, OPR_reglist}, 0x09100000, 0x0fd00000}, - {aarch32_op_LDMIB_A1, "ldm LDMIB_A1", {OPR_reg_Rn, OPR_reglist}, 0x09900000, 0x0fd00000}, - {aarch32_op_LDR_i_A1_off, "ldr LDR_i_A1_off", {OPR_reg_Rt, OPR_reg_Rn}, 0x05100000, 0x0f700000}, - {aarch32_op_LDR_i_A1_post, "ldr LDR_i_A1_post", {OPR_reg_Rt, OPR_reg_Rn}, 0x04100000, 0x0f700000}, - {aarch32_op_LDR_i_A1_pre, "ldr LDR_i_A1_pre", {OPR_reg_Rt, OPR_reg_Rn}, 0x05300000, 0x0f700000}, - {aarch32_op_LDR_l_A1, "ldr LDR_l_A1", {OPR_reg_Rt, OPR_imm_label_5}, 0x041f0000, 0x0e5f0000}, - {aarch32_op_LDR_r_A1_off, "ldr LDR_r_A1_off", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x07100000, 0x0f700010}, - {aarch32_op_LDR_r_A1_post, "ldr LDR_r_A1_post", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x06100000, 0x0f700010}, - {aarch32_op_LDR_r_A1_pre, "ldr LDR_r_A1_pre", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x07300000, 0x0f700010}, - {aarch32_op_LDRB_i_A1_off, "ldrb LDRB_i_A1_off", {OPR_reg_Rt, OPR_reg_Rn}, 0x05500000, 0x0f700000}, - {aarch32_op_LDRB_i_A1_post, "ldrb LDRB_i_A1_post", {OPR_reg_Rt, OPR_reg_Rn}, 0x04500000, 0x0f700000}, - {aarch32_op_LDRB_i_A1_pre, "ldrb LDRB_i_A1_pre", {OPR_reg_Rt, OPR_reg_Rn}, 0x05700000, 0x0f700000}, - {aarch32_op_LDRB_l_A1, "ldrb LDRB_l_A1", {OPR_reg_Rt, OPR_imm_label}, 0x045f0000, 0x0e5f0000}, - {aarch32_op_LDRB_r_A1_off, "ldrb LDRB_r_A1_off", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x07500000, 0x0f700010}, - {aarch32_op_LDRB_r_A1_post, "ldrb LDRB_r_A1_post", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x06500000, 0x0f700010}, - {aarch32_op_LDRB_r_A1_pre, "ldrb LDRB_r_A1_pre", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x07700000, 0x0f700010}, - {aarch32_op_LDRBT_A1, "ldrbt LDRBT_A1", {OPR_reg_Rt, OPR_reg_Rn}, 0x04700000, 0x0f700000}, - {aarch32_op_LDRBT_A2, "ldrbt LDRBT_A2", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x06700000, 0x0f700010}, - {aarch32_op_LDRD_i_A1_off, "ldrd LDRD_i_A1_off", {OPR_reg_Rt, OPR_reg_Rt2, OPR_reg_Rn}, 0x014000d0, 0x0f7000f0}, - {aarch32_op_LDRD_i_A1_post, "ldrd LDRD_i_A1_post", {OPR_reg_Rt, OPR_reg_Rt2, OPR_reg_Rn}, 0x004000d0, 0x0f7000f0}, - {aarch32_op_LDRD_i_A1_pre, "ldrd LDRD_i_A1_pre", {OPR_reg_Rt, OPR_reg_Rt2, OPR_reg_Rn}, 0x016000d0, 0x0f7000f0}, - {aarch32_op_LDRD_l_A1, "ldrd LDRD_l_A1", {OPR_reg_Rt, OPR_reg_Rt2, OPR_imm_label_6}, 0x004f00d0, 0x0e5f00f0}, - {aarch32_op_LDRD_r_A1_off, "ldrd LDRD_r_A1_off", {OPR_reg_Rt, OPR_reg_Rt2, OPR_reg_Rn, OPR_reg_Rm}, 0x010000d0, 0x0f7000f0}, - {aarch32_op_LDRD_r_A1_post, "ldrd LDRD_r_A1_post", {OPR_reg_Rt, OPR_reg_Rt2, OPR_reg_Rn, OPR_reg_Rm}, 0x000000d0, 0x0f7000f0}, - {aarch32_op_LDRD_r_A1_pre, "ldrd LDRD_r_A1_pre", {OPR_reg_Rt, OPR_reg_Rt2, OPR_reg_Rn, OPR_reg_Rm}, 0x012000d0, 0x0f7000f0}, - {aarch32_op_LDREX_A1, "ldrex LDREX_A1", {OPR_reg_Rt, OPR_reg_Rn}, 0x01900390, 0x0ff003f0}, - {aarch32_op_LDREXB_A1, "ldrexb LDREXB_A1", {OPR_reg_Rt, OPR_reg_Rn}, 0x01d00390, 0x0ff003f0}, - {aarch32_op_LDREXD_A1, "ldrexd LDREXD_A1", {OPR_reg_Rt, OPR_reg_Rt2, OPR_reg_Rn}, 0x01b00390, 0x0ff003f0}, - {aarch32_op_LDREXH_A1, "ldrexh LDREXH_A1", {OPR_reg_Rt, OPR_reg_Rn}, 0x01f00390, 0x0ff003f0}, - {aarch32_op_LDRH_i_A1_off, "ldrh LDRH_i_A1_off", {OPR_reg_Rt, OPR_reg_Rn}, 0x015000b0, 0x0f7000f0}, - {aarch32_op_LDRH_i_A1_post, "ldrh LDRH_i_A1_post", {OPR_reg_Rt, OPR_reg_Rn}, 0x005000b0, 0x0f7000f0}, - {aarch32_op_LDRH_i_A1_pre, "ldrh LDRH_i_A1_pre", {OPR_reg_Rt, OPR_reg_Rn}, 0x017000b0, 0x0f7000f0}, - {aarch32_op_LDRH_l_A1, "ldrh LDRH_l_A1", {OPR_reg_Rt, OPR_imm_label}, 0x005f00b0, 0x0e5f00f0}, - {aarch32_op_LDRH_r_A1_off, "ldrh LDRH_r_A1_off", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x011000b0, 0x0f7000f0}, - {aarch32_op_LDRH_r_A1_post, "ldrh LDRH_r_A1_post", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x001000b0, 0x0f7000f0}, - {aarch32_op_LDRH_r_A1_pre, "ldrh LDRH_r_A1_pre", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x013000b0, 0x0f7000f0}, - {aarch32_op_LDRHT_A1, "ldrht LDRHT_A1", {OPR_reg_Rt, OPR_reg_Rn}, 0x007000b0, 0x0f7000f0}, - {aarch32_op_LDRHT_A2, "ldrht LDRHT_A2", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x003000b0, 0x0f7000f0}, - {aarch32_op_LDRSB_i_A1_off, "ldrsb LDRSB_i_A1_off", {OPR_reg_Rt, OPR_reg_Rn}, 0x015000d0, 0x0f7000f0}, - {aarch32_op_LDRSB_i_A1_post, "ldrsb LDRSB_i_A1_post", {OPR_reg_Rt, OPR_reg_Rn}, 0x005000d0, 0x0f7000f0}, - {aarch32_op_LDRSB_i_A1_pre, "ldrsb LDRSB_i_A1_pre", {OPR_reg_Rt, OPR_reg_Rn}, 0x017000d0, 0x0f7000f0}, - {aarch32_op_LDRSB_l_A1, "ldrsb LDRSB_l_A1", {OPR_reg_Rt, OPR_imm_label}, 0x005f00d0, 0x0e5f00f0}, - {aarch32_op_LDRSB_r_A1_off, "ldrsb LDRSB_r_A1_off", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x011000d0, 0x0f7000f0}, - {aarch32_op_LDRSB_r_A1_post, "ldrsb LDRSB_r_A1_post", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x001000d0, 0x0f7000f0}, - {aarch32_op_LDRSB_r_A1_pre, "ldrsb LDRSB_r_A1_pre", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x013000d0, 0x0f7000f0}, - {aarch32_op_LDRSBT_A1, "ldrsbt LDRSBT_A1", {OPR_reg_Rt, OPR_reg_Rn}, 0x007000d0, 0x0f7000f0}, - {aarch32_op_LDRSBT_A2, "ldrsbt LDRSBT_A2", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x003000d0, 0x0f7000f0}, - {aarch32_op_LDRSH_i_A1_off, "ldrsh LDRSH_i_A1_off", {OPR_reg_Rt, OPR_reg_Rn}, 0x015000f0, 0x0f7000f0}, - {aarch32_op_LDRSH_i_A1_post, "ldrsh LDRSH_i_A1_post", {OPR_reg_Rt, OPR_reg_Rn}, 0x005000f0, 0x0f7000f0}, - {aarch32_op_LDRSH_i_A1_pre, "ldrsh LDRSH_i_A1_pre", {OPR_reg_Rt, OPR_reg_Rn}, 0x017000f0, 0x0f7000f0}, - {aarch32_op_LDRSH_l_A1, "ldrsh LDRSH_l_A1", {OPR_reg_Rt, OPR_imm_label}, 0x005f00f0, 0x0e5f00f0}, - {aarch32_op_LDRSH_r_A1_off, "ldrsh LDRSH_r_A1_off", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x011000f0, 0x0f7000f0}, - {aarch32_op_LDRSH_r_A1_post, "ldrsh LDRSH_r_A1_post", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x001000f0, 0x0f7000f0}, - {aarch32_op_LDRSH_r_A1_pre, "ldrsh LDRSH_r_A1_pre", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x013000f0, 0x0f7000f0}, - {aarch32_op_LDRSHT_A1, "ldrsht LDRSHT_A1", {OPR_reg_Rt, OPR_reg_Rn}, 0x007000f0, 0x0f7000f0}, - {aarch32_op_LDRSHT_A2, "ldrsht LDRSHT_A2", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x003000f0, 0x0f7000f0}, - {aarch32_op_LDRT_A1, "ldrt LDRT_A1", {OPR_reg_Rt, OPR_reg_Rn}, 0x04300000, 0x0f700000}, - {aarch32_op_LDRT_A2, "ldrt LDRT_A2", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x06300000, 0x0f700010}, - {aarch32_op_LSL_MOV_r_A1, "lsl LSL_MOV_r_A1", {OPR_reg_Rd, OPR_reg_Rm}, 0x01a00000, 0x0ff00070}, - {aarch32_op_LSL_MOV_rr_A1, "lsl LSL_MOV_rr_A1", {OPR_reg_Rd, OPR_reg_Rm, OPR_reg_Rs}, 0x01a00010, 0x0ff000f0}, - {aarch32_op_LSLS_MOVS_r_A1, "lsls LSLS_MOVS_r_A1", {OPR_reg_Rd, OPR_reg_Rm}, 0x01b00000, 0x0ff00070}, - {aarch32_op_LSLS_MOVS_rr_A1, "lsls LSLS_MOVS_rr_A1", {OPR_reg_Rd, OPR_reg_Rm, OPR_reg_Rs}, 0x01b00010, 0x0ff000f0}, - {aarch32_op_LSR_MOV_r_A1, "lsr LSR_MOV_r_A1", {OPR_reg_Rd, OPR_reg_Rm}, 0x01a00020, 0x0ff00070}, - {aarch32_op_LSR_MOV_rr_A1, "lsr LSR_MOV_rr_A1", {OPR_reg_Rd, OPR_reg_Rm, OPR_reg_Rs}, 0x01a00030, 0x0ff000f0}, - {aarch32_op_LSRS_MOVS_r_A1, "lsrs LSRS_MOVS_r_A1", {OPR_reg_Rd, OPR_reg_Rm}, 0x01b00020, 0x0ff00070}, - {aarch32_op_LSRS_MOVS_rr_A1, "lsrs LSRS_MOVS_rr_A1", {OPR_reg_Rd, OPR_reg_Rm, OPR_reg_Rs}, 0x01b00030, 0x0ff000f0}, - {aarch32_op_MCR_A1, "mcr MCR_A1", {OPR_reg_Rt}, 0x0e000e10, 0x0f100e10}, - {aarch32_op_MCRR_A1, "mcrr MCRR_A1", {OPR_reg_Rt, OPR_reg_Rt2_2}, 0x0c400e00, 0x0ff00e00}, - {aarch32_op_MLAS_A1, "mlas MLAS_A1", {OPR_reg_Rd_2, OPR_reg_Rn, OPR_reg_Rm_2, OPR_reg_Ra}, 0x00300090, 0x0ff000f0}, - {aarch32_op_MLA_A1, "mla MLA_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Ra}, 0x00200090, 0x0ff000f0}, - {aarch32_op_MLS_A1, "mls MLS_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Ra}, 0x00600090, 0x0ff000f0}, - {aarch32_op_MOV_i_A1, "mov MOV_i_A1", {OPR_reg_Rd, OPR_imm_const}, 0x03a00000, 0x0ff00000}, - {aarch32_op_MOVS_i_A1, "movs MOVS_i_A1", {OPR_reg_Rd, OPR_imm_const}, 0x03b00000, 0x0ff00000}, - {aarch32_op_MOV_i_A2, "movw MOV_i_A2", {OPR_reg_Rd}, 0x03000000, 0x0ff00000}, - {aarch32_op_MOV_r_A1_RRX, "mov MOV_r_A1_RRX", {OPR_reg_Rd, OPR_reg_Rm}, 0x01a00060, 0x0ff00ff0}, - {aarch32_op_MOV_r_A1, "mov MOV_r_A1", {OPR_reg_Rd, OPR_reg_Rm}, 0x01a00000, 0x0ff00010}, - {aarch32_op_MOVS_r_A1_RRX, "movs MOVS_r_A1_RRX", {OPR_reg_Rd, OPR_reg_Rm}, 0x01b00060, 0x0ff00ff0}, - {aarch32_op_MOVS_r_A1, "movs MOVS_r_A1", {OPR_reg_Rd, OPR_reg_Rm}, 0x01b00000, 0x0ff00010}, - {aarch32_op_MOVS_rr_A1, "movs MOVS_rr_A1", {OPR_reg_Rd, OPR_reg_Rm, OPR_reg_Rs}, 0x01b00010, 0x0ff00090}, - {aarch32_op_MOV_rr_A1, "mov MOV_rr_A1", {OPR_reg_Rd, OPR_reg_Rm, OPR_reg_Rs}, 0x01a00010, 0x0ff00090}, - {aarch32_op_MOVT_A1, "movt MOVT_A1", {OPR_reg_Rd}, 0x03400000, 0x0ff00000}, - {aarch32_op_MRC_A1, "mrc MRC_A1", {OPR_reg_Rt}, 0x0e100e10, 0x0f100e10}, - {aarch32_op_MRRC_A1, "mrrc MRRC_A1", {OPR_reg_Rt, OPR_reg_Rt2}, 0x0c500e00, 0x0ff00e00}, - {aarch32_op_MRS_A1_AS, "mrs MRS_A1_AS", {OPR_reg_Rd}, 0x01000000, 0x0fb002f0}, - {aarch32_op_MRS_br_A1_AS, "mrs MRS_br_A1_AS", {OPR_reg_Rd}, 0x01000200, 0x0fb002f0}, - {aarch32_op_MSR_br_A1_AS, "msr MSR_br_A1_AS", {OPR_reg_Rn}, 0x01200200, 0x0fb002f0}, - {aarch32_op_MSR_i_A1_AS, "msr MSR_i_A1_AS", {}, 0x03000000, 0x0f800000}, - {aarch32_op_MSR_r_A1_AS, "msr MSR_r_A1_AS", {OPR_reg_Rn}, 0x01200000, 0x0fb002f0}, - {aarch32_op_MULS_A1, "muls MULS_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00100090, 0x0ff000f0}, - {aarch32_op_MUL_A1, "mul MUL_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00000090, 0x0ff000f0}, - {aarch32_op_MVN_i_A1, "mvn MVN_i_A1", {OPR_reg_Rd, OPR_imm_const}, 0x03e00000, 0x0ff00000}, - {aarch32_op_MVNS_i_A1, "mvns MVNS_i_A1", {OPR_reg_Rd, OPR_imm_const}, 0x03f00000, 0x0ff00000}, - {aarch32_op_MVN_r_A1_RRX, "mvn MVN_r_A1_RRX", {OPR_reg_Rd, OPR_reg_Rm}, 0x01e00060, 0x0ff00ff0}, - {aarch32_op_MVN_r_A1, "mvn MVN_r_A1", {OPR_reg_Rd, OPR_reg_Rm}, 0x01e00000, 0x0ff00010}, - {aarch32_op_MVNS_r_A1_RRX, "mvns MVNS_r_A1_RRX", {OPR_reg_Rd, OPR_reg_Rm}, 0x01f00060, 0x0ff00ff0}, - {aarch32_op_MVNS_r_A1, "mvns MVNS_r_A1", {OPR_reg_Rd, OPR_reg_Rm}, 0x01f00000, 0x0ff00010}, - {aarch32_op_MVNS_rr_A1, "mvns MVNS_rr_A1", {OPR_reg_Rd, OPR_reg_Rm, OPR_reg_Rs}, 0x01f00010, 0x0ff00090}, - {aarch32_op_MVN_rr_A1, "mvn MVN_rr_A1", {OPR_reg_Rd, OPR_reg_Rm, OPR_reg_Rs}, 0x01e00010, 0x0ff00090}, - {aarch32_op_NOP_A1, "nop NOP_A1", {}, 0x03200000, 0x0fff00ff}, - {aarch32_op_ORR_i_A1, "orr ORR_i_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x03800000, 0x0ff00000}, - {aarch32_op_ORRS_i_A1, "orrs ORRS_i_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x03900000, 0x0ff00000}, - {aarch32_op_ORR_r_A1_RRX, "orr ORR_r_A1_RRX", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x01800060, 0x0ff00ff0}, - {aarch32_op_ORR_r_A1, "orr ORR_r_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x01800000, 0x0ff00010}, - {aarch32_op_ORRS_r_A1_RRX, "orrs ORRS_r_A1_RRX", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x01900060, 0x0ff00ff0}, - {aarch32_op_ORRS_r_A1, "orrs ORRS_r_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x01900000, 0x0ff00010}, - {aarch32_op_ORRS_rr_A1, "orrs ORRS_rr_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x01900010, 0x0ff00090}, - {aarch32_op_ORR_rr_A1, "orr ORR_rr_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x01800010, 0x0ff00090}, - {aarch32_op_PKHBT_A1, "pkhbt PKHBT_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06800010, 0x0ff00070}, - {aarch32_op_PKHTB_A1, "pkhtb PKHTB_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06800050, 0x0ff00070}, - {aarch32_op_PLD_i_A1, "pld PLD_i_A1", {OPR_reg_Rn}, 0xf5500000, 0xff700000}, - {aarch32_op_PLDW_i_A1, "pldw PLDW_i_A1", {OPR_reg_Rn}, 0xf5100000, 0xff700000}, - {aarch32_op_PLD_l_A1, "pld PLD_l_A1", {OPR_imm_label}, 0xf51f0000, 0xff3f0000}, - {aarch32_op_PLD_r_A1, "pld PLD_r_A1", {OPR_reg_Rn, OPR_reg_Rm}, 0xf7500000, 0xff700010}, - {aarch32_op_PLD_r_A1_RRX, "pld PLD_r_A1_RRX", {OPR_reg_Rn, OPR_reg_Rm}, 0xf7500060, 0xff700ff0}, - {aarch32_op_PLDW_r_A1, "pldw PLDW_r_A1", {OPR_reg_Rn, OPR_reg_Rm}, 0xf7100000, 0xff700010}, - {aarch32_op_PLDW_r_A1_RRX, "pldw PLDW_r_A1_RRX", {OPR_reg_Rn, OPR_reg_Rm}, 0xf7100060, 0xff700ff0}, - {aarch32_op_PLI_i_A1, "pli PLI_i_A1", {OPR_reg_Rn}, 0xf4500000, 0xff700000}, - {aarch32_op_PLI_r_A1_RRX, "pli PLI_r_A1_RRX", {OPR_reg_Rn, OPR_reg_Rm}, 0xf6500060, 0xff700ff0}, - {aarch32_op_PLI_r_A1, "pli PLI_r_A1", {OPR_reg_Rn, OPR_reg_Rm}, 0xf6500000, 0xff700010}, - {aarch32_op_POP_LDM_A1, "pop POP_LDM_A1", {OPR_reglist}, 0x08bd0000, 0x0fff0000}, - {aarch32_op_POP_LDR_i_A1_post, "pop POP_LDR_i_A1_post", {OPR_reg_Rn}, 0x049d0004, 0x0fff0fff}, - {aarch32_op_PUSH_STMDB_A1, "push PUSH_STMDB_A1", {OPR_reglist_3}, 0x092d0000, 0x0fff0000}, - {aarch32_op_PUSH_STR_i_A1_pre, "push PUSH_STR_i_A1_pre", {OPR_reg_Rn}, 0x052d0004, 0x0fff0fff}, - {aarch32_op_QADD_A1, "qadd QADD_A1", {OPR_reg_Rd, OPR_reg_Rm, OPR_reg_Rn}, 0x01000050, 0x0ff000f0}, - {aarch32_op_QADD16_A1, "qadd16 QADD16_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06200010, 0x0ff000f0}, - {aarch32_op_QADD8_A1, "qadd8 QADD8_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06200090, 0x0ff000f0}, - {aarch32_op_QASX_A1, "qasx QASX_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06200030, 0x0ff000f0}, - {aarch32_op_QDADD_A1, "qdadd QDADD_A1", {OPR_reg_Rd, OPR_reg_Rm, OPR_reg_Rn}, 0x01400050, 0x0ff000f0}, - {aarch32_op_QDSUB_A1, "qdsub QDSUB_A1", {OPR_reg_Rd, OPR_reg_Rm, OPR_reg_Rn}, 0x01600050, 0x0ff000f0}, - {aarch32_op_QSAX_A1, "qsax QSAX_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06200050, 0x0ff000f0}, - {aarch32_op_QSUB_A1, "qsub QSUB_A1", {OPR_reg_Rd, OPR_reg_Rm, OPR_reg_Rn}, 0x01200050, 0x0ff000f0}, - {aarch32_op_QSUB16_A1, "qsub16 QSUB16_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06200070, 0x0ff000f0}, - {aarch32_op_QSUB8_A1, "qsub8 QSUB8_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x062000f0, 0x0ff000f0}, - {aarch32_op_RBIT_A1, "rbit RBIT_A1", {OPR_reg_Rd, OPR_reg_Rm}, 0x06f00030, 0x0ff000f0}, - {aarch32_op_REV_A1, "rev REV_A1", {OPR_reg_Rd, OPR_reg_Rm}, 0x06b00030, 0x0ff000f0}, - {aarch32_op_REV16_A1, "rev16 REV16_A1", {OPR_reg_Rd, OPR_reg_Rm}, 0x06b000b0, 0x0ff000f0}, - {aarch32_op_REVSH_A1, "revsh REVSH_A1", {OPR_reg_Rd, OPR_reg_Rm}, 0x06f000b0, 0x0ff000f0}, - {aarch32_op_RFEDA_A1_AS, "rfeda RFEDA_A1_AS", {OPR_reg_Rn}, 0xf8100000, 0xffd00000}, - {aarch32_op_RFEDB_A1_AS, "rfedb RFEDB_A1_AS", {OPR_reg_Rn}, 0xf9100000, 0xffd00000}, - {aarch32_op_RFEIA_A1_AS, "rfe{ia} RFEIA_A1_AS", {OPR_reg_Rn}, 0xf8900000, 0xffd00000}, - {aarch32_op_RFEIB_A1_AS, "rfeib RFEIB_A1_AS", {OPR_reg_Rn}, 0xf9900000, 0xffd00000}, - {aarch32_op_ROR_MOV_r_A1, "ror ROR_MOV_r_A1", {OPR_reg_Rd, OPR_reg_Rm}, 0x01a00060, 0x0ff00070}, - {aarch32_op_ROR_MOV_rr_A1, "ror ROR_MOV_rr_A1", {OPR_reg_Rd, OPR_reg_Rm, OPR_reg_Rs}, 0x01a00070, 0x0ff000f0}, - {aarch32_op_RORS_MOVS_r_A1, "rors RORS_MOVS_r_A1", {OPR_reg_Rd, OPR_reg_Rm}, 0x01b00060, 0x0ff00070}, - {aarch32_op_RORS_MOVS_rr_A1, "rors RORS_MOVS_rr_A1", {OPR_reg_Rd, OPR_reg_Rm, OPR_reg_Rs}, 0x01b00070, 0x0ff000f0}, - {aarch32_op_RRX_MOV_r_A1_RRX, "rrx RRX_MOV_r_A1_RRX", {OPR_reg_Rd, OPR_reg_Rm}, 0x01a00060, 0x0ff00ff0}, - {aarch32_op_RRXS_MOVS_r_A1_RRX, "rrxs RRXS_MOVS_r_A1_RRX", {OPR_reg_Rd, OPR_reg_Rm}, 0x01b00060, 0x0ff00ff0}, - {aarch32_op_RSB_i_A1, "rsb RSB_i_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x02600000, 0x0ff00000}, - {aarch32_op_RSBS_i_A1, "rsbs RSBS_i_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x02700000, 0x0ff00000}, - {aarch32_op_RSB_r_A1_RRX, "rsb RSB_r_A1_RRX", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00600060, 0x0ff00ff0}, - {aarch32_op_RSB_r_A1, "rsb RSB_r_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00600000, 0x0ff00010}, - {aarch32_op_RSBS_r_A1_RRX, "rsbs RSBS_r_A1_RRX", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00700060, 0x0ff00ff0}, - {aarch32_op_RSBS_r_A1, "rsbs RSBS_r_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00700000, 0x0ff00010}, - {aarch32_op_RSBS_rr_A1, "rsbs RSBS_rr_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x00700010, 0x0ff00090}, - {aarch32_op_RSB_rr_A1, "rsb RSB_rr_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x00600010, 0x0ff00090}, - {aarch32_op_RSC_i_A1, "rsc RSC_i_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x02e00000, 0x0ff00000}, - {aarch32_op_RSCS_i_A1, "rscs RSCS_i_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x02f00000, 0x0ff00000}, - {aarch32_op_RSC_r_A1_RRX, "rsc RSC_r_A1_RRX", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00e00060, 0x0ff00ff0}, - {aarch32_op_RSC_r_A1, "rsc RSC_r_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00e00000, 0x0ff00010}, - {aarch32_op_RSCS_r_A1_RRX, "rscs RSCS_r_A1_RRX", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00f00060, 0x0ff00ff0}, - {aarch32_op_RSCS_r_A1, "rscs RSCS_r_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00f00000, 0x0ff00010}, - {aarch32_op_RSCS_rr_A1, "rscs RSCS_rr_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x00f00010, 0x0ff00090}, - {aarch32_op_RSC_rr_A1, "rsc RSC_rr_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x00e00010, 0x0ff00090}, - {aarch32_op_SADD16_A1, "sadd16 SADD16_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06100010, 0x0ff000f0}, - {aarch32_op_SADD8_A1, "sadd8 SADD8_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06100090, 0x0ff000f0}, - {aarch32_op_SASX_A1, "sasx SASX_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06100030, 0x0ff000f0}, - {aarch32_op_SBC_i_A1, "sbc SBC_i_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x02c00000, 0x0ff00000}, - {aarch32_op_SBCS_i_A1, "sbcs SBCS_i_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x02d00000, 0x0ff00000}, - {aarch32_op_SBC_r_A1_RRX, "sbc SBC_r_A1_RRX", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00c00060, 0x0ff00ff0}, - {aarch32_op_SBC_r_A1, "sbc SBC_r_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00c00000, 0x0ff00010}, - {aarch32_op_SBCS_r_A1_RRX, "sbcs SBCS_r_A1_RRX", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00d00060, 0x0ff00ff0}, - {aarch32_op_SBCS_r_A1, "sbcs SBCS_r_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00d00000, 0x0ff00010}, - {aarch32_op_SBCS_rr_A1, "sbcs SBCS_rr_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x00d00010, 0x0ff00090}, - {aarch32_op_SBC_rr_A1, "sbc SBC_rr_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x00c00010, 0x0ff00090}, - {aarch32_op_SBFX_A1, "sbfx SBFX_A1", {OPR_reg_Rd, OPR_reg_Rn}, 0x07a00050, 0x0fe00070}, - {aarch32_op_SDIV_A1, "sdiv SDIV_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x07100010, 0x0ff000f0}, - {aarch32_op_SEL_A1, "sel SEL_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x068000b0, 0x0ff000f0}, - {aarch32_op_SETEND_A1, "setend SETEND_A1", {}, 0xf1010000, 0xfff100f0}, - {aarch32_op_SETPAN_A1, "setpan SETPAN_A1", {}, 0xf1100000, 0xfff000f0}, - {aarch32_op_SEV_A1, "sev SEV_A1", {}, 0x03200004, 0x0fff00ff}, - {aarch32_op_SEVL_A1, "sevl SEVL_A1", {}, 0x03200005, 0x0fff00ff}, - {aarch32_op_SHA1C_A1, "sha1c SHA1C_A1", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000c00, 0xffb00f10}, - {aarch32_op_SHA1H_A1, "sha1h SHA1H_A1", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b102c0, 0xffb30fd0}, - {aarch32_op_SHA1M_A1, "sha1m SHA1M_A1", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2200c00, 0xffb00f10}, - {aarch32_op_SHA1P_A1, "sha1p SHA1P_A1", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2100c00, 0xffb00f10}, - {aarch32_op_SHA1SU0_A1, "sha1su0 SHA1SU0_A1", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2300c00, 0xffb00f10}, - {aarch32_op_SHA1SU1_A1, "sha1su1 SHA1SU1_A1", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b20380, 0xffb30fd0}, - {aarch32_op_SHA256H_A1, "sha256h SHA256H_A1", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3000c00, 0xffb00f10}, - {aarch32_op_SHA256H2_A1, "sha256h2 SHA256H2_A1", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3100c00, 0xffb00f10}, - {aarch32_op_SHA256SU0_A1, "sha256su0 SHA256SU0_A1", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b203c0, 0xffb30fd0}, - {aarch32_op_SHA256SU1_A1, "sha256su1 SHA256SU1_A1", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3200c00, 0xffb00f10}, - {aarch32_op_SHADD16_A1, "shadd16 SHADD16_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06300010, 0x0ff000f0}, - {aarch32_op_SHADD8_A1, "shadd8 SHADD8_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06300090, 0x0ff000f0}, - {aarch32_op_SHASX_A1, "shasx SHASX_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06300030, 0x0ff000f0}, - {aarch32_op_SHSAX_A1, "shsax SHSAX_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06300050, 0x0ff000f0}, - {aarch32_op_SHSUB16_A1, "shsub16 SHSUB16_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06300070, 0x0ff000f0}, - {aarch32_op_SHSUB8_A1, "shsub8 SHSUB8_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x063000f0, 0x0ff000f0}, - {aarch32_op_SMC_A1_AS, "smc SMC_A1_AS", {}, 0x01600070, 0x0ff000f0}, - {aarch32_op_SMLABB_A1, "smlabb SMLABB_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Ra}, 0x01000080, 0x0ff000f0}, - {aarch32_op_SMLABT_A1, "smlabt SMLABT_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Ra}, 0x010000c0, 0x0ff000f0}, - {aarch32_op_SMLATB_A1, "smlatb SMLATB_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Ra}, 0x010000a0, 0x0ff000f0}, - {aarch32_op_SMLATT_A1, "smlatt SMLATT_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Ra}, 0x010000e0, 0x0ff000f0}, - {aarch32_op_SMLAD_A1, "smlad SMLAD_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Ra}, 0x07000010, 0x0ff000f0}, - {aarch32_op_SMLADX_A1, "smladx SMLADX_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Ra}, 0x07000030, 0x0ff000f0}, - {aarch32_op_SMLALS_A1, "smlals SMLALS_A1", {OPR_reg_RdLo, OPR_reg_RdHi, OPR_reg_Rn, OPR_reg_Rm}, 0x00f00090, 0x0ff000f0}, - {aarch32_op_SMLAL_A1, "smlal SMLAL_A1", {OPR_reg_RdLo, OPR_reg_RdHi, OPR_reg_Rn, OPR_reg_Rm}, 0x00e00090, 0x0ff000f0}, - {aarch32_op_SMLALBB_A1, "smlalbb SMLALBB_A1", {OPR_reg_RdLo, OPR_reg_RdHi, OPR_reg_Rn, OPR_reg_Rm}, 0x01400080, 0x0ff000f0}, - {aarch32_op_SMLALBT_A1, "smlalbt SMLALBT_A1", {OPR_reg_RdLo, OPR_reg_RdHi, OPR_reg_Rn, OPR_reg_Rm}, 0x014000c0, 0x0ff000f0}, - {aarch32_op_SMLALTB_A1, "smlaltb SMLALTB_A1", {OPR_reg_RdLo, OPR_reg_RdHi, OPR_reg_Rn, OPR_reg_Rm}, 0x014000a0, 0x0ff000f0}, - {aarch32_op_SMLALTT_A1, "smlaltt SMLALTT_A1", {OPR_reg_RdLo, OPR_reg_RdHi, OPR_reg_Rn, OPR_reg_Rm}, 0x014000e0, 0x0ff000f0}, - {aarch32_op_SMLALD_A1, "smlald SMLALD_A1", {OPR_reg_RdLo, OPR_reg_RdHi, OPR_reg_Rn, OPR_reg_Rm}, 0x07400010, 0x0ff000f0}, - {aarch32_op_SMLALDX_A1, "smlaldx SMLALDX_A1", {OPR_reg_RdLo, OPR_reg_RdHi, OPR_reg_Rn, OPR_reg_Rm}, 0x07400030, 0x0ff000f0}, - {aarch32_op_SMLAWB_A1, "smlawb SMLAWB_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Ra}, 0x01200080, 0x0ff000f0}, - {aarch32_op_SMLAWT_A1, "smlawt SMLAWT_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Ra}, 0x012000c0, 0x0ff000f0}, - {aarch32_op_SMLSD_A1, "smlsd SMLSD_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Ra}, 0x07000050, 0x0ff000f0}, - {aarch32_op_SMLSDX_A1, "smlsdx SMLSDX_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Ra}, 0x07000070, 0x0ff000f0}, - {aarch32_op_SMLSLD_A1, "smlsld SMLSLD_A1", {OPR_reg_RdLo, OPR_reg_RdHi, OPR_reg_Rn, OPR_reg_Rm}, 0x07400050, 0x0ff000f0}, - {aarch32_op_SMLSLDX_A1, "smlsldx SMLSLDX_A1", {OPR_reg_RdLo, OPR_reg_RdHi, OPR_reg_Rn, OPR_reg_Rm}, 0x07400070, 0x0ff000f0}, - {aarch32_op_SMMLA_A1, "smmla SMMLA_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Ra}, 0x07500010, 0x0ff000f0}, - {aarch32_op_SMMLAR_A1, "smmlar SMMLAR_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Ra}, 0x07500030, 0x0ff000f0}, - {aarch32_op_SMMLS_A1, "smmls SMMLS_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Ra}, 0x075000d0, 0x0ff000f0}, - {aarch32_op_SMMLSR_A1, "smmlsr SMMLSR_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Ra}, 0x075000f0, 0x0ff000f0}, - {aarch32_op_SMMUL_A1, "smmul SMMUL_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x0750f010, 0x0ff0f0f0}, - {aarch32_op_SMMULR_A1, "smmulr SMMULR_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x0750f030, 0x0ff0f0f0}, - {aarch32_op_SMUAD_A1, "smuad SMUAD_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x0700f010, 0x0ff0f0f0}, - {aarch32_op_SMUADX_A1, "smuadx SMUADX_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x0700f030, 0x0ff0f0f0}, - {aarch32_op_SMULBB_A1, "smulbb SMULBB_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x01600080, 0x0ff000f0}, - {aarch32_op_SMULBT_A1, "smulbt SMULBT_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x016000c0, 0x0ff000f0}, - {aarch32_op_SMULTB_A1, "smultb SMULTB_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x016000a0, 0x0ff000f0}, - {aarch32_op_SMULTT_A1, "smultt SMULTT_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x016000e0, 0x0ff000f0}, - {aarch32_op_SMULLS_A1, "smulls SMULLS_A1", {OPR_reg_RdLo, OPR_reg_RdHi, OPR_reg_Rn, OPR_reg_Rm}, 0x00d00090, 0x0ff000f0}, - {aarch32_op_SMULL_A1, "smull SMULL_A1", {OPR_reg_RdLo, OPR_reg_RdHi, OPR_reg_Rn, OPR_reg_Rm}, 0x00c00090, 0x0ff000f0}, - {aarch32_op_SMULWB_A1, "smulwb SMULWB_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x012000a0, 0x0ff000f0}, - {aarch32_op_SMULWT_A1, "smulwt SMULWT_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x012000e0, 0x0ff000f0}, - {aarch32_op_SMUSD_A1, "smusd SMUSD_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x0700f050, 0x0ff0f0f0}, - {aarch32_op_SMUSDX_A1, "smusdx SMUSDX_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x0700f070, 0x0ff0f0f0}, - {aarch32_op_SRSDA_A1_AS, "srsda SRSDA_A1_AS", {}, 0xf8400000, 0xffd00000}, - {aarch32_op_SRSDB_A1_AS, "srsdb SRSDB_A1_AS", {}, 0xf9400000, 0xffd00000}, - {aarch32_op_SRSIA_A1_AS, "srs{ia} SRSIA_A1_AS", {}, 0xf8c00000, 0xffd00000}, - {aarch32_op_SRSIB_A1_AS, "srsib SRSIB_A1_AS", {}, 0xf9c00000, 0xffd00000}, - {aarch32_op_SSAT_A1_ASR, "ssat SSAT_A1_ASR", {OPR_reg_Rd, OPR_reg_Rn}, 0x06a00050, 0x0fe00070}, - {aarch32_op_SSAT_A1_LSL, "ssat SSAT_A1_LSL", {OPR_reg_Rd, OPR_reg_Rn}, 0x06a00010, 0x0fe00070}, - {aarch32_op_SSAT16_A1, "ssat16 SSAT16_A1", {OPR_reg_Rd, OPR_reg_Rn}, 0x06a00030, 0x0ff000f0}, - {aarch32_op_SSAX_A1, "ssax SSAX_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06100050, 0x0ff000f0}, - {aarch32_op_SSUB16_A1, "ssub16 SSUB16_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06100070, 0x0ff000f0}, - {aarch32_op_SSUB8_A1, "ssub8 SSUB8_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x061000f0, 0x0ff000f0}, - {aarch32_op_STC_A1_off, "stc STC_A1_off", {OPR_reg_Rn}, 0x0d005e00, 0x0f70ff00}, - {aarch32_op_STC_A1_post, "stc STC_A1_post", {OPR_reg_Rn}, 0x0c205e00, 0x0f70ff00}, - {aarch32_op_STC_A1_pre, "stc STC_A1_pre", {OPR_reg_Rn}, 0x0d205e00, 0x0f70ff00}, - {aarch32_op_STC_A1_unind, "stc STC_A1_unind", {OPR_reg_Rn}, 0x0c805e00, 0x0ff0ff00}, - {aarch32_op_STL_A1, "stl STL_A1", {OPR_reg_Rt_2, OPR_reg_Rn}, 0x01800090, 0x0ff003f0}, - {aarch32_op_STLB_A1, "stlb STLB_A1", {OPR_reg_Rt, OPR_reg_Rn}, 0x01c00090, 0x0ff003f0}, - {aarch32_op_STLEX_A1, "stlex STLEX_A1", {OPR_reg_Rd, OPR_reg_Rt, OPR_reg_Rn}, 0x01800290, 0x0ff003f0}, - {aarch32_op_STLEXB_A1, "stlexb STLEXB_A1", {OPR_reg_Rd, OPR_reg_Rt, OPR_reg_Rn}, 0x01c00290, 0x0ff003f0}, - {aarch32_op_STLEXD_A1, "stlexd STLEXD_A1", {OPR_reg_Rd, OPR_reg_Rt, OPR_reg_Rt2_3, OPR_reg_Rn}, 0x01a00290, 0x0ff003f0}, - {aarch32_op_STLEXH_A1, "stlexh STLEXH_A1", {OPR_reg_Rd, OPR_reg_Rt, OPR_reg_Rn}, 0x01e00290, 0x0ff003f0}, - {aarch32_op_STLH_A1, "stlh STLH_A1", {OPR_reg_Rt, OPR_reg_Rn}, 0x01e00090, 0x0ff003f0}, - {aarch32_op_STM_A1, "stm STM_A1", {OPR_reg_Rn, OPR_reglist}, 0x08800000, 0x0fd00000}, - {aarch32_op_STM_u_A1_AS, "stm STM_u_A1_AS", {OPR_reg_Rn, OPR_reglist}, 0x08400000, 0x0e500000}, - {aarch32_op_STMDA_A1, "stm STMDA_A1", {OPR_reg_Rn, OPR_reglist}, 0x08000000, 0x0fd00000}, - {aarch32_op_STMDB_A1, "stm STMDB_A1", {OPR_reg_Rn, OPR_reglist}, 0x09000000, 0x0fd00000}, - {aarch32_op_STMIB_A1, "stm STMIB_A1", {OPR_reg_Rn, OPR_reglist}, 0x09800000, 0x0fd00000}, - {aarch32_op_STR_i_A1_off, "str STR_i_A1_off", {OPR_reg_Rt, OPR_reg_Rn}, 0x05000000, 0x0f700000}, - {aarch32_op_STR_i_A1_post, "str STR_i_A1_post", {OPR_reg_Rt, OPR_reg_Rn}, 0x04000000, 0x0f700000}, - {aarch32_op_STR_i_A1_pre, "str STR_i_A1_pre", {OPR_reg_Rt, OPR_reg_Rn}, 0x05200000, 0x0f700000}, - {aarch32_op_STR_r_A1_off, "str STR_r_A1_off", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x07000000, 0x0f700010}, - {aarch32_op_STR_r_A1_post, "str STR_r_A1_post", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x06000000, 0x0f700010}, - {aarch32_op_STR_r_A1_pre, "str STR_r_A1_pre", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x07200000, 0x0f700010}, - {aarch32_op_STRB_i_A1_off, "strb STRB_i_A1_off", {OPR_reg_Rt, OPR_reg_Rn}, 0x05400000, 0x0f700000}, - {aarch32_op_STRB_i_A1_post, "strb STRB_i_A1_post", {OPR_reg_Rt, OPR_reg_Rn}, 0x04400000, 0x0f700000}, - {aarch32_op_STRB_i_A1_pre, "strb STRB_i_A1_pre", {OPR_reg_Rt, OPR_reg_Rn}, 0x05600000, 0x0f700000}, - {aarch32_op_STRB_r_A1_off, "strb STRB_r_A1_off", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x07400000, 0x0f700010}, - {aarch32_op_STRB_r_A1_post, "strb STRB_r_A1_post", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x06400000, 0x0f700010}, - {aarch32_op_STRB_r_A1_pre, "strb STRB_r_A1_pre", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x07600000, 0x0f700010}, - {aarch32_op_STRBT_A1, "strbt STRBT_A1", {OPR_reg_Rt, OPR_reg_Rn}, 0x04600000, 0x0f700000}, - {aarch32_op_STRBT_A2, "strbt STRBT_A2", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x06600000, 0x0f700010}, - {aarch32_op_STRD_i_A1_off, "strd STRD_i_A1_off", {OPR_reg_Rt, OPR_reg_Rt2, OPR_reg_Rn}, 0x014000f0, 0x0f7000f0}, - {aarch32_op_STRD_i_A1_post, "strd STRD_i_A1_post", {OPR_reg_Rt, OPR_reg_Rt2, OPR_reg_Rn}, 0x004000f0, 0x0f7000f0}, - {aarch32_op_STRD_i_A1_pre, "strd STRD_i_A1_pre", {OPR_reg_Rt, OPR_reg_Rt2, OPR_reg_Rn}, 0x016000f0, 0x0f7000f0}, - {aarch32_op_STRD_r_A1_off, "strd STRD_r_A1_off", {OPR_reg_Rt, OPR_reg_Rt2, OPR_reg_Rn, OPR_reg_Rm}, 0x010000f0, 0x0f7000f0}, - {aarch32_op_STRD_r_A1_post, "strd STRD_r_A1_post", {OPR_reg_Rt, OPR_reg_Rt2, OPR_reg_Rn, OPR_reg_Rm}, 0x000000f0, 0x0f7000f0}, - {aarch32_op_STRD_r_A1_pre, "strd STRD_r_A1_pre", {OPR_reg_Rt, OPR_reg_Rt2, OPR_reg_Rn, OPR_reg_Rm}, 0x012000f0, 0x0f7000f0}, - {aarch32_op_STREX_A1, "strex STREX_A1", {OPR_reg_Rd, OPR_reg_Rt, OPR_reg_Rn}, 0x01800390, 0x0ff003f0}, - {aarch32_op_STREXB_A1, "strexb STREXB_A1", {OPR_reg_Rd, OPR_reg_Rt, OPR_reg_Rn}, 0x01c00390, 0x0ff003f0}, - {aarch32_op_STREXD_A1, "strexd STREXD_A1", {OPR_reg_Rd, OPR_reg_Rt, OPR_reg_Rt2, OPR_reg_Rn}, 0x01a00390, 0x0ff003f0}, - {aarch32_op_STREXH_A1, "strexh STREXH_A1", {OPR_reg_Rd, OPR_reg_Rt, OPR_reg_Rn}, 0x01e00390, 0x0ff003f0}, - {aarch32_op_STRH_i_A1_off, "strh STRH_i_A1_off", {OPR_reg_Rt, OPR_reg_Rn}, 0x014000b0, 0x0f7000f0}, - {aarch32_op_STRH_i_A1_post, "strh STRH_i_A1_post", {OPR_reg_Rt, OPR_reg_Rn}, 0x004000b0, 0x0f7000f0}, - {aarch32_op_STRH_i_A1_pre, "strh STRH_i_A1_pre", {OPR_reg_Rt, OPR_reg_Rn}, 0x016000b0, 0x0f7000f0}, - {aarch32_op_STRH_r_A1_off, "strh STRH_r_A1_off", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x010000b0, 0x0f7000f0}, - {aarch32_op_STRH_r_A1_post, "strh STRH_r_A1_post", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x000000b0, 0x0f7000f0}, - {aarch32_op_STRH_r_A1_pre, "strh STRH_r_A1_pre", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x012000b0, 0x0f7000f0}, - {aarch32_op_STRHT_A1, "strht STRHT_A1", {OPR_reg_Rt, OPR_reg_Rn}, 0x006000b0, 0x0f7000f0}, - {aarch32_op_STRHT_A2, "strht STRHT_A2", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x002000b0, 0x0f7000f0}, - {aarch32_op_STRT_A1, "strt STRT_A1", {OPR_reg_Rt, OPR_reg_Rn}, 0x04200000, 0x0f700000}, - {aarch32_op_STRT_A2, "strt STRT_A2", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x06200000, 0x0f700010}, - {aarch32_op_SUB_ADR_A2, "sub SUB_ADR_A2", {OPR_reg_Rd, OPR_imm_const}, 0x024f0000, 0x0fff0000}, - {aarch32_op_SUB_i_A1, "sub SUB_i_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x02400000, 0x0ff00000}, - {aarch32_op_SUBS_i_A1, "subs SUBS_i_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x02500000, 0x0ff00000}, - {aarch32_op_SUB_r_A1_RRX, "sub SUB_r_A1_RRX", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00400060, 0x0ff00ff0}, - {aarch32_op_SUB_r_A1, "sub SUB_r_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00400000, 0x0ff00010}, - {aarch32_op_SUBS_r_A1_RRX, "subs SUBS_r_A1_RRX", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00500060, 0x0ff00ff0}, - {aarch32_op_SUBS_r_A1, "subs SUBS_r_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00500000, 0x0ff00010}, - {aarch32_op_SUBS_rr_A1, "subs SUBS_rr_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x00500010, 0x0ff00090}, - {aarch32_op_SUB_rr_A1, "sub SUB_rr_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x00400010, 0x0ff00090}, - {aarch32_op_SUB_SP_i_A1, "sub SUB_SP_i_A1", {OPR_reg_Rd, OPR_imm_const}, 0x024d0000, 0x0fff0000}, - {aarch32_op_SUBS_SP_i_A1, "subs SUBS_SP_i_A1", {OPR_reg_Rd, OPR_imm_const}, 0x025d0000, 0x0fff0000}, - {aarch32_op_SUB_SP_r_A1_RRX, "sub SUB_SP_r_A1_RRX", {OPR_reg_Rd, OPR_reg_Rm}, 0x004d0060, 0x0fff0ff0}, - {aarch32_op_SUB_SP_r_A1, "sub SUB_SP_r_A1", {OPR_reg_Rd, OPR_reg_Rm}, 0x004d0000, 0x0fff0010}, - {aarch32_op_SUBS_SP_r_A1_RRX, "subs SUBS_SP_r_A1_RRX", {OPR_reg_Rd, OPR_reg_Rm}, 0x005d0060, 0x0fff0ff0}, - {aarch32_op_SUBS_SP_r_A1, "subs SUBS_SP_r_A1", {OPR_reg_Rd, OPR_reg_Rm}, 0x005d0000, 0x0fff0010}, - {aarch32_op_SVC_A1, "svc SVC_A1", {}, 0x0f000000, 0x0f000000}, - {aarch32_op_SXTAB_A1, "sxtab SXTAB_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06a00070, 0x0ff000f0}, - {aarch32_op_SXTAB16_A1, "sxtab16 SXTAB16_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06800070, 0x0ff000f0}, - {aarch32_op_SXTAH_A1, "sxtah SXTAH_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06b00070, 0x0ff000f0}, - {aarch32_op_SXTB_A1, "sxtb SXTB_A1", {OPR_reg_Rd, OPR_reg_Rm}, 0x06af0070, 0x0fff00f0}, - {aarch32_op_SXTB16_A1, "sxtb16 SXTB16_A1", {OPR_reg_Rd, OPR_reg_Rm}, 0x068f0070, 0x0fff00f0}, - {aarch32_op_SXTH_A1, "sxth SXTH_A1", {OPR_reg_Rd, OPR_reg_Rm}, 0x06bf0070, 0x0fff00f0}, - {aarch32_op_TEQ_i_A1, "teq TEQ_i_A1", {OPR_reg_Rn, OPR_imm_const}, 0x03300000, 0x0ff00000}, - {aarch32_op_TEQ_r_A1_RRX, "teq TEQ_r_A1_RRX", {OPR_reg_Rn, OPR_reg_Rm}, 0x01300060, 0x0ff00ff0}, - {aarch32_op_TEQ_r_A1, "teq TEQ_r_A1", {OPR_reg_Rn, OPR_reg_Rm}, 0x01300000, 0x0ff00010}, - {aarch32_op_TEQ_rr_A1, "teq TEQ_rr_A1", {OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x01300010, 0x0ff00090}, - {aarch32_op_TST_i_A1, "tst TST_i_A1", {OPR_reg_Rn, OPR_imm_const}, 0x03100000, 0x0ff00000}, - {aarch32_op_TST_r_A1_RRX, "tst TST_r_A1_RRX", {OPR_reg_Rn, OPR_reg_Rm}, 0x01100060, 0x0ff00ff0}, - {aarch32_op_TST_r_A1, "tst TST_r_A1", {OPR_reg_Rn, OPR_reg_Rm}, 0x01100000, 0x0ff00010}, - {aarch32_op_TST_rr_A1, "tst TST_rr_A1", {OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x01100010, 0x0ff00090}, - {aarch32_op_UADD16_A1, "uadd16 UADD16_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06500010, 0x0ff000f0}, - {aarch32_op_UADD8_A1, "uadd8 UADD8_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06500090, 0x0ff000f0}, - {aarch32_op_UASX_A1, "uasx UASX_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06500030, 0x0ff000f0}, - {aarch32_op_UBFX_A1, "ubfx UBFX_A1", {OPR_reg_Rd, OPR_reg_Rn}, 0x07e00050, 0x0fe00070}, - {aarch32_op_UDF_A1, "udf UDF_A1", {}, 0xe7f000f0, 0xfff000f0}, - {aarch32_op_UDIV_A1, "udiv UDIV_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x07300010, 0x0ff000f0}, - {aarch32_op_UHADD16_A1, "uhadd16 UHADD16_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06700010, 0x0ff000f0}, - {aarch32_op_UHADD8_A1, "uhadd8 UHADD8_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06700090, 0x0ff000f0}, - {aarch32_op_UHASX_A1, "uhasx UHASX_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06700030, 0x0ff000f0}, - {aarch32_op_UHSAX_A1, "uhsax UHSAX_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06700050, 0x0ff000f0}, - {aarch32_op_UHSUB16_A1, "uhsub16 UHSUB16_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06700070, 0x0ff000f0}, - {aarch32_op_UHSUB8_A1, "uhsub8 UHSUB8_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x067000f0, 0x0ff000f0}, - {aarch32_op_UMAAL_A1, "umaal UMAAL_A1", {OPR_reg_RdLo, OPR_reg_RdHi, OPR_reg_Rn, OPR_reg_Rm}, 0x00400090, 0x0ff000f0}, - {aarch32_op_UMLALS_A1, "umlals UMLALS_A1", {OPR_reg_RdLo, OPR_reg_RdHi, OPR_reg_Rn, OPR_reg_Rm}, 0x00b00090, 0x0ff000f0}, - {aarch32_op_UMLAL_A1, "umlal UMLAL_A1", {OPR_reg_RdLo, OPR_reg_RdHi, OPR_reg_Rn, OPR_reg_Rm}, 0x00a00090, 0x0ff000f0}, - {aarch32_op_UMULLS_A1, "umulls UMULLS_A1", {OPR_reg_RdLo, OPR_reg_RdHi, OPR_reg_Rn, OPR_reg_Rm}, 0x00900090, 0x0ff000f0}, - {aarch32_op_UMULL_A1, "umull UMULL_A1", {OPR_reg_RdLo, OPR_reg_RdHi, OPR_reg_Rn, OPR_reg_Rm}, 0x00800090, 0x0ff000f0}, - {aarch32_op_UQADD16_A1, "uqadd16 UQADD16_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06600010, 0x0ff000f0}, - {aarch32_op_UQADD8_A1, "uqadd8 UQADD8_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06600090, 0x0ff000f0}, - {aarch32_op_UQASX_A1, "uqasx UQASX_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06600030, 0x0ff000f0}, - {aarch32_op_UQSAX_A1, "uqsax UQSAX_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06600050, 0x0ff000f0}, - {aarch32_op_UQSUB16_A1, "uqsub16 UQSUB16_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06600070, 0x0ff000f0}, - {aarch32_op_UQSUB8_A1, "uqsub8 UQSUB8_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x066000f0, 0x0ff000f0}, - {aarch32_op_USAD8_A1, "usad8 USAD8_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x0780f010, 0x0ff0f0f0}, - {aarch32_op_USADA8_A1, "usada8 USADA8_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Ra}, 0x07800010, 0x0ff000f0}, - {aarch32_op_USAT_A1_ASR, "usat USAT_A1_ASR", {OPR_reg_Rd, OPR_reg_Rn}, 0x06e00050, 0x0fe00070}, - {aarch32_op_USAT_A1_LSL, "usat USAT_A1_LSL", {OPR_reg_Rd, OPR_reg_Rn}, 0x06e00010, 0x0fe00070}, - {aarch32_op_USAT16_A1, "usat16 USAT16_A1", {OPR_reg_Rd, OPR_reg_Rn}, 0x06e00030, 0x0ff000f0}, - {aarch32_op_USAX_A1, "usax USAX_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06500050, 0x0ff000f0}, - {aarch32_op_USUB16_A1, "usub16 USUB16_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06500070, 0x0ff000f0}, - {aarch32_op_USUB8_A1, "usub8 USUB8_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x065000f0, 0x0ff000f0}, - {aarch32_op_UXTAB_A1, "uxtab UXTAB_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06e00070, 0x0ff000f0}, - {aarch32_op_UXTAB16_A1, "uxtab16 UXTAB16_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06c00070, 0x0ff000f0}, - {aarch32_op_UXTAH_A1, "uxtah UXTAH_A1", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06f00070, 0x0ff000f0}, - {aarch32_op_UXTB_A1, "uxtb UXTB_A1", {OPR_reg_Rd, OPR_reg_Rm}, 0x06ef0070, 0x0fff00f0}, - {aarch32_op_UXTB16_A1, "uxtb16 UXTB16_A1", {OPR_reg_Rd, OPR_reg_Rm}, 0x06cf0070, 0x0fff00f0}, - {aarch32_op_UXTH_A1, "uxth UXTH_A1", {OPR_reg_Rd, OPR_reg_Rm}, 0x06ff0070, 0x0fff00f0}, - {aarch32_op_VABA_A1_D, "vaba VABA_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000710, 0xfe800f50}, - {aarch32_op_VABA_A1_Q, "vaba VABA_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000750, 0xfe800f50}, - {aarch32_op_VABAL_A1, "vabal VABAL_A1", {OPR_reg_Qd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2800500, 0xfe800f50}, - {aarch32_op_VABD_f_A1_D, "vabd VABD_f_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3200d00, 0xffa00f50}, - {aarch32_op_VABD_f_A1_Q, "vabd VABD_f_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3200d40, 0xffa00f50}, - {aarch32_op_VABD_i_A1_D, "vabd VABD_i_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000700, 0xfe800f50}, - {aarch32_op_VABD_i_A1_Q, "vabd VABD_i_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000740, 0xfe800f50}, - {aarch32_op_VABDL_i_A1, "vabdl VABDL_i_A1", {OPR_reg_Qd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2800700, 0xfe800f50}, - {aarch32_op_VABS_A1_D, "vabs VABS_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b10300, 0xffb30bd0}, - {aarch32_op_VABS_A1_Q, "vabs VABS_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b10340, 0xffb30bd0}, - {aarch32_op_VABS_A2_H, "vabs VABS_A2_H", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb009c0, 0x0fbf0fd0}, - {aarch32_op_VABS_A2_S, "vabs VABS_A2_S", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb00ac0, 0x0fbf0fd0}, - {aarch32_op_VABS_A2_D, "vabs VABS_A2_D", {OPR_reg_Dd, OPR_reg_Dm}, 0x0eb00bc0, 0x0fbf0fd0}, - {aarch32_op_VACGE_A1_D, "vacge VACGE_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3000e10, 0xffa00f50}, - {aarch32_op_VACGE_A1_Q, "vacge VACGE_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3000e50, 0xffa00f50}, - {aarch32_op_VACGT_A1_D, "vacgt VACGT_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3200e10, 0xffa00f50}, - {aarch32_op_VACGT_A1_Q, "vacgt VACGT_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3200e50, 0xffa00f50}, - {aarch32_op_VACLE_VACGE_A1_D, "vacle VACLE_VACGE_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3000e10, 0xffa00f50}, - {aarch32_op_VACLE_VACGE_A1_Q, "vacle VACLE_VACGE_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3000e50, 0xffa00f50}, - {aarch32_op_VACLT_VACGT_A1_D, "vaclt VACLT_VACGT_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3200e10, 0xffa00f50}, - {aarch32_op_VACLT_VACGT_A1_Q, "vaclt VACLT_VACGT_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3200e50, 0xffa00f50}, - {aarch32_op_VADD_f_A1_D, "vadd VADD_f_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000d00, 0xffa00f50}, - {aarch32_op_VADD_f_A1_Q, "vadd VADD_f_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000d40, 0xffa00f50}, - {aarch32_op_VADD_f_A2_H, "vadd VADD_f_A2_H", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e300900, 0x0fb00f50}, - {aarch32_op_VADD_f_A2_S, "vadd VADD_f_A2_S", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e300a00, 0x0fb00f50}, - {aarch32_op_VADD_f_A2_D, "vadd VADD_f_A2_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0x0e300b00, 0x0fb00f50}, - {aarch32_op_VADD_i_A1_D, "vadd VADD_i_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000800, 0xff800f50}, - {aarch32_op_VADD_i_A1_Q, "vadd VADD_i_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000840, 0xff800f50}, - {aarch32_op_VADDHN_A1, "vaddhn VADDHN_A1", {OPR_reg_Dd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2800400, 0xff800f50}, - {aarch32_op_VADDL_A1, "vaddl VADDL_A1", {OPR_reg_Qd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2800000, 0xfe800f50}, - {aarch32_op_VADDW_A1, "vaddw VADDW_A1", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Dm}, 0xf2800100, 0xfe800f50}, - {aarch32_op_VAND_r_A1_D, "vand VAND_r_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000110, 0xffb00f50}, - {aarch32_op_VAND_r_A1_Q, "vand VAND_r_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000150, 0xffb00f50}, - {aarch32_op_VAND_VBIC_i_A1_D, "vand VAND_VBIC_i_A1_D", {OPR_reg_Dd, OPR_reg_Dd}, 0xf2800130, 0xfeb809f0}, - {aarch32_op_VAND_VBIC_i_A1_Q, "vand VAND_VBIC_i_A1_Q", {OPR_reg_Qd, OPR_reg_Qd}, 0xf2800170, 0xfeb809f0}, - {aarch32_op_VAND_VBIC_i_A2_D, "vand VAND_VBIC_i_A2_D", {OPR_reg_Dd, OPR_reg_Dd}, 0xf2800930, 0xfeb80df0}, - {aarch32_op_VAND_VBIC_i_A2_Q, "vand VAND_VBIC_i_A2_Q", {OPR_reg_Qd, OPR_reg_Qd}, 0xf2800970, 0xfeb80df0}, - {aarch32_op_VBIC_i_A1_D, "vbic VBIC_i_A1_D", {OPR_reg_Dd, OPR_reg_Dd}, 0xf2800130, 0xfeb809f0}, - {aarch32_op_VBIC_i_A1_Q, "vbic VBIC_i_A1_Q", {OPR_reg_Qd, OPR_reg_Qd}, 0xf2800170, 0xfeb809f0}, - {aarch32_op_VBIC_i_A2_D, "vbic VBIC_i_A2_D", {OPR_reg_Dd, OPR_reg_Dd}, 0xf2800930, 0xfeb80df0}, - {aarch32_op_VBIC_i_A2_Q, "vbic VBIC_i_A2_Q", {OPR_reg_Qd, OPR_reg_Qd}, 0xf2800970, 0xfeb80df0}, - {aarch32_op_VBIC_r_A1_D, "vbic VBIC_r_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2100110, 0xffb00f50}, - {aarch32_op_VBIC_r_A1_Q, "vbic VBIC_r_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2100150, 0xffb00f50}, - {aarch32_op_VBIF_A1_D, "vbif VBIF_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3300110, 0xffb00f50}, - {aarch32_op_VBIF_A1_Q, "vbif VBIF_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3300150, 0xffb00f50}, - {aarch32_op_VBIT_A1_D, "vbit VBIT_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3200110, 0xffb00f50}, - {aarch32_op_VBIT_A1_Q, "vbit VBIT_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3200150, 0xffb00f50}, - {aarch32_op_VBSL_A1_D, "vbsl VBSL_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3100110, 0xffb00f50}, - {aarch32_op_VBSL_A1_Q, "vbsl VBSL_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3100150, 0xffb00f50}, - {aarch32_op_VCEQ_i_A1_D, "vceq VCEQ_i_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b10100, 0xffb30bd0}, - {aarch32_op_VCEQ_i_A1_Q, "vceq VCEQ_i_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b10140, 0xffb30bd0}, - {aarch32_op_VCEQ_r_A1_D, "vceq VCEQ_r_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3000810, 0xff800f50}, - {aarch32_op_VCEQ_r_A1_Q, "vceq VCEQ_r_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3000850, 0xff800f50}, - {aarch32_op_VCEQ_r_A2_D, "vceq VCEQ_r_A2_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000e00, 0xffa00f50}, - {aarch32_op_VCEQ_r_A2_Q, "vceq VCEQ_r_A2_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000e40, 0xffa00f50}, - {aarch32_op_VCGE_i_A1_D, "vcge VCGE_i_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b10080, 0xffb30bd0}, - {aarch32_op_VCGE_i_A1_Q, "vcge VCGE_i_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b100c0, 0xffb30bd0}, - {aarch32_op_VCGE_r_A1_D, "vcge VCGE_r_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000310, 0xfe800f50}, - {aarch32_op_VCGE_r_A1_Q, "vcge VCGE_r_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000350, 0xfe800f50}, - {aarch32_op_VCGE_r_A2_D, "vcge VCGE_r_A2_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3000e00, 0xffa00f50}, - {aarch32_op_VCGE_r_A2_Q, "vcge VCGE_r_A2_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3000e40, 0xffa00f50}, - {aarch32_op_VCGT_i_A1_D, "vcgt VCGT_i_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b10000, 0xffb30bd0}, - {aarch32_op_VCGT_i_A1_Q, "vcgt VCGT_i_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b10040, 0xffb30bd0}, - {aarch32_op_VCGT_r_A1_D, "vcgt VCGT_r_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000300, 0xfe800f50}, - {aarch32_op_VCGT_r_A1_Q, "vcgt VCGT_r_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000340, 0xfe800f50}, - {aarch32_op_VCGT_r_A2_D, "vcgt VCGT_r_A2_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3200e00, 0xffa00f50}, - {aarch32_op_VCGT_r_A2_Q, "vcgt VCGT_r_A2_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3200e40, 0xffa00f50}, - {aarch32_op_VCLE_i_A1_D, "vcle VCLE_i_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b10180, 0xffb30bd0}, - {aarch32_op_VCLE_i_A1_Q, "vcle VCLE_i_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b101c0, 0xffb30bd0}, - {aarch32_op_VCLE_VCGE_r_A1_D, "vcle VCLE_VCGE_r_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000310, 0xfe800f50}, - {aarch32_op_VCLE_VCGE_r_A1_Q, "vcle VCLE_VCGE_r_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000350, 0xfe800f50}, - {aarch32_op_VCLE_VCGE_r_A2_D, "vcle VCLE_VCGE_r_A2_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3000e00, 0xffa00f50}, - {aarch32_op_VCLE_VCGE_r_A2_Q, "vcle VCLE_VCGE_r_A2_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3000e40, 0xffa00f50}, - {aarch32_op_VCLS_A1_D, "vcls VCLS_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b00400, 0xffb30fd0}, - {aarch32_op_VCLS_A1_Q, "vcls VCLS_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b00440, 0xffb30fd0}, - {aarch32_op_VCLT_i_A1_D, "vclt VCLT_i_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b10200, 0xffb30bd0}, - {aarch32_op_VCLT_i_A1_Q, "vclt VCLT_i_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b10240, 0xffb30bd0}, - {aarch32_op_VCLT_VCGT_r_A1_D, "vclt VCLT_VCGT_r_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000300, 0xfe800f50}, - {aarch32_op_VCLT_VCGT_r_A1_Q, "vclt VCLT_VCGT_r_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000340, 0xfe800f50}, - {aarch32_op_VCLT_VCGT_r_A2_D, "vclt VCLT_VCGT_r_A2_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3200e00, 0xffa00f50}, - {aarch32_op_VCLT_VCGT_r_A2_Q, "vclt VCLT_VCGT_r_A2_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3200e40, 0xffa00f50}, - {aarch32_op_VCLZ_A1_D, "vclz VCLZ_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b00480, 0xffb30fd0}, - {aarch32_op_VCLZ_A1_Q, "vclz VCLZ_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b004c0, 0xffb30fd0}, - {aarch32_op_VCMP_A1_H, "vcmp VCMP_A1_H", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb40940, 0x0fbf0fd0}, - {aarch32_op_VCMP_A1_S, "vcmp VCMP_A1_S", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb40a40, 0x0fbf0fd0}, - {aarch32_op_VCMP_A1_D, "vcmp VCMP_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0x0eb40b40, 0x0fbf0fd0}, - {aarch32_op_VCMP_A2_H, "vcmp VCMP_A2_H", {OPR_reg_Sd}, 0x0eb50940, 0x0fbf0fd0}, - {aarch32_op_VCMP_A2_S, "vcmp VCMP_A2_S", {OPR_reg_Sd}, 0x0eb50a40, 0x0fbf0fd0}, - {aarch32_op_VCMP_A2_D, "vcmp VCMP_A2_D", {OPR_reg_Dd}, 0x0eb50b40, 0x0fbf0fd0}, - {aarch32_op_VCMPE_A1_H, "vcmpe VCMPE_A1_H", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb409c0, 0x0fbf0fd0}, - {aarch32_op_VCMPE_A1_S, "vcmpe VCMPE_A1_S", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb40ac0, 0x0fbf0fd0}, - {aarch32_op_VCMPE_A1_D, "vcmpe VCMPE_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0x0eb40bc0, 0x0fbf0fd0}, - {aarch32_op_VCMPE_A2_H, "vcmpe VCMPE_A2_H", {OPR_reg_Sd}, 0x0eb509c0, 0x0fbf0fd0}, - {aarch32_op_VCMPE_A2_S, "vcmpe VCMPE_A2_S", {OPR_reg_Sd}, 0x0eb50ac0, 0x0fbf0fd0}, - {aarch32_op_VCMPE_A2_D, "vcmpe VCMPE_A2_D", {OPR_reg_Dd}, 0x0eb50bc0, 0x0fbf0fd0}, - {aarch32_op_VCNT_A1_D, "vcnt VCNT_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b00500, 0xffb30fd0}, - {aarch32_op_VCNT_A1_Q, "vcnt VCNT_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b00540, 0xffb30fd0}, - {aarch32_op_VCVT_ds_A1, "vcvt VCVT_ds_A1", {OPR_reg_Dd, OPR_reg_Sm}, 0x0eb70ac0, 0x0fbf0fd0}, - {aarch32_op_VCVT_sd_A1, "vcvt VCVT_sd_A1", {OPR_reg_Sd, OPR_reg_Dm}, 0x0eb70bc0, 0x0fbf0fd0}, - {aarch32_op_VCVT_sh_A1, "vcvt VCVT_sh_A1", {OPR_reg_Qd, OPR_reg_Dm}, 0xf3b20700, 0xffb30fd0}, - {aarch32_op_VCVT_hs_A1, "vcvt VCVT_hs_A1", {OPR_reg_Dd, OPR_reg_Qm}, 0xf3b20600, 0xffb30fd0}, - {aarch32_op_VCVT_is_A1_D, "vcvt VCVT_is_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b30600, 0xffb30e50}, - {aarch32_op_VCVT_is_A1_Q, "vcvt VCVT_is_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b30640, 0xffb30e50}, - {aarch32_op_VCVT_uiv_A1_H, "vcvt VCVT_uiv_A1_H", {OPR_reg_Sd, OPR_reg_Sm}, 0x0ebc09c0, 0x0fbf0fd0}, - {aarch32_op_VCVT_siv_A1_H, "vcvt VCVT_siv_A1_H", {OPR_reg_Sd, OPR_reg_Sm}, 0x0ebd09c0, 0x0fbf0fd0}, - {aarch32_op_VCVT_uiv_A1_S, "vcvt VCVT_uiv_A1_S", {OPR_reg_Sd, OPR_reg_Sm}, 0x0ebc0ac0, 0x0fbf0fd0}, - {aarch32_op_VCVT_siv_A1_S, "vcvt VCVT_siv_A1_S", {OPR_reg_Sd, OPR_reg_Sm}, 0x0ebd0ac0, 0x0fbf0fd0}, - {aarch32_op_VCVT_uiv_A1_D, "vcvt VCVT_uiv_A1_D", {OPR_reg_Sd, OPR_reg_Dm}, 0x0ebc0bc0, 0x0fbf0fd0}, - {aarch32_op_VCVT_siv_A1_D, "vcvt VCVT_siv_A1_D", {OPR_reg_Sd, OPR_reg_Dm}, 0x0ebd0bc0, 0x0fbf0fd0}, - {aarch32_op_VCVT_vi_A1_H, "vcvt VCVT_vi_A1_H", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb80940, 0x0fbf0f50}, - {aarch32_op_VCVT_vi_A1_S, "vcvt VCVT_vi_A1_S", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb80a40, 0x0fbf0f50}, - {aarch32_op_VCVT_vi_A1_D, "vcvt VCVT_vi_A1_D", {OPR_reg_Dd, OPR_reg_Sm}, 0x0eb80b40, 0x0fbf0f50}, - {aarch32_op_VCVT_xs_A1_D, "vcvt VCVT_xs_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf2800c10, 0xfe800cd0}, - {aarch32_op_VCVT_xs_A1_Q, "vcvt VCVT_xs_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf2800c50, 0xfe800cd0}, - {aarch32_op_VCVT_toxv_A1_H, "vcvt VCVT_toxv_A1_H", {OPR_reg_Sdm, OPR_reg_Sdm}, 0x0eba0940, 0x0fbe0f50}, - {aarch32_op_VCVT_xv_A1_H, "vcvt VCVT_xv_A1_H", {OPR_reg_Sdm, OPR_reg_Sdm}, 0x0ebe0940, 0x0fbe0f50}, - {aarch32_op_VCVT_toxv_A1_S, "vcvt VCVT_toxv_A1_S", {OPR_reg_Sdm, OPR_reg_Sdm}, 0x0eba0a40, 0x0fbe0f50}, - {aarch32_op_VCVT_xv_A1_S, "vcvt VCVT_xv_A1_S", {OPR_reg_Sdm, OPR_reg_Sdm}, 0x0ebe0a40, 0x0fbe0f50}, - {aarch32_op_VCVT_toxv_A1_D, "vcvt VCVT_toxv_A1_D", {OPR_reg_Ddm, OPR_reg_Ddm}, 0x0eba0b40, 0x0fbe0f50}, - {aarch32_op_VCVT_xv_A1_D, "vcvt VCVT_xv_A1_D", {OPR_reg_Ddm, OPR_reg_Ddm}, 0x0ebe0b40, 0x0fbe0f50}, - {aarch32_op_VCVTA_asimd_A1_D, "vcvta VCVTA_asimd_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b30000, 0xffb30f50}, - {aarch32_op_VCVTA_asimd_A1_Q, "vcvta VCVTA_asimd_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b30040, 0xffb30f50}, - {aarch32_op_VCVTA_vfp_A1_H, "vcvta VCVTA_vfp_A1_H", {OPR_reg_Sd, OPR_reg_Sm}, 0xfebc0940, 0xffbf0f50}, - {aarch32_op_VCVTA_vfp_A1_S, "vcvta VCVTA_vfp_A1_S", {OPR_reg_Sd, OPR_reg_Sm}, 0xfebc0a40, 0xffbf0f50}, - {aarch32_op_VCVTA_vfp_A1_D, "vcvta VCVTA_vfp_A1_D", {OPR_reg_Sd, OPR_reg_Dm}, 0xfebc0b40, 0xffbf0f50}, - {aarch32_op_VCVTB_A1_SH, "vcvtb VCVTB_A1_SH", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb20a40, 0x0fbf0fd0}, - {aarch32_op_VCVTB_A1_DH, "vcvtb VCVTB_A1_DH", {OPR_reg_Dd, OPR_reg_Sm}, 0x0eb20b40, 0x0fbf0fd0}, - {aarch32_op_VCVTB_A1_HS, "vcvtb VCVTB_A1_HS", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb30a40, 0x0fbf0fd0}, - {aarch32_op_VCVTB_A1_HD, "vcvtb VCVTB_A1_HD", {OPR_reg_Sd, OPR_reg_Dm}, 0x0eb30b40, 0x0fbf0fd0}, - {aarch32_op_VCVTM_asimd_A1_D, "vcvtm VCVTM_asimd_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b30300, 0xffb30f50}, - {aarch32_op_VCVTM_asimd_A1_Q, "vcvtm VCVTM_asimd_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b30340, 0xffb30f50}, - {aarch32_op_VCVTM_vfp_A1_H, "vcvtm VCVTM_vfp_A1_H", {OPR_reg_Sd, OPR_reg_Sm}, 0xfebf0940, 0xffbf0f50}, - {aarch32_op_VCVTM_vfp_A1_S, "vcvtm VCVTM_vfp_A1_S", {OPR_reg_Sd, OPR_reg_Sm}, 0xfebf0a40, 0xffbf0f50}, - {aarch32_op_VCVTM_vfp_A1_D, "vcvtm VCVTM_vfp_A1_D", {OPR_reg_Sd, OPR_reg_Dm}, 0xfebf0b40, 0xffbf0f50}, - {aarch32_op_VCVTN_asimd_A1_D, "vcvtn VCVTN_asimd_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b30100, 0xffb30f50}, - {aarch32_op_VCVTN_asimd_A1_Q, "vcvtn VCVTN_asimd_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b30140, 0xffb30f50}, - {aarch32_op_VCVTN_vfp_A1_H, "vcvtn VCVTN_vfp_A1_H", {OPR_reg_Sd, OPR_reg_Sm}, 0xfebd0940, 0xffbf0f50}, - {aarch32_op_VCVTN_vfp_A1_S, "vcvtn VCVTN_vfp_A1_S", {OPR_reg_Sd, OPR_reg_Sm}, 0xfebd0a40, 0xffbf0f50}, - {aarch32_op_VCVTN_vfp_A1_D, "vcvtn VCVTN_vfp_A1_D", {OPR_reg_Sd, OPR_reg_Dm}, 0xfebd0b40, 0xffbf0f50}, - {aarch32_op_VCVTP_asimd_A1_D, "vcvtp VCVTP_asimd_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b30200, 0xffb30f50}, - {aarch32_op_VCVTP_asimd_A1_Q, "vcvtp VCVTP_asimd_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b30240, 0xffb30f50}, - {aarch32_op_VCVTP_vfp_A1_H, "vcvtp VCVTP_vfp_A1_H", {OPR_reg_Sd, OPR_reg_Sm}, 0xfebe0940, 0xffbf0f50}, - {aarch32_op_VCVTP_vfp_A1_S, "vcvtp VCVTP_vfp_A1_S", {OPR_reg_Sd, OPR_reg_Sm}, 0xfebe0a40, 0xffbf0f50}, - {aarch32_op_VCVTP_vfp_A1_D, "vcvtp VCVTP_vfp_A1_D", {OPR_reg_Sd, OPR_reg_Dm}, 0xfebe0b40, 0xffbf0f50}, - {aarch32_op_VCVTR_uiv_A1_H, "vcvtr VCVTR_uiv_A1_H", {OPR_reg_Sd, OPR_reg_Sm}, 0x0ebc0940, 0x0fbf0fd0}, - {aarch32_op_VCVTR_siv_A1_H, "vcvtr VCVTR_siv_A1_H", {OPR_reg_Sd, OPR_reg_Sm}, 0x0ebd0940, 0x0fbf0fd0}, - {aarch32_op_VCVTR_uiv_A1_S, "vcvtr VCVTR_uiv_A1_S", {OPR_reg_Sd, OPR_reg_Sm}, 0x0ebc0a40, 0x0fbf0fd0}, - {aarch32_op_VCVTR_siv_A1_S, "vcvtr VCVTR_siv_A1_S", {OPR_reg_Sd, OPR_reg_Sm}, 0x0ebd0a40, 0x0fbf0fd0}, - {aarch32_op_VCVTR_uiv_A1_D, "vcvtr VCVTR_uiv_A1_D", {OPR_reg_Sd, OPR_reg_Dm}, 0x0ebc0b40, 0x0fbf0fd0}, - {aarch32_op_VCVTR_siv_A1_D, "vcvtr VCVTR_siv_A1_D", {OPR_reg_Sd, OPR_reg_Dm}, 0x0ebd0b40, 0x0fbf0fd0}, - {aarch32_op_VCVTT_A1_SH, "vcvtt VCVTT_A1_SH", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb20ac0, 0x0fbf0fd0}, - {aarch32_op_VCVTT_A1_DH, "vcvtt VCVTT_A1_DH", {OPR_reg_Dd, OPR_reg_Sm}, 0x0eb20bc0, 0x0fbf0fd0}, - {aarch32_op_VCVTT_A1_HS, "vcvtt VCVTT_A1_HS", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb30ac0, 0x0fbf0fd0}, - {aarch32_op_VCVTT_A1_HD, "vcvtt VCVTT_A1_HD", {OPR_reg_Sd, OPR_reg_Dm}, 0x0eb30bc0, 0x0fbf0fd0}, - {aarch32_op_VDIV_A1_H, "vdiv VDIV_A1_H", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e800900, 0x0fb00f50}, - {aarch32_op_VDIV_A1_S, "vdiv VDIV_A1_S", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e800a00, 0x0fb00f50}, - {aarch32_op_VDIV_A1_D, "vdiv VDIV_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0x0e800b00, 0x0fb00f50}, - {aarch32_op_VDUP_r_A1, "vdup VDUP_r_A1", {OPR_reg_Qd_2, OPR_reg_Rt}, 0x0e800b10, 0x0f900f50}, - {aarch32_op_VDUP_s_A1_D, "vdup VDUP_s_A1_D", {OPR_reg_Dd, OPR_reg_Dm_x_}, 0xf3b00c00, 0xffb00fd0}, - {aarch32_op_VDUP_s_A1_Q, "vdup VDUP_s_A1_Q", {OPR_reg_Qd, OPR_reg_Dm_x_}, 0xf3b00c40, 0xffb00fd0}, - {aarch32_op_VEOR_A1_D, "veor VEOR_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3000110, 0xffb00f50}, - {aarch32_op_VEOR_A1_Q, "veor VEOR_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3000150, 0xffb00f50}, - {aarch32_op_VEXT_A1_D, "vext VEXT_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2b00000, 0xffb00050}, - {aarch32_op_VEXT_A1_Q, "vext VEXT_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2b00040, 0xffb00050}, - {aarch32_op_VEXT_VEXT_A1_D, "vext VEXT_VEXT_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2b00000, 0xffb00050}, - {aarch32_op_VEXT_VEXT_A1_Q, "vext VEXT_VEXT_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2b00040, 0xffb00050}, - {aarch32_op_VFMA_A1_D, "vfma VFMA_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000c10, 0xffa00f50}, - {aarch32_op_VFMA_A1_Q, "vfma VFMA_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000c50, 0xffa00f50}, - {aarch32_op_VFMA_A2_H, "vfma VFMA_A2_H", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0ea00900, 0x0fb00f50}, - {aarch32_op_VFMA_A2_S, "vfma VFMA_A2_S", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0ea00a00, 0x0fb00f50}, - {aarch32_op_VFMA_A2_D, "vfma VFMA_A2_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0x0ea00b00, 0x0fb00f50}, - {aarch32_op_VFMS_A1_D, "vfms VFMS_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2200c10, 0xffa00f50}, - {aarch32_op_VFMS_A1_Q, "vfms VFMS_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2200c50, 0xffa00f50}, - {aarch32_op_VFMS_A2_H, "vfms VFMS_A2_H", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0ea00940, 0x0fb00f50}, - {aarch32_op_VFMS_A2_S, "vfms VFMS_A2_S", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0ea00a40, 0x0fb00f50}, - {aarch32_op_VFMS_A2_D, "vfms VFMS_A2_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0x0ea00b40, 0x0fb00f50}, - {aarch32_op_VFNMA_A1_H, "vfnma VFNMA_A1_H", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e900940, 0x0fb00f50}, - {aarch32_op_VFNMA_A1_S, "vfnma VFNMA_A1_S", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e900a40, 0x0fb00f50}, - {aarch32_op_VFNMA_A1_D, "vfnma VFNMA_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0x0e900b40, 0x0fb00f50}, - {aarch32_op_VFNMS_A1_H, "vfnms VFNMS_A1_H", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e900900, 0x0fb00f50}, - {aarch32_op_VFNMS_A1_S, "vfnms VFNMS_A1_S", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e900a00, 0x0fb00f50}, - {aarch32_op_VFNMS_A1_D, "vfnms VFNMS_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0x0e900b00, 0x0fb00f50}, - {aarch32_op_VHADD_A1_D, "vhadd VHADD_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000000, 0xfe800f50}, - {aarch32_op_VHADD_A1_Q, "vhadd VHADD_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000040, 0xfe800f50}, - {aarch32_op_VHSUB_A1_D, "vhsub VHSUB_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000200, 0xfe800f50}, - {aarch32_op_VHSUB_A1_Q, "vhsub VHSUB_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000240, 0xfe800f50}, - {aarch32_op_VINS_A1, "vins VINS_A1", {OPR_reg_Sd, OPR_reg_Sm}, 0xfeb00ac0, 0xffbf0fd0}, - {aarch32_op_VLD1_1_A1_nowb, "vld1 VLD1_1_A1_nowb", {OPR_reg_Rn}, 0xf4a0000f, 0xffb00f0f}, - {aarch32_op_VLD1_1_A1_posti, "vld1 VLD1_1_A1_posti", {OPR_reg_Rn}, 0xf4a0000d, 0xffb00f0f}, - {aarch32_op_VLD1_1_A1_postr, "vld1 VLD1_1_A1_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4a00000, 0xffb00f00}, - {aarch32_op_VLD1_1_A2_nowb, "vld1 VLD1_1_A2_nowb", {OPR_reg_Rn}, 0xf4a0040f, 0xffb00f0f}, - {aarch32_op_VLD1_1_A2_posti, "vld1 VLD1_1_A2_posti", {OPR_reg_Rn}, 0xf4a0040d, 0xffb00f0f}, - {aarch32_op_VLD1_1_A2_postr, "vld1 VLD1_1_A2_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4a00400, 0xffb00f00}, - {aarch32_op_VLD1_1_A3_nowb, "vld1 VLD1_1_A3_nowb", {OPR_reg_Rn}, 0xf4a0080f, 0xffb00f0f}, - {aarch32_op_VLD1_1_A3_posti, "vld1 VLD1_1_A3_posti", {OPR_reg_Rn}, 0xf4a0080d, 0xffb00f0f}, - {aarch32_op_VLD1_1_A3_postr, "vld1 VLD1_1_A3_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4a00800, 0xffb00f00}, - {aarch32_op_VLD1_a_A1_nowb, "vld1 VLD1_a_A1_nowb", {OPR_reg_Rn}, 0xf4a00c0f, 0xffb00f0f}, - {aarch32_op_VLD1_a_A1_posti, "vld1 VLD1_a_A1_posti", {OPR_reg_Rn}, 0xf4a00c0d, 0xffb00f0f}, - {aarch32_op_VLD1_a_A1_postr, "vld1 VLD1_a_A1_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4a00c00, 0xffb00f00}, - {aarch32_op_VLD1_m_A1_nowb, "vld1 VLD1_m_A1_nowb", {OPR_reg_Rn}, 0xf420070f, 0xffb00f0f}, - {aarch32_op_VLD1_m_A1_posti, "vld1 VLD1_m_A1_posti", {OPR_reg_Rn}, 0xf420070d, 0xffb00f0f}, - {aarch32_op_VLD1_m_A1_postr, "vld1 VLD1_m_A1_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4200700, 0xffb00f00}, - {aarch32_op_VLD1_m_A2_nowb, "vld1 VLD1_m_A2_nowb", {OPR_reg_Rn}, 0xf4200a0f, 0xffb00f0f}, - {aarch32_op_VLD1_m_A2_posti, "vld1 VLD1_m_A2_posti", {OPR_reg_Rn}, 0xf4200a0d, 0xffb00f0f}, - {aarch32_op_VLD1_m_A2_postr, "vld1 VLD1_m_A2_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4200a00, 0xffb00f00}, - {aarch32_op_VLD1_m_A3_nowb, "vld1 VLD1_m_A3_nowb", {OPR_reg_Rn}, 0xf420060f, 0xffb00f0f}, - {aarch32_op_VLD1_m_A3_posti, "vld1 VLD1_m_A3_posti", {OPR_reg_Rn}, 0xf420060d, 0xffb00f0f}, - {aarch32_op_VLD1_m_A3_postr, "vld1 VLD1_m_A3_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4200600, 0xffb00f00}, - {aarch32_op_VLD1_m_A4_nowb, "vld1 VLD1_m_A4_nowb", {OPR_reg_Rn}, 0xf420020f, 0xffb00f0f}, - {aarch32_op_VLD1_m_A4_posti, "vld1 VLD1_m_A4_posti", {OPR_reg_Rn}, 0xf420020d, 0xffb00f0f}, - {aarch32_op_VLD1_m_A4_postr, "vld1 VLD1_m_A4_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4200200, 0xffb00f00}, - {aarch32_op_VLD2_1_A1_nowb, "vld2 VLD2_1_A1_nowb", {OPR_reg_Rn}, 0xf4a0010f, 0xffb00f0f}, - {aarch32_op_VLD2_1_A1_posti, "vld2 VLD2_1_A1_posti", {OPR_reg_Rn}, 0xf4a0010d, 0xffb00f0f}, - {aarch32_op_VLD2_1_A1_postr, "vld2 VLD2_1_A1_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4a00100, 0xffb00f00}, - {aarch32_op_VLD2_1_A2_nowb, "vld2 VLD2_1_A2_nowb", {OPR_reg_Rn}, 0xf4a0050f, 0xffb00f0f}, - {aarch32_op_VLD2_1_A2_posti, "vld2 VLD2_1_A2_posti", {OPR_reg_Rn}, 0xf4a0050d, 0xffb00f0f}, - {aarch32_op_VLD2_1_A2_postr, "vld2 VLD2_1_A2_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4a00500, 0xffb00f00}, - {aarch32_op_VLD2_1_A3_nowb, "vld2 VLD2_1_A3_nowb", {OPR_reg_Rn}, 0xf4a0090f, 0xffb00f0f}, - {aarch32_op_VLD2_1_A3_posti, "vld2 VLD2_1_A3_posti", {OPR_reg_Rn}, 0xf4a0090d, 0xffb00f0f}, - {aarch32_op_VLD2_1_A3_postr, "vld2 VLD2_1_A3_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4a00900, 0xffb00f00}, - {aarch32_op_VLD2_a_A1_nowb, "vld2 VLD2_a_A1_nowb", {OPR_reg_Rn}, 0xf4a00d0f, 0xffb00f0f}, - {aarch32_op_VLD2_a_A1_posti, "vld2 VLD2_a_A1_posti", {OPR_reg_Rn}, 0xf4a00d0d, 0xffb00f0f}, - {aarch32_op_VLD2_a_A1_postr, "vld2 VLD2_a_A1_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4a00d00, 0xffb00f00}, - {aarch32_op_VLD2_m_A1_nowb, "vld2 VLD2_m_A1_nowb", {OPR_reg_Rn}, 0xf420080f, 0xffb00e0f}, - {aarch32_op_VLD2_m_A1_posti, "vld2 VLD2_m_A1_posti", {OPR_reg_Rn}, 0xf420080d, 0xffb00e0f}, - {aarch32_op_VLD2_m_A1_postr, "vld2 VLD2_m_A1_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4200800, 0xffb00e00}, - {aarch32_op_VLD2_m_A2_nowb, "vld2 VLD2_m_A2_nowb", {OPR_reg_Rn}, 0xf420030f, 0xffb00f0f}, - {aarch32_op_VLD2_m_A2_posti, "vld2 VLD2_m_A2_posti", {OPR_reg_Rn}, 0xf420030d, 0xffb00f0f}, - {aarch32_op_VLD2_m_A2_postr, "vld2 VLD2_m_A2_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4200300, 0xffb00f00}, - {aarch32_op_VLD3_1_A1_nowb, "vld3 VLD3_1_A1_nowb", {OPR_reg_Rn}, 0xf4a0020f, 0xffb00f0f}, - {aarch32_op_VLD3_1_A1_posti, "vld3 VLD3_1_A1_posti", {OPR_reg_Rn}, 0xf4a0020d, 0xffb00f0f}, - {aarch32_op_VLD3_1_A1_postr, "vld3 VLD3_1_A1_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4a00200, 0xffb00f00}, - {aarch32_op_VLD3_1_A2_nowb, "vld3 VLD3_1_A2_nowb", {OPR_reg_Rn}, 0xf4a0060f, 0xffb00f0f}, - {aarch32_op_VLD3_1_A2_posti, "vld3 VLD3_1_A2_posti", {OPR_reg_Rn}, 0xf4a0060d, 0xffb00f0f}, - {aarch32_op_VLD3_1_A2_postr, "vld3 VLD3_1_A2_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4a00600, 0xffb00f00}, - {aarch32_op_VLD3_1_A3_nowb, "vld3 VLD3_1_A3_nowb", {OPR_reg_Rn}, 0xf4a00a0f, 0xffb00f0f}, - {aarch32_op_VLD3_1_A3_posti, "vld3 VLD3_1_A3_posti", {OPR_reg_Rn}, 0xf4a00a0d, 0xffb00f0f}, - {aarch32_op_VLD3_1_A3_postr, "vld3 VLD3_1_A3_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4a00a00, 0xffb00f00}, - {aarch32_op_VLD3_a_A1_nowb, "vld3 VLD3_a_A1_nowb", {OPR_reg_Rn}, 0xf4a00e0f, 0xffb00f1f}, - {aarch32_op_VLD3_a_A1_posti, "vld3 VLD3_a_A1_posti", {OPR_reg_Rn}, 0xf4a00e0d, 0xffb00f1f}, - {aarch32_op_VLD3_a_A1_postr, "vld3 VLD3_a_A1_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4a00e00, 0xffb00f10}, - {aarch32_op_VLD3_m_A1_nowb, "vld3 VLD3_m_A1_nowb", {OPR_reg_Rn}, 0xf420040f, 0xffb00e0f}, - {aarch32_op_VLD3_m_A1_posti, "vld3 VLD3_m_A1_posti", {OPR_reg_Rn}, 0xf420040d, 0xffb00e0f}, - {aarch32_op_VLD3_m_A1_postr, "vld3 VLD3_m_A1_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4200400, 0xffb00e00}, - {aarch32_op_VLD4_1_A1_nowb, "vld4 VLD4_1_A1_nowb", {OPR_reg_Rn}, 0xf4a0030f, 0xffb00f0f}, - {aarch32_op_VLD4_1_A1_posti, "vld4 VLD4_1_A1_posti", {OPR_reg_Rn}, 0xf4a0030d, 0xffb00f0f}, - {aarch32_op_VLD4_1_A1_postr, "vld4 VLD4_1_A1_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4a00300, 0xffb00f00}, - {aarch32_op_VLD4_1_A2_nowb, "vld4 VLD4_1_A2_nowb", {OPR_reg_Rn}, 0xf4a0070f, 0xffb00f0f}, - {aarch32_op_VLD4_1_A2_posti, "vld4 VLD4_1_A2_posti", {OPR_reg_Rn}, 0xf4a0070d, 0xffb00f0f}, - {aarch32_op_VLD4_1_A2_postr, "vld4 VLD4_1_A2_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4a00700, 0xffb00f00}, - {aarch32_op_VLD4_1_A3_nowb, "vld4 VLD4_1_A3_nowb", {OPR_reg_Rn}, 0xf4a00b0f, 0xffb00f0f}, - {aarch32_op_VLD4_1_A3_posti, "vld4 VLD4_1_A3_posti", {OPR_reg_Rn}, 0xf4a00b0d, 0xffb00f0f}, - {aarch32_op_VLD4_1_A3_postr, "vld4 VLD4_1_A3_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4a00b00, 0xffb00f00}, - {aarch32_op_VLD4_a_A1_nowb, "vld4 VLD4_a_A1_nowb", {OPR_reg_Rn}, 0xf4a00f0f, 0xffb00f0f}, - {aarch32_op_VLD4_a_A1_posti, "vld4 VLD4_a_A1_posti", {OPR_reg_Rn}, 0xf4a00f0d, 0xffb00f0f}, - {aarch32_op_VLD4_a_A1_postr, "vld4 VLD4_a_A1_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4a00f00, 0xffb00f00}, - {aarch32_op_VLD4_m_A1_nowb, "vld4 VLD4_m_A1_nowb", {OPR_reg_Rn}, 0xf420000f, 0xffb00e0f}, - {aarch32_op_VLD4_m_A1_posti, "vld4 VLD4_m_A1_posti", {OPR_reg_Rn}, 0xf420000d, 0xffb00e0f}, - {aarch32_op_VLD4_m_A1_postr, "vld4 VLD4_m_A1_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4200000, 0xffb00e00}, - {aarch32_op_VLDMDB_A1, "vldmdb VLDMDB_A1", {OPR_reg_Rn}, 0x0d300b00, 0x0fb00f01}, - {aarch32_op_VLDM_A1, "vldm VLDM_A1", {OPR_reg_Rn}, 0x0c900b00, 0x0f900f01}, - {aarch32_op_VLDMDB_A2, "vldmdb VLDMDB_A2", {OPR_reg_Rn}, 0x0d300a00, 0x0fb00f00}, - {aarch32_op_VLDM_A2, "vldm VLDM_A2", {OPR_reg_Rn}, 0x0c900a00, 0x0f900f00}, - {aarch32_op_VLDR_A1_H, "vldr VLDR_A1_H", {OPR_reg_Sd, OPR_reg_Rn}, 0x0d100900, 0x0f300f00}, - {aarch32_op_VLDR_A1_S, "vldr VLDR_A1_S", {OPR_reg_Sd, OPR_reg_Rn}, 0x0d100a00, 0x0f300f00}, - {aarch32_op_VLDR_A1_D, "vldr VLDR_A1_D", {OPR_reg_Dd, OPR_reg_Rn}, 0x0d100b00, 0x0f300f00}, - {aarch32_op_VLDR_l_A1_H, "vldr VLDR_l_A1_H", {OPR_reg_Sd, OPR_imm_label_7}, 0x0d1f0900, 0x0f3f0f00}, - {aarch32_op_VLDR_l_A1_S, "vldr VLDR_l_A1_S", {OPR_reg_Sd, OPR_imm_label}, 0x0d1f0a00, 0x0f3f0f00}, - {aarch32_op_VLDR_l_A1_D, "vldr VLDR_l_A1_D", {OPR_reg_Dd, OPR_imm_label}, 0x0d1f0b00, 0x0f3f0f00}, - {aarch32_op_VMAX_f_A1_D, "vmax VMAX_f_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000f00, 0xffa00f50}, - {aarch32_op_VMAX_f_A1_Q, "vmax VMAX_f_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000f40, 0xffa00f50}, - {aarch32_op_VMAX_i_A1_D, "vmax VMAX_i_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000600, 0xfe800f50}, - {aarch32_op_VMAX_i_A1_Q, "vmax VMAX_i_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000640, 0xfe800f50}, - {aarch32_op_VMAXNM_A1_D, "vmaxnm VMAXNM_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3000f10, 0xffa00f50}, - {aarch32_op_VMAXNM_A1_Q, "vmaxnm VMAXNM_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3000f50, 0xffa00f50}, - {aarch32_op_VMAXNM_A2_H, "vmaxnm VMAXNM_A2_H", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0xfe800900, 0xffb00f50}, - {aarch32_op_VMAXNM_A2_S, "vmaxnm VMAXNM_A2_S", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0xfe800a00, 0xffb00f50}, - {aarch32_op_VMAXNM_A2_D, "vmaxnm VMAXNM_A2_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xfe800b00, 0xffb00f50}, - {aarch32_op_VMIN_f_A1_D, "vmin VMIN_f_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2200f00, 0xffa00f50}, - {aarch32_op_VMIN_f_A1_Q, "vmin VMIN_f_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2200f40, 0xffa00f50}, - {aarch32_op_VMIN_i_A1_D, "vmin VMIN_i_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000610, 0xfe800f50}, - {aarch32_op_VMIN_i_A1_Q, "vmin VMIN_i_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000650, 0xfe800f50}, - {aarch32_op_VMINNM_A1_D, "vminnm VMINNM_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3200f10, 0xffa00f50}, - {aarch32_op_VMINNM_A1_Q, "vminnm VMINNM_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3200f50, 0xffa00f50}, - {aarch32_op_VMINNM_A2_H, "vminnm VMINNM_A2_H", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0xfe800940, 0xffb00f50}, - {aarch32_op_VMINNM_A2_S, "vminnm VMINNM_A2_S", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0xfe800a40, 0xffb00f50}, - {aarch32_op_VMINNM_A2_D, "vminnm VMINNM_A2_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xfe800b40, 0xffb00f50}, - {aarch32_op_VMLA_f_A1_D, "vmla VMLA_f_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000d10, 0xffa00f50}, - {aarch32_op_VMLA_f_A1_Q, "vmla VMLA_f_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000d50, 0xffa00f50}, - {aarch32_op_VMLA_f_A2_H, "vmla VMLA_f_A2_H", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e000900, 0x0fb00f50}, - {aarch32_op_VMLA_f_A2_S, "vmla VMLA_f_A2_S", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e000a00, 0x0fb00f50}, - {aarch32_op_VMLA_f_A2_D, "vmla VMLA_f_A2_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0x0e000b00, 0x0fb00f50}, - {aarch32_op_VMLA_i_A1_D, "vmla VMLA_i_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000900, 0xff800f50}, - {aarch32_op_VMLA_i_A1_Q, "vmla VMLA_i_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000940, 0xff800f50}, - {aarch32_op_VMLA_s_A1_D, "vmla VMLA_s_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm_x_}, 0xf2800040, 0xff800e50}, - {aarch32_op_VMLA_s_A1_Q, "vmla VMLA_s_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Dm_x_}, 0xf3800040, 0xff800e50}, - {aarch32_op_VMLAL_i_A1, "vmlal VMLAL_i_A1", {OPR_reg_Qd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2800800, 0xfe800f50}, - {aarch32_op_VMLAL_s_A1, "vmlal VMLAL_s_A1", {OPR_reg_Qd, OPR_reg_Dn, OPR_reg_Dm_x_}, 0xf2800240, 0xfe800f50}, - {aarch32_op_VMLS_f_A1_D, "vmls VMLS_f_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2200d10, 0xffa00f50}, - {aarch32_op_VMLS_f_A1_Q, "vmls VMLS_f_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2200d50, 0xffa00f50}, - {aarch32_op_VMLS_f_A2_H, "vmls VMLS_f_A2_H", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e000940, 0x0fb00f50}, - {aarch32_op_VMLS_f_A2_S, "vmls VMLS_f_A2_S", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e000a40, 0x0fb00f50}, - {aarch32_op_VMLS_f_A2_D, "vmls VMLS_f_A2_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0x0e000b40, 0x0fb00f50}, - {aarch32_op_VMLS_i_A1_D, "vmls VMLS_i_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3000900, 0xff800f50}, - {aarch32_op_VMLS_i_A1_Q, "vmls VMLS_i_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3000940, 0xff800f50}, - {aarch32_op_VMLS_s_A1_D, "vmls VMLS_s_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm_x_}, 0xf2800440, 0xff800e50}, - {aarch32_op_VMLS_s_A1_Q, "vmls VMLS_s_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Dm_x_}, 0xf3800440, 0xff800e50}, - {aarch32_op_VMLSL_i_A1, "vmlsl VMLSL_i_A1", {OPR_reg_Qd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2800a00, 0xfe800f50}, - {aarch32_op_VMLSL_s_A1, "vmlsl VMLSL_s_A1", {OPR_reg_Qd, OPR_reg_Dn, OPR_reg_Dm_x_}, 0xf2800640, 0xfe800f50}, - {aarch32_op_VMOV_tod_A1, "vmov VMOV_tod_A1", {OPR_reg_Dm, OPR_reg_Rt, OPR_reg_Rt2}, 0x0c400b10, 0x0ff00fd0}, - {aarch32_op_VMOV_d_A1, "vmov VMOV_d_A1", {OPR_reg_Rt, OPR_reg_Rt2, OPR_reg_Dm}, 0x0c500b10, 0x0ff00fd0}, - {aarch32_op_VMOV_toh_A1, "vmov VMOV_toh_A1", {OPR_reg_Sn, OPR_reg_Rt}, 0x0e000910, 0x0ff00f10}, - {aarch32_op_VMOV_h_A1, "vmov VMOV_h_A1", {OPR_reg_Rt, OPR_reg_Sn}, 0x0e100910, 0x0ff00f10}, - {aarch32_op_VMOV_i_A1_D, "vmov VMOV_i_A1_D", {OPR_reg_Dd}, 0xf2800010, 0xfeb809f0}, - {aarch32_op_VMOV_i_A1_Q, "vmov VMOV_i_A1_Q", {OPR_reg_Qd}, 0xf2800050, 0xfeb809f0}, - {aarch32_op_VMOV_i_A2_H, "vmov VMOV_i_A2_H", {OPR_reg_Sd}, 0x0eb00900, 0x0fb00f50}, - {aarch32_op_VMOV_i_A2_S, "vmov VMOV_i_A2_S", {OPR_reg_Sd}, 0x0eb00a00, 0x0fb00f50}, - {aarch32_op_VMOV_i_A2_D, "vmov VMOV_i_A2_D", {OPR_reg_Dd}, 0x0eb00b00, 0x0fb00f50}, - {aarch32_op_VMOV_i_A3_D, "vmov VMOV_i_A3_D", {OPR_reg_Dd}, 0xf2800810, 0xfeb80df0}, - {aarch32_op_VMOV_i_A3_Q, "vmov VMOV_i_A3_Q", {OPR_reg_Qd}, 0xf2800850, 0xfeb80df0}, - {aarch32_op_VMOV_i_A4_D, "vmov VMOV_i_A4_D", {OPR_reg_Dd}, 0xf2800c10, 0xfeb80cf0}, - {aarch32_op_VMOV_i_A4_Q, "vmov VMOV_i_A4_Q", {OPR_reg_Qd}, 0xf2800c50, 0xfeb80cf0}, - {aarch32_op_VMOV_i_A5_D, "vmov VMOV_i_A5_D", {OPR_reg_Dd}, 0xf2800e30, 0xfeb80ff0}, - {aarch32_op_VMOV_i_A5_Q, "vmov VMOV_i_A5_Q", {OPR_reg_Qd}, 0xf2800e70, 0xfeb80ff0}, - {aarch32_op_VMOV_r_A2_S, "vmov VMOV_r_A2_S", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb00a40, 0x0fbf0fd0}, - {aarch32_op_VMOV_r_A2_D, "vmov VMOV_r_A2_D", {OPR_reg_Dd, OPR_reg_Dm}, 0x0eb00b40, 0x0fbf0fd0}, - {aarch32_op_VMOV_rs_A1, "vmov VMOV_rs_A1", {OPR_reg_Dd_x_, OPR_reg_Rt}, 0x0e000b10, 0x0f900f10}, - {aarch32_op_VMOV_tos_A1, "vmov VMOV_tos_A1", {OPR_reg_Sn, OPR_reg_Rt}, 0x0e000a10, 0x0ff00f10}, - {aarch32_op_VMOV_s_A1, "vmov VMOV_s_A1", {OPR_reg_Rt, OPR_reg_Sn}, 0x0e100a10, 0x0ff00f10}, - {aarch32_op_VMOV_sr_A1, "vmov VMOV_sr_A1", {OPR_reg_Rt, OPR_reg_Dn_x_}, 0x0e100b10, 0x0f100f10}, - {aarch32_op_VMOV_toss_A1, "vmov VMOV_toss_A1", {OPR_reg_Sm, OPR_reg_Sm1, OPR_reg_Rt, OPR_reg_Rt2}, 0x0c400a10, 0x0ff00fd0}, - {aarch32_op_VMOV_ss_A1, "vmov VMOV_ss_A1", {OPR_reg_Rt, OPR_reg_Rt2, OPR_reg_Sm, OPR_reg_Sm1}, 0x0c500a10, 0x0ff00fd0}, - {aarch32_op_VMOV_VORR_r_A1_D, "vmov VMOV_VORR_r_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf2200110, 0xffb00f50}, - {aarch32_op_VMOV_VORR_r_A1_Q, "vmov VMOV_VORR_r_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf2200150, 0xffb00f50}, - {aarch32_op_VMOVL_A1, "vmovl VMOVL_A1", {OPR_reg_Qd, OPR_reg_Dm}, 0xf2800a10, 0xfe870fd0}, - {aarch32_op_VMOVN_A1, "vmovn VMOVN_A1", {OPR_reg_Dd, OPR_reg_Qm}, 0xf3b20200, 0xffb30fd0}, - {aarch32_op_VMOVX_A1, "vmovx VMOVX_A1", {OPR_reg_Sd, OPR_reg_Sm}, 0xfeb00a40, 0xffbf0fd0}, - {aarch32_op_VMRS_A1_AS, "vmrs VMRS_A1_AS", {OPR_reg_Rt}, 0x0ef00a10, 0x0ff00f10}, - {aarch32_op_VMSR_A1_AS, "vmsr VMSR_A1_AS", {OPR_reg_Rt}, 0x0ee00a10, 0x0ff00f10}, - {aarch32_op_VMUL_f_A1_D, "vmul VMUL_f_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3000d10, 0xffa00f50}, - {aarch32_op_VMUL_f_A1_Q, "vmul VMUL_f_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3000d50, 0xffa00f50}, - {aarch32_op_VMUL_f_A2_H, "vmul VMUL_f_A2_H", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e200900, 0x0fb00f50}, - {aarch32_op_VMUL_f_A2_S, "vmul VMUL_f_A2_S", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e200a00, 0x0fb00f50}, - {aarch32_op_VMUL_f_A2_D, "vmul VMUL_f_A2_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0x0e200b00, 0x0fb00f50}, - {aarch32_op_VMUL_i_A1_D, "vmul VMUL_i_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000910, 0xfe800f50}, - {aarch32_op_VMUL_i_A1_Q, "vmul VMUL_i_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000950, 0xfe800f50}, - {aarch32_op_VMUL_s_A1_D, "vmul VMUL_s_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2800840, 0xff800e50}, - {aarch32_op_VMUL_s_A1_Q, "vmul VMUL_s_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Dm}, 0xf3800840, 0xff800e50}, - {aarch32_op_VMULL_i_A1, "vmull VMULL_i_A1", {OPR_reg_Qd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2800c00, 0xfe800d50}, - {aarch32_op_VMULL_s_A1, "vmull VMULL_s_A1", {OPR_reg_Qd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2800a40, 0xfe800f50}, - {aarch32_op_VMVN_i_A1_D, "vmvn VMVN_i_A1_D", {OPR_reg_Dd}, 0xf2800030, 0xfeb809f0}, - {aarch32_op_VMVN_i_A1_Q, "vmvn VMVN_i_A1_Q", {OPR_reg_Qd}, 0xf2800070, 0xfeb809f0}, - {aarch32_op_VMVN_i_A2_D, "vmvn VMVN_i_A2_D", {OPR_reg_Dd}, 0xf2800830, 0xfeb80df0}, - {aarch32_op_VMVN_i_A2_Q, "vmvn VMVN_i_A2_Q", {OPR_reg_Qd}, 0xf2800870, 0xfeb80df0}, - {aarch32_op_VMVN_i_A3_D, "vmvn VMVN_i_A3_D", {OPR_reg_Dd}, 0xf2800c30, 0xfeb80ef0}, - {aarch32_op_VMVN_i_A3_Q, "vmvn VMVN_i_A3_Q", {OPR_reg_Qd}, 0xf2800c70, 0xfeb80ef0}, - {aarch32_op_VMVN_r_A1_D, "vmvn VMVN_r_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b00580, 0xffb30fd0}, - {aarch32_op_VMVN_r_A1_Q, "vmvn VMVN_r_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b005c0, 0xffb30fd0}, - {aarch32_op_VNEG_A1_D, "vneg VNEG_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b10380, 0xffb30bd0}, - {aarch32_op_VNEG_A1_Q, "vneg VNEG_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b103c0, 0xffb30bd0}, - {aarch32_op_VNEG_A2_H, "vneg VNEG_A2_H", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb10940, 0x0fbf0fd0}, - {aarch32_op_VNEG_A2_S, "vneg VNEG_A2_S", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb10a40, 0x0fbf0fd0}, - {aarch32_op_VNEG_A2_D, "vneg VNEG_A2_D", {OPR_reg_Dd, OPR_reg_Dm}, 0x0eb10b40, 0x0fbf0fd0}, - {aarch32_op_VNMLA_A1_H, "vnmla VNMLA_A1_H", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e100940, 0x0fb00f50}, - {aarch32_op_VNMLA_A1_S, "vnmla VNMLA_A1_S", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e100a40, 0x0fb00f50}, - {aarch32_op_VNMLA_A1_D, "vnmla VNMLA_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0x0e100b40, 0x0fb00f50}, - {aarch32_op_VNMLS_A1_H, "vnmls VNMLS_A1_H", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e100900, 0x0fb00f50}, - {aarch32_op_VNMLS_A1_S, "vnmls VNMLS_A1_S", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e100a00, 0x0fb00f50}, - {aarch32_op_VNMLS_A1_D, "vnmls VNMLS_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0x0e100b00, 0x0fb00f50}, - {aarch32_op_VNMUL_A1_H, "vnmul VNMUL_A1_H", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e200940, 0x0fb00f50}, - {aarch32_op_VNMUL_A1_S, "vnmul VNMUL_A1_S", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e200a40, 0x0fb00f50}, - {aarch32_op_VNMUL_A1_D, "vnmul VNMUL_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0x0e200b40, 0x0fb00f50}, - {aarch32_op_VORN_r_A1_D, "vorn VORN_r_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2300110, 0xffb00f50}, - {aarch32_op_VORN_r_A1_Q, "vorn VORN_r_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2300150, 0xffb00f50}, - {aarch32_op_VORN_VORR_i_A1_D, "vorn VORN_VORR_i_A1_D", {OPR_reg_Dd, OPR_reg_Dd}, 0xf2800110, 0xfeb809f0}, - {aarch32_op_VORN_VORR_i_A1_Q, "vorn VORN_VORR_i_A1_Q", {OPR_reg_Qd, OPR_reg_Qd}, 0xf2800150, 0xfeb809f0}, - {aarch32_op_VORN_VORR_i_A2_D, "vorn VORN_VORR_i_A2_D", {OPR_reg_Dd, OPR_reg_Dd}, 0xf2800910, 0xfeb80df0}, - {aarch32_op_VORN_VORR_i_A2_Q, "vorn VORN_VORR_i_A2_Q", {OPR_reg_Qd, OPR_reg_Qd}, 0xf2800950, 0xfeb80df0}, - {aarch32_op_VORR_i_A1_D, "vorr VORR_i_A1_D", {OPR_reg_Dd, OPR_reg_Dd}, 0xf2800110, 0xfeb809f0}, - {aarch32_op_VORR_i_A1_Q, "vorr VORR_i_A1_Q", {OPR_reg_Qd, OPR_reg_Qd}, 0xf2800150, 0xfeb809f0}, - {aarch32_op_VORR_i_A2_D, "vorr VORR_i_A2_D", {OPR_reg_Dd, OPR_reg_Dd}, 0xf2800910, 0xfeb80df0}, - {aarch32_op_VORR_i_A2_Q, "vorr VORR_i_A2_Q", {OPR_reg_Qd, OPR_reg_Qd}, 0xf2800950, 0xfeb80df0}, - {aarch32_op_VORR_r_A1_D, "vorr VORR_r_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2200110, 0xffb00f50}, - {aarch32_op_VORR_r_A1_Q, "vorr VORR_r_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2200150, 0xffb00f50}, - {aarch32_op_VPADAL_A1_D, "vpadal VPADAL_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b00600, 0xffb30f50}, - {aarch32_op_VPADAL_A1_Q, "vpadal VPADAL_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b00640, 0xffb30f50}, - {aarch32_op_VPADD_f_A1, "vpadd VPADD_f_A1", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3000d00, 0xffa00f10}, - {aarch32_op_VPADD_i_A1, "vpadd VPADD_i_A1", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000b10, 0xff800f10}, - {aarch32_op_VPADDL_A1_D, "vpaddl VPADDL_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b00200, 0xffb30f50}, - {aarch32_op_VPADDL_A1_Q, "vpaddl VPADDL_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b00240, 0xffb30f50}, - {aarch32_op_VPMAX_f_A1, "vpmax VPMAX_f_A1", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3000f00, 0xffa00f50}, - {aarch32_op_VPMAX_i_A1, "vpmax VPMAX_i_A1", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000a00, 0xfe800f50}, - {aarch32_op_VPMIN_f_A1, "vpmin VPMIN_f_A1", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3200f00, 0xffa00f50}, - {aarch32_op_VPMIN_i_A1, "vpmin VPMIN_i_A1", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000a10, 0xfe800f50}, - {aarch32_op_VPOP_VLDM_A1, "vpop VPOP_VLDM_A1", {}, 0x0cbd0b00, 0x0fbf0f01}, - {aarch32_op_VPOP_VLDM_A2, "vpop VPOP_VLDM_A2", {}, 0x0cbd0a00, 0x0fbf0f00}, - {aarch32_op_VPUSH_VSTMDB_A1, "vpush VPUSH_VSTMDB_A1", {}, 0x0d2d0b00, 0x0fbf0f01}, - {aarch32_op_VPUSH_VSTMDB_A2, "vpush VPUSH_VSTMDB_A2", {}, 0x0d2d0a00, 0x0fbf0f00}, - {aarch32_op_VQABS_A1_D, "vqabs VQABS_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b00700, 0xffb30fd0}, - {aarch32_op_VQABS_A1_Q, "vqabs VQABS_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b00740, 0xffb30fd0}, - {aarch32_op_VQADD_A1_D, "vqadd VQADD_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000010, 0xfe800f50}, - {aarch32_op_VQADD_A1_Q, "vqadd VQADD_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000050, 0xfe800f50}, - {aarch32_op_VQDMLAL_A1, "vqdmlal VQDMLAL_A1", {OPR_reg_Qd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2800900, 0xff800f50}, - {aarch32_op_VQDMLAL_A2, "vqdmlal VQDMLAL_A2", {OPR_reg_Qd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2800340, 0xff800f50}, - {aarch32_op_VQDMLSL_A1, "vqdmlsl VQDMLSL_A1", {OPR_reg_Qd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2800b00, 0xff800f50}, - {aarch32_op_VQDMLSL_A2, "vqdmlsl VQDMLSL_A2", {OPR_reg_Qd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2800740, 0xff800f50}, - {aarch32_op_VQDMULH_A1_D, "vqdmulh VQDMULH_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000b00, 0xff800f50}, - {aarch32_op_VQDMULH_A1_Q, "vqdmulh VQDMULH_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000b40, 0xff800f50}, - {aarch32_op_VQDMULH_A2_D, "vqdmulh VQDMULH_A2_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm_x_}, 0xf2800c40, 0xff800f50}, - {aarch32_op_VQDMULH_A2_Q, "vqdmulh VQDMULH_A2_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Dm_x_}, 0xf3800c40, 0xff800f50}, - {aarch32_op_VQDMULL_A1, "vqdmull VQDMULL_A1", {OPR_reg_Qd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2800d00, 0xff800f50}, - {aarch32_op_VQDMULL_A2, "vqdmull VQDMULL_A2", {OPR_reg_Qd, OPR_reg_Dn, OPR_reg_Dm_x_}, 0xf2800b40, 0xff800f50}, - {aarch32_op_VQMOVN_A1, "vqmovn VQMOVN_A1", {OPR_reg_Dd, OPR_reg_Qm}, 0xf3b20280, 0xffb30f90}, - {aarch32_op_VQMOVUN_A1, "vqmovun VQMOVUN_A1", {OPR_reg_Dd, OPR_reg_Qm}, 0xf3b20240, 0xffb30fd0}, - {aarch32_op_VQNEG_A1_D, "vqneg VQNEG_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b00780, 0xffb30fd0}, - {aarch32_op_VQNEG_A1_Q, "vqneg VQNEG_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b007c0, 0xffb30fd0}, - {aarch32_op_VQRDMLAH_A1_D, "vqrdmlah VQRDMLAH_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3000b10, 0xff800f50}, - {aarch32_op_VQRDMLAH_A1_Q, "vqrdmlah VQRDMLAH_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3000b50, 0xff800f50}, - {aarch32_op_VQRDMLAH_A2_D, "vqrdmlah VQRDMLAH_A2_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm_x_}, 0xf2800e40, 0xff800f50}, - {aarch32_op_VQRDMLAH_A2_Q, "vqrdmlah VQRDMLAH_A2_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Dm_x_}, 0xf3800e40, 0xff800f50}, - {aarch32_op_VQRDMLSH_A1_D, "vqrdmlsh VQRDMLSH_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3000c10, 0xff800f50}, - {aarch32_op_VQRDMLSH_A1_Q, "vqrdmlsh VQRDMLSH_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3000c50, 0xff800f50}, - {aarch32_op_VQRDMLSH_A2_D, "vqrdmlsh VQRDMLSH_A2_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm_x_}, 0xf2800f40, 0xff800f50}, - {aarch32_op_VQRDMLSH_A2_Q, "vqrdmlsh VQRDMLSH_A2_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Dm_x_}, 0xf3800f40, 0xff800f50}, - {aarch32_op_VQRDMULH_A1_D, "vqrdmulh VQRDMULH_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3000b00, 0xff800f50}, - {aarch32_op_VQRDMULH_A1_Q, "vqrdmulh VQRDMULH_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3000b40, 0xff800f50}, - {aarch32_op_VQRDMULH_A2_D, "vqrdmulh VQRDMULH_A2_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm_x_}, 0xf2800d40, 0xff800f50}, - {aarch32_op_VQRDMULH_A2_Q, "vqrdmulh VQRDMULH_A2_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Dm_x_}, 0xf3800d40, 0xff800f50}, - {aarch32_op_VQRSHL_A1_D, "vqrshl VQRSHL_A1_D", {OPR_reg_Dd, OPR_reg_Dm, OPR_reg_Dn}, 0xf2000510, 0xfe800f50}, - {aarch32_op_VQRSHL_A1_Q, "vqrshl VQRSHL_A1_Q", {OPR_reg_Qd, OPR_reg_Qm, OPR_reg_Qn}, 0xf2000550, 0xfe800f50}, - {aarch32_op_VQRSHRN_A1, "vqrshrn VQRSHRN_A1", {OPR_reg_Dd, OPR_reg_Qm}, 0xf2800950, 0xfe800fd0}, - {aarch32_op_VQRSHRUN_A1, "vqrshrun VQRSHRUN_A1", {OPR_reg_Dd, OPR_reg_Qm}, 0xf3800850, 0xff800fd0}, - {aarch32_op_VQRSHRN_VQMOVN_A1, "vqrshrn VQRSHRN_VQMOVN_A1", {OPR_reg_Dd, OPR_reg_Qm}, 0xf3b20280, 0xffb30f90}, - {aarch32_op_VQRSHRUN_VQMOVUN_A1, "vqrshrun VQRSHRUN_VQMOVUN_A1", {OPR_reg_Dd, OPR_reg_Qm}, 0xf3b20240, 0xffb30fd0}, - {aarch32_op_VQSHL_i_A1_D, "vqshl VQSHL_i_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf2800710, 0xfe800f50}, - {aarch32_op_VQSHL_i_A1_Q, "vqshl VQSHL_i_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf2800750, 0xfe800f50}, - {aarch32_op_VQSHLU_i_A1_D, "vqshlu VQSHLU_i_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3800610, 0xff800f50}, - {aarch32_op_VQSHLU_i_A1_Q, "vqshlu VQSHLU_i_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3800650, 0xff800f50}, - {aarch32_op_VQSHL_r_A1_D, "vqshl VQSHL_r_A1_D", {OPR_reg_Dd, OPR_reg_Dm, OPR_reg_Dn}, 0xf2000410, 0xfe800f50}, - {aarch32_op_VQSHL_r_A1_Q, "vqshl VQSHL_r_A1_Q", {OPR_reg_Qd, OPR_reg_Qm, OPR_reg_Qn}, 0xf2000450, 0xfe800f50}, - {aarch32_op_VQSHRN_A1, "vqshrn VQSHRN_A1", {OPR_reg_Dd, OPR_reg_Qm}, 0xf2800910, 0xfe800fd0}, - {aarch32_op_VQSHRUN_A1, "vqshrun VQSHRUN_A1", {OPR_reg_Dd, OPR_reg_Qm}, 0xf3800810, 0xff800fd0}, - {aarch32_op_VQSHRN_VQMOVN_A1, "vqshrn VQSHRN_VQMOVN_A1", {OPR_reg_Dd, OPR_reg_Qm}, 0xf3b20280, 0xffb30f90}, - {aarch32_op_VQSHRUN_VQMOVUN_A1, "vqshrun VQSHRUN_VQMOVUN_A1", {OPR_reg_Dd, OPR_reg_Qm}, 0xf3b20240, 0xffb30fd0}, - {aarch32_op_VQSUB_A1_D, "vqsub VQSUB_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000210, 0xfe800f50}, - {aarch32_op_VQSUB_A1_Q, "vqsub VQSUB_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000250, 0xfe800f50}, - {aarch32_op_VRADDHN_A1, "vraddhn VRADDHN_A1", {OPR_reg_Dd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3800400, 0xff800f50}, - {aarch32_op_VRECPE_A1_D, "vrecpe VRECPE_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b30400, 0xffb30ed0}, - {aarch32_op_VRECPE_A1_Q, "vrecpe VRECPE_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b30440, 0xffb30ed0}, - {aarch32_op_VRECPS_A1_D, "vrecps VRECPS_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000f10, 0xffa00f50}, - {aarch32_op_VRECPS_A1_Q, "vrecps VRECPS_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000f50, 0xffa00f50}, - {aarch32_op_VREV16_A1_D, "vrev16 VREV16_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b00100, 0xffb30fd0}, - {aarch32_op_VREV16_A1_Q, "vrev16 VREV16_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b00140, 0xffb30fd0}, - {aarch32_op_VREV32_A1_D, "vrev32 VREV32_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b00080, 0xffb30fd0}, - {aarch32_op_VREV32_A1_Q, "vrev32 VREV32_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b000c0, 0xffb30fd0}, - {aarch32_op_VREV64_A1_D, "vrev64 VREV64_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b00000, 0xffb30fd0}, - {aarch32_op_VREV64_A1_Q, "vrev64 VREV64_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b00040, 0xffb30fd0}, - {aarch32_op_VRHADD_A1_D, "vrhadd VRHADD_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000100, 0xfe800f50}, - {aarch32_op_VRHADD_A1_Q, "vrhadd VRHADD_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000140, 0xfe800f50}, - {aarch32_op_VRINTA_asimd_A1_D, "vrinta VRINTA_asimd_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b20500, 0xffb30fd0}, - {aarch32_op_VRINTA_asimd_A1_Q, "vrinta VRINTA_asimd_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b20540, 0xffb30fd0}, - {aarch32_op_VRINTA_vfp_A1_H, "vrinta VRINTA_vfp_A1_H", {OPR_reg_Sd, OPR_reg_Sm}, 0xfeb80940, 0xffbf0fd0}, - {aarch32_op_VRINTA_vfp_A1_S, "vrinta VRINTA_vfp_A1_S", {OPR_reg_Sd, OPR_reg_Sm}, 0xfeb80a40, 0xffbf0fd0}, - {aarch32_op_VRINTA_vfp_A1_D, "vrinta VRINTA_vfp_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xfeb80b40, 0xffbf0fd0}, - {aarch32_op_VRINTM_asimd_A1_D, "vrintm VRINTM_asimd_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b20680, 0xffb30fd0}, - {aarch32_op_VRINTM_asimd_A1_Q, "vrintm VRINTM_asimd_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b206c0, 0xffb30fd0}, - {aarch32_op_VRINTM_vfp_A1_H, "vrintm VRINTM_vfp_A1_H", {OPR_reg_Sd, OPR_reg_Sm}, 0xfebb0940, 0xffbf0fd0}, - {aarch32_op_VRINTM_vfp_A1_S, "vrintm VRINTM_vfp_A1_S", {OPR_reg_Sd, OPR_reg_Sm}, 0xfebb0a40, 0xffbf0fd0}, - {aarch32_op_VRINTM_vfp_A1_D, "vrintm VRINTM_vfp_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xfebb0b40, 0xffbf0fd0}, - {aarch32_op_VRINTN_asimd_A1_D, "vrintn VRINTN_asimd_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b20400, 0xffb30fd0}, - {aarch32_op_VRINTN_asimd_A1_Q, "vrintn VRINTN_asimd_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b20440, 0xffb30fd0}, - {aarch32_op_VRINTN_vfp_A1_H, "vrintn VRINTN_vfp_A1_H", {OPR_reg_Sd, OPR_reg_Sm}, 0xfeb90940, 0xffbf0fd0}, - {aarch32_op_VRINTN_vfp_A1_S, "vrintn VRINTN_vfp_A1_S", {OPR_reg_Sd, OPR_reg_Sm}, 0xfeb90a40, 0xffbf0fd0}, - {aarch32_op_VRINTN_vfp_A1_D, "vrintn VRINTN_vfp_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xfeb90b40, 0xffbf0fd0}, - {aarch32_op_VRINTP_asimd_A1_D, "vrintp VRINTP_asimd_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b20780, 0xffb30fd0}, - {aarch32_op_VRINTP_asimd_A1_Q, "vrintp VRINTP_asimd_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b207c0, 0xffb30fd0}, - {aarch32_op_VRINTP_vfp_A1_H, "vrintp VRINTP_vfp_A1_H", {OPR_reg_Sd, OPR_reg_Sm}, 0xfeba0940, 0xffbf0fd0}, - {aarch32_op_VRINTP_vfp_A1_S, "vrintp VRINTP_vfp_A1_S", {OPR_reg_Sd, OPR_reg_Sm}, 0xfeba0a40, 0xffbf0fd0}, - {aarch32_op_VRINTP_vfp_A1_D, "vrintp VRINTP_vfp_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xfeba0b40, 0xffbf0fd0}, - {aarch32_op_VRINTR_vfp_A1_H, "vrintr VRINTR_vfp_A1_H", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb60940, 0x0fbf0fd0}, - {aarch32_op_VRINTR_vfp_A1_S, "vrintr VRINTR_vfp_A1_S", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb60a40, 0x0fbf0fd0}, - {aarch32_op_VRINTR_vfp_A1_D, "vrintr VRINTR_vfp_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0x0eb60b40, 0x0fbf0fd0}, - {aarch32_op_VRINTX_asimd_A1_D, "vrintx VRINTX_asimd_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b20480, 0xffb30fd0}, - {aarch32_op_VRINTX_asimd_A1_Q, "vrintx VRINTX_asimd_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b204c0, 0xffb30fd0}, - {aarch32_op_VRINTX_vfp_A1_H, "vrintx VRINTX_vfp_A1_H", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb70940, 0x0fbf0fd0}, - {aarch32_op_VRINTX_vfp_A1_S, "vrintx VRINTX_vfp_A1_S", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb70a40, 0x0fbf0fd0}, - {aarch32_op_VRINTX_vfp_A1_D, "vrintx VRINTX_vfp_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0x0eb70b40, 0x0fbf0fd0}, - {aarch32_op_VRINTZ_asimd_A1_D, "vrintz VRINTZ_asimd_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b20580, 0xffb30fd0}, - {aarch32_op_VRINTZ_asimd_A1_Q, "vrintz VRINTZ_asimd_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b205c0, 0xffb30fd0}, - {aarch32_op_VRINTZ_vfp_A1_H, "vrintz VRINTZ_vfp_A1_H", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb609c0, 0x0fbf0fd0}, - {aarch32_op_VRINTZ_vfp_A1_S, "vrintz VRINTZ_vfp_A1_S", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb60ac0, 0x0fbf0fd0}, - {aarch32_op_VRINTZ_vfp_A1_D, "vrintz VRINTZ_vfp_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0x0eb60bc0, 0x0fbf0fd0}, - {aarch32_op_VRSHL_A1_D, "vrshl VRSHL_A1_D", {OPR_reg_Dd, OPR_reg_Dm, OPR_reg_Dn}, 0xf2000500, 0xfe800f50}, - {aarch32_op_VRSHL_A1_Q, "vrshl VRSHL_A1_Q", {OPR_reg_Qd, OPR_reg_Qm, OPR_reg_Qn}, 0xf2000540, 0xfe800f50}, - {aarch32_op_VRSHR_A1_D, "vrshr VRSHR_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf2800210, 0xfe800f50}, - {aarch32_op_VRSHR_A1_Q, "vrshr VRSHR_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf2800250, 0xfe800f50}, - {aarch32_op_VRSHR_VORR_r_A1_D, "vrshr VRSHR_VORR_r_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf2200110, 0xffb00f50}, - {aarch32_op_VRSHR_VORR_r_A1_Q, "vrshr VRSHR_VORR_r_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf2200150, 0xffb00f50}, - {aarch32_op_VRSHRN_A1, "vrshrn VRSHRN_A1", {OPR_reg_Dd, OPR_reg_Qm}, 0xf2800850, 0xff800fd0}, - {aarch32_op_VRSHRN_VMOVN_A1, "vrshrn VRSHRN_VMOVN_A1", {OPR_reg_Dd, OPR_reg_Qm}, 0xf3b20200, 0xffb30fd0}, - {aarch32_op_VRSQRTE_A1_D, "vrsqrte VRSQRTE_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b30480, 0xffb30ed0}, - {aarch32_op_VRSQRTE_A1_Q, "vrsqrte VRSQRTE_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b304c0, 0xffb30ed0}, - {aarch32_op_VRSQRTS_A1_D, "vrsqrts VRSQRTS_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2200f10, 0xffa00f50}, - {aarch32_op_VRSQRTS_A1_Q, "vrsqrts VRSQRTS_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2200f50, 0xffa00f50}, - {aarch32_op_VRSRA_A1_Q, "vrsra VRSRA_A1_Q", {OPR_reg_Dd, OPR_reg_Dm}, 0xf2800310, 0xfe800f50}, - {aarch32_op_VRSRA_A1_D, "vrsra VRSRA_A1_D", {OPR_reg_Qd, OPR_reg_Qm}, 0xf2800350, 0xfe800f50}, - {aarch32_op_VRSUBHN_A1, "vrsubhn VRSUBHN_A1", {OPR_reg_Dd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3800600, 0xff800f50}, - {aarch32_op_VSELEQ_A1_D, "vseleq VSELEQ_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xfe000b00, 0xffb00f50}, - {aarch32_op_VSELEQ_A1_H, "vseleq VSELEQ_A1_H", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0xfe000900, 0xffb00f50}, - {aarch32_op_VSELEQ_A1_S, "vseleq VSELEQ_A1_S", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0xfe000a00, 0xffb00f50}, - {aarch32_op_VSELGE_A1_D, "vselge VSELGE_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xfe200b00, 0xffb00f50}, - {aarch32_op_VSELGE_A1_H, "vselge VSELGE_A1_H", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0xfe200900, 0xffb00f50}, - {aarch32_op_VSELGE_A1_S, "vselge VSELGE_A1_S", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0xfe200a00, 0xffb00f50}, - {aarch32_op_VSELGT_A1_D, "vselgt VSELGT_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xfe300b00, 0xffb00f50}, - {aarch32_op_VSELGT_A1_H, "vselgt VSELGT_A1_H", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0xfe300900, 0xffb00f50}, - {aarch32_op_VSELGT_A1_S, "vselgt VSELGT_A1_S", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0xfe300a00, 0xffb00f50}, - {aarch32_op_VSELVS_A1_D, "vselvs VSELVS_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xfe100b00, 0xffb00f50}, - {aarch32_op_VSELVS_A1_H, "vselvs VSELVS_A1_H", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0xfe100900, 0xffb00f50}, - {aarch32_op_VSELVS_A1_S, "vselvs VSELVS_A1_S", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0xfe100a00, 0xffb00f50}, - {aarch32_op_VSHL_i_A1_D, "vshl VSHL_i_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf2800510, 0xff800f50}, - {aarch32_op_VSHL_i_A1_Q, "vshl VSHL_i_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf2800550, 0xff800f50}, - {aarch32_op_VSHL_r_A1_D, "vshl VSHL_r_A1_D", {OPR_reg_Dd, OPR_reg_Dm, OPR_reg_Dn}, 0xf2000400, 0xfe800f50}, - {aarch32_op_VSHL_r_A1_Q, "vshl VSHL_r_A1_Q", {OPR_reg_Qd, OPR_reg_Qm, OPR_reg_Qn}, 0xf2000440, 0xfe800f50}, - {aarch32_op_VSHLL_A1, "vshll VSHLL_A1", {OPR_reg_Qd, OPR_reg_Dm}, 0xf2800a10, 0xfe800fd0}, - {aarch32_op_VSHLL_A2, "vshll VSHLL_A2", {OPR_reg_Qd, OPR_reg_Dm}, 0xf3b20300, 0xffb30fd0}, - {aarch32_op_VSHR_A1_D, "vshr VSHR_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf2800010, 0xfe800f50}, - {aarch32_op_VSHR_A1_Q, "vshr VSHR_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf2800050, 0xfe800f50}, - {aarch32_op_VSHR_VORR_r_A1_D, "vshr VSHR_VORR_r_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf2200110, 0xffb00f50}, - {aarch32_op_VSHR_VORR_r_A1_Q, "vshr VSHR_VORR_r_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf2200150, 0xffb00f50}, - {aarch32_op_VSHRN_A1, "vshrn VSHRN_A1", {OPR_reg_Dd, OPR_reg_Qm}, 0xf2800810, 0xff800fd0}, - {aarch32_op_VSHRN_VMOVN_A1, "vshrn VSHRN_VMOVN_A1", {OPR_reg_Dd, OPR_reg_Qm}, 0xf3b20200, 0xffb30fd0}, - {aarch32_op_VSLI_A1_D, "vsli VSLI_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3800510, 0xff800f50}, - {aarch32_op_VSLI_A1_Q, "vsli VSLI_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3800550, 0xff800f50}, - {aarch32_op_VSQRT_A1_H, "vsqrt VSQRT_A1_H", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb109c0, 0x0fbf0fd0}, - {aarch32_op_VSQRT_A1_S, "vsqrt VSQRT_A1_S", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb10ac0, 0x0fbf0fd0}, - {aarch32_op_VSQRT_A1_D, "vsqrt VSQRT_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0x0eb10bc0, 0x0fbf0fd0}, - {aarch32_op_VSRA_A1_D, "vsra VSRA_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf2800110, 0xfe800f50}, - {aarch32_op_VSRA_A1_Q, "vsra VSRA_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf2800150, 0xfe800f50}, - {aarch32_op_VSRI_A1_D, "vsri VSRI_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3800410, 0xff800f50}, - {aarch32_op_VSRI_A1_Q, "vsri VSRI_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3800450, 0xff800f50}, - {aarch32_op_VST1_1_A1_nowb, "vst1 VST1_1_A1_nowb", {OPR_reg_Rn}, 0xf480000f, 0xffb00f0f}, - {aarch32_op_VST1_1_A1_posti, "vst1 VST1_1_A1_posti", {OPR_reg_Rn}, 0xf480000d, 0xffb00f0f}, - {aarch32_op_VST1_1_A1_postr, "vst1 VST1_1_A1_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4800000, 0xffb00f00}, - {aarch32_op_VST1_1_A2_nowb, "vst1 VST1_1_A2_nowb", {OPR_reg_Rn}, 0xf480040f, 0xffb00f0f}, - {aarch32_op_VST1_1_A2_posti, "vst1 VST1_1_A2_posti", {OPR_reg_Rn}, 0xf480040d, 0xffb00f0f}, - {aarch32_op_VST1_1_A2_postr, "vst1 VST1_1_A2_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4800400, 0xffb00f00}, - {aarch32_op_VST1_1_A3_nowb, "vst1 VST1_1_A3_nowb", {OPR_reg_Rn}, 0xf480080f, 0xffb00f0f}, - {aarch32_op_VST1_1_A3_posti, "vst1 VST1_1_A3_posti", {OPR_reg_Rn}, 0xf480080d, 0xffb00f0f}, - {aarch32_op_VST1_1_A3_postr, "vst1 VST1_1_A3_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4800800, 0xffb00f00}, - {aarch32_op_VST1_m_A1_nowb, "vst1 VST1_m_A1_nowb", {OPR_reg_Rn}, 0xf400070f, 0xffb00f0f}, - {aarch32_op_VST1_m_A1_posti, "vst1 VST1_m_A1_posti", {OPR_reg_Rn}, 0xf400070d, 0xffb00f0f}, - {aarch32_op_VST1_m_A1_postr, "vst1 VST1_m_A1_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4000700, 0xffb00f00}, - {aarch32_op_VST1_m_A2_nowb, "vst1 VST1_m_A2_nowb", {OPR_reg_Rn}, 0xf4000a0f, 0xffb00f0f}, - {aarch32_op_VST1_m_A2_posti, "vst1 VST1_m_A2_posti", {OPR_reg_Rn}, 0xf4000a0d, 0xffb00f0f}, - {aarch32_op_VST1_m_A2_postr, "vst1 VST1_m_A2_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4000a00, 0xffb00f00}, - {aarch32_op_VST1_m_A3_nowb, "vst1 VST1_m_A3_nowb", {OPR_reg_Rn}, 0xf400060f, 0xffb00f0f}, - {aarch32_op_VST1_m_A3_posti, "vst1 VST1_m_A3_posti", {OPR_reg_Rn}, 0xf400060d, 0xffb00f0f}, - {aarch32_op_VST1_m_A3_postr, "vst1 VST1_m_A3_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4000600, 0xffb00f00}, - {aarch32_op_VST1_m_A4_nowb, "vst1 VST1_m_A4_nowb", {OPR_reg_Rn}, 0xf400020f, 0xffb00f0f}, - {aarch32_op_VST1_m_A4_posti, "vst1 VST1_m_A4_posti", {OPR_reg_Rn}, 0xf400020d, 0xffb00f0f}, - {aarch32_op_VST1_m_A4_postr, "vst1 VST1_m_A4_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4000200, 0xffb00f00}, - {aarch32_op_VST2_1_A1_nowb, "vst2 VST2_1_A1_nowb", {OPR_reg_Rn}, 0xf480010f, 0xffb00f0f}, - {aarch32_op_VST2_1_A1_posti, "vst2 VST2_1_A1_posti", {OPR_reg_Rn}, 0xf480010d, 0xffb00f0f}, - {aarch32_op_VST2_1_A1_postr, "vst2 VST2_1_A1_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4800100, 0xffb00f00}, - {aarch32_op_VST2_1_A2_nowb, "vst2 VST2_1_A2_nowb", {OPR_reg_Rn}, 0xf480050f, 0xffb00f0f}, - {aarch32_op_VST2_1_A2_posti, "vst2 VST2_1_A2_posti", {OPR_reg_Rn}, 0xf480050d, 0xffb00f0f}, - {aarch32_op_VST2_1_A2_postr, "vst2 VST2_1_A2_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4800500, 0xffb00f00}, - {aarch32_op_VST2_1_A3_nowb, "vst2 VST2_1_A3_nowb", {OPR_reg_Rn}, 0xf480090f, 0xffb00f0f}, - {aarch32_op_VST2_1_A3_posti, "vst2 VST2_1_A3_posti", {OPR_reg_Rn}, 0xf480090d, 0xffb00f0f}, - {aarch32_op_VST2_1_A3_postr, "vst2 VST2_1_A3_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4800900, 0xffb00f00}, - {aarch32_op_VST2_m_A1_nowb, "vst2 VST2_m_A1_nowb", {OPR_reg_Rn}, 0xf400080f, 0xffb00e0f}, - {aarch32_op_VST2_m_A1_posti, "vst2 VST2_m_A1_posti", {OPR_reg_Rn}, 0xf400080d, 0xffb00e0f}, - {aarch32_op_VST2_m_A1_postr, "vst2 VST2_m_A1_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4000800, 0xffb00e00}, - {aarch32_op_VST2_m_A2_nowb, "vst2 VST2_m_A2_nowb", {OPR_reg_Rn}, 0xf400030f, 0xffb00f0f}, - {aarch32_op_VST2_m_A2_posti, "vst2 VST2_m_A2_posti", {OPR_reg_Rn}, 0xf400030d, 0xffb00f0f}, - {aarch32_op_VST2_m_A2_postr, "vst2 VST2_m_A2_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4000300, 0xffb00f00}, - {aarch32_op_VST3_1_A1_nowb, "vst3 VST3_1_A1_nowb", {OPR_reg_Rn}, 0xf480020f, 0xffb00f0f}, - {aarch32_op_VST3_1_A1_posti, "vst3 VST3_1_A1_posti", {OPR_reg_Rn}, 0xf480020d, 0xffb00f0f}, - {aarch32_op_VST3_1_A1_postr, "vst3 VST3_1_A1_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4800200, 0xffb00f00}, - {aarch32_op_VST3_1_A2_nowb, "vst3 VST3_1_A2_nowb", {OPR_reg_Rn}, 0xf480060f, 0xffb00f0f}, - {aarch32_op_VST3_1_A2_posti, "vst3 VST3_1_A2_posti", {OPR_reg_Rn}, 0xf480060d, 0xffb00f0f}, - {aarch32_op_VST3_1_A2_postr, "vst3 VST3_1_A2_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4800600, 0xffb00f00}, - {aarch32_op_VST3_1_A3_nowb, "vst3 VST3_1_A3_nowb", {OPR_reg_Rn}, 0xf4800a0f, 0xffb00f0f}, - {aarch32_op_VST3_1_A3_posti, "vst3 VST3_1_A3_posti", {OPR_reg_Rn}, 0xf4800a0d, 0xffb00f0f}, - {aarch32_op_VST3_1_A3_postr, "vst3 VST3_1_A3_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4800a00, 0xffb00f00}, - {aarch32_op_VST3_m_A1_nowb, "vst3 VST3_m_A1_nowb", {OPR_reg_Rn}, 0xf400040f, 0xffb00e0f}, - {aarch32_op_VST3_m_A1_posti, "vst3 VST3_m_A1_posti", {OPR_reg_Rn}, 0xf400040d, 0xffb00e0f}, - {aarch32_op_VST3_m_A1_postr, "vst3 VST3_m_A1_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4000400, 0xffb00e00}, - {aarch32_op_VST4_1_A1_nowb, "vst4 VST4_1_A1_nowb", {OPR_reg_Rn}, 0xf480030f, 0xffb00f0f}, - {aarch32_op_VST4_1_A1_posti, "vst4 VST4_1_A1_posti", {OPR_reg_Rn}, 0xf480030d, 0xffb00f0f}, - {aarch32_op_VST4_1_A1_postr, "vst4 VST4_1_A1_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4800300, 0xffb00f00}, - {aarch32_op_VST4_1_A2_nowb, "vst4 VST4_1_A2_nowb", {OPR_reg_Rn}, 0xf480070f, 0xffb00f0f}, - {aarch32_op_VST4_1_A2_posti, "vst4 VST4_1_A2_posti", {OPR_reg_Rn}, 0xf480070d, 0xffb00f0f}, - {aarch32_op_VST4_1_A2_postr, "vst4 VST4_1_A2_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4800700, 0xffb00f00}, - {aarch32_op_VST4_1_A3_nowb, "vst4 VST4_1_A3_nowb", {OPR_reg_Rn}, 0xf4800b0f, 0xffb00f0f}, - {aarch32_op_VST4_1_A3_posti, "vst4 VST4_1_A3_posti", {OPR_reg_Rn}, 0xf4800b0d, 0xffb00f0f}, - {aarch32_op_VST4_1_A3_postr, "vst4 VST4_1_A3_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4800b00, 0xffb00f00}, - {aarch32_op_VST4_m_A1_nowb, "vst4 VST4_m_A1_nowb", {OPR_reg_Rn}, 0xf400000f, 0xffb00e0f}, - {aarch32_op_VST4_m_A1_posti, "vst4 VST4_m_A1_posti", {OPR_reg_Rn}, 0xf400000d, 0xffb00e0f}, - {aarch32_op_VST4_m_A1_postr, "vst4 VST4_m_A1_postr", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4000000, 0xffb00e00}, - {aarch32_op_VSTMDB_A1, "vstmdb VSTMDB_A1", {OPR_reg_Rn}, 0x0d200b00, 0x0fb00f01}, - {aarch32_op_VSTM_A1, "vstm VSTM_A1", {OPR_reg_Rn}, 0x0c800b00, 0x0f900f01}, - {aarch32_op_VSTMDB_A2, "vstmdb VSTMDB_A2", {OPR_reg_Rn}, 0x0d200a00, 0x0fb00f00}, - {aarch32_op_VSTM_A2, "vstm VSTM_A2", {OPR_reg_Rn}, 0x0c800a00, 0x0f900f00}, - {aarch32_op_VSTR_A1_H, "vstr VSTR_A1_H", {OPR_reg_Sd, OPR_reg_Rn}, 0x0d000900, 0x0f300f00}, - {aarch32_op_VSTR_A1_S, "vstr VSTR_A1_S", {OPR_reg_Sd, OPR_reg_Rn}, 0x0d000a00, 0x0f300f00}, - {aarch32_op_VSTR_A1_D, "vstr VSTR_A1_D", {OPR_reg_Dd, OPR_reg_Rn}, 0x0d000b00, 0x0f300f00}, - {aarch32_op_VSUB_f_A1_D, "vsub VSUB_f_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2200d00, 0xffa00f50}, - {aarch32_op_VSUB_f_A1_Q, "vsub VSUB_f_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2200d40, 0xffa00f50}, - {aarch32_op_VSUB_f_A2_H, "vsub VSUB_f_A2_H", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e300940, 0x0fb00f50}, - {aarch32_op_VSUB_f_A2_S, "vsub VSUB_f_A2_S", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e300a40, 0x0fb00f50}, - {aarch32_op_VSUB_f_A2_D, "vsub VSUB_f_A2_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0x0e300b40, 0x0fb00f50}, - {aarch32_op_VSUB_i_A1_D, "vsub VSUB_i_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3000800, 0xff800f50}, - {aarch32_op_VSUB_i_A1_Q, "vsub VSUB_i_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3000840, 0xff800f50}, - {aarch32_op_VSUBHN_A1, "vsubhn VSUBHN_A1", {OPR_reg_Dd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2800600, 0xff800f50}, - {aarch32_op_VSUBL_A1, "vsubl VSUBL_A1", {OPR_reg_Qd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2800200, 0xfe800f50}, - {aarch32_op_VSUBW_A1, "vsubw VSUBW_A1", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Dm}, 0xf2800300, 0xfe800f50}, - {aarch32_op_VSWP_A1_D, "vswp VSWP_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b20000, 0xffbf0fd0}, - {aarch32_op_VSWP_A1_Q, "vswp VSWP_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b20040, 0xffbf0fd0}, - {aarch32_op_VTBL_A1, "vtbl VTBL_A1", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b00800, 0xffb00c50}, - {aarch32_op_VTBX_A1, "vtbx VTBX_A1", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b00840, 0xffb00c50}, - {aarch32_op_VTRN_A1_D, "vtrn VTRN_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b20080, 0xffb30fd0}, - {aarch32_op_VTRN_A1_Q, "vtrn VTRN_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b200c0, 0xffb30fd0}, - {aarch32_op_VTST_A1_D, "vtst VTST_A1_D", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000810, 0xff800f50}, - {aarch32_op_VTST_A1_Q, "vtst VTST_A1_Q", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000850, 0xff800f50}, - {aarch32_op_VUZP_A1_D, "vuzp VUZP_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b20100, 0xffb30fd0}, - {aarch32_op_VUZP_A1_Q, "vuzp VUZP_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b20140, 0xffb30fd0}, - {aarch32_op_VUZP_VTRN_A1_D, "vuzp VUZP_VTRN_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b20080, 0xffb30fd0}, - {aarch32_op_VZIP_A1_D, "vzip VZIP_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b20180, 0xffb30fd0}, - {aarch32_op_VZIP_A1_Q, "vzip VZIP_A1_Q", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b201c0, 0xffb30fd0}, - {aarch32_op_VZIP_VTRN_A1_D, "vzip VZIP_VTRN_A1_D", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b20080, 0xffb30fd0}, - {aarch32_op_WFE_A1, "wfe WFE_A1", {}, 0x03200002, 0x0fff00ff}, - {aarch32_op_WFI_A1, "wfi WFI_A1", {}, 0x03200003, 0x0fff00ff}, - {aarch32_op_YIELD_A1, "yield YIELD_A1", {}, 0x03200001, 0x0fff00ff} + {aarch32_op_ADC_i_A1, "adc", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x02a00000, 0x0ff00000}, + {aarch32_op_ADCS_i_A1, "adcs", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x02b00000, 0x0ff00000}, + {aarch32_op_ADC_r_A1_RRX, "adc", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00a00060, 0x0ff00ff0}, + {aarch32_op_ADC_r_A1, "adc", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00a00000, 0x0ff00010}, + {aarch32_op_ADCS_r_A1_RRX, "adcs", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00b00060, 0x0ff00ff0}, + {aarch32_op_ADCS_r_A1, "adcs", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00b00000, 0x0ff00010}, + {aarch32_op_ADCS_rr_A1, "adcs", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x00b00010, 0x0ff00090}, + {aarch32_op_ADC_rr_A1, "adc", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x00a00010, 0x0ff00090}, + {aarch32_op_ADD_ADR_A1, "add", {OPR_reg_Rd, OPR_imm_const}, 0x028f0000, 0x0fff0000}, + {aarch32_op_ADD_i_A1, "add", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x02800000, 0x0ff00000}, + {aarch32_op_ADDS_i_A1, "adds", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x02900000, 0x0ff00000}, + {aarch32_op_ADD_r_A1_RRX, "add", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00800060, 0x0ff00ff0}, + {aarch32_op_ADD_r_A1, "add", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00800000, 0x0ff00010}, + {aarch32_op_ADDS_r_A1_RRX, "adds", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00900060, 0x0ff00ff0}, + {aarch32_op_ADDS_r_A1, "adds", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00900000, 0x0ff00010}, + {aarch32_op_ADDS_rr_A1, "adds", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x00900010, 0x0ff00090}, + {aarch32_op_ADD_rr_A1, "add", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x00800010, 0x0ff00090}, + {aarch32_op_ADD_SP_i_A1, "add", {OPR_reg_Rd, OPR_imm_const}, 0x028d0000, 0x0fff0000}, + {aarch32_op_ADDS_SP_i_A1, "adds", {OPR_reg_Rd, OPR_imm_const}, 0x029d0000, 0x0fff0000}, + {aarch32_op_ADD_SP_r_A1_RRX, "add", {OPR_reg_Rd, OPR_reg_Rm}, 0x008d0060, 0x0fff0ff0}, + {aarch32_op_ADD_SP_r_A1, "add", {OPR_reg_Rd, OPR_reg_Rm}, 0x008d0000, 0x0fff0010}, + {aarch32_op_ADDS_SP_r_A1_RRX, "adds", {OPR_reg_Rd, OPR_reg_Rm}, 0x009d0060, 0x0fff0ff0}, + {aarch32_op_ADDS_SP_r_A1, "adds", {OPR_reg_Rd, OPR_reg_Rm}, 0x009d0000, 0x0fff0010}, + {aarch32_op_ADR_A1, "adr", {OPR_reg_Rd, OPR_imm_label}, 0x028f0000, 0x0fff0000}, + {aarch32_op_ADR_A2, "adr", {OPR_reg_Rd, OPR_imm_label}, 0x024f0000, 0x0fff0000}, + {aarch32_op_AESD_A1, "aesd", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b00340, 0xffb30fd0}, + {aarch32_op_AESE_A1, "aese", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b00300, 0xffb30fd0}, + {aarch32_op_AESIMC_A1, "aesimc", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b003c0, 0xffb30fd0}, + {aarch32_op_AESMC_A1, "aesmc", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b00380, 0xffb30fd0}, + {aarch32_op_AND_i_A1, "and", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x02000000, 0x0ff00000}, + {aarch32_op_ANDS_i_A1, "ands", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x02100000, 0x0ff00000}, + {aarch32_op_AND_r_A1_RRX, "and", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00000060, 0x0ff00ff0}, + {aarch32_op_AND_r_A1, "and", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00000000, 0x0ff00010}, + {aarch32_op_ANDS_r_A1_RRX, "ands", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00100060, 0x0ff00ff0}, + {aarch32_op_ANDS_r_A1, "ands", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00100000, 0x0ff00010}, + {aarch32_op_ANDS_rr_A1, "ands", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x00100010, 0x0ff00090}, + {aarch32_op_AND_rr_A1, "and", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x00000010, 0x0ff00090}, + {aarch32_op_ASR_MOV_r_A1, "asr", {OPR_reg_Rd, OPR_reg_Rm}, 0x01a00040, 0x0ff00070}, + {aarch32_op_ASR_MOV_rr_A1, "asr", {OPR_reg_Rd, OPR_reg_Rm, OPR_reg_Rs}, 0x01a00050, 0x0ff000f0}, + {aarch32_op_ASRS_MOVS_r_A1, "asrs", {OPR_reg_Rd, OPR_reg_Rm}, 0x01b00040, 0x0ff00070}, + {aarch32_op_ASRS_MOVS_rr_A1, "asrs", {OPR_reg_Rd, OPR_reg_Rm, OPR_reg_Rs}, 0x01b00050, 0x0ff000f0}, + {aarch32_op_B_A1, "b", {OPR_imm_label_2}, 0x0a000000, 0x0f000000}, + {aarch32_op_BFC_A1, "bfc", {OPR_reg_Rd}, 0x07c0001f, 0x0fe0007f}, + {aarch32_op_BFI_A1, "bfi", {OPR_reg_Rd, OPR_reg_Rn_2}, 0x07c00010, 0x0fe00070}, + {aarch32_op_BIC_i_A1, "bic", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x03c00000, 0x0ff00000}, + {aarch32_op_BICS_i_A1, "bics", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x03d00000, 0x0ff00000}, + {aarch32_op_BIC_r_A1_RRX, "bic", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x01c00060, 0x0ff00ff0}, + {aarch32_op_BIC_r_A1, "bic", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x01c00000, 0x0ff00010}, + {aarch32_op_BICS_r_A1_RRX, "bics", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x01d00060, 0x0ff00ff0}, + {aarch32_op_BICS_r_A1, "bics", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x01d00000, 0x0ff00010}, + {aarch32_op_BICS_rr_A1, "bics", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x01d00010, 0x0ff00090}, + {aarch32_op_BIC_rr_A1, "bic", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x01c00010, 0x0ff00090}, + {aarch32_op_BKPT_A1, "bkpt", {}, 0x01200070, 0x0ff000f0}, + {aarch32_op_BL_i_A1, "bl", {OPR_imm_label}, 0x0b000000, 0x0f000000}, + {aarch32_op_BL_i_A2, "blx", {OPR_imm_label_3}, 0xfa000000, 0xfe000000}, + {aarch32_op_BLX_r_A1, "blx", {OPR_reg_Rm}, 0x01200030, 0x0ff000f0}, + {aarch32_op_BX_A1, "bx", {OPR_reg_Rm}, 0x01200010, 0x0ff000f0}, + {aarch32_op_BXJ_A1, "bxj", {OPR_reg_Rm}, 0x01200020, 0x0ff000f0}, + {aarch32_op_CLREX_A1, "clrex", {}, 0xf5700010, 0xfff000f0}, + {aarch32_op_CLZ_A1, "clz", {OPR_reg_Rd, OPR_reg_Rm}, 0x01600010, 0x0ff000f0}, + {aarch32_op_CMN_i_A1, "cmn", {OPR_reg_Rn, OPR_imm_const}, 0x03700000, 0x0ff00000}, + {aarch32_op_CMN_r_A1_RRX, "cmn", {OPR_reg_Rn, OPR_reg_Rm}, 0x01700060, 0x0ff00ff0}, + {aarch32_op_CMN_r_A1, "cmn", {OPR_reg_Rn, OPR_reg_Rm}, 0x01700000, 0x0ff00010}, + {aarch32_op_CMN_rr_A1, "cmn", {OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x01700010, 0x0ff00090}, + {aarch32_op_CMP_i_A1, "cmp", {OPR_reg_Rn, OPR_imm_const}, 0x03500000, 0x0ff00000}, + {aarch32_op_CMP_r_A1_RRX, "cmp", {OPR_reg_Rn, OPR_reg_Rm}, 0x01500060, 0x0ff00ff0}, + {aarch32_op_CMP_r_A1, "cmp", {OPR_reg_Rn, OPR_reg_Rm}, 0x01500000, 0x0ff00010}, + {aarch32_op_CMP_rr_A1, "cmp", {OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x01500010, 0x0ff00090}, + {aarch32_op_CPS_A1_AS, "cps", {}, 0xf1020000, 0xffff0020}, + {aarch32_op_CPSID_A1_AS, "cpsid", {}, 0xf10c0000, 0xffff0020}, + {aarch32_op_CPSID_A1_ASM, "cpsid", {}, 0xf10e0000, 0xffff0020}, + {aarch32_op_CPSIE_A1_AS, "cpsie", {}, 0xf1080000, 0xffff0020}, + {aarch32_op_CPSIE_A1_ASM, "cpsie", {}, 0xf10a0000, 0xffff0020}, + {aarch32_op_CRC32B_A1, "crc32b", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x01000040, 0x0ff002f0}, + {aarch32_op_CRC32H_A1, "crc32h", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x01200040, 0x0ff002f0}, + {aarch32_op_CRC32W_A1, "crc32w", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x01400040, 0x0ff002f0}, + {aarch32_op_CRC32CB_A1, "crc32cb", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x01000240, 0x0ff002f0}, + {aarch32_op_CRC32CH_A1, "crc32ch", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x01200240, 0x0ff002f0}, + {aarch32_op_CRC32CW_A1, "crc32cw", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x01400240, 0x0ff002f0}, + {aarch32_op_DBG_A1, "dbg", {}, 0x032000f0, 0x0fff00f0}, + {aarch32_op_DMB_A1, "dmb", {}, 0xf5700050, 0xfff000f0}, + {aarch32_op_DSB_A1, "dsb", {}, 0xf5700040, 0xfff000f0}, + {aarch32_op_EOR_i_A1, "eor", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x02200000, 0x0ff00000}, + {aarch32_op_EORS_i_A1, "eors", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x02300000, 0x0ff00000}, + {aarch32_op_EOR_r_A1_RRX, "eor", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00200060, 0x0ff00ff0}, + {aarch32_op_EOR_r_A1, "eor", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00200000, 0x0ff00010}, + {aarch32_op_EORS_r_A1_RRX, "eors", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00300060, 0x0ff00ff0}, + {aarch32_op_EORS_r_A1, "eors", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00300000, 0x0ff00010}, + {aarch32_op_EORS_rr_A1, "eors", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x00300010, 0x0ff00090}, + {aarch32_op_EOR_rr_A1, "eor", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x00200010, 0x0ff00090}, + {aarch32_op_ERET_A1, "eret", {}, 0x01600060, 0x0ff000f0}, + {aarch32_op_ESB_A1, "esb", {}, 0x03200010, 0x0fff00ff}, + {aarch32_op_FLDMDBX_A1, "fldmdbx", {OPR_reg_Rn}, 0x0d300b01, 0x0fb00f01}, + {aarch32_op_FLDMIAX_A1, "fldmiax", {OPR_reg_Rn}, 0x0c900b01, 0x0f900f01}, + {aarch32_op_FSTMDBX_A1, "fstmdbx", {OPR_reg_Rn}, 0x0d200b01, 0x0fb00f01}, + {aarch32_op_FSTMIAX_A1, "fstmiax", {OPR_reg_Rn}, 0x0c800b01, 0x0f900f01}, + {aarch32_op_HLT_A1, "hlt", {}, 0x01000070, 0x0ff000f0}, + {aarch32_op_HVC_A1, "hvc", {}, 0x01400070, 0x0ff000f0}, + {aarch32_op_ISB_A1, "isb", {}, 0xf5700060, 0xfff000f0}, + {aarch32_op_LDA_A1, "lda", {OPR_reg_Rt, OPR_reg_Rn}, 0x01900090, 0x0ff003f0}, + {aarch32_op_LDAB_A1, "ldab", {OPR_reg_Rt, OPR_reg_Rn}, 0x01d00090, 0x0ff003f0}, + {aarch32_op_LDAEX_A1, "ldaex", {OPR_reg_Rt, OPR_reg_Rn}, 0x01900290, 0x0ff003f0}, + {aarch32_op_LDAEXB_A1, "ldaexb", {OPR_reg_Rt, OPR_reg_Rn}, 0x01d00290, 0x0ff003f0}, + {aarch32_op_LDAEXD_A1, "ldaexd", {OPR_reg_Rt, OPR_reg_Rt2, OPR_reg_Rn}, 0x01b00290, 0x0ff003f0}, + {aarch32_op_LDAEXH_A1, "ldaexh", {OPR_reg_Rt, OPR_reg_Rn}, 0x01f00290, 0x0ff003f0}, + {aarch32_op_LDAH_A1, "ldah", {OPR_reg_Rt, OPR_reg_Rn}, 0x01f00090, 0x0ff003f0}, + {aarch32_op_LDC_i_A1_off, "ldc", {OPR_reg_Rn}, 0x0d105e00, 0x0f70ff00}, + {aarch32_op_LDC_i_A1_post, "ldc", {OPR_reg_Rn_3}, 0x0c305e00, 0x0f70ff00}, + {aarch32_op_LDC_i_A1_pre, "ldc", {OPR_reg_Rn}, 0x0d305e00, 0x0f70ff00}, + {aarch32_op_LDC_i_A1_unind, "ldc", {OPR_reg_Rn}, 0x0c905e00, 0x0ff0ff00}, + {aarch32_op_LDC_l_A1, "ldc", {OPR_imm_label_4}, 0x0c1f5e00, 0x0e1fff00}, + {aarch32_op_LDM_A1, "ldm", {OPR_reg_Rn, OPR_reglist}, 0x08900000, 0x0fd00000}, + {aarch32_op_LDM_e_A1_AS, "ldm", {OPR_reg_Rn, OPR_reglist_2}, 0x08508000, 0x0e508000}, + {aarch32_op_LDM_u_A1_AS, "ldm", {OPR_reg_Rn, OPR_reglist}, 0x08500000, 0x0e508000}, + {aarch32_op_LDMDA_A1, "ldm", {OPR_reg_Rn, OPR_reglist}, 0x08100000, 0x0fd00000}, + {aarch32_op_LDMDB_A1, "ldm", {OPR_reg_Rn, OPR_reglist}, 0x09100000, 0x0fd00000}, + {aarch32_op_LDMIB_A1, "ldm", {OPR_reg_Rn, OPR_reglist}, 0x09900000, 0x0fd00000}, + {aarch32_op_LDR_i_A1_off, "ldr", {OPR_reg_Rt, OPR_reg_Rn}, 0x05100000, 0x0f700000}, + {aarch32_op_LDR_i_A1_post, "ldr", {OPR_reg_Rt, OPR_reg_Rn}, 0x04100000, 0x0f700000}, + {aarch32_op_LDR_i_A1_pre, "ldr", {OPR_reg_Rt, OPR_reg_Rn}, 0x05300000, 0x0f700000}, + {aarch32_op_LDR_l_A1, "ldr", {OPR_reg_Rt, OPR_imm_label_5}, 0x041f0000, 0x0e5f0000}, + {aarch32_op_LDR_r_A1_off, "ldr", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x07100000, 0x0f700010}, + {aarch32_op_LDR_r_A1_post, "ldr", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x06100000, 0x0f700010}, + {aarch32_op_LDR_r_A1_pre, "ldr", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x07300000, 0x0f700010}, + {aarch32_op_LDRB_i_A1_off, "ldrb", {OPR_reg_Rt, OPR_reg_Rn}, 0x05500000, 0x0f700000}, + {aarch32_op_LDRB_i_A1_post, "ldrb", {OPR_reg_Rt, OPR_reg_Rn}, 0x04500000, 0x0f700000}, + {aarch32_op_LDRB_i_A1_pre, "ldrb", {OPR_reg_Rt, OPR_reg_Rn}, 0x05700000, 0x0f700000}, + {aarch32_op_LDRB_l_A1, "ldrb", {OPR_reg_Rt, OPR_imm_label}, 0x045f0000, 0x0e5f0000}, + {aarch32_op_LDRB_r_A1_off, "ldrb", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x07500000, 0x0f700010}, + {aarch32_op_LDRB_r_A1_post, "ldrb", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x06500000, 0x0f700010}, + {aarch32_op_LDRB_r_A1_pre, "ldrb", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x07700000, 0x0f700010}, + {aarch32_op_LDRBT_A1, "ldrbt", {OPR_reg_Rt, OPR_reg_Rn}, 0x04700000, 0x0f700000}, + {aarch32_op_LDRBT_A2, "ldrbt", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x06700000, 0x0f700010}, + {aarch32_op_LDRD_i_A1_off, "ldrd", {OPR_reg_Rt, OPR_reg_Rt2, OPR_reg_Rn}, 0x014000d0, 0x0f7000f0}, + {aarch32_op_LDRD_i_A1_post, "ldrd", {OPR_reg_Rt, OPR_reg_Rt2, OPR_reg_Rn}, 0x004000d0, 0x0f7000f0}, + {aarch32_op_LDRD_i_A1_pre, "ldrd", {OPR_reg_Rt, OPR_reg_Rt2, OPR_reg_Rn}, 0x016000d0, 0x0f7000f0}, + {aarch32_op_LDRD_l_A1, "ldrd", {OPR_reg_Rt, OPR_reg_Rt2, OPR_imm_label_6}, 0x004f00d0, 0x0e5f00f0}, + {aarch32_op_LDRD_r_A1_off, "ldrd", {OPR_reg_Rt, OPR_reg_Rt2, OPR_reg_Rn, OPR_reg_Rm}, 0x010000d0, 0x0f7000f0}, + {aarch32_op_LDRD_r_A1_post, "ldrd", {OPR_reg_Rt, OPR_reg_Rt2, OPR_reg_Rn, OPR_reg_Rm}, 0x000000d0, 0x0f7000f0}, + {aarch32_op_LDRD_r_A1_pre, "ldrd", {OPR_reg_Rt, OPR_reg_Rt2, OPR_reg_Rn, OPR_reg_Rm}, 0x012000d0, 0x0f7000f0}, + {aarch32_op_LDREX_A1, "ldrex", {OPR_reg_Rt, OPR_reg_Rn}, 0x01900390, 0x0ff003f0}, + {aarch32_op_LDREXB_A1, "ldrexb", {OPR_reg_Rt, OPR_reg_Rn}, 0x01d00390, 0x0ff003f0}, + {aarch32_op_LDREXD_A1, "ldrexd", {OPR_reg_Rt, OPR_reg_Rt2, OPR_reg_Rn}, 0x01b00390, 0x0ff003f0}, + {aarch32_op_LDREXH_A1, "ldrexh", {OPR_reg_Rt, OPR_reg_Rn}, 0x01f00390, 0x0ff003f0}, + {aarch32_op_LDRH_i_A1_off, "ldrh", {OPR_reg_Rt, OPR_reg_Rn}, 0x015000b0, 0x0f7000f0}, + {aarch32_op_LDRH_i_A1_post, "ldrh", {OPR_reg_Rt, OPR_reg_Rn}, 0x005000b0, 0x0f7000f0}, + {aarch32_op_LDRH_i_A1_pre, "ldrh", {OPR_reg_Rt, OPR_reg_Rn}, 0x017000b0, 0x0f7000f0}, + {aarch32_op_LDRH_l_A1, "ldrh", {OPR_reg_Rt, OPR_imm_label}, 0x005f00b0, 0x0e5f00f0}, + {aarch32_op_LDRH_r_A1_off, "ldrh", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x011000b0, 0x0f7000f0}, + {aarch32_op_LDRH_r_A1_post, "ldrh", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x001000b0, 0x0f7000f0}, + {aarch32_op_LDRH_r_A1_pre, "ldrh", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x013000b0, 0x0f7000f0}, + {aarch32_op_LDRHT_A1, "ldrht", {OPR_reg_Rt, OPR_reg_Rn}, 0x007000b0, 0x0f7000f0}, + {aarch32_op_LDRHT_A2, "ldrht", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x003000b0, 0x0f7000f0}, + {aarch32_op_LDRSB_i_A1_off, "ldrsb", {OPR_reg_Rt, OPR_reg_Rn}, 0x015000d0, 0x0f7000f0}, + {aarch32_op_LDRSB_i_A1_post, "ldrsb", {OPR_reg_Rt, OPR_reg_Rn}, 0x005000d0, 0x0f7000f0}, + {aarch32_op_LDRSB_i_A1_pre, "ldrsb", {OPR_reg_Rt, OPR_reg_Rn}, 0x017000d0, 0x0f7000f0}, + {aarch32_op_LDRSB_l_A1, "ldrsb", {OPR_reg_Rt, OPR_imm_label}, 0x005f00d0, 0x0e5f00f0}, + {aarch32_op_LDRSB_r_A1_off, "ldrsb", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x011000d0, 0x0f7000f0}, + {aarch32_op_LDRSB_r_A1_post, "ldrsb", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x001000d0, 0x0f7000f0}, + {aarch32_op_LDRSB_r_A1_pre, "ldrsb", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x013000d0, 0x0f7000f0}, + {aarch32_op_LDRSBT_A1, "ldrsbt", {OPR_reg_Rt, OPR_reg_Rn}, 0x007000d0, 0x0f7000f0}, + {aarch32_op_LDRSBT_A2, "ldrsbt", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x003000d0, 0x0f7000f0}, + {aarch32_op_LDRSH_i_A1_off, "ldrsh", {OPR_reg_Rt, OPR_reg_Rn}, 0x015000f0, 0x0f7000f0}, + {aarch32_op_LDRSH_i_A1_post, "ldrsh", {OPR_reg_Rt, OPR_reg_Rn}, 0x005000f0, 0x0f7000f0}, + {aarch32_op_LDRSH_i_A1_pre, "ldrsh", {OPR_reg_Rt, OPR_reg_Rn}, 0x017000f0, 0x0f7000f0}, + {aarch32_op_LDRSH_l_A1, "ldrsh", {OPR_reg_Rt, OPR_imm_label}, 0x005f00f0, 0x0e5f00f0}, + {aarch32_op_LDRSH_r_A1_off, "ldrsh", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x011000f0, 0x0f7000f0}, + {aarch32_op_LDRSH_r_A1_post, "ldrsh", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x001000f0, 0x0f7000f0}, + {aarch32_op_LDRSH_r_A1_pre, "ldrsh", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x013000f0, 0x0f7000f0}, + {aarch32_op_LDRSHT_A1, "ldrsht", {OPR_reg_Rt, OPR_reg_Rn}, 0x007000f0, 0x0f7000f0}, + {aarch32_op_LDRSHT_A2, "ldrsht", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x003000f0, 0x0f7000f0}, + {aarch32_op_LDRT_A1, "ldrt", {OPR_reg_Rt, OPR_reg_Rn}, 0x04300000, 0x0f700000}, + {aarch32_op_LDRT_A2, "ldrt", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x06300000, 0x0f700010}, + {aarch32_op_LSL_MOV_r_A1, "lsl", {OPR_reg_Rd, OPR_reg_Rm}, 0x01a00000, 0x0ff00070}, + {aarch32_op_LSL_MOV_rr_A1, "lsl", {OPR_reg_Rd, OPR_reg_Rm, OPR_reg_Rs}, 0x01a00010, 0x0ff000f0}, + {aarch32_op_LSLS_MOVS_r_A1, "lsls", {OPR_reg_Rd, OPR_reg_Rm}, 0x01b00000, 0x0ff00070}, + {aarch32_op_LSLS_MOVS_rr_A1, "lsls", {OPR_reg_Rd, OPR_reg_Rm, OPR_reg_Rs}, 0x01b00010, 0x0ff000f0}, + {aarch32_op_LSR_MOV_r_A1, "lsr", {OPR_reg_Rd, OPR_reg_Rm}, 0x01a00020, 0x0ff00070}, + {aarch32_op_LSR_MOV_rr_A1, "lsr", {OPR_reg_Rd, OPR_reg_Rm, OPR_reg_Rs}, 0x01a00030, 0x0ff000f0}, + {aarch32_op_LSRS_MOVS_r_A1, "lsrs", {OPR_reg_Rd, OPR_reg_Rm}, 0x01b00020, 0x0ff00070}, + {aarch32_op_LSRS_MOVS_rr_A1, "lsrs", {OPR_reg_Rd, OPR_reg_Rm, OPR_reg_Rs}, 0x01b00030, 0x0ff000f0}, + {aarch32_op_MCR_A1, "mcr", {OPR_reg_Rt}, 0x0e000e10, 0x0f100e10}, + {aarch32_op_MCRR_A1, "mcrr", {OPR_reg_Rt, OPR_reg_Rt2_2}, 0x0c400e00, 0x0ff00e00}, + {aarch32_op_MLAS_A1, "mlas", {OPR_reg_Rd_2, OPR_reg_Rn, OPR_reg_Rm_2, OPR_reg_Ra}, 0x00300090, 0x0ff000f0}, + {aarch32_op_MLA_A1, "mla", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Ra}, 0x00200090, 0x0ff000f0}, + {aarch32_op_MLS_A1, "mls", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Ra}, 0x00600090, 0x0ff000f0}, + {aarch32_op_MOV_i_A1, "mov", {OPR_reg_Rd, OPR_imm_const}, 0x03a00000, 0x0ff00000}, + {aarch32_op_MOVS_i_A1, "movs", {OPR_reg_Rd, OPR_imm_const}, 0x03b00000, 0x0ff00000}, + {aarch32_op_MOV_i_A2, "movw", {OPR_reg_Rd}, 0x03000000, 0x0ff00000}, + {aarch32_op_MOV_r_A1_RRX, "mov", {OPR_reg_Rd, OPR_reg_Rm}, 0x01a00060, 0x0ff00ff0}, + {aarch32_op_MOV_r_A1, "mov", {OPR_reg_Rd, OPR_reg_Rm}, 0x01a00000, 0x0ff00010}, + {aarch32_op_MOVS_r_A1_RRX, "movs", {OPR_reg_Rd, OPR_reg_Rm}, 0x01b00060, 0x0ff00ff0}, + {aarch32_op_MOVS_r_A1, "movs", {OPR_reg_Rd, OPR_reg_Rm}, 0x01b00000, 0x0ff00010}, + {aarch32_op_MOVS_rr_A1, "movs", {OPR_reg_Rd, OPR_reg_Rm, OPR_reg_Rs}, 0x01b00010, 0x0ff00090}, + {aarch32_op_MOV_rr_A1, "mov", {OPR_reg_Rd, OPR_reg_Rm, OPR_reg_Rs}, 0x01a00010, 0x0ff00090}, + {aarch32_op_MOVT_A1, "movt", {OPR_reg_Rd}, 0x03400000, 0x0ff00000}, + {aarch32_op_MRC_A1, "mrc", {OPR_reg_Rt}, 0x0e100e10, 0x0f100e10}, + {aarch32_op_MRRC_A1, "mrrc", {OPR_reg_Rt, OPR_reg_Rt2}, 0x0c500e00, 0x0ff00e00}, + {aarch32_op_MRS_A1_AS, "mrs", {OPR_reg_Rd}, 0x01000000, 0x0fb002f0}, + {aarch32_op_MRS_br_A1_AS, "mrs", {OPR_reg_Rd}, 0x01000200, 0x0fb002f0}, + {aarch32_op_MSR_br_A1_AS, "msr", {OPR_reg_Rn}, 0x01200200, 0x0fb002f0}, + {aarch32_op_MSR_i_A1_AS, "msr", {}, 0x03000000, 0x0f800000}, + {aarch32_op_MSR_r_A1_AS, "msr", {OPR_reg_Rn}, 0x01200000, 0x0fb002f0}, + {aarch32_op_MULS_A1, "muls", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00100090, 0x0ff000f0}, + {aarch32_op_MUL_A1, "mul", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00000090, 0x0ff000f0}, + {aarch32_op_MVN_i_A1, "mvn", {OPR_reg_Rd, OPR_imm_const}, 0x03e00000, 0x0ff00000}, + {aarch32_op_MVNS_i_A1, "mvns", {OPR_reg_Rd, OPR_imm_const}, 0x03f00000, 0x0ff00000}, + {aarch32_op_MVN_r_A1_RRX, "mvn", {OPR_reg_Rd, OPR_reg_Rm}, 0x01e00060, 0x0ff00ff0}, + {aarch32_op_MVN_r_A1, "mvn", {OPR_reg_Rd, OPR_reg_Rm}, 0x01e00000, 0x0ff00010}, + {aarch32_op_MVNS_r_A1_RRX, "mvns", {OPR_reg_Rd, OPR_reg_Rm}, 0x01f00060, 0x0ff00ff0}, + {aarch32_op_MVNS_r_A1, "mvns", {OPR_reg_Rd, OPR_reg_Rm}, 0x01f00000, 0x0ff00010}, + {aarch32_op_MVNS_rr_A1, "mvns", {OPR_reg_Rd, OPR_reg_Rm, OPR_reg_Rs}, 0x01f00010, 0x0ff00090}, + {aarch32_op_MVN_rr_A1, "mvn", {OPR_reg_Rd, OPR_reg_Rm, OPR_reg_Rs}, 0x01e00010, 0x0ff00090}, + {aarch32_op_NOP_A1, "nop", {}, 0x03200000, 0x0fff00ff}, + {aarch32_op_ORR_i_A1, "orr", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x03800000, 0x0ff00000}, + {aarch32_op_ORRS_i_A1, "orrs", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x03900000, 0x0ff00000}, + {aarch32_op_ORR_r_A1_RRX, "orr", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x01800060, 0x0ff00ff0}, + {aarch32_op_ORR_r_A1, "orr", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x01800000, 0x0ff00010}, + {aarch32_op_ORRS_r_A1_RRX, "orrs", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x01900060, 0x0ff00ff0}, + {aarch32_op_ORRS_r_A1, "orrs", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x01900000, 0x0ff00010}, + {aarch32_op_ORRS_rr_A1, "orrs", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x01900010, 0x0ff00090}, + {aarch32_op_ORR_rr_A1, "orr", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x01800010, 0x0ff00090}, + {aarch32_op_PKHBT_A1, "pkhbt", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06800010, 0x0ff00070}, + {aarch32_op_PKHTB_A1, "pkhtb", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06800050, 0x0ff00070}, + {aarch32_op_PLD_i_A1, "pld", {OPR_reg_Rn}, 0xf5500000, 0xff700000}, + {aarch32_op_PLDW_i_A1, "pldw", {OPR_reg_Rn}, 0xf5100000, 0xff700000}, + {aarch32_op_PLD_l_A1, "pld", {OPR_imm_label}, 0xf51f0000, 0xff3f0000}, + {aarch32_op_PLD_r_A1, "pld", {OPR_reg_Rn, OPR_reg_Rm}, 0xf7500000, 0xff700010}, + {aarch32_op_PLD_r_A1_RRX, "pld", {OPR_reg_Rn, OPR_reg_Rm}, 0xf7500060, 0xff700ff0}, + {aarch32_op_PLDW_r_A1, "pldw", {OPR_reg_Rn, OPR_reg_Rm}, 0xf7100000, 0xff700010}, + {aarch32_op_PLDW_r_A1_RRX, "pldw", {OPR_reg_Rn, OPR_reg_Rm}, 0xf7100060, 0xff700ff0}, + {aarch32_op_PLI_i_A1, "pli", {OPR_reg_Rn}, 0xf4500000, 0xff700000}, + {aarch32_op_PLI_r_A1_RRX, "pli", {OPR_reg_Rn, OPR_reg_Rm}, 0xf6500060, 0xff700ff0}, + {aarch32_op_PLI_r_A1, "pli", {OPR_reg_Rn, OPR_reg_Rm}, 0xf6500000, 0xff700010}, + {aarch32_op_POP_LDM_A1, "pop", {OPR_reglist}, 0x08bd0000, 0x0fff0000}, + {aarch32_op_POP_LDR_i_A1_post, "pop", {OPR_reg_Rn}, 0x049d0004, 0x0fff0fff}, + {aarch32_op_PUSH_STMDB_A1, "push", {OPR_reglist_3}, 0x092d0000, 0x0fff0000}, + {aarch32_op_PUSH_STR_i_A1_pre, "push", {OPR_reg_Rn}, 0x052d0004, 0x0fff0fff}, + {aarch32_op_QADD_A1, "qadd", {OPR_reg_Rd, OPR_reg_Rm, OPR_reg_Rn}, 0x01000050, 0x0ff000f0}, + {aarch32_op_QADD16_A1, "qadd16", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06200010, 0x0ff000f0}, + {aarch32_op_QADD8_A1, "qadd8", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06200090, 0x0ff000f0}, + {aarch32_op_QASX_A1, "qasx", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06200030, 0x0ff000f0}, + {aarch32_op_QDADD_A1, "qdadd", {OPR_reg_Rd, OPR_reg_Rm, OPR_reg_Rn}, 0x01400050, 0x0ff000f0}, + {aarch32_op_QDSUB_A1, "qdsub", {OPR_reg_Rd, OPR_reg_Rm, OPR_reg_Rn}, 0x01600050, 0x0ff000f0}, + {aarch32_op_QSAX_A1, "qsax", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06200050, 0x0ff000f0}, + {aarch32_op_QSUB_A1, "qsub", {OPR_reg_Rd, OPR_reg_Rm, OPR_reg_Rn}, 0x01200050, 0x0ff000f0}, + {aarch32_op_QSUB16_A1, "qsub16", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06200070, 0x0ff000f0}, + {aarch32_op_QSUB8_A1, "qsub8", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x062000f0, 0x0ff000f0}, + {aarch32_op_RBIT_A1, "rbit", {OPR_reg_Rd, OPR_reg_Rm}, 0x06f00030, 0x0ff000f0}, + {aarch32_op_REV_A1, "rev", {OPR_reg_Rd, OPR_reg_Rm}, 0x06b00030, 0x0ff000f0}, + {aarch32_op_REV16_A1, "rev16", {OPR_reg_Rd, OPR_reg_Rm}, 0x06b000b0, 0x0ff000f0}, + {aarch32_op_REVSH_A1, "revsh", {OPR_reg_Rd, OPR_reg_Rm}, 0x06f000b0, 0x0ff000f0}, + {aarch32_op_RFEDA_A1_AS, "rfeda", {OPR_reg_Rn}, 0xf8100000, 0xffd00000}, + {aarch32_op_RFEDB_A1_AS, "rfedb", {OPR_reg_Rn}, 0xf9100000, 0xffd00000}, + {aarch32_op_RFEIA_A1_AS, "rfe{ia}", {OPR_reg_Rn}, 0xf8900000, 0xffd00000}, + {aarch32_op_RFEIB_A1_AS, "rfeib", {OPR_reg_Rn}, 0xf9900000, 0xffd00000}, + {aarch32_op_ROR_MOV_r_A1, "ror", {OPR_reg_Rd, OPR_reg_Rm}, 0x01a00060, 0x0ff00070}, + {aarch32_op_ROR_MOV_rr_A1, "ror", {OPR_reg_Rd, OPR_reg_Rm, OPR_reg_Rs}, 0x01a00070, 0x0ff000f0}, + {aarch32_op_RORS_MOVS_r_A1, "rors", {OPR_reg_Rd, OPR_reg_Rm}, 0x01b00060, 0x0ff00070}, + {aarch32_op_RORS_MOVS_rr_A1, "rors", {OPR_reg_Rd, OPR_reg_Rm, OPR_reg_Rs}, 0x01b00070, 0x0ff000f0}, + {aarch32_op_RRX_MOV_r_A1_RRX, "rrx", {OPR_reg_Rd, OPR_reg_Rm}, 0x01a00060, 0x0ff00ff0}, + {aarch32_op_RRXS_MOVS_r_A1_RRX, "rrxs", {OPR_reg_Rd, OPR_reg_Rm}, 0x01b00060, 0x0ff00ff0}, + {aarch32_op_RSB_i_A1, "rsb", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x02600000, 0x0ff00000}, + {aarch32_op_RSBS_i_A1, "rsbs", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x02700000, 0x0ff00000}, + {aarch32_op_RSB_r_A1_RRX, "rsb", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00600060, 0x0ff00ff0}, + {aarch32_op_RSB_r_A1, "rsb", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00600000, 0x0ff00010}, + {aarch32_op_RSBS_r_A1_RRX, "rsbs", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00700060, 0x0ff00ff0}, + {aarch32_op_RSBS_r_A1, "rsbs", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00700000, 0x0ff00010}, + {aarch32_op_RSBS_rr_A1, "rsbs", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x00700010, 0x0ff00090}, + {aarch32_op_RSB_rr_A1, "rsb", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x00600010, 0x0ff00090}, + {aarch32_op_RSC_i_A1, "rsc", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x02e00000, 0x0ff00000}, + {aarch32_op_RSCS_i_A1, "rscs", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x02f00000, 0x0ff00000}, + {aarch32_op_RSC_r_A1_RRX, "rsc", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00e00060, 0x0ff00ff0}, + {aarch32_op_RSC_r_A1, "rsc", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00e00000, 0x0ff00010}, + {aarch32_op_RSCS_r_A1_RRX, "rscs", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00f00060, 0x0ff00ff0}, + {aarch32_op_RSCS_r_A1, "rscs", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00f00000, 0x0ff00010}, + {aarch32_op_RSCS_rr_A1, "rscs", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x00f00010, 0x0ff00090}, + {aarch32_op_RSC_rr_A1, "rsc", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x00e00010, 0x0ff00090}, + {aarch32_op_SADD16_A1, "sadd16", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06100010, 0x0ff000f0}, + {aarch32_op_SADD8_A1, "sadd8", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06100090, 0x0ff000f0}, + {aarch32_op_SASX_A1, "sasx", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06100030, 0x0ff000f0}, + {aarch32_op_SBC_i_A1, "sbc", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x02c00000, 0x0ff00000}, + {aarch32_op_SBCS_i_A1, "sbcs", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x02d00000, 0x0ff00000}, + {aarch32_op_SBC_r_A1_RRX, "sbc", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00c00060, 0x0ff00ff0}, + {aarch32_op_SBC_r_A1, "sbc", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00c00000, 0x0ff00010}, + {aarch32_op_SBCS_r_A1_RRX, "sbcs", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00d00060, 0x0ff00ff0}, + {aarch32_op_SBCS_r_A1, "sbcs", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00d00000, 0x0ff00010}, + {aarch32_op_SBCS_rr_A1, "sbcs", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x00d00010, 0x0ff00090}, + {aarch32_op_SBC_rr_A1, "sbc", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x00c00010, 0x0ff00090}, + {aarch32_op_SBFX_A1, "sbfx", {OPR_reg_Rd, OPR_reg_Rn}, 0x07a00050, 0x0fe00070}, + {aarch32_op_SDIV_A1, "sdiv", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x07100010, 0x0ff000f0}, + {aarch32_op_SEL_A1, "sel", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x068000b0, 0x0ff000f0}, + {aarch32_op_SETEND_A1, "setend", {}, 0xf1010000, 0xfff100f0}, + {aarch32_op_SETPAN_A1, "setpan", {}, 0xf1100000, 0xfff000f0}, + {aarch32_op_SEV_A1, "sev", {}, 0x03200004, 0x0fff00ff}, + {aarch32_op_SEVL_A1, "sevl", {}, 0x03200005, 0x0fff00ff}, + {aarch32_op_SHA1C_A1, "sha1c", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000c00, 0xffb00f10}, + {aarch32_op_SHA1H_A1, "sha1h", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b102c0, 0xffb30fd0}, + {aarch32_op_SHA1M_A1, "sha1m", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2200c00, 0xffb00f10}, + {aarch32_op_SHA1P_A1, "sha1p", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2100c00, 0xffb00f10}, + {aarch32_op_SHA1SU0_A1, "sha1su0", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2300c00, 0xffb00f10}, + {aarch32_op_SHA1SU1_A1, "sha1su1", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b20380, 0xffb30fd0}, + {aarch32_op_SHA256H_A1, "sha256h", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3000c00, 0xffb00f10}, + {aarch32_op_SHA256H2_A1, "sha256h2", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3100c00, 0xffb00f10}, + {aarch32_op_SHA256SU0_A1, "sha256su0", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b203c0, 0xffb30fd0}, + {aarch32_op_SHA256SU1_A1, "sha256su1", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3200c00, 0xffb00f10}, + {aarch32_op_SHADD16_A1, "shadd16", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06300010, 0x0ff000f0}, + {aarch32_op_SHADD8_A1, "shadd8", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06300090, 0x0ff000f0}, + {aarch32_op_SHASX_A1, "shasx", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06300030, 0x0ff000f0}, + {aarch32_op_SHSAX_A1, "shsax", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06300050, 0x0ff000f0}, + {aarch32_op_SHSUB16_A1, "shsub16", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06300070, 0x0ff000f0}, + {aarch32_op_SHSUB8_A1, "shsub8", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x063000f0, 0x0ff000f0}, + {aarch32_op_SMC_A1_AS, "smc", {}, 0x01600070, 0x0ff000f0}, + {aarch32_op_SMLABB_A1, "smlabb", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Ra}, 0x01000080, 0x0ff000f0}, + {aarch32_op_SMLABT_A1, "smlabt", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Ra}, 0x010000c0, 0x0ff000f0}, + {aarch32_op_SMLATB_A1, "smlatb", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Ra}, 0x010000a0, 0x0ff000f0}, + {aarch32_op_SMLATT_A1, "smlatt", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Ra}, 0x010000e0, 0x0ff000f0}, + {aarch32_op_SMLAD_A1, "smlad", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Ra}, 0x07000010, 0x0ff000f0}, + {aarch32_op_SMLADX_A1, "smladx", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Ra}, 0x07000030, 0x0ff000f0}, + {aarch32_op_SMLALS_A1, "smlals", {OPR_reg_RdLo, OPR_reg_RdHi, OPR_reg_Rn, OPR_reg_Rm}, 0x00f00090, 0x0ff000f0}, + {aarch32_op_SMLAL_A1, "smlal", {OPR_reg_RdLo, OPR_reg_RdHi, OPR_reg_Rn, OPR_reg_Rm}, 0x00e00090, 0x0ff000f0}, + {aarch32_op_SMLALBB_A1, "smlalbb", {OPR_reg_RdLo, OPR_reg_RdHi, OPR_reg_Rn, OPR_reg_Rm}, 0x01400080, 0x0ff000f0}, + {aarch32_op_SMLALBT_A1, "smlalbt", {OPR_reg_RdLo, OPR_reg_RdHi, OPR_reg_Rn, OPR_reg_Rm}, 0x014000c0, 0x0ff000f0}, + {aarch32_op_SMLALTB_A1, "smlaltb", {OPR_reg_RdLo, OPR_reg_RdHi, OPR_reg_Rn, OPR_reg_Rm}, 0x014000a0, 0x0ff000f0}, + {aarch32_op_SMLALTT_A1, "smlaltt", {OPR_reg_RdLo, OPR_reg_RdHi, OPR_reg_Rn, OPR_reg_Rm}, 0x014000e0, 0x0ff000f0}, + {aarch32_op_SMLALD_A1, "smlald", {OPR_reg_RdLo, OPR_reg_RdHi, OPR_reg_Rn, OPR_reg_Rm}, 0x07400010, 0x0ff000f0}, + {aarch32_op_SMLALDX_A1, "smlaldx", {OPR_reg_RdLo, OPR_reg_RdHi, OPR_reg_Rn, OPR_reg_Rm}, 0x07400030, 0x0ff000f0}, + {aarch32_op_SMLAWB_A1, "smlawb", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Ra}, 0x01200080, 0x0ff000f0}, + {aarch32_op_SMLAWT_A1, "smlawt", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Ra}, 0x012000c0, 0x0ff000f0}, + {aarch32_op_SMLSD_A1, "smlsd", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Ra}, 0x07000050, 0x0ff000f0}, + {aarch32_op_SMLSDX_A1, "smlsdx", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Ra}, 0x07000070, 0x0ff000f0}, + {aarch32_op_SMLSLD_A1, "smlsld", {OPR_reg_RdLo, OPR_reg_RdHi, OPR_reg_Rn, OPR_reg_Rm}, 0x07400050, 0x0ff000f0}, + {aarch32_op_SMLSLDX_A1, "smlsldx", {OPR_reg_RdLo, OPR_reg_RdHi, OPR_reg_Rn, OPR_reg_Rm}, 0x07400070, 0x0ff000f0}, + {aarch32_op_SMMLA_A1, "smmla", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Ra}, 0x07500010, 0x0ff000f0}, + {aarch32_op_SMMLAR_A1, "smmlar", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Ra}, 0x07500030, 0x0ff000f0}, + {aarch32_op_SMMLS_A1, "smmls", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Ra}, 0x075000d0, 0x0ff000f0}, + {aarch32_op_SMMLSR_A1, "smmlsr", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Ra}, 0x075000f0, 0x0ff000f0}, + {aarch32_op_SMMUL_A1, "smmul", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x0750f010, 0x0ff0f0f0}, + {aarch32_op_SMMULR_A1, "smmulr", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x0750f030, 0x0ff0f0f0}, + {aarch32_op_SMUAD_A1, "smuad", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x0700f010, 0x0ff0f0f0}, + {aarch32_op_SMUADX_A1, "smuadx", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x0700f030, 0x0ff0f0f0}, + {aarch32_op_SMULBB_A1, "smulbb", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x01600080, 0x0ff000f0}, + {aarch32_op_SMULBT_A1, "smulbt", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x016000c0, 0x0ff000f0}, + {aarch32_op_SMULTB_A1, "smultb", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x016000a0, 0x0ff000f0}, + {aarch32_op_SMULTT_A1, "smultt", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x016000e0, 0x0ff000f0}, + {aarch32_op_SMULLS_A1, "smulls", {OPR_reg_RdLo, OPR_reg_RdHi, OPR_reg_Rn, OPR_reg_Rm}, 0x00d00090, 0x0ff000f0}, + {aarch32_op_SMULL_A1, "smull", {OPR_reg_RdLo, OPR_reg_RdHi, OPR_reg_Rn, OPR_reg_Rm}, 0x00c00090, 0x0ff000f0}, + {aarch32_op_SMULWB_A1, "smulwb", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x012000a0, 0x0ff000f0}, + {aarch32_op_SMULWT_A1, "smulwt", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x012000e0, 0x0ff000f0}, + {aarch32_op_SMUSD_A1, "smusd", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x0700f050, 0x0ff0f0f0}, + {aarch32_op_SMUSDX_A1, "smusdx", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x0700f070, 0x0ff0f0f0}, + {aarch32_op_SRSDA_A1_AS, "srsda", {}, 0xf8400000, 0xffd00000}, + {aarch32_op_SRSDB_A1_AS, "srsdb", {}, 0xf9400000, 0xffd00000}, + {aarch32_op_SRSIA_A1_AS, "srs{ia}", {}, 0xf8c00000, 0xffd00000}, + {aarch32_op_SRSIB_A1_AS, "srsib", {}, 0xf9c00000, 0xffd00000}, + {aarch32_op_SSAT_A1_ASR, "ssat", {OPR_reg_Rd, OPR_reg_Rn}, 0x06a00050, 0x0fe00070}, + {aarch32_op_SSAT_A1_LSL, "ssat", {OPR_reg_Rd, OPR_reg_Rn}, 0x06a00010, 0x0fe00070}, + {aarch32_op_SSAT16_A1, "ssat16", {OPR_reg_Rd, OPR_reg_Rn}, 0x06a00030, 0x0ff000f0}, + {aarch32_op_SSAX_A1, "ssax", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06100050, 0x0ff000f0}, + {aarch32_op_SSUB16_A1, "ssub16", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06100070, 0x0ff000f0}, + {aarch32_op_SSUB8_A1, "ssub8", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x061000f0, 0x0ff000f0}, + {aarch32_op_STC_A1_off, "stc", {OPR_reg_Rn}, 0x0d005e00, 0x0f70ff00}, + {aarch32_op_STC_A1_post, "stc", {OPR_reg_Rn}, 0x0c205e00, 0x0f70ff00}, + {aarch32_op_STC_A1_pre, "stc", {OPR_reg_Rn}, 0x0d205e00, 0x0f70ff00}, + {aarch32_op_STC_A1_unind, "stc", {OPR_reg_Rn}, 0x0c805e00, 0x0ff0ff00}, + {aarch32_op_STL_A1, "stl", {OPR_reg_Rt_2, OPR_reg_Rn}, 0x01800090, 0x0ff003f0}, + {aarch32_op_STLB_A1, "stlb", {OPR_reg_Rt, OPR_reg_Rn}, 0x01c00090, 0x0ff003f0}, + {aarch32_op_STLEX_A1, "stlex", {OPR_reg_Rd, OPR_reg_Rt, OPR_reg_Rn}, 0x01800290, 0x0ff003f0}, + {aarch32_op_STLEXB_A1, "stlexb", {OPR_reg_Rd, OPR_reg_Rt, OPR_reg_Rn}, 0x01c00290, 0x0ff003f0}, + {aarch32_op_STLEXD_A1, "stlexd", {OPR_reg_Rd, OPR_reg_Rt, OPR_reg_Rt2_3, OPR_reg_Rn}, 0x01a00290, 0x0ff003f0}, + {aarch32_op_STLEXH_A1, "stlexh", {OPR_reg_Rd, OPR_reg_Rt, OPR_reg_Rn}, 0x01e00290, 0x0ff003f0}, + {aarch32_op_STLH_A1, "stlh", {OPR_reg_Rt, OPR_reg_Rn}, 0x01e00090, 0x0ff003f0}, + {aarch32_op_STM_A1, "stm", {OPR_reg_Rn, OPR_reglist}, 0x08800000, 0x0fd00000}, + {aarch32_op_STM_u_A1_AS, "stm", {OPR_reg_Rn, OPR_reglist}, 0x08400000, 0x0e500000}, + {aarch32_op_STMDA_A1, "stm", {OPR_reg_Rn, OPR_reglist}, 0x08000000, 0x0fd00000}, + {aarch32_op_STMDB_A1, "stm", {OPR_reg_Rn, OPR_reglist}, 0x09000000, 0x0fd00000}, + {aarch32_op_STMIB_A1, "stm", {OPR_reg_Rn, OPR_reglist}, 0x09800000, 0x0fd00000}, + {aarch32_op_STR_i_A1_off, "str", {OPR_reg_Rt, OPR_reg_Rn}, 0x05000000, 0x0f700000}, + {aarch32_op_STR_i_A1_post, "str", {OPR_reg_Rt, OPR_reg_Rn}, 0x04000000, 0x0f700000}, + {aarch32_op_STR_i_A1_pre, "str", {OPR_reg_Rt, OPR_reg_Rn}, 0x05200000, 0x0f700000}, + {aarch32_op_STR_r_A1_off, "str", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x07000000, 0x0f700010}, + {aarch32_op_STR_r_A1_post, "str", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x06000000, 0x0f700010}, + {aarch32_op_STR_r_A1_pre, "str", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x07200000, 0x0f700010}, + {aarch32_op_STRB_i_A1_off, "strb", {OPR_reg_Rt, OPR_reg_Rn}, 0x05400000, 0x0f700000}, + {aarch32_op_STRB_i_A1_post, "strb", {OPR_reg_Rt, OPR_reg_Rn}, 0x04400000, 0x0f700000}, + {aarch32_op_STRB_i_A1_pre, "strb", {OPR_reg_Rt, OPR_reg_Rn}, 0x05600000, 0x0f700000}, + {aarch32_op_STRB_r_A1_off, "strb", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x07400000, 0x0f700010}, + {aarch32_op_STRB_r_A1_post, "strb", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x06400000, 0x0f700010}, + {aarch32_op_STRB_r_A1_pre, "strb", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x07600000, 0x0f700010}, + {aarch32_op_STRBT_A1, "strbt", {OPR_reg_Rt, OPR_reg_Rn}, 0x04600000, 0x0f700000}, + {aarch32_op_STRBT_A2, "strbt", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x06600000, 0x0f700010}, + {aarch32_op_STRD_i_A1_off, "strd", {OPR_reg_Rt, OPR_reg_Rt2, OPR_reg_Rn}, 0x014000f0, 0x0f7000f0}, + {aarch32_op_STRD_i_A1_post, "strd", {OPR_reg_Rt, OPR_reg_Rt2, OPR_reg_Rn}, 0x004000f0, 0x0f7000f0}, + {aarch32_op_STRD_i_A1_pre, "strd", {OPR_reg_Rt, OPR_reg_Rt2, OPR_reg_Rn}, 0x016000f0, 0x0f7000f0}, + {aarch32_op_STRD_r_A1_off, "strd", {OPR_reg_Rt, OPR_reg_Rt2, OPR_reg_Rn, OPR_reg_Rm}, 0x010000f0, 0x0f7000f0}, + {aarch32_op_STRD_r_A1_post, "strd", {OPR_reg_Rt, OPR_reg_Rt2, OPR_reg_Rn, OPR_reg_Rm}, 0x000000f0, 0x0f7000f0}, + {aarch32_op_STRD_r_A1_pre, "strd", {OPR_reg_Rt, OPR_reg_Rt2, OPR_reg_Rn, OPR_reg_Rm}, 0x012000f0, 0x0f7000f0}, + {aarch32_op_STREX_A1, "strex", {OPR_reg_Rd, OPR_reg_Rt, OPR_reg_Rn}, 0x01800390, 0x0ff003f0}, + {aarch32_op_STREXB_A1, "strexb", {OPR_reg_Rd, OPR_reg_Rt, OPR_reg_Rn}, 0x01c00390, 0x0ff003f0}, + {aarch32_op_STREXD_A1, "strexd", {OPR_reg_Rd, OPR_reg_Rt, OPR_reg_Rt2, OPR_reg_Rn}, 0x01a00390, 0x0ff003f0}, + {aarch32_op_STREXH_A1, "strexh", {OPR_reg_Rd, OPR_reg_Rt, OPR_reg_Rn}, 0x01e00390, 0x0ff003f0}, + {aarch32_op_STRH_i_A1_off, "strh", {OPR_reg_Rt, OPR_reg_Rn}, 0x014000b0, 0x0f7000f0}, + {aarch32_op_STRH_i_A1_post, "strh", {OPR_reg_Rt, OPR_reg_Rn}, 0x004000b0, 0x0f7000f0}, + {aarch32_op_STRH_i_A1_pre, "strh", {OPR_reg_Rt, OPR_reg_Rn}, 0x016000b0, 0x0f7000f0}, + {aarch32_op_STRH_r_A1_off, "strh", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x010000b0, 0x0f7000f0}, + {aarch32_op_STRH_r_A1_post, "strh", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x000000b0, 0x0f7000f0}, + {aarch32_op_STRH_r_A1_pre, "strh", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x012000b0, 0x0f7000f0}, + {aarch32_op_STRHT_A1, "strht", {OPR_reg_Rt, OPR_reg_Rn}, 0x006000b0, 0x0f7000f0}, + {aarch32_op_STRHT_A2, "strht", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x002000b0, 0x0f7000f0}, + {aarch32_op_STRT_A1, "strt", {OPR_reg_Rt, OPR_reg_Rn}, 0x04200000, 0x0f700000}, + {aarch32_op_STRT_A2, "strt", {OPR_reg_Rt, OPR_reg_Rn, OPR_reg_Rm}, 0x06200000, 0x0f700010}, + {aarch32_op_SUB_ADR_A2, "sub", {OPR_reg_Rd, OPR_imm_const}, 0x024f0000, 0x0fff0000}, + {aarch32_op_SUB_i_A1, "sub", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x02400000, 0x0ff00000}, + {aarch32_op_SUBS_i_A1, "subs", {OPR_reg_Rd, OPR_reg_Rn, OPR_imm_const}, 0x02500000, 0x0ff00000}, + {aarch32_op_SUB_r_A1_RRX, "sub", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00400060, 0x0ff00ff0}, + {aarch32_op_SUB_r_A1, "sub", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00400000, 0x0ff00010}, + {aarch32_op_SUBS_r_A1_RRX, "subs", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00500060, 0x0ff00ff0}, + {aarch32_op_SUBS_r_A1, "subs", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x00500000, 0x0ff00010}, + {aarch32_op_SUBS_rr_A1, "subs", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x00500010, 0x0ff00090}, + {aarch32_op_SUB_rr_A1, "sub", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x00400010, 0x0ff00090}, + {aarch32_op_SUB_SP_i_A1, "sub", {OPR_reg_Rd, OPR_imm_const}, 0x024d0000, 0x0fff0000}, + {aarch32_op_SUBS_SP_i_A1, "subs", {OPR_reg_Rd, OPR_imm_const}, 0x025d0000, 0x0fff0000}, + {aarch32_op_SUB_SP_r_A1_RRX, "sub", {OPR_reg_Rd, OPR_reg_Rm}, 0x004d0060, 0x0fff0ff0}, + {aarch32_op_SUB_SP_r_A1, "sub", {OPR_reg_Rd, OPR_reg_Rm}, 0x004d0000, 0x0fff0010}, + {aarch32_op_SUBS_SP_r_A1_RRX, "subs", {OPR_reg_Rd, OPR_reg_Rm}, 0x005d0060, 0x0fff0ff0}, + {aarch32_op_SUBS_SP_r_A1, "subs", {OPR_reg_Rd, OPR_reg_Rm}, 0x005d0000, 0x0fff0010}, + {aarch32_op_SVC_A1, "svc", {}, 0x0f000000, 0x0f000000}, + {aarch32_op_SXTAB_A1, "sxtab", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06a00070, 0x0ff000f0}, + {aarch32_op_SXTAB16_A1, "sxtab16", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06800070, 0x0ff000f0}, + {aarch32_op_SXTAH_A1, "sxtah", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06b00070, 0x0ff000f0}, + {aarch32_op_SXTB_A1, "sxtb", {OPR_reg_Rd, OPR_reg_Rm}, 0x06af0070, 0x0fff00f0}, + {aarch32_op_SXTB16_A1, "sxtb16", {OPR_reg_Rd, OPR_reg_Rm}, 0x068f0070, 0x0fff00f0}, + {aarch32_op_SXTH_A1, "sxth", {OPR_reg_Rd, OPR_reg_Rm}, 0x06bf0070, 0x0fff00f0}, + {aarch32_op_TEQ_i_A1, "teq", {OPR_reg_Rn, OPR_imm_const}, 0x03300000, 0x0ff00000}, + {aarch32_op_TEQ_r_A1_RRX, "teq", {OPR_reg_Rn, OPR_reg_Rm}, 0x01300060, 0x0ff00ff0}, + {aarch32_op_TEQ_r_A1, "teq", {OPR_reg_Rn, OPR_reg_Rm}, 0x01300000, 0x0ff00010}, + {aarch32_op_TEQ_rr_A1, "teq", {OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x01300010, 0x0ff00090}, + {aarch32_op_TST_i_A1, "tst", {OPR_reg_Rn, OPR_imm_const}, 0x03100000, 0x0ff00000}, + {aarch32_op_TST_r_A1_RRX, "tst", {OPR_reg_Rn, OPR_reg_Rm}, 0x01100060, 0x0ff00ff0}, + {aarch32_op_TST_r_A1, "tst", {OPR_reg_Rn, OPR_reg_Rm}, 0x01100000, 0x0ff00010}, + {aarch32_op_TST_rr_A1, "tst", {OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Rs}, 0x01100010, 0x0ff00090}, + {aarch32_op_UADD16_A1, "uadd16", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06500010, 0x0ff000f0}, + {aarch32_op_UADD8_A1, "uadd8", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06500090, 0x0ff000f0}, + {aarch32_op_UASX_A1, "uasx", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06500030, 0x0ff000f0}, + {aarch32_op_UBFX_A1, "ubfx", {OPR_reg_Rd, OPR_reg_Rn}, 0x07e00050, 0x0fe00070}, + {aarch32_op_UDF_A1, "udf", {}, 0xe7f000f0, 0xfff000f0}, + {aarch32_op_UDIV_A1, "udiv", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x07300010, 0x0ff000f0}, + {aarch32_op_UHADD16_A1, "uhadd16", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06700010, 0x0ff000f0}, + {aarch32_op_UHADD8_A1, "uhadd8", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06700090, 0x0ff000f0}, + {aarch32_op_UHASX_A1, "uhasx", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06700030, 0x0ff000f0}, + {aarch32_op_UHSAX_A1, "uhsax", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06700050, 0x0ff000f0}, + {aarch32_op_UHSUB16_A1, "uhsub16", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06700070, 0x0ff000f0}, + {aarch32_op_UHSUB8_A1, "uhsub8", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x067000f0, 0x0ff000f0}, + {aarch32_op_UMAAL_A1, "umaal", {OPR_reg_RdLo, OPR_reg_RdHi, OPR_reg_Rn, OPR_reg_Rm}, 0x00400090, 0x0ff000f0}, + {aarch32_op_UMLALS_A1, "umlals", {OPR_reg_RdLo, OPR_reg_RdHi, OPR_reg_Rn, OPR_reg_Rm}, 0x00b00090, 0x0ff000f0}, + {aarch32_op_UMLAL_A1, "umlal", {OPR_reg_RdLo, OPR_reg_RdHi, OPR_reg_Rn, OPR_reg_Rm}, 0x00a00090, 0x0ff000f0}, + {aarch32_op_UMULLS_A1, "umulls", {OPR_reg_RdLo, OPR_reg_RdHi, OPR_reg_Rn, OPR_reg_Rm}, 0x00900090, 0x0ff000f0}, + {aarch32_op_UMULL_A1, "umull", {OPR_reg_RdLo, OPR_reg_RdHi, OPR_reg_Rn, OPR_reg_Rm}, 0x00800090, 0x0ff000f0}, + {aarch32_op_UQADD16_A1, "uqadd16", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06600010, 0x0ff000f0}, + {aarch32_op_UQADD8_A1, "uqadd8", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06600090, 0x0ff000f0}, + {aarch32_op_UQASX_A1, "uqasx", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06600030, 0x0ff000f0}, + {aarch32_op_UQSAX_A1, "uqsax", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06600050, 0x0ff000f0}, + {aarch32_op_UQSUB16_A1, "uqsub16", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06600070, 0x0ff000f0}, + {aarch32_op_UQSUB8_A1, "uqsub8", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x066000f0, 0x0ff000f0}, + {aarch32_op_USAD8_A1, "usad8", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x0780f010, 0x0ff0f0f0}, + {aarch32_op_USADA8_A1, "usada8", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm, OPR_reg_Ra}, 0x07800010, 0x0ff000f0}, + {aarch32_op_USAT_A1_ASR, "usat", {OPR_reg_Rd, OPR_reg_Rn}, 0x06e00050, 0x0fe00070}, + {aarch32_op_USAT_A1_LSL, "usat", {OPR_reg_Rd, OPR_reg_Rn}, 0x06e00010, 0x0fe00070}, + {aarch32_op_USAT16_A1, "usat16", {OPR_reg_Rd, OPR_reg_Rn}, 0x06e00030, 0x0ff000f0}, + {aarch32_op_USAX_A1, "usax", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06500050, 0x0ff000f0}, + {aarch32_op_USUB16_A1, "usub16", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06500070, 0x0ff000f0}, + {aarch32_op_USUB8_A1, "usub8", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x065000f0, 0x0ff000f0}, + {aarch32_op_UXTAB_A1, "uxtab", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06e00070, 0x0ff000f0}, + {aarch32_op_UXTAB16_A1, "uxtab16", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06c00070, 0x0ff000f0}, + {aarch32_op_UXTAH_A1, "uxtah", {OPR_reg_Rd, OPR_reg_Rn, OPR_reg_Rm}, 0x06f00070, 0x0ff000f0}, + {aarch32_op_UXTB_A1, "uxtb", {OPR_reg_Rd, OPR_reg_Rm}, 0x06ef0070, 0x0fff00f0}, + {aarch32_op_UXTB16_A1, "uxtb16", {OPR_reg_Rd, OPR_reg_Rm}, 0x06cf0070, 0x0fff00f0}, + {aarch32_op_UXTH_A1, "uxth", {OPR_reg_Rd, OPR_reg_Rm}, 0x06ff0070, 0x0fff00f0}, + {aarch32_op_VABA_A1_D, "vaba", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000710, 0xfe800f50}, + {aarch32_op_VABA_A1_Q, "vaba", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000750, 0xfe800f50}, + {aarch32_op_VABAL_A1, "vabal", {OPR_reg_Qd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2800500, 0xfe800f50}, + {aarch32_op_VABD_f_A1_D, "vabd", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3200d00, 0xffa00f50}, + {aarch32_op_VABD_f_A1_Q, "vabd", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3200d40, 0xffa00f50}, + {aarch32_op_VABD_i_A1_D, "vabd", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000700, 0xfe800f50}, + {aarch32_op_VABD_i_A1_Q, "vabd", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000740, 0xfe800f50}, + {aarch32_op_VABDL_i_A1, "vabdl", {OPR_reg_Qd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2800700, 0xfe800f50}, + {aarch32_op_VABS_A1_D, "vabs", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b10300, 0xffb30bd0}, + {aarch32_op_VABS_A1_Q, "vabs", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b10340, 0xffb30bd0}, + {aarch32_op_VABS_A2_H, "vabs", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb009c0, 0x0fbf0fd0}, + {aarch32_op_VABS_A2_S, "vabs", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb00ac0, 0x0fbf0fd0}, + {aarch32_op_VABS_A2_D, "vabs", {OPR_reg_Dd, OPR_reg_Dm}, 0x0eb00bc0, 0x0fbf0fd0}, + {aarch32_op_VACGE_A1_D, "vacge", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3000e10, 0xffa00f50}, + {aarch32_op_VACGE_A1_Q, "vacge", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3000e50, 0xffa00f50}, + {aarch32_op_VACGT_A1_D, "vacgt", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3200e10, 0xffa00f50}, + {aarch32_op_VACGT_A1_Q, "vacgt", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3200e50, 0xffa00f50}, + {aarch32_op_VACLE_VACGE_A1_D, "vacle", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3000e10, 0xffa00f50}, + {aarch32_op_VACLE_VACGE_A1_Q, "vacle", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3000e50, 0xffa00f50}, + {aarch32_op_VACLT_VACGT_A1_D, "vaclt", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3200e10, 0xffa00f50}, + {aarch32_op_VACLT_VACGT_A1_Q, "vaclt", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3200e50, 0xffa00f50}, + {aarch32_op_VADD_f_A1_D, "vadd", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000d00, 0xffa00f50}, + {aarch32_op_VADD_f_A1_Q, "vadd", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000d40, 0xffa00f50}, + {aarch32_op_VADD_f_A2_H, "vadd", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e300900, 0x0fb00f50}, + {aarch32_op_VADD_f_A2_S, "vadd", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e300a00, 0x0fb00f50}, + {aarch32_op_VADD_f_A2_D, "vadd", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0x0e300b00, 0x0fb00f50}, + {aarch32_op_VADD_i_A1_D, "vadd", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000800, 0xff800f50}, + {aarch32_op_VADD_i_A1_Q, "vadd", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000840, 0xff800f50}, + {aarch32_op_VADDHN_A1, "vaddhn", {OPR_reg_Dd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2800400, 0xff800f50}, + {aarch32_op_VADDL_A1, "vaddl", {OPR_reg_Qd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2800000, 0xfe800f50}, + {aarch32_op_VADDW_A1, "vaddw", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Dm}, 0xf2800100, 0xfe800f50}, + {aarch32_op_VAND_r_A1_D, "vand", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000110, 0xffb00f50}, + {aarch32_op_VAND_r_A1_Q, "vand", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000150, 0xffb00f50}, + {aarch32_op_VAND_VBIC_i_A1_D, "vand", {OPR_reg_Dd, OPR_reg_Dd}, 0xf2800130, 0xfeb809f0}, + {aarch32_op_VAND_VBIC_i_A1_Q, "vand", {OPR_reg_Qd, OPR_reg_Qd}, 0xf2800170, 0xfeb809f0}, + {aarch32_op_VAND_VBIC_i_A2_D, "vand", {OPR_reg_Dd, OPR_reg_Dd}, 0xf2800930, 0xfeb80df0}, + {aarch32_op_VAND_VBIC_i_A2_Q, "vand", {OPR_reg_Qd, OPR_reg_Qd}, 0xf2800970, 0xfeb80df0}, + {aarch32_op_VBIC_i_A1_D, "vbic", {OPR_reg_Dd, OPR_reg_Dd}, 0xf2800130, 0xfeb809f0}, + {aarch32_op_VBIC_i_A1_Q, "vbic", {OPR_reg_Qd, OPR_reg_Qd}, 0xf2800170, 0xfeb809f0}, + {aarch32_op_VBIC_i_A2_D, "vbic", {OPR_reg_Dd, OPR_reg_Dd}, 0xf2800930, 0xfeb80df0}, + {aarch32_op_VBIC_i_A2_Q, "vbic", {OPR_reg_Qd, OPR_reg_Qd}, 0xf2800970, 0xfeb80df0}, + {aarch32_op_VBIC_r_A1_D, "vbic", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2100110, 0xffb00f50}, + {aarch32_op_VBIC_r_A1_Q, "vbic", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2100150, 0xffb00f50}, + {aarch32_op_VBIF_A1_D, "vbif", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3300110, 0xffb00f50}, + {aarch32_op_VBIF_A1_Q, "vbif", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3300150, 0xffb00f50}, + {aarch32_op_VBIT_A1_D, "vbit", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3200110, 0xffb00f50}, + {aarch32_op_VBIT_A1_Q, "vbit", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3200150, 0xffb00f50}, + {aarch32_op_VBSL_A1_D, "vbsl", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3100110, 0xffb00f50}, + {aarch32_op_VBSL_A1_Q, "vbsl", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3100150, 0xffb00f50}, + {aarch32_op_VCEQ_i_A1_D, "vceq", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b10100, 0xffb30bd0}, + {aarch32_op_VCEQ_i_A1_Q, "vceq", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b10140, 0xffb30bd0}, + {aarch32_op_VCEQ_r_A1_D, "vceq", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3000810, 0xff800f50}, + {aarch32_op_VCEQ_r_A1_Q, "vceq", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3000850, 0xff800f50}, + {aarch32_op_VCEQ_r_A2_D, "vceq", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000e00, 0xffa00f50}, + {aarch32_op_VCEQ_r_A2_Q, "vceq", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000e40, 0xffa00f50}, + {aarch32_op_VCGE_i_A1_D, "vcge", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b10080, 0xffb30bd0}, + {aarch32_op_VCGE_i_A1_Q, "vcge", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b100c0, 0xffb30bd0}, + {aarch32_op_VCGE_r_A1_D, "vcge", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000310, 0xfe800f50}, + {aarch32_op_VCGE_r_A1_Q, "vcge", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000350, 0xfe800f50}, + {aarch32_op_VCGE_r_A2_D, "vcge", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3000e00, 0xffa00f50}, + {aarch32_op_VCGE_r_A2_Q, "vcge", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3000e40, 0xffa00f50}, + {aarch32_op_VCGT_i_A1_D, "vcgt", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b10000, 0xffb30bd0}, + {aarch32_op_VCGT_i_A1_Q, "vcgt", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b10040, 0xffb30bd0}, + {aarch32_op_VCGT_r_A1_D, "vcgt", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000300, 0xfe800f50}, + {aarch32_op_VCGT_r_A1_Q, "vcgt", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000340, 0xfe800f50}, + {aarch32_op_VCGT_r_A2_D, "vcgt", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3200e00, 0xffa00f50}, + {aarch32_op_VCGT_r_A2_Q, "vcgt", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3200e40, 0xffa00f50}, + {aarch32_op_VCLE_i_A1_D, "vcle", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b10180, 0xffb30bd0}, + {aarch32_op_VCLE_i_A1_Q, "vcle", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b101c0, 0xffb30bd0}, + {aarch32_op_VCLE_VCGE_r_A1_D, "vcle", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000310, 0xfe800f50}, + {aarch32_op_VCLE_VCGE_r_A1_Q, "vcle", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000350, 0xfe800f50}, + {aarch32_op_VCLE_VCGE_r_A2_D, "vcle", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3000e00, 0xffa00f50}, + {aarch32_op_VCLE_VCGE_r_A2_Q, "vcle", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3000e40, 0xffa00f50}, + {aarch32_op_VCLS_A1_D, "vcls", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b00400, 0xffb30fd0}, + {aarch32_op_VCLS_A1_Q, "vcls", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b00440, 0xffb30fd0}, + {aarch32_op_VCLT_i_A1_D, "vclt", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b10200, 0xffb30bd0}, + {aarch32_op_VCLT_i_A1_Q, "vclt", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b10240, 0xffb30bd0}, + {aarch32_op_VCLT_VCGT_r_A1_D, "vclt", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000300, 0xfe800f50}, + {aarch32_op_VCLT_VCGT_r_A1_Q, "vclt", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000340, 0xfe800f50}, + {aarch32_op_VCLT_VCGT_r_A2_D, "vclt", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3200e00, 0xffa00f50}, + {aarch32_op_VCLT_VCGT_r_A2_Q, "vclt", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3200e40, 0xffa00f50}, + {aarch32_op_VCLZ_A1_D, "vclz", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b00480, 0xffb30fd0}, + {aarch32_op_VCLZ_A1_Q, "vclz", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b004c0, 0xffb30fd0}, + {aarch32_op_VCMP_A1_H, "vcmp", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb40940, 0x0fbf0fd0}, + {aarch32_op_VCMP_A1_S, "vcmp", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb40a40, 0x0fbf0fd0}, + {aarch32_op_VCMP_A1_D, "vcmp", {OPR_reg_Dd, OPR_reg_Dm}, 0x0eb40b40, 0x0fbf0fd0}, + {aarch32_op_VCMP_A2_H, "vcmp", {OPR_reg_Sd}, 0x0eb50940, 0x0fbf0fd0}, + {aarch32_op_VCMP_A2_S, "vcmp", {OPR_reg_Sd}, 0x0eb50a40, 0x0fbf0fd0}, + {aarch32_op_VCMP_A2_D, "vcmp", {OPR_reg_Dd}, 0x0eb50b40, 0x0fbf0fd0}, + {aarch32_op_VCMPE_A1_H, "vcmpe", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb409c0, 0x0fbf0fd0}, + {aarch32_op_VCMPE_A1_S, "vcmpe", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb40ac0, 0x0fbf0fd0}, + {aarch32_op_VCMPE_A1_D, "vcmpe", {OPR_reg_Dd, OPR_reg_Dm}, 0x0eb40bc0, 0x0fbf0fd0}, + {aarch32_op_VCMPE_A2_H, "vcmpe", {OPR_reg_Sd}, 0x0eb509c0, 0x0fbf0fd0}, + {aarch32_op_VCMPE_A2_S, "vcmpe", {OPR_reg_Sd}, 0x0eb50ac0, 0x0fbf0fd0}, + {aarch32_op_VCMPE_A2_D, "vcmpe", {OPR_reg_Dd}, 0x0eb50bc0, 0x0fbf0fd0}, + {aarch32_op_VCNT_A1_D, "vcnt", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b00500, 0xffb30fd0}, + {aarch32_op_VCNT_A1_Q, "vcnt", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b00540, 0xffb30fd0}, + {aarch32_op_VCVT_ds_A1, "vcvt", {OPR_reg_Dd, OPR_reg_Sm}, 0x0eb70ac0, 0x0fbf0fd0}, + {aarch32_op_VCVT_sd_A1, "vcvt", {OPR_reg_Sd, OPR_reg_Dm}, 0x0eb70bc0, 0x0fbf0fd0}, + {aarch32_op_VCVT_sh_A1, "vcvt", {OPR_reg_Qd, OPR_reg_Dm}, 0xf3b20700, 0xffb30fd0}, + {aarch32_op_VCVT_hs_A1, "vcvt", {OPR_reg_Dd, OPR_reg_Qm}, 0xf3b20600, 0xffb30fd0}, + {aarch32_op_VCVT_is_A1_D, "vcvt", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b30600, 0xffb30e50}, + {aarch32_op_VCVT_is_A1_Q, "vcvt", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b30640, 0xffb30e50}, + {aarch32_op_VCVT_uiv_A1_H, "vcvt", {OPR_reg_Sd, OPR_reg_Sm}, 0x0ebc09c0, 0x0fbf0fd0}, + {aarch32_op_VCVT_siv_A1_H, "vcvt", {OPR_reg_Sd, OPR_reg_Sm}, 0x0ebd09c0, 0x0fbf0fd0}, + {aarch32_op_VCVT_uiv_A1_S, "vcvt", {OPR_reg_Sd, OPR_reg_Sm}, 0x0ebc0ac0, 0x0fbf0fd0}, + {aarch32_op_VCVT_siv_A1_S, "vcvt", {OPR_reg_Sd, OPR_reg_Sm}, 0x0ebd0ac0, 0x0fbf0fd0}, + {aarch32_op_VCVT_uiv_A1_D, "vcvt", {OPR_reg_Sd, OPR_reg_Dm}, 0x0ebc0bc0, 0x0fbf0fd0}, + {aarch32_op_VCVT_siv_A1_D, "vcvt", {OPR_reg_Sd, OPR_reg_Dm}, 0x0ebd0bc0, 0x0fbf0fd0}, + {aarch32_op_VCVT_vi_A1_H, "vcvt", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb80940, 0x0fbf0f50}, + {aarch32_op_VCVT_vi_A1_S, "vcvt", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb80a40, 0x0fbf0f50}, + {aarch32_op_VCVT_vi_A1_D, "vcvt", {OPR_reg_Dd, OPR_reg_Sm}, 0x0eb80b40, 0x0fbf0f50}, + {aarch32_op_VCVT_xs_A1_D, "vcvt", {OPR_reg_Dd, OPR_reg_Dm}, 0xf2800c10, 0xfe800cd0}, + {aarch32_op_VCVT_xs_A1_Q, "vcvt", {OPR_reg_Qd, OPR_reg_Qm}, 0xf2800c50, 0xfe800cd0}, + {aarch32_op_VCVT_toxv_A1_H, "vcvt", {OPR_reg_Sdm, OPR_reg_Sdm}, 0x0eba0940, 0x0fbe0f50}, + {aarch32_op_VCVT_xv_A1_H, "vcvt", {OPR_reg_Sdm, OPR_reg_Sdm}, 0x0ebe0940, 0x0fbe0f50}, + {aarch32_op_VCVT_toxv_A1_S, "vcvt", {OPR_reg_Sdm, OPR_reg_Sdm}, 0x0eba0a40, 0x0fbe0f50}, + {aarch32_op_VCVT_xv_A1_S, "vcvt", {OPR_reg_Sdm, OPR_reg_Sdm}, 0x0ebe0a40, 0x0fbe0f50}, + {aarch32_op_VCVT_toxv_A1_D, "vcvt", {OPR_reg_Ddm, OPR_reg_Ddm}, 0x0eba0b40, 0x0fbe0f50}, + {aarch32_op_VCVT_xv_A1_D, "vcvt", {OPR_reg_Ddm, OPR_reg_Ddm}, 0x0ebe0b40, 0x0fbe0f50}, + {aarch32_op_VCVTA_asimd_A1_D, "vcvta", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b30000, 0xffb30f50}, + {aarch32_op_VCVTA_asimd_A1_Q, "vcvta", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b30040, 0xffb30f50}, + {aarch32_op_VCVTA_vfp_A1_H, "vcvta", {OPR_reg_Sd, OPR_reg_Sm}, 0xfebc0940, 0xffbf0f50}, + {aarch32_op_VCVTA_vfp_A1_S, "vcvta", {OPR_reg_Sd, OPR_reg_Sm}, 0xfebc0a40, 0xffbf0f50}, + {aarch32_op_VCVTA_vfp_A1_D, "vcvta", {OPR_reg_Sd, OPR_reg_Dm}, 0xfebc0b40, 0xffbf0f50}, + {aarch32_op_VCVTB_A1_SH, "vcvtb", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb20a40, 0x0fbf0fd0}, + {aarch32_op_VCVTB_A1_DH, "vcvtb", {OPR_reg_Dd, OPR_reg_Sm}, 0x0eb20b40, 0x0fbf0fd0}, + {aarch32_op_VCVTB_A1_HS, "vcvtb", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb30a40, 0x0fbf0fd0}, + {aarch32_op_VCVTB_A1_HD, "vcvtb", {OPR_reg_Sd, OPR_reg_Dm}, 0x0eb30b40, 0x0fbf0fd0}, + {aarch32_op_VCVTM_asimd_A1_D, "vcvtm", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b30300, 0xffb30f50}, + {aarch32_op_VCVTM_asimd_A1_Q, "vcvtm", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b30340, 0xffb30f50}, + {aarch32_op_VCVTM_vfp_A1_H, "vcvtm", {OPR_reg_Sd, OPR_reg_Sm}, 0xfebf0940, 0xffbf0f50}, + {aarch32_op_VCVTM_vfp_A1_S, "vcvtm", {OPR_reg_Sd, OPR_reg_Sm}, 0xfebf0a40, 0xffbf0f50}, + {aarch32_op_VCVTM_vfp_A1_D, "vcvtm", {OPR_reg_Sd, OPR_reg_Dm}, 0xfebf0b40, 0xffbf0f50}, + {aarch32_op_VCVTN_asimd_A1_D, "vcvtn", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b30100, 0xffb30f50}, + {aarch32_op_VCVTN_asimd_A1_Q, "vcvtn", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b30140, 0xffb30f50}, + {aarch32_op_VCVTN_vfp_A1_H, "vcvtn", {OPR_reg_Sd, OPR_reg_Sm}, 0xfebd0940, 0xffbf0f50}, + {aarch32_op_VCVTN_vfp_A1_S, "vcvtn", {OPR_reg_Sd, OPR_reg_Sm}, 0xfebd0a40, 0xffbf0f50}, + {aarch32_op_VCVTN_vfp_A1_D, "vcvtn", {OPR_reg_Sd, OPR_reg_Dm}, 0xfebd0b40, 0xffbf0f50}, + {aarch32_op_VCVTP_asimd_A1_D, "vcvtp", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b30200, 0xffb30f50}, + {aarch32_op_VCVTP_asimd_A1_Q, "vcvtp", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b30240, 0xffb30f50}, + {aarch32_op_VCVTP_vfp_A1_H, "vcvtp", {OPR_reg_Sd, OPR_reg_Sm}, 0xfebe0940, 0xffbf0f50}, + {aarch32_op_VCVTP_vfp_A1_S, "vcvtp", {OPR_reg_Sd, OPR_reg_Sm}, 0xfebe0a40, 0xffbf0f50}, + {aarch32_op_VCVTP_vfp_A1_D, "vcvtp", {OPR_reg_Sd, OPR_reg_Dm}, 0xfebe0b40, 0xffbf0f50}, + {aarch32_op_VCVTR_uiv_A1_H, "vcvtr", {OPR_reg_Sd, OPR_reg_Sm}, 0x0ebc0940, 0x0fbf0fd0}, + {aarch32_op_VCVTR_siv_A1_H, "vcvtr", {OPR_reg_Sd, OPR_reg_Sm}, 0x0ebd0940, 0x0fbf0fd0}, + {aarch32_op_VCVTR_uiv_A1_S, "vcvtr", {OPR_reg_Sd, OPR_reg_Sm}, 0x0ebc0a40, 0x0fbf0fd0}, + {aarch32_op_VCVTR_siv_A1_S, "vcvtr", {OPR_reg_Sd, OPR_reg_Sm}, 0x0ebd0a40, 0x0fbf0fd0}, + {aarch32_op_VCVTR_uiv_A1_D, "vcvtr", {OPR_reg_Sd, OPR_reg_Dm}, 0x0ebc0b40, 0x0fbf0fd0}, + {aarch32_op_VCVTR_siv_A1_D, "vcvtr", {OPR_reg_Sd, OPR_reg_Dm}, 0x0ebd0b40, 0x0fbf0fd0}, + {aarch32_op_VCVTT_A1_SH, "vcvtt", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb20ac0, 0x0fbf0fd0}, + {aarch32_op_VCVTT_A1_DH, "vcvtt", {OPR_reg_Dd, OPR_reg_Sm}, 0x0eb20bc0, 0x0fbf0fd0}, + {aarch32_op_VCVTT_A1_HS, "vcvtt", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb30ac0, 0x0fbf0fd0}, + {aarch32_op_VCVTT_A1_HD, "vcvtt", {OPR_reg_Sd, OPR_reg_Dm}, 0x0eb30bc0, 0x0fbf0fd0}, + {aarch32_op_VDIV_A1_H, "vdiv", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e800900, 0x0fb00f50}, + {aarch32_op_VDIV_A1_S, "vdiv", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e800a00, 0x0fb00f50}, + {aarch32_op_VDIV_A1_D, "vdiv", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0x0e800b00, 0x0fb00f50}, + {aarch32_op_VDUP_r_A1, "vdup", {OPR_reg_Qd_2, OPR_reg_Rt}, 0x0e800b10, 0x0f900f50}, + {aarch32_op_VDUP_s_A1_D, "vdup", {OPR_reg_Dd, OPR_reg_Dm_x_}, 0xf3b00c00, 0xffb00fd0}, + {aarch32_op_VDUP_s_A1_Q, "vdup", {OPR_reg_Qd, OPR_reg_Dm_x_}, 0xf3b00c40, 0xffb00fd0}, + {aarch32_op_VEOR_A1_D, "veor", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3000110, 0xffb00f50}, + {aarch32_op_VEOR_A1_Q, "veor", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3000150, 0xffb00f50}, + {aarch32_op_VEXT_A1_D, "vext", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2b00000, 0xffb00050}, + {aarch32_op_VEXT_A1_Q, "vext", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2b00040, 0xffb00050}, + {aarch32_op_VEXT_VEXT_A1_D, "vext", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2b00000, 0xffb00050}, + {aarch32_op_VEXT_VEXT_A1_Q, "vext", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2b00040, 0xffb00050}, + {aarch32_op_VFMA_A1_D, "vfma", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000c10, 0xffa00f50}, + {aarch32_op_VFMA_A1_Q, "vfma", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000c50, 0xffa00f50}, + {aarch32_op_VFMA_A2_H, "vfma", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0ea00900, 0x0fb00f50}, + {aarch32_op_VFMA_A2_S, "vfma", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0ea00a00, 0x0fb00f50}, + {aarch32_op_VFMA_A2_D, "vfma", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0x0ea00b00, 0x0fb00f50}, + {aarch32_op_VFMS_A1_D, "vfms", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2200c10, 0xffa00f50}, + {aarch32_op_VFMS_A1_Q, "vfms", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2200c50, 0xffa00f50}, + {aarch32_op_VFMS_A2_H, "vfms", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0ea00940, 0x0fb00f50}, + {aarch32_op_VFMS_A2_S, "vfms", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0ea00a40, 0x0fb00f50}, + {aarch32_op_VFMS_A2_D, "vfms", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0x0ea00b40, 0x0fb00f50}, + {aarch32_op_VFNMA_A1_H, "vfnma", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e900940, 0x0fb00f50}, + {aarch32_op_VFNMA_A1_S, "vfnma", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e900a40, 0x0fb00f50}, + {aarch32_op_VFNMA_A1_D, "vfnma", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0x0e900b40, 0x0fb00f50}, + {aarch32_op_VFNMS_A1_H, "vfnms", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e900900, 0x0fb00f50}, + {aarch32_op_VFNMS_A1_S, "vfnms", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e900a00, 0x0fb00f50}, + {aarch32_op_VFNMS_A1_D, "vfnms", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0x0e900b00, 0x0fb00f50}, + {aarch32_op_VHADD_A1_D, "vhadd", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000000, 0xfe800f50}, + {aarch32_op_VHADD_A1_Q, "vhadd", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000040, 0xfe800f50}, + {aarch32_op_VHSUB_A1_D, "vhsub", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000200, 0xfe800f50}, + {aarch32_op_VHSUB_A1_Q, "vhsub", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000240, 0xfe800f50}, + {aarch32_op_VINS_A1, "vins", {OPR_reg_Sd, OPR_reg_Sm}, 0xfeb00ac0, 0xffbf0fd0}, + {aarch32_op_VLD1_1_A1_nowb, "vld1", {OPR_reg_Rn}, 0xf4a0000f, 0xffb00f0f}, + {aarch32_op_VLD1_1_A1_posti, "vld1", {OPR_reg_Rn}, 0xf4a0000d, 0xffb00f0f}, + {aarch32_op_VLD1_1_A1_postr, "vld1", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4a00000, 0xffb00f00}, + {aarch32_op_VLD1_1_A2_nowb, "vld1", {OPR_reg_Rn}, 0xf4a0040f, 0xffb00f0f}, + {aarch32_op_VLD1_1_A2_posti, "vld1", {OPR_reg_Rn}, 0xf4a0040d, 0xffb00f0f}, + {aarch32_op_VLD1_1_A2_postr, "vld1", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4a00400, 0xffb00f00}, + {aarch32_op_VLD1_1_A3_nowb, "vld1", {OPR_reg_Rn}, 0xf4a0080f, 0xffb00f0f}, + {aarch32_op_VLD1_1_A3_posti, "vld1", {OPR_reg_Rn}, 0xf4a0080d, 0xffb00f0f}, + {aarch32_op_VLD1_1_A3_postr, "vld1", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4a00800, 0xffb00f00}, + {aarch32_op_VLD1_a_A1_nowb, "vld1", {OPR_reg_Rn}, 0xf4a00c0f, 0xffb00f0f}, + {aarch32_op_VLD1_a_A1_posti, "vld1", {OPR_reg_Rn}, 0xf4a00c0d, 0xffb00f0f}, + {aarch32_op_VLD1_a_A1_postr, "vld1", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4a00c00, 0xffb00f00}, + {aarch32_op_VLD1_m_A1_nowb, "vld1", {OPR_reg_Rn}, 0xf420070f, 0xffb00f0f}, + {aarch32_op_VLD1_m_A1_posti, "vld1", {OPR_reg_Rn}, 0xf420070d, 0xffb00f0f}, + {aarch32_op_VLD1_m_A1_postr, "vld1", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4200700, 0xffb00f00}, + {aarch32_op_VLD1_m_A2_nowb, "vld1", {OPR_reg_Rn}, 0xf4200a0f, 0xffb00f0f}, + {aarch32_op_VLD1_m_A2_posti, "vld1", {OPR_reg_Rn}, 0xf4200a0d, 0xffb00f0f}, + {aarch32_op_VLD1_m_A2_postr, "vld1", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4200a00, 0xffb00f00}, + {aarch32_op_VLD1_m_A3_nowb, "vld1", {OPR_reg_Rn}, 0xf420060f, 0xffb00f0f}, + {aarch32_op_VLD1_m_A3_posti, "vld1", {OPR_reg_Rn}, 0xf420060d, 0xffb00f0f}, + {aarch32_op_VLD1_m_A3_postr, "vld1", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4200600, 0xffb00f00}, + {aarch32_op_VLD1_m_A4_nowb, "vld1", {OPR_reg_Rn}, 0xf420020f, 0xffb00f0f}, + {aarch32_op_VLD1_m_A4_posti, "vld1", {OPR_reg_Rn}, 0xf420020d, 0xffb00f0f}, + {aarch32_op_VLD1_m_A4_postr, "vld1", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4200200, 0xffb00f00}, + {aarch32_op_VLD2_1_A1_nowb, "vld2", {OPR_reg_Rn}, 0xf4a0010f, 0xffb00f0f}, + {aarch32_op_VLD2_1_A1_posti, "vld2", {OPR_reg_Rn}, 0xf4a0010d, 0xffb00f0f}, + {aarch32_op_VLD2_1_A1_postr, "vld2", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4a00100, 0xffb00f00}, + {aarch32_op_VLD2_1_A2_nowb, "vld2", {OPR_reg_Rn}, 0xf4a0050f, 0xffb00f0f}, + {aarch32_op_VLD2_1_A2_posti, "vld2", {OPR_reg_Rn}, 0xf4a0050d, 0xffb00f0f}, + {aarch32_op_VLD2_1_A2_postr, "vld2", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4a00500, 0xffb00f00}, + {aarch32_op_VLD2_1_A3_nowb, "vld2", {OPR_reg_Rn}, 0xf4a0090f, 0xffb00f0f}, + {aarch32_op_VLD2_1_A3_posti, "vld2", {OPR_reg_Rn}, 0xf4a0090d, 0xffb00f0f}, + {aarch32_op_VLD2_1_A3_postr, "vld2", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4a00900, 0xffb00f00}, + {aarch32_op_VLD2_a_A1_nowb, "vld2", {OPR_reg_Rn}, 0xf4a00d0f, 0xffb00f0f}, + {aarch32_op_VLD2_a_A1_posti, "vld2", {OPR_reg_Rn}, 0xf4a00d0d, 0xffb00f0f}, + {aarch32_op_VLD2_a_A1_postr, "vld2", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4a00d00, 0xffb00f00}, + {aarch32_op_VLD2_m_A1_nowb, "vld2", {OPR_reg_Rn}, 0xf420080f, 0xffb00e0f}, + {aarch32_op_VLD2_m_A1_posti, "vld2", {OPR_reg_Rn}, 0xf420080d, 0xffb00e0f}, + {aarch32_op_VLD2_m_A1_postr, "vld2", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4200800, 0xffb00e00}, + {aarch32_op_VLD2_m_A2_nowb, "vld2", {OPR_reg_Rn}, 0xf420030f, 0xffb00f0f}, + {aarch32_op_VLD2_m_A2_posti, "vld2", {OPR_reg_Rn}, 0xf420030d, 0xffb00f0f}, + {aarch32_op_VLD2_m_A2_postr, "vld2", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4200300, 0xffb00f00}, + {aarch32_op_VLD3_1_A1_nowb, "vld3", {OPR_reg_Rn}, 0xf4a0020f, 0xffb00f0f}, + {aarch32_op_VLD3_1_A1_posti, "vld3", {OPR_reg_Rn}, 0xf4a0020d, 0xffb00f0f}, + {aarch32_op_VLD3_1_A1_postr, "vld3", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4a00200, 0xffb00f00}, + {aarch32_op_VLD3_1_A2_nowb, "vld3", {OPR_reg_Rn}, 0xf4a0060f, 0xffb00f0f}, + {aarch32_op_VLD3_1_A2_posti, "vld3", {OPR_reg_Rn}, 0xf4a0060d, 0xffb00f0f}, + {aarch32_op_VLD3_1_A2_postr, "vld3", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4a00600, 0xffb00f00}, + {aarch32_op_VLD3_1_A3_nowb, "vld3", {OPR_reg_Rn}, 0xf4a00a0f, 0xffb00f0f}, + {aarch32_op_VLD3_1_A3_posti, "vld3", {OPR_reg_Rn}, 0xf4a00a0d, 0xffb00f0f}, + {aarch32_op_VLD3_1_A3_postr, "vld3", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4a00a00, 0xffb00f00}, + {aarch32_op_VLD3_a_A1_nowb, "vld3", {OPR_reg_Rn}, 0xf4a00e0f, 0xffb00f1f}, + {aarch32_op_VLD3_a_A1_posti, "vld3", {OPR_reg_Rn}, 0xf4a00e0d, 0xffb00f1f}, + {aarch32_op_VLD3_a_A1_postr, "vld3", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4a00e00, 0xffb00f10}, + {aarch32_op_VLD3_m_A1_nowb, "vld3", {OPR_reg_Rn}, 0xf420040f, 0xffb00e0f}, + {aarch32_op_VLD3_m_A1_posti, "vld3", {OPR_reg_Rn}, 0xf420040d, 0xffb00e0f}, + {aarch32_op_VLD3_m_A1_postr, "vld3", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4200400, 0xffb00e00}, + {aarch32_op_VLD4_1_A1_nowb, "vld4", {OPR_reg_Rn}, 0xf4a0030f, 0xffb00f0f}, + {aarch32_op_VLD4_1_A1_posti, "vld4", {OPR_reg_Rn}, 0xf4a0030d, 0xffb00f0f}, + {aarch32_op_VLD4_1_A1_postr, "vld4", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4a00300, 0xffb00f00}, + {aarch32_op_VLD4_1_A2_nowb, "vld4", {OPR_reg_Rn}, 0xf4a0070f, 0xffb00f0f}, + {aarch32_op_VLD4_1_A2_posti, "vld4", {OPR_reg_Rn}, 0xf4a0070d, 0xffb00f0f}, + {aarch32_op_VLD4_1_A2_postr, "vld4", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4a00700, 0xffb00f00}, + {aarch32_op_VLD4_1_A3_nowb, "vld4", {OPR_reg_Rn}, 0xf4a00b0f, 0xffb00f0f}, + {aarch32_op_VLD4_1_A3_posti, "vld4", {OPR_reg_Rn}, 0xf4a00b0d, 0xffb00f0f}, + {aarch32_op_VLD4_1_A3_postr, "vld4", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4a00b00, 0xffb00f00}, + {aarch32_op_VLD4_a_A1_nowb, "vld4", {OPR_reg_Rn}, 0xf4a00f0f, 0xffb00f0f}, + {aarch32_op_VLD4_a_A1_posti, "vld4", {OPR_reg_Rn}, 0xf4a00f0d, 0xffb00f0f}, + {aarch32_op_VLD4_a_A1_postr, "vld4", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4a00f00, 0xffb00f00}, + {aarch32_op_VLD4_m_A1_nowb, "vld4", {OPR_reg_Rn}, 0xf420000f, 0xffb00e0f}, + {aarch32_op_VLD4_m_A1_posti, "vld4", {OPR_reg_Rn}, 0xf420000d, 0xffb00e0f}, + {aarch32_op_VLD4_m_A1_postr, "vld4", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4200000, 0xffb00e00}, + {aarch32_op_VLDMDB_A1, "vldmdb", {OPR_reg_Rn}, 0x0d300b00, 0x0fb00f01}, + {aarch32_op_VLDM_A1, "vldm", {OPR_reg_Rn}, 0x0c900b00, 0x0f900f01}, + {aarch32_op_VLDMDB_A2, "vldmdb", {OPR_reg_Rn}, 0x0d300a00, 0x0fb00f00}, + {aarch32_op_VLDM_A2, "vldm", {OPR_reg_Rn}, 0x0c900a00, 0x0f900f00}, + {aarch32_op_VLDR_A1_H, "vldr", {OPR_reg_Sd, OPR_reg_Rn}, 0x0d100900, 0x0f300f00}, + {aarch32_op_VLDR_A1_S, "vldr", {OPR_reg_Sd, OPR_reg_Rn}, 0x0d100a00, 0x0f300f00}, + {aarch32_op_VLDR_A1_D, "vldr", {OPR_reg_Dd, OPR_reg_Rn}, 0x0d100b00, 0x0f300f00}, + {aarch32_op_VLDR_l_A1_H, "vldr", {OPR_reg_Sd, OPR_imm_label_7}, 0x0d1f0900, 0x0f3f0f00}, + {aarch32_op_VLDR_l_A1_S, "vldr", {OPR_reg_Sd, OPR_imm_label}, 0x0d1f0a00, 0x0f3f0f00}, + {aarch32_op_VLDR_l_A1_D, "vldr", {OPR_reg_Dd, OPR_imm_label}, 0x0d1f0b00, 0x0f3f0f00}, + {aarch32_op_VMAX_f_A1_D, "vmax", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000f00, 0xffa00f50}, + {aarch32_op_VMAX_f_A1_Q, "vmax", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000f40, 0xffa00f50}, + {aarch32_op_VMAX_i_A1_D, "vmax", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000600, 0xfe800f50}, + {aarch32_op_VMAX_i_A1_Q, "vmax", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000640, 0xfe800f50}, + {aarch32_op_VMAXNM_A1_D, "vmaxnm", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3000f10, 0xffa00f50}, + {aarch32_op_VMAXNM_A1_Q, "vmaxnm", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3000f50, 0xffa00f50}, + {aarch32_op_VMAXNM_A2_H, "vmaxnm", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0xfe800900, 0xffb00f50}, + {aarch32_op_VMAXNM_A2_S, "vmaxnm", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0xfe800a00, 0xffb00f50}, + {aarch32_op_VMAXNM_A2_D, "vmaxnm", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xfe800b00, 0xffb00f50}, + {aarch32_op_VMIN_f_A1_D, "vmin", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2200f00, 0xffa00f50}, + {aarch32_op_VMIN_f_A1_Q, "vmin", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2200f40, 0xffa00f50}, + {aarch32_op_VMIN_i_A1_D, "vmin", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000610, 0xfe800f50}, + {aarch32_op_VMIN_i_A1_Q, "vmin", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000650, 0xfe800f50}, + {aarch32_op_VMINNM_A1_D, "vminnm", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3200f10, 0xffa00f50}, + {aarch32_op_VMINNM_A1_Q, "vminnm", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3200f50, 0xffa00f50}, + {aarch32_op_VMINNM_A2_H, "vminnm", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0xfe800940, 0xffb00f50}, + {aarch32_op_VMINNM_A2_S, "vminnm", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0xfe800a40, 0xffb00f50}, + {aarch32_op_VMINNM_A2_D, "vminnm", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xfe800b40, 0xffb00f50}, + {aarch32_op_VMLA_f_A1_D, "vmla", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000d10, 0xffa00f50}, + {aarch32_op_VMLA_f_A1_Q, "vmla", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000d50, 0xffa00f50}, + {aarch32_op_VMLA_f_A2_H, "vmla", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e000900, 0x0fb00f50}, + {aarch32_op_VMLA_f_A2_S, "vmla", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e000a00, 0x0fb00f50}, + {aarch32_op_VMLA_f_A2_D, "vmla", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0x0e000b00, 0x0fb00f50}, + {aarch32_op_VMLA_i_A1_D, "vmla", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000900, 0xff800f50}, + {aarch32_op_VMLA_i_A1_Q, "vmla", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000940, 0xff800f50}, + {aarch32_op_VMLA_s_A1_D, "vmla", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm_x_}, 0xf2800040, 0xff800e50}, + {aarch32_op_VMLA_s_A1_Q, "vmla", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Dm_x_}, 0xf3800040, 0xff800e50}, + {aarch32_op_VMLAL_i_A1, "vmlal", {OPR_reg_Qd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2800800, 0xfe800f50}, + {aarch32_op_VMLAL_s_A1, "vmlal", {OPR_reg_Qd, OPR_reg_Dn, OPR_reg_Dm_x_}, 0xf2800240, 0xfe800f50}, + {aarch32_op_VMLS_f_A1_D, "vmls", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2200d10, 0xffa00f50}, + {aarch32_op_VMLS_f_A1_Q, "vmls", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2200d50, 0xffa00f50}, + {aarch32_op_VMLS_f_A2_H, "vmls", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e000940, 0x0fb00f50}, + {aarch32_op_VMLS_f_A2_S, "vmls", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e000a40, 0x0fb00f50}, + {aarch32_op_VMLS_f_A2_D, "vmls", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0x0e000b40, 0x0fb00f50}, + {aarch32_op_VMLS_i_A1_D, "vmls", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3000900, 0xff800f50}, + {aarch32_op_VMLS_i_A1_Q, "vmls", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3000940, 0xff800f50}, + {aarch32_op_VMLS_s_A1_D, "vmls", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm_x_}, 0xf2800440, 0xff800e50}, + {aarch32_op_VMLS_s_A1_Q, "vmls", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Dm_x_}, 0xf3800440, 0xff800e50}, + {aarch32_op_VMLSL_i_A1, "vmlsl", {OPR_reg_Qd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2800a00, 0xfe800f50}, + {aarch32_op_VMLSL_s_A1, "vmlsl", {OPR_reg_Qd, OPR_reg_Dn, OPR_reg_Dm_x_}, 0xf2800640, 0xfe800f50}, + {aarch32_op_VMOV_tod_A1, "vmov", {OPR_reg_Dm, OPR_reg_Rt, OPR_reg_Rt2}, 0x0c400b10, 0x0ff00fd0}, + {aarch32_op_VMOV_d_A1, "vmov", {OPR_reg_Rt, OPR_reg_Rt2, OPR_reg_Dm}, 0x0c500b10, 0x0ff00fd0}, + {aarch32_op_VMOV_toh_A1, "vmov", {OPR_reg_Sn, OPR_reg_Rt}, 0x0e000910, 0x0ff00f10}, + {aarch32_op_VMOV_h_A1, "vmov", {OPR_reg_Rt, OPR_reg_Sn}, 0x0e100910, 0x0ff00f10}, + {aarch32_op_VMOV_i_A1_D, "vmov", {OPR_reg_Dd}, 0xf2800010, 0xfeb809f0}, + {aarch32_op_VMOV_i_A1_Q, "vmov", {OPR_reg_Qd}, 0xf2800050, 0xfeb809f0}, + {aarch32_op_VMOV_i_A2_H, "vmov", {OPR_reg_Sd}, 0x0eb00900, 0x0fb00f50}, + {aarch32_op_VMOV_i_A2_S, "vmov", {OPR_reg_Sd}, 0x0eb00a00, 0x0fb00f50}, + {aarch32_op_VMOV_i_A2_D, "vmov", {OPR_reg_Dd}, 0x0eb00b00, 0x0fb00f50}, + {aarch32_op_VMOV_i_A3_D, "vmov", {OPR_reg_Dd}, 0xf2800810, 0xfeb80df0}, + {aarch32_op_VMOV_i_A3_Q, "vmov", {OPR_reg_Qd}, 0xf2800850, 0xfeb80df0}, + {aarch32_op_VMOV_i_A4_D, "vmov", {OPR_reg_Dd}, 0xf2800c10, 0xfeb80cf0}, + {aarch32_op_VMOV_i_A4_Q, "vmov", {OPR_reg_Qd}, 0xf2800c50, 0xfeb80cf0}, + {aarch32_op_VMOV_i_A5_D, "vmov", {OPR_reg_Dd}, 0xf2800e30, 0xfeb80ff0}, + {aarch32_op_VMOV_i_A5_Q, "vmov", {OPR_reg_Qd}, 0xf2800e70, 0xfeb80ff0}, + {aarch32_op_VMOV_r_A2_S, "vmov", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb00a40, 0x0fbf0fd0}, + {aarch32_op_VMOV_r_A2_D, "vmov", {OPR_reg_Dd, OPR_reg_Dm}, 0x0eb00b40, 0x0fbf0fd0}, + {aarch32_op_VMOV_rs_A1, "vmov", {OPR_reg_Dd_x_, OPR_reg_Rt}, 0x0e000b10, 0x0f900f10}, + {aarch32_op_VMOV_tos_A1, "vmov", {OPR_reg_Sn, OPR_reg_Rt}, 0x0e000a10, 0x0ff00f10}, + {aarch32_op_VMOV_s_A1, "vmov", {OPR_reg_Rt, OPR_reg_Sn}, 0x0e100a10, 0x0ff00f10}, + {aarch32_op_VMOV_sr_A1, "vmov", {OPR_reg_Rt, OPR_reg_Dn_x_}, 0x0e100b10, 0x0f100f10}, + {aarch32_op_VMOV_toss_A1, "vmov", {OPR_reg_Sm, OPR_reg_Sm1, OPR_reg_Rt, OPR_reg_Rt2}, 0x0c400a10, 0x0ff00fd0}, + {aarch32_op_VMOV_ss_A1, "vmov", {OPR_reg_Rt, OPR_reg_Rt2, OPR_reg_Sm, OPR_reg_Sm1}, 0x0c500a10, 0x0ff00fd0}, + {aarch32_op_VMOV_VORR_r_A1_D, "vmov", {OPR_reg_Dd, OPR_reg_Dm}, 0xf2200110, 0xffb00f50}, + {aarch32_op_VMOV_VORR_r_A1_Q, "vmov", {OPR_reg_Qd, OPR_reg_Qm}, 0xf2200150, 0xffb00f50}, + {aarch32_op_VMOVL_A1, "vmovl", {OPR_reg_Qd, OPR_reg_Dm}, 0xf2800a10, 0xfe870fd0}, + {aarch32_op_VMOVN_A1, "vmovn", {OPR_reg_Dd, OPR_reg_Qm}, 0xf3b20200, 0xffb30fd0}, + {aarch32_op_VMOVX_A1, "vmovx", {OPR_reg_Sd, OPR_reg_Sm}, 0xfeb00a40, 0xffbf0fd0}, + {aarch32_op_VMRS_A1_AS, "vmrs", {OPR_reg_Rt}, 0x0ef00a10, 0x0ff00f10}, + {aarch32_op_VMSR_A1_AS, "vmsr", {OPR_reg_Rt}, 0x0ee00a10, 0x0ff00f10}, + {aarch32_op_VMUL_f_A1_D, "vmul", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3000d10, 0xffa00f50}, + {aarch32_op_VMUL_f_A1_Q, "vmul", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3000d50, 0xffa00f50}, + {aarch32_op_VMUL_f_A2_H, "vmul", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e200900, 0x0fb00f50}, + {aarch32_op_VMUL_f_A2_S, "vmul", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e200a00, 0x0fb00f50}, + {aarch32_op_VMUL_f_A2_D, "vmul", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0x0e200b00, 0x0fb00f50}, + {aarch32_op_VMUL_i_A1_D, "vmul", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000910, 0xfe800f50}, + {aarch32_op_VMUL_i_A1_Q, "vmul", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000950, 0xfe800f50}, + {aarch32_op_VMUL_s_A1_D, "vmul", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2800840, 0xff800e50}, + {aarch32_op_VMUL_s_A1_Q, "vmul", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Dm}, 0xf3800840, 0xff800e50}, + {aarch32_op_VMULL_i_A1, "vmull", {OPR_reg_Qd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2800c00, 0xfe800d50}, + {aarch32_op_VMULL_s_A1, "vmull", {OPR_reg_Qd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2800a40, 0xfe800f50}, + {aarch32_op_VMVN_i_A1_D, "vmvn", {OPR_reg_Dd}, 0xf2800030, 0xfeb809f0}, + {aarch32_op_VMVN_i_A1_Q, "vmvn", {OPR_reg_Qd}, 0xf2800070, 0xfeb809f0}, + {aarch32_op_VMVN_i_A2_D, "vmvn", {OPR_reg_Dd}, 0xf2800830, 0xfeb80df0}, + {aarch32_op_VMVN_i_A2_Q, "vmvn", {OPR_reg_Qd}, 0xf2800870, 0xfeb80df0}, + {aarch32_op_VMVN_i_A3_D, "vmvn", {OPR_reg_Dd}, 0xf2800c30, 0xfeb80ef0}, + {aarch32_op_VMVN_i_A3_Q, "vmvn", {OPR_reg_Qd}, 0xf2800c70, 0xfeb80ef0}, + {aarch32_op_VMVN_r_A1_D, "vmvn", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b00580, 0xffb30fd0}, + {aarch32_op_VMVN_r_A1_Q, "vmvn", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b005c0, 0xffb30fd0}, + {aarch32_op_VNEG_A1_D, "vneg", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b10380, 0xffb30bd0}, + {aarch32_op_VNEG_A1_Q, "vneg", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b103c0, 0xffb30bd0}, + {aarch32_op_VNEG_A2_H, "vneg", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb10940, 0x0fbf0fd0}, + {aarch32_op_VNEG_A2_S, "vneg", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb10a40, 0x0fbf0fd0}, + {aarch32_op_VNEG_A2_D, "vneg", {OPR_reg_Dd, OPR_reg_Dm}, 0x0eb10b40, 0x0fbf0fd0}, + {aarch32_op_VNMLA_A1_H, "vnmla", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e100940, 0x0fb00f50}, + {aarch32_op_VNMLA_A1_S, "vnmla", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e100a40, 0x0fb00f50}, + {aarch32_op_VNMLA_A1_D, "vnmla", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0x0e100b40, 0x0fb00f50}, + {aarch32_op_VNMLS_A1_H, "vnmls", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e100900, 0x0fb00f50}, + {aarch32_op_VNMLS_A1_S, "vnmls", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e100a00, 0x0fb00f50}, + {aarch32_op_VNMLS_A1_D, "vnmls", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0x0e100b00, 0x0fb00f50}, + {aarch32_op_VNMUL_A1_H, "vnmul", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e200940, 0x0fb00f50}, + {aarch32_op_VNMUL_A1_S, "vnmul", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e200a40, 0x0fb00f50}, + {aarch32_op_VNMUL_A1_D, "vnmul", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0x0e200b40, 0x0fb00f50}, + {aarch32_op_VORN_r_A1_D, "vorn", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2300110, 0xffb00f50}, + {aarch32_op_VORN_r_A1_Q, "vorn", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2300150, 0xffb00f50}, + {aarch32_op_VORN_VORR_i_A1_D, "vorn", {OPR_reg_Dd, OPR_reg_Dd}, 0xf2800110, 0xfeb809f0}, + {aarch32_op_VORN_VORR_i_A1_Q, "vorn", {OPR_reg_Qd, OPR_reg_Qd}, 0xf2800150, 0xfeb809f0}, + {aarch32_op_VORN_VORR_i_A2_D, "vorn", {OPR_reg_Dd, OPR_reg_Dd}, 0xf2800910, 0xfeb80df0}, + {aarch32_op_VORN_VORR_i_A2_Q, "vorn", {OPR_reg_Qd, OPR_reg_Qd}, 0xf2800950, 0xfeb80df0}, + {aarch32_op_VORR_i_A1_D, "vorr", {OPR_reg_Dd, OPR_reg_Dd}, 0xf2800110, 0xfeb809f0}, + {aarch32_op_VORR_i_A1_Q, "vorr", {OPR_reg_Qd, OPR_reg_Qd}, 0xf2800150, 0xfeb809f0}, + {aarch32_op_VORR_i_A2_D, "vorr", {OPR_reg_Dd, OPR_reg_Dd}, 0xf2800910, 0xfeb80df0}, + {aarch32_op_VORR_i_A2_Q, "vorr", {OPR_reg_Qd, OPR_reg_Qd}, 0xf2800950, 0xfeb80df0}, + {aarch32_op_VORR_r_A1_D, "vorr", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2200110, 0xffb00f50}, + {aarch32_op_VORR_r_A1_Q, "vorr", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2200150, 0xffb00f50}, + {aarch32_op_VPADAL_A1_D, "vpadal", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b00600, 0xffb30f50}, + {aarch32_op_VPADAL_A1_Q, "vpadal", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b00640, 0xffb30f50}, + {aarch32_op_VPADD_f_A1, "vpadd", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3000d00, 0xffa00f10}, + {aarch32_op_VPADD_i_A1, "vpadd", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000b10, 0xff800f10}, + {aarch32_op_VPADDL_A1_D, "vpaddl", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b00200, 0xffb30f50}, + {aarch32_op_VPADDL_A1_Q, "vpaddl", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b00240, 0xffb30f50}, + {aarch32_op_VPMAX_f_A1, "vpmax", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3000f00, 0xffa00f50}, + {aarch32_op_VPMAX_i_A1, "vpmax", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000a00, 0xfe800f50}, + {aarch32_op_VPMIN_f_A1, "vpmin", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3200f00, 0xffa00f50}, + {aarch32_op_VPMIN_i_A1, "vpmin", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000a10, 0xfe800f50}, + {aarch32_op_VPOP_VLDM_A1, "vpop", {}, 0x0cbd0b00, 0x0fbf0f01}, + {aarch32_op_VPOP_VLDM_A2, "vpop", {}, 0x0cbd0a00, 0x0fbf0f00}, + {aarch32_op_VPUSH_VSTMDB_A1, "vpush", {}, 0x0d2d0b00, 0x0fbf0f01}, + {aarch32_op_VPUSH_VSTMDB_A2, "vpush", {}, 0x0d2d0a00, 0x0fbf0f00}, + {aarch32_op_VQABS_A1_D, "vqabs", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b00700, 0xffb30fd0}, + {aarch32_op_VQABS_A1_Q, "vqabs", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b00740, 0xffb30fd0}, + {aarch32_op_VQADD_A1_D, "vqadd", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000010, 0xfe800f50}, + {aarch32_op_VQADD_A1_Q, "vqadd", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000050, 0xfe800f50}, + {aarch32_op_VQDMLAL_A1, "vqdmlal", {OPR_reg_Qd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2800900, 0xff800f50}, + {aarch32_op_VQDMLAL_A2, "vqdmlal", {OPR_reg_Qd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2800340, 0xff800f50}, + {aarch32_op_VQDMLSL_A1, "vqdmlsl", {OPR_reg_Qd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2800b00, 0xff800f50}, + {aarch32_op_VQDMLSL_A2, "vqdmlsl", {OPR_reg_Qd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2800740, 0xff800f50}, + {aarch32_op_VQDMULH_A1_D, "vqdmulh", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000b00, 0xff800f50}, + {aarch32_op_VQDMULH_A1_Q, "vqdmulh", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000b40, 0xff800f50}, + {aarch32_op_VQDMULH_A2_D, "vqdmulh", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm_x_}, 0xf2800c40, 0xff800f50}, + {aarch32_op_VQDMULH_A2_Q, "vqdmulh", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Dm_x_}, 0xf3800c40, 0xff800f50}, + {aarch32_op_VQDMULL_A1, "vqdmull", {OPR_reg_Qd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2800d00, 0xff800f50}, + {aarch32_op_VQDMULL_A2, "vqdmull", {OPR_reg_Qd, OPR_reg_Dn, OPR_reg_Dm_x_}, 0xf2800b40, 0xff800f50}, + {aarch32_op_VQMOVN_A1, "vqmovn", {OPR_reg_Dd, OPR_reg_Qm}, 0xf3b20280, 0xffb30f90}, + {aarch32_op_VQMOVUN_A1, "vqmovun", {OPR_reg_Dd, OPR_reg_Qm}, 0xf3b20240, 0xffb30fd0}, + {aarch32_op_VQNEG_A1_D, "vqneg", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b00780, 0xffb30fd0}, + {aarch32_op_VQNEG_A1_Q, "vqneg", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b007c0, 0xffb30fd0}, + {aarch32_op_VQRDMLAH_A1_D, "vqrdmlah", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3000b10, 0xff800f50}, + {aarch32_op_VQRDMLAH_A1_Q, "vqrdmlah", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3000b50, 0xff800f50}, + {aarch32_op_VQRDMLAH_A2_D, "vqrdmlah", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm_x_}, 0xf2800e40, 0xff800f50}, + {aarch32_op_VQRDMLAH_A2_Q, "vqrdmlah", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Dm_x_}, 0xf3800e40, 0xff800f50}, + {aarch32_op_VQRDMLSH_A1_D, "vqrdmlsh", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3000c10, 0xff800f50}, + {aarch32_op_VQRDMLSH_A1_Q, "vqrdmlsh", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3000c50, 0xff800f50}, + {aarch32_op_VQRDMLSH_A2_D, "vqrdmlsh", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm_x_}, 0xf2800f40, 0xff800f50}, + {aarch32_op_VQRDMLSH_A2_Q, "vqrdmlsh", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Dm_x_}, 0xf3800f40, 0xff800f50}, + {aarch32_op_VQRDMULH_A1_D, "vqrdmulh", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3000b00, 0xff800f50}, + {aarch32_op_VQRDMULH_A1_Q, "vqrdmulh", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3000b40, 0xff800f50}, + {aarch32_op_VQRDMULH_A2_D, "vqrdmulh", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm_x_}, 0xf2800d40, 0xff800f50}, + {aarch32_op_VQRDMULH_A2_Q, "vqrdmulh", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Dm_x_}, 0xf3800d40, 0xff800f50}, + {aarch32_op_VQRSHL_A1_D, "vqrshl", {OPR_reg_Dd, OPR_reg_Dm, OPR_reg_Dn}, 0xf2000510, 0xfe800f50}, + {aarch32_op_VQRSHL_A1_Q, "vqrshl", {OPR_reg_Qd, OPR_reg_Qm, OPR_reg_Qn}, 0xf2000550, 0xfe800f50}, + {aarch32_op_VQRSHRN_A1, "vqrshrn", {OPR_reg_Dd, OPR_reg_Qm}, 0xf2800950, 0xfe800fd0}, + {aarch32_op_VQRSHRUN_A1, "vqrshrun", {OPR_reg_Dd, OPR_reg_Qm}, 0xf3800850, 0xff800fd0}, + {aarch32_op_VQRSHRN_VQMOVN_A1, "vqrshrn", {OPR_reg_Dd, OPR_reg_Qm}, 0xf3b20280, 0xffb30f90}, + {aarch32_op_VQRSHRUN_VQMOVUN_A1, "vqrshrun", {OPR_reg_Dd, OPR_reg_Qm}, 0xf3b20240, 0xffb30fd0}, + {aarch32_op_VQSHL_i_A1_D, "vqshl", {OPR_reg_Dd, OPR_reg_Dm}, 0xf2800710, 0xfe800f50}, + {aarch32_op_VQSHL_i_A1_Q, "vqshl", {OPR_reg_Qd, OPR_reg_Qm}, 0xf2800750, 0xfe800f50}, + {aarch32_op_VQSHLU_i_A1_D, "vqshlu", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3800610, 0xff800f50}, + {aarch32_op_VQSHLU_i_A1_Q, "vqshlu", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3800650, 0xff800f50}, + {aarch32_op_VQSHL_r_A1_D, "vqshl", {OPR_reg_Dd, OPR_reg_Dm, OPR_reg_Dn}, 0xf2000410, 0xfe800f50}, + {aarch32_op_VQSHL_r_A1_Q, "vqshl", {OPR_reg_Qd, OPR_reg_Qm, OPR_reg_Qn}, 0xf2000450, 0xfe800f50}, + {aarch32_op_VQSHRN_A1, "vqshrn", {OPR_reg_Dd, OPR_reg_Qm}, 0xf2800910, 0xfe800fd0}, + {aarch32_op_VQSHRUN_A1, "vqshrun", {OPR_reg_Dd, OPR_reg_Qm}, 0xf3800810, 0xff800fd0}, + {aarch32_op_VQSHRN_VQMOVN_A1, "vqshrn", {OPR_reg_Dd, OPR_reg_Qm}, 0xf3b20280, 0xffb30f90}, + {aarch32_op_VQSHRUN_VQMOVUN_A1, "vqshrun", {OPR_reg_Dd, OPR_reg_Qm}, 0xf3b20240, 0xffb30fd0}, + {aarch32_op_VQSUB_A1_D, "vqsub", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000210, 0xfe800f50}, + {aarch32_op_VQSUB_A1_Q, "vqsub", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000250, 0xfe800f50}, + {aarch32_op_VRADDHN_A1, "vraddhn", {OPR_reg_Dd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3800400, 0xff800f50}, + {aarch32_op_VRECPE_A1_D, "vrecpe", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b30400, 0xffb30ed0}, + {aarch32_op_VRECPE_A1_Q, "vrecpe", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b30440, 0xffb30ed0}, + {aarch32_op_VRECPS_A1_D, "vrecps", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000f10, 0xffa00f50}, + {aarch32_op_VRECPS_A1_Q, "vrecps", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000f50, 0xffa00f50}, + {aarch32_op_VREV16_A1_D, "vrev16", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b00100, 0xffb30fd0}, + {aarch32_op_VREV16_A1_Q, "vrev16", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b00140, 0xffb30fd0}, + {aarch32_op_VREV32_A1_D, "vrev32", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b00080, 0xffb30fd0}, + {aarch32_op_VREV32_A1_Q, "vrev32", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b000c0, 0xffb30fd0}, + {aarch32_op_VREV64_A1_D, "vrev64", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b00000, 0xffb30fd0}, + {aarch32_op_VREV64_A1_Q, "vrev64", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b00040, 0xffb30fd0}, + {aarch32_op_VRHADD_A1_D, "vrhadd", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000100, 0xfe800f50}, + {aarch32_op_VRHADD_A1_Q, "vrhadd", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000140, 0xfe800f50}, + {aarch32_op_VRINTA_asimd_A1_D, "vrinta", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b20500, 0xffb30fd0}, + {aarch32_op_VRINTA_asimd_A1_Q, "vrinta", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b20540, 0xffb30fd0}, + {aarch32_op_VRINTA_vfp_A1_H, "vrinta", {OPR_reg_Sd, OPR_reg_Sm}, 0xfeb80940, 0xffbf0fd0}, + {aarch32_op_VRINTA_vfp_A1_S, "vrinta", {OPR_reg_Sd, OPR_reg_Sm}, 0xfeb80a40, 0xffbf0fd0}, + {aarch32_op_VRINTA_vfp_A1_D, "vrinta", {OPR_reg_Dd, OPR_reg_Dm}, 0xfeb80b40, 0xffbf0fd0}, + {aarch32_op_VRINTM_asimd_A1_D, "vrintm", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b20680, 0xffb30fd0}, + {aarch32_op_VRINTM_asimd_A1_Q, "vrintm", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b206c0, 0xffb30fd0}, + {aarch32_op_VRINTM_vfp_A1_H, "vrintm", {OPR_reg_Sd, OPR_reg_Sm}, 0xfebb0940, 0xffbf0fd0}, + {aarch32_op_VRINTM_vfp_A1_S, "vrintm", {OPR_reg_Sd, OPR_reg_Sm}, 0xfebb0a40, 0xffbf0fd0}, + {aarch32_op_VRINTM_vfp_A1_D, "vrintm", {OPR_reg_Dd, OPR_reg_Dm}, 0xfebb0b40, 0xffbf0fd0}, + {aarch32_op_VRINTN_asimd_A1_D, "vrintn", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b20400, 0xffb30fd0}, + {aarch32_op_VRINTN_asimd_A1_Q, "vrintn", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b20440, 0xffb30fd0}, + {aarch32_op_VRINTN_vfp_A1_H, "vrintn", {OPR_reg_Sd, OPR_reg_Sm}, 0xfeb90940, 0xffbf0fd0}, + {aarch32_op_VRINTN_vfp_A1_S, "vrintn", {OPR_reg_Sd, OPR_reg_Sm}, 0xfeb90a40, 0xffbf0fd0}, + {aarch32_op_VRINTN_vfp_A1_D, "vrintn", {OPR_reg_Dd, OPR_reg_Dm}, 0xfeb90b40, 0xffbf0fd0}, + {aarch32_op_VRINTP_asimd_A1_D, "vrintp", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b20780, 0xffb30fd0}, + {aarch32_op_VRINTP_asimd_A1_Q, "vrintp", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b207c0, 0xffb30fd0}, + {aarch32_op_VRINTP_vfp_A1_H, "vrintp", {OPR_reg_Sd, OPR_reg_Sm}, 0xfeba0940, 0xffbf0fd0}, + {aarch32_op_VRINTP_vfp_A1_S, "vrintp", {OPR_reg_Sd, OPR_reg_Sm}, 0xfeba0a40, 0xffbf0fd0}, + {aarch32_op_VRINTP_vfp_A1_D, "vrintp", {OPR_reg_Dd, OPR_reg_Dm}, 0xfeba0b40, 0xffbf0fd0}, + {aarch32_op_VRINTR_vfp_A1_H, "vrintr", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb60940, 0x0fbf0fd0}, + {aarch32_op_VRINTR_vfp_A1_S, "vrintr", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb60a40, 0x0fbf0fd0}, + {aarch32_op_VRINTR_vfp_A1_D, "vrintr", {OPR_reg_Dd, OPR_reg_Dm}, 0x0eb60b40, 0x0fbf0fd0}, + {aarch32_op_VRINTX_asimd_A1_D, "vrintx", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b20480, 0xffb30fd0}, + {aarch32_op_VRINTX_asimd_A1_Q, "vrintx", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b204c0, 0xffb30fd0}, + {aarch32_op_VRINTX_vfp_A1_H, "vrintx", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb70940, 0x0fbf0fd0}, + {aarch32_op_VRINTX_vfp_A1_S, "vrintx", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb70a40, 0x0fbf0fd0}, + {aarch32_op_VRINTX_vfp_A1_D, "vrintx", {OPR_reg_Dd, OPR_reg_Dm}, 0x0eb70b40, 0x0fbf0fd0}, + {aarch32_op_VRINTZ_asimd_A1_D, "vrintz", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b20580, 0xffb30fd0}, + {aarch32_op_VRINTZ_asimd_A1_Q, "vrintz", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b205c0, 0xffb30fd0}, + {aarch32_op_VRINTZ_vfp_A1_H, "vrintz", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb609c0, 0x0fbf0fd0}, + {aarch32_op_VRINTZ_vfp_A1_S, "vrintz", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb60ac0, 0x0fbf0fd0}, + {aarch32_op_VRINTZ_vfp_A1_D, "vrintz", {OPR_reg_Dd, OPR_reg_Dm}, 0x0eb60bc0, 0x0fbf0fd0}, + {aarch32_op_VRSHL_A1_D, "vrshl", {OPR_reg_Dd, OPR_reg_Dm, OPR_reg_Dn}, 0xf2000500, 0xfe800f50}, + {aarch32_op_VRSHL_A1_Q, "vrshl", {OPR_reg_Qd, OPR_reg_Qm, OPR_reg_Qn}, 0xf2000540, 0xfe800f50}, + {aarch32_op_VRSHR_A1_D, "vrshr", {OPR_reg_Dd, OPR_reg_Dm}, 0xf2800210, 0xfe800f50}, + {aarch32_op_VRSHR_A1_Q, "vrshr", {OPR_reg_Qd, OPR_reg_Qm}, 0xf2800250, 0xfe800f50}, + {aarch32_op_VRSHR_VORR_r_A1_D, "vrshr", {OPR_reg_Dd, OPR_reg_Dm}, 0xf2200110, 0xffb00f50}, + {aarch32_op_VRSHR_VORR_r_A1_Q, "vrshr", {OPR_reg_Qd, OPR_reg_Qm}, 0xf2200150, 0xffb00f50}, + {aarch32_op_VRSHRN_A1, "vrshrn", {OPR_reg_Dd, OPR_reg_Qm}, 0xf2800850, 0xff800fd0}, + {aarch32_op_VRSHRN_VMOVN_A1, "vrshrn", {OPR_reg_Dd, OPR_reg_Qm}, 0xf3b20200, 0xffb30fd0}, + {aarch32_op_VRSQRTE_A1_D, "vrsqrte", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b30480, 0xffb30ed0}, + {aarch32_op_VRSQRTE_A1_Q, "vrsqrte", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b304c0, 0xffb30ed0}, + {aarch32_op_VRSQRTS_A1_D, "vrsqrts", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2200f10, 0xffa00f50}, + {aarch32_op_VRSQRTS_A1_Q, "vrsqrts", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2200f50, 0xffa00f50}, + {aarch32_op_VRSRA_A1_Q, "vrsra", {OPR_reg_Dd, OPR_reg_Dm}, 0xf2800310, 0xfe800f50}, + {aarch32_op_VRSRA_A1_D, "vrsra", {OPR_reg_Qd, OPR_reg_Qm}, 0xf2800350, 0xfe800f50}, + {aarch32_op_VRSUBHN_A1, "vrsubhn", {OPR_reg_Dd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3800600, 0xff800f50}, + {aarch32_op_VSELEQ_A1_D, "vseleq", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xfe000b00, 0xffb00f50}, + {aarch32_op_VSELEQ_A1_H, "vseleq", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0xfe000900, 0xffb00f50}, + {aarch32_op_VSELEQ_A1_S, "vseleq", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0xfe000a00, 0xffb00f50}, + {aarch32_op_VSELGE_A1_D, "vselge", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xfe200b00, 0xffb00f50}, + {aarch32_op_VSELGE_A1_H, "vselge", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0xfe200900, 0xffb00f50}, + {aarch32_op_VSELGE_A1_S, "vselge", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0xfe200a00, 0xffb00f50}, + {aarch32_op_VSELGT_A1_D, "vselgt", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xfe300b00, 0xffb00f50}, + {aarch32_op_VSELGT_A1_H, "vselgt", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0xfe300900, 0xffb00f50}, + {aarch32_op_VSELGT_A1_S, "vselgt", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0xfe300a00, 0xffb00f50}, + {aarch32_op_VSELVS_A1_D, "vselvs", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xfe100b00, 0xffb00f50}, + {aarch32_op_VSELVS_A1_H, "vselvs", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0xfe100900, 0xffb00f50}, + {aarch32_op_VSELVS_A1_S, "vselvs", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0xfe100a00, 0xffb00f50}, + {aarch32_op_VSHL_i_A1_D, "vshl", {OPR_reg_Dd, OPR_reg_Dm}, 0xf2800510, 0xff800f50}, + {aarch32_op_VSHL_i_A1_Q, "vshl", {OPR_reg_Qd, OPR_reg_Qm}, 0xf2800550, 0xff800f50}, + {aarch32_op_VSHL_r_A1_D, "vshl", {OPR_reg_Dd, OPR_reg_Dm, OPR_reg_Dn}, 0xf2000400, 0xfe800f50}, + {aarch32_op_VSHL_r_A1_Q, "vshl", {OPR_reg_Qd, OPR_reg_Qm, OPR_reg_Qn}, 0xf2000440, 0xfe800f50}, + {aarch32_op_VSHLL_A1, "vshll", {OPR_reg_Qd, OPR_reg_Dm}, 0xf2800a10, 0xfe800fd0}, + {aarch32_op_VSHLL_A2, "vshll", {OPR_reg_Qd, OPR_reg_Dm}, 0xf3b20300, 0xffb30fd0}, + {aarch32_op_VSHR_A1_D, "vshr", {OPR_reg_Dd, OPR_reg_Dm}, 0xf2800010, 0xfe800f50}, + {aarch32_op_VSHR_A1_Q, "vshr", {OPR_reg_Qd, OPR_reg_Qm}, 0xf2800050, 0xfe800f50}, + {aarch32_op_VSHR_VORR_r_A1_D, "vshr", {OPR_reg_Dd, OPR_reg_Dm}, 0xf2200110, 0xffb00f50}, + {aarch32_op_VSHR_VORR_r_A1_Q, "vshr", {OPR_reg_Qd, OPR_reg_Qm}, 0xf2200150, 0xffb00f50}, + {aarch32_op_VSHRN_A1, "vshrn", {OPR_reg_Dd, OPR_reg_Qm}, 0xf2800810, 0xff800fd0}, + {aarch32_op_VSHRN_VMOVN_A1, "vshrn", {OPR_reg_Dd, OPR_reg_Qm}, 0xf3b20200, 0xffb30fd0}, + {aarch32_op_VSLI_A1_D, "vsli", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3800510, 0xff800f50}, + {aarch32_op_VSLI_A1_Q, "vsli", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3800550, 0xff800f50}, + {aarch32_op_VSQRT_A1_H, "vsqrt", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb109c0, 0x0fbf0fd0}, + {aarch32_op_VSQRT_A1_S, "vsqrt", {OPR_reg_Sd, OPR_reg_Sm}, 0x0eb10ac0, 0x0fbf0fd0}, + {aarch32_op_VSQRT_A1_D, "vsqrt", {OPR_reg_Dd, OPR_reg_Dm}, 0x0eb10bc0, 0x0fbf0fd0}, + {aarch32_op_VSRA_A1_D, "vsra", {OPR_reg_Dd, OPR_reg_Dm}, 0xf2800110, 0xfe800f50}, + {aarch32_op_VSRA_A1_Q, "vsra", {OPR_reg_Qd, OPR_reg_Qm}, 0xf2800150, 0xfe800f50}, + {aarch32_op_VSRI_A1_D, "vsri", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3800410, 0xff800f50}, + {aarch32_op_VSRI_A1_Q, "vsri", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3800450, 0xff800f50}, + {aarch32_op_VST1_1_A1_nowb, "vst1", {OPR_reg_Rn}, 0xf480000f, 0xffb00f0f}, + {aarch32_op_VST1_1_A1_posti, "vst1", {OPR_reg_Rn}, 0xf480000d, 0xffb00f0f}, + {aarch32_op_VST1_1_A1_postr, "vst1", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4800000, 0xffb00f00}, + {aarch32_op_VST1_1_A2_nowb, "vst1", {OPR_reg_Rn}, 0xf480040f, 0xffb00f0f}, + {aarch32_op_VST1_1_A2_posti, "vst1", {OPR_reg_Rn}, 0xf480040d, 0xffb00f0f}, + {aarch32_op_VST1_1_A2_postr, "vst1", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4800400, 0xffb00f00}, + {aarch32_op_VST1_1_A3_nowb, "vst1", {OPR_reg_Rn}, 0xf480080f, 0xffb00f0f}, + {aarch32_op_VST1_1_A3_posti, "vst1", {OPR_reg_Rn}, 0xf480080d, 0xffb00f0f}, + {aarch32_op_VST1_1_A3_postr, "vst1", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4800800, 0xffb00f00}, + {aarch32_op_VST1_m_A1_nowb, "vst1", {OPR_reg_Rn}, 0xf400070f, 0xffb00f0f}, + {aarch32_op_VST1_m_A1_posti, "vst1", {OPR_reg_Rn}, 0xf400070d, 0xffb00f0f}, + {aarch32_op_VST1_m_A1_postr, "vst1", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4000700, 0xffb00f00}, + {aarch32_op_VST1_m_A2_nowb, "vst1", {OPR_reg_Rn}, 0xf4000a0f, 0xffb00f0f}, + {aarch32_op_VST1_m_A2_posti, "vst1", {OPR_reg_Rn}, 0xf4000a0d, 0xffb00f0f}, + {aarch32_op_VST1_m_A2_postr, "vst1", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4000a00, 0xffb00f00}, + {aarch32_op_VST1_m_A3_nowb, "vst1", {OPR_reg_Rn}, 0xf400060f, 0xffb00f0f}, + {aarch32_op_VST1_m_A3_posti, "vst1", {OPR_reg_Rn}, 0xf400060d, 0xffb00f0f}, + {aarch32_op_VST1_m_A3_postr, "vst1", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4000600, 0xffb00f00}, + {aarch32_op_VST1_m_A4_nowb, "vst1", {OPR_reg_Rn}, 0xf400020f, 0xffb00f0f}, + {aarch32_op_VST1_m_A4_posti, "vst1", {OPR_reg_Rn}, 0xf400020d, 0xffb00f0f}, + {aarch32_op_VST1_m_A4_postr, "vst1", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4000200, 0xffb00f00}, + {aarch32_op_VST2_1_A1_nowb, "vst2", {OPR_reg_Rn}, 0xf480010f, 0xffb00f0f}, + {aarch32_op_VST2_1_A1_posti, "vst2", {OPR_reg_Rn}, 0xf480010d, 0xffb00f0f}, + {aarch32_op_VST2_1_A1_postr, "vst2", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4800100, 0xffb00f00}, + {aarch32_op_VST2_1_A2_nowb, "vst2", {OPR_reg_Rn}, 0xf480050f, 0xffb00f0f}, + {aarch32_op_VST2_1_A2_posti, "vst2", {OPR_reg_Rn}, 0xf480050d, 0xffb00f0f}, + {aarch32_op_VST2_1_A2_postr, "vst2", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4800500, 0xffb00f00}, + {aarch32_op_VST2_1_A3_nowb, "vst2", {OPR_reg_Rn}, 0xf480090f, 0xffb00f0f}, + {aarch32_op_VST2_1_A3_posti, "vst2", {OPR_reg_Rn}, 0xf480090d, 0xffb00f0f}, + {aarch32_op_VST2_1_A3_postr, "vst2", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4800900, 0xffb00f00}, + {aarch32_op_VST2_m_A1_nowb, "vst2", {OPR_reg_Rn}, 0xf400080f, 0xffb00e0f}, + {aarch32_op_VST2_m_A1_posti, "vst2", {OPR_reg_Rn}, 0xf400080d, 0xffb00e0f}, + {aarch32_op_VST2_m_A1_postr, "vst2", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4000800, 0xffb00e00}, + {aarch32_op_VST2_m_A2_nowb, "vst2", {OPR_reg_Rn}, 0xf400030f, 0xffb00f0f}, + {aarch32_op_VST2_m_A2_posti, "vst2", {OPR_reg_Rn}, 0xf400030d, 0xffb00f0f}, + {aarch32_op_VST2_m_A2_postr, "vst2", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4000300, 0xffb00f00}, + {aarch32_op_VST3_1_A1_nowb, "vst3", {OPR_reg_Rn}, 0xf480020f, 0xffb00f0f}, + {aarch32_op_VST3_1_A1_posti, "vst3", {OPR_reg_Rn}, 0xf480020d, 0xffb00f0f}, + {aarch32_op_VST3_1_A1_postr, "vst3", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4800200, 0xffb00f00}, + {aarch32_op_VST3_1_A2_nowb, "vst3", {OPR_reg_Rn}, 0xf480060f, 0xffb00f0f}, + {aarch32_op_VST3_1_A2_posti, "vst3", {OPR_reg_Rn}, 0xf480060d, 0xffb00f0f}, + {aarch32_op_VST3_1_A2_postr, "vst3", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4800600, 0xffb00f00}, + {aarch32_op_VST3_1_A3_nowb, "vst3", {OPR_reg_Rn}, 0xf4800a0f, 0xffb00f0f}, + {aarch32_op_VST3_1_A3_posti, "vst3", {OPR_reg_Rn}, 0xf4800a0d, 0xffb00f0f}, + {aarch32_op_VST3_1_A3_postr, "vst3", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4800a00, 0xffb00f00}, + {aarch32_op_VST3_m_A1_nowb, "vst3", {OPR_reg_Rn}, 0xf400040f, 0xffb00e0f}, + {aarch32_op_VST3_m_A1_posti, "vst3", {OPR_reg_Rn}, 0xf400040d, 0xffb00e0f}, + {aarch32_op_VST3_m_A1_postr, "vst3", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4000400, 0xffb00e00}, + {aarch32_op_VST4_1_A1_nowb, "vst4", {OPR_reg_Rn}, 0xf480030f, 0xffb00f0f}, + {aarch32_op_VST4_1_A1_posti, "vst4", {OPR_reg_Rn}, 0xf480030d, 0xffb00f0f}, + {aarch32_op_VST4_1_A1_postr, "vst4", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4800300, 0xffb00f00}, + {aarch32_op_VST4_1_A2_nowb, "vst4", {OPR_reg_Rn}, 0xf480070f, 0xffb00f0f}, + {aarch32_op_VST4_1_A2_posti, "vst4", {OPR_reg_Rn}, 0xf480070d, 0xffb00f0f}, + {aarch32_op_VST4_1_A2_postr, "vst4", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4800700, 0xffb00f00}, + {aarch32_op_VST4_1_A3_nowb, "vst4", {OPR_reg_Rn}, 0xf4800b0f, 0xffb00f0f}, + {aarch32_op_VST4_1_A3_posti, "vst4", {OPR_reg_Rn}, 0xf4800b0d, 0xffb00f0f}, + {aarch32_op_VST4_1_A3_postr, "vst4", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4800b00, 0xffb00f00}, + {aarch32_op_VST4_m_A1_nowb, "vst4", {OPR_reg_Rn}, 0xf400000f, 0xffb00e0f}, + {aarch32_op_VST4_m_A1_posti, "vst4", {OPR_reg_Rn}, 0xf400000d, 0xffb00e0f}, + {aarch32_op_VST4_m_A1_postr, "vst4", {OPR_reg_Rn, OPR_reg_Rm}, 0xf4000000, 0xffb00e00}, + {aarch32_op_VSTMDB_A1, "vstmdb", {OPR_reg_Rn}, 0x0d200b00, 0x0fb00f01}, + {aarch32_op_VSTM_A1, "vstm", {OPR_reg_Rn}, 0x0c800b00, 0x0f900f01}, + {aarch32_op_VSTMDB_A2, "vstmdb", {OPR_reg_Rn}, 0x0d200a00, 0x0fb00f00}, + {aarch32_op_VSTM_A2, "vstm", {OPR_reg_Rn}, 0x0c800a00, 0x0f900f00}, + {aarch32_op_VSTR_A1_H, "vstr", {OPR_reg_Sd, OPR_reg_Rn}, 0x0d000900, 0x0f300f00}, + {aarch32_op_VSTR_A1_S, "vstr", {OPR_reg_Sd, OPR_reg_Rn}, 0x0d000a00, 0x0f300f00}, + {aarch32_op_VSTR_A1_D, "vstr", {OPR_reg_Dd, OPR_reg_Rn}, 0x0d000b00, 0x0f300f00}, + {aarch32_op_VSUB_f_A1_D, "vsub", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2200d00, 0xffa00f50}, + {aarch32_op_VSUB_f_A1_Q, "vsub", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2200d40, 0xffa00f50}, + {aarch32_op_VSUB_f_A2_H, "vsub", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e300940, 0x0fb00f50}, + {aarch32_op_VSUB_f_A2_S, "vsub", {OPR_reg_Sd, OPR_reg_Sn, OPR_reg_Sm}, 0x0e300a40, 0x0fb00f50}, + {aarch32_op_VSUB_f_A2_D, "vsub", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0x0e300b40, 0x0fb00f50}, + {aarch32_op_VSUB_i_A1_D, "vsub", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf3000800, 0xff800f50}, + {aarch32_op_VSUB_i_A1_Q, "vsub", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf3000840, 0xff800f50}, + {aarch32_op_VSUBHN_A1, "vsubhn", {OPR_reg_Dd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2800600, 0xff800f50}, + {aarch32_op_VSUBL_A1, "vsubl", {OPR_reg_Qd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2800200, 0xfe800f50}, + {aarch32_op_VSUBW_A1, "vsubw", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Dm}, 0xf2800300, 0xfe800f50}, + {aarch32_op_VSWP_A1_D, "vswp", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b20000, 0xffbf0fd0}, + {aarch32_op_VSWP_A1_Q, "vswp", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b20040, 0xffbf0fd0}, + {aarch32_op_VTBL_A1, "vtbl", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b00800, 0xffb00c50}, + {aarch32_op_VTBX_A1, "vtbx", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b00840, 0xffb00c50}, + {aarch32_op_VTRN_A1_D, "vtrn", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b20080, 0xffb30fd0}, + {aarch32_op_VTRN_A1_Q, "vtrn", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b200c0, 0xffb30fd0}, + {aarch32_op_VTST_A1_D, "vtst", {OPR_reg_Dd, OPR_reg_Dn, OPR_reg_Dm}, 0xf2000810, 0xff800f50}, + {aarch32_op_VTST_A1_Q, "vtst", {OPR_reg_Qd, OPR_reg_Qn, OPR_reg_Qm}, 0xf2000850, 0xff800f50}, + {aarch32_op_VUZP_A1_D, "vuzp", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b20100, 0xffb30fd0}, + {aarch32_op_VUZP_A1_Q, "vuzp", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b20140, 0xffb30fd0}, + {aarch32_op_VUZP_VTRN_A1_D, "vuzp", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b20080, 0xffb30fd0}, + {aarch32_op_VZIP_A1_D, "vzip", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b20180, 0xffb30fd0}, + {aarch32_op_VZIP_A1_Q, "vzip", {OPR_reg_Qd, OPR_reg_Qm}, 0xf3b201c0, 0xffb30fd0}, + {aarch32_op_VZIP_VTRN_A1_D, "vzip", {OPR_reg_Dd, OPR_reg_Dm}, 0xf3b20080, 0xffb30fd0}, + {aarch32_op_WFE_A1, "wfe", {}, 0x03200002, 0x0fff00ff}, + {aarch32_op_WFI_A1, "wfi", {}, 0x03200003, 0x0fff00ff}, + {aarch32_op_YIELD_A1, "yield", {}, 0x03200001, 0x0fff00ff} }; static Insn_Entry_t* INVALID_INSN = &insnTable[0]; @@ -2893,7 +2893,7 @@ static const char* bit_rep[] = { // // Static functions for use in this file only. // -#define DEBUG_AARCH32_DECODE 1 +#define DEBUG_AARCH32_DECODE 0 #if DEBUG_AARCH32_DECODE static void print_bin(FILE* fp, uint32_t insn)