From 5f9bbfdd1875d079be34d74a9f5ae8feb82b3c3c Mon Sep 17 00:00:00 2001 From: Sunny Shah Date: Sun, 6 Nov 2016 17:41:34 -0600 Subject: [PATCH] Instruction decoding fix: Alias ORR to MOV when the first source operand is WZR and the 'shift' and 'imm6' fields are both 0. --- instructionAPI/src/InstructionDecoder-aarch64.C | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/instructionAPI/src/InstructionDecoder-aarch64.C b/instructionAPI/src/InstructionDecoder-aarch64.C index a7a7b4cb08..c79a16fdc6 100644 --- a/instructionAPI/src/InstructionDecoder-aarch64.C +++ b/instructionAPI/src/InstructionDecoder-aarch64.C @@ -2544,7 +2544,15 @@ Expression::Ptr InstructionDecoder_aarch64::makeMemRefExPair2(){ else if (hasShift) { if (IS_INSN_ADDSUB_SHIFT(insn) || IS_INSN_LOGICAL_SHIFT(insn)) //add-sub shifted | logical shifted { - processShiftFieldShiftedInsn(immLen, immVal); + if(IS_INSN_LOGICAL_SHIFT(insn) && shiftField == 0 && field<5, 9>(insn) == 0x1F && immVal == 0) { + insn_in_progress->getOperation().operationID = aarch64_op_mov_orr_log_shift; + insn_in_progress->getOperation().mnemonic = "mov"; + skipRn = true; + + insn_in_progress->appendOperand(makeRmExpr(), true, false); + } else { + processShiftFieldShiftedInsn(immLen, immVal); + } } else if (IS_INSN_ADDSUB_IMM(insn)) //add-sub (immediate) {