From e13086adbc45fe8d973eefd2a2d2b7c4a303781f Mon Sep 17 00:00:00 2001 From: Sunny Shah Date: Thu, 11 May 2017 10:49:37 -0500 Subject: [PATCH] Added pseudocode extractor extract and instruction pseudocode files ISA_ps contains one file for each instruction in the XML specification, with each file containing the pseudocode for that instruction extracted from the specification by the script. --- instructionAPI/ISA_ps/abs_advsimd | 17 +++ instructionAPI/ISA_ps/adc | 18 ++++ instructionAPI/ISA_ps/adcs | 18 ++++ instructionAPI/ISA_ps/add_addsub_ext | 26 +++++ instructionAPI/ISA_ps/add_addsub_imm | 26 +++++ instructionAPI/ISA_ps/add_addsub_shift | 22 ++++ instructionAPI/ISA_ps/add_advsimd | 19 ++++ instructionAPI/ISA_ps/addhn_advsimd | 23 ++++ instructionAPI/ISA_ps/addp_advsimd_pair | 5 + instructionAPI/ISA_ps/addp_advsimd_vec | 16 +++ instructionAPI/ISA_ps/adds_addsub_ext | 26 +++++ instructionAPI/ISA_ps/adds_addsub_imm | 26 +++++ instructionAPI/ISA_ps/adds_addsub_shift | 22 ++++ instructionAPI/ISA_ps/addv_advsimd | 5 + instructionAPI/ISA_ps/adr | 9 ++ instructionAPI/ISA_ps/adrp | 9 ++ instructionAPI/ISA_ps/aesd_advsimd | 14 +++ instructionAPI/ISA_ps/aese_advsimd | 14 +++ instructionAPI/ISA_ps/aesimc_advsimd | 12 +++ instructionAPI/ISA_ps/aesmc_advsimd | 12 +++ instructionAPI/ISA_ps/and_advsimd | 18 ++++ instructionAPI/ISA_ps/and_log_imm | 23 ++++ instructionAPI/ISA_ps/and_log_shift | 20 ++++ instructionAPI/ISA_ps/ands_log_imm | 23 ++++ instructionAPI/ISA_ps/ands_log_shift | 20 ++++ instructionAPI/ISA_ps/asr_asrv | 7 ++ instructionAPI/ISA_ps/asr_sbfm | 13 +++ instructionAPI/ISA_ps/asrv | 7 ++ instructionAPI/ISA_ps/at_sys | 6 ++ instructionAPI/ISA_ps/b_cond | 5 + instructionAPI/ISA_ps/b_uncond | 5 + instructionAPI/ISA_ps/bfi_bfm | 13 +++ instructionAPI/ISA_ps/bfm | 13 +++ instructionAPI/ISA_ps/bfxil_bfm | 13 +++ instructionAPI/ISA_ps/bic_advsimd_imm | 23 ++++ instructionAPI/ISA_ps/bic_advsimd_reg | 18 ++++ instructionAPI/ISA_ps/bic_log_shift | 20 ++++ instructionAPI/ISA_ps/bics | 20 ++++ instructionAPI/ISA_ps/bif_advsimd | 31 ++++++ instructionAPI/ISA_ps/bit_advsimd | 31 ++++++ instructionAPI/ISA_ps/bl | 5 + instructionAPI/ISA_ps/blr | 6 ++ instructionAPI/ISA_ps/br | 6 ++ instructionAPI/ISA_ps/brk | 3 + instructionAPI/ISA_ps/bsl_advsimd | 31 ++++++ instructionAPI/ISA_ps/cbnz | 7 ++ instructionAPI/ISA_ps/cbz | 7 ++ instructionAPI/ISA_ps/ccmn_imm | 14 +++ instructionAPI/ISA_ps/ccmn_reg | 14 +++ instructionAPI/ISA_ps/ccmp_imm | 14 +++ instructionAPI/ISA_ps/ccmp_reg | 14 +++ instructionAPI/ISA_ps/cinc_csinc | 16 +++ instructionAPI/ISA_ps/cinv_csinv | 16 +++ instructionAPI/ISA_ps/clrex | 3 + instructionAPI/ISA_ps/cls_advsimd | 15 +++ instructionAPI/ISA_ps/cls_int | 12 +++ instructionAPI/ISA_ps/clz_advsimd | 15 +++ instructionAPI/ISA_ps/clz_int | 12 +++ instructionAPI/ISA_ps/cmeq_advsimd_reg | 21 ++++ instructionAPI/ISA_ps/cmeq_advsimd_zero | 24 +++++ instructionAPI/ISA_ps/cmge_advsimd_reg | 18 ++++ instructionAPI/ISA_ps/cmge_advsimd_zero | 24 +++++ instructionAPI/ISA_ps/cmgt_advsimd_reg | 18 ++++ instructionAPI/ISA_ps/cmgt_advsimd_zero | 24 +++++ instructionAPI/ISA_ps/cmhi_advsimd | 18 ++++ instructionAPI/ISA_ps/cmhs_advsimd | 18 ++++ instructionAPI/ISA_ps/cmle_advsimd | 24 +++++ instructionAPI/ISA_ps/cmlt_advsimd | 24 +++++ instructionAPI/ISA_ps/cmn_adds_addsub_ext | 26 +++++ instructionAPI/ISA_ps/cmn_adds_addsub_imm | 26 +++++ instructionAPI/ISA_ps/cmn_adds_addsub_shift | 22 ++++ instructionAPI/ISA_ps/cmp_subs_addsub_ext | 26 +++++ instructionAPI/ISA_ps/cmp_subs_addsub_imm | 26 +++++ instructionAPI/ISA_ps/cmp_subs_addsub_shift | 22 ++++ instructionAPI/ISA_ps/cmtst_advsimd | 21 ++++ instructionAPI/ISA_ps/cneg_csneg | 16 +++ instructionAPI/ISA_ps/cnt_advsimd | 11 ++ instructionAPI/ISA_ps/crc32 | 15 +++ instructionAPI/ISA_ps/crc32c | 15 +++ instructionAPI/ISA_ps/csel | 15 +++ instructionAPI/ISA_ps/cset_csinc | 16 +++ instructionAPI/ISA_ps/csetm_csinv | 16 +++ instructionAPI/ISA_ps/csinc | 17 +++ instructionAPI/ISA_ps/csinv | 17 +++ instructionAPI/ISA_ps/csneg | 16 +++ instructionAPI/ISA_ps/dc_sys | 7 ++ instructionAPI/ISA_ps/dcps1 | 3 + instructionAPI/ISA_ps/dcps2 | 3 + instructionAPI/ISA_ps/dcps3 | 3 + instructionAPI/ISA_ps/dmb | 12 +++ instructionAPI/ISA_ps/drps | 3 + instructionAPI/ISA_ps/dsb | 12 +++ instructionAPI/ISA_ps/dup_advsimd_elt | 11 ++ instructionAPI/ISA_ps/dup_advsimd_gen | 9 ++ instructionAPI/ISA_ps/encodingindex | 0 .../ISA_ps/enumerated-symbol-accounts | 0 instructionAPI/ISA_ps/eon | 20 ++++ instructionAPI/ISA_ps/eor_advsimd | 31 ++++++ instructionAPI/ISA_ps/eor_log_imm | 23 ++++ instructionAPI/ISA_ps/eor_log_shift | 20 ++++ instructionAPI/ISA_ps/eret | 3 + instructionAPI/ISA_ps/ext_advsimd | 8 ++ instructionAPI/ISA_ps/extr | 10 ++ instructionAPI/ISA_ps/fabd_advsimd | 17 +++ instructionAPI/ISA_ps/fabs_advsimd | 17 +++ instructionAPI/ISA_ps/fabs_float | 18 ++++ instructionAPI/ISA_ps/facge_advsimd | 27 +++++ instructionAPI/ISA_ps/facgt_advsimd | 27 +++++ instructionAPI/ISA_ps/fadd_advsimd | 21 ++++ instructionAPI/ISA_ps/fadd_float | 14 +++ instructionAPI/ISA_ps/faddp_advsimd_pair | 5 + instructionAPI/ISA_ps/faddp_advsimd_vec | 21 ++++ instructionAPI/ISA_ps/fccmp_float | 13 +++ instructionAPI/ISA_ps/fccmpe_float | 13 +++ instructionAPI/ISA_ps/fcmeq_advsimd_reg | 27 +++++ instructionAPI/ISA_ps/fcmeq_advsimd_zero | 25 +++++ instructionAPI/ISA_ps/fcmge_advsimd_reg | 27 +++++ instructionAPI/ISA_ps/fcmge_advsimd_zero | 25 +++++ instructionAPI/ISA_ps/fcmgt_advsimd_reg | 27 +++++ instructionAPI/ISA_ps/fcmgt_advsimd_zero | 25 +++++ instructionAPI/ISA_ps/fcmle_advsimd | 25 +++++ instructionAPI/ISA_ps/fcmlt_advsimd | 25 +++++ instructionAPI/ISA_ps/fcmp_float | 10 ++ instructionAPI/ISA_ps/fcmpe_float | 10 ++ instructionAPI/ISA_ps/fcsel_float | 8 ++ instructionAPI/ISA_ps/fcvt_float | 9 ++ instructionAPI/ISA_ps/fcvtas_advsimd | 12 +++ instructionAPI/ISA_ps/fcvtas_float | 26 +++++ instructionAPI/ISA_ps/fcvtau_advsimd | 12 +++ instructionAPI/ISA_ps/fcvtau_float | 26 +++++ instructionAPI/ISA_ps/fcvtl_advsimd | 10 ++ instructionAPI/ISA_ps/fcvtms_advsimd | 12 +++ instructionAPI/ISA_ps/fcvtms_float | 26 +++++ instructionAPI/ISA_ps/fcvtmu_advsimd | 12 +++ instructionAPI/ISA_ps/fcvtmu_float | 26 +++++ instructionAPI/ISA_ps/fcvtn_advsimd | 10 ++ instructionAPI/ISA_ps/fcvtns_advsimd | 12 +++ instructionAPI/ISA_ps/fcvtns_float | 26 +++++ instructionAPI/ISA_ps/fcvtnu_advsimd | 12 +++ instructionAPI/ISA_ps/fcvtnu_float | 26 +++++ instructionAPI/ISA_ps/fcvtps_advsimd | 12 +++ instructionAPI/ISA_ps/fcvtps_float | 26 +++++ instructionAPI/ISA_ps/fcvtpu_advsimd | 12 +++ instructionAPI/ISA_ps/fcvtpu_float | 26 +++++ instructionAPI/ISA_ps/fcvtxn_advsimd | 10 ++ instructionAPI/ISA_ps/fcvtzs_advsimd_fix | 12 +++ instructionAPI/ISA_ps/fcvtzs_advsimd_int | 12 +++ instructionAPI/ISA_ps/fcvtzs_float_fix | 18 ++++ instructionAPI/ISA_ps/fcvtzs_float_int | 26 +++++ instructionAPI/ISA_ps/fcvtzu_advsimd_fix | 12 +++ instructionAPI/ISA_ps/fcvtzu_advsimd_int | 12 +++ instructionAPI/ISA_ps/fcvtzu_float_fix | 18 ++++ instructionAPI/ISA_ps/fcvtzu_float_int | 26 +++++ instructionAPI/ISA_ps/fdiv_advsimd | 15 +++ instructionAPI/ISA_ps/fdiv_float | 10 ++ instructionAPI/ISA_ps/fmadd_float | 13 +++ instructionAPI/ISA_ps/fmax_advsimd | 26 +++++ instructionAPI/ISA_ps/fmax_float | 18 ++++ instructionAPI/ISA_ps/fmaxnm_advsimd | 26 +++++ instructionAPI/ISA_ps/fmaxnm_float | 18 ++++ instructionAPI/ISA_ps/fmaxnmp_advsimd_pair | 5 + instructionAPI/ISA_ps/fmaxnmp_advsimd_vec | 26 +++++ instructionAPI/ISA_ps/fmaxnmv_advsimd | 5 + instructionAPI/ISA_ps/fmaxp_advsimd_pair | 5 + instructionAPI/ISA_ps/fmaxp_advsimd_vec | 26 +++++ instructionAPI/ISA_ps/fmaxv_advsimd | 5 + instructionAPI/ISA_ps/fmin_advsimd | 26 +++++ instructionAPI/ISA_ps/fmin_float | 18 ++++ instructionAPI/ISA_ps/fminnm_advsimd | 26 +++++ instructionAPI/ISA_ps/fminnm_float | 18 ++++ instructionAPI/ISA_ps/fminnmp_advsimd_pair | 5 + instructionAPI/ISA_ps/fminnmp_advsimd_vec | 26 +++++ instructionAPI/ISA_ps/fminnmv_advsimd | 5 + instructionAPI/ISA_ps/fminp_advsimd_pair | 5 + instructionAPI/ISA_ps/fminp_advsimd_vec | 26 +++++ instructionAPI/ISA_ps/fminv_advsimd | 5 + instructionAPI/ISA_ps/fmla_advsimd_elt | 15 +++ instructionAPI/ISA_ps/fmla_advsimd_vec | 17 +++ instructionAPI/ISA_ps/fmls_advsimd_elt | 15 +++ instructionAPI/ISA_ps/fmls_advsimd_vec | 17 +++ instructionAPI/ISA_ps/fmov_advsimd | 23 ++++ instructionAPI/ISA_ps/fmov_float | 18 ++++ instructionAPI/ISA_ps/fmov_float_gen | 26 +++++ instructionAPI/ISA_ps/fmov_float_imm | 5 + instructionAPI/ISA_ps/fmsub_float | 13 +++ instructionAPI/ISA_ps/fmul_advsimd_elt | 18 ++++ instructionAPI/ISA_ps/fmul_advsimd_vec | 15 +++ instructionAPI/ISA_ps/fmul_float | 12 +++ instructionAPI/ISA_ps/fmulx_advsimd_elt | 18 ++++ instructionAPI/ISA_ps/fmulx_advsimd_vec | 14 +++ instructionAPI/ISA_ps/fneg_advsimd | 17 +++ instructionAPI/ISA_ps/fneg_float | 18 ++++ instructionAPI/ISA_ps/fnmadd_float | 13 +++ instructionAPI/ISA_ps/fnmsub_float | 13 +++ instructionAPI/ISA_ps/fnmul_float | 12 +++ instructionAPI/ISA_ps/fpsimdindex | 0 instructionAPI/ISA_ps/frecpe_advsimd | 12 +++ instructionAPI/ISA_ps/frecps_advsimd | 15 +++ instructionAPI/ISA_ps/frecpx_advsimd | 12 +++ instructionAPI/ISA_ps/frinta_advsimd | 12 +++ instructionAPI/ISA_ps/frinta_float | 10 ++ instructionAPI/ISA_ps/frinti_advsimd | 12 +++ instructionAPI/ISA_ps/frinti_float | 10 ++ instructionAPI/ISA_ps/frintm_advsimd | 12 +++ instructionAPI/ISA_ps/frintm_float | 10 ++ instructionAPI/ISA_ps/frintn_advsimd | 12 +++ instructionAPI/ISA_ps/frintn_float | 10 ++ instructionAPI/ISA_ps/frintp_advsimd | 12 +++ instructionAPI/ISA_ps/frintp_float | 10 ++ instructionAPI/ISA_ps/frintx_advsimd | 12 +++ instructionAPI/ISA_ps/frintx_float | 10 ++ instructionAPI/ISA_ps/frintz_advsimd | 12 +++ instructionAPI/ISA_ps/frintz_float | 10 ++ instructionAPI/ISA_ps/frsqrte_advsimd | 12 +++ instructionAPI/ISA_ps/frsqrts_advsimd | 15 +++ instructionAPI/ISA_ps/fsqrt_advsimd | 12 +++ instructionAPI/ISA_ps/fsqrt_float | 18 ++++ instructionAPI/ISA_ps/fsub_advsimd | 17 +++ instructionAPI/ISA_ps/fsub_float | 14 +++ instructionAPI/ISA_ps/hint | 48 +++++++++ instructionAPI/ISA_ps/hlt | 3 + instructionAPI/ISA_ps/hvc | 12 +++ instructionAPI/ISA_ps/ic_sys | 6 ++ instructionAPI/ISA_ps/index | 0 instructionAPI/ISA_ps/ins_advsimd_elt | 9 ++ instructionAPI/ISA_ps/ins_advsimd_gen | 9 ++ instructionAPI/ISA_ps/isb | 12 +++ instructionAPI/ISA_ps/ld1_advsimd_mult | 41 +++++++ instructionAPI/ISA_ps/ld1_advsimd_sngl | 52 +++++++++ instructionAPI/ISA_ps/ld1r_advsimd | 52 +++++++++ instructionAPI/ISA_ps/ld2_advsimd_mult | 41 +++++++ instructionAPI/ISA_ps/ld2_advsimd_sngl | 52 +++++++++ instructionAPI/ISA_ps/ld2r_advsimd | 52 +++++++++ instructionAPI/ISA_ps/ld3_advsimd_mult | 41 +++++++ instructionAPI/ISA_ps/ld3_advsimd_sngl | 52 +++++++++ instructionAPI/ISA_ps/ld3r_advsimd | 52 +++++++++ instructionAPI/ISA_ps/ld4_advsimd_mult | 41 +++++++ instructionAPI/ISA_ps/ld4_advsimd_sngl | 52 +++++++++ instructionAPI/ISA_ps/ld4r_advsimd | 52 +++++++++ instructionAPI/ISA_ps/ldar | 22 ++++ instructionAPI/ISA_ps/ldarb | 22 ++++ instructionAPI/ISA_ps/ldarh | 22 ++++ instructionAPI/ISA_ps/ldaxp | 94 ++++++++++++++++ instructionAPI/ISA_ps/ldaxr | 94 ++++++++++++++++ instructionAPI/ISA_ps/ldaxrb | 94 ++++++++++++++++ instructionAPI/ISA_ps/ldaxrh | 94 ++++++++++++++++ instructionAPI/ISA_ps/ldnp_fpsimd | 53 +++++++++ instructionAPI/ISA_ps/ldnp_gen | 59 ++++++++++ instructionAPI/ISA_ps/ldp_fpsimd | 53 +++++++++ instructionAPI/ISA_ps/ldp_gen | 75 +++++++++++++ instructionAPI/ISA_ps/ldpsw | 75 +++++++++++++ instructionAPI/ISA_ps/ldr_imm_fpsimd | 38 +++++++ instructionAPI/ISA_ps/ldr_imm_gen | 60 +++++++++++ instructionAPI/ISA_ps/ldr_lit_fpsimd | 9 ++ instructionAPI/ISA_ps/ldr_lit_gen | 18 ++++ instructionAPI/ISA_ps/ldr_reg_fpsimd | 39 +++++++ instructionAPI/ISA_ps/ldr_reg_gen | 61 +++++++++++ instructionAPI/ISA_ps/ldrb_imm | 60 +++++++++++ instructionAPI/ISA_ps/ldrb_reg | 61 +++++++++++ instructionAPI/ISA_ps/ldrh_imm | 60 +++++++++++ instructionAPI/ISA_ps/ldrh_reg | 61 +++++++++++ instructionAPI/ISA_ps/ldrsb_imm | 60 +++++++++++ instructionAPI/ISA_ps/ldrsb_reg | 61 +++++++++++ instructionAPI/ISA_ps/ldrsh_imm | 60 +++++++++++ instructionAPI/ISA_ps/ldrsh_reg | 61 +++++++++++ instructionAPI/ISA_ps/ldrsw_imm | 60 +++++++++++ instructionAPI/ISA_ps/ldrsw_lit | 18 ++++ instructionAPI/ISA_ps/ldrsw_reg | 61 +++++++++++ instructionAPI/ISA_ps/ldtr | 60 +++++++++++ instructionAPI/ISA_ps/ldtrb | 60 +++++++++++ instructionAPI/ISA_ps/ldtrh | 60 +++++++++++ instructionAPI/ISA_ps/ldtrsb | 60 +++++++++++ instructionAPI/ISA_ps/ldtrsh | 60 +++++++++++ instructionAPI/ISA_ps/ldtrsw | 60 +++++++++++ instructionAPI/ISA_ps/ldur_fpsimd | 38 +++++++ instructionAPI/ISA_ps/ldur_gen | 60 +++++++++++ instructionAPI/ISA_ps/ldurb | 60 +++++++++++ instructionAPI/ISA_ps/ldurh | 60 +++++++++++ instructionAPI/ISA_ps/ldursb | 60 +++++++++++ instructionAPI/ISA_ps/ldursh | 60 +++++++++++ instructionAPI/ISA_ps/ldursw | 60 +++++++++++ instructionAPI/ISA_ps/ldxp | 94 ++++++++++++++++ instructionAPI/ISA_ps/ldxr | 94 ++++++++++++++++ instructionAPI/ISA_ps/ldxrb | 94 ++++++++++++++++ instructionAPI/ISA_ps/ldxrh | 94 ++++++++++++++++ instructionAPI/ISA_ps/lsl_lslv | 7 ++ instructionAPI/ISA_ps/lsl_ubfm | 13 +++ instructionAPI/ISA_ps/lslv | 7 ++ instructionAPI/ISA_ps/lsr_lsrv | 7 ++ instructionAPI/ISA_ps/lsr_ubfm | 13 +++ instructionAPI/ISA_ps/lsrv | 7 ++ instructionAPI/ISA_ps/madd | 15 +++ instructionAPI/ISA_ps/mla_advsimd_elt | 21 ++++ instructionAPI/ISA_ps/mla_advsimd_vec | 22 ++++ instructionAPI/ISA_ps/mls_advsimd_elt | 21 ++++ instructionAPI/ISA_ps/mls_advsimd_vec | 22 ++++ instructionAPI/ISA_ps/mneg_msub | 15 +++ instructionAPI/ISA_ps/mov_add_addsub_imm | 26 +++++ instructionAPI/ISA_ps/mov_dup_advsimd_elt | 11 ++ instructionAPI/ISA_ps/mov_ins_advsimd_elt | 9 ++ instructionAPI/ISA_ps/mov_ins_advsimd_gen | 9 ++ instructionAPI/ISA_ps/mov_movn | 15 +++ instructionAPI/ISA_ps/mov_movz | 15 +++ instructionAPI/ISA_ps/mov_orr_advsimd_reg | 18 ++++ instructionAPI/ISA_ps/mov_orr_log_imm | 23 ++++ instructionAPI/ISA_ps/mov_orr_log_shift | 20 ++++ instructionAPI/ISA_ps/mov_umov_advsimd | 6 ++ instructionAPI/ISA_ps/movi_advsimd | 23 ++++ instructionAPI/ISA_ps/movk | 15 +++ instructionAPI/ISA_ps/movn | 15 +++ instructionAPI/ISA_ps/movz | 15 +++ instructionAPI/ISA_ps/mrs | 7 ++ instructionAPI/ISA_ps/msr_imm | 18 ++++ instructionAPI/ISA_ps/msr_reg | 7 ++ instructionAPI/ISA_ps/msub | 15 +++ instructionAPI/ISA_ps/mul_advsimd_elt | 17 +++ instructionAPI/ISA_ps/mul_advsimd_vec | 21 ++++ instructionAPI/ISA_ps/mul_madd | 15 +++ instructionAPI/ISA_ps/mvn_not_advsimd | 12 +++ instructionAPI/ISA_ps/mvn_orn_log_shift | 20 ++++ instructionAPI/ISA_ps/mvni_advsimd | 23 ++++ instructionAPI/ISA_ps/neg_advsimd | 17 +++ instructionAPI/ISA_ps/neg_sub_addsub_shift | 22 ++++ instructionAPI/ISA_ps/negs_subs_addsub_shift | 22 ++++ instructionAPI/ISA_ps/ngc_sbc | 18 ++++ instructionAPI/ISA_ps/ngcs_sbcs | 18 ++++ instructionAPI/ISA_ps/nop_hint | 48 +++++++++ instructionAPI/ISA_ps/not_advsimd | 12 +++ instructionAPI/ISA_ps/orn_advsimd | 18 ++++ instructionAPI/ISA_ps/orn_log_shift | 20 ++++ instructionAPI/ISA_ps/orr_advsimd_imm | 23 ++++ instructionAPI/ISA_ps/orr_advsimd_reg | 18 ++++ instructionAPI/ISA_ps/orr_log_imm | 23 ++++ instructionAPI/ISA_ps/orr_log_shift | 20 ++++ instructionAPI/ISA_ps/permindex | 0 instructionAPI/ISA_ps/pmul_advsimd | 21 ++++ instructionAPI/ISA_ps/pmull_advsimd | 15 +++ instructionAPI/ISA_ps/prfm_imm | 60 +++++++++++ instructionAPI/ISA_ps/prfm_lit | 18 ++++ instructionAPI/ISA_ps/prfm_reg | 61 +++++++++++ instructionAPI/ISA_ps/prfum | 60 +++++++++++ instructionAPI/ISA_ps/raddhn_advsimd | 23 ++++ instructionAPI/ISA_ps/rbit_advsimd | 15 +++ instructionAPI/ISA_ps/rbit_int | 28 +++++ instructionAPI/ISA_ps/ret | 6 ++ instructionAPI/ISA_ps/rev | 28 +++++ instructionAPI/ISA_ps/rev16_advsimd | 11 ++ instructionAPI/ISA_ps/rev16_int | 28 +++++ instructionAPI/ISA_ps/rev32_advsimd | 11 ++ instructionAPI/ISA_ps/rev32_int | 28 +++++ instructionAPI/ISA_ps/rev64_advsimd | 11 ++ instructionAPI/ISA_ps/ror_extr | 10 ++ instructionAPI/ISA_ps/ror_rorv | 7 ++ instructionAPI/ISA_ps/rorv | 7 ++ instructionAPI/ISA_ps/rshrn_advsimd | 13 +++ instructionAPI/ISA_ps/rsubhn_advsimd | 23 ++++ instructionAPI/ISA_ps/saba_advsimd | 17 +++ instructionAPI/ISA_ps/sabal_advsimd | 17 +++ instructionAPI/ISA_ps/sabd_advsimd | 17 +++ instructionAPI/ISA_ps/sabdl_advsimd | 17 +++ instructionAPI/ISA_ps/sadalp_advsimd | 18 ++++ instructionAPI/ISA_ps/saddl_advsimd | 21 ++++ instructionAPI/ISA_ps/saddlp_advsimd | 18 ++++ instructionAPI/ISA_ps/saddlv_advsimd | 11 ++ instructionAPI/ISA_ps/saddw_advsimd | 21 ++++ instructionAPI/ISA_ps/sbc | 18 ++++ instructionAPI/ISA_ps/sbcs | 18 ++++ instructionAPI/ISA_ps/sbfiz_sbfm | 13 +++ instructionAPI/ISA_ps/sbfm | 13 +++ instructionAPI/ISA_ps/sbfx_sbfm | 13 +++ instructionAPI/ISA_ps/scvtf_advsimd_fix | 12 +++ instructionAPI/ISA_ps/scvtf_advsimd_int | 13 +++ instructionAPI/ISA_ps/scvtf_float_fix | 18 ++++ instructionAPI/ISA_ps/scvtf_float_int | 26 +++++ instructionAPI/ISA_ps/sdiv | 13 +++ instructionAPI/ISA_ps/sev_hint | 48 +++++++++ instructionAPI/ISA_ps/sevl_hint | 48 +++++++++ instructionAPI/ISA_ps/sha1c_advsimd | 15 +++ instructionAPI/ISA_ps/sha1h_advsimd | 6 ++ instructionAPI/ISA_ps/sha1m_advsimd | 15 +++ instructionAPI/ISA_ps/sha1p_advsimd | 15 +++ instructionAPI/ISA_ps/sha1su0_advsimd | 12 +++ instructionAPI/ISA_ps/sha1su1_advsimd | 13 +++ instructionAPI/ISA_ps/sha256h2_advsimd | 11 ++ instructionAPI/ISA_ps/sha256h_advsimd | 11 ++ instructionAPI/ISA_ps/sha256su0_advsimd | 15 +++ instructionAPI/ISA_ps/sha256su1_advsimd | 27 +++++ instructionAPI/ISA_ps/shadd_advsimd | 17 +++ instructionAPI/ISA_ps/shared_pseudocode | 0 instructionAPI/ISA_ps/shl_advsimd | 10 ++ instructionAPI/ISA_ps/shll_advsimd | 12 +++ instructionAPI/ISA_ps/shrn_advsimd | 13 +++ instructionAPI/ISA_ps/shsub_advsimd | 17 +++ instructionAPI/ISA_ps/sli_advsimd | 13 +++ instructionAPI/ISA_ps/smaddl | 15 +++ instructionAPI/ISA_ps/smax_advsimd | 17 +++ instructionAPI/ISA_ps/smaxp_advsimd | 18 ++++ instructionAPI/ISA_ps/smaxv_advsimd | 13 +++ instructionAPI/ISA_ps/smc | 13 +++ instructionAPI/ISA_ps/smin_advsimd | 17 +++ instructionAPI/ISA_ps/sminp_advsimd | 18 ++++ instructionAPI/ISA_ps/sminv_advsimd | 13 +++ instructionAPI/ISA_ps/smlal_advsimd_elt | 22 ++++ instructionAPI/ISA_ps/smlal_advsimd_vec | 24 +++++ instructionAPI/ISA_ps/smlsl_advsimd_elt | 22 ++++ instructionAPI/ISA_ps/smlsl_advsimd_vec | 24 +++++ instructionAPI/ISA_ps/smnegl_smsubl | 15 +++ instructionAPI/ISA_ps/smov_advsimd | 6 ++ instructionAPI/ISA_ps/smsubl | 15 +++ instructionAPI/ISA_ps/smulh | 10 ++ instructionAPI/ISA_ps/smull_advsimd_elt | 17 +++ instructionAPI/ISA_ps/smull_advsimd_vec | 15 +++ instructionAPI/ISA_ps/smull_smaddl | 15 +++ instructionAPI/ISA_ps/sqabs_advsimd | 19 ++++ instructionAPI/ISA_ps/sqadd_advsimd | 19 ++++ instructionAPI/ISA_ps/sqdmlal_advsimd_elt | 27 +++++ instructionAPI/ISA_ps/sqdmlal_advsimd_vec | 27 +++++ instructionAPI/ISA_ps/sqdmlsl_advsimd_elt | 27 +++++ instructionAPI/ISA_ps/sqdmlsl_advsimd_vec | 27 +++++ instructionAPI/ISA_ps/sqdmulh_advsimd_elt | 21 ++++ instructionAPI/ISA_ps/sqdmulh_advsimd_vec | 20 ++++ instructionAPI/ISA_ps/sqdmull_advsimd_elt | 20 ++++ instructionAPI/ISA_ps/sqdmull_advsimd_vec | 19 ++++ instructionAPI/ISA_ps/sqneg_advsimd | 19 ++++ instructionAPI/ISA_ps/sqrdmulh_advsimd_elt | 21 ++++ instructionAPI/ISA_ps/sqrdmulh_advsimd_vec | 20 ++++ instructionAPI/ISA_ps/sqrshl_advsimd | 26 +++++ instructionAPI/ISA_ps/sqrshrn_advsimd | 15 +++ instructionAPI/ISA_ps/sqrshrun_advsimd | 15 +++ instructionAPI/ISA_ps/sqshl_advsimd_imm | 14 +++ instructionAPI/ISA_ps/sqshl_advsimd_reg | 26 +++++ instructionAPI/ISA_ps/sqshlu_advsimd | 14 +++ instructionAPI/ISA_ps/sqshrn_advsimd | 15 +++ instructionAPI/ISA_ps/sqshrun_advsimd | 15 +++ instructionAPI/ISA_ps/sqsub_advsimd | 19 ++++ instructionAPI/ISA_ps/sqxtn_advsimd | 14 +++ instructionAPI/ISA_ps/sqxtun_advsimd | 14 +++ instructionAPI/ISA_ps/srhadd_advsimd | 15 +++ instructionAPI/ISA_ps/sri_advsimd | 13 +++ instructionAPI/ISA_ps/srshl_advsimd | 26 +++++ instructionAPI/ISA_ps/srshr_advsimd | 15 +++ instructionAPI/ISA_ps/srsra_advsimd | 15 +++ instructionAPI/ISA_ps/sshl_advsimd | 26 +++++ instructionAPI/ISA_ps/sshll_advsimd | 12 +++ instructionAPI/ISA_ps/sshr_advsimd | 15 +++ instructionAPI/ISA_ps/ssra_advsimd | 15 +++ instructionAPI/ISA_ps/ssubl_advsimd | 21 ++++ instructionAPI/ISA_ps/ssubw_advsimd | 21 ++++ instructionAPI/ISA_ps/st1_advsimd_mult | 41 +++++++ instructionAPI/ISA_ps/st1_advsimd_sngl | 52 +++++++++ instructionAPI/ISA_ps/st2_advsimd_mult | 41 +++++++ instructionAPI/ISA_ps/st2_advsimd_sngl | 52 +++++++++ instructionAPI/ISA_ps/st3_advsimd_mult | 41 +++++++ instructionAPI/ISA_ps/st3_advsimd_sngl | 52 +++++++++ instructionAPI/ISA_ps/st4_advsimd_mult | 41 +++++++ instructionAPI/ISA_ps/st4_advsimd_sngl | 52 +++++++++ instructionAPI/ISA_ps/stlr | 22 ++++ instructionAPI/ISA_ps/stlrb | 22 ++++ instructionAPI/ISA_ps/stlrh | 22 ++++ instructionAPI/ISA_ps/stlxp | 94 ++++++++++++++++ instructionAPI/ISA_ps/stlxr | 94 ++++++++++++++++ instructionAPI/ISA_ps/stlxrb | 94 ++++++++++++++++ instructionAPI/ISA_ps/stlxrh | 94 ++++++++++++++++ instructionAPI/ISA_ps/stnp_fpsimd | 53 +++++++++ instructionAPI/ISA_ps/stnp_gen | 59 ++++++++++ instructionAPI/ISA_ps/stp_fpsimd | 53 +++++++++ instructionAPI/ISA_ps/stp_gen | 76 +++++++++++++ instructionAPI/ISA_ps/str_imm_fpsimd | 38 +++++++ instructionAPI/ISA_ps/str_imm_gen | 60 +++++++++++ instructionAPI/ISA_ps/str_reg_fpsimd | 39 +++++++ instructionAPI/ISA_ps/str_reg_gen | 61 +++++++++++ instructionAPI/ISA_ps/strb_imm | 60 +++++++++++ instructionAPI/ISA_ps/strb_reg | 61 +++++++++++ instructionAPI/ISA_ps/strh_imm | 60 +++++++++++ instructionAPI/ISA_ps/strh_reg | 61 +++++++++++ instructionAPI/ISA_ps/sttr | 60 +++++++++++ instructionAPI/ISA_ps/sttrb | 60 +++++++++++ instructionAPI/ISA_ps/sttrh | 60 +++++++++++ instructionAPI/ISA_ps/stur_fpsimd | 38 +++++++ instructionAPI/ISA_ps/stur_gen | 60 +++++++++++ instructionAPI/ISA_ps/sturb | 60 +++++++++++ instructionAPI/ISA_ps/sturh | 60 +++++++++++ instructionAPI/ISA_ps/stxp | 94 ++++++++++++++++ instructionAPI/ISA_ps/stxr | 94 ++++++++++++++++ instructionAPI/ISA_ps/stxrb | 94 ++++++++++++++++ instructionAPI/ISA_ps/stxrh | 94 ++++++++++++++++ instructionAPI/ISA_ps/sub_addsub_ext | 26 +++++ instructionAPI/ISA_ps/sub_addsub_imm | 26 +++++ instructionAPI/ISA_ps/sub_addsub_shift | 22 ++++ instructionAPI/ISA_ps/sub_advsimd | 19 ++++ instructionAPI/ISA_ps/subhn_advsimd | 23 ++++ instructionAPI/ISA_ps/subs_addsub_ext | 26 +++++ instructionAPI/ISA_ps/subs_addsub_imm | 26 +++++ instructionAPI/ISA_ps/subs_addsub_shift | 22 ++++ instructionAPI/ISA_ps/suqadd_advsimd | 17 +++ instructionAPI/ISA_ps/svc | 3 + instructionAPI/ISA_ps/sxtb_sbfm | 13 +++ instructionAPI/ISA_ps/sxth_sbfm | 13 +++ instructionAPI/ISA_ps/sxtl_sshll_advsimd | 12 +++ instructionAPI/ISA_ps/sxtw_sbfm | 13 +++ instructionAPI/ISA_ps/sys | 6 ++ instructionAPI/ISA_ps/sysl | 7 ++ instructionAPI/ISA_ps/tbl_advsimd | 22 ++++ instructionAPI/ISA_ps/tbnz | 7 ++ instructionAPI/ISA_ps/tbx_advsimd | 22 ++++ instructionAPI/ISA_ps/tbz | 7 ++ instructionAPI/ISA_ps/temp.py | 12 +++ instructionAPI/ISA_ps/tlbi_sys | 7 ++ instructionAPI/ISA_ps/trn1_advsimd | 13 +++ instructionAPI/ISA_ps/trn2_advsimd | 13 +++ instructionAPI/ISA_ps/tst_ands_log_imm | 23 ++++ instructionAPI/ISA_ps/tst_ands_log_shift | 21 ++++ instructionAPI/ISA_ps/uaba_advsimd | 17 +++ instructionAPI/ISA_ps/uabal_advsimd | 17 +++ instructionAPI/ISA_ps/uabd_advsimd | 17 +++ instructionAPI/ISA_ps/uabdl_advsimd | 17 +++ instructionAPI/ISA_ps/uadalp_advsimd | 18 ++++ instructionAPI/ISA_ps/uaddl_advsimd | 21 ++++ instructionAPI/ISA_ps/uaddlp_advsimd | 18 ++++ instructionAPI/ISA_ps/uaddlv_advsimd | 11 ++ instructionAPI/ISA_ps/uaddw_advsimd | 21 ++++ instructionAPI/ISA_ps/ubfiz_ubfm | 13 +++ instructionAPI/ISA_ps/ubfm | 13 +++ instructionAPI/ISA_ps/ubfx_ubfm | 13 +++ instructionAPI/ISA_ps/ucvtf_advsimd_fix | 12 +++ instructionAPI/ISA_ps/ucvtf_advsimd_int | 13 +++ instructionAPI/ISA_ps/ucvtf_float_fix | 18 ++++ instructionAPI/ISA_ps/ucvtf_float_int | 26 +++++ instructionAPI/ISA_ps/udiv | 13 +++ instructionAPI/ISA_ps/uhadd_advsimd | 17 +++ instructionAPI/ISA_ps/uhsub_advsimd | 17 +++ instructionAPI/ISA_ps/umaddl | 15 +++ instructionAPI/ISA_ps/umax_advsimd | 17 +++ instructionAPI/ISA_ps/umaxp_advsimd | 18 ++++ instructionAPI/ISA_ps/umaxv_advsimd | 13 +++ instructionAPI/ISA_ps/umin_advsimd | 17 +++ instructionAPI/ISA_ps/uminp_advsimd | 18 ++++ instructionAPI/ISA_ps/uminv_advsimd | 13 +++ instructionAPI/ISA_ps/umlal_advsimd_elt | 22 ++++ instructionAPI/ISA_ps/umlal_advsimd_vec | 24 +++++ instructionAPI/ISA_ps/umlsl_advsimd_elt | 22 ++++ instructionAPI/ISA_ps/umlsl_advsimd_vec | 24 +++++ instructionAPI/ISA_ps/umnegl_umsubl | 15 +++ instructionAPI/ISA_ps/umov_advsimd | 6 ++ instructionAPI/ISA_ps/umsubl | 15 +++ instructionAPI/ISA_ps/umulh | 10 ++ instructionAPI/ISA_ps/umull_advsimd_elt | 17 +++ instructionAPI/ISA_ps/umull_advsimd_vec | 15 +++ instructionAPI/ISA_ps/umull_umaddl | 15 +++ instructionAPI/ISA_ps/uqadd_advsimd | 19 ++++ instructionAPI/ISA_ps/uqrshl_advsimd | 26 +++++ instructionAPI/ISA_ps/uqrshrn_advsimd | 15 +++ instructionAPI/ISA_ps/uqshl_advsimd_imm | 14 +++ instructionAPI/ISA_ps/uqshl_advsimd_reg | 26 +++++ instructionAPI/ISA_ps/uqshrn_advsimd | 15 +++ instructionAPI/ISA_ps/uqsub_advsimd | 19 ++++ instructionAPI/ISA_ps/uqxtn_advsimd | 14 +++ instructionAPI/ISA_ps/urecpe_advsimd | 12 +++ instructionAPI/ISA_ps/urhadd_advsimd | 15 +++ instructionAPI/ISA_ps/urshl_advsimd | 26 +++++ instructionAPI/ISA_ps/urshr_advsimd | 15 +++ instructionAPI/ISA_ps/ursqrte_advsimd | 12 +++ instructionAPI/ISA_ps/ursra_advsimd | 15 +++ instructionAPI/ISA_ps/ushl_advsimd | 26 +++++ instructionAPI/ISA_ps/ushll_advsimd | 12 +++ instructionAPI/ISA_ps/ushr_advsimd | 15 +++ instructionAPI/ISA_ps/usqadd_advsimd | 17 +++ instructionAPI/ISA_ps/usra_advsimd | 15 +++ instructionAPI/ISA_ps/usubl_advsimd | 21 ++++ instructionAPI/ISA_ps/usubw_advsimd | 21 ++++ instructionAPI/ISA_ps/uxtb_ubfm | 13 +++ instructionAPI/ISA_ps/uxth_ubfm | 13 +++ instructionAPI/ISA_ps/uxtl_ushll_advsimd | 12 +++ instructionAPI/ISA_ps/uzp1_advsimd | 13 +++ instructionAPI/ISA_ps/uzp2_advsimd | 13 +++ instructionAPI/ISA_ps/wfe_hint | 48 +++++++++ instructionAPI/ISA_ps/wfi_hint | 48 +++++++++ instructionAPI/ISA_ps/xtn_advsimd | 11 ++ instructionAPI/ISA_ps/yield_hint | 48 +++++++++ instructionAPI/ISA_ps/zip1_advsimd | 15 +++ instructionAPI/ISA_ps/zip2_advsimd | 15 +++ .../aarch64_pseudocode_extractor.py | 101 ++++++++++++++++++ 582 files changed, 13788 insertions(+) create mode 100644 instructionAPI/ISA_ps/abs_advsimd create mode 100644 instructionAPI/ISA_ps/adc create mode 100644 instructionAPI/ISA_ps/adcs create mode 100644 instructionAPI/ISA_ps/add_addsub_ext create mode 100644 instructionAPI/ISA_ps/add_addsub_imm create mode 100644 instructionAPI/ISA_ps/add_addsub_shift create mode 100644 instructionAPI/ISA_ps/add_advsimd create mode 100644 instructionAPI/ISA_ps/addhn_advsimd create mode 100644 instructionAPI/ISA_ps/addp_advsimd_pair create mode 100644 instructionAPI/ISA_ps/addp_advsimd_vec create mode 100644 instructionAPI/ISA_ps/adds_addsub_ext create mode 100644 instructionAPI/ISA_ps/adds_addsub_imm create mode 100644 instructionAPI/ISA_ps/adds_addsub_shift create mode 100644 instructionAPI/ISA_ps/addv_advsimd create mode 100644 instructionAPI/ISA_ps/adr create mode 100644 instructionAPI/ISA_ps/adrp create mode 100644 instructionAPI/ISA_ps/aesd_advsimd create mode 100644 instructionAPI/ISA_ps/aese_advsimd create mode 100644 instructionAPI/ISA_ps/aesimc_advsimd create mode 100644 instructionAPI/ISA_ps/aesmc_advsimd create mode 100644 instructionAPI/ISA_ps/and_advsimd create mode 100644 instructionAPI/ISA_ps/and_log_imm create mode 100644 instructionAPI/ISA_ps/and_log_shift create mode 100644 instructionAPI/ISA_ps/ands_log_imm create mode 100644 instructionAPI/ISA_ps/ands_log_shift create mode 100644 instructionAPI/ISA_ps/asr_asrv create mode 100644 instructionAPI/ISA_ps/asr_sbfm create mode 100644 instructionAPI/ISA_ps/asrv create mode 100644 instructionAPI/ISA_ps/at_sys create mode 100644 instructionAPI/ISA_ps/b_cond create mode 100644 instructionAPI/ISA_ps/b_uncond create mode 100644 instructionAPI/ISA_ps/bfi_bfm create mode 100644 instructionAPI/ISA_ps/bfm create mode 100644 instructionAPI/ISA_ps/bfxil_bfm create mode 100644 instructionAPI/ISA_ps/bic_advsimd_imm create mode 100644 instructionAPI/ISA_ps/bic_advsimd_reg create mode 100644 instructionAPI/ISA_ps/bic_log_shift create mode 100644 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instructionAPI/ISA_ps/clz_int create mode 100644 instructionAPI/ISA_ps/cmeq_advsimd_reg create mode 100644 instructionAPI/ISA_ps/cmeq_advsimd_zero create mode 100644 instructionAPI/ISA_ps/cmge_advsimd_reg create mode 100644 instructionAPI/ISA_ps/cmge_advsimd_zero create mode 100644 instructionAPI/ISA_ps/cmgt_advsimd_reg create mode 100644 instructionAPI/ISA_ps/cmgt_advsimd_zero create mode 100644 instructionAPI/ISA_ps/cmhi_advsimd create mode 100644 instructionAPI/ISA_ps/cmhs_advsimd create mode 100644 instructionAPI/ISA_ps/cmle_advsimd create mode 100644 instructionAPI/ISA_ps/cmlt_advsimd create mode 100644 instructionAPI/ISA_ps/cmn_adds_addsub_ext create mode 100644 instructionAPI/ISA_ps/cmn_adds_addsub_imm create mode 100644 instructionAPI/ISA_ps/cmn_adds_addsub_shift create mode 100644 instructionAPI/ISA_ps/cmp_subs_addsub_ext create mode 100644 instructionAPI/ISA_ps/cmp_subs_addsub_imm create mode 100644 instructionAPI/ISA_ps/cmp_subs_addsub_shift create mode 100644 instructionAPI/ISA_ps/cmtst_advsimd create mode 100644 instructionAPI/ISA_ps/cneg_csneg create mode 100644 instructionAPI/ISA_ps/cnt_advsimd create mode 100644 instructionAPI/ISA_ps/crc32 create mode 100644 instructionAPI/ISA_ps/crc32c create mode 100644 instructionAPI/ISA_ps/csel create mode 100644 instructionAPI/ISA_ps/cset_csinc create mode 100644 instructionAPI/ISA_ps/csetm_csinv create mode 100644 instructionAPI/ISA_ps/csinc create mode 100644 instructionAPI/ISA_ps/csinv create mode 100644 instructionAPI/ISA_ps/csneg create mode 100644 instructionAPI/ISA_ps/dc_sys create mode 100644 instructionAPI/ISA_ps/dcps1 create mode 100644 instructionAPI/ISA_ps/dcps2 create mode 100644 instructionAPI/ISA_ps/dcps3 create mode 100644 instructionAPI/ISA_ps/dmb create mode 100644 instructionAPI/ISA_ps/drps create mode 100644 instructionAPI/ISA_ps/dsb create mode 100644 instructionAPI/ISA_ps/dup_advsimd_elt create mode 100644 instructionAPI/ISA_ps/dup_advsimd_gen create mode 100644 instructionAPI/ISA_ps/encodingindex create mode 100644 instructionAPI/ISA_ps/enumerated-symbol-accounts create mode 100644 instructionAPI/ISA_ps/eon create mode 100644 instructionAPI/ISA_ps/eor_advsimd create mode 100644 instructionAPI/ISA_ps/eor_log_imm create mode 100644 instructionAPI/ISA_ps/eor_log_shift create mode 100644 instructionAPI/ISA_ps/eret create mode 100644 instructionAPI/ISA_ps/ext_advsimd create mode 100644 instructionAPI/ISA_ps/extr create mode 100644 instructionAPI/ISA_ps/fabd_advsimd create mode 100644 instructionAPI/ISA_ps/fabs_advsimd create mode 100644 instructionAPI/ISA_ps/fabs_float create mode 100644 instructionAPI/ISA_ps/facge_advsimd create mode 100644 instructionAPI/ISA_ps/facgt_advsimd create mode 100644 instructionAPI/ISA_ps/fadd_advsimd create mode 100644 instructionAPI/ISA_ps/fadd_float create mode 100644 instructionAPI/ISA_ps/faddp_advsimd_pair create mode 100644 instructionAPI/ISA_ps/faddp_advsimd_vec create mode 100644 instructionAPI/ISA_ps/fccmp_float create mode 100644 instructionAPI/ISA_ps/fccmpe_float create mode 100644 instructionAPI/ISA_ps/fcmeq_advsimd_reg create mode 100644 instructionAPI/ISA_ps/fcmeq_advsimd_zero create mode 100644 instructionAPI/ISA_ps/fcmge_advsimd_reg create mode 100644 instructionAPI/ISA_ps/fcmge_advsimd_zero create mode 100644 instructionAPI/ISA_ps/fcmgt_advsimd_reg create mode 100644 instructionAPI/ISA_ps/fcmgt_advsimd_zero create mode 100644 instructionAPI/ISA_ps/fcmle_advsimd create mode 100644 instructionAPI/ISA_ps/fcmlt_advsimd create mode 100644 instructionAPI/ISA_ps/fcmp_float create mode 100644 instructionAPI/ISA_ps/fcmpe_float create mode 100644 instructionAPI/ISA_ps/fcsel_float create mode 100644 instructionAPI/ISA_ps/fcvt_float create mode 100644 instructionAPI/ISA_ps/fcvtas_advsimd create mode 100644 instructionAPI/ISA_ps/fcvtas_float create mode 100644 instructionAPI/ISA_ps/fcvtau_advsimd create mode 100644 instructionAPI/ISA_ps/fcvtau_float create mode 100644 instructionAPI/ISA_ps/fcvtl_advsimd create mode 100644 instructionAPI/ISA_ps/fcvtms_advsimd create mode 100644 instructionAPI/ISA_ps/fcvtms_float create mode 100644 instructionAPI/ISA_ps/fcvtmu_advsimd create mode 100644 instructionAPI/ISA_ps/fcvtmu_float create mode 100644 instructionAPI/ISA_ps/fcvtn_advsimd create mode 100644 instructionAPI/ISA_ps/fcvtns_advsimd create mode 100644 instructionAPI/ISA_ps/fcvtns_float create mode 100644 instructionAPI/ISA_ps/fcvtnu_advsimd create mode 100644 instructionAPI/ISA_ps/fcvtnu_float create mode 100644 instructionAPI/ISA_ps/fcvtps_advsimd create mode 100644 instructionAPI/ISA_ps/fcvtps_float create mode 100644 instructionAPI/ISA_ps/fcvtpu_advsimd create mode 100644 instructionAPI/ISA_ps/fcvtpu_float create mode 100644 instructionAPI/ISA_ps/fcvtxn_advsimd create mode 100644 instructionAPI/ISA_ps/fcvtzs_advsimd_fix create mode 100644 instructionAPI/ISA_ps/fcvtzs_advsimd_int create mode 100644 instructionAPI/ISA_ps/fcvtzs_float_fix create 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instructionAPI/ISA_ps/fmaxv_advsimd create mode 100644 instructionAPI/ISA_ps/fmin_advsimd create mode 100644 instructionAPI/ISA_ps/fmin_float create mode 100644 instructionAPI/ISA_ps/fminnm_advsimd create mode 100644 instructionAPI/ISA_ps/fminnm_float create mode 100644 instructionAPI/ISA_ps/fminnmp_advsimd_pair create mode 100644 instructionAPI/ISA_ps/fminnmp_advsimd_vec create mode 100644 instructionAPI/ISA_ps/fminnmv_advsimd create mode 100644 instructionAPI/ISA_ps/fminp_advsimd_pair create mode 100644 instructionAPI/ISA_ps/fminp_advsimd_vec create mode 100644 instructionAPI/ISA_ps/fminv_advsimd create mode 100644 instructionAPI/ISA_ps/fmla_advsimd_elt create mode 100644 instructionAPI/ISA_ps/fmla_advsimd_vec create mode 100644 instructionAPI/ISA_ps/fmls_advsimd_elt create mode 100644 instructionAPI/ISA_ps/fmls_advsimd_vec create mode 100644 instructionAPI/ISA_ps/fmov_advsimd create mode 100644 instructionAPI/ISA_ps/fmov_float create mode 100644 instructionAPI/ISA_ps/fmov_float_gen create mode 100644 instructionAPI/ISA_ps/fmov_float_imm create mode 100644 instructionAPI/ISA_ps/fmsub_float create mode 100644 instructionAPI/ISA_ps/fmul_advsimd_elt create mode 100644 instructionAPI/ISA_ps/fmul_advsimd_vec create mode 100644 instructionAPI/ISA_ps/fmul_float create mode 100644 instructionAPI/ISA_ps/fmulx_advsimd_elt create mode 100644 instructionAPI/ISA_ps/fmulx_advsimd_vec create mode 100644 instructionAPI/ISA_ps/fneg_advsimd create mode 100644 instructionAPI/ISA_ps/fneg_float create mode 100644 instructionAPI/ISA_ps/fnmadd_float create mode 100644 instructionAPI/ISA_ps/fnmsub_float create mode 100644 instructionAPI/ISA_ps/fnmul_float create mode 100644 instructionAPI/ISA_ps/fpsimdindex create mode 100644 instructionAPI/ISA_ps/frecpe_advsimd create mode 100644 instructionAPI/ISA_ps/frecps_advsimd create mode 100644 instructionAPI/ISA_ps/frecpx_advsimd create mode 100644 instructionAPI/ISA_ps/frinta_advsimd create mode 100644 instructionAPI/ISA_ps/frinta_float create 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instructionAPI/ISA_ps/hint create mode 100644 instructionAPI/ISA_ps/hlt create mode 100644 instructionAPI/ISA_ps/hvc create mode 100644 instructionAPI/ISA_ps/ic_sys create mode 100644 instructionAPI/ISA_ps/index create mode 100644 instructionAPI/ISA_ps/ins_advsimd_elt create mode 100644 instructionAPI/ISA_ps/ins_advsimd_gen create mode 100644 instructionAPI/ISA_ps/isb create mode 100644 instructionAPI/ISA_ps/ld1_advsimd_mult create mode 100644 instructionAPI/ISA_ps/ld1_advsimd_sngl create mode 100644 instructionAPI/ISA_ps/ld1r_advsimd create mode 100644 instructionAPI/ISA_ps/ld2_advsimd_mult create mode 100644 instructionAPI/ISA_ps/ld2_advsimd_sngl create mode 100644 instructionAPI/ISA_ps/ld2r_advsimd create mode 100644 instructionAPI/ISA_ps/ld3_advsimd_mult create mode 100644 instructionAPI/ISA_ps/ld3_advsimd_sngl create mode 100644 instructionAPI/ISA_ps/ld3r_advsimd create mode 100644 instructionAPI/ISA_ps/ld4_advsimd_mult create mode 100644 instructionAPI/ISA_ps/ld4_advsimd_sngl create mode 100644 instructionAPI/ISA_ps/ld4r_advsimd create mode 100644 instructionAPI/ISA_ps/ldar create mode 100644 instructionAPI/ISA_ps/ldarb create mode 100644 instructionAPI/ISA_ps/ldarh create mode 100644 instructionAPI/ISA_ps/ldaxp create mode 100644 instructionAPI/ISA_ps/ldaxr create mode 100644 instructionAPI/ISA_ps/ldaxrb create mode 100644 instructionAPI/ISA_ps/ldaxrh create mode 100644 instructionAPI/ISA_ps/ldnp_fpsimd create mode 100644 instructionAPI/ISA_ps/ldnp_gen create mode 100644 instructionAPI/ISA_ps/ldp_fpsimd create mode 100644 instructionAPI/ISA_ps/ldp_gen create mode 100644 instructionAPI/ISA_ps/ldpsw create mode 100644 instructionAPI/ISA_ps/ldr_imm_fpsimd create mode 100644 instructionAPI/ISA_ps/ldr_imm_gen create mode 100644 instructionAPI/ISA_ps/ldr_lit_fpsimd create mode 100644 instructionAPI/ISA_ps/ldr_lit_gen create mode 100644 instructionAPI/ISA_ps/ldr_reg_fpsimd create mode 100644 instructionAPI/ISA_ps/ldr_reg_gen create mode 100644 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instructionAPI/ISA_ps/uzp1_advsimd create mode 100644 instructionAPI/ISA_ps/uzp2_advsimd create mode 100644 instructionAPI/ISA_ps/wfe_hint create mode 100644 instructionAPI/ISA_ps/wfi_hint create mode 100644 instructionAPI/ISA_ps/xtn_advsimd create mode 100644 instructionAPI/ISA_ps/yield_hint create mode 100644 instructionAPI/ISA_ps/zip1_advsimd create mode 100644 instructionAPI/ISA_ps/zip2_advsimd create mode 100644 instructionAPI/aarch64_pseudocode_extractor.py diff --git a/instructionAPI/ISA_ps/abs_advsimd b/instructionAPI/ISA_ps/abs_advsimd new file mode 100644 index 0000000000..f2993f25a4 --- /dev/null +++ b/instructionAPI/ISA_ps/abs_advsimd @@ -0,0 +1,17 @@ +##abs_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +integer element; + +for e = 0 to elements-1 + element = SInt(Elem[operand, e, esize]); + if neg then + element = -element; + else + element = Abs(element); + end + Elem[result, e, esize] = element; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/adc b/instructionAPI/ISA_ps/adc new file mode 100644 index 0000000000..73b7525749 --- /dev/null +++ b/instructionAPI/ISA_ps/adc @@ -0,0 +1,18 @@ +##adc_execute +bits(datasize) result; +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = X[m]; +bits(4) nzcv; + +if sub_op then + operand2 = NOT(operand2); +end + +(result, nzcv) = AddWithCarry(operand1, operand2, PSTATE.C); + +if setflags then + PSTATE. = nzcv; +end + +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/adcs b/instructionAPI/ISA_ps/adcs new file mode 100644 index 0000000000..9a0108b92b --- /dev/null +++ b/instructionAPI/ISA_ps/adcs @@ -0,0 +1,18 @@ +##adcs_execute +bits(datasize) result; +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = X[m]; +bits(4) nzcv; + +if sub_op then + operand2 = NOT(operand2); +end + +(result, nzcv) = AddWithCarry(operand1, operand2, PSTATE.C); + +if setflags then + PSTATE. = nzcv; +end + +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/add_addsub_ext b/instructionAPI/ISA_ps/add_addsub_ext new file mode 100644 index 0000000000..542c69de42 --- /dev/null +++ b/instructionAPI/ISA_ps/add_addsub_ext @@ -0,0 +1,26 @@ +##add_addsub_ext_execute +bits(datasize) result; +bits(datasize) operand1 = if n == 31 then SP[] else X[n]; +bits(datasize) operand2 = ExtendReg(m, extend_type, shift); +bits(4) nzcv; +bit carry_in; + +if sub_op then + operand2 = NOT(operand2); + carry_in = 1; +else + carry_in = 0; +end + +(result, nzcv) = AddWithCarry(operand1, operand2, carry_in); + +if setflags then + PSTATE. = nzcv; +end + +if d == 31 && !setflags then + SP[] = result; +else + X[d] = result; +end +@@ diff --git a/instructionAPI/ISA_ps/add_addsub_imm b/instructionAPI/ISA_ps/add_addsub_imm new file mode 100644 index 0000000000..a4ff8c406c --- /dev/null +++ b/instructionAPI/ISA_ps/add_addsub_imm @@ -0,0 +1,26 @@ +##add_addsub_imm_execute +bits(datasize) result; +bits(datasize) operand1 = if n == 31 then SP[] else X[n]; +bits(datasize) operand2 = imm; +bits(4) nzcv; +bit carry_in; + +if sub_op then + operand2 = NOT(operand2); + carry_in = 1; +else + carry_in = 0; +end + +(result, nzcv) = AddWithCarry(operand1, operand2, carry_in); + +if setflags then + PSTATE. = nzcv; +end + +if d == 31 && !setflags then + SP[] = result; +else + X[d] = result; +end +@@ diff --git a/instructionAPI/ISA_ps/add_addsub_shift b/instructionAPI/ISA_ps/add_addsub_shift new file mode 100644 index 0000000000..f0d3892725 --- /dev/null +++ b/instructionAPI/ISA_ps/add_addsub_shift @@ -0,0 +1,22 @@ +##add_addsub_shift_execute +bits(datasize) result; +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount); +bits(4) nzcv; +bit carry_in; + +if sub_op then + operand2 = NOT(operand2); + carry_in = 1; +else + carry_in = 0; +end + +(result, nzcv) = AddWithCarry(operand1, operand2, carry_in); + +if setflags then + PSTATE. = nzcv; +end + +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/add_advsimd b/instructionAPI/ISA_ps/add_advsimd new file mode 100644 index 0000000000..e32d7d1b41 --- /dev/null +++ b/instructionAPI/ISA_ps/add_advsimd @@ -0,0 +1,19 @@ +##add_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +bits(esize) element1; +bits(esize) element2; + +for e = 0 to elements-1 + element1 = Elem[operand1, e, esize]; + element2 = Elem[operand2, e, esize]; + if sub_op then + Elem[result, e, esize] = element1 - element2; + else + Elem[result, e, esize] = element1 + element2; + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/addhn_advsimd b/instructionAPI/ISA_ps/addhn_advsimd new file mode 100644 index 0000000000..64ed104ecf --- /dev/null +++ b/instructionAPI/ISA_ps/addhn_advsimd @@ -0,0 +1,23 @@ +##addhn_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(2*datasize) operand1 = V[n]; +bits(2*datasize) operand2 = V[m]; +bits(datasize) result; +integer round_const = if round then 1 << (esize - 1) else 0; +bits(2*esize) element1; +bits(2*esize) element2; +bits(2*esize) sum; + +for e = 0 to elements-1 + element1 = Elem[operand1, e, 2*esize]; + element2 = Elem[operand2, e, 2*esize]; + if sub_op then + sum = element1 - element2; + else + sum = element1 + element2; + end + sum = sum + round_const; + Elem[result, e, esize] = sum<2*esize-1:esize>; + +Vpart[d, part] = result; +@@ diff --git a/instructionAPI/ISA_ps/addp_advsimd_pair b/instructionAPI/ISA_ps/addp_advsimd_pair new file mode 100644 index 0000000000..1678394cc6 --- /dev/null +++ b/instructionAPI/ISA_ps/addp_advsimd_pair @@ -0,0 +1,5 @@ +##addp_advsimd_pair_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +V[d] = Reduce(op, operand, esize); +@@ diff --git a/instructionAPI/ISA_ps/addp_advsimd_vec b/instructionAPI/ISA_ps/addp_advsimd_vec new file mode 100644 index 0000000000..1af0a72665 --- /dev/null +++ b/instructionAPI/ISA_ps/addp_advsimd_vec @@ -0,0 +1,16 @@ +##addp_advsimd_vec_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +bits(2*datasize) concat = operand2:operand1; +bits(esize) element1; +bits(esize) element2; + +for e = 0 to elements-1 + element1 = Elem[concat, 2*e, esize]; + element2 = Elem[concat, (2*e)+1, esize]; + Elem[result, e, esize] = element1 + element2; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/adds_addsub_ext b/instructionAPI/ISA_ps/adds_addsub_ext new file mode 100644 index 0000000000..f07c97137d --- /dev/null +++ b/instructionAPI/ISA_ps/adds_addsub_ext @@ -0,0 +1,26 @@ +##adds_addsub_ext_execute +bits(datasize) result; +bits(datasize) operand1 = if n == 31 then SP[] else X[n]; +bits(datasize) operand2 = ExtendReg(m, extend_type, shift); +bits(4) nzcv; +bit carry_in; + +if sub_op then + operand2 = NOT(operand2); + carry_in = 1; +else + carry_in = 0; +end + +(result, nzcv) = AddWithCarry(operand1, operand2, carry_in); + +if setflags then + PSTATE. = nzcv; +end + +if d == 31 && !setflags then + SP[] = result; +else + X[d] = result; +end +@@ diff --git a/instructionAPI/ISA_ps/adds_addsub_imm b/instructionAPI/ISA_ps/adds_addsub_imm new file mode 100644 index 0000000000..9829ce1c10 --- /dev/null +++ b/instructionAPI/ISA_ps/adds_addsub_imm @@ -0,0 +1,26 @@ +##adds_addsub_imm_execute +bits(datasize) result; +bits(datasize) operand1 = if n == 31 then SP[] else X[n]; +bits(datasize) operand2 = imm; +bits(4) nzcv; +bit carry_in; + +if sub_op then + operand2 = NOT(operand2); + carry_in = 1; +else + carry_in = 0; +end + +(result, nzcv) = AddWithCarry(operand1, operand2, carry_in); + +if setflags then + PSTATE. = nzcv; +end + +if d == 31 && !setflags then + SP[] = result; +else + X[d] = result; +end +@@ diff --git a/instructionAPI/ISA_ps/adds_addsub_shift b/instructionAPI/ISA_ps/adds_addsub_shift new file mode 100644 index 0000000000..e413e04e9c --- /dev/null +++ b/instructionAPI/ISA_ps/adds_addsub_shift @@ -0,0 +1,22 @@ +##adds_addsub_shift_execute +bits(datasize) result; +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount); +bits(4) nzcv; +bit carry_in; + +if sub_op then + operand2 = NOT(operand2); + carry_in = 1; +else + carry_in = 0; +end + +(result, nzcv) = AddWithCarry(operand1, operand2, carry_in); + +if setflags then + PSTATE. = nzcv; +end + +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/addv_advsimd b/instructionAPI/ISA_ps/addv_advsimd new file mode 100644 index 0000000000..c622bea7f3 --- /dev/null +++ b/instructionAPI/ISA_ps/addv_advsimd @@ -0,0 +1,5 @@ +##addv_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +V[d] = Reduce(op, operand, esize); +@@ diff --git a/instructionAPI/ISA_ps/adr b/instructionAPI/ISA_ps/adr new file mode 100644 index 0000000000..789b5637e2 --- /dev/null +++ b/instructionAPI/ISA_ps/adr @@ -0,0 +1,9 @@ +##adr_execute +bits(64) base = PC[]; + +if page then + base<11:0> = Zeros(12); +end + +X[d] = base + imm; +@@ diff --git a/instructionAPI/ISA_ps/adrp b/instructionAPI/ISA_ps/adrp new file mode 100644 index 0000000000..2d5e64710d --- /dev/null +++ b/instructionAPI/ISA_ps/adrp @@ -0,0 +1,9 @@ +##adrp_execute +bits(64) base = PC[]; + +if page then + base<11:0> = Zeros(12); +end + +X[d] = base + imm; +@@ diff --git a/instructionAPI/ISA_ps/aesd_advsimd b/instructionAPI/ISA_ps/aesd_advsimd new file mode 100644 index 0000000000..95c2c52078 --- /dev/null +++ b/instructionAPI/ISA_ps/aesd_advsimd @@ -0,0 +1,14 @@ +##aesd_advsimd_execute +CheckCryptoEnabled64(); + +bits(128) operand1 = V[d]; +bits(128) operand2 = V[n]; +bits(128) result; +result = operand1 EOR operand2; +if decrypt then + result = AESInvSubBytes(AESInvShiftRows(result)); +else + result = AESSubBytes(AESShiftRows(result)); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/aese_advsimd b/instructionAPI/ISA_ps/aese_advsimd new file mode 100644 index 0000000000..a3c0a6192c --- /dev/null +++ b/instructionAPI/ISA_ps/aese_advsimd @@ -0,0 +1,14 @@ +##aese_advsimd_execute +CheckCryptoEnabled64(); + +bits(128) operand1 = V[d]; +bits(128) operand2 = V[n]; +bits(128) result; +result = operand1 EOR operand2; +if decrypt then + result = AESInvSubBytes(AESInvShiftRows(result)); +else + result = AESSubBytes(AESShiftRows(result)); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/aesimc_advsimd b/instructionAPI/ISA_ps/aesimc_advsimd new file mode 100644 index 0000000000..893d432d46 --- /dev/null +++ b/instructionAPI/ISA_ps/aesimc_advsimd @@ -0,0 +1,12 @@ +##aesimc_advsimd_execute +CheckCryptoEnabled64(); + +bits(128) operand = V[n]; +bits(128) result; +if decrypt then + result = AESInvMixColumns(operand); +else + result = AESMixColumns(operand); +end +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/aesmc_advsimd b/instructionAPI/ISA_ps/aesmc_advsimd new file mode 100644 index 0000000000..7c92c6f986 --- /dev/null +++ b/instructionAPI/ISA_ps/aesmc_advsimd @@ -0,0 +1,12 @@ +##aesmc_advsimd_execute +CheckCryptoEnabled64(); + +bits(128) operand = V[n]; +bits(128) result; +if decrypt then + result = AESInvMixColumns(operand); +else + result = AESMixColumns(operand); +end +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/and_advsimd b/instructionAPI/ISA_ps/and_advsimd new file mode 100644 index 0000000000..8cd819b430 --- /dev/null +++ b/instructionAPI/ISA_ps/and_advsimd @@ -0,0 +1,18 @@ +##and_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; + +if invert then operand2 = NOT(operand2); + +case op of + when LogicalOp_AND + result = operand1 AND operand2; + end + when LogicalOp_ORR + result = operand1 OR operand2; + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/and_log_imm b/instructionAPI/ISA_ps/and_log_imm new file mode 100644 index 0000000000..f73dc58081 --- /dev/null +++ b/instructionAPI/ISA_ps/and_log_imm @@ -0,0 +1,23 @@ +##and_log_imm_execute +bits(datasize) result; +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = imm; + +case op of + when LogicalOp_AND result = operand1 AND operand2; + end + when LogicalOp_ORR result = operand1 OR operand2; + end + when LogicalOp_EOR result = operand1 EOR operand2; + end + +if setflags then + PSTATE. = result:IsZeroBit(result):00; +end + +if d == 31 && !setflags then + SP[] = result; +else + X[d] = result; +end +@@ diff --git a/instructionAPI/ISA_ps/and_log_shift b/instructionAPI/ISA_ps/and_log_shift new file mode 100644 index 0000000000..3f83872778 --- /dev/null +++ b/instructionAPI/ISA_ps/and_log_shift @@ -0,0 +1,20 @@ +##and_log_shift_execute +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount); + +if invert then operand2 = NOT(operand2) end; + +case op of + when LogicalOp_AND result = operand1 AND operand2; + end + when LogicalOp_ORR result = operand1 OR operand2; + end + when LogicalOp_EOR result = operand1 EOR operand2; + end + +if setflags then + PSTATE. = result:IsZeroBit(result):00; +end + +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/ands_log_imm b/instructionAPI/ISA_ps/ands_log_imm new file mode 100644 index 0000000000..fd4ac2796a --- /dev/null +++ b/instructionAPI/ISA_ps/ands_log_imm @@ -0,0 +1,23 @@ +##ands_log_imm_execute +bits(datasize) result; +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = imm; + +case op of + when LogicalOp_AND result = operand1 AND operand2; + end + when LogicalOp_ORR result = operand1 OR operand2; + end + when LogicalOp_EOR result = operand1 EOR operand2; + end + +if setflags then + PSTATE. = result:IsZeroBit(result):00; +end + +if d == 31 && !setflags then + SP[] = result; +else + X[d] = result; +end +@@ diff --git a/instructionAPI/ISA_ps/ands_log_shift b/instructionAPI/ISA_ps/ands_log_shift new file mode 100644 index 0000000000..09993de147 --- /dev/null +++ b/instructionAPI/ISA_ps/ands_log_shift @@ -0,0 +1,20 @@ +##ands_log_shift_execute +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount); + +if invert then operand2 = NOT(operand2) end; + +case op of + when LogicalOp_AND result = operand1 AND operand2; + end + when LogicalOp_ORR result = operand1 OR operand2; + end + when LogicalOp_EOR result = operand1 EOR operand2; + end + +if setflags then + PSTATE. = result:IsZeroBit(result):00; +end + +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/asr_asrv b/instructionAPI/ISA_ps/asr_asrv new file mode 100644 index 0000000000..707477c1ac --- /dev/null +++ b/instructionAPI/ISA_ps/asr_asrv @@ -0,0 +1,7 @@ +##asr_asrv_execute +bits(datasize) result; +bits(datasize) operand2 = X[m]; + +result = ShiftReg(n, shift_type, UInt(operand2) MOD datasize); +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/asr_sbfm b/instructionAPI/ISA_ps/asr_sbfm new file mode 100644 index 0000000000..f794f1afe4 --- /dev/null +++ b/instructionAPI/ISA_ps/asr_sbfm @@ -0,0 +1,13 @@ +##asr_sbfm_execute +bits(datasize) dst = if inzero then Zeros(64) else X[d]; +bits(datasize) src = X[n]; + +// perform bitfield move on low bits +bits(datasize) bot = (dst AND NOT(wmask)) OR (ROR(src, R) AND wmask); + +// determine extension bits (sign, zero or dest register) +bits(datasize) top = if extend then Replicate(src) else dst; + +// combine extension bits and result bits +X[d] = (top AND NOT(tmask)) OR (bot AND tmask); +@@ diff --git a/instructionAPI/ISA_ps/asrv b/instructionAPI/ISA_ps/asrv new file mode 100644 index 0000000000..4c64c52c00 --- /dev/null +++ b/instructionAPI/ISA_ps/asrv @@ -0,0 +1,7 @@ +##asrv_execute +bits(datasize) result; +bits(datasize) operand2 = X[m]; + +result = ShiftReg(n, shift_type, UInt(operand2) MOD datasize); +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/at_sys b/instructionAPI/ISA_ps/at_sys new file mode 100644 index 0000000000..d197b8ea01 --- /dev/null +++ b/instructionAPI/ISA_ps/at_sys @@ -0,0 +1,6 @@ +##at_sys_execute +if has_result then + X[t] = SysOp_R(sys_op0, sys_op1, sys_crn, sys_crm, sys_op2); +else + SysOp_W(sys_op0, sys_op1, sys_crn, sys_crm, sys_op2, X[t]); +@@ diff --git a/instructionAPI/ISA_ps/b_cond b/instructionAPI/ISA_ps/b_cond new file mode 100644 index 0000000000..8e5c77728b --- /dev/null +++ b/instructionAPI/ISA_ps/b_cond @@ -0,0 +1,5 @@ +##b_cond_execute +if ConditionHolds(condition) then + BranchTo(PC[] + offset, BranchType_JMP); +end +@@ diff --git a/instructionAPI/ISA_ps/b_uncond b/instructionAPI/ISA_ps/b_uncond new file mode 100644 index 0000000000..a06604b58c --- /dev/null +++ b/instructionAPI/ISA_ps/b_uncond @@ -0,0 +1,5 @@ +##b_uncond_execute +if branch_type == BranchType_CALL then X[30] = PC[] + 4; + +BranchTo(PC[] + offset, branch_type); +@@ diff --git a/instructionAPI/ISA_ps/bfi_bfm b/instructionAPI/ISA_ps/bfi_bfm new file mode 100644 index 0000000000..391566650b --- /dev/null +++ b/instructionAPI/ISA_ps/bfi_bfm @@ -0,0 +1,13 @@ +##bfi_bfm_execute +bits(datasize) dst = if inzero then Zeros(64) else X[d]; +bits(datasize) src = X[n]; + +// perform bitfield move on low bits +bits(datasize) bot = (dst AND NOT(wmask)) OR (ROR(src, R) AND wmask); + +// determine extension bits (sign, zero or dest register) +bits(datasize) top = if extend then Replicate(src) else dst; + +// combine extension bits and result bits +X[d] = (top AND NOT(tmask)) OR (bot AND tmask); +@@ diff --git a/instructionAPI/ISA_ps/bfm b/instructionAPI/ISA_ps/bfm new file mode 100644 index 0000000000..98638d934d --- /dev/null +++ b/instructionAPI/ISA_ps/bfm @@ -0,0 +1,13 @@ +##bfm_execute +bits(datasize) dst = if inzero then Zeros(64) else X[d]; +bits(datasize) src = X[n]; + +// perform bitfield move on low bits +bits(datasize) bot = (dst AND NOT(wmask)) OR (ROR(src, R) AND wmask); + +// determine extension bits (sign, zero or dest register) +bits(datasize) top = if extend then Replicate(src) else dst; + +// combine extension bits and result bits +X[d] = (top AND NOT(tmask)) OR (bot AND tmask); +@@ diff --git a/instructionAPI/ISA_ps/bfxil_bfm b/instructionAPI/ISA_ps/bfxil_bfm new file mode 100644 index 0000000000..2d7ec1c127 --- /dev/null +++ b/instructionAPI/ISA_ps/bfxil_bfm @@ -0,0 +1,13 @@ +##bfxil_bfm_execute +bits(datasize) dst = if inzero then Zeros(64) else X[d]; +bits(datasize) src = X[n]; + +// perform bitfield move on low bits +bits(datasize) bot = (dst AND NOT(wmask)) OR (ROR(src, R) AND wmask); + +// determine extension bits (sign, zero or dest register) +bits(datasize) top = if extend then Replicate(src) else dst; + +// combine extension bits and result bits +X[d] = (top AND NOT(tmask)) OR (bot AND tmask); +@@ diff --git a/instructionAPI/ISA_ps/bic_advsimd_imm b/instructionAPI/ISA_ps/bic_advsimd_imm new file mode 100644 index 0000000000..27b98d14cd --- /dev/null +++ b/instructionAPI/ISA_ps/bic_advsimd_imm @@ -0,0 +1,23 @@ +##bic_advsimd_imm_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand; +bits(datasize) result; + +case operation of + when ImmediateOp_MOVI + result = imm; + end + when ImmediateOp_MVNI + result = NOT(imm); + end + when ImmediateOp_ORR + operand = V[rd]; + result = operand OR imm; + end + when ImmediateOp_BIC + operand = V[rd]; + result = operand AND NOT(imm); + end + +V[rd] = result; +@@ diff --git a/instructionAPI/ISA_ps/bic_advsimd_reg b/instructionAPI/ISA_ps/bic_advsimd_reg new file mode 100644 index 0000000000..559a3313bf --- /dev/null +++ b/instructionAPI/ISA_ps/bic_advsimd_reg @@ -0,0 +1,18 @@ +##bic_advsimd_reg_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; + +if invert then operand2 = NOT(operand2); + +case op of + when LogicalOp_AND + result = operand1 AND operand2; + end + when LogicalOp_ORR + result = operand1 OR operand2; + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/bic_log_shift b/instructionAPI/ISA_ps/bic_log_shift new file mode 100644 index 0000000000..efed9717d1 --- /dev/null +++ b/instructionAPI/ISA_ps/bic_log_shift @@ -0,0 +1,20 @@ +##bic_log_shift_execute +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount); + +if invert then operand2 = NOT(operand2) end; + +case op of + when LogicalOp_AND result = operand1 AND operand2; + end + when LogicalOp_ORR result = operand1 OR operand2; + end + when LogicalOp_EOR result = operand1 EOR operand2; + end + +if setflags then + PSTATE. = result:IsZeroBit(result):00; +end + +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/bics b/instructionAPI/ISA_ps/bics new file mode 100644 index 0000000000..82810531ea --- /dev/null +++ b/instructionAPI/ISA_ps/bics @@ -0,0 +1,20 @@ +##bics_execute +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount); + +if invert then operand2 = NOT(operand2) end; + +case op of + when LogicalOp_AND result = operand1 AND operand2; + end + when LogicalOp_ORR result = operand1 OR operand2; + end + when LogicalOp_EOR result = operand1 EOR operand2; + end + +if setflags then + PSTATE. = result:IsZeroBit(result):00; +end + +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/bif_advsimd b/instructionAPI/ISA_ps/bif_advsimd new file mode 100644 index 0000000000..d8da5febf5 --- /dev/null +++ b/instructionAPI/ISA_ps/bif_advsimd @@ -0,0 +1,31 @@ +##bif_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1; +bits(datasize) operand2; +bits(datasize) operand3; +bits(datasize) operand4 = V[n]; + +case op of + when VBitOp_VEOR + operand1 = V[m]; + operand2 = Zeros(64); + operand3 = Ones(); + end + when VBitOp_VBSL + operand1 = V[m]; + operand2 = operand1; + operand3 = V[d]; + end + when VBitOp_VBIT + operand1 = V[d]; + operand2 = operand1; + operand3 = V[m]; + end + when VBitOp_VBIF + operand1 = V[d]; + operand2 = operand1; + operand3 = NOT(V[m]); + end + +V[d] = operand1 EOR ((operand2 EOR operand4) AND operand3); +@@ diff --git a/instructionAPI/ISA_ps/bit_advsimd b/instructionAPI/ISA_ps/bit_advsimd new file mode 100644 index 0000000000..c89b42362d --- /dev/null +++ b/instructionAPI/ISA_ps/bit_advsimd @@ -0,0 +1,31 @@ +##bit_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1; +bits(datasize) operand2; +bits(datasize) operand3; +bits(datasize) operand4 = V[n]; + +case op of + when VBitOp_VEOR + operand1 = V[m]; + operand2 = Zeros(64); + operand3 = Ones(); + end + when VBitOp_VBSL + operand1 = V[m]; + operand2 = operand1; + operand3 = V[d]; + end + when VBitOp_VBIT + operand1 = V[d]; + operand2 = operand1; + operand3 = V[m]; + end + when VBitOp_VBIF + operand1 = V[d]; + operand2 = operand1; + operand3 = NOT(V[m]); + end + +V[d] = operand1 EOR ((operand2 EOR operand4) AND operand3); +@@ diff --git a/instructionAPI/ISA_ps/bl b/instructionAPI/ISA_ps/bl new file mode 100644 index 0000000000..f1e13ed985 --- /dev/null +++ b/instructionAPI/ISA_ps/bl @@ -0,0 +1,5 @@ +##bl_execute +if branch_type == BranchType_CALL then X[30] = PC[] + 4; + +BranchTo(PC[] + offset, branch_type); +@@ diff --git a/instructionAPI/ISA_ps/blr b/instructionAPI/ISA_ps/blr new file mode 100644 index 0000000000..eb8e475f0f --- /dev/null +++ b/instructionAPI/ISA_ps/blr @@ -0,0 +1,6 @@ +##blr_execute +bits(64) target = X[n]; + +if branch_type == BranchType_CALL then X[30] = PC[] + 4; +BranchTo(target, branch_type); +@@ diff --git a/instructionAPI/ISA_ps/br b/instructionAPI/ISA_ps/br new file mode 100644 index 0000000000..578372ef4c --- /dev/null +++ b/instructionAPI/ISA_ps/br @@ -0,0 +1,6 @@ +##br_execute +bits(64) target = X[n]; + +if branch_type == BranchType_CALL then X[30] = PC[] + 4; +BranchTo(target, branch_type); +@@ diff --git a/instructionAPI/ISA_ps/brk b/instructionAPI/ISA_ps/brk new file mode 100644 index 0000000000..a13ba03a5d --- /dev/null +++ b/instructionAPI/ISA_ps/brk @@ -0,0 +1,3 @@ +##brk_execute +AArch64.SoftwareBreakpoint(comment); +@@ diff --git a/instructionAPI/ISA_ps/bsl_advsimd b/instructionAPI/ISA_ps/bsl_advsimd new file mode 100644 index 0000000000..fad87b620c --- /dev/null +++ b/instructionAPI/ISA_ps/bsl_advsimd @@ -0,0 +1,31 @@ +##bsl_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1; +bits(datasize) operand2; +bits(datasize) operand3; +bits(datasize) operand4 = V[n]; + +case op of + when VBitOp_VEOR + operand1 = V[m]; + operand2 = Zeros(64); + operand3 = Ones(); + end + when VBitOp_VBSL + operand1 = V[m]; + operand2 = operand1; + operand3 = V[d]; + end + when VBitOp_VBIT + operand1 = V[d]; + operand2 = operand1; + operand3 = V[m]; + end + when VBitOp_VBIF + operand1 = V[d]; + operand2 = operand1; + operand3 = NOT(V[m]); + end + +V[d] = operand1 EOR ((operand2 EOR operand4) AND operand3); +@@ diff --git a/instructionAPI/ISA_ps/cbnz b/instructionAPI/ISA_ps/cbnz new file mode 100644 index 0000000000..3f9c7cc55b --- /dev/null +++ b/instructionAPI/ISA_ps/cbnz @@ -0,0 +1,7 @@ +##cbnz_execute +bits(datasize) operand1 = X[t]; + +if IsZero(operand1) == iszero then + BranchTo(PC[] + offset, BranchType_JMP); +end +@@ diff --git a/instructionAPI/ISA_ps/cbz b/instructionAPI/ISA_ps/cbz new file mode 100644 index 0000000000..55d13e4f58 --- /dev/null +++ b/instructionAPI/ISA_ps/cbz @@ -0,0 +1,7 @@ +##cbz_execute +bits(datasize) operand1 = X[t]; + +if IsZero(operand1) == iszero then + BranchTo(PC[] + offset, BranchType_JMP); +end +@@ diff --git a/instructionAPI/ISA_ps/ccmn_imm b/instructionAPI/ISA_ps/ccmn_imm new file mode 100644 index 0000000000..24905f03bb --- /dev/null +++ b/instructionAPI/ISA_ps/ccmn_imm @@ -0,0 +1,14 @@ +##ccmn_imm_execute +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = imm; +bit carry_in = 0; + +if ConditionHolds(condition) then + if sub_op then + operand2 = NOT(operand2); + carry_in = 1; + end + (null, flags) = AddWithCarry(operand1, operand2, carry_in); +end +PSTATE. = flags; +@@ diff --git a/instructionAPI/ISA_ps/ccmn_reg b/instructionAPI/ISA_ps/ccmn_reg new file mode 100644 index 0000000000..07cc5e95e6 --- /dev/null +++ b/instructionAPI/ISA_ps/ccmn_reg @@ -0,0 +1,14 @@ +##ccmn_reg_execute +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = X[m]; +bit carry_in = 0; + +if ConditionHolds(condition) then + if sub_op then + operand2 = NOT(operand2); + carry_in = 1; + end + (null, flags) = AddWithCarry(operand1, operand2, carry_in); +end +PSTATE. = flags; +@@ diff --git a/instructionAPI/ISA_ps/ccmp_imm b/instructionAPI/ISA_ps/ccmp_imm new file mode 100644 index 0000000000..939ab77489 --- /dev/null +++ b/instructionAPI/ISA_ps/ccmp_imm @@ -0,0 +1,14 @@ +##ccmp_imm_execute +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = imm; +bit carry_in = 0; + +if ConditionHolds(condition) then + if sub_op then + operand2 = NOT(operand2); + carry_in = 1; + end + (-, flags) = AddWithCarry(operand1, operand2, carry_in); +end +PSTATE. = flags; +@@ diff --git a/instructionAPI/ISA_ps/ccmp_reg b/instructionAPI/ISA_ps/ccmp_reg new file mode 100644 index 0000000000..832947bfe3 --- /dev/null +++ b/instructionAPI/ISA_ps/ccmp_reg @@ -0,0 +1,14 @@ +##ccmp_reg_execute +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = X[m]; +bit carry_in = 0; + +if ConditionHolds(condition) then + if sub_op then + operand2 = NOT(operand2); + carry_in = 1; + end + (null, flags) = AddWithCarry(operand1, operand2, carry_in); +end +PSTATE. = flags; +@@ diff --git a/instructionAPI/ISA_ps/cinc_csinc b/instructionAPI/ISA_ps/cinc_csinc new file mode 100644 index 0000000000..3b4c5c00c7 --- /dev/null +++ b/instructionAPI/ISA_ps/cinc_csinc @@ -0,0 +1,16 @@ +##cinc_csinc_execute +bits(datasize) result; +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = X[m]; + +if ConditionHolds(condition) then + result = operand1; +else + result = operand2; + if else_inv then result = NOT(result); + if else_inc then result = result + 1; + + end +X[d] = result; +end +@@ diff --git a/instructionAPI/ISA_ps/cinv_csinv b/instructionAPI/ISA_ps/cinv_csinv new file mode 100644 index 0000000000..374df4f6c0 --- /dev/null +++ b/instructionAPI/ISA_ps/cinv_csinv @@ -0,0 +1,16 @@ +##cinv_csinv_execute +bits(datasize) result; +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = X[m]; + +if ConditionHolds(condition) then + result = operand1; +else + result = operand2; + if else_inv then result = NOT(result); + if else_inc then result = result + 1; + + end +X[d] = result; +end +@@ diff --git a/instructionAPI/ISA_ps/clrex b/instructionAPI/ISA_ps/clrex new file mode 100644 index 0000000000..a78b0a0f1e --- /dev/null +++ b/instructionAPI/ISA_ps/clrex @@ -0,0 +1,3 @@ +##clrex_execute +ClearExclusiveLocal(ProcessorID()); +@@ diff --git a/instructionAPI/ISA_ps/cls_advsimd b/instructionAPI/ISA_ps/cls_advsimd new file mode 100644 index 0000000000..34d5651719 --- /dev/null +++ b/instructionAPI/ISA_ps/cls_advsimd @@ -0,0 +1,15 @@ +##cls_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; + +integer count; +for e = 0 to elements-1 + if countop == CountOp_CLS then + count = CountLeadingSignBits(Elem[operand, e, esize]); + else + count = CountLeadingZeroBits(Elem[operand, e, esize]); + end + Elem[result, e, esize] = count; +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/cls_int b/instructionAPI/ISA_ps/cls_int new file mode 100644 index 0000000000..937b7b170c --- /dev/null +++ b/instructionAPI/ISA_ps/cls_int @@ -0,0 +1,12 @@ +##cls_int_execute +integer result; +bits(datasize) operand1 = X[n]; + +if opcode == CountOp_CLZ then + result = CountLeadingZeroBits(operand1); +else + result = CountLeadingSignBits(operand1); +end + +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/clz_advsimd b/instructionAPI/ISA_ps/clz_advsimd new file mode 100644 index 0000000000..502f60127a --- /dev/null +++ b/instructionAPI/ISA_ps/clz_advsimd @@ -0,0 +1,15 @@ +##clz_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; + +integer count; +for e = 0 to elements-1 + if countop == CountOp_CLS then + count = CountLeadingSignBits(Elem[operand, e, esize]); + else + count = CountLeadingZeroBits(Elem[operand, e, esize]); + end + Elem[result, e, esize] = count; +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/clz_int b/instructionAPI/ISA_ps/clz_int new file mode 100644 index 0000000000..9db0c4cccd --- /dev/null +++ b/instructionAPI/ISA_ps/clz_int @@ -0,0 +1,12 @@ +##clz_int_execute +integer result; +bits(datasize) operand1 = X[n]; + +if opcode == CountOp_CLZ then + result = CountLeadingZeroBits(operand1); +else + result = CountLeadingSignBits(operand1); +end + +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/cmeq_advsimd_reg b/instructionAPI/ISA_ps/cmeq_advsimd_reg new file mode 100644 index 0000000000..267241763d --- /dev/null +++ b/instructionAPI/ISA_ps/cmeq_advsimd_reg @@ -0,0 +1,21 @@ +##cmeq_advsimd_reg_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +bits(esize) element1; +bits(esize) element2; +boolean test_passed; + +for e = 0 to elements-1 + element1 = Elem[operand1, e, esize]; + element2 = Elem[operand2, e, esize]; + if and_test then + test_passed = !IsZero(element1 AND element2); + else + test_passed = (element1 == element2); + Elem[result, e, esize] = if test_passed then Ones() else Zeros(64); + + end +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/cmeq_advsimd_zero b/instructionAPI/ISA_ps/cmeq_advsimd_zero new file mode 100644 index 0000000000..d0adc8c9a0 --- /dev/null +++ b/instructionAPI/ISA_ps/cmeq_advsimd_zero @@ -0,0 +1,24 @@ +##cmeq_advsimd_zero_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +integer element; +boolean test_passed; + +for e = 0 to elements-1 + element = SInt(Elem[operand, e, esize]); + case comparison of + when CompareOp_GT test_passed = element > 0; + end + when CompareOp_GE test_passed = element >= 0; + end + when CompareOp_EQ test_passed = element == 0; + end + when CompareOp_LE test_passed = element <= 0; + end + when CompareOp_LT test_passed = element < 0; + Elem[result, e, esize] = if test_passed then Ones() else Zeros(64); + + end +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/cmge_advsimd_reg b/instructionAPI/ISA_ps/cmge_advsimd_reg new file mode 100644 index 0000000000..6163405e0f --- /dev/null +++ b/instructionAPI/ISA_ps/cmge_advsimd_reg @@ -0,0 +1,18 @@ +##cmge_advsimd_reg_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +integer element1; +integer element2; +boolean test_passed; + +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + test_passed = if cmp_eq then element1 >= element2 else element1 > element2; + Elem[result, e, esize] = if test_passed then Ones() else Zeros(64); + + end +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/cmge_advsimd_zero b/instructionAPI/ISA_ps/cmge_advsimd_zero new file mode 100644 index 0000000000..20a9f88896 --- /dev/null +++ b/instructionAPI/ISA_ps/cmge_advsimd_zero @@ -0,0 +1,24 @@ +##cmge_advsimd_zero_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +integer element; +boolean test_passed; + +for e = 0 to elements-1 + element = SInt(Elem[operand, e, esize]); + case comparison of + when CompareOp_GT test_passed = element > 0; + end + when CompareOp_GE test_passed = element >= 0; + end + when CompareOp_EQ test_passed = element == 0; + end + when CompareOp_LE test_passed = element <= 0; + end + when CompareOp_LT test_passed = element < 0; + Elem[result, e, esize] = if test_passed then Ones() else Zeros(64); + + end +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/cmgt_advsimd_reg b/instructionAPI/ISA_ps/cmgt_advsimd_reg new file mode 100644 index 0000000000..652825de25 --- /dev/null +++ b/instructionAPI/ISA_ps/cmgt_advsimd_reg @@ -0,0 +1,18 @@ +##cmgt_advsimd_reg_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +integer element1; +integer element2; +boolean test_passed; + +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + test_passed = if cmp_eq then element1 >= element2 else element1 > element2; + Elem[result, e, esize] = if test_passed then Ones() else Zeros(64); + + end +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/cmgt_advsimd_zero b/instructionAPI/ISA_ps/cmgt_advsimd_zero new file mode 100644 index 0000000000..e42e329830 --- /dev/null +++ b/instructionAPI/ISA_ps/cmgt_advsimd_zero @@ -0,0 +1,24 @@ +##cmgt_advsimd_zero_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +integer element; +boolean test_passed; + +for e = 0 to elements-1 + element = SInt(Elem[operand, e, esize]); + case comparison of + when CompareOp_GT test_passed = element > 0; + end + when CompareOp_GE test_passed = element >= 0; + end + when CompareOp_EQ test_passed = element == 0; + end + when CompareOp_LE test_passed = element <= 0; + end + when CompareOp_LT test_passed = element < 0; + Elem[result, e, esize] = if test_passed then Ones() else Zeros(64); + + end +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/cmhi_advsimd b/instructionAPI/ISA_ps/cmhi_advsimd new file mode 100644 index 0000000000..09261c3305 --- /dev/null +++ b/instructionAPI/ISA_ps/cmhi_advsimd @@ -0,0 +1,18 @@ +##cmhi_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +integer element1; +integer element2; +boolean test_passed; + +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + test_passed = if cmp_eq then element1 >= element2 else element1 > element2; + Elem[result, e, esize] = if test_passed then Ones() else Zeros(64); + + end +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/cmhs_advsimd b/instructionAPI/ISA_ps/cmhs_advsimd new file mode 100644 index 0000000000..3d119bcc35 --- /dev/null +++ b/instructionAPI/ISA_ps/cmhs_advsimd @@ -0,0 +1,18 @@ +##cmhs_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +integer element1; +integer element2; +boolean test_passed; + +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + test_passed = if cmp_eq then element1 >= element2 else element1 > element2; + Elem[result, e, esize] = if test_passed then Ones() else Zeros(64); + + end +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/cmle_advsimd b/instructionAPI/ISA_ps/cmle_advsimd new file mode 100644 index 0000000000..cff197a0b0 --- /dev/null +++ b/instructionAPI/ISA_ps/cmle_advsimd @@ -0,0 +1,24 @@ +##cmle_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +integer element; +boolean test_passed; + +for e = 0 to elements-1 + element = SInt(Elem[operand, e, esize]); + case comparison of + when CompareOp_GT test_passed = element > 0; + end + when CompareOp_GE test_passed = element >= 0; + end + when CompareOp_EQ test_passed = element == 0; + end + when CompareOp_LE test_passed = element <= 0; + end + when CompareOp_LT test_passed = element < 0; + Elem[result, e, esize] = if test_passed then Ones() else Zeros(64); + + end +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/cmlt_advsimd b/instructionAPI/ISA_ps/cmlt_advsimd new file mode 100644 index 0000000000..65d72d9fac --- /dev/null +++ b/instructionAPI/ISA_ps/cmlt_advsimd @@ -0,0 +1,24 @@ +##cmlt_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +integer element; +boolean test_passed; + +for e = 0 to elements-1 + element = SInt(Elem[operand, e, esize]); + case comparison of + when CompareOp_GT test_passed = element > 0; + end + when CompareOp_GE test_passed = element >= 0; + end + when CompareOp_EQ test_passed = element == 0; + end + when CompareOp_LE test_passed = element <= 0; + end + when CompareOp_LT test_passed = element < 0; + Elem[result, e, esize] = if test_passed then Ones() else Zeros(64); + + end +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/cmn_adds_addsub_ext b/instructionAPI/ISA_ps/cmn_adds_addsub_ext new file mode 100644 index 0000000000..0b1cc57025 --- /dev/null +++ b/instructionAPI/ISA_ps/cmn_adds_addsub_ext @@ -0,0 +1,26 @@ +##cmn_adds_addsub_ext_execute +bits(datasize) result; +bits(datasize) operand1 = if n == 31 then SP[] else X[n]; +bits(datasize) operand2 = ExtendReg(m, extend_type, shift); +bits(4) nzcv; +bit carry_in; + +if sub_op then + operand2 = NOT(operand2); + carry_in = 1; +else + carry_in = 0; +end + +(result, nzcv) = AddWithCarry(operand1, operand2, carry_in); + +if setflags then + PSTATE. = nzcv; +end + +if d == 31 && !setflags then + SP[] = result; +else + X[d] = result; +end +@@ diff --git a/instructionAPI/ISA_ps/cmn_adds_addsub_imm b/instructionAPI/ISA_ps/cmn_adds_addsub_imm new file mode 100644 index 0000000000..4094bb1f95 --- /dev/null +++ b/instructionAPI/ISA_ps/cmn_adds_addsub_imm @@ -0,0 +1,26 @@ +##cmn_adds_addsub_imm_execute +bits(datasize) result; +bits(datasize) operand1 = if n == 31 then SP[] else X[n]; +bits(datasize) operand2 = imm; +bits(4) nzcv; +bit carry_in; + +if sub_op then + operand2 = NOT(operand2); + carry_in = 1; +else + carry_in = 0; +end + +(result, nzcv) = AddWithCarry(operand1, operand2, carry_in); + +if setflags then + PSTATE. = nzcv; +end + +if d == 31 && !setflags then + SP[] = result; +else + X[d] = result; +end +@@ diff --git a/instructionAPI/ISA_ps/cmn_adds_addsub_shift b/instructionAPI/ISA_ps/cmn_adds_addsub_shift new file mode 100644 index 0000000000..2748f5375a --- /dev/null +++ b/instructionAPI/ISA_ps/cmn_adds_addsub_shift @@ -0,0 +1,22 @@ +##cmn_adds_addsub_shift_execute +bits(datasize) result; +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount); +bits(4) nzcv; +bit carry_in; + +if sub_op then + operand2 = NOT(operand2); + carry_in = 1; +else + carry_in = 0; +end + +(result, nzcv) = AddWithCarry(operand1, operand2, carry_in); + +if setflags then + PSTATE. = nzcv; +end + +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/cmp_subs_addsub_ext b/instructionAPI/ISA_ps/cmp_subs_addsub_ext new file mode 100644 index 0000000000..ee32e33a10 --- /dev/null +++ b/instructionAPI/ISA_ps/cmp_subs_addsub_ext @@ -0,0 +1,26 @@ +##cmp_subs_addsub_ext_execute +bits(datasize) result; +bits(datasize) operand1 = if n == 31 then SP[] else X[n]; +bits(datasize) operand2 = ExtendReg(m, extend_type, shift); +bits(4) nzcv; +bit carry_in; + +if sub_op then + operand2 = NOT(operand2); + carry_in = 1; +else + carry_in = 0; +end + +(result, nzcv) = AddWithCarry(operand1, operand2, carry_in); + +if setflags then + PSTATE. = nzcv; +end + +if d == 31 && !setflags then + SP[] = result; +else + X[d] = result; +end +@@ diff --git a/instructionAPI/ISA_ps/cmp_subs_addsub_imm b/instructionAPI/ISA_ps/cmp_subs_addsub_imm new file mode 100644 index 0000000000..cbb207be7e --- /dev/null +++ b/instructionAPI/ISA_ps/cmp_subs_addsub_imm @@ -0,0 +1,26 @@ +##cmp_subs_addsub_imm_execute +bits(datasize) result; +bits(datasize) operand1 = if n == 31 then SP[] else X[n]; +bits(datasize) operand2 = imm; +bits(4) nzcv; +bit carry_in; + +if sub_op then + operand2 = NOT(operand2); + carry_in = 1; +else + carry_in = 0; +end + +(result, nzcv) = AddWithCarry(operand1, operand2, carry_in); + +if setflags then + PSTATE. = nzcv; +end + +if d == 31 && !setflags then + SP[] = result; +else + X[d] = result; +end +@@ diff --git a/instructionAPI/ISA_ps/cmp_subs_addsub_shift b/instructionAPI/ISA_ps/cmp_subs_addsub_shift new file mode 100644 index 0000000000..c36b94f4c8 --- /dev/null +++ b/instructionAPI/ISA_ps/cmp_subs_addsub_shift @@ -0,0 +1,22 @@ +##cmp_subs_addsub_shift_execute +bits(datasize) result; +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount); +bits(4) nzcv; +bit carry_in; + +if sub_op then + operand2 = NOT(operand2); + carry_in = 1; +else + carry_in = 0; +end + +(result, nzcv) = AddWithCarry(operand1, operand2, carry_in); + +if setflags then + PSTATE. = nzcv; +end + +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/cmtst_advsimd b/instructionAPI/ISA_ps/cmtst_advsimd new file mode 100644 index 0000000000..be2bea88df --- /dev/null +++ b/instructionAPI/ISA_ps/cmtst_advsimd @@ -0,0 +1,21 @@ +##cmtst_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +bits(esize) element1; +bits(esize) element2; +boolean test_passed; + +for e = 0 to elements-1 + element1 = Elem[operand1, e, esize]; + element2 = Elem[operand2, e, esize]; + if and_test then + test_passed = !IsZero(element1 AND element2); + else + test_passed = (element1 == element2); + Elem[result, e, esize] = if test_passed then Ones() else Zeros(64); + + end +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/cneg_csneg b/instructionAPI/ISA_ps/cneg_csneg new file mode 100644 index 0000000000..0613f00dbc --- /dev/null +++ b/instructionAPI/ISA_ps/cneg_csneg @@ -0,0 +1,16 @@ +##cneg_csneg_execute +bits(datasize) result; +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = X[m]; + +if ConditionHolds(condition) then + result = operand1; +else + result = operand2; + if else_inv then result = NOT(result); + if else_inc then result = result + 1; + + end +X[d] = result; +end +@@ diff --git a/instructionAPI/ISA_ps/cnt_advsimd b/instructionAPI/ISA_ps/cnt_advsimd new file mode 100644 index 0000000000..7509872ab7 --- /dev/null +++ b/instructionAPI/ISA_ps/cnt_advsimd @@ -0,0 +1,11 @@ +##cnt_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; + +integer count; +for e = 0 to elements-1 + count = BitCount(Elem[operand, e, esize]); + Elem[result, e, esize] = count; +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/crc32 b/instructionAPI/ISA_ps/crc32 new file mode 100644 index 0000000000..980974cc37 --- /dev/null +++ b/instructionAPI/ISA_ps/crc32 @@ -0,0 +1,15 @@ +##crc32_execute +if !HaveCRCExt() then + UnallocatedEncoding(); +end + +bits(32) acc = X[n]; // accumulator +bits(size) val = X[m]; // input value +bits(32) poly = (if crc32c then 0x1EDC6F41 else 0x04C11DB7)<31:0>; + +bits(32+size) tempacc = BitReverse(acc) : Zeros(size); +bits(size+32) tempval = BitReverse(val) : Zeros(32); + +// Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation +X[d] = BitReverse(Poly32Mod2(tempacc EOR tempval, poly)); +@@ diff --git a/instructionAPI/ISA_ps/crc32c b/instructionAPI/ISA_ps/crc32c new file mode 100644 index 0000000000..8bf6d17dda --- /dev/null +++ b/instructionAPI/ISA_ps/crc32c @@ -0,0 +1,15 @@ +##crc32c_execute +if !HaveCRCExt() then + UnallocatedEncoding(); +end + +bits(32) acc = X[n]; // accumulator +bits(size) val = X[m]; // input value +bits(32) poly = (if crc32c then 0x1EDC6F41 else 0x04C11DB7)<31:0>; + +bits(32+size) tempacc = BitReverse(acc) : Zeros(size); +bits(size+32) tempval = BitReverse(val) : Zeros(32); + +// Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation +X[d] = BitReverse(Poly32Mod2(tempacc EOR tempval, poly)); +@@ diff --git a/instructionAPI/ISA_ps/csel b/instructionAPI/ISA_ps/csel new file mode 100644 index 0000000000..a4540e3ab0 --- /dev/null +++ b/instructionAPI/ISA_ps/csel @@ -0,0 +1,15 @@ +##csel_execute +bits(datasize) result; +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = X[m]; + +if ConditionHolds(condition) then + result = operand1; +else + result = operand2; + if else_inv then result = NOT(result) end; + if else_inc then result = result + 1; + end +end +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/cset_csinc b/instructionAPI/ISA_ps/cset_csinc new file mode 100644 index 0000000000..f74f37b4fb --- /dev/null +++ b/instructionAPI/ISA_ps/cset_csinc @@ -0,0 +1,16 @@ +##cset_csinc_execute +bits(datasize) result; +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = X[m]; + +if ConditionHolds(condition) then + result = operand1; +else + result = operand2; + if else_inv then result = NOT(result); + if else_inc then result = result + 1; + + end +X[d] = result; +end +@@ diff --git a/instructionAPI/ISA_ps/csetm_csinv b/instructionAPI/ISA_ps/csetm_csinv new file mode 100644 index 0000000000..3ef7383d08 --- /dev/null +++ b/instructionAPI/ISA_ps/csetm_csinv @@ -0,0 +1,16 @@ +##csetm_csinv_execute +bits(datasize) result; +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = X[m]; + +if ConditionHolds(condition) then + result = operand1; +else + result = operand2; + if else_inv then result = NOT(result); + if else_inc then result = result + 1; + + end +X[d] = result; +end +@@ diff --git a/instructionAPI/ISA_ps/csinc b/instructionAPI/ISA_ps/csinc new file mode 100644 index 0000000000..ec5879c669 --- /dev/null +++ b/instructionAPI/ISA_ps/csinc @@ -0,0 +1,17 @@ +##csinc_execute +bits(datasize) result; +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = X[m]; + +if ConditionHolds(condition) then + result = operand1; +else + result = operand2; + if else_inv then result = NOT(result); + end + if else_inc then result = result + 1; + end +end + +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/csinv b/instructionAPI/ISA_ps/csinv new file mode 100644 index 0000000000..a5b9615304 --- /dev/null +++ b/instructionAPI/ISA_ps/csinv @@ -0,0 +1,17 @@ +##csinv_execute +bits(datasize) result; +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = X[m]; + +if ConditionHolds(condition) then + result = operand1; +else + result = operand2; + if else_inv then result = NOT(result) end; + if else_inc then result = result + 1; + + end +end + +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/csneg b/instructionAPI/ISA_ps/csneg new file mode 100644 index 0000000000..31d3d74f7c --- /dev/null +++ b/instructionAPI/ISA_ps/csneg @@ -0,0 +1,16 @@ +##csneg_execute +bits(datasize) result; +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = X[m]; + +if ConditionHolds(condition) then + result = operand1; +else + result = operand2; + if else_inv then result = NOT(result) end; + if else_inc then result = result + 1; + end +end + +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/dc_sys b/instructionAPI/ISA_ps/dc_sys new file mode 100644 index 0000000000..fb75d68b66 --- /dev/null +++ b/instructionAPI/ISA_ps/dc_sys @@ -0,0 +1,7 @@ +##dc_sys_execute +if has_result then + X[t] = SysOp_R(sys_op0, sys_op1, sys_crn, sys_crm, sys_op2); +else + SysOp_W(sys_op0, sys_op1, sys_crn, sys_crm, sys_op2, X[t]); +end +@@ diff --git a/instructionAPI/ISA_ps/dcps1 b/instructionAPI/ISA_ps/dcps1 new file mode 100644 index 0000000000..21beeb0a37 --- /dev/null +++ b/instructionAPI/ISA_ps/dcps1 @@ -0,0 +1,3 @@ +##dcps1_execute +DCPSInstruction(target_level); +@@ diff --git a/instructionAPI/ISA_ps/dcps2 b/instructionAPI/ISA_ps/dcps2 new file mode 100644 index 0000000000..8e94f280e7 --- /dev/null +++ b/instructionAPI/ISA_ps/dcps2 @@ -0,0 +1,3 @@ +##dcps2_execute +DCPSInstruction(target_level); +@@ diff --git a/instructionAPI/ISA_ps/dcps3 b/instructionAPI/ISA_ps/dcps3 new file mode 100644 index 0000000000..dda17372dc --- /dev/null +++ b/instructionAPI/ISA_ps/dcps3 @@ -0,0 +1,3 @@ +##dcps3_execute +DCPSInstruction(target_level); +@@ diff --git a/instructionAPI/ISA_ps/dmb b/instructionAPI/ISA_ps/dmb new file mode 100644 index 0000000000..099ff47be3 --- /dev/null +++ b/instructionAPI/ISA_ps/dmb @@ -0,0 +1,12 @@ +##dmb_execute +case op of + when MemBarrierOp_DSB + DataSynchronizationBarrier(domain, types); + end + when MemBarrierOp_DMB + DataMemoryBarrier(domain, types); + end + when MemBarrierOp_ISB + InstructionSynchronizationBarrier(); + end +@@ diff --git a/instructionAPI/ISA_ps/drps b/instructionAPI/ISA_ps/drps new file mode 100644 index 0000000000..5ecda8ebdd --- /dev/null +++ b/instructionAPI/ISA_ps/drps @@ -0,0 +1,3 @@ +##drps_execute +DRPSInstruction(); +@@ diff --git a/instructionAPI/ISA_ps/dsb b/instructionAPI/ISA_ps/dsb new file mode 100644 index 0000000000..ac1cd3e6f4 --- /dev/null +++ b/instructionAPI/ISA_ps/dsb @@ -0,0 +1,12 @@ +##dsb_execute +case op of + when MemBarrierOp_DSB + DataSynchronizationBarrier(domain, types); + end + when MemBarrierOp_DMB + DataMemoryBarrier(domain, types); + end + when MemBarrierOp_ISB + InstructionSynchronizationBarrier(); + end +@@ diff --git a/instructionAPI/ISA_ps/dup_advsimd_elt b/instructionAPI/ISA_ps/dup_advsimd_elt new file mode 100644 index 0000000000..abc6bfba06 --- /dev/null +++ b/instructionAPI/ISA_ps/dup_advsimd_elt @@ -0,0 +1,11 @@ +##dup_advsimd_elt_execute +CheckFPAdvSIMDEnabled64(); +bits(idxdsize) operand = V[n]; +bits(datasize) result; +bits(esize) element; + +element = Elem[operand, index, esize]; +for e = 0 to elements-1 + Elem[result, e, esize] = element; +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/dup_advsimd_gen b/instructionAPI/ISA_ps/dup_advsimd_gen new file mode 100644 index 0000000000..94cd5d545c --- /dev/null +++ b/instructionAPI/ISA_ps/dup_advsimd_gen @@ -0,0 +1,9 @@ +##dup_advsimd_gen_execute +CheckFPAdvSIMDEnabled64(); +bits(esize) element = X[n]; +bits(datasize) result; + +for e = 0 to elements-1 + Elem[result, e, esize] = element; +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/encodingindex b/instructionAPI/ISA_ps/encodingindex new file mode 100644 index 0000000000..e69de29bb2 diff --git a/instructionAPI/ISA_ps/enumerated-symbol-accounts b/instructionAPI/ISA_ps/enumerated-symbol-accounts new file mode 100644 index 0000000000..e69de29bb2 diff --git a/instructionAPI/ISA_ps/eon b/instructionAPI/ISA_ps/eon new file mode 100644 index 0000000000..f1937d37b0 --- /dev/null +++ b/instructionAPI/ISA_ps/eon @@ -0,0 +1,20 @@ +##eon_execute +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount); + +if invert then operand2 = NOT(operand2) end; + +case op of + when LogicalOp_AND result = operand1 AND operand2; + end + when LogicalOp_ORR result = operand1 OR operand2; + end + when LogicalOp_EOR result = operand1 EOR operand2; + end + +if setflags then + PSTATE. = result:IsZeroBit(result):00; +end + +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/eor_advsimd b/instructionAPI/ISA_ps/eor_advsimd new file mode 100644 index 0000000000..5b1d327ecc --- /dev/null +++ b/instructionAPI/ISA_ps/eor_advsimd @@ -0,0 +1,31 @@ +##eor_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1; +bits(datasize) operand2; +bits(datasize) operand3; +bits(datasize) operand4 = V[n]; + +case op of + when VBitOp_VEOR + operand1 = V[m]; + operand2 = Zeros(64); + operand3 = Ones(); + end + when VBitOp_VBSL + operand1 = V[m]; + operand2 = operand1; + operand3 = V[d]; + end + when VBitOp_VBIT + operand1 = V[d]; + operand2 = operand1; + operand3 = V[m]; + end + when VBitOp_VBIF + operand1 = V[d]; + operand2 = operand1; + operand3 = NOT(V[m]); + end + +V[d] = operand1 EOR ((operand2 EOR operand4) AND operand3); +@@ diff --git a/instructionAPI/ISA_ps/eor_log_imm b/instructionAPI/ISA_ps/eor_log_imm new file mode 100644 index 0000000000..c175a08831 --- /dev/null +++ b/instructionAPI/ISA_ps/eor_log_imm @@ -0,0 +1,23 @@ +##eor_log_imm_execute +bits(datasize) result; +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = imm; + +case op of + when LogicalOp_AND result = operand1 AND operand2; + end + when LogicalOp_ORR result = operand1 OR operand2; + end + when LogicalOp_EOR result = operand1 EOR operand2; + end + +if setflags then + PSTATE. = result:IsZeroBit(result):00; +end + +if d == 31 && !setflags then + SP[] = result; +else + X[d] = result; +end +@@ diff --git a/instructionAPI/ISA_ps/eor_log_shift b/instructionAPI/ISA_ps/eor_log_shift new file mode 100644 index 0000000000..52fe6b946c --- /dev/null +++ b/instructionAPI/ISA_ps/eor_log_shift @@ -0,0 +1,20 @@ +##eor_log_shift_execute +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount); + +if invert then operand2 = NOT(operand2) end; + +case op of + when LogicalOp_AND result = operand1 AND operand2; + end + when LogicalOp_ORR result = operand1 OR operand2; + end + when LogicalOp_EOR result = operand1 EOR operand2; + end + +if setflags then + PSTATE. = result:IsZeroBit(result):00; +end + +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/eret b/instructionAPI/ISA_ps/eret new file mode 100644 index 0000000000..2352a6db9a --- /dev/null +++ b/instructionAPI/ISA_ps/eret @@ -0,0 +1,3 @@ +##eret_execute +AArch64.ExceptionReturn(ELR[], SPSR[]); +@@ diff --git a/instructionAPI/ISA_ps/ext_advsimd b/instructionAPI/ISA_ps/ext_advsimd new file mode 100644 index 0000000000..e3a43c5687 --- /dev/null +++ b/instructionAPI/ISA_ps/ext_advsimd @@ -0,0 +1,8 @@ +##ext_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) hi = V[m]; +bits(datasize) lo = V[n]; +bits(datasize*2) concat = hi : lo; + +V[d] = concat; +@@ diff --git a/instructionAPI/ISA_ps/extr b/instructionAPI/ISA_ps/extr new file mode 100644 index 0000000000..38b04eb19e --- /dev/null +++ b/instructionAPI/ISA_ps/extr @@ -0,0 +1,10 @@ +##extr_execute +bits(datasize) result; +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = X[m]; +bits(2*datasize) concat = operand1:operand2; + +result = concat; + +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fabd_advsimd b/instructionAPI/ISA_ps/fabd_advsimd new file mode 100644 index 0000000000..ab7983dc6d --- /dev/null +++ b/instructionAPI/ISA_ps/fabd_advsimd @@ -0,0 +1,17 @@ +##fabd_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +bits(esize) element1; +bits(esize) element2; +bits(esize) diff; + +for e = 0 to elements-1 + element1 = Elem[operand1, e, esize]; + element2 = Elem[operand2, e, esize]; + diff = FPSub(element1, element2, FPCR); + Elem[result, e, esize] = if abs then FPAbs(diff) else diff; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fabs_advsimd b/instructionAPI/ISA_ps/fabs_advsimd new file mode 100644 index 0000000000..d2ddad583b --- /dev/null +++ b/instructionAPI/ISA_ps/fabs_advsimd @@ -0,0 +1,17 @@ +##fabs_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +bits(esize) element; + +for e = 0 to elements-1 + element = Elem[operand, e, esize]; + if neg then + element = FPNeg(element); + else + element = FPAbs(element); + end + Elem[result, e, esize] = element; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fabs_float b/instructionAPI/ISA_ps/fabs_float new file mode 100644 index 0000000000..6d1d335404 --- /dev/null +++ b/instructionAPI/ISA_ps/fabs_float @@ -0,0 +1,18 @@ +##fabs_float_execute +CheckFPAdvSIMDEnabled64(); + +bits(datasize) result; +bits(datasize) operand = V[n]; + +case fpop of + when FPUnaryOp_MOV result = operand; + end + when FPUnaryOp_ABS result = FPAbs(operand); + end + when FPUnaryOp_NEG result = FPNeg(operand); + end + when FPUnaryOp_SQRT result = FPSqrt(operand, FPCR); + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/facge_advsimd b/instructionAPI/ISA_ps/facge_advsimd new file mode 100644 index 0000000000..858e7b66f4 --- /dev/null +++ b/instructionAPI/ISA_ps/facge_advsimd @@ -0,0 +1,27 @@ +##facge_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +bits(esize) element1; +bits(esize) element2; +boolean test_passed; + +for e = 0 to elements-1 + element1 = Elem[operand1, e, esize]; + element2 = Elem[operand2, e, esize]; + if abs then + element1 = FPAbs(element1); + element2 = FPAbs(element2); + end + case cmp of + when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR); + end + when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR); + end + when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR); + Elem[result, e, esize] = if test_passed then Ones() else Zeros(64); + + end +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/facgt_advsimd b/instructionAPI/ISA_ps/facgt_advsimd new file mode 100644 index 0000000000..c5ea8b84ca --- /dev/null +++ b/instructionAPI/ISA_ps/facgt_advsimd @@ -0,0 +1,27 @@ +##facgt_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +bits(esize) element1; +bits(esize) element2; +boolean test_passed; + +for e = 0 to elements-1 + element1 = Elem[operand1, e, esize]; + element2 = Elem[operand2, e, esize]; + if abs then + element1 = FPAbs(element1); + element2 = FPAbs(element2); + end + case cmp of + when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR); + end + when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR); + end + when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR); + Elem[result, e, esize] = if test_passed then Ones() else Zeros(64); + + end +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fadd_advsimd b/instructionAPI/ISA_ps/fadd_advsimd new file mode 100644 index 0000000000..a2f824487a --- /dev/null +++ b/instructionAPI/ISA_ps/fadd_advsimd @@ -0,0 +1,21 @@ +##fadd_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +bits(2*datasize) concat = operand2:operand1; +bits(esize) element1; +bits(esize) element2; + +for e = 0 to elements-1 + if pair then + element1 = Elem[concat, 2*e, esize]; + element2 = Elem[concat, (2*e)+1, esize]; + else + element1 = Elem[operand1, e, esize]; + element2 = Elem[operand2, e, esize]; + end + Elem[result, e, esize] = FPAdd(element1, element2, FPCR); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fadd_float b/instructionAPI/ISA_ps/fadd_float new file mode 100644 index 0000000000..680272d9af --- /dev/null +++ b/instructionAPI/ISA_ps/fadd_float @@ -0,0 +1,14 @@ +##fadd_float_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) result; +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; + +if sub_op then + result = FPSub(operand1, operand2, FPCR); +else + result = FPAdd(operand1, operand2, FPCR); +end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/faddp_advsimd_pair b/instructionAPI/ISA_ps/faddp_advsimd_pair new file mode 100644 index 0000000000..e8916680ff --- /dev/null +++ b/instructionAPI/ISA_ps/faddp_advsimd_pair @@ -0,0 +1,5 @@ +##faddp_advsimd_pair_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +V[d] = Reduce(op, operand, esize); +@@ diff --git a/instructionAPI/ISA_ps/faddp_advsimd_vec b/instructionAPI/ISA_ps/faddp_advsimd_vec new file mode 100644 index 0000000000..d72d1162bf --- /dev/null +++ b/instructionAPI/ISA_ps/faddp_advsimd_vec @@ -0,0 +1,21 @@ +##faddp_advsimd_vec_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +bits(2*datasize) concat = operand2:operand1; +bits(esize) element1; +bits(esize) element2; + +for e = 0 to elements-1 + if pair then + element1 = Elem[concat, 2*e, esize]; + element2 = Elem[concat, (2*e)+1, esize]; + else + element1 = Elem[operand1, e, esize]; + element2 = Elem[operand2, e, esize]; + end + Elem[result, e, esize] = FPAdd(element1, element2, FPCR); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fccmp_float b/instructionAPI/ISA_ps/fccmp_float new file mode 100644 index 0000000000..94df7c7850 --- /dev/null +++ b/instructionAPI/ISA_ps/fccmp_float @@ -0,0 +1,13 @@ +##fccmp_float_execute +CheckFPAdvSIMDEnabled64(); + +bits(datasize) operand1 = V[n]; +bits(datasize) operand2; + +operand2 = V[m]; + +if ConditionHolds(condition) then + flags = FPCompare(operand1, operand2, signal_all_nans, FPCR); +end +PSTATE. = flags; +@@ diff --git a/instructionAPI/ISA_ps/fccmpe_float b/instructionAPI/ISA_ps/fccmpe_float new file mode 100644 index 0000000000..d2cbe0b03d --- /dev/null +++ b/instructionAPI/ISA_ps/fccmpe_float @@ -0,0 +1,13 @@ +##fccmpe_float_execute +CheckFPAdvSIMDEnabled64(); + +bits(datasize) operand1 = V[n]; +bits(datasize) operand2; + +operand2 = V[m]; + +if ConditionHolds(condition) then + flags = FPCompare(operand1, operand2, signal_all_nans, FPCR); +end +PSTATE. = flags; +@@ diff --git a/instructionAPI/ISA_ps/fcmeq_advsimd_reg b/instructionAPI/ISA_ps/fcmeq_advsimd_reg new file mode 100644 index 0000000000..c5651a89b6 --- /dev/null +++ b/instructionAPI/ISA_ps/fcmeq_advsimd_reg @@ -0,0 +1,27 @@ +##fcmeq_advsimd_reg_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +bits(esize) element1; +bits(esize) element2; +boolean test_passed; + +for e = 0 to elements-1 + element1 = Elem[operand1, e, esize]; + element2 = Elem[operand2, e, esize]; + if abs then + element1 = FPAbs(element1); + element2 = FPAbs(element2); + end + case cmp of + when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR); + end + when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR); + end + when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR); + Elem[result, e, esize] = if test_passed then Ones() else Zeros(64); + + end +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fcmeq_advsimd_zero b/instructionAPI/ISA_ps/fcmeq_advsimd_zero new file mode 100644 index 0000000000..1ff7de3121 --- /dev/null +++ b/instructionAPI/ISA_ps/fcmeq_advsimd_zero @@ -0,0 +1,25 @@ +##fcmeq_advsimd_zero_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +bits(esize) zero = FPZero(0); +bits(esize) element; +boolean test_passed; + +for e = 0 to elements-1 + element = Elem[operand, e, esize]; + case comparison of + when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); + end + when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); + end + when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); + end + when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); + end + when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); + Elem[result, e, esize] = if test_passed then Ones() else Zeros(64); + + end +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fcmge_advsimd_reg b/instructionAPI/ISA_ps/fcmge_advsimd_reg new file mode 100644 index 0000000000..8bd1888d5c --- /dev/null +++ b/instructionAPI/ISA_ps/fcmge_advsimd_reg @@ -0,0 +1,27 @@ +##fcmge_advsimd_reg_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +bits(esize) element1; +bits(esize) element2; +boolean test_passed; + +for e = 0 to elements-1 + element1 = Elem[operand1, e, esize]; + element2 = Elem[operand2, e, esize]; + if abs then + element1 = FPAbs(element1); + element2 = FPAbs(element2); + end + case cmp of + when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR); + end + when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR); + end + when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR); + Elem[result, e, esize] = if test_passed then Ones() else Zeros(64); + + end +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fcmge_advsimd_zero b/instructionAPI/ISA_ps/fcmge_advsimd_zero new file mode 100644 index 0000000000..1ff2d39662 --- /dev/null +++ b/instructionAPI/ISA_ps/fcmge_advsimd_zero @@ -0,0 +1,25 @@ +##fcmge_advsimd_zero_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +bits(esize) zero = FPZero(0); +bits(esize) element; +boolean test_passed; + +for e = 0 to elements-1 + element = Elem[operand, e, esize]; + case comparison of + when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); + end + when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); + end + when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); + end + when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); + end + when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); + Elem[result, e, esize] = if test_passed then Ones() else Zeros(64); + + end +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fcmgt_advsimd_reg b/instructionAPI/ISA_ps/fcmgt_advsimd_reg new file mode 100644 index 0000000000..919ff6fdc8 --- /dev/null +++ b/instructionAPI/ISA_ps/fcmgt_advsimd_reg @@ -0,0 +1,27 @@ +##fcmgt_advsimd_reg_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +bits(esize) element1; +bits(esize) element2; +boolean test_passed; + +for e = 0 to elements-1 + element1 = Elem[operand1, e, esize]; + element2 = Elem[operand2, e, esize]; + if abs then + element1 = FPAbs(element1); + element2 = FPAbs(element2); + end + case cmp of + when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR); + end + when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR); + end + when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR); + Elem[result, e, esize] = if test_passed then Ones() else Zeros(64); + + end +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fcmgt_advsimd_zero b/instructionAPI/ISA_ps/fcmgt_advsimd_zero new file mode 100644 index 0000000000..6365a16a40 --- /dev/null +++ b/instructionAPI/ISA_ps/fcmgt_advsimd_zero @@ -0,0 +1,25 @@ +##fcmgt_advsimd_zero_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +bits(esize) zero = FPZero(0); +bits(esize) element; +boolean test_passed; + +for e = 0 to elements-1 + element = Elem[operand, e, esize]; + case comparison of + when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); + end + when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); + end + when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); + end + when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); + end + when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); + Elem[result, e, esize] = if test_passed then Ones() else Zeros(64); + + end +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fcmle_advsimd b/instructionAPI/ISA_ps/fcmle_advsimd new file mode 100644 index 0000000000..fd933ba0f1 --- /dev/null +++ b/instructionAPI/ISA_ps/fcmle_advsimd @@ -0,0 +1,25 @@ +##fcmle_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +bits(esize) zero = FPZero(0); +bits(esize) element; +boolean test_passed; + +for e = 0 to elements-1 + element = Elem[operand, e, esize]; + case comparison of + when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); + end + when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); + end + when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); + end + when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); + end + when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); + Elem[result, e, esize] = if test_passed then Ones() else Zeros(64); + + end +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fcmlt_advsimd b/instructionAPI/ISA_ps/fcmlt_advsimd new file mode 100644 index 0000000000..ba1487d1b9 --- /dev/null +++ b/instructionAPI/ISA_ps/fcmlt_advsimd @@ -0,0 +1,25 @@ +##fcmlt_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +bits(esize) zero = FPZero(0); +bits(esize) element; +boolean test_passed; + +for e = 0 to elements-1 + element = Elem[operand, e, esize]; + case comparison of + when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); + end + when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); + end + when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); + end + when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); + end + when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); + Elem[result, e, esize] = if test_passed then Ones() else Zeros(64); + + end +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fcmp_float b/instructionAPI/ISA_ps/fcmp_float new file mode 100644 index 0000000000..ba2622bc59 --- /dev/null +++ b/instructionAPI/ISA_ps/fcmp_float @@ -0,0 +1,10 @@ +##fcmp_float_execute +CheckFPAdvSIMDEnabled64(); + +bits(datasize) operand1 = V[n]; +bits(datasize) operand2; + +operand2 = if cmp_with_zero then FPZero(0) else V[m]; + +PSTATE. = FPCompare(operand1, operand2, signal_all_nans, FPCR); +@@ diff --git a/instructionAPI/ISA_ps/fcmpe_float b/instructionAPI/ISA_ps/fcmpe_float new file mode 100644 index 0000000000..78cc1b7a32 --- /dev/null +++ b/instructionAPI/ISA_ps/fcmpe_float @@ -0,0 +1,10 @@ +##fcmpe_float_execute +CheckFPAdvSIMDEnabled64(); + +bits(datasize) operand1 = V[n]; +bits(datasize) operand2; + +operand2 = if cmp_with_zero then FPZero(0) else V[m]; + +PSTATE. = FPCompare(operand1, operand2, signal_all_nans, FPCR); +@@ diff --git a/instructionAPI/ISA_ps/fcsel_float b/instructionAPI/ISA_ps/fcsel_float new file mode 100644 index 0000000000..3120f26ec1 --- /dev/null +++ b/instructionAPI/ISA_ps/fcsel_float @@ -0,0 +1,8 @@ +##fcsel_float_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) result; + +result = if ConditionHolds(condition) then V[n] else V[m]; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fcvt_float b/instructionAPI/ISA_ps/fcvt_float new file mode 100644 index 0000000000..90f7b833d1 --- /dev/null +++ b/instructionAPI/ISA_ps/fcvt_float @@ -0,0 +1,9 @@ +##fcvt_float_execute +CheckFPAdvSIMDEnabled64(); + +bits(dstsize) result; +bits(srcsize) operand = V[n]; + +result = FPConvert(operand, FPCR); +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fcvtas_advsimd b/instructionAPI/ISA_ps/fcvtas_advsimd new file mode 100644 index 0000000000..c23e81542c --- /dev/null +++ b/instructionAPI/ISA_ps/fcvtas_advsimd @@ -0,0 +1,12 @@ +##fcvtas_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +bits(esize) element; + +for e = 0 to elements-1 + element = Elem[operand, e, esize]; + Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fcvtas_float b/instructionAPI/ISA_ps/fcvtas_float new file mode 100644 index 0000000000..1a99acdaf2 --- /dev/null +++ b/instructionAPI/ISA_ps/fcvtas_float @@ -0,0 +1,26 @@ +##fcvtas_float_execute +CheckFPAdvSIMDEnabled64(); + +bits(fltsize) fltval; +bits(intsize) intval; + +case op of + when FPConvOp_CVT_FtoI + fltval = V[n]; + intval = FPToFixed(fltval, 0, unsigned, FPCR, rounding); + X[d] = intval; + end + when FPConvOp_CVT_ItoF + intval = X[n]; + fltval = FixedToFP(intval, 0, unsigned, FPCR, rounding); + V[d] = fltval; + end + when FPConvOp_MOV_FtoI + intval = Vpart[n,part]; + X[d] = intval; + end + when FPConvOp_MOV_ItoF + intval = X[n]; + Vpart[d,part] = intval; + end +@@ diff --git a/instructionAPI/ISA_ps/fcvtau_advsimd b/instructionAPI/ISA_ps/fcvtau_advsimd new file mode 100644 index 0000000000..5cc271dd65 --- /dev/null +++ b/instructionAPI/ISA_ps/fcvtau_advsimd @@ -0,0 +1,12 @@ +##fcvtau_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +bits(esize) element; + +for e = 0 to elements-1 + element = Elem[operand, e, esize]; + Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fcvtau_float b/instructionAPI/ISA_ps/fcvtau_float new file mode 100644 index 0000000000..f3200fad4c --- /dev/null +++ b/instructionAPI/ISA_ps/fcvtau_float @@ -0,0 +1,26 @@ +##fcvtau_float_execute +CheckFPAdvSIMDEnabled64(); + +bits(fltsize) fltval; +bits(intsize) intval; + +case op of + when FPConvOp_CVT_FtoI + fltval = V[n]; + intval = FPToFixed(fltval, 0, unsigned, FPCR, rounding); + X[d] = intval; + end + when FPConvOp_CVT_ItoF + intval = X[n]; + fltval = FixedToFP(intval, 0, unsigned, FPCR, rounding); + V[d] = fltval; + end + when FPConvOp_MOV_FtoI + intval = Vpart[n,part]; + X[d] = intval; + end + when FPConvOp_MOV_ItoF + intval = X[n]; + Vpart[d,part] = intval; + end +@@ diff --git a/instructionAPI/ISA_ps/fcvtl_advsimd b/instructionAPI/ISA_ps/fcvtl_advsimd new file mode 100644 index 0000000000..fe3ef3888a --- /dev/null +++ b/instructionAPI/ISA_ps/fcvtl_advsimd @@ -0,0 +1,10 @@ +##fcvtl_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = Vpart[n, part]; +bits(2*datasize) result; + +for e = 0 to elements-1 + Elem[result, e, 2*esize] = FPConvert(Elem[operand, e, esize], FPCR); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fcvtms_advsimd b/instructionAPI/ISA_ps/fcvtms_advsimd new file mode 100644 index 0000000000..00d832183f --- /dev/null +++ b/instructionAPI/ISA_ps/fcvtms_advsimd @@ -0,0 +1,12 @@ +##fcvtms_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +bits(esize) element; + +for e = 0 to elements-1 + element = Elem[operand, e, esize]; + Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fcvtms_float b/instructionAPI/ISA_ps/fcvtms_float new file mode 100644 index 0000000000..9631ae70cc --- /dev/null +++ b/instructionAPI/ISA_ps/fcvtms_float @@ -0,0 +1,26 @@ +##fcvtms_float_execute +CheckFPAdvSIMDEnabled64(); + +bits(fltsize) fltval; +bits(intsize) intval; + +case op of + when FPConvOp_CVT_FtoI + fltval = V[n]; + intval = FPToFixed(fltval, 0, unsigned, FPCR, rounding); + X[d] = intval; + end + when FPConvOp_CVT_ItoF + intval = X[n]; + fltval = FixedToFP(intval, 0, unsigned, FPCR, rounding); + V[d] = fltval; + end + when FPConvOp_MOV_FtoI + intval = Vpart[n,part]; + X[d] = intval; + end + when FPConvOp_MOV_ItoF + intval = X[n]; + Vpart[d,part] = intval; + end +@@ diff --git a/instructionAPI/ISA_ps/fcvtmu_advsimd b/instructionAPI/ISA_ps/fcvtmu_advsimd new file mode 100644 index 0000000000..35ea3cb1e6 --- /dev/null +++ b/instructionAPI/ISA_ps/fcvtmu_advsimd @@ -0,0 +1,12 @@ +##fcvtmu_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +bits(esize) element; + +for e = 0 to elements-1 + element = Elem[operand, e, esize]; + Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fcvtmu_float b/instructionAPI/ISA_ps/fcvtmu_float new file mode 100644 index 0000000000..3089f148e8 --- /dev/null +++ b/instructionAPI/ISA_ps/fcvtmu_float @@ -0,0 +1,26 @@ +##fcvtmu_float_execute +CheckFPAdvSIMDEnabled64(); + +bits(fltsize) fltval; +bits(intsize) intval; + +case op of + when FPConvOp_CVT_FtoI + fltval = V[n]; + intval = FPToFixed(fltval, 0, unsigned, FPCR, rounding); + X[d] = intval; + end + when FPConvOp_CVT_ItoF + intval = X[n]; + fltval = FixedToFP(intval, 0, unsigned, FPCR, rounding); + V[d] = fltval; + end + when FPConvOp_MOV_FtoI + intval = Vpart[n,part]; + X[d] = intval; + end + when FPConvOp_MOV_ItoF + intval = X[n]; + Vpart[d,part] = intval; + end +@@ diff --git a/instructionAPI/ISA_ps/fcvtn_advsimd b/instructionAPI/ISA_ps/fcvtn_advsimd new file mode 100644 index 0000000000..6d2678e7ff --- /dev/null +++ b/instructionAPI/ISA_ps/fcvtn_advsimd @@ -0,0 +1,10 @@ +##fcvtn_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(2*datasize) operand = V[n]; +bits(datasize) result; + +for e = 0 to elements-1 + Elem[result, e, esize] = FPConvert(Elem[operand, e, 2*esize], FPCR); + +Vpart[d, part] = result; +@@ diff --git a/instructionAPI/ISA_ps/fcvtns_advsimd b/instructionAPI/ISA_ps/fcvtns_advsimd new file mode 100644 index 0000000000..5648cb59f2 --- /dev/null +++ b/instructionAPI/ISA_ps/fcvtns_advsimd @@ -0,0 +1,12 @@ +##fcvtns_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +bits(esize) element; + +for e = 0 to elements-1 + element = Elem[operand, e, esize]; + Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fcvtns_float b/instructionAPI/ISA_ps/fcvtns_float new file mode 100644 index 0000000000..f8d16d0703 --- /dev/null +++ b/instructionAPI/ISA_ps/fcvtns_float @@ -0,0 +1,26 @@ +##fcvtns_float_execute +CheckFPAdvSIMDEnabled64(); + +bits(fltsize) fltval; +bits(intsize) intval; + +case op of + when FPConvOp_CVT_FtoI + fltval = V[n]; + intval = FPToFixed(fltval, 0, unsigned, FPCR, rounding); + X[d] = intval; + end + when FPConvOp_CVT_ItoF + intval = X[n]; + fltval = FixedToFP(intval, 0, unsigned, FPCR, rounding); + V[d] = fltval; + end + when FPConvOp_MOV_FtoI + intval = Vpart[n,part]; + X[d] = intval; + end + when FPConvOp_MOV_ItoF + intval = X[n]; + Vpart[d,part] = intval; + end +@@ diff --git a/instructionAPI/ISA_ps/fcvtnu_advsimd b/instructionAPI/ISA_ps/fcvtnu_advsimd new file mode 100644 index 0000000000..43461fa128 --- /dev/null +++ b/instructionAPI/ISA_ps/fcvtnu_advsimd @@ -0,0 +1,12 @@ +##fcvtnu_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +bits(esize) element; + +for e = 0 to elements-1 + element = Elem[operand, e, esize]; + Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fcvtnu_float b/instructionAPI/ISA_ps/fcvtnu_float new file mode 100644 index 0000000000..7b800dc4ef --- /dev/null +++ b/instructionAPI/ISA_ps/fcvtnu_float @@ -0,0 +1,26 @@ +##fcvtnu_float_execute +CheckFPAdvSIMDEnabled64(); + +bits(fltsize) fltval; +bits(intsize) intval; + +case op of + when FPConvOp_CVT_FtoI + fltval = V[n]; + intval = FPToFixed(fltval, 0, unsigned, FPCR, rounding); + X[d] = intval; + end + when FPConvOp_CVT_ItoF + intval = X[n]; + fltval = FixedToFP(intval, 0, unsigned, FPCR, rounding); + V[d] = fltval; + end + when FPConvOp_MOV_FtoI + intval = Vpart[n,part]; + X[d] = intval; + end + when FPConvOp_MOV_ItoF + intval = X[n]; + Vpart[d,part] = intval; + end +@@ diff --git a/instructionAPI/ISA_ps/fcvtps_advsimd b/instructionAPI/ISA_ps/fcvtps_advsimd new file mode 100644 index 0000000000..80cb793039 --- /dev/null +++ b/instructionAPI/ISA_ps/fcvtps_advsimd @@ -0,0 +1,12 @@ +##fcvtps_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +bits(esize) element; + +for e = 0 to elements-1 + element = Elem[operand, e, esize]; + Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fcvtps_float b/instructionAPI/ISA_ps/fcvtps_float new file mode 100644 index 0000000000..a11f36fe20 --- /dev/null +++ b/instructionAPI/ISA_ps/fcvtps_float @@ -0,0 +1,26 @@ +##fcvtps_float_execute +CheckFPAdvSIMDEnabled64(); + +bits(fltsize) fltval; +bits(intsize) intval; + +case op of + when FPConvOp_CVT_FtoI + fltval = V[n]; + intval = FPToFixed(fltval, 0, unsigned, FPCR, rounding); + X[d] = intval; + end + when FPConvOp_CVT_ItoF + intval = X[n]; + fltval = FixedToFP(intval, 0, unsigned, FPCR, rounding); + V[d] = fltval; + end + when FPConvOp_MOV_FtoI + intval = Vpart[n,part]; + X[d] = intval; + end + when FPConvOp_MOV_ItoF + intval = X[n]; + Vpart[d,part] = intval; + end +@@ diff --git a/instructionAPI/ISA_ps/fcvtpu_advsimd b/instructionAPI/ISA_ps/fcvtpu_advsimd new file mode 100644 index 0000000000..d8ae97361c --- /dev/null +++ b/instructionAPI/ISA_ps/fcvtpu_advsimd @@ -0,0 +1,12 @@ +##fcvtpu_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +bits(esize) element; + +for e = 0 to elements-1 + element = Elem[operand, e, esize]; + Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fcvtpu_float b/instructionAPI/ISA_ps/fcvtpu_float new file mode 100644 index 0000000000..48e2c93c86 --- /dev/null +++ b/instructionAPI/ISA_ps/fcvtpu_float @@ -0,0 +1,26 @@ +##fcvtpu_float_execute +CheckFPAdvSIMDEnabled64(); + +bits(fltsize) fltval; +bits(intsize) intval; + +case op of + when FPConvOp_CVT_FtoI + fltval = V[n]; + intval = FPToFixed(fltval, 0, unsigned, FPCR, rounding); + X[d] = intval; + end + when FPConvOp_CVT_ItoF + intval = X[n]; + fltval = FixedToFP(intval, 0, unsigned, FPCR, rounding); + V[d] = fltval; + end + when FPConvOp_MOV_FtoI + intval = Vpart[n,part]; + X[d] = intval; + end + when FPConvOp_MOV_ItoF + intval = X[n]; + Vpart[d,part] = intval; + end +@@ diff --git a/instructionAPI/ISA_ps/fcvtxn_advsimd b/instructionAPI/ISA_ps/fcvtxn_advsimd new file mode 100644 index 0000000000..7654de9e23 --- /dev/null +++ b/instructionAPI/ISA_ps/fcvtxn_advsimd @@ -0,0 +1,10 @@ +##fcvtxn_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(2*datasize) operand = V[n]; +bits(datasize) result; + +for e = 0 to elements-1 + Elem[result, e, esize] = FPConvert(Elem[operand, e, 2*esize], FPCR, FPRounding_ODD); + +Vpart[d, part] = result; +@@ diff --git a/instructionAPI/ISA_ps/fcvtzs_advsimd_fix b/instructionAPI/ISA_ps/fcvtzs_advsimd_fix new file mode 100644 index 0000000000..4085f8cacb --- /dev/null +++ b/instructionAPI/ISA_ps/fcvtzs_advsimd_fix @@ -0,0 +1,12 @@ +##fcvtzs_advsimd_fix_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +bits(esize) element; + +for e = 0 to elements-1 + element = Elem[operand, e, esize]; + Elem[result, e, esize] = FPToFixed(element, fracbits, unsigned, FPCR, rounding); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fcvtzs_advsimd_int b/instructionAPI/ISA_ps/fcvtzs_advsimd_int new file mode 100644 index 0000000000..4078dd581e --- /dev/null +++ b/instructionAPI/ISA_ps/fcvtzs_advsimd_int @@ -0,0 +1,12 @@ +##fcvtzs_advsimd_int_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +bits(esize) element; + +for e = 0 to elements-1 + element = Elem[operand, e, esize]; + Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fcvtzs_float_fix b/instructionAPI/ISA_ps/fcvtzs_float_fix new file mode 100644 index 0000000000..fd1df7b6aa --- /dev/null +++ b/instructionAPI/ISA_ps/fcvtzs_float_fix @@ -0,0 +1,18 @@ +##fcvtzs_float_fix_execute +CheckFPAdvSIMDEnabled64(); + +bits(fltsize) fltval; +bits(intsize) intval; + +case op of + when FPConvOp_CVT_FtoI + fltval = V[n]; + intval = FPToFixed(fltval, fracbits, unsigned, FPCR, rounding); + X[d] = intval; + end + when FPConvOp_CVT_ItoF + intval = X[n]; + fltval = FixedToFP(intval, fracbits, unsigned, FPCR, rounding); + V[d] = fltval; + end +@@ diff --git a/instructionAPI/ISA_ps/fcvtzs_float_int b/instructionAPI/ISA_ps/fcvtzs_float_int new file mode 100644 index 0000000000..7215d31d8a --- /dev/null +++ b/instructionAPI/ISA_ps/fcvtzs_float_int @@ -0,0 +1,26 @@ +##fcvtzs_float_int_execute +CheckFPAdvSIMDEnabled64(); + +bits(fltsize) fltval; +bits(intsize) intval; + +case op of + when FPConvOp_CVT_FtoI + fltval = V[n]; + intval = FPToFixed(fltval, 0, unsigned, FPCR, rounding); + X[d] = intval; + end + when FPConvOp_CVT_ItoF + intval = X[n]; + fltval = FixedToFP(intval, 0, unsigned, FPCR, rounding); + V[d] = fltval; + end + when FPConvOp_MOV_FtoI + intval = Vpart[n,part]; + X[d] = intval; + end + when FPConvOp_MOV_ItoF + intval = X[n]; + Vpart[d,part] = intval; + end +@@ diff --git a/instructionAPI/ISA_ps/fcvtzu_advsimd_fix b/instructionAPI/ISA_ps/fcvtzu_advsimd_fix new file mode 100644 index 0000000000..1f631e1e63 --- /dev/null +++ b/instructionAPI/ISA_ps/fcvtzu_advsimd_fix @@ -0,0 +1,12 @@ +##fcvtzu_advsimd_fix_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +bits(esize) element; + +for e = 0 to elements-1 + element = Elem[operand, e, esize]; + Elem[result, e, esize] = FPToFixed(element, fracbits, unsigned, FPCR, rounding); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fcvtzu_advsimd_int b/instructionAPI/ISA_ps/fcvtzu_advsimd_int new file mode 100644 index 0000000000..00935265b5 --- /dev/null +++ b/instructionAPI/ISA_ps/fcvtzu_advsimd_int @@ -0,0 +1,12 @@ +##fcvtzu_advsimd_int_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +bits(esize) element; + +for e = 0 to elements-1 + element = Elem[operand, e, esize]; + Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fcvtzu_float_fix b/instructionAPI/ISA_ps/fcvtzu_float_fix new file mode 100644 index 0000000000..3e8f584c73 --- /dev/null +++ b/instructionAPI/ISA_ps/fcvtzu_float_fix @@ -0,0 +1,18 @@ +##fcvtzu_float_fix_execute +CheckFPAdvSIMDEnabled64(); + +bits(fltsize) fltval; +bits(intsize) intval; + +case op of + when FPConvOp_CVT_FtoI + fltval = V[n]; + intval = FPToFixed(fltval, fracbits, unsigned, FPCR, rounding); + X[d] = intval; + end + when FPConvOp_CVT_ItoF + intval = X[n]; + fltval = FixedToFP(intval, fracbits, unsigned, FPCR, rounding); + V[d] = fltval; + end +@@ diff --git a/instructionAPI/ISA_ps/fcvtzu_float_int b/instructionAPI/ISA_ps/fcvtzu_float_int new file mode 100644 index 0000000000..70caf301b4 --- /dev/null +++ b/instructionAPI/ISA_ps/fcvtzu_float_int @@ -0,0 +1,26 @@ +##fcvtzu_float_int_execute +CheckFPAdvSIMDEnabled64(); + +bits(fltsize) fltval; +bits(intsize) intval; + +case op of + when FPConvOp_CVT_FtoI + fltval = V[n]; + intval = FPToFixed(fltval, 0, unsigned, FPCR, rounding); + X[d] = intval; + end + when FPConvOp_CVT_ItoF + intval = X[n]; + fltval = FixedToFP(intval, 0, unsigned, FPCR, rounding); + V[d] = fltval; + end + when FPConvOp_MOV_FtoI + intval = Vpart[n,part]; + X[d] = intval; + end + when FPConvOp_MOV_ItoF + intval = X[n]; + Vpart[d,part] = intval; + end +@@ diff --git a/instructionAPI/ISA_ps/fdiv_advsimd b/instructionAPI/ISA_ps/fdiv_advsimd new file mode 100644 index 0000000000..0b880e9a1a --- /dev/null +++ b/instructionAPI/ISA_ps/fdiv_advsimd @@ -0,0 +1,15 @@ +##fdiv_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +bits(esize) element1; +bits(esize) element2; + +for e = 0 to elements-1 + element1 = Elem[operand1, e, esize]; + element2 = Elem[operand2, e, esize]; + Elem[result, e, esize] = FPDiv(element1, element2, FPCR); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fdiv_float b/instructionAPI/ISA_ps/fdiv_float new file mode 100644 index 0000000000..8c05f579b2 --- /dev/null +++ b/instructionAPI/ISA_ps/fdiv_float @@ -0,0 +1,10 @@ +##fdiv_float_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) result; +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; + +result = FPDiv(operand1, operand2, FPCR); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fmadd_float b/instructionAPI/ISA_ps/fmadd_float new file mode 100644 index 0000000000..41f5e09877 --- /dev/null +++ b/instructionAPI/ISA_ps/fmadd_float @@ -0,0 +1,13 @@ +##fmadd_float_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) result; +bits(datasize) operanda = V[a]; +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; + +if opa_neg then operanda = FPNeg(operanda); +if op1_neg then operand1 = FPNeg(operand1); +result = FPMulAdd(operanda, operand1, operand2, FPCR); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fmax_advsimd b/instructionAPI/ISA_ps/fmax_advsimd new file mode 100644 index 0000000000..f3a8d2ba20 --- /dev/null +++ b/instructionAPI/ISA_ps/fmax_advsimd @@ -0,0 +1,26 @@ +##fmax_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +bits(2*datasize) concat = operand2:operand1; +bits(esize) element1; +bits(esize) element2; + +for e = 0 to elements-1 + if pair then + element1 = Elem[concat, 2*e, esize]; + element2 = Elem[concat, (2*e)+1, esize]; + else + element1 = Elem[operand1, e, esize]; + element2 = Elem[operand2, e, esize]; + end + + if minimum then + Elem[result, e, esize] = FPMin(element1, element2, FPCR); + else + Elem[result, e, esize] = FPMax(element1, element2, FPCR); + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fmax_float b/instructionAPI/ISA_ps/fmax_float new file mode 100644 index 0000000000..d60b727444 --- /dev/null +++ b/instructionAPI/ISA_ps/fmax_float @@ -0,0 +1,18 @@ +##fmax_float_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) result; +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; + +case operation of + when FPMaxMinOp_MAX result = FPMax(operand1, operand2, FPCR); + end + when FPMaxMinOp_MIN result = FPMin(operand1, operand2, FPCR); + end + when FPMaxMinOp_MAXNUM result = FPMaxNum(operand1, operand2, FPCR); + end + when FPMaxMinOp_MINNUM result = FPMinNum(operand1, operand2, FPCR); + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fmaxnm_advsimd b/instructionAPI/ISA_ps/fmaxnm_advsimd new file mode 100644 index 0000000000..b554d07383 --- /dev/null +++ b/instructionAPI/ISA_ps/fmaxnm_advsimd @@ -0,0 +1,26 @@ +##fmaxnm_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +bits(2*datasize) concat = operand2:operand1; +bits(esize) element1; +bits(esize) element2; + +for e = 0 to elements-1 + if pair then + element1 = Elem[concat, 2*e, esize]; + element2 = Elem[concat, (2*e)+1, esize]; + else + element1 = Elem[operand1, e, esize]; + element2 = Elem[operand2, e, esize]; + end + + if minimum then + Elem[result, e, esize] = FPMinNum(element1, element2, FPCR); + else + Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR); + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fmaxnm_float b/instructionAPI/ISA_ps/fmaxnm_float new file mode 100644 index 0000000000..c4ffdf3716 --- /dev/null +++ b/instructionAPI/ISA_ps/fmaxnm_float @@ -0,0 +1,18 @@ +##fmaxnm_float_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) result; +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; + +case operation of + when FPMaxMinOp_MAX result = FPMax(operand1, operand2, FPCR); + end + when FPMaxMinOp_MIN result = FPMin(operand1, operand2, FPCR); + end + when FPMaxMinOp_MAXNUM result = FPMaxNum(operand1, operand2, FPCR); + end + when FPMaxMinOp_MINNUM result = FPMinNum(operand1, operand2, FPCR); + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fmaxnmp_advsimd_pair b/instructionAPI/ISA_ps/fmaxnmp_advsimd_pair new file mode 100644 index 0000000000..d3f14d9beb --- /dev/null +++ b/instructionAPI/ISA_ps/fmaxnmp_advsimd_pair @@ -0,0 +1,5 @@ +##fmaxnmp_advsimd_pair_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +V[d] = Reduce(op, operand, esize); +@@ diff --git a/instructionAPI/ISA_ps/fmaxnmp_advsimd_vec b/instructionAPI/ISA_ps/fmaxnmp_advsimd_vec new file mode 100644 index 0000000000..d6c8d9863a --- /dev/null +++ b/instructionAPI/ISA_ps/fmaxnmp_advsimd_vec @@ -0,0 +1,26 @@ +##fmaxnmp_advsimd_vec_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +bits(2*datasize) concat = operand2:operand1; +bits(esize) element1; +bits(esize) element2; + +for e = 0 to elements-1 + if pair then + element1 = Elem[concat, 2*e, esize]; + element2 = Elem[concat, (2*e)+1, esize]; + else + element1 = Elem[operand1, e, esize]; + element2 = Elem[operand2, e, esize]; + end + + if minimum then + Elem[result, e, esize] = FPMinNum(element1, element2, FPCR); + else + Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR); + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fmaxnmv_advsimd b/instructionAPI/ISA_ps/fmaxnmv_advsimd new file mode 100644 index 0000000000..930afc707e --- /dev/null +++ b/instructionAPI/ISA_ps/fmaxnmv_advsimd @@ -0,0 +1,5 @@ +##fmaxnmv_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +V[d] = Reduce(op, operand, esize); +@@ diff --git a/instructionAPI/ISA_ps/fmaxp_advsimd_pair b/instructionAPI/ISA_ps/fmaxp_advsimd_pair new file mode 100644 index 0000000000..01cd880017 --- /dev/null +++ b/instructionAPI/ISA_ps/fmaxp_advsimd_pair @@ -0,0 +1,5 @@ +##fmaxp_advsimd_pair_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +V[d] = Reduce(op, operand, esize); +@@ diff --git a/instructionAPI/ISA_ps/fmaxp_advsimd_vec b/instructionAPI/ISA_ps/fmaxp_advsimd_vec new file mode 100644 index 0000000000..631357df1c --- /dev/null +++ b/instructionAPI/ISA_ps/fmaxp_advsimd_vec @@ -0,0 +1,26 @@ +##fmaxp_advsimd_vec_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +bits(2*datasize) concat = operand2:operand1; +bits(esize) element1; +bits(esize) element2; + +for e = 0 to elements-1 + if pair then + element1 = Elem[concat, 2*e, esize]; + element2 = Elem[concat, (2*e)+1, esize]; + else + element1 = Elem[operand1, e, esize]; + element2 = Elem[operand2, e, esize]; + end + + if minimum then + Elem[result, e, esize] = FPMin(element1, element2, FPCR); + else + Elem[result, e, esize] = FPMax(element1, element2, FPCR); + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fmaxv_advsimd b/instructionAPI/ISA_ps/fmaxv_advsimd new file mode 100644 index 0000000000..a8711b1ae9 --- /dev/null +++ b/instructionAPI/ISA_ps/fmaxv_advsimd @@ -0,0 +1,5 @@ +##fmaxv_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +V[d] = Reduce(op, operand, esize); +@@ diff --git a/instructionAPI/ISA_ps/fmin_advsimd b/instructionAPI/ISA_ps/fmin_advsimd new file mode 100644 index 0000000000..072f86e81d --- /dev/null +++ b/instructionAPI/ISA_ps/fmin_advsimd @@ -0,0 +1,26 @@ +##fmin_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +bits(2*datasize) concat = operand2:operand1; +bits(esize) element1; +bits(esize) element2; + +for e = 0 to elements-1 + if pair then + element1 = Elem[concat, 2*e, esize]; + element2 = Elem[concat, (2*e)+1, esize]; + else + element1 = Elem[operand1, e, esize]; + element2 = Elem[operand2, e, esize]; + end + + if minimum then + Elem[result, e, esize] = FPMin(element1, element2, FPCR); + else + Elem[result, e, esize] = FPMax(element1, element2, FPCR); + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fmin_float b/instructionAPI/ISA_ps/fmin_float new file mode 100644 index 0000000000..b1621c2cf5 --- /dev/null +++ b/instructionAPI/ISA_ps/fmin_float @@ -0,0 +1,18 @@ +##fmin_float_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) result; +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; + +case operation of + when FPMaxMinOp_MAX result = FPMax(operand1, operand2, FPCR); + end + when FPMaxMinOp_MIN result = FPMin(operand1, operand2, FPCR); + end + when FPMaxMinOp_MAXNUM result = FPMaxNum(operand1, operand2, FPCR); + end + when FPMaxMinOp_MINNUM result = FPMinNum(operand1, operand2, FPCR); + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fminnm_advsimd b/instructionAPI/ISA_ps/fminnm_advsimd new file mode 100644 index 0000000000..f7e9f1cf4e --- /dev/null +++ b/instructionAPI/ISA_ps/fminnm_advsimd @@ -0,0 +1,26 @@ +##fminnm_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +bits(2*datasize) concat = operand2:operand1; +bits(esize) element1; +bits(esize) element2; + +for e = 0 to elements-1 + if pair then + element1 = Elem[concat, 2*e, esize]; + element2 = Elem[concat, (2*e)+1, esize]; + else + element1 = Elem[operand1, e, esize]; + element2 = Elem[operand2, e, esize]; + end + + if minimum then + Elem[result, e, esize] = FPMinNum(element1, element2, FPCR); + else + Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR); + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fminnm_float b/instructionAPI/ISA_ps/fminnm_float new file mode 100644 index 0000000000..25dfd087d9 --- /dev/null +++ b/instructionAPI/ISA_ps/fminnm_float @@ -0,0 +1,18 @@ +##fminnm_float_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) result; +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; + +case operation of + when FPMaxMinOp_MAX result = FPMax(operand1, operand2, FPCR); + end + when FPMaxMinOp_MIN result = FPMin(operand1, operand2, FPCR); + end + when FPMaxMinOp_MAXNUM result = FPMaxNum(operand1, operand2, FPCR); + end + when FPMaxMinOp_MINNUM result = FPMinNum(operand1, operand2, FPCR); + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fminnmp_advsimd_pair b/instructionAPI/ISA_ps/fminnmp_advsimd_pair new file mode 100644 index 0000000000..4b5202f7fd --- /dev/null +++ b/instructionAPI/ISA_ps/fminnmp_advsimd_pair @@ -0,0 +1,5 @@ +##fminnmp_advsimd_pair_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +V[d] = Reduce(op, operand, esize); +@@ diff --git a/instructionAPI/ISA_ps/fminnmp_advsimd_vec b/instructionAPI/ISA_ps/fminnmp_advsimd_vec new file mode 100644 index 0000000000..2f8f24ff03 --- /dev/null +++ b/instructionAPI/ISA_ps/fminnmp_advsimd_vec @@ -0,0 +1,26 @@ +##fminnmp_advsimd_vec_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +bits(2*datasize) concat = operand2:operand1; +bits(esize) element1; +bits(esize) element2; + +for e = 0 to elements-1 + if pair then + element1 = Elem[concat, 2*e, esize]; + element2 = Elem[concat, (2*e)+1, esize]; + else + element1 = Elem[operand1, e, esize]; + element2 = Elem[operand2, e, esize]; + end + + if minimum then + Elem[result, e, esize] = FPMinNum(element1, element2, FPCR); + else + Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR); + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fminnmv_advsimd b/instructionAPI/ISA_ps/fminnmv_advsimd new file mode 100644 index 0000000000..9b741015cc --- /dev/null +++ b/instructionAPI/ISA_ps/fminnmv_advsimd @@ -0,0 +1,5 @@ +##fminnmv_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +V[d] = Reduce(op, operand, esize); +@@ diff --git a/instructionAPI/ISA_ps/fminp_advsimd_pair b/instructionAPI/ISA_ps/fminp_advsimd_pair new file mode 100644 index 0000000000..f7512d8112 --- /dev/null +++ b/instructionAPI/ISA_ps/fminp_advsimd_pair @@ -0,0 +1,5 @@ +##fminp_advsimd_pair_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +V[d] = Reduce(op, operand, esize); +@@ diff --git a/instructionAPI/ISA_ps/fminp_advsimd_vec b/instructionAPI/ISA_ps/fminp_advsimd_vec new file mode 100644 index 0000000000..c52f0a72d2 --- /dev/null +++ b/instructionAPI/ISA_ps/fminp_advsimd_vec @@ -0,0 +1,26 @@ +##fminp_advsimd_vec_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +bits(2*datasize) concat = operand2:operand1; +bits(esize) element1; +bits(esize) element2; + +for e = 0 to elements-1 + if pair then + element1 = Elem[concat, 2*e, esize]; + element2 = Elem[concat, (2*e)+1, esize]; + else + element1 = Elem[operand1, e, esize]; + element2 = Elem[operand2, e, esize]; + end + + if minimum then + Elem[result, e, esize] = FPMin(element1, element2, FPCR); + else + Elem[result, e, esize] = FPMax(element1, element2, FPCR); + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fminv_advsimd b/instructionAPI/ISA_ps/fminv_advsimd new file mode 100644 index 0000000000..76af454da8 --- /dev/null +++ b/instructionAPI/ISA_ps/fminv_advsimd @@ -0,0 +1,5 @@ +##fminv_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +V[d] = Reduce(op, operand, esize); +@@ diff --git a/instructionAPI/ISA_ps/fmla_advsimd_elt b/instructionAPI/ISA_ps/fmla_advsimd_elt new file mode 100644 index 0000000000..f0eb3f693f --- /dev/null +++ b/instructionAPI/ISA_ps/fmla_advsimd_elt @@ -0,0 +1,15 @@ +##fmla_advsimd_elt_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(idxdsize) operand2 = V[m]; +bits(datasize) operand3 = V[d]; +bits(datasize) result; +bits(esize) element1; +bits(esize) element2 = Elem[operand2, index, esize]; + +for e = 0 to elements-1 + element1 = Elem[operand1, e, esize]; + if sub_op then element1 = FPNeg(element1); + Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR); +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fmla_advsimd_vec b/instructionAPI/ISA_ps/fmla_advsimd_vec new file mode 100644 index 0000000000..de04c835a4 --- /dev/null +++ b/instructionAPI/ISA_ps/fmla_advsimd_vec @@ -0,0 +1,17 @@ +##fmla_advsimd_vec_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) operand3 = V[d]; +bits(datasize) result; +bits(esize) element1; +bits(esize) element2; + +for e = 0 to elements-1 + element1 = Elem[operand1, e, esize]; + element2 = Elem[operand2, e, esize]; + if sub_op then element1 = FPNeg(element1); + Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fmls_advsimd_elt b/instructionAPI/ISA_ps/fmls_advsimd_elt new file mode 100644 index 0000000000..a9557289a6 --- /dev/null +++ b/instructionAPI/ISA_ps/fmls_advsimd_elt @@ -0,0 +1,15 @@ +##fmls_advsimd_elt_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(idxdsize) operand2 = V[m]; +bits(datasize) operand3 = V[d]; +bits(datasize) result; +bits(esize) element1; +bits(esize) element2 = Elem[operand2, index, esize]; + +for e = 0 to elements-1 + element1 = Elem[operand1, e, esize]; + if sub_op then element1 = FPNeg(element1); + Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR); +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fmls_advsimd_vec b/instructionAPI/ISA_ps/fmls_advsimd_vec new file mode 100644 index 0000000000..4f3f593618 --- /dev/null +++ b/instructionAPI/ISA_ps/fmls_advsimd_vec @@ -0,0 +1,17 @@ +##fmls_advsimd_vec_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) operand3 = V[d]; +bits(datasize) result; +bits(esize) element1; +bits(esize) element2; + +for e = 0 to elements-1 + element1 = Elem[operand1, e, esize]; + element2 = Elem[operand2, e, esize]; + if sub_op then element1 = FPNeg(element1); + Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fmov_advsimd b/instructionAPI/ISA_ps/fmov_advsimd new file mode 100644 index 0000000000..7e7854fe14 --- /dev/null +++ b/instructionAPI/ISA_ps/fmov_advsimd @@ -0,0 +1,23 @@ +##fmov_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand; +bits(datasize) result; + +case operation of + when ImmediateOp_MOVI + result = imm; + end + when ImmediateOp_MVNI + result = NOT(imm); + end + when ImmediateOp_ORR + operand = V[rd]; + result = operand OR imm; + end + when ImmediateOp_BIC + operand = V[rd]; + result = operand AND NOT(imm); + end + +V[rd] = result; +@@ diff --git a/instructionAPI/ISA_ps/fmov_float b/instructionAPI/ISA_ps/fmov_float new file mode 100644 index 0000000000..c7a4985740 --- /dev/null +++ b/instructionAPI/ISA_ps/fmov_float @@ -0,0 +1,18 @@ +##fmov_float_execute +CheckFPAdvSIMDEnabled64(); + +bits(datasize) result; +bits(datasize) operand = V[n]; + +case fpop of + when FPUnaryOp_MOV result = operand; + end + when FPUnaryOp_ABS result = FPAbs(operand); + end + when FPUnaryOp_NEG result = FPNeg(operand); + end + when FPUnaryOp_SQRT result = FPSqrt(operand, FPCR); + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fmov_float_gen b/instructionAPI/ISA_ps/fmov_float_gen new file mode 100644 index 0000000000..a4b0bcb2e4 --- /dev/null +++ b/instructionAPI/ISA_ps/fmov_float_gen @@ -0,0 +1,26 @@ +##fmov_float_gen_execute +CheckFPAdvSIMDEnabled64(); + +bits(fltsize) fltval; +bits(intsize) intval; + +case op of + when FPConvOp_CVT_FtoI + fltval = V[n]; + intval = FPToFixed(fltval, 0, unsigned, FPCR, rounding); + X[d] = intval; + end + when FPConvOp_CVT_ItoF + intval = X[n]; + fltval = FixedToFP(intval, 0, unsigned, FPCR, rounding); + V[d] = fltval; + end + when FPConvOp_MOV_FtoI + intval = Vpart[n,part]; + X[d] = intval; + end + when FPConvOp_MOV_ItoF + intval = X[n]; + Vpart[d,part] = intval; + end +@@ diff --git a/instructionAPI/ISA_ps/fmov_float_imm b/instructionAPI/ISA_ps/fmov_float_imm new file mode 100644 index 0000000000..5cc6142bee --- /dev/null +++ b/instructionAPI/ISA_ps/fmov_float_imm @@ -0,0 +1,5 @@ +##fmov_float_imm_execute +CheckFPAdvSIMDEnabled64(); + +V[d] = imm; +@@ diff --git a/instructionAPI/ISA_ps/fmsub_float b/instructionAPI/ISA_ps/fmsub_float new file mode 100644 index 0000000000..1cb69337c1 --- /dev/null +++ b/instructionAPI/ISA_ps/fmsub_float @@ -0,0 +1,13 @@ +##fmsub_float_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) result; +bits(datasize) operanda = V[a]; +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; + +if opa_neg then operanda = FPNeg(operanda); +if op1_neg then operand1 = FPNeg(operand1); +result = FPMulAdd(operanda, operand1, operand2, FPCR); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fmul_advsimd_elt b/instructionAPI/ISA_ps/fmul_advsimd_elt new file mode 100644 index 0000000000..9bf23c2559 --- /dev/null +++ b/instructionAPI/ISA_ps/fmul_advsimd_elt @@ -0,0 +1,18 @@ +##fmul_advsimd_elt_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(idxdsize) operand2 = V[m]; +bits(datasize) result; +bits(esize) element1; +bits(esize) element2 = Elem[operand2, index, esize]; + +for e = 0 to elements-1 + element1 = Elem[operand1, e, esize]; + if mulx_op then + Elem[result, e, esize] = FPMulX(element1, element2, FPCR); + else + Elem[result, e, esize] = FPMul(element1, element2, FPCR); + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fmul_advsimd_vec b/instructionAPI/ISA_ps/fmul_advsimd_vec new file mode 100644 index 0000000000..35f523dc3e --- /dev/null +++ b/instructionAPI/ISA_ps/fmul_advsimd_vec @@ -0,0 +1,15 @@ +##fmul_advsimd_vec_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +bits(esize) element1; +bits(esize) element2; + +for e = 0 to elements-1 + element1 = Elem[operand1, e, esize]; + element2 = Elem[operand2, e, esize]; + Elem[result, e, esize] = FPMul(element1, element2, FPCR); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fmul_float b/instructionAPI/ISA_ps/fmul_float new file mode 100644 index 0000000000..b989fb607f --- /dev/null +++ b/instructionAPI/ISA_ps/fmul_float @@ -0,0 +1,12 @@ +##fmul_float_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) result; +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; + +result = FPMul(operand1, operand2, FPCR); + +if negated then result = FPNeg(result); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fmulx_advsimd_elt b/instructionAPI/ISA_ps/fmulx_advsimd_elt new file mode 100644 index 0000000000..1adf16ed00 --- /dev/null +++ b/instructionAPI/ISA_ps/fmulx_advsimd_elt @@ -0,0 +1,18 @@ +##fmulx_advsimd_elt_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(idxdsize) operand2 = V[m]; +bits(datasize) result; +bits(esize) element1; +bits(esize) element2 = Elem[operand2, index, esize]; + +for e = 0 to elements-1 + element1 = Elem[operand1, e, esize]; + if mulx_op then + Elem[result, e, esize] = FPMulX(element1, element2, FPCR); + else + Elem[result, e, esize] = FPMul(element1, element2, FPCR); + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fmulx_advsimd_vec b/instructionAPI/ISA_ps/fmulx_advsimd_vec new file mode 100644 index 0000000000..e7ecb44582 --- /dev/null +++ b/instructionAPI/ISA_ps/fmulx_advsimd_vec @@ -0,0 +1,14 @@ +##fmulx_advsimd_vec_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +bits(esize) element1; +bits(esize) element2; + +for e = 0 to elements-1 + element1 = Elem[operand1, e, esize]; + element2 = Elem[operand2, e, esize]; + Elem[result, e, esize] = FPMulX(element1, element2, FPCR); +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fneg_advsimd b/instructionAPI/ISA_ps/fneg_advsimd new file mode 100644 index 0000000000..dd064377aa --- /dev/null +++ b/instructionAPI/ISA_ps/fneg_advsimd @@ -0,0 +1,17 @@ +##fneg_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +bits(esize) element; + +for e = 0 to elements-1 + element = Elem[operand, e, esize]; + if neg then + element = FPNeg(element); + else + element = FPAbs(element); + end + Elem[result, e, esize] = element; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fneg_float b/instructionAPI/ISA_ps/fneg_float new file mode 100644 index 0000000000..5e1695db0e --- /dev/null +++ b/instructionAPI/ISA_ps/fneg_float @@ -0,0 +1,18 @@ +##fneg_float_execute +CheckFPAdvSIMDEnabled64(); + +bits(datasize) result; +bits(datasize) operand = V[n]; + +case fpop of + when FPUnaryOp_MOV result = operand; + end + when FPUnaryOp_ABS result = FPAbs(operand); + end + when FPUnaryOp_NEG result = FPNeg(operand); + end + when FPUnaryOp_SQRT result = FPSqrt(operand, FPCR); + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fnmadd_float b/instructionAPI/ISA_ps/fnmadd_float new file mode 100644 index 0000000000..ffe93bf415 --- /dev/null +++ b/instructionAPI/ISA_ps/fnmadd_float @@ -0,0 +1,13 @@ +##fnmadd_float_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) result; +bits(datasize) operanda = V[a]; +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; + +if opa_neg then operanda = FPNeg(operanda); +if op1_neg then operand1 = FPNeg(operand1); +result = FPMulAdd(operanda, operand1, operand2, FPCR); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fnmsub_float b/instructionAPI/ISA_ps/fnmsub_float new file mode 100644 index 0000000000..fc84ec78ea --- /dev/null +++ b/instructionAPI/ISA_ps/fnmsub_float @@ -0,0 +1,13 @@ +##fnmsub_float_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) result; +bits(datasize) operanda = V[a]; +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; + +if opa_neg then operanda = FPNeg(operanda); +if op1_neg then operand1 = FPNeg(operand1); +result = FPMulAdd(operanda, operand1, operand2, FPCR); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fnmul_float b/instructionAPI/ISA_ps/fnmul_float new file mode 100644 index 0000000000..dbe2e9952d --- /dev/null +++ b/instructionAPI/ISA_ps/fnmul_float @@ -0,0 +1,12 @@ +##fnmul_float_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) result; +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; + +result = FPMul(operand1, operand2, FPCR); + +if negated then result = FPNeg(result); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fpsimdindex b/instructionAPI/ISA_ps/fpsimdindex new file mode 100644 index 0000000000..e69de29bb2 diff --git a/instructionAPI/ISA_ps/frecpe_advsimd b/instructionAPI/ISA_ps/frecpe_advsimd new file mode 100644 index 0000000000..b638790181 --- /dev/null +++ b/instructionAPI/ISA_ps/frecpe_advsimd @@ -0,0 +1,12 @@ +##frecpe_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +bits(esize) element; + +for e = 0 to elements-1 + element = Elem[operand, e, esize]; + Elem[result, e, esize] = FPRecipEstimate(element, FPCR); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/frecps_advsimd b/instructionAPI/ISA_ps/frecps_advsimd new file mode 100644 index 0000000000..8c260c14dc --- /dev/null +++ b/instructionAPI/ISA_ps/frecps_advsimd @@ -0,0 +1,15 @@ +##frecps_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +bits(esize) element1; +bits(esize) element2; + +for e = 0 to elements-1 + element1 = Elem[operand1, e, esize]; + element2 = Elem[operand2, e, esize]; + Elem[result, e, esize] = FPRecipStepFused(element1, element2); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/frecpx_advsimd b/instructionAPI/ISA_ps/frecpx_advsimd new file mode 100644 index 0000000000..0f60ba0bdd --- /dev/null +++ b/instructionAPI/ISA_ps/frecpx_advsimd @@ -0,0 +1,12 @@ +##frecpx_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +bits(esize) element; + +for e = 0 to elements-1 + element = Elem[operand, e, esize]; + Elem[result, e, esize] = FPRecpX(element, FPCR); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/frinta_advsimd b/instructionAPI/ISA_ps/frinta_advsimd new file mode 100644 index 0000000000..b856dde3e5 --- /dev/null +++ b/instructionAPI/ISA_ps/frinta_advsimd @@ -0,0 +1,12 @@ +##frinta_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +bits(esize) element; + +for e = 0 to elements-1 + element = Elem[operand, e, esize]; + Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/frinta_float b/instructionAPI/ISA_ps/frinta_float new file mode 100644 index 0000000000..a57fcdce99 --- /dev/null +++ b/instructionAPI/ISA_ps/frinta_float @@ -0,0 +1,10 @@ +##frinta_float_execute +CheckFPAdvSIMDEnabled64(); + +bits(datasize) result; +bits(datasize) operand = V[n]; + +result = FPRoundInt(operand, FPCR, rounding, exact); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/frinti_advsimd b/instructionAPI/ISA_ps/frinti_advsimd new file mode 100644 index 0000000000..8beae3f000 --- /dev/null +++ b/instructionAPI/ISA_ps/frinti_advsimd @@ -0,0 +1,12 @@ +##frinti_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +bits(esize) element; + +for e = 0 to elements-1 + element = Elem[operand, e, esize]; + Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/frinti_float b/instructionAPI/ISA_ps/frinti_float new file mode 100644 index 0000000000..e7fcf73f96 --- /dev/null +++ b/instructionAPI/ISA_ps/frinti_float @@ -0,0 +1,10 @@ +##frinti_float_execute +CheckFPAdvSIMDEnabled64(); + +bits(datasize) result; +bits(datasize) operand = V[n]; + +result = FPRoundInt(operand, FPCR, rounding, exact); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/frintm_advsimd b/instructionAPI/ISA_ps/frintm_advsimd new file mode 100644 index 0000000000..5c109a2656 --- /dev/null +++ b/instructionAPI/ISA_ps/frintm_advsimd @@ -0,0 +1,12 @@ +##frintm_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +bits(esize) element; + +for e = 0 to elements-1 + element = Elem[operand, e, esize]; + Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/frintm_float b/instructionAPI/ISA_ps/frintm_float new file mode 100644 index 0000000000..a522cb541d --- /dev/null +++ b/instructionAPI/ISA_ps/frintm_float @@ -0,0 +1,10 @@ +##frintm_float_execute +CheckFPAdvSIMDEnabled64(); + +bits(datasize) result; +bits(datasize) operand = V[n]; + +result = FPRoundInt(operand, FPCR, rounding, exact); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/frintn_advsimd b/instructionAPI/ISA_ps/frintn_advsimd new file mode 100644 index 0000000000..30686c3f31 --- /dev/null +++ b/instructionAPI/ISA_ps/frintn_advsimd @@ -0,0 +1,12 @@ +##frintn_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +bits(esize) element; + +for e = 0 to elements-1 + element = Elem[operand, e, esize]; + Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/frintn_float b/instructionAPI/ISA_ps/frintn_float new file mode 100644 index 0000000000..47fc1e626f --- /dev/null +++ b/instructionAPI/ISA_ps/frintn_float @@ -0,0 +1,10 @@ +##frintn_float_execute +CheckFPAdvSIMDEnabled64(); + +bits(datasize) result; +bits(datasize) operand = V[n]; + +result = FPRoundInt(operand, FPCR, rounding, exact); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/frintp_advsimd b/instructionAPI/ISA_ps/frintp_advsimd new file mode 100644 index 0000000000..c77b28b7e8 --- /dev/null +++ b/instructionAPI/ISA_ps/frintp_advsimd @@ -0,0 +1,12 @@ +##frintp_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +bits(esize) element; + +for e = 0 to elements-1 + element = Elem[operand, e, esize]; + Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/frintp_float b/instructionAPI/ISA_ps/frintp_float new file mode 100644 index 0000000000..0a0d49e6b1 --- /dev/null +++ b/instructionAPI/ISA_ps/frintp_float @@ -0,0 +1,10 @@ +##frintp_float_execute +CheckFPAdvSIMDEnabled64(); + +bits(datasize) result; +bits(datasize) operand = V[n]; + +result = FPRoundInt(operand, FPCR, rounding, exact); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/frintx_advsimd b/instructionAPI/ISA_ps/frintx_advsimd new file mode 100644 index 0000000000..0391efb7ca --- /dev/null +++ b/instructionAPI/ISA_ps/frintx_advsimd @@ -0,0 +1,12 @@ +##frintx_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +bits(esize) element; + +for e = 0 to elements-1 + element = Elem[operand, e, esize]; + Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/frintx_float b/instructionAPI/ISA_ps/frintx_float new file mode 100644 index 0000000000..de6eea054f --- /dev/null +++ b/instructionAPI/ISA_ps/frintx_float @@ -0,0 +1,10 @@ +##frintx_float_execute +CheckFPAdvSIMDEnabled64(); + +bits(datasize) result; +bits(datasize) operand = V[n]; + +result = FPRoundInt(operand, FPCR, rounding, exact); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/frintz_advsimd b/instructionAPI/ISA_ps/frintz_advsimd new file mode 100644 index 0000000000..73f35f1dd3 --- /dev/null +++ b/instructionAPI/ISA_ps/frintz_advsimd @@ -0,0 +1,12 @@ +##frintz_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +bits(esize) element; + +for e = 0 to elements-1 + element = Elem[operand, e, esize]; + Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/frintz_float b/instructionAPI/ISA_ps/frintz_float new file mode 100644 index 0000000000..6b8ccdb9b3 --- /dev/null +++ b/instructionAPI/ISA_ps/frintz_float @@ -0,0 +1,10 @@ +##frintz_float_execute +CheckFPAdvSIMDEnabled64(); + +bits(datasize) result; +bits(datasize) operand = V[n]; + +result = FPRoundInt(operand, FPCR, rounding, exact); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/frsqrte_advsimd b/instructionAPI/ISA_ps/frsqrte_advsimd new file mode 100644 index 0000000000..d31f6975db --- /dev/null +++ b/instructionAPI/ISA_ps/frsqrte_advsimd @@ -0,0 +1,12 @@ +##frsqrte_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +bits(esize) element; + +for e = 0 to elements-1 + element = Elem[operand, e, esize]; + Elem[result, e, esize] = FPRSqrtEstimate(element, FPCR); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/frsqrts_advsimd b/instructionAPI/ISA_ps/frsqrts_advsimd new file mode 100644 index 0000000000..20bde0f5fe --- /dev/null +++ b/instructionAPI/ISA_ps/frsqrts_advsimd @@ -0,0 +1,15 @@ +##frsqrts_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +bits(esize) element1; +bits(esize) element2; + +for e = 0 to elements-1 + element1 = Elem[operand1, e, esize]; + element2 = Elem[operand2, e, esize]; + Elem[result, e, esize] = FPRSqrtStepFused(element1, element2); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fsqrt_advsimd b/instructionAPI/ISA_ps/fsqrt_advsimd new file mode 100644 index 0000000000..0bc8194176 --- /dev/null +++ b/instructionAPI/ISA_ps/fsqrt_advsimd @@ -0,0 +1,12 @@ +##fsqrt_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +bits(esize) element; + +for e = 0 to elements-1 + element = Elem[operand, e, esize]; + Elem[result, e, esize] = FPSqrt(element, FPCR); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fsqrt_float b/instructionAPI/ISA_ps/fsqrt_float new file mode 100644 index 0000000000..af44595ce1 --- /dev/null +++ b/instructionAPI/ISA_ps/fsqrt_float @@ -0,0 +1,18 @@ +##fsqrt_float_execute +CheckFPAdvSIMDEnabled64(); + +bits(datasize) result; +bits(datasize) operand = V[n]; + +case fpop of + when FPUnaryOp_MOV result = operand; + end + when FPUnaryOp_ABS result = FPAbs(operand); + end + when FPUnaryOp_NEG result = FPNeg(operand); + end + when FPUnaryOp_SQRT result = FPSqrt(operand, FPCR); + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fsub_advsimd b/instructionAPI/ISA_ps/fsub_advsimd new file mode 100644 index 0000000000..27456e1bea --- /dev/null +++ b/instructionAPI/ISA_ps/fsub_advsimd @@ -0,0 +1,17 @@ +##fsub_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +bits(esize) element1; +bits(esize) element2; +bits(esize) diff; + +for e = 0 to elements-1 + element1 = Elem[operand1, e, esize]; + element2 = Elem[operand2, e, esize]; + diff = FPSub(element1, element2, FPCR); + Elem[result, e, esize] = if abs then FPAbs(diff) else diff; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/fsub_float b/instructionAPI/ISA_ps/fsub_float new file mode 100644 index 0000000000..9d7f932b3f --- /dev/null +++ b/instructionAPI/ISA_ps/fsub_float @@ -0,0 +1,14 @@ +##fsub_float_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) result; +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; + +if sub_op then + result = FPSub(operand1, operand2, FPCR); +else + result = FPAdd(operand1, operand2, FPCR); +end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/hint b/instructionAPI/ISA_ps/hint new file mode 100644 index 0000000000..4992d47550 --- /dev/null +++ b/instructionAPI/ISA_ps/hint @@ -0,0 +1,48 @@ +##hint_execute +case op of + when SystemHintOp_YIELD + Hint_Yield(); + end + + when SystemHintOp_WFE + if EventRegistered() then + ClearEventRegister(); + else + if PSTATE.EL == EL0 then + AArch64.CheckForWFxTrap(EL1, TRUE); + end + if HaveEL(EL2) && !IsSecure() && PSTATE.EL IN {EL0,EL1} then + AArch64.CheckForWFxTrap(EL2, TRUE); + end + if HaveEL(EL3) && PSTATE.EL != EL3 then + AArch64.CheckForWFxTrap(EL3, TRUE); + end + WaitForEvent(); + end + + end + when SystemHintOp_WFI + if !InterruptPending() then + if PSTATE.EL == EL0 then + AArch64.CheckForWFxTrap(EL1, FALSE); + end + if HaveEL(EL2) && !IsSecure() && PSTATE.EL IN {EL0,EL1} then + AArch64.CheckForWFxTrap(EL2, FALSE); + end + if HaveEL(EL3) && PSTATE.EL != EL3 then + AArch64.CheckForWFxTrap(EL3, FALSE); + end + WaitForInterrupt(); + end + + end + when SystemHintOp_SEV + SendEvent(); + end + + when SystemHintOp_SEVL + EventRegisterSet(); + end + + otherwise // do nothing +@@ diff --git a/instructionAPI/ISA_ps/hlt b/instructionAPI/ISA_ps/hlt new file mode 100644 index 0000000000..dea046eddd --- /dev/null +++ b/instructionAPI/ISA_ps/hlt @@ -0,0 +1,3 @@ +##hlt_execute +Halt(DebugHalt_HaltInstruction); +@@ diff --git a/instructionAPI/ISA_ps/hvc b/instructionAPI/ISA_ps/hvc new file mode 100644 index 0000000000..e3c94679cb --- /dev/null +++ b/instructionAPI/ISA_ps/hvc @@ -0,0 +1,12 @@ +##hvc_execute +if !HaveEL(EL2) || PSTATE.EL == EL0 || (PSTATE.EL == EL1 && IsSecure()) then + UnallocatedEncoding(); +end + +hvc_enable = if HaveEL(EL3) then SCR_EL3.HCE else NOT(HCR_EL2.HCD); +if hvc_enable == 0 then + AArch64.UndefinedFault(); +else + AArch64.CallHypervisor(imm); +end +@@ diff --git a/instructionAPI/ISA_ps/ic_sys b/instructionAPI/ISA_ps/ic_sys new file mode 100644 index 0000000000..be6027fa09 --- /dev/null +++ b/instructionAPI/ISA_ps/ic_sys @@ -0,0 +1,6 @@ +##ic_sys_execute +if has_result then + X[t] = SysOp_R(sys_op0, sys_op1, sys_crn, sys_crm, sys_op2); +else + SysOp_W(sys_op0, sys_op1, sys_crn, sys_crm, sys_op2, X[t]); +@@ diff --git a/instructionAPI/ISA_ps/index b/instructionAPI/ISA_ps/index new file mode 100644 index 0000000000..e69de29bb2 diff --git a/instructionAPI/ISA_ps/ins_advsimd_elt b/instructionAPI/ISA_ps/ins_advsimd_elt new file mode 100644 index 0000000000..cd6a5d6f35 --- /dev/null +++ b/instructionAPI/ISA_ps/ins_advsimd_elt @@ -0,0 +1,9 @@ +##ins_advsimd_elt_execute +CheckFPAdvSIMDEnabled64(); +bits(idxdsize) operand = V[n]; +bits(128) result; + +result = V[d]; +Elem[result, dst_index, esize] = Elem[operand, src_index, esize]; +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/ins_advsimd_gen b/instructionAPI/ISA_ps/ins_advsimd_gen new file mode 100644 index 0000000000..eb1966e0c0 --- /dev/null +++ b/instructionAPI/ISA_ps/ins_advsimd_gen @@ -0,0 +1,9 @@ +##ins_advsimd_gen_execute +CheckFPAdvSIMDEnabled64(); +bits(esize) element = X[n]; +bits(datasize) result; + +result = V[d]; +Elem[result, index, esize] = element; +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/isb b/instructionAPI/ISA_ps/isb new file mode 100644 index 0000000000..c32d70363c --- /dev/null +++ b/instructionAPI/ISA_ps/isb @@ -0,0 +1,12 @@ +##isb_execute +case op of + when MemBarrierOp_DSB + DataSynchronizationBarrier(domain, types); + end + when MemBarrierOp_DMB + DataMemoryBarrier(domain, types); + end + when MemBarrierOp_ISB + InstructionSynchronizationBarrier(); + end +@@ diff --git a/instructionAPI/ISA_ps/ld1_advsimd_mult b/instructionAPI/ISA_ps/ld1_advsimd_mult new file mode 100644 index 0000000000..1ee296b51d --- /dev/null +++ b/instructionAPI/ISA_ps/ld1_advsimd_mult @@ -0,0 +1,41 @@ +##ld1_advsimd_mult_execute +CheckFPAdvSIMDEnabled64(); + +bits(64) address; +bits(64) offs; +bits(datasize) rval; +integer e, r, s, tt; +constant integer ebytes = esize / 8; + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +offs = Zeros(64); +for r = 0 to rpt-1 + for e = 0 to elements-1 + tt = (t + r) MOD 32; + for s = 0 to selem-1 + rval = V[tt]; + if memop == MemOp_LOAD then + Elem[rval, e, esize] = Mem[address + offs, ebytes, AccType_VEC]; + V[tt] = rval; + else // memop == MemOp_STORE + Mem[address + offs, ebytes, AccType_VEC] = Elem[rval, e, esize]; + end + offs = offs + ebytes; + tt = (tt + 1) MOD 32; + +if wback then + if m != 31 then + offs = X[m]; + end + if n == 31 then + SP[] = address + offs; + else + X[n] = address + offs; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ld1_advsimd_sngl b/instructionAPI/ISA_ps/ld1_advsimd_sngl new file mode 100644 index 0000000000..97b9d0fd71 --- /dev/null +++ b/instructionAPI/ISA_ps/ld1_advsimd_sngl @@ -0,0 +1,52 @@ +##ld1_advsimd_sngl_execute +CheckFPAdvSIMDEnabled64(); + +bits(64) address; +bits(64) offs; +bits(128) rval; +bits(esize) element; +integer s; +constant integer ebytes = esize / 8; + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +offs = Zeros(64); +if replicate then + // load and replicate to all elements + for s = 0 to selem-1 + element = Mem[address + offs, ebytes, AccType_VEC]; + // replicate to fill 128- or 64-bit register + V[t] = Replicate(element, datasize / esize); + offs = offs + ebytes; + t = (t + 1) MOD 32; +else + // load/store one element per register + for s = 0 to selem-1 + rval = V[t]; + if memop == MemOp_LOAD then + // insert into one lane of 128-bit register + Elem[rval, index, esize] = Mem[address + offs, ebytes, AccType_VEC]; + V[t] = rval; + else // memop == MemOp_STORE + // extract from one lane of 128-bit register + Mem[address + offs, ebytes, AccType_VEC] = Elem[rval, index, esize]; + end + offs = offs + ebytes; + t = (t + 1) MOD 32; +end + +if wback then + if m != 31 then + offs = X[m]; + end + if n == 31 then + SP[] = address + offs; + else + X[n] = address + offs; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ld1r_advsimd b/instructionAPI/ISA_ps/ld1r_advsimd new file mode 100644 index 0000000000..c462733dda --- /dev/null +++ b/instructionAPI/ISA_ps/ld1r_advsimd @@ -0,0 +1,52 @@ +##ld1r_advsimd_execute +CheckFPAdvSIMDEnabled64(); + +bits(64) address; +bits(64) offs; +bits(128) rval; +bits(esize) element; +integer s; +constant integer ebytes = esize / 8; + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +offs = Zeros(64); +if replicate then + // load and replicate to all elements + for s = 0 to selem-1 + element = Mem[address + offs, ebytes, AccType_VEC]; + // replicate to fill 128- or 64-bit register + V[t] = Replicate(element, datasize / esize); + offs = offs + ebytes; + t = (t + 1) MOD 32; +else + // load/store one element per register + for s = 0 to selem-1 + rval = V[t]; + if memop == MemOp_LOAD then + // insert into one lane of 128-bit register + Elem[rval, index, esize] = Mem[address + offs, ebytes, AccType_VEC]; + V[t] = rval; + else // memop == MemOp_STORE + // extract from one lane of 128-bit register + Mem[address + offs, ebytes, AccType_VEC] = Elem[rval, index, esize]; + end + offs = offs + ebytes; + t = (t + 1) MOD 32; +end + +if wback then + if m != 31 then + offs = X[m]; + end + if n == 31 then + SP[] = address + offs; + else + X[n] = address + offs; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ld2_advsimd_mult b/instructionAPI/ISA_ps/ld2_advsimd_mult new file mode 100644 index 0000000000..bd7d67f501 --- /dev/null +++ b/instructionAPI/ISA_ps/ld2_advsimd_mult @@ -0,0 +1,41 @@ +##ld2_advsimd_mult_execute +CheckFPAdvSIMDEnabled64(); + +bits(64) address; +bits(64) offs; +bits(datasize) rval; +integer e, r, s, tt; +constant integer ebytes = esize / 8; + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +offs = Zeros(64); +for r = 0 to rpt-1 + for e = 0 to elements-1 + tt = (t + r) MOD 32; + for s = 0 to selem-1 + rval = V[tt]; + if memop == MemOp_LOAD then + Elem[rval, e, esize] = Mem[address + offs, ebytes, AccType_VEC]; + V[tt] = rval; + else // memop == MemOp_STORE + Mem[address + offs, ebytes, AccType_VEC] = Elem[rval, e, esize]; + end + offs = offs + ebytes; + tt = (tt + 1) MOD 32; + +if wback then + if m != 31 then + offs = X[m]; + end + if n == 31 then + SP[] = address + offs; + else + X[n] = address + offs; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ld2_advsimd_sngl b/instructionAPI/ISA_ps/ld2_advsimd_sngl new file mode 100644 index 0000000000..96376f817f --- /dev/null +++ b/instructionAPI/ISA_ps/ld2_advsimd_sngl @@ -0,0 +1,52 @@ +##ld2_advsimd_sngl_execute +CheckFPAdvSIMDEnabled64(); + +bits(64) address; +bits(64) offs; +bits(128) rval; +bits(esize) element; +integer s; +constant integer ebytes = esize / 8; + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +offs = Zeros(64); +if replicate then + // load and replicate to all elements + for s = 0 to selem-1 + element = Mem[address + offs, ebytes, AccType_VEC]; + // replicate to fill 128- or 64-bit register + V[t] = Replicate(element, datasize / esize); + offs = offs + ebytes; + t = (t + 1) MOD 32; +else + // load/store one element per register + for s = 0 to selem-1 + rval = V[t]; + if memop == MemOp_LOAD then + // insert into one lane of 128-bit register + Elem[rval, index, esize] = Mem[address + offs, ebytes, AccType_VEC]; + V[t] = rval; + else // memop == MemOp_STORE + // extract from one lane of 128-bit register + Mem[address + offs, ebytes, AccType_VEC] = Elem[rval, index, esize]; + end + offs = offs + ebytes; + t = (t + 1) MOD 32; +end + +if wback then + if m != 31 then + offs = X[m]; + end + if n == 31 then + SP[] = address + offs; + else + X[n] = address + offs; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ld2r_advsimd b/instructionAPI/ISA_ps/ld2r_advsimd new file mode 100644 index 0000000000..e6d1beb2bd --- /dev/null +++ b/instructionAPI/ISA_ps/ld2r_advsimd @@ -0,0 +1,52 @@ +##ld2r_advsimd_execute +CheckFPAdvSIMDEnabled64(); + +bits(64) address; +bits(64) offs; +bits(128) rval; +bits(esize) element; +integer s; +constant integer ebytes = esize / 8; + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +offs = Zeros(64); +if replicate then + // load and replicate to all elements + for s = 0 to selem-1 + element = Mem[address + offs, ebytes, AccType_VEC]; + // replicate to fill 128- or 64-bit register + V[t] = Replicate(element, datasize / esize); + offs = offs + ebytes; + t = (t + 1) MOD 32; +else + // load/store one element per register + for s = 0 to selem-1 + rval = V[t]; + if memop == MemOp_LOAD then + // insert into one lane of 128-bit register + Elem[rval, index, esize] = Mem[address + offs, ebytes, AccType_VEC]; + V[t] = rval; + else // memop == MemOp_STORE + // extract from one lane of 128-bit register + Mem[address + offs, ebytes, AccType_VEC] = Elem[rval, index, esize]; + end + offs = offs + ebytes; + t = (t + 1) MOD 32; +end + +if wback then + if m != 31 then + offs = X[m]; + end + if n == 31 then + SP[] = address + offs; + else + X[n] = address + offs; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ld3_advsimd_mult b/instructionAPI/ISA_ps/ld3_advsimd_mult new file mode 100644 index 0000000000..7a9a0f930d --- /dev/null +++ b/instructionAPI/ISA_ps/ld3_advsimd_mult @@ -0,0 +1,41 @@ +##ld3_advsimd_mult_execute +CheckFPAdvSIMDEnabled64(); + +bits(64) address; +bits(64) offs; +bits(datasize) rval; +integer e, r, s, tt; +constant integer ebytes = esize / 8; + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +offs = Zeros(64); +for r = 0 to rpt-1 + for e = 0 to elements-1 + tt = (t + r) MOD 32; + for s = 0 to selem-1 + rval = V[tt]; + if memop == MemOp_LOAD then + Elem[rval, e, esize] = Mem[address + offs, ebytes, AccType_VEC]; + V[tt] = rval; + else // memop == MemOp_STORE + Mem[address + offs, ebytes, AccType_VEC] = Elem[rval, e, esize]; + end + offs = offs + ebytes; + tt = (tt + 1) MOD 32; + +if wback then + if m != 31 then + offs = X[m]; + end + if n == 31 then + SP[] = address + offs; + else + X[n] = address + offs; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ld3_advsimd_sngl b/instructionAPI/ISA_ps/ld3_advsimd_sngl new file mode 100644 index 0000000000..ea332bfc7c --- /dev/null +++ b/instructionAPI/ISA_ps/ld3_advsimd_sngl @@ -0,0 +1,52 @@ +##ld3_advsimd_sngl_execute +CheckFPAdvSIMDEnabled64(); + +bits(64) address; +bits(64) offs; +bits(128) rval; +bits(esize) element; +integer s; +constant integer ebytes = esize / 8; + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +offs = Zeros(64); +if replicate then + // load and replicate to all elements + for s = 0 to selem-1 + element = Mem[address + offs, ebytes, AccType_VEC]; + // replicate to fill 128- or 64-bit register + V[t] = Replicate(element, datasize / esize); + offs = offs + ebytes; + t = (t + 1) MOD 32; +else + // load/store one element per register + for s = 0 to selem-1 + rval = V[t]; + if memop == MemOp_LOAD then + // insert into one lane of 128-bit register + Elem[rval, index, esize] = Mem[address + offs, ebytes, AccType_VEC]; + V[t] = rval; + else // memop == MemOp_STORE + // extract from one lane of 128-bit register + Mem[address + offs, ebytes, AccType_VEC] = Elem[rval, index, esize]; + end + offs = offs + ebytes; + t = (t + 1) MOD 32; +end + +if wback then + if m != 31 then + offs = X[m]; + end + if n == 31 then + SP[] = address + offs; + else + X[n] = address + offs; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ld3r_advsimd b/instructionAPI/ISA_ps/ld3r_advsimd new file mode 100644 index 0000000000..8188dd6db9 --- /dev/null +++ b/instructionAPI/ISA_ps/ld3r_advsimd @@ -0,0 +1,52 @@ +##ld3r_advsimd_execute +CheckFPAdvSIMDEnabled64(); + +bits(64) address; +bits(64) offs; +bits(128) rval; +bits(esize) element; +integer s; +constant integer ebytes = esize / 8; + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +offs = Zeros(64); +if replicate then + // load and replicate to all elements + for s = 0 to selem-1 + element = Mem[address + offs, ebytes, AccType_VEC]; + // replicate to fill 128- or 64-bit register + V[t] = Replicate(element, datasize / esize); + offs = offs + ebytes; + t = (t + 1) MOD 32; +else + // load/store one element per register + for s = 0 to selem-1 + rval = V[t]; + if memop == MemOp_LOAD then + // insert into one lane of 128-bit register + Elem[rval, index, esize] = Mem[address + offs, ebytes, AccType_VEC]; + V[t] = rval; + else // memop == MemOp_STORE + // extract from one lane of 128-bit register + Mem[address + offs, ebytes, AccType_VEC] = Elem[rval, index, esize]; + end + offs = offs + ebytes; + t = (t + 1) MOD 32; +end + +if wback then + if m != 31 then + offs = X[m]; + end + if n == 31 then + SP[] = address + offs; + else + X[n] = address + offs; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ld4_advsimd_mult b/instructionAPI/ISA_ps/ld4_advsimd_mult new file mode 100644 index 0000000000..2a6778914e --- /dev/null +++ b/instructionAPI/ISA_ps/ld4_advsimd_mult @@ -0,0 +1,41 @@ +##ld4_advsimd_mult_execute +CheckFPAdvSIMDEnabled64(); + +bits(64) address; +bits(64) offs; +bits(datasize) rval; +integer e, r, s, tt; +constant integer ebytes = esize / 8; + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +offs = Zeros(64); +for r = 0 to rpt-1 + for e = 0 to elements-1 + tt = (t + r) MOD 32; + for s = 0 to selem-1 + rval = V[tt]; + if memop == MemOp_LOAD then + Elem[rval, e, esize] = Mem[address + offs, ebytes, AccType_VEC]; + V[tt] = rval; + else // memop == MemOp_STORE + Mem[address + offs, ebytes, AccType_VEC] = Elem[rval, e, esize]; + end + offs = offs + ebytes; + tt = (tt + 1) MOD 32; + +if wback then + if m != 31 then + offs = X[m]; + end + if n == 31 then + SP[] = address + offs; + else + X[n] = address + offs; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ld4_advsimd_sngl b/instructionAPI/ISA_ps/ld4_advsimd_sngl new file mode 100644 index 0000000000..78277946b8 --- /dev/null +++ b/instructionAPI/ISA_ps/ld4_advsimd_sngl @@ -0,0 +1,52 @@ +##ld4_advsimd_sngl_execute +CheckFPAdvSIMDEnabled64(); + +bits(64) address; +bits(64) offs; +bits(128) rval; +bits(esize) element; +integer s; +constant integer ebytes = esize / 8; + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +offs = Zeros(64); +if replicate then + // load and replicate to all elements + for s = 0 to selem-1 + element = Mem[address + offs, ebytes, AccType_VEC]; + // replicate to fill 128- or 64-bit register + V[t] = Replicate(element, datasize / esize); + offs = offs + ebytes; + t = (t + 1) MOD 32; +else + // load/store one element per register + for s = 0 to selem-1 + rval = V[t]; + if memop == MemOp_LOAD then + // insert into one lane of 128-bit register + Elem[rval, index, esize] = Mem[address + offs, ebytes, AccType_VEC]; + V[t] = rval; + else // memop == MemOp_STORE + // extract from one lane of 128-bit register + Mem[address + offs, ebytes, AccType_VEC] = Elem[rval, index, esize]; + end + offs = offs + ebytes; + t = (t + 1) MOD 32; +end + +if wback then + if m != 31 then + offs = X[m]; + end + if n == 31 then + SP[] = address + offs; + else + X[n] = address + offs; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ld4r_advsimd b/instructionAPI/ISA_ps/ld4r_advsimd new file mode 100644 index 0000000000..d1ccbd7e38 --- /dev/null +++ b/instructionAPI/ISA_ps/ld4r_advsimd @@ -0,0 +1,52 @@ +##ld4r_advsimd_execute +CheckFPAdvSIMDEnabled64(); + +bits(64) address; +bits(64) offs; +bits(128) rval; +bits(esize) element; +integer s; +constant integer ebytes = esize / 8; + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +offs = Zeros(64); +if replicate then + // load and replicate to all elements + for s = 0 to selem-1 + element = Mem[address + offs, ebytes, AccType_VEC]; + // replicate to fill 128- or 64-bit register + V[t] = Replicate(element, datasize / esize); + offs = offs + ebytes; + t = (t + 1) MOD 32; +else + // load/store one element per register + for s = 0 to selem-1 + rval = V[t]; + if memop == MemOp_LOAD then + // insert into one lane of 128-bit register + Elem[rval, index, esize] = Mem[address + offs, ebytes, AccType_VEC]; + V[t] = rval; + else // memop == MemOp_STORE + // extract from one lane of 128-bit register + Mem[address + offs, ebytes, AccType_VEC] = Elem[rval, index, esize]; + end + offs = offs + ebytes; + t = (t + 1) MOD 32; +end + +if wback then + if m != 31 then + offs = X[m]; + end + if n == 31 then + SP[] = address + offs; + else + X[n] = address + offs; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ldar b/instructionAPI/ISA_ps/ldar new file mode 100644 index 0000000000..f696675f6b --- /dev/null +++ b/instructionAPI/ISA_ps/ldar @@ -0,0 +1,22 @@ +##ldar_execute +bits(64) address; +bits(datasize) data; +constant integer dbytes = datasize / 8; + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +case memop of + when MemOp_STORE + data = X[t]; + Mem[address, dbytes, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, dbytes, acctype]; + X[t] = ZeroExtend(data, regsize); + end +@@ diff --git a/instructionAPI/ISA_ps/ldarb b/instructionAPI/ISA_ps/ldarb new file mode 100644 index 0000000000..ba78eb9769 --- /dev/null +++ b/instructionAPI/ISA_ps/ldarb @@ -0,0 +1,22 @@ +##ldarb_execute +bits(64) address; +bits(datasize) data; +constant integer dbytes = datasize / 8; + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +case memop of + when MemOp_STORE + data = X[t]; + Mem[address, dbytes, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, dbytes, acctype]; + X[t] = ZeroExtend(data, regsize); + end +@@ diff --git a/instructionAPI/ISA_ps/ldarh b/instructionAPI/ISA_ps/ldarh new file mode 100644 index 0000000000..bde8b7abda --- /dev/null +++ b/instructionAPI/ISA_ps/ldarh @@ -0,0 +1,22 @@ +##ldarh_execute +bits(64) address; +bits(datasize) data; +constant integer dbytes = datasize / 8; + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +case memop of + when MemOp_STORE + data = X[t]; + Mem[address, dbytes, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, dbytes, acctype]; + X[t] = ZeroExtend(data, regsize); + end +@@ diff --git a/instructionAPI/ISA_ps/ldaxp b/instructionAPI/ISA_ps/ldaxp new file mode 100644 index 0000000000..b874ce2042 --- /dev/null +++ b/instructionAPI/ISA_ps/ldaxp @@ -0,0 +1,94 @@ +##ldaxp_execute +bits(64) address; +bits(datasize) data; +constant integer dbytes = datasize / 8; +boolean rt_unknown = FALSE; +boolean rn_unknown = FALSE; + +if memop == MemOp_LOAD && pair && t == t2 then + case c of +end + +if memop == MemOp_STORE then + if s == t || (pair && s == t2) then + case c of + end + if s == n && n != 31 then + case c of + end + +end +if n == 31 then + address = SP[]; +elsif rn_unknown then + address = bits(64) UNKNOWN; +else + address = X[n]; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + elsif pair then + bits(datasize / 2) el1 = X[t]; + bits(datasize / 2) el2 = X[t2]; + data = if BigEndian() then el1 : el2 else el2 : el1; + else + end + data = X[t]; + end + + bit status = 1; + // Check whether the Exclusive Monitors are set to include the + // physical memory locations corresponding to virtual address + // range [address, address+dbytes-1]. + if AArch64.ExclusiveMonitorsPass(address, dbytes) then + // This atomic write will be rejected if it does not refer + // to the same physical locations after address translation. + Mem[address, dbytes, acctype] = data; + status = ExclusiveMonitorsStatus(); + end + X[s] = ZeroExtend(status, 32); + end + + when MemOp_LOAD + // Tell the Exclusive Monitors to record a sequence of one or more atomic + // memory reads from virtual address range [address, address+dbytes-1]. + // The Exclusive Monitor will only be set if all the reads are from the + // same dbytes-aligned physical address, to allow for the possibility of + // an atomicity break if the translation is changed between reads. + AArch64.SetExclusiveMonitors(address, dbytes); + end + + if pair then + // load exclusive pair + if rt_unknown then + X[t] = bits(datasize) UNKNOWN; + elsif elsize == 32 then + // 32-bit load exclusive pair (atomic) + data = Mem[address, dbytes, acctype]; + if BigEndian() then + X[t] = data; + X[t2] = data; + else + X[t] = data; + X[t2] = data; + else // elsize == 64 + end + // 64-bit load exclusive pair (not atomic), + // but must be 128-bit aligned + if address != Align(address, dbytes) then + iswrite = FALSE; + secondstage = FALSE; + AArch64.Abort(address, AArch64.AlignmentFault(acctype, iswrite, secondstage)); + end + X[t] = Mem[address + 0, 8, acctype]; + X[t2] = Mem[address + 8, 8, acctype]; + else + end + // load {acquire} {exclusive} single register + data = Mem[address, dbytes, acctype]; + X[t] = ZeroExtend(data, regsize); + end +@@ diff --git a/instructionAPI/ISA_ps/ldaxr b/instructionAPI/ISA_ps/ldaxr new file mode 100644 index 0000000000..8655c3c78b --- /dev/null +++ b/instructionAPI/ISA_ps/ldaxr @@ -0,0 +1,94 @@ +##ldaxr_execute +bits(64) address; +bits(datasize) data; +constant integer dbytes = datasize / 8; +boolean rt_unknown = FALSE; +boolean rn_unknown = FALSE; + +if memop == MemOp_LOAD && pair && t == t2 then + case c of +end + +if memop == MemOp_STORE then + if s == t || (pair && s == t2) then + case c of + end + if s == n && n != 31 then + case c of + end + +end +if n == 31 then + address = SP[]; +elsif rn_unknown then + address = bits(64) UNKNOWN; +else + address = X[n]; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + elsif pair then + bits(datasize / 2) el1 = X[t]; + bits(datasize / 2) el2 = X[t2]; + data = if BigEndian() then el1 : el2 else el2 : el1; + else + end + data = X[t]; + end + + bit status = 1; + // Check whether the Exclusive Monitors are set to include the + // physical memory locations corresponding to virtual address + // range [address, address+dbytes-1]. + if AArch64.ExclusiveMonitorsPass(address, dbytes) then + // This atomic write will be rejected if it does not refer + // to the same physical locations after address translation. + Mem[address, dbytes, acctype] = data; + status = ExclusiveMonitorsStatus(); + end + X[s] = ZeroExtend(status, 32); + end + + when MemOp_LOAD + // Tell the Exclusive Monitors to record a sequence of one or more atomic + // memory reads from virtual address range [address, address+dbytes-1]. + // The Exclusive Monitor will only be set if all the reads are from the + // same dbytes-aligned physical address, to allow for the possibility of + // an atomicity break if the translation is changed between reads. + AArch64.SetExclusiveMonitors(address, dbytes); + end + + if pair then + // load exclusive pair + if rt_unknown then + X[t] = bits(datasize) UNKNOWN; + elsif elsize == 32 then + // 32-bit load exclusive pair (atomic) + data = Mem[address, dbytes, acctype]; + if BigEndian() then + X[t] = data; + X[t2] = data; + else + X[t] = data; + X[t2] = data; + else // elsize == 64 + end + // 64-bit load exclusive pair (not atomic), + // but must be 128-bit aligned + if address != Align(address, dbytes) then + iswrite = FALSE; + secondstage = FALSE; + AArch64.Abort(address, AArch64.AlignmentFault(acctype, iswrite, secondstage)); + end + X[t] = Mem[address + 0, 8, acctype]; + X[t2] = Mem[address + 8, 8, acctype]; + else + end + // load {acquire} {exclusive} single register + data = Mem[address, dbytes, acctype]; + X[t] = ZeroExtend(data, regsize); + end +@@ diff --git a/instructionAPI/ISA_ps/ldaxrb b/instructionAPI/ISA_ps/ldaxrb new file mode 100644 index 0000000000..b5e818e397 --- /dev/null +++ b/instructionAPI/ISA_ps/ldaxrb @@ -0,0 +1,94 @@ +##ldaxrb_execute +bits(64) address; +bits(datasize) data; +constant integer dbytes = datasize / 8; +boolean rt_unknown = FALSE; +boolean rn_unknown = FALSE; + +if memop == MemOp_LOAD && pair && t == t2 then + case c of +end + +if memop == MemOp_STORE then + if s == t || (pair && s == t2) then + case c of + end + if s == n && n != 31 then + case c of + end + +end +if n == 31 then + address = SP[]; +elsif rn_unknown then + address = bits(64) UNKNOWN; +else + address = X[n]; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + elsif pair then + bits(datasize / 2) el1 = X[t]; + bits(datasize / 2) el2 = X[t2]; + data = if BigEndian() then el1 : el2 else el2 : el1; + else + end + data = X[t]; + end + + bit status = 1; + // Check whether the Exclusive Monitors are set to include the + // physical memory locations corresponding to virtual address + // range [address, address+dbytes-1]. + if AArch64.ExclusiveMonitorsPass(address, dbytes) then + // This atomic write will be rejected if it does not refer + // to the same physical locations after address translation. + Mem[address, dbytes, acctype] = data; + status = ExclusiveMonitorsStatus(); + end + X[s] = ZeroExtend(status, 32); + end + + when MemOp_LOAD + // Tell the Exclusive Monitors to record a sequence of one or more atomic + // memory reads from virtual address range [address, address+dbytes-1]. + // The Exclusive Monitor will only be set if all the reads are from the + // same dbytes-aligned physical address, to allow for the possibility of + // an atomicity break if the translation is changed between reads. + AArch64.SetExclusiveMonitors(address, dbytes); + end + + if pair then + // load exclusive pair + if rt_unknown then + X[t] = bits(datasize) UNKNOWN; + elsif elsize == 32 then + // 32-bit load exclusive pair (atomic) + data = Mem[address, dbytes, acctype]; + if BigEndian() then + X[t] = data; + X[t2] = data; + else + X[t] = data; + X[t2] = data; + else // elsize == 64 + end + // 64-bit load exclusive pair (not atomic), + // but must be 128-bit aligned + if address != Align(address, dbytes) then + iswrite = FALSE; + secondstage = FALSE; + AArch64.Abort(address, AArch64.AlignmentFault(acctype, iswrite, secondstage)); + end + X[t] = Mem[address + 0, 8, acctype]; + X[t2] = Mem[address + 8, 8, acctype]; + else + end + // load {acquire} {exclusive} single register + data = Mem[address, dbytes, acctype]; + X[t] = ZeroExtend(data, regsize); + end +@@ diff --git a/instructionAPI/ISA_ps/ldaxrh b/instructionAPI/ISA_ps/ldaxrh new file mode 100644 index 0000000000..dc60cda727 --- /dev/null +++ b/instructionAPI/ISA_ps/ldaxrh @@ -0,0 +1,94 @@ +##ldaxrh_execute +bits(64) address; +bits(datasize) data; +constant integer dbytes = datasize / 8; +boolean rt_unknown = FALSE; +boolean rn_unknown = FALSE; + +if memop == MemOp_LOAD && pair && t == t2 then + case c of +end + +if memop == MemOp_STORE then + if s == t || (pair && s == t2) then + case c of + end + if s == n && n != 31 then + case c of + end + +end +if n == 31 then + address = SP[]; +elsif rn_unknown then + address = bits(64) UNKNOWN; +else + address = X[n]; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + elsif pair then + bits(datasize / 2) el1 = X[t]; + bits(datasize / 2) el2 = X[t2]; + data = if BigEndian() then el1 : el2 else el2 : el1; + else + end + data = X[t]; + end + + bit status = 1; + // Check whether the Exclusive Monitors are set to include the + // physical memory locations corresponding to virtual address + // range [address, address+dbytes-1]. + if AArch64.ExclusiveMonitorsPass(address, dbytes) then + // This atomic write will be rejected if it does not refer + // to the same physical locations after address translation. + Mem[address, dbytes, acctype] = data; + status = ExclusiveMonitorsStatus(); + end + X[s] = ZeroExtend(status, 32); + end + + when MemOp_LOAD + // Tell the Exclusive Monitors to record a sequence of one or more atomic + // memory reads from virtual address range [address, address+dbytes-1]. + // The Exclusive Monitor will only be set if all the reads are from the + // same dbytes-aligned physical address, to allow for the possibility of + // an atomicity break if the translation is changed between reads. + AArch64.SetExclusiveMonitors(address, dbytes); + end + + if pair then + // load exclusive pair + if rt_unknown then + X[t] = bits(datasize) UNKNOWN; + elsif elsize == 32 then + // 32-bit load exclusive pair (atomic) + data = Mem[address, dbytes, acctype]; + if BigEndian() then + X[t] = data; + X[t2] = data; + else + X[t] = data; + X[t2] = data; + else // elsize == 64 + end + // 64-bit load exclusive pair (not atomic), + // but must be 128-bit aligned + if address != Align(address, dbytes) then + iswrite = FALSE; + secondstage = FALSE; + AArch64.Abort(address, AArch64.AlignmentFault(acctype, iswrite, secondstage)); + end + X[t] = Mem[address + 0, 8, acctype]; + X[t2] = Mem[address + 8, 8, acctype]; + else + end + // load {acquire} {exclusive} single register + data = Mem[address, dbytes, acctype]; + X[t] = ZeroExtend(data, regsize); + end +@@ diff --git a/instructionAPI/ISA_ps/ldnp_fpsimd b/instructionAPI/ISA_ps/ldnp_fpsimd new file mode 100644 index 0000000000..1a4250d5be --- /dev/null +++ b/instructionAPI/ISA_ps/ldnp_fpsimd @@ -0,0 +1,53 @@ +##ldnp_fpsimd_execute +CheckFPAdvSIMDEnabled64(); + +bits(64) address; +bits(datasize) data1; +bits(datasize) data2; +constant integer dbytes = datasize / 8; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && t == t2 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + data1 = V[t]; + data2 = V[t2]; + Mem[address + 0 , dbytes, acctype] = data1; + Mem[address + dbytes, dbytes, acctype] = data2; + end + + when MemOp_LOAD + data1 = Mem[address + 0 , dbytes, acctype]; + data2 = Mem[address + dbytes, dbytes, acctype]; + if rt_unknown then + data1 = bits(datasize) UNKNOWN; + data2 = bits(datasize) UNKNOWN; + end + V[t] = data1; + V[t2] = data2; + end + +if wback then + if postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ldnp_gen b/instructionAPI/ISA_ps/ldnp_gen new file mode 100644 index 0000000000..385c73984c --- /dev/null +++ b/instructionAPI/ISA_ps/ldnp_gen @@ -0,0 +1,59 @@ +##ldnp_gen_execute +bits(64) address; +bits(datasize) data1; +bits(datasize) data2; +constant integer dbytes = datasize / 8; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && t == t2 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown && t == n then + data1 = bits(datasize) UNKNOWN; + else + data1 = X[t]; + end + if rt_unknown && t2 == n then + data2 = bits(datasize) UNKNOWN; + else + data2 = X[t2]; + end + Mem[address + 0 , dbytes, acctype] = data1; + Mem[address + dbytes, dbytes, acctype] = data2; + end + + when MemOp_LOAD + data1 = Mem[address + 0 , dbytes, acctype]; + data2 = Mem[address + dbytes, dbytes, acctype]; + if rt_unknown then + data1 = bits(datasize) UNKNOWN; + data2 = bits(datasize) UNKNOWN; + end + X[t] = data1; + X[t2] = data2; + end + +if wback then + if postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ldp_fpsimd b/instructionAPI/ISA_ps/ldp_fpsimd new file mode 100644 index 0000000000..be24093bb5 --- /dev/null +++ b/instructionAPI/ISA_ps/ldp_fpsimd @@ -0,0 +1,53 @@ +##ldp_fpsimd_execute +CheckFPAdvSIMDEnabled64(); + +bits(64) address; +bits(datasize) data1; +bits(datasize) data2; +constant integer dbytes = datasize / 8; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && t == t2 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + data1 = V[t]; + data2 = V[t2]; + Mem[address + 0 , dbytes, acctype] = data1; + Mem[address + dbytes, dbytes, acctype] = data2; + end + + when MemOp_LOAD + data1 = Mem[address + 0 , dbytes, acctype]; + data2 = Mem[address + dbytes, dbytes, acctype]; + if rt_unknown then + data1 = bits(datasize) UNKNOWN; + data2 = bits(datasize) UNKNOWN; + end + V[t] = data1; + V[t2] = data2; + end + +if wback then + if postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ldp_gen b/instructionAPI/ISA_ps/ldp_gen new file mode 100644 index 0000000000..26b2b9e627 --- /dev/null +++ b/instructionAPI/ISA_ps/ldp_gen @@ -0,0 +1,75 @@ +##ldp_gen_execute +bits(64) address; +bits(datasize) data1; +bits(datasize) data2; +constant integer dbytes = datasize / 8; +boolean rt_unknown = FALSE; +boolean wb_unknown = FALSE; + +if memop == MemOp_LOAD && wback && (t == n || t2 == n) && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && (t == n || t2 == n) && n != 31 then + case c of +end + +if memop == MemOp_LOAD && t == t2 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown && t == n then + data1 = bits(datasize) UNKNOWN; + else + data1 = X[t]; + end + if rt_unknown && t2 == n then + data2 = bits(datasize) UNKNOWN; + else + data2 = X[t2]; + end + Mem[address + 0 , dbytes, acctype] = data1; + Mem[address + dbytes, dbytes, acctype] = data2; + end + + when MemOp_LOAD + data1 = Mem[address + 0 , dbytes, acctype]; + data2 = Mem[address + dbytes, dbytes, acctype]; + if rt_unknown then + data1 = bits(datasize) UNKNOWN; + data2 = bits(datasize) UNKNOWN; + end + if signed then + X[t] = SignExtend(data1, 64); + X[t2] = SignExtend(data2, 64); + else + X[t] = data1; + X[t2] = data2; + end + + end +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ldpsw b/instructionAPI/ISA_ps/ldpsw new file mode 100644 index 0000000000..34e03c931d --- /dev/null +++ b/instructionAPI/ISA_ps/ldpsw @@ -0,0 +1,75 @@ +##ldpsw_execute +bits(64) address; +bits(datasize) data1; +bits(datasize) data2; +constant integer dbytes = datasize / 8; +boolean rt_unknown = FALSE; +boolean wb_unknown = FALSE; + +if memop == MemOp_LOAD && wback && (t == n || t2 == n) && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && (t == n || t2 == n) && n != 31 then + case c of +end + +if memop == MemOp_LOAD && t == t2 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown && t == n then + data1 = bits(datasize) UNKNOWN; + else + data1 = X[t]; + end + if rt_unknown && t2 == n then + data2 = bits(datasize) UNKNOWN; + else + data2 = X[t2]; + end + Mem[address + 0 , dbytes, acctype] = data1; + Mem[address + dbytes, dbytes, acctype] = data2; + end + + when MemOp_LOAD + data1 = Mem[address + 0 , dbytes, acctype]; + data2 = Mem[address + dbytes, dbytes, acctype]; + if rt_unknown then + data1 = bits(datasize) UNKNOWN; + data2 = bits(datasize) UNKNOWN; + end + if signed then + X[t] = SignExtend(data1, 64); + X[t2] = SignExtend(data2, 64); + else + X[t] = data1; + X[t2] = data2; + end + + end +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ldr_imm_fpsimd b/instructionAPI/ISA_ps/ldr_imm_fpsimd new file mode 100644 index 0000000000..a665539ee2 --- /dev/null +++ b/instructionAPI/ISA_ps/ldr_imm_fpsimd @@ -0,0 +1,38 @@ +##ldr_imm_fpsimd_execute +CheckFPAdvSIMDEnabled64(); + +bits(64) address; +bits(datasize) data; + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + data = V[t]; + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + V[t] = data; + end + +if wback then + if postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ldr_imm_gen b/instructionAPI/ISA_ps/ldr_imm_gen new file mode 100644 index 0000000000..475e36436e --- /dev/null +++ b/instructionAPI/ISA_ps/ldr_imm_gen @@ -0,0 +1,60 @@ +##ldr_imm_gen_execute +bits(64) address; +bits(datasize) data; +boolean wb_unknown = FALSE; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && wback && n == t && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && n == t && n != 31 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + else + data = X[t]; + end + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + if signed then + X[t] = SignExtend(data, regsize); + else + X[t] = ZeroExtend(data, regsize); + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ldr_lit_fpsimd b/instructionAPI/ISA_ps/ldr_lit_fpsimd new file mode 100644 index 0000000000..a4120885f5 --- /dev/null +++ b/instructionAPI/ISA_ps/ldr_lit_fpsimd @@ -0,0 +1,9 @@ +##ldr_lit_fpsimd_execute +bits(64) address = PC[] + offset; +bits(size*8) data; + +CheckFPAdvSIMDEnabled64(); + +data = Mem[address, size, AccType_VEC]; +V[t] = data; +@@ diff --git a/instructionAPI/ISA_ps/ldr_lit_gen b/instructionAPI/ISA_ps/ldr_lit_gen new file mode 100644 index 0000000000..0df8213b1b --- /dev/null +++ b/instructionAPI/ISA_ps/ldr_lit_gen @@ -0,0 +1,18 @@ +##ldr_lit_gen_execute +bits(64) address = PC[] + offset; +bits(size*8) data; + +case memop of + when MemOp_LOAD + data = Mem[address, size, AccType_NORMAL]; + if signed then + X[t] = SignExtend(data, 64); + else + X[t] = data; + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end +@@ diff --git a/instructionAPI/ISA_ps/ldr_reg_fpsimd b/instructionAPI/ISA_ps/ldr_reg_fpsimd new file mode 100644 index 0000000000..cc977b2b46 --- /dev/null +++ b/instructionAPI/ISA_ps/ldr_reg_fpsimd @@ -0,0 +1,39 @@ +##ldr_reg_fpsimd_execute +bits(64) offset = ExtendReg(m, extend_type, shift); +CheckFPAdvSIMDEnabled64(); + +bits(64) address; +bits(datasize) data; + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + data = V[t]; + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + V[t] = data; + end + +if wback then + if postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ldr_reg_gen b/instructionAPI/ISA_ps/ldr_reg_gen new file mode 100644 index 0000000000..8ab0221b40 --- /dev/null +++ b/instructionAPI/ISA_ps/ldr_reg_gen @@ -0,0 +1,61 @@ +##ldr_reg_gen_execute +bits(64) offset = ExtendReg(m, extend_type, shift); +bits(64) address; +bits(datasize) data; +boolean wb_unknown = FALSE; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && wback && n == t && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && n == t && n != 31 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + else + data = X[t]; + end + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + if signed then + X[t] = SignExtend(data, regsize); + else + X[t] = ZeroExtend(data, regsize); + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ldrb_imm b/instructionAPI/ISA_ps/ldrb_imm new file mode 100644 index 0000000000..b8e1593fda --- /dev/null +++ b/instructionAPI/ISA_ps/ldrb_imm @@ -0,0 +1,60 @@ +##ldrb_imm_execute +bits(64) address; +bits(datasize) data; +boolean wb_unknown = FALSE; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && wback && n == t && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && n == t && n != 31 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + else + data = X[t]; + end + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + if signed then + X[t] = SignExtend(data, regsize); + else + X[t] = ZeroExtend(data, regsize); + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ldrb_reg b/instructionAPI/ISA_ps/ldrb_reg new file mode 100644 index 0000000000..95c463002a --- /dev/null +++ b/instructionAPI/ISA_ps/ldrb_reg @@ -0,0 +1,61 @@ +##ldrb_reg_execute +bits(64) offset = ExtendReg(m, extend_type, shift); +bits(64) address; +bits(datasize) data; +boolean wb_unknown = FALSE; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && wback && n == t && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && n == t && n != 31 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + else + data = X[t]; + end + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + if signed then + X[t] = SignExtend(data, regsize); + else + X[t] = ZeroExtend(data, regsize); + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ldrh_imm b/instructionAPI/ISA_ps/ldrh_imm new file mode 100644 index 0000000000..ebd280ca0d --- /dev/null +++ b/instructionAPI/ISA_ps/ldrh_imm @@ -0,0 +1,60 @@ +##ldrh_imm_execute +bits(64) address; +bits(datasize) data; +boolean wb_unknown = FALSE; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && wback && n == t && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && n == t && n != 31 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + else + data = X[t]; + end + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + if signed then + X[t] = SignExtend(data, regsize); + else + X[t] = ZeroExtend(data, regsize); + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ldrh_reg b/instructionAPI/ISA_ps/ldrh_reg new file mode 100644 index 0000000000..6da5d367e1 --- /dev/null +++ b/instructionAPI/ISA_ps/ldrh_reg @@ -0,0 +1,61 @@ +##ldrh_reg_execute +bits(64) offset = ExtendReg(m, extend_type, shift); +bits(64) address; +bits(datasize) data; +boolean wb_unknown = FALSE; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && wback && n == t && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && n == t && n != 31 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + else + data = X[t]; + end + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + if signed then + X[t] = SignExtend(data, regsize); + else + X[t] = ZeroExtend(data, regsize); + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ldrsb_imm b/instructionAPI/ISA_ps/ldrsb_imm new file mode 100644 index 0000000000..facef13352 --- /dev/null +++ b/instructionAPI/ISA_ps/ldrsb_imm @@ -0,0 +1,60 @@ +##ldrsb_imm_execute +bits(64) address; +bits(datasize) data; +boolean wb_unknown = FALSE; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && wback && n == t && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && n == t && n != 31 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + else + data = X[t]; + end + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + if signed then + X[t] = SignExtend(data, regsize); + else + X[t] = ZeroExtend(data, regsize); + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ldrsb_reg b/instructionAPI/ISA_ps/ldrsb_reg new file mode 100644 index 0000000000..2679e7bbbd --- /dev/null +++ b/instructionAPI/ISA_ps/ldrsb_reg @@ -0,0 +1,61 @@ +##ldrsb_reg_execute +bits(64) offset = ExtendReg(m, extend_type, shift); +bits(64) address; +bits(datasize) data; +boolean wb_unknown = FALSE; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && wback && n == t && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && n == t && n != 31 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + else + data = X[t]; + end + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + if signed then + X[t] = SignExtend(data, regsize); + else + X[t] = ZeroExtend(data, regsize); + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ldrsh_imm b/instructionAPI/ISA_ps/ldrsh_imm new file mode 100644 index 0000000000..7fde046b66 --- /dev/null +++ b/instructionAPI/ISA_ps/ldrsh_imm @@ -0,0 +1,60 @@ +##ldrsh_imm_execute +bits(64) address; +bits(datasize) data; +boolean wb_unknown = FALSE; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && wback && n == t && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && n == t && n != 31 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + else + data = X[t]; + end + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + if signed then + X[t] = SignExtend(data, regsize); + else + X[t] = ZeroExtend(data, regsize); + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ldrsh_reg b/instructionAPI/ISA_ps/ldrsh_reg new file mode 100644 index 0000000000..9c6aa670ef --- /dev/null +++ b/instructionAPI/ISA_ps/ldrsh_reg @@ -0,0 +1,61 @@ +##ldrsh_reg_execute +bits(64) offset = ExtendReg(m, extend_type, shift); +bits(64) address; +bits(datasize) data; +boolean wb_unknown = FALSE; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && wback && n == t && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && n == t && n != 31 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + else + data = X[t]; + end + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + if signed then + X[t] = SignExtend(data, regsize); + else + X[t] = ZeroExtend(data, regsize); + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ldrsw_imm b/instructionAPI/ISA_ps/ldrsw_imm new file mode 100644 index 0000000000..0a77c7abbb --- /dev/null +++ b/instructionAPI/ISA_ps/ldrsw_imm @@ -0,0 +1,60 @@ +##ldrsw_imm_execute +bits(64) address; +bits(datasize) data; +boolean wb_unknown = FALSE; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && wback && n == t && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && n == t && n != 31 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + else + data = X[t]; + end + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + if signed then + X[t] = SignExtend(data, regsize); + else + X[t] = ZeroExtend(data, regsize); + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ldrsw_lit b/instructionAPI/ISA_ps/ldrsw_lit new file mode 100644 index 0000000000..9432aa8e5f --- /dev/null +++ b/instructionAPI/ISA_ps/ldrsw_lit @@ -0,0 +1,18 @@ +##ldrsw_lit_execute +bits(64) address = PC[] + offset; +bits(size*8) data; + +case memop of + when MemOp_LOAD + data = Mem[address, size, AccType_NORMAL]; + if signed then + X[t] = SignExtend(data, 64); + else + X[t] = data; + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end +@@ diff --git a/instructionAPI/ISA_ps/ldrsw_reg b/instructionAPI/ISA_ps/ldrsw_reg new file mode 100644 index 0000000000..78bb63b7fe --- /dev/null +++ b/instructionAPI/ISA_ps/ldrsw_reg @@ -0,0 +1,61 @@ +##ldrsw_reg_execute +bits(64) offset = ExtendReg(m, extend_type, shift); +bits(64) address; +bits(datasize) data; +boolean wb_unknown = FALSE; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && wback && n == t && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && n == t && n != 31 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + else + data = X[t]; + end + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + if signed then + X[t] = SignExtend(data, regsize); + else + X[t] = ZeroExtend(data, regsize); + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ldtr b/instructionAPI/ISA_ps/ldtr new file mode 100644 index 0000000000..729f4cc831 --- /dev/null +++ b/instructionAPI/ISA_ps/ldtr @@ -0,0 +1,60 @@ +##ldtr_execute +bits(64) address; +bits(datasize) data; +boolean wb_unknown = FALSE; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && wback && n == t && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && n == t && n != 31 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + else + data = X[t]; + end + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + if signed then + X[t] = SignExtend(data, regsize); + else + X[t] = ZeroExtend(data, regsize); + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ldtrb b/instructionAPI/ISA_ps/ldtrb new file mode 100644 index 0000000000..79038c3030 --- /dev/null +++ b/instructionAPI/ISA_ps/ldtrb @@ -0,0 +1,60 @@ +##ldtrb_execute +bits(64) address; +bits(datasize) data; +boolean wb_unknown = FALSE; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && wback && n == t && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && n == t && n != 31 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + else + data = X[t]; + end + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + if signed then + X[t] = SignExtend(data, regsize); + else + X[t] = ZeroExtend(data, regsize); + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ldtrh b/instructionAPI/ISA_ps/ldtrh new file mode 100644 index 0000000000..786f9ce24f --- /dev/null +++ b/instructionAPI/ISA_ps/ldtrh @@ -0,0 +1,60 @@ +##ldtrh_execute +bits(64) address; +bits(datasize) data; +boolean wb_unknown = FALSE; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && wback && n == t && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && n == t && n != 31 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + else + data = X[t]; + end + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + if signed then + X[t] = SignExtend(data, regsize); + else + X[t] = ZeroExtend(data, regsize); + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ldtrsb b/instructionAPI/ISA_ps/ldtrsb new file mode 100644 index 0000000000..e1260a2d48 --- /dev/null +++ b/instructionAPI/ISA_ps/ldtrsb @@ -0,0 +1,60 @@ +##ldtrsb_execute +bits(64) address; +bits(datasize) data; +boolean wb_unknown = FALSE; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && wback && n == t && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && n == t && n != 31 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + else + data = X[t]; + end + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + if signed then + X[t] = SignExtend(data, regsize); + else + X[t] = ZeroExtend(data, regsize); + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ldtrsh b/instructionAPI/ISA_ps/ldtrsh new file mode 100644 index 0000000000..fb35b198b6 --- /dev/null +++ b/instructionAPI/ISA_ps/ldtrsh @@ -0,0 +1,60 @@ +##ldtrsh_execute +bits(64) address; +bits(datasize) data; +boolean wb_unknown = FALSE; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && wback && n == t && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && n == t && n != 31 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + else + data = X[t]; + end + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + if signed then + X[t] = SignExtend(data, regsize); + else + X[t] = ZeroExtend(data, regsize); + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ldtrsw b/instructionAPI/ISA_ps/ldtrsw new file mode 100644 index 0000000000..2275b920b1 --- /dev/null +++ b/instructionAPI/ISA_ps/ldtrsw @@ -0,0 +1,60 @@ +##ldtrsw_execute +bits(64) address; +bits(datasize) data; +boolean wb_unknown = FALSE; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && wback && n == t && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && n == t && n != 31 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + else + data = X[t]; + end + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + if signed then + X[t] = SignExtend(data, regsize); + else + X[t] = ZeroExtend(data, regsize); + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ldur_fpsimd b/instructionAPI/ISA_ps/ldur_fpsimd new file mode 100644 index 0000000000..6f732ab360 --- /dev/null +++ b/instructionAPI/ISA_ps/ldur_fpsimd @@ -0,0 +1,38 @@ +##ldur_fpsimd_execute +CheckFPAdvSIMDEnabled64(); + +bits(64) address; +bits(datasize) data; + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + data = V[t]; + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + V[t] = data; + end + +if wback then + if postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ldur_gen b/instructionAPI/ISA_ps/ldur_gen new file mode 100644 index 0000000000..199a5264fe --- /dev/null +++ b/instructionAPI/ISA_ps/ldur_gen @@ -0,0 +1,60 @@ +##ldur_gen_execute +bits(64) address; +bits(datasize) data; +boolean wb_unknown = FALSE; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && wback && n == t && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && n == t && n != 31 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + else + data = X[t]; + end + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + if signed then + X[t] = SignExtend(data, regsize); + else + X[t] = ZeroExtend(data, regsize); + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ldurb b/instructionAPI/ISA_ps/ldurb new file mode 100644 index 0000000000..885df6eedf --- /dev/null +++ b/instructionAPI/ISA_ps/ldurb @@ -0,0 +1,60 @@ +##ldurb_execute +bits(64) address; +bits(datasize) data; +boolean wb_unknown = FALSE; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && wback && n == t && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && n == t && n != 31 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + else + data = X[t]; + end + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + if signed then + X[t] = SignExtend(data, regsize); + else + X[t] = ZeroExtend(data, regsize); + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ldurh b/instructionAPI/ISA_ps/ldurh new file mode 100644 index 0000000000..988d83bafe --- /dev/null +++ b/instructionAPI/ISA_ps/ldurh @@ -0,0 +1,60 @@ +##ldurh_execute +bits(64) address; +bits(datasize) data; +boolean wb_unknown = FALSE; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && wback && n == t && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && n == t && n != 31 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + else + data = X[t]; + end + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + if signed then + X[t] = SignExtend(data, regsize); + else + X[t] = ZeroExtend(data, regsize); + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ldursb b/instructionAPI/ISA_ps/ldursb new file mode 100644 index 0000000000..dbbb04b4be --- /dev/null +++ b/instructionAPI/ISA_ps/ldursb @@ -0,0 +1,60 @@ +##ldursb_execute +bits(64) address; +bits(datasize) data; +boolean wb_unknown = FALSE; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && wback && n == t && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && n == t && n != 31 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + else + data = X[t]; + end + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + if signed then + X[t] = SignExtend(data, regsize); + else + X[t] = ZeroExtend(data, regsize); + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ldursh b/instructionAPI/ISA_ps/ldursh new file mode 100644 index 0000000000..5c27670a88 --- /dev/null +++ b/instructionAPI/ISA_ps/ldursh @@ -0,0 +1,60 @@ +##ldursh_execute +bits(64) address; +bits(datasize) data; +boolean wb_unknown = FALSE; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && wback && n == t && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && n == t && n != 31 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + else + data = X[t]; + end + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + if signed then + X[t] = SignExtend(data, regsize); + else + X[t] = ZeroExtend(data, regsize); + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ldursw b/instructionAPI/ISA_ps/ldursw new file mode 100644 index 0000000000..52aa516597 --- /dev/null +++ b/instructionAPI/ISA_ps/ldursw @@ -0,0 +1,60 @@ +##ldursw_execute +bits(64) address; +bits(datasize) data; +boolean wb_unknown = FALSE; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && wback && n == t && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && n == t && n != 31 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + else + data = X[t]; + end + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + if signed then + X[t] = SignExtend(data, regsize); + else + X[t] = ZeroExtend(data, regsize); + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/ldxp b/instructionAPI/ISA_ps/ldxp new file mode 100644 index 0000000000..99795f6f05 --- /dev/null +++ b/instructionAPI/ISA_ps/ldxp @@ -0,0 +1,94 @@ +##ldxp_execute +bits(64) address; +bits(datasize) data; +constant integer dbytes = datasize / 8; +boolean rt_unknown = FALSE; +boolean rn_unknown = FALSE; + +if memop == MemOp_LOAD && pair && t == t2 then + case c of +end + +if memop == MemOp_STORE then + if s == t || (pair && s == t2) then + case c of + end + if s == n && n != 31 then + case c of + end + +end +if n == 31 then + address = SP[]; +elsif rn_unknown then + address = bits(64) UNKNOWN; +else + address = X[n]; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + elsif pair then + bits(datasize / 2) el1 = X[t]; + bits(datasize / 2) el2 = X[t2]; + data = if BigEndian() then el1 : el2 else el2 : el1; + else + end + data = X[t]; + end + + bit status = 1; + // Check whether the Exclusive Monitors are set to include the + // physical memory locations corresponding to virtual address + // range [address, address+dbytes-1]. + if AArch64.ExclusiveMonitorsPass(address, dbytes) then + // This atomic write will be rejected if it does not refer + // to the same physical locations after address translation. + Mem[address, dbytes, acctype] = data; + status = ExclusiveMonitorsStatus(); + end + X[s] = ZeroExtend(status, 32); + end + + when MemOp_LOAD + // Tell the Exclusive Monitors to record a sequence of one or more atomic + // memory reads from virtual address range [address, address+dbytes-1]. + // The Exclusive Monitor will only be set if all the reads are from the + // same dbytes-aligned physical address, to allow for the possibility of + // an atomicity break if the translation is changed between reads. + AArch64.SetExclusiveMonitors(address, dbytes); + end + + if pair then + // load exclusive pair + if rt_unknown then + X[t] = bits(datasize) UNKNOWN; + elsif elsize == 32 then + // 32-bit load exclusive pair (atomic) + data = Mem[address, dbytes, acctype]; + if BigEndian() then + X[t] = data; + X[t2] = data; + else + X[t] = data; + X[t2] = data; + else // elsize == 64 + end + // 64-bit load exclusive pair (not atomic), + // but must be 128-bit aligned + if address != Align(address, dbytes) then + iswrite = FALSE; + secondstage = FALSE; + AArch64.Abort(address, AArch64.AlignmentFault(acctype, iswrite, secondstage)); + end + X[t] = Mem[address + 0, 8, acctype]; + X[t2] = Mem[address + 8, 8, acctype]; + else + end + // load {acquire} {exclusive} single register + data = Mem[address, dbytes, acctype]; + X[t] = ZeroExtend(data, regsize); + end +@@ diff --git a/instructionAPI/ISA_ps/ldxr b/instructionAPI/ISA_ps/ldxr new file mode 100644 index 0000000000..375c5fecb8 --- /dev/null +++ b/instructionAPI/ISA_ps/ldxr @@ -0,0 +1,94 @@ +##ldxr_execute +bits(64) address; +bits(datasize) data; +constant integer dbytes = datasize / 8; +boolean rt_unknown = FALSE; +boolean rn_unknown = FALSE; + +if memop == MemOp_LOAD && pair && t == t2 then + case c of +end + +if memop == MemOp_STORE then + if s == t || (pair && s == t2) then + case c of + end + if s == n && n != 31 then + case c of + end + +end +if n == 31 then + address = SP[]; +elsif rn_unknown then + address = bits(64) UNKNOWN; +else + address = X[n]; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + elsif pair then + bits(datasize / 2) el1 = X[t]; + bits(datasize / 2) el2 = X[t2]; + data = if BigEndian() then el1 : el2 else el2 : el1; + else + end + data = X[t]; + end + + bit status = 1; + // Check whether the Exclusive Monitors are set to include the + // physical memory locations corresponding to virtual address + // range [address, address+dbytes-1]. + if AArch64.ExclusiveMonitorsPass(address, dbytes) then + // This atomic write will be rejected if it does not refer + // to the same physical locations after address translation. + Mem[address, dbytes, acctype] = data; + status = ExclusiveMonitorsStatus(); + end + X[s] = ZeroExtend(status, 32); + end + + when MemOp_LOAD + // Tell the Exclusive Monitors to record a sequence of one or more atomic + // memory reads from virtual address range [address, address+dbytes-1]. + // The Exclusive Monitor will only be set if all the reads are from the + // same dbytes-aligned physical address, to allow for the possibility of + // an atomicity break if the translation is changed between reads. + AArch64.SetExclusiveMonitors(address, dbytes); + end + + if pair then + // load exclusive pair + if rt_unknown then + X[t] = bits(datasize) UNKNOWN; + elsif elsize == 32 then + // 32-bit load exclusive pair (atomic) + data = Mem[address, dbytes, acctype]; + if BigEndian() then + X[t] = data; + X[t2] = data; + else + X[t] = data; + X[t2] = data; + else // elsize == 64 + end + // 64-bit load exclusive pair (not atomic), + // but must be 128-bit aligned + if address != Align(address, dbytes) then + iswrite = FALSE; + secondstage = FALSE; + AArch64.Abort(address, AArch64.AlignmentFault(acctype, iswrite, secondstage)); + end + X[t] = Mem[address + 0, 8, acctype]; + X[t2] = Mem[address + 8, 8, acctype]; + else + end + // load {acquire} {exclusive} single register + data = Mem[address, dbytes, acctype]; + X[t] = ZeroExtend(data, regsize); + end +@@ diff --git a/instructionAPI/ISA_ps/ldxrb b/instructionAPI/ISA_ps/ldxrb new file mode 100644 index 0000000000..a445029a70 --- /dev/null +++ b/instructionAPI/ISA_ps/ldxrb @@ -0,0 +1,94 @@ +##ldxrb_execute +bits(64) address; +bits(datasize) data; +constant integer dbytes = datasize / 8; +boolean rt_unknown = FALSE; +boolean rn_unknown = FALSE; + +if memop == MemOp_LOAD && pair && t == t2 then + case c of +end + +if memop == MemOp_STORE then + if s == t || (pair && s == t2) then + case c of + end + if s == n && n != 31 then + case c of + end + +end +if n == 31 then + address = SP[]; +elsif rn_unknown then + address = bits(64) UNKNOWN; +else + address = X[n]; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + elsif pair then + bits(datasize / 2) el1 = X[t]; + bits(datasize / 2) el2 = X[t2]; + data = if BigEndian() then el1 : el2 else el2 : el1; + else + end + data = X[t]; + end + + bit status = 1; + // Check whether the Exclusive Monitors are set to include the + // physical memory locations corresponding to virtual address + // range [address, address+dbytes-1]. + if AArch64.ExclusiveMonitorsPass(address, dbytes) then + // This atomic write will be rejected if it does not refer + // to the same physical locations after address translation. + Mem[address, dbytes, acctype] = data; + status = ExclusiveMonitorsStatus(); + end + X[s] = ZeroExtend(status, 32); + end + + when MemOp_LOAD + // Tell the Exclusive Monitors to record a sequence of one or more atomic + // memory reads from virtual address range [address, address+dbytes-1]. + // The Exclusive Monitor will only be set if all the reads are from the + // same dbytes-aligned physical address, to allow for the possibility of + // an atomicity break if the translation is changed between reads. + AArch64.SetExclusiveMonitors(address, dbytes); + end + + if pair then + // load exclusive pair + if rt_unknown then + X[t] = bits(datasize) UNKNOWN; + elsif elsize == 32 then + // 32-bit load exclusive pair (atomic) + data = Mem[address, dbytes, acctype]; + if BigEndian() then + X[t] = data; + X[t2] = data; + else + X[t] = data; + X[t2] = data; + else // elsize == 64 + end + // 64-bit load exclusive pair (not atomic), + // but must be 128-bit aligned + if address != Align(address, dbytes) then + iswrite = FALSE; + secondstage = FALSE; + AArch64.Abort(address, AArch64.AlignmentFault(acctype, iswrite, secondstage)); + end + X[t] = Mem[address + 0, 8, acctype]; + X[t2] = Mem[address + 8, 8, acctype]; + else + end + // load {acquire} {exclusive} single register + data = Mem[address, dbytes, acctype]; + X[t] = ZeroExtend(data, regsize); + end +@@ diff --git a/instructionAPI/ISA_ps/ldxrh b/instructionAPI/ISA_ps/ldxrh new file mode 100644 index 0000000000..c0286172f6 --- /dev/null +++ b/instructionAPI/ISA_ps/ldxrh @@ -0,0 +1,94 @@ +##ldxrh_execute +bits(64) address; +bits(datasize) data; +constant integer dbytes = datasize / 8; +boolean rt_unknown = FALSE; +boolean rn_unknown = FALSE; + +if memop == MemOp_LOAD && pair && t == t2 then + case c of +end + +if memop == MemOp_STORE then + if s == t || (pair && s == t2) then + case c of + end + if s == n && n != 31 then + case c of + end + +end +if n == 31 then + address = SP[]; +elsif rn_unknown then + address = bits(64) UNKNOWN; +else + address = X[n]; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + elsif pair then + bits(datasize / 2) el1 = X[t]; + bits(datasize / 2) el2 = X[t2]; + data = if BigEndian() then el1 : el2 else el2 : el1; + else + end + data = X[t]; + end + + bit status = 1; + // Check whether the Exclusive Monitors are set to include the + // physical memory locations corresponding to virtual address + // range [address, address+dbytes-1]. + if AArch64.ExclusiveMonitorsPass(address, dbytes) then + // This atomic write will be rejected if it does not refer + // to the same physical locations after address translation. + Mem[address, dbytes, acctype] = data; + status = ExclusiveMonitorsStatus(); + end + X[s] = ZeroExtend(status, 32); + end + + when MemOp_LOAD + // Tell the Exclusive Monitors to record a sequence of one or more atomic + // memory reads from virtual address range [address, address+dbytes-1]. + // The Exclusive Monitor will only be set if all the reads are from the + // same dbytes-aligned physical address, to allow for the possibility of + // an atomicity break if the translation is changed between reads. + AArch64.SetExclusiveMonitors(address, dbytes); + end + + if pair then + // load exclusive pair + if rt_unknown then + X[t] = bits(datasize) UNKNOWN; + elsif elsize == 32 then + // 32-bit load exclusive pair (atomic) + data = Mem[address, dbytes, acctype]; + if BigEndian() then + X[t] = data; + X[t2] = data; + else + X[t] = data; + X[t2] = data; + else // elsize == 64 + end + // 64-bit load exclusive pair (not atomic), + // but must be 128-bit aligned + if address != Align(address, dbytes) then + iswrite = FALSE; + secondstage = FALSE; + AArch64.Abort(address, AArch64.AlignmentFault(acctype, iswrite, secondstage)); + end + X[t] = Mem[address + 0, 8, acctype]; + X[t2] = Mem[address + 8, 8, acctype]; + else + end + // load {acquire} {exclusive} single register + data = Mem[address, dbytes, acctype]; + X[t] = ZeroExtend(data, regsize); + end +@@ diff --git a/instructionAPI/ISA_ps/lsl_lslv b/instructionAPI/ISA_ps/lsl_lslv new file mode 100644 index 0000000000..0861bec6f2 --- /dev/null +++ b/instructionAPI/ISA_ps/lsl_lslv @@ -0,0 +1,7 @@ +##lsl_lslv_execute +bits(datasize) result; +bits(datasize) operand2 = X[m]; + +result = ShiftReg(n, shift_type, UInt(operand2) MOD datasize); +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/lsl_ubfm b/instructionAPI/ISA_ps/lsl_ubfm new file mode 100644 index 0000000000..304fa48e5f --- /dev/null +++ b/instructionAPI/ISA_ps/lsl_ubfm @@ -0,0 +1,13 @@ +##lsl_ubfm_execute +bits(datasize) dst = if inzero then Zeros(64) else X[d]; +bits(datasize) src = X[n]; + +// perform bitfield move on low bits +bits(datasize) bot = (dst AND NOT(wmask)) OR (ROR(src, R) AND wmask); + +// determine extension bits (sign, zero or dest register) +bits(datasize) top = if extend then Replicate(src) else dst; + +// combine extension bits and result bits +X[d] = (top AND NOT(tmask)) OR (bot AND tmask); +@@ diff --git a/instructionAPI/ISA_ps/lslv b/instructionAPI/ISA_ps/lslv new file mode 100644 index 0000000000..966a5f7285 --- /dev/null +++ b/instructionAPI/ISA_ps/lslv @@ -0,0 +1,7 @@ +##lslv_execute +bits(datasize) result; +bits(datasize) operand2 = X[m]; + +result = ShiftReg(n, shift_type, UInt(operand2) MOD datasize); +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/lsr_lsrv b/instructionAPI/ISA_ps/lsr_lsrv new file mode 100644 index 0000000000..06d7700ebe --- /dev/null +++ b/instructionAPI/ISA_ps/lsr_lsrv @@ -0,0 +1,7 @@ +##lsr_lsrv_execute +bits(datasize) result; +bits(datasize) operand2 = X[m]; + +result = ShiftReg(n, shift_type, UInt(operand2) MOD datasize); +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/lsr_ubfm b/instructionAPI/ISA_ps/lsr_ubfm new file mode 100644 index 0000000000..2a10d7fec6 --- /dev/null +++ b/instructionAPI/ISA_ps/lsr_ubfm @@ -0,0 +1,13 @@ +##lsr_ubfm_execute +bits(datasize) dst = if inzero then Zeros(64) else X[d]; +bits(datasize) src = X[n]; + +// perform bitfield move on low bits +bits(datasize) bot = (dst AND NOT(wmask)) OR (ROR(src, R) AND wmask); + +// determine extension bits (sign, zero or dest register) +bits(datasize) top = if extend then Replicate(src) else dst; + +// combine extension bits and result bits +X[d] = (top AND NOT(tmask)) OR (bot AND tmask); +@@ diff --git a/instructionAPI/ISA_ps/lsrv b/instructionAPI/ISA_ps/lsrv new file mode 100644 index 0000000000..5d81fe1716 --- /dev/null +++ b/instructionAPI/ISA_ps/lsrv @@ -0,0 +1,7 @@ +##lsrv_execute +bits(datasize) result; +bits(datasize) operand2 = X[m]; + +result = ShiftReg(n, shift_type, UInt(operand2) MOD datasize); +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/madd b/instructionAPI/ISA_ps/madd new file mode 100644 index 0000000000..3d0737f7e5 --- /dev/null +++ b/instructionAPI/ISA_ps/madd @@ -0,0 +1,15 @@ +##madd_execute +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = X[m]; +bits(destsize) operand3 = X[a]; + +integer result; + +if sub_op then + result = UInt(operand3) - (UInt(operand1) * UInt(operand2)); +else + result = UInt(operand3) + (UInt(operand1) * UInt(operand2)); +end + +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/mla_advsimd_elt b/instructionAPI/ISA_ps/mla_advsimd_elt new file mode 100644 index 0000000000..fcba77fc9a --- /dev/null +++ b/instructionAPI/ISA_ps/mla_advsimd_elt @@ -0,0 +1,21 @@ +##mla_advsimd_elt_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(idxdsize) operand2 = V[m]; +bits(datasize) operand3 = V[d]; +bits(datasize) result; +integer element1; +integer element2; +bits(esize) product; + +element2 = UInt(Elem[operand2, index, esize]); +for e = 0 to elements-1 + element1 = UInt(Elem[operand1, e, esize]); + product = (element1 * element2); + if sub_op then + Elem[result, e, esize] = Elem[operand3, e, esize] - product; + else + Elem[result, e, esize] = Elem[operand3, e, esize] + product; + end +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/mla_advsimd_vec b/instructionAPI/ISA_ps/mla_advsimd_vec new file mode 100644 index 0000000000..f371e6257c --- /dev/null +++ b/instructionAPI/ISA_ps/mla_advsimd_vec @@ -0,0 +1,22 @@ +##mla_advsimd_vec_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) operand3 = V[d]; +bits(datasize) result; +bits(esize) element1; +bits(esize) element2; +bits(esize) product; + +for e = 0 to elements-1 + element1 = Elem[operand1, e, esize]; + element2 = Elem[operand2, e, esize]; + product = (UInt(element1) * UInt(element2)); + if sub_op then + Elem[result, e, esize] = Elem[operand3, e, esize] - product; + else + Elem[result, e, esize] = Elem[operand3, e, esize] + product; + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/mls_advsimd_elt b/instructionAPI/ISA_ps/mls_advsimd_elt new file mode 100644 index 0000000000..b0f66f0620 --- /dev/null +++ b/instructionAPI/ISA_ps/mls_advsimd_elt @@ -0,0 +1,21 @@ +##mls_advsimd_elt_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(idxdsize) operand2 = V[m]; +bits(datasize) operand3 = V[d]; +bits(datasize) result; +integer element1; +integer element2; +bits(esize) product; + +element2 = UInt(Elem[operand2, index, esize]); +for e = 0 to elements-1 + element1 = UInt(Elem[operand1, e, esize]); + product = (element1 * element2); + if sub_op then + Elem[result, e, esize] = Elem[operand3, e, esize] - product; + else + Elem[result, e, esize] = Elem[operand3, e, esize] + product; + end +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/mls_advsimd_vec b/instructionAPI/ISA_ps/mls_advsimd_vec new file mode 100644 index 0000000000..abefe505e7 --- /dev/null +++ b/instructionAPI/ISA_ps/mls_advsimd_vec @@ -0,0 +1,22 @@ +##mls_advsimd_vec_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) operand3 = V[d]; +bits(datasize) result; +bits(esize) element1; +bits(esize) element2; +bits(esize) product; + +for e = 0 to elements-1 + element1 = Elem[operand1, e, esize]; + element2 = Elem[operand2, e, esize]; + product = (UInt(element1) * UInt(element2)); + if sub_op then + Elem[result, e, esize] = Elem[operand3, e, esize] - product; + else + Elem[result, e, esize] = Elem[operand3, e, esize] + product; + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/mneg_msub b/instructionAPI/ISA_ps/mneg_msub new file mode 100644 index 0000000000..fb41829122 --- /dev/null +++ b/instructionAPI/ISA_ps/mneg_msub @@ -0,0 +1,15 @@ +##mneg_msub_execute +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = X[m]; +bits(destsize) operand3 = X[a]; + +integer result; + +if sub_op then + result = UInt(operand3) - (UInt(operand1) * UInt(operand2)); +else + result = UInt(operand3) + (UInt(operand1) * UInt(operand2)); +end + +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/mov_add_addsub_imm b/instructionAPI/ISA_ps/mov_add_addsub_imm new file mode 100644 index 0000000000..9b2d465406 --- /dev/null +++ b/instructionAPI/ISA_ps/mov_add_addsub_imm @@ -0,0 +1,26 @@ +##mov_add_addsub_imm_execute +bits(datasize) result; +bits(datasize) operand1 = if n == 31 then SP[] else X[n]; +bits(datasize) operand2 = imm; +bits(4) nzcv; +bit carry_in; + +if sub_op then + operand2 = NOT(operand2); + carry_in = 1; +else + carry_in = 0; +end + +(result, nzcv) = AddWithCarry(operand1, operand2, carry_in); + +if setflags then + PSTATE. = nzcv; +end + +if d == 31 && !setflags then + SP[] = result; +else + X[d] = result; +end +@@ diff --git a/instructionAPI/ISA_ps/mov_dup_advsimd_elt b/instructionAPI/ISA_ps/mov_dup_advsimd_elt new file mode 100644 index 0000000000..061189ebc8 --- /dev/null +++ b/instructionAPI/ISA_ps/mov_dup_advsimd_elt @@ -0,0 +1,11 @@ +##mov_dup_advsimd_elt_execute +CheckFPAdvSIMDEnabled64(); +bits(idxdsize) operand = V[n]; +bits(datasize) result; +bits(esize) element; + +element = Elem[operand, index, esize]; +for e = 0 to elements-1 + Elem[result, e, esize] = element; +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/mov_ins_advsimd_elt b/instructionAPI/ISA_ps/mov_ins_advsimd_elt new file mode 100644 index 0000000000..544a300431 --- /dev/null +++ b/instructionAPI/ISA_ps/mov_ins_advsimd_elt @@ -0,0 +1,9 @@ +##mov_ins_advsimd_elt_execute +CheckFPAdvSIMDEnabled64(); +bits(idxdsize) operand = V[n]; +bits(128) result; + +result = V[d]; +Elem[result, dst_index, esize] = Elem[operand, src_index, esize]; +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/mov_ins_advsimd_gen b/instructionAPI/ISA_ps/mov_ins_advsimd_gen new file mode 100644 index 0000000000..913107717b --- /dev/null +++ b/instructionAPI/ISA_ps/mov_ins_advsimd_gen @@ -0,0 +1,9 @@ +##mov_ins_advsimd_gen_execute +CheckFPAdvSIMDEnabled64(); +bits(esize) element = X[n]; +bits(datasize) result; + +result = V[d]; +Elem[result, index, esize] = element; +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/mov_movn b/instructionAPI/ISA_ps/mov_movn new file mode 100644 index 0000000000..f06a1473fa --- /dev/null +++ b/instructionAPI/ISA_ps/mov_movn @@ -0,0 +1,15 @@ +##mov_movn_execute +bits(datasize) result; + +if opcode == MoveWideOp_K then + result = X[d]; +else + result = Zeros(64); +end + +result = imm; +if opcode == MoveWideOp_N then + result = NOT(result); +end +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/mov_movz b/instructionAPI/ISA_ps/mov_movz new file mode 100644 index 0000000000..206a9fa61e --- /dev/null +++ b/instructionAPI/ISA_ps/mov_movz @@ -0,0 +1,15 @@ +##mov_movz_execute +bits(datasize) result; + +if opcode == MoveWideOp_K then + result = X[d]; +else + result = Zeros(64); +end + +result = imm; +if opcode == MoveWideOp_N then + result = NOT(result); +end +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/mov_orr_advsimd_reg b/instructionAPI/ISA_ps/mov_orr_advsimd_reg new file mode 100644 index 0000000000..a529626b3c --- /dev/null +++ b/instructionAPI/ISA_ps/mov_orr_advsimd_reg @@ -0,0 +1,18 @@ +##mov_orr_advsimd_reg_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; + +if invert then operand2 = NOT(operand2); + +case op of + when LogicalOp_AND + result = operand1 AND operand2; + end + when LogicalOp_ORR + result = operand1 OR operand2; + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/mov_orr_log_imm b/instructionAPI/ISA_ps/mov_orr_log_imm new file mode 100644 index 0000000000..0b1055cbe7 --- /dev/null +++ b/instructionAPI/ISA_ps/mov_orr_log_imm @@ -0,0 +1,23 @@ +##mov_orr_log_imm_execute +bits(datasize) result; +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = imm; + +case op of + when LogicalOp_AND result = operand1 AND operand2; + end + when LogicalOp_ORR result = operand1 OR operand2; + end + when LogicalOp_EOR result = operand1 EOR operand2; + end + +if setflags then + PSTATE. = result:IsZeroBit(result):00; +end + +if d == 31 && !setflags then + SP[] = result; +else + X[d] = result; +end +@@ diff --git a/instructionAPI/ISA_ps/mov_orr_log_shift b/instructionAPI/ISA_ps/mov_orr_log_shift new file mode 100644 index 0000000000..48e04a0c4b --- /dev/null +++ b/instructionAPI/ISA_ps/mov_orr_log_shift @@ -0,0 +1,20 @@ +##mov_orr_log_shift_execute +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount); + +if invert then operand2 = NOT(operand2) end; + +case op of + when LogicalOp_AND result = operand1 AND operand2; + end + when LogicalOp_ORR result = operand1 OR operand2; + end + when LogicalOp_EOR result = operand1 EOR operand2; + end + +if setflags then + PSTATE. = result:IsZeroBit(result):00; +end + +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/mov_umov_advsimd b/instructionAPI/ISA_ps/mov_umov_advsimd new file mode 100644 index 0000000000..238f8fb039 --- /dev/null +++ b/instructionAPI/ISA_ps/mov_umov_advsimd @@ -0,0 +1,6 @@ +##mov_umov_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(idxdsize) operand = V[n]; + +X[d] = ZeroExtend(Elem[operand, index, esize], datasize); +@@ diff --git a/instructionAPI/ISA_ps/movi_advsimd b/instructionAPI/ISA_ps/movi_advsimd new file mode 100644 index 0000000000..4562c9c4a7 --- /dev/null +++ b/instructionAPI/ISA_ps/movi_advsimd @@ -0,0 +1,23 @@ +##movi_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand; +bits(datasize) result; + +case operation of + when ImmediateOp_MOVI + result = imm; + end + when ImmediateOp_MVNI + result = NOT(imm); + end + when ImmediateOp_ORR + operand = V[rd]; + result = operand OR imm; + end + when ImmediateOp_BIC + operand = V[rd]; + result = operand AND NOT(imm); + end + +V[rd] = result; +@@ diff --git a/instructionAPI/ISA_ps/movk b/instructionAPI/ISA_ps/movk new file mode 100644 index 0000000000..56698900d5 --- /dev/null +++ b/instructionAPI/ISA_ps/movk @@ -0,0 +1,15 @@ +##movk_execute +bits(datasize) result; + +if opcode == MoveWideOp_K then + result = X[d]; +else + result = Zeros(64); +end + +result = imm; +if opcode == MoveWideOp_N then + result = NOT(result); +end +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/movn b/instructionAPI/ISA_ps/movn new file mode 100644 index 0000000000..4a70d12505 --- /dev/null +++ b/instructionAPI/ISA_ps/movn @@ -0,0 +1,15 @@ +##movn_execute +bits(datasize) result; + +if opcode == MoveWideOp_K then + result = X[d]; +else + result = Zeros(64); +end + +result = imm; +if opcode == MoveWideOp_N then + result = NOT(result); +end +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/movz b/instructionAPI/ISA_ps/movz new file mode 100644 index 0000000000..fe511ed05f --- /dev/null +++ b/instructionAPI/ISA_ps/movz @@ -0,0 +1,15 @@ +##movz_execute +bits(datasize) result; + +if opcode == MoveWideOp_K then + result = X[d]; +else + result = Zeros(64); +end + +result = imm; +if opcode == MoveWideOp_N then + result = NOT(result); +end +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/mrs b/instructionAPI/ISA_ps/mrs new file mode 100644 index 0000000000..96e4d50eea --- /dev/null +++ b/instructionAPI/ISA_ps/mrs @@ -0,0 +1,7 @@ +##mrs_execute +if read then + X[t] = System_Get(sys_op0, sys_op1, sys_crn, sys_crm, sys_op2); +else + System_Put(sys_op0, sys_op1, sys_crn, sys_crm, sys_op2, X[t]); +end +@@ diff --git a/instructionAPI/ISA_ps/msr_imm b/instructionAPI/ISA_ps/msr_imm new file mode 100644 index 0000000000..d573f17114 --- /dev/null +++ b/instructionAPI/ISA_ps/msr_imm @@ -0,0 +1,18 @@ +##msr_imm_execute +case field of + when PSTATEField_SP + PSTATE.SP = operand<0>; + end + when PSTATEField_DAIFSet + PSTATE.D = PSTATE.D OR operand<3>; + PSTATE.A = PSTATE.A OR operand<2>; + PSTATE.I = PSTATE.I OR operand<1>; + PSTATE.F = PSTATE.F OR operand<0>; + end + when PSTATEField_DAIFClr + PSTATE.D = PSTATE.D AND NOT(operand<3>); + PSTATE.A = PSTATE.A AND NOT(operand<2>); + PSTATE.I = PSTATE.I AND NOT(operand<1>); + PSTATE.F = PSTATE.F AND NOT(operand<0>); + end +@@ diff --git a/instructionAPI/ISA_ps/msr_reg b/instructionAPI/ISA_ps/msr_reg new file mode 100644 index 0000000000..c6782a6221 --- /dev/null +++ b/instructionAPI/ISA_ps/msr_reg @@ -0,0 +1,7 @@ +##msr_reg_execute +if read then + X[t] = System_Get(sys_op0, sys_op1, sys_crn, sys_crm, sys_op2); +else + System_Put(sys_op0, sys_op1, sys_crn, sys_crm, sys_op2, X[t]); +end +@@ diff --git a/instructionAPI/ISA_ps/msub b/instructionAPI/ISA_ps/msub new file mode 100644 index 0000000000..22c31e9eca --- /dev/null +++ b/instructionAPI/ISA_ps/msub @@ -0,0 +1,15 @@ +##msub_execute +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = X[m]; +bits(destsize) operand3 = X[a]; + +integer result; + +if sub_op then + result = UInt(operand3) - (UInt(operand1) * UInt(operand2)); +else + result = UInt(operand3) + (UInt(operand1) * UInt(operand2)); +end + +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/mul_advsimd_elt b/instructionAPI/ISA_ps/mul_advsimd_elt new file mode 100644 index 0000000000..c44d3622c4 --- /dev/null +++ b/instructionAPI/ISA_ps/mul_advsimd_elt @@ -0,0 +1,17 @@ +##mul_advsimd_elt_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(idxdsize) operand2 = V[m]; +bits(datasize) result; +integer element1; +integer element2; +bits(esize) product; + +element2 = UInt(Elem[operand2, index, esize]); +for e = 0 to elements-1 + element1 = UInt(Elem[operand1, e, esize]); + product = (element1 * element2); + Elem[result, e, esize] = product; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/mul_advsimd_vec b/instructionAPI/ISA_ps/mul_advsimd_vec new file mode 100644 index 0000000000..56c2c59ee1 --- /dev/null +++ b/instructionAPI/ISA_ps/mul_advsimd_vec @@ -0,0 +1,21 @@ +##mul_advsimd_vec_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +bits(esize) element1; +bits(esize) element2; +bits(esize) product; + +for e = 0 to elements-1 + element1 = Elem[operand1, e, esize]; + element2 = Elem[operand2, e, esize]; + if poly then + product = PolynomialMult(element1, element2); + else + product = (UInt(element1) * UInt(element2)); + end + Elem[result, e, esize] = product; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/mul_madd b/instructionAPI/ISA_ps/mul_madd new file mode 100644 index 0000000000..ebd33fe4c5 --- /dev/null +++ b/instructionAPI/ISA_ps/mul_madd @@ -0,0 +1,15 @@ +##mul_madd_execute +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = X[m]; +bits(destsize) operand3 = X[a]; + +integer result; + +if sub_op then + result = UInt(operand3) - (UInt(operand1) * UInt(operand2)); +else + result = UInt(operand3) + (UInt(operand1) * UInt(operand2)); +end + +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/mvn_not_advsimd b/instructionAPI/ISA_ps/mvn_not_advsimd new file mode 100644 index 0000000000..eaa0820dee --- /dev/null +++ b/instructionAPI/ISA_ps/mvn_not_advsimd @@ -0,0 +1,12 @@ +##mvn_not_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +bits(esize) element; + +for e = 0 to elements-1 + element = Elem[operand, e, esize]; + Elem[result, e, esize] = NOT(element); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/mvn_orn_log_shift b/instructionAPI/ISA_ps/mvn_orn_log_shift new file mode 100644 index 0000000000..09013651f7 --- /dev/null +++ b/instructionAPI/ISA_ps/mvn_orn_log_shift @@ -0,0 +1,20 @@ +##mvn_orn_log_shift_execute +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount); + +if invert then operand2 = NOT(operand2) end; + +case op of + when LogicalOp_AND result = operand1 AND operand2; + end + when LogicalOp_ORR result = operand1 OR operand2; + end + when LogicalOp_EOR result = operand1 EOR operand2; + end + +if setflags then + PSTATE. = result:IsZeroBit(result):00; +end + +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/mvni_advsimd b/instructionAPI/ISA_ps/mvni_advsimd new file mode 100644 index 0000000000..5613c2a14e --- /dev/null +++ b/instructionAPI/ISA_ps/mvni_advsimd @@ -0,0 +1,23 @@ +##mvni_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand; +bits(datasize) result; + +case operation of + when ImmediateOp_MOVI + result = imm; + end + when ImmediateOp_MVNI + result = NOT(imm); + end + when ImmediateOp_ORR + operand = V[rd]; + result = operand OR imm; + end + when ImmediateOp_BIC + operand = V[rd]; + result = operand AND NOT(imm); + end + +V[rd] = result; +@@ diff --git a/instructionAPI/ISA_ps/neg_advsimd b/instructionAPI/ISA_ps/neg_advsimd new file mode 100644 index 0000000000..a1b35e92f9 --- /dev/null +++ b/instructionAPI/ISA_ps/neg_advsimd @@ -0,0 +1,17 @@ +##neg_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +integer element; + +for e = 0 to elements-1 + element = SInt(Elem[operand, e, esize]); + if neg then + element = -element; + else + element = Abs(element); + end + Elem[result, e, esize] = element; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/neg_sub_addsub_shift b/instructionAPI/ISA_ps/neg_sub_addsub_shift new file mode 100644 index 0000000000..82b83340fa --- /dev/null +++ b/instructionAPI/ISA_ps/neg_sub_addsub_shift @@ -0,0 +1,22 @@ +##neg_sub_addsub_shift_execute +bits(datasize) result; +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount); +bits(4) nzcv; +bit carry_in; + +if sub_op then + operand2 = NOT(operand2); + carry_in = 1; +else + carry_in = 0; +end + +(result, nzcv) = AddWithCarry(operand1, operand2, carry_in); + +if setflags then + PSTATE. = nzcv; +end + +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/negs_subs_addsub_shift b/instructionAPI/ISA_ps/negs_subs_addsub_shift new file mode 100644 index 0000000000..43503b7990 --- /dev/null +++ b/instructionAPI/ISA_ps/negs_subs_addsub_shift @@ -0,0 +1,22 @@ +##negs_subs_addsub_shift_execute +bits(datasize) result; +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount); +bits(4) nzcv; +bit carry_in; + +if sub_op then + operand2 = NOT(operand2); + carry_in = 1; +else + carry_in = 0; +end + +(result, nzcv) = AddWithCarry(operand1, operand2, carry_in); + +if setflags then + PSTATE. = nzcv; +end + +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/ngc_sbc b/instructionAPI/ISA_ps/ngc_sbc new file mode 100644 index 0000000000..69b9254bee --- /dev/null +++ b/instructionAPI/ISA_ps/ngc_sbc @@ -0,0 +1,18 @@ +##ngc_sbc_execute +bits(datasize) result; +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = X[m]; +bits(4) nzcv; + +if sub_op then + operand2 = NOT(operand2); +end + +(result, nzcv) = AddWithCarry(operand1, operand2, PSTATE.C); + +if setflags then + PSTATE. = nzcv; +end + +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/ngcs_sbcs b/instructionAPI/ISA_ps/ngcs_sbcs new file mode 100644 index 0000000000..b7bf668aac --- /dev/null +++ b/instructionAPI/ISA_ps/ngcs_sbcs @@ -0,0 +1,18 @@ +##ngcs_sbcs_execute +bits(datasize) result; +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = X[m]; +bits(4) nzcv; + +if sub_op then + operand2 = NOT(operand2); +end + +(result, nzcv) = AddWithCarry(operand1, operand2, PSTATE.C); + +if setflags then + PSTATE. = nzcv; +end + +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/nop_hint b/instructionAPI/ISA_ps/nop_hint new file mode 100644 index 0000000000..6dbbcab220 --- /dev/null +++ b/instructionAPI/ISA_ps/nop_hint @@ -0,0 +1,48 @@ +##nop_hint_execute +case op of + when SystemHintOp_YIELD + Hint_Yield(); + end + + when SystemHintOp_WFE + if EventRegistered() then + ClearEventRegister(); + else + if PSTATE.EL == EL0 then + AArch64.CheckForWFxTrap(EL1, TRUE); + end + if HaveEL(EL2) && !IsSecure() && PSTATE.EL IN {EL0,EL1} then + AArch64.CheckForWFxTrap(EL2, TRUE); + end + if HaveEL(EL3) && PSTATE.EL != EL3 then + AArch64.CheckForWFxTrap(EL3, TRUE); + end + WaitForEvent(); + end + + end + when SystemHintOp_WFI + if !InterruptPending() then + if PSTATE.EL == EL0 then + AArch64.CheckForWFxTrap(EL1, FALSE); + end + if HaveEL(EL2) && !IsSecure() && PSTATE.EL IN {EL0,EL1} then + AArch64.CheckForWFxTrap(EL2, FALSE); + end + if HaveEL(EL3) && PSTATE.EL != EL3 then + AArch64.CheckForWFxTrap(EL3, FALSE); + end + WaitForInterrupt(); + end + + end + when SystemHintOp_SEV + SendEvent(); + end + + when SystemHintOp_SEVL + EventRegisterSet(); + end + + otherwise // do nothing +@@ diff --git a/instructionAPI/ISA_ps/not_advsimd b/instructionAPI/ISA_ps/not_advsimd new file mode 100644 index 0000000000..e076d833bc --- /dev/null +++ b/instructionAPI/ISA_ps/not_advsimd @@ -0,0 +1,12 @@ +##not_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +bits(esize) element; + +for e = 0 to elements-1 + element = Elem[operand, e, esize]; + Elem[result, e, esize] = NOT(element); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/orn_advsimd b/instructionAPI/ISA_ps/orn_advsimd new file mode 100644 index 0000000000..60dcfa3477 --- /dev/null +++ b/instructionAPI/ISA_ps/orn_advsimd @@ -0,0 +1,18 @@ +##orn_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; + +if invert then operand2 = NOT(operand2); + +case op of + when LogicalOp_AND + result = operand1 AND operand2; + end + when LogicalOp_ORR + result = operand1 OR operand2; + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/orn_log_shift b/instructionAPI/ISA_ps/orn_log_shift new file mode 100644 index 0000000000..7da3ad787f --- /dev/null +++ b/instructionAPI/ISA_ps/orn_log_shift @@ -0,0 +1,20 @@ +##orn_log_shift_execute +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount); + +if invert then operand2 = NOT(operand2) end; + +case op of + when LogicalOp_AND result = operand1 AND operand2; + end + when LogicalOp_ORR result = operand1 OR operand2; + end + when LogicalOp_EOR result = operand1 EOR operand2; + end + +if setflags then + PSTATE. = result:IsZeroBit(result):00; +end + +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/orr_advsimd_imm b/instructionAPI/ISA_ps/orr_advsimd_imm new file mode 100644 index 0000000000..2669b73340 --- /dev/null +++ b/instructionAPI/ISA_ps/orr_advsimd_imm @@ -0,0 +1,23 @@ +##orr_advsimd_imm_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand; +bits(datasize) result; + +case operation of + when ImmediateOp_MOVI + result = imm; + end + when ImmediateOp_MVNI + result = NOT(imm); + end + when ImmediateOp_ORR + operand = V[rd]; + result = operand OR imm; + end + when ImmediateOp_BIC + operand = V[rd]; + result = operand AND NOT(imm); + end + +V[rd] = result; +@@ diff --git a/instructionAPI/ISA_ps/orr_advsimd_reg b/instructionAPI/ISA_ps/orr_advsimd_reg new file mode 100644 index 0000000000..bc437c8c1a --- /dev/null +++ b/instructionAPI/ISA_ps/orr_advsimd_reg @@ -0,0 +1,18 @@ +##orr_advsimd_reg_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; + +if invert then operand2 = NOT(operand2); + +case op of + when LogicalOp_AND + result = operand1 AND operand2; + end + when LogicalOp_ORR + result = operand1 OR operand2; + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/orr_log_imm b/instructionAPI/ISA_ps/orr_log_imm new file mode 100644 index 0000000000..f498bd1aef --- /dev/null +++ b/instructionAPI/ISA_ps/orr_log_imm @@ -0,0 +1,23 @@ +##orr_log_imm_execute +bits(datasize) result; +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = imm; + +case op of + when LogicalOp_AND result = operand1 AND operand2; + end + when LogicalOp_ORR result = operand1 OR operand2; + end + when LogicalOp_EOR result = operand1 EOR operand2; + end + +if setflags then + PSTATE. = result:IsZeroBit(result):00; +end + +if d == 31 && !setflags then + SP[] = result; +else + X[d] = result; +end +@@ diff --git a/instructionAPI/ISA_ps/orr_log_shift b/instructionAPI/ISA_ps/orr_log_shift new file mode 100644 index 0000000000..0d5b3a3a80 --- /dev/null +++ b/instructionAPI/ISA_ps/orr_log_shift @@ -0,0 +1,20 @@ +##orr_log_shift_execute +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount); + +if invert then operand2 = NOT(operand2) end; + +case op of + when LogicalOp_AND result = operand1 AND operand2; + end + when LogicalOp_ORR result = operand1 OR operand2; + end + when LogicalOp_EOR result = operand1 EOR operand2; + end + +if setflags then + PSTATE. = result:IsZeroBit(result):00; +end + +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/permindex b/instructionAPI/ISA_ps/permindex new file mode 100644 index 0000000000..e69de29bb2 diff --git a/instructionAPI/ISA_ps/pmul_advsimd b/instructionAPI/ISA_ps/pmul_advsimd new file mode 100644 index 0000000000..f328bc2d19 --- /dev/null +++ b/instructionAPI/ISA_ps/pmul_advsimd @@ -0,0 +1,21 @@ +##pmul_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +bits(esize) element1; +bits(esize) element2; +bits(esize) product; + +for e = 0 to elements-1 + element1 = Elem[operand1, e, esize]; + element2 = Elem[operand2, e, esize]; + if poly then + product = PolynomialMult(element1, element2); + else + product = (UInt(element1) * UInt(element2)); + end + Elem[result, e, esize] = product; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/pmull_advsimd b/instructionAPI/ISA_ps/pmull_advsimd new file mode 100644 index 0000000000..3630836445 --- /dev/null +++ b/instructionAPI/ISA_ps/pmull_advsimd @@ -0,0 +1,15 @@ +##pmull_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = Vpart[n, part]; +bits(datasize) operand2 = Vpart[m, part]; +bits(2*datasize) result; +bits(esize) element1; +bits(esize) element2; + +for e = 0 to elements-1 + element1 = Elem[operand1, e, esize]; + element2 = Elem[operand2, e, esize]; + Elem[result, e, 2*esize] = PolynomialMult(element1, element2); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/prfm_imm b/instructionAPI/ISA_ps/prfm_imm new file mode 100644 index 0000000000..a3892e6b37 --- /dev/null +++ b/instructionAPI/ISA_ps/prfm_imm @@ -0,0 +1,60 @@ +##prfm_imm_execute +bits(64) address; +bits(datasize) data; +boolean wb_unknown = FALSE; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && wback && n == t && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && n == t && n != 31 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + else + data = X[t]; + end + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + if signed then + X[t] = SignExtend(data, regsize); + else + X[t] = ZeroExtend(data, regsize); + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/prfm_lit b/instructionAPI/ISA_ps/prfm_lit new file mode 100644 index 0000000000..eab0ae0547 --- /dev/null +++ b/instructionAPI/ISA_ps/prfm_lit @@ -0,0 +1,18 @@ +##prfm_lit_execute +bits(64) address = PC[] + offset; +bits(size*8) data; + +case memop of + when MemOp_LOAD + data = Mem[address, size, AccType_NORMAL]; + if signed then + X[t] = SignExtend(data, 64); + else + X[t] = data; + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end +@@ diff --git a/instructionAPI/ISA_ps/prfm_reg b/instructionAPI/ISA_ps/prfm_reg new file mode 100644 index 0000000000..12f7e72896 --- /dev/null +++ b/instructionAPI/ISA_ps/prfm_reg @@ -0,0 +1,61 @@ +##prfm_reg_execute +bits(64) offset = ExtendReg(m, extend_type, shift); +bits(64) address; +bits(datasize) data; +boolean wb_unknown = FALSE; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && wback && n == t && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && n == t && n != 31 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + else + data = X[t]; + end + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + if signed then + X[t] = SignExtend(data, regsize); + else + X[t] = ZeroExtend(data, regsize); + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/prfum b/instructionAPI/ISA_ps/prfum new file mode 100644 index 0000000000..400caa11c7 --- /dev/null +++ b/instructionAPI/ISA_ps/prfum @@ -0,0 +1,60 @@ +##prfum_execute +bits(64) address; +bits(datasize) data; +boolean wb_unknown = FALSE; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && wback && n == t && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && n == t && n != 31 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + else + data = X[t]; + end + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + if signed then + X[t] = SignExtend(data, regsize); + else + X[t] = ZeroExtend(data, regsize); + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/raddhn_advsimd b/instructionAPI/ISA_ps/raddhn_advsimd new file mode 100644 index 0000000000..487659daf2 --- /dev/null +++ b/instructionAPI/ISA_ps/raddhn_advsimd @@ -0,0 +1,23 @@ +##raddhn_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(2*datasize) operand1 = V[n]; +bits(2*datasize) operand2 = V[m]; +bits(datasize) result; +integer round_const = if round then 1 << (esize - 1) else 0; +bits(2*esize) element1; +bits(2*esize) element2; +bits(2*esize) sum; + +for e = 0 to elements-1 + element1 = Elem[operand1, e, 2*esize]; + element2 = Elem[operand2, e, 2*esize]; + if sub_op then + sum = element1 - element2; + else + sum = element1 + element2; + end + sum = sum + round_const; + Elem[result, e, esize] = sum<2*esize-1:esize>; + +Vpart[d, part] = result; +@@ diff --git a/instructionAPI/ISA_ps/rbit_advsimd b/instructionAPI/ISA_ps/rbit_advsimd new file mode 100644 index 0000000000..99ccf0321a --- /dev/null +++ b/instructionAPI/ISA_ps/rbit_advsimd @@ -0,0 +1,15 @@ +##rbit_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +bits(esize) element; +bits(esize) rev; + +for e = 0 to elements-1 + element = Elem[operand, e, esize]; + for i = 0 to esize-1 + rev = element; + Elem[result, e, esize] = rev; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/rbit_int b/instructionAPI/ISA_ps/rbit_int new file mode 100644 index 0000000000..b5c30dbe84 --- /dev/null +++ b/instructionAPI/ISA_ps/rbit_int @@ -0,0 +1,28 @@ +##rbit_int_execute +bits(datasize) result; +bits(6) V; +integer vbit; + +case op of + when RevOp_REV16 V = 001000; + end + when RevOp_REV32 V = 011000; + end + when RevOp_REV64 V = 111000; + when RevOp_RBIT V = if datasize == 64 then 111111 else 011111; + + end +result = X[n]; +for vbit = 0 to 5 + // Swap pairs of 2^vbit bits in result + if V == 1 then + bits(datasize) tmp = result; + integer vsize = 1 << vbit; + integer base = 0; + while base < datasize do + result = tmp; + result = tmp; + base = base + (2 * vsize); + end +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/ret b/instructionAPI/ISA_ps/ret new file mode 100644 index 0000000000..401831bd79 --- /dev/null +++ b/instructionAPI/ISA_ps/ret @@ -0,0 +1,6 @@ +##ret_execute +bits(64) target = X[n]; + +if branch_type == BranchType_CALL then X[30] = PC[] + 4; +BranchTo(target, branch_type); +@@ diff --git a/instructionAPI/ISA_ps/rev b/instructionAPI/ISA_ps/rev new file mode 100644 index 0000000000..3eac0c72f1 --- /dev/null +++ b/instructionAPI/ISA_ps/rev @@ -0,0 +1,28 @@ +##rev_execute +bits(datasize) result; +bits(6) V; +integer vbit; + +case op of + when RevOp_REV16 V = 001000; + end + when RevOp_REV32 V = 011000; + end + when RevOp_REV64 V = 111000; + when RevOp_RBIT V = if datasize == 64 then 111111 else 011111; + + end +result = X[n]; +for vbit = 0 to 5 + // Swap pairs of 2^vbit bits in result + if V == 1 then + bits(datasize) tmp = result; + integer vsize = 1 << vbit; + integer base = 0; + while base < datasize do + result = tmp; + result = tmp; + base = base + (2 * vsize); + end +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/rev16_advsimd b/instructionAPI/ISA_ps/rev16_advsimd new file mode 100644 index 0000000000..d5aea33346 --- /dev/null +++ b/instructionAPI/ISA_ps/rev16_advsimd @@ -0,0 +1,11 @@ +##rev16_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +integer e_rev; +for e = 0 to elements-1 + e_rev = UInt(e<3:0> EOR revmask); + Elem[result, e_rev, esize] = Elem[operand, e, esize]; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/rev16_int b/instructionAPI/ISA_ps/rev16_int new file mode 100644 index 0000000000..47c87e12ba --- /dev/null +++ b/instructionAPI/ISA_ps/rev16_int @@ -0,0 +1,28 @@ +##rev16_int_execute +bits(datasize) result; +bits(6) V; +integer vbit; + +case op of + when RevOp_REV16 V = 001000; + end + when RevOp_REV32 V = 011000; + end + when RevOp_REV64 V = 111000; + when RevOp_RBIT V = if datasize == 64 then 111111 else 011111; + + end +result = X[n]; +for vbit = 0 to 5 + // Swap pairs of 2^vbit bits in result + if V == 1 then + bits(datasize) tmp = result; + integer vsize = 1 << vbit; + integer base = 0; + while base < datasize do + result = tmp; + result = tmp; + base = base + (2 * vsize); + end +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/rev32_advsimd b/instructionAPI/ISA_ps/rev32_advsimd new file mode 100644 index 0000000000..6bc72a6e56 --- /dev/null +++ b/instructionAPI/ISA_ps/rev32_advsimd @@ -0,0 +1,11 @@ +##rev32_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +integer e_rev; +for e = 0 to elements-1 + e_rev = UInt(e<3:0> EOR revmask); + Elem[result, e_rev, esize] = Elem[operand, e, esize]; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/rev32_int b/instructionAPI/ISA_ps/rev32_int new file mode 100644 index 0000000000..4752910d39 --- /dev/null +++ b/instructionAPI/ISA_ps/rev32_int @@ -0,0 +1,28 @@ +##rev32_int_execute +bits(datasize) result; +bits(6) V; +integer vbit; + +case op of + when RevOp_REV16 V = 001000; + end + when RevOp_REV32 V = 011000; + end + when RevOp_REV64 V = 111000; + when RevOp_RBIT V = if datasize == 64 then 111111 else 011111; + + end +result = X[n]; +for vbit = 0 to 5 + // Swap pairs of 2^vbit bits in result + if V == 1 then + bits(datasize) tmp = result; + integer vsize = 1 << vbit; + integer base = 0; + while base < datasize do + result = tmp; + result = tmp; + base = base + (2 * vsize); + end +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/rev64_advsimd b/instructionAPI/ISA_ps/rev64_advsimd new file mode 100644 index 0000000000..5e7c3b7d85 --- /dev/null +++ b/instructionAPI/ISA_ps/rev64_advsimd @@ -0,0 +1,11 @@ +##rev64_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +integer e_rev; +for e = 0 to elements-1 + e_rev = UInt(e<3:0> EOR revmask); + Elem[result, e_rev, esize] = Elem[operand, e, esize]; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/ror_extr b/instructionAPI/ISA_ps/ror_extr new file mode 100644 index 0000000000..7a04641639 --- /dev/null +++ b/instructionAPI/ISA_ps/ror_extr @@ -0,0 +1,10 @@ +##ror_extr_execute +bits(datasize) result; +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = X[m]; +bits(2*datasize) concat = operand1:operand2; + +result = concat; + +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/ror_rorv b/instructionAPI/ISA_ps/ror_rorv new file mode 100644 index 0000000000..3a3763b1ec --- /dev/null +++ b/instructionAPI/ISA_ps/ror_rorv @@ -0,0 +1,7 @@ +##ror_rorv_execute +bits(datasize) result; +bits(datasize) operand2 = X[m]; + +result = ShiftReg(n, shift_type, UInt(operand2) MOD datasize); +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/rorv b/instructionAPI/ISA_ps/rorv new file mode 100644 index 0000000000..2f5f174419 --- /dev/null +++ b/instructionAPI/ISA_ps/rorv @@ -0,0 +1,7 @@ +##rorv_execute +bits(datasize) result; +bits(datasize) operand2 = X[m]; + +result = ShiftReg(n, shift_type, UInt(operand2) MOD datasize); +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/rshrn_advsimd b/instructionAPI/ISA_ps/rshrn_advsimd new file mode 100644 index 0000000000..de4e6d1ee0 --- /dev/null +++ b/instructionAPI/ISA_ps/rshrn_advsimd @@ -0,0 +1,13 @@ +##rshrn_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize*2) operand = V[n]; +bits(datasize) result; +integer round_const = if round then (1 << (shift - 1)) else 0; +integer element; + +for e = 0 to elements-1 + element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift; + Elem[result, e, esize] = element; + +Vpart[d, part] = result; +@@ diff --git a/instructionAPI/ISA_ps/rsubhn_advsimd b/instructionAPI/ISA_ps/rsubhn_advsimd new file mode 100644 index 0000000000..e966083e10 --- /dev/null +++ b/instructionAPI/ISA_ps/rsubhn_advsimd @@ -0,0 +1,23 @@ +##rsubhn_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(2*datasize) operand1 = V[n]; +bits(2*datasize) operand2 = V[m]; +bits(datasize) result; +integer round_const = if round then 1 << (esize - 1) else 0; +bits(2*esize) element1; +bits(2*esize) element2; +bits(2*esize) sum; + +for e = 0 to elements-1 + element1 = Elem[operand1, e, 2*esize]; + element2 = Elem[operand2, e, 2*esize]; + if sub_op then + sum = element1 - element2; + else + sum = element1 + element2; + end + sum = sum + round_const; + Elem[result, e, esize] = sum<2*esize-1:esize>; + +Vpart[d, part] = result; +@@ diff --git a/instructionAPI/ISA_ps/saba_advsimd b/instructionAPI/ISA_ps/saba_advsimd new file mode 100644 index 0000000000..ae7f136983 --- /dev/null +++ b/instructionAPI/ISA_ps/saba_advsimd @@ -0,0 +1,17 @@ +##saba_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +integer element1; +integer element2; +bits(esize) absdiff; + +result = if accumulate then V[d] else Zeros(64); +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + absdiff = Abs(element1 - element2); + Elem[result, e, esize] = Elem[result, e, esize] + absdiff; +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sabal_advsimd b/instructionAPI/ISA_ps/sabal_advsimd new file mode 100644 index 0000000000..06aaaa3ecc --- /dev/null +++ b/instructionAPI/ISA_ps/sabal_advsimd @@ -0,0 +1,17 @@ +##sabal_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = Vpart[n, part]; +bits(datasize) operand2 = Vpart[m, part]; +bits(2*datasize) result; +integer element1; +integer element2; +bits(2*esize) absdiff; + +result = if accumulate then V[d] else Zeros(64); +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + absdiff = Abs(element1 - element2)<2*esize-1:0>; + Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff; +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sabd_advsimd b/instructionAPI/ISA_ps/sabd_advsimd new file mode 100644 index 0000000000..58e1836a26 --- /dev/null +++ b/instructionAPI/ISA_ps/sabd_advsimd @@ -0,0 +1,17 @@ +##sabd_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +integer element1; +integer element2; +bits(esize) absdiff; + +result = if accumulate then V[d] else Zeros(64); +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + absdiff = Abs(element1 - element2); + Elem[result, e, esize] = Elem[result, e, esize] + absdiff; +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sabdl_advsimd b/instructionAPI/ISA_ps/sabdl_advsimd new file mode 100644 index 0000000000..f06e890e36 --- /dev/null +++ b/instructionAPI/ISA_ps/sabdl_advsimd @@ -0,0 +1,17 @@ +##sabdl_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = Vpart[n, part]; +bits(datasize) operand2 = Vpart[m, part]; +bits(2*datasize) result; +integer element1; +integer element2; +bits(2*esize) absdiff; + +result = if accumulate then V[d] else Zeros(64); +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + absdiff = Abs(element1 - element2)<2*esize-1:0>; + Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff; +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sadalp_advsimd b/instructionAPI/ISA_ps/sadalp_advsimd new file mode 100644 index 0000000000..f8c81458ce --- /dev/null +++ b/instructionAPI/ISA_ps/sadalp_advsimd @@ -0,0 +1,18 @@ +##sadalp_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; + +bits(2*esize) sum; +integer op1; +integer op2; + +result = if acc then V[d] else Zeros(64); +for e = 0 to elements-1 + op1 = Int(Elem[operand, 2*e+0, esize], unsigned); + op2 = Int(Elem[operand, 2*e+1, esize], unsigned); + sum = (op1 + op2)<2*esize-1:0>; + Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/saddl_advsimd b/instructionAPI/ISA_ps/saddl_advsimd new file mode 100644 index 0000000000..5d6def833d --- /dev/null +++ b/instructionAPI/ISA_ps/saddl_advsimd @@ -0,0 +1,21 @@ +##saddl_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = Vpart[n, part]; +bits(datasize) operand2 = Vpart[m, part]; +bits(2*datasize) result; +integer element1; +integer element2; +integer sum; + +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + if sub_op then + sum = element1 - element2; + else + sum = element1 + element2; + end + Elem[result, e, 2*esize] = sum<2*esize-1:0>; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/saddlp_advsimd b/instructionAPI/ISA_ps/saddlp_advsimd new file mode 100644 index 0000000000..daa6635767 --- /dev/null +++ b/instructionAPI/ISA_ps/saddlp_advsimd @@ -0,0 +1,18 @@ +##saddlp_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; + +bits(2*esize) sum; +integer op1; +integer op2; + +result = if acc then V[d] else Zeros(64); +for e = 0 to elements-1 + op1 = Int(Elem[operand, 2*e+0, esize], unsigned); + op2 = Int(Elem[operand, 2*e+1, esize], unsigned); + sum = (op1 + op2)<2*esize-1:0>; + Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/saddlv_advsimd b/instructionAPI/ISA_ps/saddlv_advsimd new file mode 100644 index 0000000000..94cd2ffaee --- /dev/null +++ b/instructionAPI/ISA_ps/saddlv_advsimd @@ -0,0 +1,11 @@ +##saddlv_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +integer sum; + +sum = Int(Elem[operand, 0, esize], unsigned); +for e = 1 to elements-1 + sum = sum + Int(Elem[operand, e, esize], unsigned); + +V[d] = sum<2*esize-1:0>; +@@ diff --git a/instructionAPI/ISA_ps/saddw_advsimd b/instructionAPI/ISA_ps/saddw_advsimd new file mode 100644 index 0000000000..590f680c82 --- /dev/null +++ b/instructionAPI/ISA_ps/saddw_advsimd @@ -0,0 +1,21 @@ +##saddw_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(2*datasize) operand1 = V[n]; +bits(datasize) operand2 = Vpart[m, part]; +bits(2*datasize) result; +integer element1; +integer element2; +integer sum; + +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, 2*esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + if sub_op then + sum = element1 - element2; + else + sum = element1 + element2; + end + Elem[result, e, 2*esize] = sum<2*esize-1:0>; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sbc b/instructionAPI/ISA_ps/sbc new file mode 100644 index 0000000000..8a0efe6788 --- /dev/null +++ b/instructionAPI/ISA_ps/sbc @@ -0,0 +1,18 @@ +##sbc_execute +bits(datasize) result; +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = X[m]; +bits(4) nzcv; + +if sub_op then + operand2 = NOT(operand2); +end + +(result, nzcv) = AddWithCarry(operand1, operand2, PSTATE.C); + +if setflags then + PSTATE. = nzcv; +end + +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sbcs b/instructionAPI/ISA_ps/sbcs new file mode 100644 index 0000000000..13c95ea263 --- /dev/null +++ b/instructionAPI/ISA_ps/sbcs @@ -0,0 +1,18 @@ +##sbcs_execute +bits(datasize) result; +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = X[m]; +bits(4) nzcv; + +if sub_op then + operand2 = NOT(operand2); +end + +(result, nzcv) = AddWithCarry(operand1, operand2, PSTATE.C); + +if setflags then + PSTATE. = nzcv; +end + +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sbfiz_sbfm b/instructionAPI/ISA_ps/sbfiz_sbfm new file mode 100644 index 0000000000..91b2c5ccc1 --- /dev/null +++ b/instructionAPI/ISA_ps/sbfiz_sbfm @@ -0,0 +1,13 @@ +##sbfiz_sbfm_execute +bits(datasize) dst = if inzero then Zeros(64) else X[d]; +bits(datasize) src = X[n]; + +// perform bitfield move on low bits +bits(datasize) bot = (dst AND NOT(wmask)) OR (ROR(src, R) AND wmask); + +// determine extension bits (sign, zero or dest register) +bits(datasize) top = if extend then Replicate(src) else dst; + +// combine extension bits and result bits +X[d] = (top AND NOT(tmask)) OR (bot AND tmask); +@@ diff --git a/instructionAPI/ISA_ps/sbfm b/instructionAPI/ISA_ps/sbfm new file mode 100644 index 0000000000..42a8fe7e1d --- /dev/null +++ b/instructionAPI/ISA_ps/sbfm @@ -0,0 +1,13 @@ +##sbfm_execute +bits(datasize) dst = if inzero then Zeros(64) else X[d]; +bits(datasize) src = X[n]; + +// perform bitfield move on low bits +bits(datasize) bot = (dst AND NOT(wmask)) OR (ROR(src, R) AND wmask); + +// determine extension bits (sign, zero or dest register) +bits(datasize) top = if extend then Replicate(src) else dst; + +// combine extension bits and result bits +X[d] = (top AND NOT(tmask)) OR (bot AND tmask); +@@ diff --git a/instructionAPI/ISA_ps/sbfx_sbfm b/instructionAPI/ISA_ps/sbfx_sbfm new file mode 100644 index 0000000000..8bf94af882 --- /dev/null +++ b/instructionAPI/ISA_ps/sbfx_sbfm @@ -0,0 +1,13 @@ +##sbfx_sbfm_execute +bits(datasize) dst = if inzero then Zeros(64) else X[d]; +bits(datasize) src = X[n]; + +// perform bitfield move on low bits +bits(datasize) bot = (dst AND NOT(wmask)) OR (ROR(src, R) AND wmask); + +// determine extension bits (sign, zero or dest register) +bits(datasize) top = if extend then Replicate(src) else dst; + +// combine extension bits and result bits +X[d] = (top AND NOT(tmask)) OR (bot AND tmask); +@@ diff --git a/instructionAPI/ISA_ps/scvtf_advsimd_fix b/instructionAPI/ISA_ps/scvtf_advsimd_fix new file mode 100644 index 0000000000..849606e3df --- /dev/null +++ b/instructionAPI/ISA_ps/scvtf_advsimd_fix @@ -0,0 +1,12 @@ +##scvtf_advsimd_fix_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +bits(esize) element; + +for e = 0 to elements-1 + element = Elem[operand, e, esize]; + Elem[result, e, esize] = FixedToFP(element, fracbits, unsigned, FPCR, rounding); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/scvtf_advsimd_int b/instructionAPI/ISA_ps/scvtf_advsimd_int new file mode 100644 index 0000000000..a1ccd14625 --- /dev/null +++ b/instructionAPI/ISA_ps/scvtf_advsimd_int @@ -0,0 +1,13 @@ +##scvtf_advsimd_int_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +FPRounding rounding = FPRoundingMode(FPCR); +bits(esize) element; + +for e = 0 to elements-1 + element = Elem[operand, e, esize]; + Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/scvtf_float_fix b/instructionAPI/ISA_ps/scvtf_float_fix new file mode 100644 index 0000000000..6c850ca557 --- /dev/null +++ b/instructionAPI/ISA_ps/scvtf_float_fix @@ -0,0 +1,18 @@ +##scvtf_float_fix_execute +CheckFPAdvSIMDEnabled64(); + +bits(fltsize) fltval; +bits(intsize) intval; + +case op of + when FPConvOp_CVT_FtoI + fltval = V[n]; + intval = FPToFixed(fltval, fracbits, unsigned, FPCR, rounding); + X[d] = intval; + end + when FPConvOp_CVT_ItoF + intval = X[n]; + fltval = FixedToFP(intval, fracbits, unsigned, FPCR, rounding); + V[d] = fltval; + end +@@ diff --git a/instructionAPI/ISA_ps/scvtf_float_int b/instructionAPI/ISA_ps/scvtf_float_int new file mode 100644 index 0000000000..1ac3c14d76 --- /dev/null +++ b/instructionAPI/ISA_ps/scvtf_float_int @@ -0,0 +1,26 @@ +##scvtf_float_int_execute +CheckFPAdvSIMDEnabled64(); + +bits(fltsize) fltval; +bits(intsize) intval; + +case op of + when FPConvOp_CVT_FtoI + fltval = V[n]; + intval = FPToFixed(fltval, 0, unsigned, FPCR, rounding); + X[d] = intval; + end + when FPConvOp_CVT_ItoF + intval = X[n]; + fltval = FixedToFP(intval, 0, unsigned, FPCR, rounding); + V[d] = fltval; + end + when FPConvOp_MOV_FtoI + intval = Vpart[n,part]; + X[d] = intval; + end + when FPConvOp_MOV_ItoF + intval = X[n]; + Vpart[d,part] = intval; + end +@@ diff --git a/instructionAPI/ISA_ps/sdiv b/instructionAPI/ISA_ps/sdiv new file mode 100644 index 0000000000..900e7a1320 --- /dev/null +++ b/instructionAPI/ISA_ps/sdiv @@ -0,0 +1,13 @@ +##sdiv_execute +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = X[m]; +integer result; + +if IsZero(operand2) then + result = 0; +else + result = RoundTowardsZero(Int(operand1, true) / Int(operand2, true)); +end + +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sev_hint b/instructionAPI/ISA_ps/sev_hint new file mode 100644 index 0000000000..4bf69d8c98 --- /dev/null +++ b/instructionAPI/ISA_ps/sev_hint @@ -0,0 +1,48 @@ +##sev_hint_execute +case op of + when SystemHintOp_YIELD + Hint_Yield(); + end + + when SystemHintOp_WFE + if EventRegistered() then + ClearEventRegister(); + else + if PSTATE.EL == EL0 then + AArch64.CheckForWFxTrap(EL1, TRUE); + end + if HaveEL(EL2) && !IsSecure() && PSTATE.EL IN {EL0,EL1} then + AArch64.CheckForWFxTrap(EL2, TRUE); + end + if HaveEL(EL3) && PSTATE.EL != EL3 then + AArch64.CheckForWFxTrap(EL3, TRUE); + end + WaitForEvent(); + end + + end + when SystemHintOp_WFI + if !InterruptPending() then + if PSTATE.EL == EL0 then + AArch64.CheckForWFxTrap(EL1, FALSE); + end + if HaveEL(EL2) && !IsSecure() && PSTATE.EL IN {EL0,EL1} then + AArch64.CheckForWFxTrap(EL2, FALSE); + end + if HaveEL(EL3) && PSTATE.EL != EL3 then + AArch64.CheckForWFxTrap(EL3, FALSE); + end + WaitForInterrupt(); + end + + end + when SystemHintOp_SEV + SendEvent(); + end + + when SystemHintOp_SEVL + EventRegisterSet(); + end + + otherwise // do nothing +@@ diff --git a/instructionAPI/ISA_ps/sevl_hint b/instructionAPI/ISA_ps/sevl_hint new file mode 100644 index 0000000000..f1c66928d8 --- /dev/null +++ b/instructionAPI/ISA_ps/sevl_hint @@ -0,0 +1,48 @@ +##sevl_hint_execute +case op of + when SystemHintOp_YIELD + Hint_Yield(); + end + + when SystemHintOp_WFE + if EventRegistered() then + ClearEventRegister(); + else + if PSTATE.EL == EL0 then + AArch64.CheckForWFxTrap(EL1, TRUE); + end + if HaveEL(EL2) && !IsSecure() && PSTATE.EL IN {EL0,EL1} then + AArch64.CheckForWFxTrap(EL2, TRUE); + end + if HaveEL(EL3) && PSTATE.EL != EL3 then + AArch64.CheckForWFxTrap(EL3, TRUE); + end + WaitForEvent(); + end + + end + when SystemHintOp_WFI + if !InterruptPending() then + if PSTATE.EL == EL0 then + AArch64.CheckForWFxTrap(EL1, FALSE); + end + if HaveEL(EL2) && !IsSecure() && PSTATE.EL IN {EL0,EL1} then + AArch64.CheckForWFxTrap(EL2, FALSE); + end + if HaveEL(EL3) && PSTATE.EL != EL3 then + AArch64.CheckForWFxTrap(EL3, FALSE); + end + WaitForInterrupt(); + end + + end + when SystemHintOp_SEV + SendEvent(); + end + + when SystemHintOp_SEVL + EventRegisterSet(); + end + + otherwise // do nothing +@@ diff --git a/instructionAPI/ISA_ps/sha1c_advsimd b/instructionAPI/ISA_ps/sha1c_advsimd new file mode 100644 index 0000000000..d07158477e --- /dev/null +++ b/instructionAPI/ISA_ps/sha1c_advsimd @@ -0,0 +1,15 @@ +##sha1c_advsimd_execute +CheckCryptoEnabled64(); + +bits(128) X = V[d]; +bits(32) Y = V[n]; // Note: 32 not 128 bits wide +bits(128) W = V[m]; +bits(32) t; + +for e = 0 to 3 + t = SHAchoose(X<63:32>, X<95:64>, X<127:96>); + Y = Y + ROL(X<31:0>, 5) + t + Elem[W, e, 32]; + X<63:32> = ROL(X<63:32>, 30); + = ROL(Y : X, 32); +V[d] = X; +@@ diff --git a/instructionAPI/ISA_ps/sha1h_advsimd b/instructionAPI/ISA_ps/sha1h_advsimd new file mode 100644 index 0000000000..d04eff955d --- /dev/null +++ b/instructionAPI/ISA_ps/sha1h_advsimd @@ -0,0 +1,6 @@ +##sha1h_advsimd_execute +CheckCryptoEnabled64(); + +bits(32) operand = V[n]; // read element [0] only, [1-3] zeroed +V[d] = ROL(operand, 30); +@@ diff --git a/instructionAPI/ISA_ps/sha1m_advsimd b/instructionAPI/ISA_ps/sha1m_advsimd new file mode 100644 index 0000000000..261361f361 --- /dev/null +++ b/instructionAPI/ISA_ps/sha1m_advsimd @@ -0,0 +1,15 @@ +##sha1m_advsimd_execute +CheckCryptoEnabled64(); + +bits(128) X = V[d]; +bits(32) Y = V[n]; // Note: 32 not 128 bits wide +bits(128) W = V[m]; +bits(32) t; + +for e = 0 to 3 + t = SHAmajority(X<63:32>, X<95:64>, X<127:96>); + Y = Y + ROL(X<31:0>, 5) + t + Elem[W, e, 32]; + X<63:32> = ROL(X<63:32>, 30); + = ROL(Y : X, 32); +V[d] = X; +@@ diff --git a/instructionAPI/ISA_ps/sha1p_advsimd b/instructionAPI/ISA_ps/sha1p_advsimd new file mode 100644 index 0000000000..cef7173810 --- /dev/null +++ b/instructionAPI/ISA_ps/sha1p_advsimd @@ -0,0 +1,15 @@ +##sha1p_advsimd_execute +CheckCryptoEnabled64(); + +bits(128) X = V[d]; +bits(32) Y = V[n]; // Note: 32 not 128 bits wide +bits(128) W = V[m]; +bits(32) t; + +for e = 0 to 3 + t = SHAparity(X<63:32>, X<95:64>, X<127:96>); + Y = Y + ROL(X<31:0>, 5) + t + Elem[W, e, 32]; + X<63:32> = ROL(X<63:32>, 30); + = ROL(Y : X, 32); +V[d] = X; +@@ diff --git a/instructionAPI/ISA_ps/sha1su0_advsimd b/instructionAPI/ISA_ps/sha1su0_advsimd new file mode 100644 index 0000000000..ffd19ddf12 --- /dev/null +++ b/instructionAPI/ISA_ps/sha1su0_advsimd @@ -0,0 +1,12 @@ +##sha1su0_advsimd_execute +CheckCryptoEnabled64(); + +bits(128) operand1 = V[d]; +bits(128) operand2 = V[n]; +bits(128) operand3 = V[m]; +bits(128) result; + +result = operand2<63:0> : operand1<127:64>; +result = result EOR operand1 EOR operand3; +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sha1su1_advsimd b/instructionAPI/ISA_ps/sha1su1_advsimd new file mode 100644 index 0000000000..266b6238e0 --- /dev/null +++ b/instructionAPI/ISA_ps/sha1su1_advsimd @@ -0,0 +1,13 @@ +##sha1su1_advsimd_execute +CheckCryptoEnabled64(); + +bits(128) operand1 = V[d]; +bits(128) operand2 = V[n]; +bits(128) result; +bits(128) T = operand1 EOR LSR(operand2, 32); +result<31:0> = ROL(T<31:0>, 1); +result<63:32> = ROL(T<63:32>, 1); +result<95:64> = ROL(T<95:64>, 1); +result<127:96> = ROL(T<127:96>, 1) EOR ROL(T<31:0>, 2); +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sha256h2_advsimd b/instructionAPI/ISA_ps/sha256h2_advsimd new file mode 100644 index 0000000000..ddb8f3f1e8 --- /dev/null +++ b/instructionAPI/ISA_ps/sha256h2_advsimd @@ -0,0 +1,11 @@ +##sha256h2_advsimd_execute +CheckCryptoEnabled64(); + +bits(128) result; +if part1 then + result = SHA256hash(V[d], V[n], V[m], TRUE); +else + result = SHA256hash(V[n], V[d], V[m], FALSE); +end +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sha256h_advsimd b/instructionAPI/ISA_ps/sha256h_advsimd new file mode 100644 index 0000000000..a531e14e84 --- /dev/null +++ b/instructionAPI/ISA_ps/sha256h_advsimd @@ -0,0 +1,11 @@ +##sha256h_advsimd_execute +CheckCryptoEnabled64(); + +bits(128) result; +if part1 then + result = SHA256hash(V[d], V[n], V[m], TRUE); +else + result = SHA256hash(V[n], V[d], V[m], FALSE); +end +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sha256su0_advsimd b/instructionAPI/ISA_ps/sha256su0_advsimd new file mode 100644 index 0000000000..17d033a080 --- /dev/null +++ b/instructionAPI/ISA_ps/sha256su0_advsimd @@ -0,0 +1,15 @@ +##sha256su0_advsimd_execute +CheckCryptoEnabled64(); + +bits(128) operand1 = V[d]; +bits(128) operand2 = V[n]; +bits(128) result; +bits(128) T = operand2<31:0> : operand1<127:32>; +bits(32) elt; + +for e = 0 to 3 + elt = Elem[T, e, 32]; + elt = ROR(elt, 7) EOR ROR(elt, 18) EOR LSR(elt, 3); + Elem[result, e, 32] = elt + Elem[operand1, e, 32]; +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sha256su1_advsimd b/instructionAPI/ISA_ps/sha256su1_advsimd new file mode 100644 index 0000000000..7eda820080 --- /dev/null +++ b/instructionAPI/ISA_ps/sha256su1_advsimd @@ -0,0 +1,27 @@ +##sha256su1_advsimd_execute +CheckCryptoEnabled64(); + +bits(128) operand1 = V[d]; +bits(128) operand2 = V[n]; +bits(128) operand3 = V[m]; +bits(128) result; +bits(128) T0 = operand3<31:0> : operand2<127:32>; +bits(64) T1; +bits(32) elt; + +T1 = operand3<127:64>; +for e = 0 to 1 + elt = Elem[T1, e, 32]; + elt = ROR(elt, 17) EOR ROR(elt, 19) EOR LSR(elt, 10); + elt = elt + Elem[operand1, e, 32] + Elem[T0, e, 32]; + Elem[result, e, 32] = elt; + +T1 = result<63:0>; +for e = 2 to 3 + elt = Elem[T1, e - 2, 32]; + elt = ROR(elt, 17) EOR ROR(elt, 19) EOR LSR(elt, 10); + elt = elt + Elem[operand1, e, 32] + Elem[T0, e, 32]; + Elem[result, e, 32] = elt; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/shadd_advsimd b/instructionAPI/ISA_ps/shadd_advsimd new file mode 100644 index 0000000000..2559efcf4f --- /dev/null +++ b/instructionAPI/ISA_ps/shadd_advsimd @@ -0,0 +1,17 @@ +##shadd_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +integer element1; +integer element2; +integer sum; + +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + sum = element1 + element2; + Elem[result, e, esize] = sum; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/shared_pseudocode b/instructionAPI/ISA_ps/shared_pseudocode new file mode 100644 index 0000000000..e69de29bb2 diff --git a/instructionAPI/ISA_ps/shl_advsimd b/instructionAPI/ISA_ps/shl_advsimd new file mode 100644 index 0000000000..1c2c92d3eb --- /dev/null +++ b/instructionAPI/ISA_ps/shl_advsimd @@ -0,0 +1,10 @@ +##shl_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; + +for e = 0 to elements-1 + Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/shll_advsimd b/instructionAPI/ISA_ps/shll_advsimd new file mode 100644 index 0000000000..a9e01cfd47 --- /dev/null +++ b/instructionAPI/ISA_ps/shll_advsimd @@ -0,0 +1,12 @@ +##shll_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = Vpart[n, part]; +bits(2*datasize) result; +integer element; + +for e = 0 to elements-1 + element = Int(Elem[operand, e, esize], unsigned) << shift; + Elem[result, e, 2*esize] = element<2*esize-1:0>; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/shrn_advsimd b/instructionAPI/ISA_ps/shrn_advsimd new file mode 100644 index 0000000000..06ec8f38e9 --- /dev/null +++ b/instructionAPI/ISA_ps/shrn_advsimd @@ -0,0 +1,13 @@ +##shrn_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize*2) operand = V[n]; +bits(datasize) result; +integer round_const = if round then (1 << (shift - 1)) else 0; +integer element; + +for e = 0 to elements-1 + element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift; + Elem[result, e, esize] = element; + +Vpart[d, part] = result; +@@ diff --git a/instructionAPI/ISA_ps/shsub_advsimd b/instructionAPI/ISA_ps/shsub_advsimd new file mode 100644 index 0000000000..7ef6dc9457 --- /dev/null +++ b/instructionAPI/ISA_ps/shsub_advsimd @@ -0,0 +1,17 @@ +##shsub_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +integer element1; +integer element2; +integer diff; + +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + diff = element1 - element2; + Elem[result, e, esize] = diff; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sli_advsimd b/instructionAPI/ISA_ps/sli_advsimd new file mode 100644 index 0000000000..946dac0ad7 --- /dev/null +++ b/instructionAPI/ISA_ps/sli_advsimd @@ -0,0 +1,13 @@ +##sli_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) operand2 = V[d]; +bits(datasize) result; +bits(esize) mask = LSL(Ones(esize), shift); +bits(esize) shifted; + +for e = 0 to elements-1 + shifted = LSL(Elem[operand, e, esize], shift); + Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted; +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/smaddl b/instructionAPI/ISA_ps/smaddl new file mode 100644 index 0000000000..e6c9c3fad0 --- /dev/null +++ b/instructionAPI/ISA_ps/smaddl @@ -0,0 +1,15 @@ +##smaddl_execute +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = X[m]; +bits(destsize) operand3 = X[a]; + +integer result; + +if sub_op then + result = Int(operand3, true) - (Int(operand1, true) * Int(operand2, true)); +else + result = Int(operand3, true) + (Int(operand1, true) * Int(operand2, true)); +end + +X[d] = result<63:0>; +@@ diff --git a/instructionAPI/ISA_ps/smax_advsimd b/instructionAPI/ISA_ps/smax_advsimd new file mode 100644 index 0000000000..507045f5bb --- /dev/null +++ b/instructionAPI/ISA_ps/smax_advsimd @@ -0,0 +1,17 @@ +##smax_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +integer element1; +integer element2; +integer maxmin; + +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + maxmin = if minimum then Min(element1, element2) else Max(element1, element2); + Elem[result, e, esize] = maxmin; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/smaxp_advsimd b/instructionAPI/ISA_ps/smaxp_advsimd new file mode 100644 index 0000000000..5a33502d2f --- /dev/null +++ b/instructionAPI/ISA_ps/smaxp_advsimd @@ -0,0 +1,18 @@ +##smaxp_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +bits(2*datasize) concat = operand2:operand1; +integer element1; +integer element2; +integer maxmin; + +for e = 0 to elements-1 + element1 = Int(Elem[concat, 2*e, esize], unsigned); + element2 = Int(Elem[concat, (2*e)+1, esize], unsigned); + maxmin = if minimum then Min(element1, element2) else Max(element1, element2); + Elem[result, e, esize] = maxmin; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/smaxv_advsimd b/instructionAPI/ISA_ps/smaxv_advsimd new file mode 100644 index 0000000000..0bd3726f28 --- /dev/null +++ b/instructionAPI/ISA_ps/smaxv_advsimd @@ -0,0 +1,13 @@ +##smaxv_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +integer maxmin; +integer element; + +maxmin = Int(Elem[operand, 0, esize], unsigned); +for e = 1 to elements-1 + element = Int(Elem[operand, e, esize], unsigned); + maxmin = if min then Min(maxmin, element) else Max(maxmin, element); + +V[d] = maxmin; +@@ diff --git a/instructionAPI/ISA_ps/smc b/instructionAPI/ISA_ps/smc new file mode 100644 index 0000000000..b1fb49d6bc --- /dev/null +++ b/instructionAPI/ISA_ps/smc @@ -0,0 +1,13 @@ +##smc_execute +if !HaveEL(EL3) || PSTATE.EL == EL0 then + UnallocatedEncoding(); + +AArch64.CheckForSMCTrap(imm); + +if SCR_EL3.SMD == 1 then + // SMC disabled + AArch64.UndefinedFault(); +else + AArch64.CallSecureMonitor(imm); +end +@@ diff --git a/instructionAPI/ISA_ps/smin_advsimd b/instructionAPI/ISA_ps/smin_advsimd new file mode 100644 index 0000000000..8aa31ff833 --- /dev/null +++ b/instructionAPI/ISA_ps/smin_advsimd @@ -0,0 +1,17 @@ +##smin_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +integer element1; +integer element2; +integer maxmin; + +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + maxmin = if minimum then Min(element1, element2) else Max(element1, element2); + Elem[result, e, esize] = maxmin; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sminp_advsimd b/instructionAPI/ISA_ps/sminp_advsimd new file mode 100644 index 0000000000..a9841dbf35 --- /dev/null +++ b/instructionAPI/ISA_ps/sminp_advsimd @@ -0,0 +1,18 @@ +##sminp_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +bits(2*datasize) concat = operand2:operand1; +integer element1; +integer element2; +integer maxmin; + +for e = 0 to elements-1 + element1 = Int(Elem[concat, 2*e, esize], unsigned); + element2 = Int(Elem[concat, (2*e)+1, esize], unsigned); + maxmin = if minimum then Min(element1, element2) else Max(element1, element2); + Elem[result, e, esize] = maxmin; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sminv_advsimd b/instructionAPI/ISA_ps/sminv_advsimd new file mode 100644 index 0000000000..44bfbae6eb --- /dev/null +++ b/instructionAPI/ISA_ps/sminv_advsimd @@ -0,0 +1,13 @@ +##sminv_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +integer maxmin; +integer element; + +maxmin = Int(Elem[operand, 0, esize], unsigned); +for e = 1 to elements-1 + element = Int(Elem[operand, e, esize], unsigned); + maxmin = if min then Min(maxmin, element) else Max(maxmin, element); + +V[d] = maxmin; +@@ diff --git a/instructionAPI/ISA_ps/smlal_advsimd_elt b/instructionAPI/ISA_ps/smlal_advsimd_elt new file mode 100644 index 0000000000..0d9a1514d4 --- /dev/null +++ b/instructionAPI/ISA_ps/smlal_advsimd_elt @@ -0,0 +1,22 @@ +##smlal_advsimd_elt_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = Vpart[n, part]; +bits(idxdsize) operand2 = V[m]; +bits(2*datasize) operand3 = V[d]; +bits(2*datasize) result; +integer element1; +integer element2; +bits(2*esize) product; + +element2 = Int(Elem[operand2, index, esize], unsigned); +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + product = (element1 * element2)<2*esize-1:0>; + if sub_op then + Elem[result, e, 2*esize] = Elem[operand3, e, 2*esize] - product; + else + Elem[result, e, 2*esize] = Elem[operand3, e, 2*esize] + product; + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/smlal_advsimd_vec b/instructionAPI/ISA_ps/smlal_advsimd_vec new file mode 100644 index 0000000000..36c2afa3bc --- /dev/null +++ b/instructionAPI/ISA_ps/smlal_advsimd_vec @@ -0,0 +1,24 @@ +##smlal_advsimd_vec_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = Vpart[n, part]; +bits(datasize) operand2 = Vpart[m, part]; +bits(2*datasize) operand3 = V[d]; +bits(2*datasize) result; +integer element1; +integer element2; +bits(2*esize) product; +bits(2*esize) accum; + +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + product = (element1 * element2)<2*esize-1:0>; + if sub_op then + accum = Elem[operand3, e, 2*esize] - product; + else + accum = Elem[operand3, e, 2*esize] + product; + end + Elem[result, e, 2*esize] = accum; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/smlsl_advsimd_elt b/instructionAPI/ISA_ps/smlsl_advsimd_elt new file mode 100644 index 0000000000..66de6ac979 --- /dev/null +++ b/instructionAPI/ISA_ps/smlsl_advsimd_elt @@ -0,0 +1,22 @@ +##smlsl_advsimd_elt_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = Vpart[n, part]; +bits(idxdsize) operand2 = V[m]; +bits(2*datasize) operand3 = V[d]; +bits(2*datasize) result; +integer element1; +integer element2; +bits(2*esize) product; + +element2 = Int(Elem[operand2, index, esize], unsigned); +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + product = (element1 * element2)<2*esize-1:0>; + if sub_op then + Elem[result, e, 2*esize] = Elem[operand3, e, 2*esize] - product; + else + Elem[result, e, 2*esize] = Elem[operand3, e, 2*esize] + product; + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/smlsl_advsimd_vec b/instructionAPI/ISA_ps/smlsl_advsimd_vec new file mode 100644 index 0000000000..7cba2876b8 --- /dev/null +++ b/instructionAPI/ISA_ps/smlsl_advsimd_vec @@ -0,0 +1,24 @@ +##smlsl_advsimd_vec_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = Vpart[n, part]; +bits(datasize) operand2 = Vpart[m, part]; +bits(2*datasize) operand3 = V[d]; +bits(2*datasize) result; +integer element1; +integer element2; +bits(2*esize) product; +bits(2*esize) accum; + +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + product = (element1 * element2)<2*esize-1:0>; + if sub_op then + accum = Elem[operand3, e, 2*esize] - product; + else + accum = Elem[operand3, e, 2*esize] + product; + end + Elem[result, e, 2*esize] = accum; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/smnegl_smsubl b/instructionAPI/ISA_ps/smnegl_smsubl new file mode 100644 index 0000000000..25fc1697e6 --- /dev/null +++ b/instructionAPI/ISA_ps/smnegl_smsubl @@ -0,0 +1,15 @@ +##smnegl_smsubl_execute +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = X[m]; +bits(destsize) operand3 = X[a]; + +integer result; + +if sub_op then + result = Int(operand3, true) - (Int(operand1, true) * Int(operand2, true)); +else + result = Int(operand3, true) + (Int(operand1, true) * Int(operand2, true)); +end + +X[d] = result<63:0>; +@@ diff --git a/instructionAPI/ISA_ps/smov_advsimd b/instructionAPI/ISA_ps/smov_advsimd new file mode 100644 index 0000000000..97a5e881b5 --- /dev/null +++ b/instructionAPI/ISA_ps/smov_advsimd @@ -0,0 +1,6 @@ +##smov_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(idxdsize) operand = V[n]; + +X[d] = SignExtend(Elem[operand, index, esize], datasize); +@@ diff --git a/instructionAPI/ISA_ps/smsubl b/instructionAPI/ISA_ps/smsubl new file mode 100644 index 0000000000..84b6dcaf44 --- /dev/null +++ b/instructionAPI/ISA_ps/smsubl @@ -0,0 +1,15 @@ +##smsubl_execute +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = X[m]; +bits(destsize) operand3 = X[a]; + +integer result; + +if sub_op then + result = Int(operand3, true) - (Int(operand1, true) * Int(operand2, true)); +else + result = Int(operand3, true) + (Int(operand1, true) * Int(operand2, true)); +end + +X[d] = result<63:0>; +@@ diff --git a/instructionAPI/ISA_ps/smulh b/instructionAPI/ISA_ps/smulh new file mode 100644 index 0000000000..10b5f75833 --- /dev/null +++ b/instructionAPI/ISA_ps/smulh @@ -0,0 +1,10 @@ +##smulh_execute +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = X[m]; + +integer result; + +result = Int(operand1, true) * Int(operand2, true); + +X[d] = result<127:64>; +@@ diff --git a/instructionAPI/ISA_ps/smull_advsimd_elt b/instructionAPI/ISA_ps/smull_advsimd_elt new file mode 100644 index 0000000000..a08462c7d4 --- /dev/null +++ b/instructionAPI/ISA_ps/smull_advsimd_elt @@ -0,0 +1,17 @@ +##smull_advsimd_elt_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = Vpart[n, part]; +bits(idxdsize) operand2 = V[m]; +bits(2*datasize) result; +integer element1; +integer element2; +bits(2*esize) product; + +element2 = Int(Elem[operand2, index, esize], unsigned); +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + product = (element1 * element2)<2*esize-1:0>; + Elem[result, e, 2*esize] = product; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/smull_advsimd_vec b/instructionAPI/ISA_ps/smull_advsimd_vec new file mode 100644 index 0000000000..2ab0f7a0e5 --- /dev/null +++ b/instructionAPI/ISA_ps/smull_advsimd_vec @@ -0,0 +1,15 @@ +##smull_advsimd_vec_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = Vpart[n, part]; +bits(datasize) operand2 = Vpart[m, part]; +bits(2*datasize) result; +integer element1; +integer element2; + +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + Elem[result, e, 2*esize] = (element1 * element2)<2*esize-1:0>; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/smull_smaddl b/instructionAPI/ISA_ps/smull_smaddl new file mode 100644 index 0000000000..a89ad5d6c2 --- /dev/null +++ b/instructionAPI/ISA_ps/smull_smaddl @@ -0,0 +1,15 @@ +##smull_smaddl_execute +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = X[m]; +bits(destsize) operand3 = X[a]; + +integer result; + +if sub_op then + result = Int(operand3, true) - (Int(operand1, true) * Int(operand2, true)); +else + result = Int(operand3, true) + (Int(operand1, true) * Int(operand2, true)); +end + +X[d] = result<63:0>; +@@ diff --git a/instructionAPI/ISA_ps/sqabs_advsimd b/instructionAPI/ISA_ps/sqabs_advsimd new file mode 100644 index 0000000000..c9d58bdfe5 --- /dev/null +++ b/instructionAPI/ISA_ps/sqabs_advsimd @@ -0,0 +1,19 @@ +##sqabs_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +integer element; +boolean sat; + +for e = 0 to elements-1 + element = SInt(Elem[operand, e, esize]); + if neg then + element = -element; + else + element = Abs(element); + end + (Elem[result, e, esize], sat) = SignedSatQ(element, esize); + if sat then FPSR.QC = 1; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sqadd_advsimd b/instructionAPI/ISA_ps/sqadd_advsimd new file mode 100644 index 0000000000..1cb97e2ea7 --- /dev/null +++ b/instructionAPI/ISA_ps/sqadd_advsimd @@ -0,0 +1,19 @@ +##sqadd_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +integer element1; +integer element2; +integer sum; +boolean sat; + +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + sum = element1 + element2; + (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned); + if sat then FPSR.QC = 1; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sqdmlal_advsimd_elt b/instructionAPI/ISA_ps/sqdmlal_advsimd_elt new file mode 100644 index 0000000000..0aec896c10 --- /dev/null +++ b/instructionAPI/ISA_ps/sqdmlal_advsimd_elt @@ -0,0 +1,27 @@ +##sqdmlal_advsimd_elt_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = Vpart[n, part]; +bits(idxdsize) operand2 = V[m]; +bits(2*datasize) operand3 = V[d]; +bits(2*datasize) result; +integer element1; +integer element2; +bits(2*esize) product; +integer accum; +boolean sat1; +boolean sat2; + +element2 = SInt(Elem[operand2, index, esize]); +for e = 0 to elements-1 + element1 = SInt(Elem[operand1, e, esize]); + (product, sat1) = SignedSatQ(2 * element1 * element2, 2*esize); + if sub_op then + accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product); + else + accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product); + end + (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2*esize); + if sat1 || sat2 then FPSR.QC = 1; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sqdmlal_advsimd_vec b/instructionAPI/ISA_ps/sqdmlal_advsimd_vec new file mode 100644 index 0000000000..dde084a09c --- /dev/null +++ b/instructionAPI/ISA_ps/sqdmlal_advsimd_vec @@ -0,0 +1,27 @@ +##sqdmlal_advsimd_vec_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = Vpart[n, part]; +bits(datasize) operand2 = Vpart[m, part]; +bits(2*datasize) operand3 = V[d]; +bits(2*datasize) result; +integer element1; +integer element2; +bits(2*esize) product; +integer accum; +boolean sat1; +boolean sat2; + +for e = 0 to elements-1 + element1 = SInt(Elem[operand1, e, esize]); + element2 = SInt(Elem[operand2, e, esize]); + (product, sat1) = SignedSatQ(2 * element1 * element2, 2*esize); + if sub_op then + accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product); + else + accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product); + end + (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2*esize); + if sat1 || sat2 then FPSR.QC = 1; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sqdmlsl_advsimd_elt b/instructionAPI/ISA_ps/sqdmlsl_advsimd_elt new file mode 100644 index 0000000000..e0e69778d0 --- /dev/null +++ b/instructionAPI/ISA_ps/sqdmlsl_advsimd_elt @@ -0,0 +1,27 @@ +##sqdmlsl_advsimd_elt_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = Vpart[n, part]; +bits(idxdsize) operand2 = V[m]; +bits(2*datasize) operand3 = V[d]; +bits(2*datasize) result; +integer element1; +integer element2; +bits(2*esize) product; +integer accum; +boolean sat1; +boolean sat2; + +element2 = SInt(Elem[operand2, index, esize]); +for e = 0 to elements-1 + element1 = SInt(Elem[operand1, e, esize]); + (product, sat1) = SignedSatQ(2 * element1 * element2, 2*esize); + if sub_op then + accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product); + else + accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product); + end + (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2*esize); + if sat1 || sat2 then FPSR.QC = 1; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sqdmlsl_advsimd_vec b/instructionAPI/ISA_ps/sqdmlsl_advsimd_vec new file mode 100644 index 0000000000..ec66919271 --- /dev/null +++ b/instructionAPI/ISA_ps/sqdmlsl_advsimd_vec @@ -0,0 +1,27 @@ +##sqdmlsl_advsimd_vec_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = Vpart[n, part]; +bits(datasize) operand2 = Vpart[m, part]; +bits(2*datasize) operand3 = V[d]; +bits(2*datasize) result; +integer element1; +integer element2; +bits(2*esize) product; +integer accum; +boolean sat1; +boolean sat2; + +for e = 0 to elements-1 + element1 = SInt(Elem[operand1, e, esize]); + element2 = SInt(Elem[operand2, e, esize]); + (product, sat1) = SignedSatQ(2 * element1 * element2, 2*esize); + if sub_op then + accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product); + else + accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product); + end + (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2*esize); + if sat1 || sat2 then FPSR.QC = 1; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sqdmulh_advsimd_elt b/instructionAPI/ISA_ps/sqdmulh_advsimd_elt new file mode 100644 index 0000000000..8652fea33f --- /dev/null +++ b/instructionAPI/ISA_ps/sqdmulh_advsimd_elt @@ -0,0 +1,21 @@ +##sqdmulh_advsimd_elt_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(idxdsize) operand2 = V[m]; +bits(datasize) result; +integer round_const = if round then 1 << (esize - 1) else 0; +integer element1; +integer element2; +integer product; +boolean sat; + +element2 = SInt(Elem[operand2, index, esize]); +for e = 0 to elements-1 + element1 = SInt(Elem[operand1, e, esize]); + product = (2 * element1 * element2) + round_const; + // The following only saturates if element1 and element2 equal -(2^(esize-1)) + (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize); + if sat then FPSR.QC = 1; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sqdmulh_advsimd_vec b/instructionAPI/ISA_ps/sqdmulh_advsimd_vec new file mode 100644 index 0000000000..26902117dd --- /dev/null +++ b/instructionAPI/ISA_ps/sqdmulh_advsimd_vec @@ -0,0 +1,20 @@ +##sqdmulh_advsimd_vec_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +integer round_const = if rounding then 1 << (esize - 1) else 0; +integer element1; +integer element2; +integer product; +boolean sat; + +for e = 0 to elements-1 + element1 = SInt(Elem[operand1, e, esize]); + element2 = SInt(Elem[operand2, e, esize]); + product = (2 * element1 * element2) + round_const; + (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize); + if sat then FPSR.QC = 1; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sqdmull_advsimd_elt b/instructionAPI/ISA_ps/sqdmull_advsimd_elt new file mode 100644 index 0000000000..a0661c6461 --- /dev/null +++ b/instructionAPI/ISA_ps/sqdmull_advsimd_elt @@ -0,0 +1,20 @@ +##sqdmull_advsimd_elt_execute +CheckFPAdvSIMDEnabled64(); + +bits(datasize) operand1 = Vpart[n, part]; +bits(idxdsize) operand2 = V[m]; +bits(2*datasize) result; +integer element1; +integer element2; +bits(2*esize) product; +boolean sat; + +element2 = SInt(Elem[operand2, index, esize]); +for e = 0 to elements-1 + element1 = SInt(Elem[operand1, e, esize]); + (product, sat) = SignedSatQ(2 * element1 * element2, 2*esize); + Elem[result, e, 2*esize] = product; + if sat then FPSR.QC = 1; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sqdmull_advsimd_vec b/instructionAPI/ISA_ps/sqdmull_advsimd_vec new file mode 100644 index 0000000000..3a49d4c471 --- /dev/null +++ b/instructionAPI/ISA_ps/sqdmull_advsimd_vec @@ -0,0 +1,19 @@ +##sqdmull_advsimd_vec_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = Vpart[n, part]; +bits(datasize) operand2 = Vpart[m, part]; +bits(2*datasize) result; +integer element1; +integer element2; +bits(2*esize) product; +boolean sat; + +for e = 0 to elements-1 + element1 = SInt(Elem[operand1, e, esize]); + element2 = SInt(Elem[operand2, e, esize]); + (product, sat) = SignedSatQ(2 * element1 * element2, 2*esize); + Elem[result, e, 2*esize] = product; + if sat then FPSR.QC = 1; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sqneg_advsimd b/instructionAPI/ISA_ps/sqneg_advsimd new file mode 100644 index 0000000000..3390b12cfc --- /dev/null +++ b/instructionAPI/ISA_ps/sqneg_advsimd @@ -0,0 +1,19 @@ +##sqneg_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +integer element; +boolean sat; + +for e = 0 to elements-1 + element = SInt(Elem[operand, e, esize]); + if neg then + element = -element; + else + element = Abs(element); + end + (Elem[result, e, esize], sat) = SignedSatQ(element, esize); + if sat then FPSR.QC = 1; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sqrdmulh_advsimd_elt b/instructionAPI/ISA_ps/sqrdmulh_advsimd_elt new file mode 100644 index 0000000000..389a37a8ce --- /dev/null +++ b/instructionAPI/ISA_ps/sqrdmulh_advsimd_elt @@ -0,0 +1,21 @@ +##sqrdmulh_advsimd_elt_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(idxdsize) operand2 = V[m]; +bits(datasize) result; +integer round_const = if round then 1 << (esize - 1) else 0; +integer element1; +integer element2; +integer product; +boolean sat; + +element2 = SInt(Elem[operand2, index, esize]); +for e = 0 to elements-1 + element1 = SInt(Elem[operand1, e, esize]); + product = (2 * element1 * element2) + round_const; + // The following only saturates if element1 and element2 equal -(2^(esize-1)) + (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize); + if sat then FPSR.QC = 1; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sqrdmulh_advsimd_vec b/instructionAPI/ISA_ps/sqrdmulh_advsimd_vec new file mode 100644 index 0000000000..5baa157f1a --- /dev/null +++ b/instructionAPI/ISA_ps/sqrdmulh_advsimd_vec @@ -0,0 +1,20 @@ +##sqrdmulh_advsimd_vec_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +integer round_const = if rounding then 1 << (esize - 1) else 0; +integer element1; +integer element2; +integer product; +boolean sat; + +for e = 0 to elements-1 + element1 = SInt(Elem[operand1, e, esize]); + element2 = SInt(Elem[operand2, e, esize]); + product = (2 * element1 * element2) + round_const; + (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize); + if sat then FPSR.QC = 1; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sqrshl_advsimd b/instructionAPI/ISA_ps/sqrshl_advsimd new file mode 100644 index 0000000000..64765132d4 --- /dev/null +++ b/instructionAPI/ISA_ps/sqrshl_advsimd @@ -0,0 +1,26 @@ +##sqrshl_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; + +integer round_const = 0; +integer shift; +integer element; +boolean sat; + +for e = 0 to elements-1 + shift = SInt(Elem[operand2, e, esize]<7:0>); + if rounding then + round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift + element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; + if saturating then + (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); + if sat then FPSR.QC = 1; + else + end + Elem[result, e, esize] = element; + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sqrshrn_advsimd b/instructionAPI/ISA_ps/sqrshrn_advsimd new file mode 100644 index 0000000000..9af8dbb3df --- /dev/null +++ b/instructionAPI/ISA_ps/sqrshrn_advsimd @@ -0,0 +1,15 @@ +##sqrshrn_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize*2) operand = V[n]; +bits(datasize) result; +integer round_const = if round then (1 << (shift - 1)) else 0; +integer element; +boolean sat; + +for e = 0 to elements-1 + element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift; + (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); + if sat then FPSR.QC = 1; + +Vpart[d, part] = result; +@@ diff --git a/instructionAPI/ISA_ps/sqrshrun_advsimd b/instructionAPI/ISA_ps/sqrshrun_advsimd new file mode 100644 index 0000000000..32fa47c16c --- /dev/null +++ b/instructionAPI/ISA_ps/sqrshrun_advsimd @@ -0,0 +1,15 @@ +##sqrshrun_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize*2) operand = V[n]; +bits(datasize) result; +integer round_const = if round then (1 << (shift - 1)) else 0; +integer element; +boolean sat; + +for e = 0 to elements-1 + element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift; + (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize); + if sat then FPSR.QC = 1; + +Vpart[d, part] = result; +@@ diff --git a/instructionAPI/ISA_ps/sqshl_advsimd_imm b/instructionAPI/ISA_ps/sqshl_advsimd_imm new file mode 100644 index 0000000000..6fe554a147 --- /dev/null +++ b/instructionAPI/ISA_ps/sqshl_advsimd_imm @@ -0,0 +1,14 @@ +##sqshl_advsimd_imm_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +integer element; +boolean sat; + +for e = 0 to elements-1 + element = Int(Elem[operand, e, esize], src_unsigned) << shift; + (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned); + if sat then FPSR.QC = 1; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sqshl_advsimd_reg b/instructionAPI/ISA_ps/sqshl_advsimd_reg new file mode 100644 index 0000000000..4499f4fd26 --- /dev/null +++ b/instructionAPI/ISA_ps/sqshl_advsimd_reg @@ -0,0 +1,26 @@ +##sqshl_advsimd_reg_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; + +integer round_const = 0; +integer shift; +integer element; +boolean sat; + +for e = 0 to elements-1 + shift = SInt(Elem[operand2, e, esize]<7:0>); + if rounding then + round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift + element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; + if saturating then + (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); + if sat then FPSR.QC = 1; + else + end + Elem[result, e, esize] = element; + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sqshlu_advsimd b/instructionAPI/ISA_ps/sqshlu_advsimd new file mode 100644 index 0000000000..6537823625 --- /dev/null +++ b/instructionAPI/ISA_ps/sqshlu_advsimd @@ -0,0 +1,14 @@ +##sqshlu_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +integer element; +boolean sat; + +for e = 0 to elements-1 + element = Int(Elem[operand, e, esize], src_unsigned) << shift; + (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned); + if sat then FPSR.QC = 1; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sqshrn_advsimd b/instructionAPI/ISA_ps/sqshrn_advsimd new file mode 100644 index 0000000000..32732a5cc6 --- /dev/null +++ b/instructionAPI/ISA_ps/sqshrn_advsimd @@ -0,0 +1,15 @@ +##sqshrn_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize*2) operand = V[n]; +bits(datasize) result; +integer round_const = if round then (1 << (shift - 1)) else 0; +integer element; +boolean sat; + +for e = 0 to elements-1 + element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift; + (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); + if sat then FPSR.QC = 1; + +Vpart[d, part] = result; +@@ diff --git a/instructionAPI/ISA_ps/sqshrun_advsimd b/instructionAPI/ISA_ps/sqshrun_advsimd new file mode 100644 index 0000000000..f53505f19e --- /dev/null +++ b/instructionAPI/ISA_ps/sqshrun_advsimd @@ -0,0 +1,15 @@ +##sqshrun_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize*2) operand = V[n]; +bits(datasize) result; +integer round_const = if round then (1 << (shift - 1)) else 0; +integer element; +boolean sat; + +for e = 0 to elements-1 + element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift; + (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize); + if sat then FPSR.QC = 1; + +Vpart[d, part] = result; +@@ diff --git a/instructionAPI/ISA_ps/sqsub_advsimd b/instructionAPI/ISA_ps/sqsub_advsimd new file mode 100644 index 0000000000..87ce05493f --- /dev/null +++ b/instructionAPI/ISA_ps/sqsub_advsimd @@ -0,0 +1,19 @@ +##sqsub_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +integer element1; +integer element2; +integer diff; +boolean sat; + +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + diff = element1 - element2; + (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned); + if sat then FPSR.QC = 1; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sqxtn_advsimd b/instructionAPI/ISA_ps/sqxtn_advsimd new file mode 100644 index 0000000000..4028c0c43a --- /dev/null +++ b/instructionAPI/ISA_ps/sqxtn_advsimd @@ -0,0 +1,14 @@ +##sqxtn_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(2*datasize) operand = V[n]; +bits(datasize) result; +bits(2*esize) element; +boolean sat; + +for e = 0 to elements-1 + element = Elem[operand, e, 2*esize]; + (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned); + if sat then FPSR.QC = 1; + +Vpart[d, part] = result; +@@ diff --git a/instructionAPI/ISA_ps/sqxtun_advsimd b/instructionAPI/ISA_ps/sqxtun_advsimd new file mode 100644 index 0000000000..1d421f4e88 --- /dev/null +++ b/instructionAPI/ISA_ps/sqxtun_advsimd @@ -0,0 +1,14 @@ +##sqxtun_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(2*datasize) operand = V[n]; +bits(datasize) result; +bits(2*esize) element; +boolean sat; + +for e = 0 to elements-1 + element = Elem[operand, e, 2*esize]; + (Elem[result, e, esize], sat) = UnsignedSatQ(SInt(element), esize); + if sat then FPSR.QC = 1; + +Vpart[d, part] = result; +@@ diff --git a/instructionAPI/ISA_ps/srhadd_advsimd b/instructionAPI/ISA_ps/srhadd_advsimd new file mode 100644 index 0000000000..9b58561720 --- /dev/null +++ b/instructionAPI/ISA_ps/srhadd_advsimd @@ -0,0 +1,15 @@ +##srhadd_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +integer element1; +integer element2; + +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + Elem[result, e, esize] = (element1 + element2 + 1); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sri_advsimd b/instructionAPI/ISA_ps/sri_advsimd new file mode 100644 index 0000000000..e8e6376c98 --- /dev/null +++ b/instructionAPI/ISA_ps/sri_advsimd @@ -0,0 +1,13 @@ +##sri_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) operand2 = V[d]; +bits(datasize) result; +bits(esize) mask = LSR(Ones(esize), shift); +bits(esize) shifted; + +for e = 0 to elements-1 + shifted = LSR(Elem[operand, e, esize], shift); + Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted; +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/srshl_advsimd b/instructionAPI/ISA_ps/srshl_advsimd new file mode 100644 index 0000000000..5c1c506454 --- /dev/null +++ b/instructionAPI/ISA_ps/srshl_advsimd @@ -0,0 +1,26 @@ +##srshl_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; + +integer round_const = 0; +integer shift; +integer element; +boolean sat; + +for e = 0 to elements-1 + shift = SInt(Elem[operand2, e, esize]<7:0>); + if rounding then + round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift + element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; + if saturating then + (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); + if sat then FPSR.QC = 1; + else + end + Elem[result, e, esize] = element; + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/srshr_advsimd b/instructionAPI/ISA_ps/srshr_advsimd new file mode 100644 index 0000000000..387f516aaf --- /dev/null +++ b/instructionAPI/ISA_ps/srshr_advsimd @@ -0,0 +1,15 @@ +##srshr_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) operand2; +bits(datasize) result; +integer round_const = if round then (1 << (shift - 1)) else 0; +integer element; + +operand2 = if accumulate then V[d] else Zeros(64); +for e = 0 to elements-1 + element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; + Elem[result, e, esize] = Elem[operand2, e, esize] + element; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/srsra_advsimd b/instructionAPI/ISA_ps/srsra_advsimd new file mode 100644 index 0000000000..87abd40ede --- /dev/null +++ b/instructionAPI/ISA_ps/srsra_advsimd @@ -0,0 +1,15 @@ +##srsra_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) operand2; +bits(datasize) result; +integer round_const = if round then (1 << (shift - 1)) else 0; +integer element; + +operand2 = if accumulate then V[d] else Zeros(64); +for e = 0 to elements-1 + element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; + Elem[result, e, esize] = Elem[operand2, e, esize] + element; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sshl_advsimd b/instructionAPI/ISA_ps/sshl_advsimd new file mode 100644 index 0000000000..a9cff2575e --- /dev/null +++ b/instructionAPI/ISA_ps/sshl_advsimd @@ -0,0 +1,26 @@ +##sshl_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; + +integer round_const = 0; +integer shift; +integer element; +boolean sat; + +for e = 0 to elements-1 + shift = SInt(Elem[operand2, e, esize]<7:0>); + if rounding then + round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift + element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; + if saturating then + (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); + if sat then FPSR.QC = 1; + else + end + Elem[result, e, esize] = element; + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sshll_advsimd b/instructionAPI/ISA_ps/sshll_advsimd new file mode 100644 index 0000000000..18101e9ed1 --- /dev/null +++ b/instructionAPI/ISA_ps/sshll_advsimd @@ -0,0 +1,12 @@ +##sshll_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = Vpart[n, part]; +bits(datasize*2) result; +integer element; + +for e = 0 to elements-1 + element = Int(Elem[operand, e, esize], unsigned) << shift; + Elem[result, e, 2*esize] = element<2*esize-1:0>; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sshr_advsimd b/instructionAPI/ISA_ps/sshr_advsimd new file mode 100644 index 0000000000..dd331004c5 --- /dev/null +++ b/instructionAPI/ISA_ps/sshr_advsimd @@ -0,0 +1,15 @@ +##sshr_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) operand2; +bits(datasize) result; +integer round_const = if round then (1 << (shift - 1)) else 0; +integer element; + +operand2 = if accumulate then V[d] else Zeros(64); +for e = 0 to elements-1 + element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; + Elem[result, e, esize] = Elem[operand2, e, esize] + element; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/ssra_advsimd b/instructionAPI/ISA_ps/ssra_advsimd new file mode 100644 index 0000000000..d2b110b74d --- /dev/null +++ b/instructionAPI/ISA_ps/ssra_advsimd @@ -0,0 +1,15 @@ +##ssra_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) operand2; +bits(datasize) result; +integer round_const = if round then (1 << (shift - 1)) else 0; +integer element; + +operand2 = if accumulate then V[d] else Zeros(64); +for e = 0 to elements-1 + element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; + Elem[result, e, esize] = Elem[operand2, e, esize] + element; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/ssubl_advsimd b/instructionAPI/ISA_ps/ssubl_advsimd new file mode 100644 index 0000000000..6b7b742a82 --- /dev/null +++ b/instructionAPI/ISA_ps/ssubl_advsimd @@ -0,0 +1,21 @@ +##ssubl_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = Vpart[n, part]; +bits(datasize) operand2 = Vpart[m, part]; +bits(2*datasize) result; +integer element1; +integer element2; +integer sum; + +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + if sub_op then + sum = element1 - element2; + else + sum = element1 + element2; + end + Elem[result, e, 2*esize] = sum<2*esize-1:0>; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/ssubw_advsimd b/instructionAPI/ISA_ps/ssubw_advsimd new file mode 100644 index 0000000000..8f2e275a37 --- /dev/null +++ b/instructionAPI/ISA_ps/ssubw_advsimd @@ -0,0 +1,21 @@ +##ssubw_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(2*datasize) operand1 = V[n]; +bits(datasize) operand2 = Vpart[m, part]; +bits(2*datasize) result; +integer element1; +integer element2; +integer sum; + +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, 2*esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + if sub_op then + sum = element1 - element2; + else + sum = element1 + element2; + end + Elem[result, e, 2*esize] = sum<2*esize-1:0>; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/st1_advsimd_mult b/instructionAPI/ISA_ps/st1_advsimd_mult new file mode 100644 index 0000000000..c325f80f97 --- /dev/null +++ b/instructionAPI/ISA_ps/st1_advsimd_mult @@ -0,0 +1,41 @@ +##st1_advsimd_mult_execute +CheckFPAdvSIMDEnabled64(); + +bits(64) address; +bits(64) offs; +bits(datasize) rval; +integer e, r, s, tt; +constant integer ebytes = esize / 8; + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +offs = Zeros(64); +for r = 0 to rpt-1 + for e = 0 to elements-1 + tt = (t + r) MOD 32; + for s = 0 to selem-1 + rval = V[tt]; + if memop == MemOp_LOAD then + Elem[rval, e, esize] = Mem[address + offs, ebytes, AccType_VEC]; + V[tt] = rval; + else // memop == MemOp_STORE + Mem[address + offs, ebytes, AccType_VEC] = Elem[rval, e, esize]; + end + offs = offs + ebytes; + tt = (tt + 1) MOD 32; + +if wback then + if m != 31 then + offs = X[m]; + end + if n == 31 then + SP[] = address + offs; + else + X[n] = address + offs; + end +end +@@ diff --git a/instructionAPI/ISA_ps/st1_advsimd_sngl b/instructionAPI/ISA_ps/st1_advsimd_sngl new file mode 100644 index 0000000000..af44d11e5a --- /dev/null +++ b/instructionAPI/ISA_ps/st1_advsimd_sngl @@ -0,0 +1,52 @@ +##st1_advsimd_sngl_execute +CheckFPAdvSIMDEnabled64(); + +bits(64) address; +bits(64) offs; +bits(128) rval; +bits(esize) element; +integer s; +constant integer ebytes = esize / 8; + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +offs = Zeros(64); +if replicate then + // load and replicate to all elements + for s = 0 to selem-1 + element = Mem[address + offs, ebytes, AccType_VEC]; + // replicate to fill 128- or 64-bit register + V[t] = Replicate(element, datasize / esize); + offs = offs + ebytes; + t = (t + 1) MOD 32; +else + // load/store one element per register + for s = 0 to selem-1 + rval = V[t]; + if memop == MemOp_LOAD then + // insert into one lane of 128-bit register + Elem[rval, index, esize] = Mem[address + offs, ebytes, AccType_VEC]; + V[t] = rval; + else // memop == MemOp_STORE + // extract from one lane of 128-bit register + Mem[address + offs, ebytes, AccType_VEC] = Elem[rval, index, esize]; + end + offs = offs + ebytes; + t = (t + 1) MOD 32; +end + +if wback then + if m != 31 then + offs = X[m]; + end + if n == 31 then + SP[] = address + offs; + else + X[n] = address + offs; + end +end +@@ diff --git a/instructionAPI/ISA_ps/st2_advsimd_mult b/instructionAPI/ISA_ps/st2_advsimd_mult new file mode 100644 index 0000000000..73f2386baf --- /dev/null +++ b/instructionAPI/ISA_ps/st2_advsimd_mult @@ -0,0 +1,41 @@ +##st2_advsimd_mult_execute +CheckFPAdvSIMDEnabled64(); + +bits(64) address; +bits(64) offs; +bits(datasize) rval; +integer e, r, s, tt; +constant integer ebytes = esize / 8; + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +offs = Zeros(64); +for r = 0 to rpt-1 + for e = 0 to elements-1 + tt = (t + r) MOD 32; + for s = 0 to selem-1 + rval = V[tt]; + if memop == MemOp_LOAD then + Elem[rval, e, esize] = Mem[address + offs, ebytes, AccType_VEC]; + V[tt] = rval; + else // memop == MemOp_STORE + Mem[address + offs, ebytes, AccType_VEC] = Elem[rval, e, esize]; + end + offs = offs + ebytes; + tt = (tt + 1) MOD 32; + +if wback then + if m != 31 then + offs = X[m]; + end + if n == 31 then + SP[] = address + offs; + else + X[n] = address + offs; + end +end +@@ diff --git a/instructionAPI/ISA_ps/st2_advsimd_sngl b/instructionAPI/ISA_ps/st2_advsimd_sngl new file mode 100644 index 0000000000..6462f68171 --- /dev/null +++ b/instructionAPI/ISA_ps/st2_advsimd_sngl @@ -0,0 +1,52 @@ +##st2_advsimd_sngl_execute +CheckFPAdvSIMDEnabled64(); + +bits(64) address; +bits(64) offs; +bits(128) rval; +bits(esize) element; +integer s; +constant integer ebytes = esize / 8; + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +offs = Zeros(64); +if replicate then + // load and replicate to all elements + for s = 0 to selem-1 + element = Mem[address + offs, ebytes, AccType_VEC]; + // replicate to fill 128- or 64-bit register + V[t] = Replicate(element, datasize / esize); + offs = offs + ebytes; + t = (t + 1) MOD 32; +else + // load/store one element per register + for s = 0 to selem-1 + rval = V[t]; + if memop == MemOp_LOAD then + // insert into one lane of 128-bit register + Elem[rval, index, esize] = Mem[address + offs, ebytes, AccType_VEC]; + V[t] = rval; + else // memop == MemOp_STORE + // extract from one lane of 128-bit register + Mem[address + offs, ebytes, AccType_VEC] = Elem[rval, index, esize]; + end + offs = offs + ebytes; + t = (t + 1) MOD 32; +end + +if wback then + if m != 31 then + offs = X[m]; + end + if n == 31 then + SP[] = address + offs; + else + X[n] = address + offs; + end +end +@@ diff --git a/instructionAPI/ISA_ps/st3_advsimd_mult b/instructionAPI/ISA_ps/st3_advsimd_mult new file mode 100644 index 0000000000..d2e40a4495 --- /dev/null +++ b/instructionAPI/ISA_ps/st3_advsimd_mult @@ -0,0 +1,41 @@ +##st3_advsimd_mult_execute +CheckFPAdvSIMDEnabled64(); + +bits(64) address; +bits(64) offs; +bits(datasize) rval; +integer e, r, s, tt; +constant integer ebytes = esize / 8; + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +offs = Zeros(64); +for r = 0 to rpt-1 + for e = 0 to elements-1 + tt = (t + r) MOD 32; + for s = 0 to selem-1 + rval = V[tt]; + if memop == MemOp_LOAD then + Elem[rval, e, esize] = Mem[address + offs, ebytes, AccType_VEC]; + V[tt] = rval; + else // memop == MemOp_STORE + Mem[address + offs, ebytes, AccType_VEC] = Elem[rval, e, esize]; + end + offs = offs + ebytes; + tt = (tt + 1) MOD 32; + +if wback then + if m != 31 then + offs = X[m]; + end + if n == 31 then + SP[] = address + offs; + else + X[n] = address + offs; + end +end +@@ diff --git a/instructionAPI/ISA_ps/st3_advsimd_sngl b/instructionAPI/ISA_ps/st3_advsimd_sngl new file mode 100644 index 0000000000..c327986493 --- /dev/null +++ b/instructionAPI/ISA_ps/st3_advsimd_sngl @@ -0,0 +1,52 @@ +##st3_advsimd_sngl_execute +CheckFPAdvSIMDEnabled64(); + +bits(64) address; +bits(64) offs; +bits(128) rval; +bits(esize) element; +integer s; +constant integer ebytes = esize / 8; + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +offs = Zeros(64); +if replicate then + // load and replicate to all elements + for s = 0 to selem-1 + element = Mem[address + offs, ebytes, AccType_VEC]; + // replicate to fill 128- or 64-bit register + V[t] = Replicate(element, datasize / esize); + offs = offs + ebytes; + t = (t + 1) MOD 32; +else + // load/store one element per register + for s = 0 to selem-1 + rval = V[t]; + if memop == MemOp_LOAD then + // insert into one lane of 128-bit register + Elem[rval, index, esize] = Mem[address + offs, ebytes, AccType_VEC]; + V[t] = rval; + else // memop == MemOp_STORE + // extract from one lane of 128-bit register + Mem[address + offs, ebytes, AccType_VEC] = Elem[rval, index, esize]; + end + offs = offs + ebytes; + t = (t + 1) MOD 32; +end + +if wback then + if m != 31 then + offs = X[m]; + end + if n == 31 then + SP[] = address + offs; + else + X[n] = address + offs; + end +end +@@ diff --git a/instructionAPI/ISA_ps/st4_advsimd_mult b/instructionAPI/ISA_ps/st4_advsimd_mult new file mode 100644 index 0000000000..ffed3ab5a4 --- /dev/null +++ b/instructionAPI/ISA_ps/st4_advsimd_mult @@ -0,0 +1,41 @@ +##st4_advsimd_mult_execute +CheckFPAdvSIMDEnabled64(); + +bits(64) address; +bits(64) offs; +bits(datasize) rval; +integer e, r, s, tt; +constant integer ebytes = esize / 8; + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +offs = Zeros(64); +for r = 0 to rpt-1 + for e = 0 to elements-1 + tt = (t + r) MOD 32; + for s = 0 to selem-1 + rval = V[tt]; + if memop == MemOp_LOAD then + Elem[rval, e, esize] = Mem[address + offs, ebytes, AccType_VEC]; + V[tt] = rval; + else // memop == MemOp_STORE + Mem[address + offs, ebytes, AccType_VEC] = Elem[rval, e, esize]; + end + offs = offs + ebytes; + tt = (tt + 1) MOD 32; + +if wback then + if m != 31 then + offs = X[m]; + end + if n == 31 then + SP[] = address + offs; + else + X[n] = address + offs; + end +end +@@ diff --git a/instructionAPI/ISA_ps/st4_advsimd_sngl b/instructionAPI/ISA_ps/st4_advsimd_sngl new file mode 100644 index 0000000000..227c090fd2 --- /dev/null +++ b/instructionAPI/ISA_ps/st4_advsimd_sngl @@ -0,0 +1,52 @@ +##st4_advsimd_sngl_execute +CheckFPAdvSIMDEnabled64(); + +bits(64) address; +bits(64) offs; +bits(128) rval; +bits(esize) element; +integer s; +constant integer ebytes = esize / 8; + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +offs = Zeros(64); +if replicate then + // load and replicate to all elements + for s = 0 to selem-1 + element = Mem[address + offs, ebytes, AccType_VEC]; + // replicate to fill 128- or 64-bit register + V[t] = Replicate(element, datasize / esize); + offs = offs + ebytes; + t = (t + 1) MOD 32; +else + // load/store one element per register + for s = 0 to selem-1 + rval = V[t]; + if memop == MemOp_LOAD then + // insert into one lane of 128-bit register + Elem[rval, index, esize] = Mem[address + offs, ebytes, AccType_VEC]; + V[t] = rval; + else // memop == MemOp_STORE + // extract from one lane of 128-bit register + Mem[address + offs, ebytes, AccType_VEC] = Elem[rval, index, esize]; + end + offs = offs + ebytes; + t = (t + 1) MOD 32; +end + +if wback then + if m != 31 then + offs = X[m]; + end + if n == 31 then + SP[] = address + offs; + else + X[n] = address + offs; + end +end +@@ diff --git a/instructionAPI/ISA_ps/stlr b/instructionAPI/ISA_ps/stlr new file mode 100644 index 0000000000..713301194d --- /dev/null +++ b/instructionAPI/ISA_ps/stlr @@ -0,0 +1,22 @@ +##stlr_execute +bits(64) address; +bits(datasize) data; +constant integer dbytes = datasize / 8; + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +case memop of + when MemOp_STORE + data = X[t]; + Mem[address, dbytes, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, dbytes, acctype]; + X[t] = ZeroExtend(data, regsize); + end +@@ diff --git a/instructionAPI/ISA_ps/stlrb b/instructionAPI/ISA_ps/stlrb new file mode 100644 index 0000000000..1c12a4e1b5 --- /dev/null +++ b/instructionAPI/ISA_ps/stlrb @@ -0,0 +1,22 @@ +##stlrb_execute +bits(64) address; +bits(datasize) data; +constant integer dbytes = datasize / 8; + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +case memop of + when MemOp_STORE + data = X[t]; + Mem[address, dbytes, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, dbytes, acctype]; + X[t] = ZeroExtend(data, regsize); + end +@@ diff --git a/instructionAPI/ISA_ps/stlrh b/instructionAPI/ISA_ps/stlrh new file mode 100644 index 0000000000..99cd1d0e03 --- /dev/null +++ b/instructionAPI/ISA_ps/stlrh @@ -0,0 +1,22 @@ +##stlrh_execute +bits(64) address; +bits(datasize) data; +constant integer dbytes = datasize / 8; + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +case memop of + when MemOp_STORE + data = X[t]; + Mem[address, dbytes, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, dbytes, acctype]; + X[t] = ZeroExtend(data, regsize); + end +@@ diff --git a/instructionAPI/ISA_ps/stlxp b/instructionAPI/ISA_ps/stlxp new file mode 100644 index 0000000000..0bac419bd2 --- /dev/null +++ b/instructionAPI/ISA_ps/stlxp @@ -0,0 +1,94 @@ +##stlxp_execute +bits(64) address; +bits(datasize) data; +constant integer dbytes = datasize / 8; +boolean rt_unknown = FALSE; +boolean rn_unknown = FALSE; + +if memop == MemOp_LOAD && pair && t == t2 then + case c of +end + +if memop == MemOp_STORE then + if s == t || (pair && s == t2) then + case c of + end + if s == n && n != 31 then + case c of + end + +end +if n == 31 then + address = SP[]; +elsif rn_unknown then + address = bits(64) UNKNOWN; +else + address = X[n]; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + elsif pair then + bits(datasize / 2) el1 = X[t]; + bits(datasize / 2) el2 = X[t2]; + data = if BigEndian() then el1 : el2 else el2 : el1; + else + end + data = X[t]; + end + + bit status = 1; + // Check whether the Exclusive Monitors are set to include the + // physical memory locations corresponding to virtual address + // range [address, address+dbytes-1]. + if AArch64.ExclusiveMonitorsPass(address, dbytes) then + // This atomic write will be rejected if it does not refer + // to the same physical locations after address translation. + Mem[address, dbytes, acctype] = data; + status = ExclusiveMonitorsStatus(); + end + X[s] = ZeroExtend(status, 32); + end + + when MemOp_LOAD + // Tell the Exclusive Monitors to record a sequence of one or more atomic + // memory reads from virtual address range [address, address+dbytes-1]. + // The Exclusive Monitor will only be set if all the reads are from the + // same dbytes-aligned physical address, to allow for the possibility of + // an atomicity break if the translation is changed between reads. + AArch64.SetExclusiveMonitors(address, dbytes); + end + + if pair then + // load exclusive pair + if rt_unknown then + X[t] = bits(datasize) UNKNOWN; + elsif elsize == 32 then + // 32-bit load exclusive pair (atomic) + data = Mem[address, dbytes, acctype]; + if BigEndian() then + X[t] = data; + X[t2] = data; + else + X[t] = data; + X[t2] = data; + else // elsize == 64 + end + // 64-bit load exclusive pair (not atomic), + // but must be 128-bit aligned + if address != Align(address, dbytes) then + iswrite = FALSE; + secondstage = FALSE; + AArch64.Abort(address, AArch64.AlignmentFault(acctype, iswrite, secondstage)); + end + X[t] = Mem[address + 0, 8, acctype]; + X[t2] = Mem[address + 8, 8, acctype]; + else + end + // load {acquire} {exclusive} single register + data = Mem[address, dbytes, acctype]; + X[t] = ZeroExtend(data, regsize); + end +@@ diff --git a/instructionAPI/ISA_ps/stlxr b/instructionAPI/ISA_ps/stlxr new file mode 100644 index 0000000000..26feb8cc4e --- /dev/null +++ b/instructionAPI/ISA_ps/stlxr @@ -0,0 +1,94 @@ +##stlxr_execute +bits(64) address; +bits(datasize) data; +constant integer dbytes = datasize / 8; +boolean rt_unknown = FALSE; +boolean rn_unknown = FALSE; + +if memop == MemOp_LOAD && pair && t == t2 then + case c of +end + +if memop == MemOp_STORE then + if s == t || (pair && s == t2) then + case c of + end + if s == n && n != 31 then + case c of + end + +end +if n == 31 then + address = SP[]; +elsif rn_unknown then + address = bits(64) UNKNOWN; +else + address = X[n]; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + elsif pair then + bits(datasize / 2) el1 = X[t]; + bits(datasize / 2) el2 = X[t2]; + data = if BigEndian() then el1 : el2 else el2 : el1; + else + end + data = X[t]; + end + + bit status = 1; + // Check whether the Exclusive Monitors are set to include the + // physical memory locations corresponding to virtual address + // range [address, address+dbytes-1]. + if AArch64.ExclusiveMonitorsPass(address, dbytes) then + // This atomic write will be rejected if it does not refer + // to the same physical locations after address translation. + Mem[address, dbytes, acctype] = data; + status = ExclusiveMonitorsStatus(); + end + X[s] = ZeroExtend(status, 32); + end + + when MemOp_LOAD + // Tell the Exclusive Monitors to record a sequence of one or more atomic + // memory reads from virtual address range [address, address+dbytes-1]. + // The Exclusive Monitor will only be set if all the reads are from the + // same dbytes-aligned physical address, to allow for the possibility of + // an atomicity break if the translation is changed between reads. + AArch64.SetExclusiveMonitors(address, dbytes); + end + + if pair then + // load exclusive pair + if rt_unknown then + X[t] = bits(datasize) UNKNOWN; + elsif elsize == 32 then + // 32-bit load exclusive pair (atomic) + data = Mem[address, dbytes, acctype]; + if BigEndian() then + X[t] = data; + X[t2] = data; + else + X[t] = data; + X[t2] = data; + else // elsize == 64 + end + // 64-bit load exclusive pair (not atomic), + // but must be 128-bit aligned + if address != Align(address, dbytes) then + iswrite = FALSE; + secondstage = FALSE; + AArch64.Abort(address, AArch64.AlignmentFault(acctype, iswrite, secondstage)); + end + X[t] = Mem[address + 0, 8, acctype]; + X[t2] = Mem[address + 8, 8, acctype]; + else + end + // load {acquire} {exclusive} single register + data = Mem[address, dbytes, acctype]; + X[t] = ZeroExtend(data, regsize); + end +@@ diff --git a/instructionAPI/ISA_ps/stlxrb b/instructionAPI/ISA_ps/stlxrb new file mode 100644 index 0000000000..9466a53e25 --- /dev/null +++ b/instructionAPI/ISA_ps/stlxrb @@ -0,0 +1,94 @@ +##stlxrb_execute +bits(64) address; +bits(datasize) data; +constant integer dbytes = datasize / 8; +boolean rt_unknown = FALSE; +boolean rn_unknown = FALSE; + +if memop == MemOp_LOAD && pair && t == t2 then + case c of +end + +if memop == MemOp_STORE then + if s == t || (pair && s == t2) then + case c of + end + if s == n && n != 31 then + case c of + end + +end +if n == 31 then + address = SP[]; +elsif rn_unknown then + address = bits(64) UNKNOWN; +else + address = X[n]; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + elsif pair then + bits(datasize / 2) el1 = X[t]; + bits(datasize / 2) el2 = X[t2]; + data = if BigEndian() then el1 : el2 else el2 : el1; + else + end + data = X[t]; + end + + bit status = 1; + // Check whether the Exclusive Monitors are set to include the + // physical memory locations corresponding to virtual address + // range [address, address+dbytes-1]. + if AArch64.ExclusiveMonitorsPass(address, dbytes) then + // This atomic write will be rejected if it does not refer + // to the same physical locations after address translation. + Mem[address, dbytes, acctype] = data; + status = ExclusiveMonitorsStatus(); + end + X[s] = ZeroExtend(status, 32); + end + + when MemOp_LOAD + // Tell the Exclusive Monitors to record a sequence of one or more atomic + // memory reads from virtual address range [address, address+dbytes-1]. + // The Exclusive Monitor will only be set if all the reads are from the + // same dbytes-aligned physical address, to allow for the possibility of + // an atomicity break if the translation is changed between reads. + AArch64.SetExclusiveMonitors(address, dbytes); + end + + if pair then + // load exclusive pair + if rt_unknown then + X[t] = bits(datasize) UNKNOWN; + elsif elsize == 32 then + // 32-bit load exclusive pair (atomic) + data = Mem[address, dbytes, acctype]; + if BigEndian() then + X[t] = data; + X[t2] = data; + else + X[t] = data; + X[t2] = data; + else // elsize == 64 + end + // 64-bit load exclusive pair (not atomic), + // but must be 128-bit aligned + if address != Align(address, dbytes) then + iswrite = FALSE; + secondstage = FALSE; + AArch64.Abort(address, AArch64.AlignmentFault(acctype, iswrite, secondstage)); + end + X[t] = Mem[address + 0, 8, acctype]; + X[t2] = Mem[address + 8, 8, acctype]; + else + end + // load {acquire} {exclusive} single register + data = Mem[address, dbytes, acctype]; + X[t] = ZeroExtend(data, regsize); + end +@@ diff --git a/instructionAPI/ISA_ps/stlxrh b/instructionAPI/ISA_ps/stlxrh new file mode 100644 index 0000000000..3cf70b918c --- /dev/null +++ b/instructionAPI/ISA_ps/stlxrh @@ -0,0 +1,94 @@ +##stlxrh_execute +bits(64) address; +bits(datasize) data; +constant integer dbytes = datasize / 8; +boolean rt_unknown = FALSE; +boolean rn_unknown = FALSE; + +if memop == MemOp_LOAD && pair && t == t2 then + case c of +end + +if memop == MemOp_STORE then + if s == t || (pair && s == t2) then + case c of + end + if s == n && n != 31 then + case c of + end + +end +if n == 31 then + address = SP[]; +elsif rn_unknown then + address = bits(64) UNKNOWN; +else + address = X[n]; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + elsif pair then + bits(datasize / 2) el1 = X[t]; + bits(datasize / 2) el2 = X[t2]; + data = if BigEndian() then el1 : el2 else el2 : el1; + else + end + data = X[t]; + end + + bit status = 1; + // Check whether the Exclusive Monitors are set to include the + // physical memory locations corresponding to virtual address + // range [address, address+dbytes-1]. + if AArch64.ExclusiveMonitorsPass(address, dbytes) then + // This atomic write will be rejected if it does not refer + // to the same physical locations after address translation. + Mem[address, dbytes, acctype] = data; + status = ExclusiveMonitorsStatus(); + end + X[s] = ZeroExtend(status, 32); + end + + when MemOp_LOAD + // Tell the Exclusive Monitors to record a sequence of one or more atomic + // memory reads from virtual address range [address, address+dbytes-1]. + // The Exclusive Monitor will only be set if all the reads are from the + // same dbytes-aligned physical address, to allow for the possibility of + // an atomicity break if the translation is changed between reads. + AArch64.SetExclusiveMonitors(address, dbytes); + end + + if pair then + // load exclusive pair + if rt_unknown then + X[t] = bits(datasize) UNKNOWN; + elsif elsize == 32 then + // 32-bit load exclusive pair (atomic) + data = Mem[address, dbytes, acctype]; + if BigEndian() then + X[t] = data; + X[t2] = data; + else + X[t] = data; + X[t2] = data; + else // elsize == 64 + end + // 64-bit load exclusive pair (not atomic), + // but must be 128-bit aligned + if address != Align(address, dbytes) then + iswrite = FALSE; + secondstage = FALSE; + AArch64.Abort(address, AArch64.AlignmentFault(acctype, iswrite, secondstage)); + end + X[t] = Mem[address + 0, 8, acctype]; + X[t2] = Mem[address + 8, 8, acctype]; + else + end + // load {acquire} {exclusive} single register + data = Mem[address, dbytes, acctype]; + X[t] = ZeroExtend(data, regsize); + end +@@ diff --git a/instructionAPI/ISA_ps/stnp_fpsimd b/instructionAPI/ISA_ps/stnp_fpsimd new file mode 100644 index 0000000000..ac26d2fb50 --- /dev/null +++ b/instructionAPI/ISA_ps/stnp_fpsimd @@ -0,0 +1,53 @@ +##stnp_fpsimd_execute +CheckFPAdvSIMDEnabled64(); + +bits(64) address; +bits(datasize) data1; +bits(datasize) data2; +constant integer dbytes = datasize / 8; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && t == t2 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + data1 = V[t]; + data2 = V[t2]; + Mem[address + 0 , dbytes, acctype] = data1; + Mem[address + dbytes, dbytes, acctype] = data2; + end + + when MemOp_LOAD + data1 = Mem[address + 0 , dbytes, acctype]; + data2 = Mem[address + dbytes, dbytes, acctype]; + if rt_unknown then + data1 = bits(datasize) UNKNOWN; + data2 = bits(datasize) UNKNOWN; + end + V[t] = data1; + V[t2] = data2; + end + +if wback then + if postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/stnp_gen b/instructionAPI/ISA_ps/stnp_gen new file mode 100644 index 0000000000..712f2c7ebf --- /dev/null +++ b/instructionAPI/ISA_ps/stnp_gen @@ -0,0 +1,59 @@ +##stnp_gen_execute +bits(64) address; +bits(datasize) data1; +bits(datasize) data2; +constant integer dbytes = datasize / 8; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && t == t2 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown && t == n then + data1 = bits(datasize) UNKNOWN; + else + data1 = X[t]; + end + if rt_unknown && t2 == n then + data2 = bits(datasize) UNKNOWN; + else + data2 = X[t2]; + end + Mem[address + 0 , dbytes, acctype] = data1; + Mem[address + dbytes, dbytes, acctype] = data2; + end + + when MemOp_LOAD + data1 = Mem[address + 0 , dbytes, acctype]; + data2 = Mem[address + dbytes, dbytes, acctype]; + if rt_unknown then + data1 = bits(datasize) UNKNOWN; + data2 = bits(datasize) UNKNOWN; + end + X[t] = data1; + X[t2] = data2; + end + +if wback then + if postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/stp_fpsimd b/instructionAPI/ISA_ps/stp_fpsimd new file mode 100644 index 0000000000..f9f251c006 --- /dev/null +++ b/instructionAPI/ISA_ps/stp_fpsimd @@ -0,0 +1,53 @@ +##stp_fpsimd_execute +CheckFPAdvSIMDEnabled64(); + +bits(64) address; +bits(datasize) data1; +bits(datasize) data2; +constant integer dbytes = datasize / 8; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && t == t2 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + data1 = V[t]; + data2 = V[t2]; + Mem[address + 0 , dbytes, acctype] = data1; + Mem[address + dbytes, dbytes, acctype] = data2; + end + + when MemOp_LOAD + data1 = Mem[address + 0 , dbytes, acctype]; + data2 = Mem[address + dbytes, dbytes, acctype]; + if rt_unknown then + data1 = bits(datasize) UNKNOWN; + data2 = bits(datasize) UNKNOWN; + end + V[t] = data1; + V[t2] = data2; + end + +if wback then + if postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/stp_gen b/instructionAPI/ISA_ps/stp_gen new file mode 100644 index 0000000000..79975a8731 --- /dev/null +++ b/instructionAPI/ISA_ps/stp_gen @@ -0,0 +1,76 @@ +##stp_gen_execute +bits(64) address; +bits(datasize) data1; +bits(datasize) data2; +constant integer dbytes = datasize / 8; +boolean rt_unknown = FALSE; +boolean wb_unknown = FALSE; + +if memop == MemOp_LOAD && wback && (t == n || t2 == n) && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && (t == n || t2 == n) && n != 31 then + case c of +end + +if memop == MemOp_LOAD && t == t2 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown && t == n then + data1 = bits(datasize) UNKNOWN; + else + data1 = X[t]; + end + if rt_unknown && t2 == n then + data2 = bits(datasize) UNKNOWN; + else + data2 = X[t2]; + end + Mem[address + 0 , dbytes, acctype] = data1; + Mem[address + dbytes, dbytes, acctype] = data2; + end + + when MemOp_LOAD + data1 = Mem[address + 0 , dbytes, acctype]; + data2 = Mem[address + dbytes, dbytes, acctype]; + if rt_unknown then + data1 = bits(datasize) UNKNOWN; + data2 = bits(datasize) UNKNOWN; + end + if signed then + X[t] = SignExtend(data1, 64); + X[t2] = SignExtend(data2, 64); + else + X[t] = data1; + X[t2] = data2; + end + + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/str_imm_fpsimd b/instructionAPI/ISA_ps/str_imm_fpsimd new file mode 100644 index 0000000000..9e449c69ef --- /dev/null +++ b/instructionAPI/ISA_ps/str_imm_fpsimd @@ -0,0 +1,38 @@ +##str_imm_fpsimd_execute +CheckFPAdvSIMDEnabled64(); + +bits(64) address; +bits(datasize) data; + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + data = V[t]; + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + V[t] = data; + end + +if wback then + if postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/str_imm_gen b/instructionAPI/ISA_ps/str_imm_gen new file mode 100644 index 0000000000..697b4a9a4f --- /dev/null +++ b/instructionAPI/ISA_ps/str_imm_gen @@ -0,0 +1,60 @@ +##str_imm_gen_execute +bits(64) address; +bits(datasize) data; +boolean wb_unknown = FALSE; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && wback && n == t && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && n == t && n != 31 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + else + data = X[t]; + end + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + if signed then + X[t] = SignExtend(data, regsize); + else + X[t] = ZeroExtend(data, regsize); + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/str_reg_fpsimd b/instructionAPI/ISA_ps/str_reg_fpsimd new file mode 100644 index 0000000000..1dafb55fd3 --- /dev/null +++ b/instructionAPI/ISA_ps/str_reg_fpsimd @@ -0,0 +1,39 @@ +##str_reg_fpsimd_execute +bits(64) offset = ExtendReg(m, extend_type, shift); +CheckFPAdvSIMDEnabled64(); + +bits(64) address; +bits(datasize) data; + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + data = V[t]; + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + V[t] = data; + end + +if wback then + if postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/str_reg_gen b/instructionAPI/ISA_ps/str_reg_gen new file mode 100644 index 0000000000..d90afd073d --- /dev/null +++ b/instructionAPI/ISA_ps/str_reg_gen @@ -0,0 +1,61 @@ +##str_reg_gen_execute +bits(64) offset = ExtendReg(m, extend_type, shift); +bits(64) address; +bits(datasize) data; +boolean wb_unknown = FALSE; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && wback && n == t && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && n == t && n != 31 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + else + data = X[t]; + end + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + if signed then + X[t] = SignExtend(data, regsize); + else + X[t] = ZeroExtend(data, regsize); + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/strb_imm b/instructionAPI/ISA_ps/strb_imm new file mode 100644 index 0000000000..5991ac260c --- /dev/null +++ b/instructionAPI/ISA_ps/strb_imm @@ -0,0 +1,60 @@ +##strb_imm_execute +bits(64) address; +bits(datasize) data; +boolean wb_unknown = FALSE; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && wback && n == t && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && n == t && n != 31 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + else + data = X[t]; + end + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + if signed then + X[t] = SignExtend(data, regsize); + else + X[t] = ZeroExtend(data, regsize); + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/strb_reg b/instructionAPI/ISA_ps/strb_reg new file mode 100644 index 0000000000..206fbcc2ab --- /dev/null +++ b/instructionAPI/ISA_ps/strb_reg @@ -0,0 +1,61 @@ +##strb_reg_execute +bits(64) offset = ExtendReg(m, extend_type, shift); +bits(64) address; +bits(datasize) data; +boolean wb_unknown = FALSE; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && wback && n == t && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && n == t && n != 31 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + else + data = X[t]; + end + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + if signed then + X[t] = SignExtend(data, regsize); + else + X[t] = ZeroExtend(data, regsize); + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/strh_imm b/instructionAPI/ISA_ps/strh_imm new file mode 100644 index 0000000000..96c0f2918a --- /dev/null +++ b/instructionAPI/ISA_ps/strh_imm @@ -0,0 +1,60 @@ +##strh_imm_execute +bits(64) address; +bits(datasize) data; +boolean wb_unknown = FALSE; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && wback && n == t && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && n == t && n != 31 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + else + data = X[t]; + end + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + if signed then + X[t] = SignExtend(data, regsize); + else + X[t] = ZeroExtend(data, regsize); + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/strh_reg b/instructionAPI/ISA_ps/strh_reg new file mode 100644 index 0000000000..a2fbaf7f47 --- /dev/null +++ b/instructionAPI/ISA_ps/strh_reg @@ -0,0 +1,61 @@ +##strh_reg_execute +bits(64) offset = ExtendReg(m, extend_type, shift); +bits(64) address; +bits(datasize) data; +boolean wb_unknown = FALSE; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && wback && n == t && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && n == t && n != 31 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + else + data = X[t]; + end + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + if signed then + X[t] = SignExtend(data, regsize); + else + X[t] = ZeroExtend(data, regsize); + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/sttr b/instructionAPI/ISA_ps/sttr new file mode 100644 index 0000000000..9683dc347f --- /dev/null +++ b/instructionAPI/ISA_ps/sttr @@ -0,0 +1,60 @@ +##sttr_execute +bits(64) address; +bits(datasize) data; +boolean wb_unknown = FALSE; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && wback && n == t && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && n == t && n != 31 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + else + data = X[t]; + end + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + if signed then + X[t] = SignExtend(data, regsize); + else + X[t] = ZeroExtend(data, regsize); + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/sttrb b/instructionAPI/ISA_ps/sttrb new file mode 100644 index 0000000000..660d0d038c --- /dev/null +++ b/instructionAPI/ISA_ps/sttrb @@ -0,0 +1,60 @@ +##sttrb_execute +bits(64) address; +bits(datasize) data; +boolean wb_unknown = FALSE; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && wback && n == t && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && n == t && n != 31 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + else + data = X[t]; + end + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + if signed then + X[t] = SignExtend(data, regsize); + else + X[t] = ZeroExtend(data, regsize); + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/sttrh b/instructionAPI/ISA_ps/sttrh new file mode 100644 index 0000000000..a32cc796d3 --- /dev/null +++ b/instructionAPI/ISA_ps/sttrh @@ -0,0 +1,60 @@ +##sttrh_execute +bits(64) address; +bits(datasize) data; +boolean wb_unknown = FALSE; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && wback && n == t && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && n == t && n != 31 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + else + data = X[t]; + end + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + if signed then + X[t] = SignExtend(data, regsize); + else + X[t] = ZeroExtend(data, regsize); + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/stur_fpsimd b/instructionAPI/ISA_ps/stur_fpsimd new file mode 100644 index 0000000000..f7437d1cb0 --- /dev/null +++ b/instructionAPI/ISA_ps/stur_fpsimd @@ -0,0 +1,38 @@ +##stur_fpsimd_execute +CheckFPAdvSIMDEnabled64(); + +bits(64) address; +bits(datasize) data; + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + data = V[t]; + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + V[t] = data; + end + +if wback then + if postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/stur_gen b/instructionAPI/ISA_ps/stur_gen new file mode 100644 index 0000000000..c53e5e4a4c --- /dev/null +++ b/instructionAPI/ISA_ps/stur_gen @@ -0,0 +1,60 @@ +##stur_gen_execute +bits(64) address; +bits(datasize) data; +boolean wb_unknown = FALSE; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && wback && n == t && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && n == t && n != 31 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + else + data = X[t]; + end + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + if signed then + X[t] = SignExtend(data, regsize); + else + X[t] = ZeroExtend(data, regsize); + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/sturb b/instructionAPI/ISA_ps/sturb new file mode 100644 index 0000000000..52f0be0f0e --- /dev/null +++ b/instructionAPI/ISA_ps/sturb @@ -0,0 +1,60 @@ +##sturb_execute +bits(64) address; +bits(datasize) data; +boolean wb_unknown = FALSE; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && wback && n == t && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && n == t && n != 31 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + else + data = X[t]; + end + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + if signed then + X[t] = SignExtend(data, regsize); + else + X[t] = ZeroExtend(data, regsize); + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/sturh b/instructionAPI/ISA_ps/sturh new file mode 100644 index 0000000000..18a64751dd --- /dev/null +++ b/instructionAPI/ISA_ps/sturh @@ -0,0 +1,60 @@ +##sturh_execute +bits(64) address; +bits(datasize) data; +boolean wb_unknown = FALSE; +boolean rt_unknown = FALSE; + +if memop == MemOp_LOAD && wback && n == t && n != 31 then + case c of +end + +if memop == MemOp_STORE && wback && n == t && n != 31 then + case c of +end + +if n == 31 then + address = SP[]; +else + address = X[n]; +end + +if ! postindex then + address = address + offset; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + else + data = X[t]; + end + Mem[address, datasize / 8, acctype] = data; + end + + when MemOp_LOAD + data = Mem[address, datasize / 8, acctype]; + if signed then + X[t] = SignExtend(data, regsize); + else + X[t] = ZeroExtend(data, regsize); + end + + end + when MemOp_PREFETCH + Prefetch(address, t<4:0>); + end + +if wback then + if wb_unknown then + address = bits(64) UNKNOWN; + elsif postindex then + address = address + offset; + end + if n == 31 then + SP[] = address; + else + X[n] = address; + end +end +@@ diff --git a/instructionAPI/ISA_ps/stxp b/instructionAPI/ISA_ps/stxp new file mode 100644 index 0000000000..f2893b514c --- /dev/null +++ b/instructionAPI/ISA_ps/stxp @@ -0,0 +1,94 @@ +##stxp_execute +bits(64) address; +bits(datasize) data; +constant integer dbytes = datasize / 8; +boolean rt_unknown = FALSE; +boolean rn_unknown = FALSE; + +if memop == MemOp_LOAD && pair && t == t2 then + case c of +end + +if memop == MemOp_STORE then + if s == t || (pair && s == t2) then + case c of + end + if s == n && n != 31 then + case c of + end + +end +if n == 31 then + address = SP[]; +elsif rn_unknown then + address = bits(64) UNKNOWN; +else + address = X[n]; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + elsif pair then + bits(datasize / 2) el1 = X[t]; + bits(datasize / 2) el2 = X[t2]; + data = if BigEndian() then el1 : el2 else el2 : el1; + else + end + data = X[t]; + end + + bit status = 1; + // Check whether the Exclusive Monitors are set to include the + // physical memory locations corresponding to virtual address + // range [address, address+dbytes-1]. + if AArch64.ExclusiveMonitorsPass(address, dbytes) then + // This atomic write will be rejected if it does not refer + // to the same physical locations after address translation. + Mem[address, dbytes, acctype] = data; + status = ExclusiveMonitorsStatus(); + end + X[s] = ZeroExtend(status, 32); + end + + when MemOp_LOAD + // Tell the Exclusive Monitors to record a sequence of one or more atomic + // memory reads from virtual address range [address, address+dbytes-1]. + // The Exclusive Monitor will only be set if all the reads are from the + // same dbytes-aligned physical address, to allow for the possibility of + // an atomicity break if the translation is changed between reads. + AArch64.SetExclusiveMonitors(address, dbytes); + end + + if pair then + // load exclusive pair + if rt_unknown then + X[t] = bits(datasize) UNKNOWN; + elsif elsize == 32 then + // 32-bit load exclusive pair (atomic) + data = Mem[address, dbytes, acctype]; + if BigEndian() then + X[t] = data; + X[t2] = data; + else + X[t] = data; + X[t2] = data; + else // elsize == 64 + end + // 64-bit load exclusive pair (not atomic), + // but must be 128-bit aligned + if address != Align(address, dbytes) then + iswrite = FALSE; + secondstage = FALSE; + AArch64.Abort(address, AArch64.AlignmentFault(acctype, iswrite, secondstage)); + end + X[t] = Mem[address + 0, 8, acctype]; + X[t2] = Mem[address + 8, 8, acctype]; + else + end + // load {acquire} {exclusive} single register + data = Mem[address, dbytes, acctype]; + X[t] = ZeroExtend(data, regsize); + end +@@ diff --git a/instructionAPI/ISA_ps/stxr b/instructionAPI/ISA_ps/stxr new file mode 100644 index 0000000000..23420d4675 --- /dev/null +++ b/instructionAPI/ISA_ps/stxr @@ -0,0 +1,94 @@ +##stxr_execute +bits(64) address; +bits(datasize) data; +constant integer dbytes = datasize / 8; +boolean rt_unknown = FALSE; +boolean rn_unknown = FALSE; + +if memop == MemOp_LOAD && pair && t == t2 then + case c of +end + +if memop == MemOp_STORE then + if s == t || (pair && s == t2) then + case c of + end + if s == n && n != 31 then + case c of + end + +end +if n == 31 then + address = SP[]; +elsif rn_unknown then + address = bits(64) UNKNOWN; +else + address = X[n]; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + elsif pair then + bits(datasize / 2) el1 = X[t]; + bits(datasize / 2) el2 = X[t2]; + data = if BigEndian() then el1 : el2 else el2 : el1; + else + end + data = X[t]; + end + + bit status = 1; + // Check whether the Exclusive Monitors are set to include the + // physical memory locations corresponding to virtual address + // range [address, address+dbytes-1]. + if AArch64.ExclusiveMonitorsPass(address, dbytes) then + // This atomic write will be rejected if it does not refer + // to the same physical locations after address translation. + Mem[address, dbytes, acctype] = data; + status = ExclusiveMonitorsStatus(); + end + X[s] = ZeroExtend(status, 32); + end + + when MemOp_LOAD + // Tell the Exclusive Monitors to record a sequence of one or more atomic + // memory reads from virtual address range [address, address+dbytes-1]. + // The Exclusive Monitor will only be set if all the reads are from the + // same dbytes-aligned physical address, to allow for the possibility of + // an atomicity break if the translation is changed between reads. + AArch64.SetExclusiveMonitors(address, dbytes); + end + + if pair then + // load exclusive pair + if rt_unknown then + X[t] = bits(datasize) UNKNOWN; + elsif elsize == 32 then + // 32-bit load exclusive pair (atomic) + data = Mem[address, dbytes, acctype]; + if BigEndian() then + X[t] = data; + X[t2] = data; + else + X[t] = data; + X[t2] = data; + else // elsize == 64 + end + // 64-bit load exclusive pair (not atomic), + // but must be 128-bit aligned + if address != Align(address, dbytes) then + iswrite = FALSE; + secondstage = FALSE; + AArch64.Abort(address, AArch64.AlignmentFault(acctype, iswrite, secondstage)); + end + X[t] = Mem[address + 0, 8, acctype]; + X[t2] = Mem[address + 8, 8, acctype]; + else + end + // load {acquire} {exclusive} single register + data = Mem[address, dbytes, acctype]; + X[t] = ZeroExtend(data, regsize); + end +@@ diff --git a/instructionAPI/ISA_ps/stxrb b/instructionAPI/ISA_ps/stxrb new file mode 100644 index 0000000000..d6324ac290 --- /dev/null +++ b/instructionAPI/ISA_ps/stxrb @@ -0,0 +1,94 @@ +##stxrb_execute +bits(64) address; +bits(datasize) data; +constant integer dbytes = datasize / 8; +boolean rt_unknown = FALSE; +boolean rn_unknown = FALSE; + +if memop == MemOp_LOAD && pair && t == t2 then + case c of +end + +if memop == MemOp_STORE then + if s == t || (pair && s == t2) then + case c of + end + if s == n && n != 31 then + case c of + end + +end +if n == 31 then + address = SP[]; +elsif rn_unknown then + address = bits(64) UNKNOWN; +else + address = X[n]; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + elsif pair then + bits(datasize / 2) el1 = X[t]; + bits(datasize / 2) el2 = X[t2]; + data = if BigEndian() then el1 : el2 else el2 : el1; + else + end + data = X[t]; + end + + bit status = 1; + // Check whether the Exclusive Monitors are set to include the + // physical memory locations corresponding to virtual address + // range [address, address+dbytes-1]. + if AArch64.ExclusiveMonitorsPass(address, dbytes) then + // This atomic write will be rejected if it does not refer + // to the same physical locations after address translation. + Mem[address, dbytes, acctype] = data; + status = ExclusiveMonitorsStatus(); + end + X[s] = ZeroExtend(status, 32); + end + + when MemOp_LOAD + // Tell the Exclusive Monitors to record a sequence of one or more atomic + // memory reads from virtual address range [address, address+dbytes-1]. + // The Exclusive Monitor will only be set if all the reads are from the + // same dbytes-aligned physical address, to allow for the possibility of + // an atomicity break if the translation is changed between reads. + AArch64.SetExclusiveMonitors(address, dbytes); + end + + if pair then + // load exclusive pair + if rt_unknown then + X[t] = bits(datasize) UNKNOWN; + elsif elsize == 32 then + // 32-bit load exclusive pair (atomic) + data = Mem[address, dbytes, acctype]; + if BigEndian() then + X[t] = data; + X[t2] = data; + else + X[t] = data; + X[t2] = data; + else // elsize == 64 + end + // 64-bit load exclusive pair (not atomic), + // but must be 128-bit aligned + if address != Align(address, dbytes) then + iswrite = FALSE; + secondstage = FALSE; + AArch64.Abort(address, AArch64.AlignmentFault(acctype, iswrite, secondstage)); + end + X[t] = Mem[address + 0, 8, acctype]; + X[t2] = Mem[address + 8, 8, acctype]; + else + end + // load {acquire} {exclusive} single register + data = Mem[address, dbytes, acctype]; + X[t] = ZeroExtend(data, regsize); + end +@@ diff --git a/instructionAPI/ISA_ps/stxrh b/instructionAPI/ISA_ps/stxrh new file mode 100644 index 0000000000..f58275dbdf --- /dev/null +++ b/instructionAPI/ISA_ps/stxrh @@ -0,0 +1,94 @@ +##stxrh_execute +bits(64) address; +bits(datasize) data; +constant integer dbytes = datasize / 8; +boolean rt_unknown = FALSE; +boolean rn_unknown = FALSE; + +if memop == MemOp_LOAD && pair && t == t2 then + case c of +end + +if memop == MemOp_STORE then + if s == t || (pair && s == t2) then + case c of + end + if s == n && n != 31 then + case c of + end + +end +if n == 31 then + address = SP[]; +elsif rn_unknown then + address = bits(64) UNKNOWN; +else + address = X[n]; +end + +case memop of + when MemOp_STORE + if rt_unknown then + data = bits(datasize) UNKNOWN; + elsif pair then + bits(datasize / 2) el1 = X[t]; + bits(datasize / 2) el2 = X[t2]; + data = if BigEndian() then el1 : el2 else el2 : el1; + else + end + data = X[t]; + end + + bit status = 1; + // Check whether the Exclusive Monitors are set to include the + // physical memory locations corresponding to virtual address + // range [address, address+dbytes-1]. + if AArch64.ExclusiveMonitorsPass(address, dbytes) then + // This atomic write will be rejected if it does not refer + // to the same physical locations after address translation. + Mem[address, dbytes, acctype] = data; + status = ExclusiveMonitorsStatus(); + end + X[s] = ZeroExtend(status, 32); + end + + when MemOp_LOAD + // Tell the Exclusive Monitors to record a sequence of one or more atomic + // memory reads from virtual address range [address, address+dbytes-1]. + // The Exclusive Monitor will only be set if all the reads are from the + // same dbytes-aligned physical address, to allow for the possibility of + // an atomicity break if the translation is changed between reads. + AArch64.SetExclusiveMonitors(address, dbytes); + end + + if pair then + // load exclusive pair + if rt_unknown then + X[t] = bits(datasize) UNKNOWN; + elsif elsize == 32 then + // 32-bit load exclusive pair (atomic) + data = Mem[address, dbytes, acctype]; + if BigEndian() then + X[t] = data; + X[t2] = data; + else + X[t] = data; + X[t2] = data; + else // elsize == 64 + end + // 64-bit load exclusive pair (not atomic), + // but must be 128-bit aligned + if address != Align(address, dbytes) then + iswrite = FALSE; + secondstage = FALSE; + AArch64.Abort(address, AArch64.AlignmentFault(acctype, iswrite, secondstage)); + end + X[t] = Mem[address + 0, 8, acctype]; + X[t2] = Mem[address + 8, 8, acctype]; + else + end + // load {acquire} {exclusive} single register + data = Mem[address, dbytes, acctype]; + X[t] = ZeroExtend(data, regsize); + end +@@ diff --git a/instructionAPI/ISA_ps/sub_addsub_ext b/instructionAPI/ISA_ps/sub_addsub_ext new file mode 100644 index 0000000000..1076193963 --- /dev/null +++ b/instructionAPI/ISA_ps/sub_addsub_ext @@ -0,0 +1,26 @@ +##sub_addsub_ext_execute +bits(datasize) result; +bits(datasize) operand1 = if n == 31 then SP[] else X[n]; +bits(datasize) operand2 = ExtendReg(m, extend_type, shift); +bits(4) nzcv; +bit carry_in; + +if sub_op then + operand2 = NOT(operand2); + carry_in = 1; +else + carry_in = 0; +end + +(result, nzcv) = AddWithCarry(operand1, operand2, carry_in); + +if setflags then + PSTATE. = nzcv; +end + +if d == 31 && !setflags then + SP[] = result; +else + X[d] = result; +end +@@ diff --git a/instructionAPI/ISA_ps/sub_addsub_imm b/instructionAPI/ISA_ps/sub_addsub_imm new file mode 100644 index 0000000000..1fe1dc27e6 --- /dev/null +++ b/instructionAPI/ISA_ps/sub_addsub_imm @@ -0,0 +1,26 @@ +##sub_addsub_imm_execute +bits(datasize) result; +bits(datasize) operand1 = if n == 31 then SP[] else X[n]; +bits(datasize) operand2 = imm; +bits(4) nzcv; +bit carry_in; + +if sub_op then + operand2 = NOT(operand2); + carry_in = 1; +else + carry_in = 0; +end + +(result, nzcv) = AddWithCarry(operand1, operand2, carry_in); + +if setflags then + PSTATE. = nzcv; +end + +if d == 31 && !setflags then + SP[] = result; +else + X[d] = result; +end +@@ diff --git a/instructionAPI/ISA_ps/sub_addsub_shift b/instructionAPI/ISA_ps/sub_addsub_shift new file mode 100644 index 0000000000..9647182b02 --- /dev/null +++ b/instructionAPI/ISA_ps/sub_addsub_shift @@ -0,0 +1,22 @@ +##sub_addsub_shift_execute +bits(datasize) result; +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount); +bits(4) nzcv; +bit carry_in; + +if sub_op then + operand2 = NOT(operand2); + carry_in = 1; +else + carry_in = 0; +end + +(result, nzcv) = AddWithCarry(operand1, operand2, carry_in); + +if setflags then + PSTATE. = nzcv; +end + +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sub_advsimd b/instructionAPI/ISA_ps/sub_advsimd new file mode 100644 index 0000000000..c82331b4fc --- /dev/null +++ b/instructionAPI/ISA_ps/sub_advsimd @@ -0,0 +1,19 @@ +##sub_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +bits(esize) element1; +bits(esize) element2; + +for e = 0 to elements-1 + element1 = Elem[operand1, e, esize]; + element2 = Elem[operand2, e, esize]; + if sub_op then + Elem[result, e, esize] = element1 - element2; + else + Elem[result, e, esize] = element1 + element2; + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/subhn_advsimd b/instructionAPI/ISA_ps/subhn_advsimd new file mode 100644 index 0000000000..830843cdb3 --- /dev/null +++ b/instructionAPI/ISA_ps/subhn_advsimd @@ -0,0 +1,23 @@ +##subhn_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(2*datasize) operand1 = V[n]; +bits(2*datasize) operand2 = V[m]; +bits(datasize) result; +integer round_const = if round then 1 << (esize - 1) else 0; +bits(2*esize) element1; +bits(2*esize) element2; +bits(2*esize) sum; + +for e = 0 to elements-1 + element1 = Elem[operand1, e, 2*esize]; + element2 = Elem[operand2, e, 2*esize]; + if sub_op then + sum = element1 - element2; + else + sum = element1 + element2; + end + sum = sum + round_const; + Elem[result, e, esize] = sum<2*esize-1:esize>; + +Vpart[d, part] = result; +@@ diff --git a/instructionAPI/ISA_ps/subs_addsub_ext b/instructionAPI/ISA_ps/subs_addsub_ext new file mode 100644 index 0000000000..07641e49e5 --- /dev/null +++ b/instructionAPI/ISA_ps/subs_addsub_ext @@ -0,0 +1,26 @@ +##subs_addsub_ext_execute +bits(datasize) result; +bits(datasize) operand1 = if n == 31 then SP[] else X[n]; +bits(datasize) operand2 = ExtendReg(m, extend_type, shift); +bits(4) nzcv; +bit carry_in; + +if sub_op then + operand2 = NOT(operand2); + carry_in = 1; +else + carry_in = 0; +end + +(result, nzcv) = AddWithCarry(operand1, operand2, carry_in); + +if setflags then + PSTATE. = nzcv; +end + +if d == 31 && !setflags then + SP[] = result; +else + X[d] = result; +end +@@ diff --git a/instructionAPI/ISA_ps/subs_addsub_imm b/instructionAPI/ISA_ps/subs_addsub_imm new file mode 100644 index 0000000000..25dcbbd1fe --- /dev/null +++ b/instructionAPI/ISA_ps/subs_addsub_imm @@ -0,0 +1,26 @@ +##subs_addsub_imm_execute +bits(datasize) result; +bits(datasize) operand1 = if n == 31 then SP[] else X[n]; +bits(datasize) operand2 = imm; +bits(4) nzcv; +bit carry_in; + +if sub_op then + operand2 = NOT(operand2); + carry_in = 1; +else + carry_in = 0; +end + +(result, nzcv) = AddWithCarry(operand1, operand2, carry_in); + +if setflags then + PSTATE. = nzcv; +end + +if d == 31 && !setflags then + SP[] = result; +else + X[d] = result; +end +@@ diff --git a/instructionAPI/ISA_ps/subs_addsub_shift b/instructionAPI/ISA_ps/subs_addsub_shift new file mode 100644 index 0000000000..7f87500347 --- /dev/null +++ b/instructionAPI/ISA_ps/subs_addsub_shift @@ -0,0 +1,22 @@ +##subs_addsub_shift_execute +bits(datasize) result; +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount); +bits(4) nzcv; +bit carry_in; + +if sub_op then + operand2 = NOT(operand2); + carry_in = 1; +else + carry_in = 0; +end + +(result, nzcv) = AddWithCarry(operand1, operand2, carry_in); + +if setflags then + PSTATE. = nzcv; +end + +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/suqadd_advsimd b/instructionAPI/ISA_ps/suqadd_advsimd new file mode 100644 index 0000000000..a815bb271f --- /dev/null +++ b/instructionAPI/ISA_ps/suqadd_advsimd @@ -0,0 +1,17 @@ +##suqadd_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; + +bits(datasize) operand2 = V[d]; +integer op1; +integer op2; +boolean sat; + +for e = 0 to elements-1 + op1 = Int(Elem[operand, e, esize], !unsigned); + op2 = Int(Elem[operand2, e, esize], unsigned); + (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned); + if sat then FPSR.QC = 1; +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/svc b/instructionAPI/ISA_ps/svc new file mode 100644 index 0000000000..8149115bf9 --- /dev/null +++ b/instructionAPI/ISA_ps/svc @@ -0,0 +1,3 @@ +##svc_execute +AArch64.CallSupervisor(imm); +@@ diff --git a/instructionAPI/ISA_ps/sxtb_sbfm b/instructionAPI/ISA_ps/sxtb_sbfm new file mode 100644 index 0000000000..acf5641030 --- /dev/null +++ b/instructionAPI/ISA_ps/sxtb_sbfm @@ -0,0 +1,13 @@ +##sxtb_sbfm_execute +bits(datasize) dst = if inzero then Zeros(64) else X[d]; +bits(datasize) src = X[n]; + +// perform bitfield move on low bits +bits(datasize) bot = (dst AND NOT(wmask)) OR (ROR(src, R) AND wmask); + +// determine extension bits (sign, zero or dest register) +bits(datasize) top = if extend then Replicate(src) else dst; + +// combine extension bits and result bits +X[d] = (top AND NOT(tmask)) OR (bot AND tmask); +@@ diff --git a/instructionAPI/ISA_ps/sxth_sbfm b/instructionAPI/ISA_ps/sxth_sbfm new file mode 100644 index 0000000000..6dc57bd9c2 --- /dev/null +++ b/instructionAPI/ISA_ps/sxth_sbfm @@ -0,0 +1,13 @@ +##sxth_sbfm_execute +bits(datasize) dst = if inzero then Zeros(64) else X[d]; +bits(datasize) src = X[n]; + +// perform bitfield move on low bits +bits(datasize) bot = (dst AND NOT(wmask)) OR (ROR(src, R) AND wmask); + +// determine extension bits (sign, zero or dest register) +bits(datasize) top = if extend then Replicate(src) else dst; + +// combine extension bits and result bits +X[d] = (top AND NOT(tmask)) OR (bot AND tmask); +@@ diff --git a/instructionAPI/ISA_ps/sxtl_sshll_advsimd b/instructionAPI/ISA_ps/sxtl_sshll_advsimd new file mode 100644 index 0000000000..f05c2ecc33 --- /dev/null +++ b/instructionAPI/ISA_ps/sxtl_sshll_advsimd @@ -0,0 +1,12 @@ +##sxtl_sshll_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = Vpart[n, part]; +bits(datasize*2) result; +integer element; + +for e = 0 to elements-1 + element = Int(Elem[operand, e, esize], unsigned) << shift; + Elem[result, e, 2*esize] = element<2*esize-1:0>; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/sxtw_sbfm b/instructionAPI/ISA_ps/sxtw_sbfm new file mode 100644 index 0000000000..b22b03f521 --- /dev/null +++ b/instructionAPI/ISA_ps/sxtw_sbfm @@ -0,0 +1,13 @@ +##sxtw_sbfm_execute +bits(datasize) dst = if inzero then Zeros(64) else X[d]; +bits(datasize) src = X[n]; + +// perform bitfield move on low bits +bits(datasize) bot = (dst AND NOT(wmask)) OR (ROR(src, R) AND wmask); + +// determine extension bits (sign, zero or dest register) +bits(datasize) top = if extend then Replicate(src) else dst; + +// combine extension bits and result bits +X[d] = (top AND NOT(tmask)) OR (bot AND tmask); +@@ diff --git a/instructionAPI/ISA_ps/sys b/instructionAPI/ISA_ps/sys new file mode 100644 index 0000000000..d7d7b2234a --- /dev/null +++ b/instructionAPI/ISA_ps/sys @@ -0,0 +1,6 @@ +##sys_execute +if has_result then + X[t] = SysOp_R(sys_op0, sys_op1, sys_crn, sys_crm, sys_op2); +else + SysOp_W(sys_op0, sys_op1, sys_crn, sys_crm, sys_op2, X[t]); +@@ diff --git a/instructionAPI/ISA_ps/sysl b/instructionAPI/ISA_ps/sysl new file mode 100644 index 0000000000..42013a269f --- /dev/null +++ b/instructionAPI/ISA_ps/sysl @@ -0,0 +1,7 @@ +##sysl_execute +if has_result then + X[t] = SysOp_R(sys_op0, sys_op1, sys_crn, sys_crm, sys_op2); +else + SysOp_W(sys_op0, sys_op1, sys_crn, sys_crm, sys_op2, X[t]); +end +@@ diff --git a/instructionAPI/ISA_ps/tbl_advsimd b/instructionAPI/ISA_ps/tbl_advsimd new file mode 100644 index 0000000000..dfa44039da --- /dev/null +++ b/instructionAPI/ISA_ps/tbl_advsimd @@ -0,0 +1,22 @@ +##tbl_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) indices = V[m]; +bits(128*regs) table = Zeros(64); +bits(datasize) result; +integer index; +integer i; + +// Create table from registers +for i = 0 to regs - 1 + table<128*i+127:128*i> = V[n]; + n = (n + 1) MOD 32; + +result = if is_tbl then Zeros(64) else V[d]; +for i = 0 to elements - 1 + index = UInt(Elem[indices, i, 8]); + if index < 16 * regs then + Elem[result, i, 8] = Elem[table, index, 8]; + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/tbnz b/instructionAPI/ISA_ps/tbnz new file mode 100644 index 0000000000..26e6ac7469 --- /dev/null +++ b/instructionAPI/ISA_ps/tbnz @@ -0,0 +1,7 @@ +##tbnz_execute +bits(datasize) operand = X[t]; + +if operand == bit_val then + BranchTo(PC[] + offset, BranchType_JMP); +end +@@ diff --git a/instructionAPI/ISA_ps/tbx_advsimd b/instructionAPI/ISA_ps/tbx_advsimd new file mode 100644 index 0000000000..df1b798505 --- /dev/null +++ b/instructionAPI/ISA_ps/tbx_advsimd @@ -0,0 +1,22 @@ +##tbx_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) indices = V[m]; +bits(128*regs) table = Zeros(64); +bits(datasize) result; +integer index; +integer i; + +// Create table from registers +for i = 0 to regs - 1 + table<128*i+127:128*i> = V[n]; + n = (n + 1) MOD 32; + +result = if is_tbl then Zeros(64) else V[d]; +for i = 0 to elements - 1 + index = UInt(Elem[indices, i, 8]); + if index < 16 * regs then + Elem[result, i, 8] = Elem[table, index, 8]; + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/tbz b/instructionAPI/ISA_ps/tbz new file mode 100644 index 0000000000..2258d0cf6d --- /dev/null +++ b/instructionAPI/ISA_ps/tbz @@ -0,0 +1,7 @@ +##tbz_execute +bits(datasize) operand = X[t]; + +if operand == bit_val then + BranchTo(PC[] + offset, BranchType_JMP); +end +@@ diff --git a/instructionAPI/ISA_ps/temp.py b/instructionAPI/ISA_ps/temp.py new file mode 100644 index 0000000000..b83b4d9df3 --- /dev/null +++ b/instructionAPI/ISA_ps/temp.py @@ -0,0 +1,12 @@ +import os, sys +import re +d = os.listdir(".") +for f in d: + fdata = "" + with open(f) as curfile: + fdata = curfile.read() + fdata = re.sub(r"/", "/", fdata) + o = open(f, "w") + o.write(fdata) + o.close() + diff --git a/instructionAPI/ISA_ps/tlbi_sys b/instructionAPI/ISA_ps/tlbi_sys new file mode 100644 index 0000000000..a79b3b1ea3 --- /dev/null +++ b/instructionAPI/ISA_ps/tlbi_sys @@ -0,0 +1,7 @@ +##tlbi_sys_execute +if has_result then + X[t] = SysOp_R(sys_op0, sys_op1, sys_crn, sys_crm, sys_op2); +else + SysOp_W(sys_op0, sys_op1, sys_crn, sys_crm, sys_op2, X[t]); +end +@@ diff --git a/instructionAPI/ISA_ps/trn1_advsimd b/instructionAPI/ISA_ps/trn1_advsimd new file mode 100644 index 0000000000..4c819c42ac --- /dev/null +++ b/instructionAPI/ISA_ps/trn1_advsimd @@ -0,0 +1,13 @@ +##trn1_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +integer p; + +for p = 0 to pairs-1 + Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize]; + Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize]; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/trn2_advsimd b/instructionAPI/ISA_ps/trn2_advsimd new file mode 100644 index 0000000000..83f2f7f629 --- /dev/null +++ b/instructionAPI/ISA_ps/trn2_advsimd @@ -0,0 +1,13 @@ +##trn2_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +integer p; + +for p = 0 to pairs-1 + Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize]; + Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize]; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/tst_ands_log_imm b/instructionAPI/ISA_ps/tst_ands_log_imm new file mode 100644 index 0000000000..d68e9fbc55 --- /dev/null +++ b/instructionAPI/ISA_ps/tst_ands_log_imm @@ -0,0 +1,23 @@ +##tst_ands_log_imm_execute +bits(datasize) result; +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = imm; + +case op of + when LogicalOp_AND result = operand1 AND operand2; + end + when LogicalOp_ORR result = operand1 OR operand2; + end + when LogicalOp_EOR result = operand1 EOR operand2; + end + +if setflags then + PSTATE. = result:IsZeroBit(result):00; +end + +if d == 31 && !setflags then + SP[] = result; +else + X[d] = result; +end +@@ diff --git a/instructionAPI/ISA_ps/tst_ands_log_shift b/instructionAPI/ISA_ps/tst_ands_log_shift new file mode 100644 index 0000000000..53a4b9e375 --- /dev/null +++ b/instructionAPI/ISA_ps/tst_ands_log_shift @@ -0,0 +1,21 @@ +##tst_ands_log_shift_execute +bits(datasize) result; +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount); + +if invert then operand2 = NOT(operand2) end; + +case op of + when LogicalOp_AND result = operand1 AND operand2; + end + when LogicalOp_ORR result = operand1 OR operand2; + end + when LogicalOp_EOR result = operand1 EOR operand2; + end + +if setflags then + PSTATE. = result:IsZeroBit(result):00; +end + +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/uaba_advsimd b/instructionAPI/ISA_ps/uaba_advsimd new file mode 100644 index 0000000000..c3c2c40ff8 --- /dev/null +++ b/instructionAPI/ISA_ps/uaba_advsimd @@ -0,0 +1,17 @@ +##uaba_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +integer element1; +integer element2; +bits(esize) absdiff; + +result = if accumulate then V[d] else Zeros(64); +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + absdiff = Abs(element1 - element2); + Elem[result, e, esize] = Elem[result, e, esize] + absdiff; +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/uabal_advsimd b/instructionAPI/ISA_ps/uabal_advsimd new file mode 100644 index 0000000000..334125896b --- /dev/null +++ b/instructionAPI/ISA_ps/uabal_advsimd @@ -0,0 +1,17 @@ +##uabal_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = Vpart[n, part]; +bits(datasize) operand2 = Vpart[m, part]; +bits(2*datasize) result; +integer element1; +integer element2; +bits(2*esize) absdiff; + +result = if accumulate then V[d] else Zeros(64); +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + absdiff = Abs(element1 - element2)<2*esize-1:0>; + Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff; +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/uabd_advsimd b/instructionAPI/ISA_ps/uabd_advsimd new file mode 100644 index 0000000000..9e96577c80 --- /dev/null +++ b/instructionAPI/ISA_ps/uabd_advsimd @@ -0,0 +1,17 @@ +##uabd_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +integer element1; +integer element2; +bits(esize) absdiff; + +result = if accumulate then V[d] else Zeros(64); +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + absdiff = Abs(element1 - element2); + Elem[result, e, esize] = Elem[result, e, esize] + absdiff; +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/uabdl_advsimd b/instructionAPI/ISA_ps/uabdl_advsimd new file mode 100644 index 0000000000..d1f4e72cf7 --- /dev/null +++ b/instructionAPI/ISA_ps/uabdl_advsimd @@ -0,0 +1,17 @@ +##uabdl_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = Vpart[n, part]; +bits(datasize) operand2 = Vpart[m, part]; +bits(2*datasize) result; +integer element1; +integer element2; +bits(2*esize) absdiff; + +result = if accumulate then V[d] else Zeros(64); +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + absdiff = Abs(element1 - element2)<2*esize-1:0>; + Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff; +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/uadalp_advsimd b/instructionAPI/ISA_ps/uadalp_advsimd new file mode 100644 index 0000000000..934464797b --- /dev/null +++ b/instructionAPI/ISA_ps/uadalp_advsimd @@ -0,0 +1,18 @@ +##uadalp_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; + +bits(2*esize) sum; +integer op1; +integer op2; + +result = if acc then V[d] else Zeros(64); +for e = 0 to elements-1 + op1 = Int(Elem[operand, 2*e+0, esize], unsigned); + op2 = Int(Elem[operand, 2*e+1, esize], unsigned); + sum = (op1 + op2)<2*esize-1:0>; + Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/uaddl_advsimd b/instructionAPI/ISA_ps/uaddl_advsimd new file mode 100644 index 0000000000..c42a0bf1be --- /dev/null +++ b/instructionAPI/ISA_ps/uaddl_advsimd @@ -0,0 +1,21 @@ +##uaddl_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = Vpart[n, part]; +bits(datasize) operand2 = Vpart[m, part]; +bits(2*datasize) result; +integer element1; +integer element2; +integer sum; + +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + if sub_op then + sum = element1 - element2; + else + sum = element1 + element2; + end + Elem[result, e, 2*esize] = sum<2*esize-1:0>; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/uaddlp_advsimd b/instructionAPI/ISA_ps/uaddlp_advsimd new file mode 100644 index 0000000000..8504b175bf --- /dev/null +++ b/instructionAPI/ISA_ps/uaddlp_advsimd @@ -0,0 +1,18 @@ +##uaddlp_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; + +bits(2*esize) sum; +integer op1; +integer op2; + +result = if acc then V[d] else Zeros(64); +for e = 0 to elements-1 + op1 = Int(Elem[operand, 2*e+0, esize], unsigned); + op2 = Int(Elem[operand, 2*e+1, esize], unsigned); + sum = (op1 + op2)<2*esize-1:0>; + Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/uaddlv_advsimd b/instructionAPI/ISA_ps/uaddlv_advsimd new file mode 100644 index 0000000000..12670dd8d9 --- /dev/null +++ b/instructionAPI/ISA_ps/uaddlv_advsimd @@ -0,0 +1,11 @@ +##uaddlv_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +integer sum; + +sum = Int(Elem[operand, 0, esize], unsigned); +for e = 1 to elements-1 + sum = sum + Int(Elem[operand, e, esize], unsigned); + +V[d] = sum<2*esize-1:0>; +@@ diff --git a/instructionAPI/ISA_ps/uaddw_advsimd b/instructionAPI/ISA_ps/uaddw_advsimd new file mode 100644 index 0000000000..ef691224c0 --- /dev/null +++ b/instructionAPI/ISA_ps/uaddw_advsimd @@ -0,0 +1,21 @@ +##uaddw_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(2*datasize) operand1 = V[n]; +bits(datasize) operand2 = Vpart[m, part]; +bits(2*datasize) result; +integer element1; +integer element2; +integer sum; + +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, 2*esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + if sub_op then + sum = element1 - element2; + else + sum = element1 + element2; + end + Elem[result, e, 2*esize] = sum<2*esize-1:0>; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/ubfiz_ubfm b/instructionAPI/ISA_ps/ubfiz_ubfm new file mode 100644 index 0000000000..a9ea8b60db --- /dev/null +++ b/instructionAPI/ISA_ps/ubfiz_ubfm @@ -0,0 +1,13 @@ +##ubfiz_ubfm_execute +bits(datasize) dst = if inzero then Zeros(64) else X[d]; +bits(datasize) src = X[n]; + +// perform bitfield move on low bits +bits(datasize) bot = (dst AND NOT(wmask)) OR (ROR(src, R) AND wmask); + +// determine extension bits (sign, zero or dest register) +bits(datasize) top = if extend then Replicate(src) else dst; + +// combine extension bits and result bits +X[d] = (top AND NOT(tmask)) OR (bot AND tmask); +@@ diff --git a/instructionAPI/ISA_ps/ubfm b/instructionAPI/ISA_ps/ubfm new file mode 100644 index 0000000000..56cb6c7c58 --- /dev/null +++ b/instructionAPI/ISA_ps/ubfm @@ -0,0 +1,13 @@ +##ubfm_execute +bits(datasize) dst = if inzero then Zeros(64) else X[d]; +bits(datasize) src = X[n]; + +// perform bitfield move on low bits +bits(datasize) bot = (dst AND NOT(wmask)) OR (ROR(src, R) AND wmask); + +// determine extension bits (sign, zero or dest register) +bits(datasize) top = if extend then Replicate(src) else dst; + +// combine extension bits and result bits +X[d] = (top AND NOT(tmask)) OR (bot AND tmask); +@@ diff --git a/instructionAPI/ISA_ps/ubfx_ubfm b/instructionAPI/ISA_ps/ubfx_ubfm new file mode 100644 index 0000000000..170a1ade0c --- /dev/null +++ b/instructionAPI/ISA_ps/ubfx_ubfm @@ -0,0 +1,13 @@ +##ubfx_ubfm_execute +bits(datasize) dst = if inzero then Zeros(64) else X[d]; +bits(datasize) src = X[n]; + +// perform bitfield move on low bits +bits(datasize) bot = (dst AND NOT(wmask)) OR (ROR(src, R) AND wmask); + +// determine extension bits (sign, zero or dest register) +bits(datasize) top = if extend then Replicate(src) else dst; + +// combine extension bits and result bits +X[d] = (top AND NOT(tmask)) OR (bot AND tmask); +@@ diff --git a/instructionAPI/ISA_ps/ucvtf_advsimd_fix b/instructionAPI/ISA_ps/ucvtf_advsimd_fix new file mode 100644 index 0000000000..cc5ae484e1 --- /dev/null +++ b/instructionAPI/ISA_ps/ucvtf_advsimd_fix @@ -0,0 +1,12 @@ +##ucvtf_advsimd_fix_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +bits(esize) element; + +for e = 0 to elements-1 + element = Elem[operand, e, esize]; + Elem[result, e, esize] = FixedToFP(element, fracbits, unsigned, FPCR, rounding); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/ucvtf_advsimd_int b/instructionAPI/ISA_ps/ucvtf_advsimd_int new file mode 100644 index 0000000000..16f8343745 --- /dev/null +++ b/instructionAPI/ISA_ps/ucvtf_advsimd_int @@ -0,0 +1,13 @@ +##ucvtf_advsimd_int_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +FPRounding rounding = FPRoundingMode(FPCR); +bits(esize) element; + +for e = 0 to elements-1 + element = Elem[operand, e, esize]; + Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/ucvtf_float_fix b/instructionAPI/ISA_ps/ucvtf_float_fix new file mode 100644 index 0000000000..fbe9c674d7 --- /dev/null +++ b/instructionAPI/ISA_ps/ucvtf_float_fix @@ -0,0 +1,18 @@ +##ucvtf_float_fix_execute +CheckFPAdvSIMDEnabled64(); + +bits(fltsize) fltval; +bits(intsize) intval; + +case op of + when FPConvOp_CVT_FtoI + fltval = V[n]; + intval = FPToFixed(fltval, fracbits, unsigned, FPCR, rounding); + X[d] = intval; + end + when FPConvOp_CVT_ItoF + intval = X[n]; + fltval = FixedToFP(intval, fracbits, unsigned, FPCR, rounding); + V[d] = fltval; + end +@@ diff --git a/instructionAPI/ISA_ps/ucvtf_float_int b/instructionAPI/ISA_ps/ucvtf_float_int new file mode 100644 index 0000000000..cebe3fe9a8 --- /dev/null +++ b/instructionAPI/ISA_ps/ucvtf_float_int @@ -0,0 +1,26 @@ +##ucvtf_float_int_execute +CheckFPAdvSIMDEnabled64(); + +bits(fltsize) fltval; +bits(intsize) intval; + +case op of + when FPConvOp_CVT_FtoI + fltval = V[n]; + intval = FPToFixed(fltval, 0, unsigned, FPCR, rounding); + X[d] = intval; + end + when FPConvOp_CVT_ItoF + intval = X[n]; + fltval = FixedToFP(intval, 0, unsigned, FPCR, rounding); + V[d] = fltval; + end + when FPConvOp_MOV_FtoI + intval = Vpart[n,part]; + X[d] = intval; + end + when FPConvOp_MOV_ItoF + intval = X[n]; + Vpart[d,part] = intval; + end +@@ diff --git a/instructionAPI/ISA_ps/udiv b/instructionAPI/ISA_ps/udiv new file mode 100644 index 0000000000..0fc17df1cd --- /dev/null +++ b/instructionAPI/ISA_ps/udiv @@ -0,0 +1,13 @@ +##udiv_execute +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = X[m]; +integer result; + +if IsZero(operand2) then + result = 0; +else + result = RoundTowardsZero(Int(operand1, true) / Int(operand2, true)); +end + +X[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/uhadd_advsimd b/instructionAPI/ISA_ps/uhadd_advsimd new file mode 100644 index 0000000000..294c337d25 --- /dev/null +++ b/instructionAPI/ISA_ps/uhadd_advsimd @@ -0,0 +1,17 @@ +##uhadd_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +integer element1; +integer element2; +integer sum; + +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + sum = element1 + element2; + Elem[result, e, esize] = sum; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/uhsub_advsimd b/instructionAPI/ISA_ps/uhsub_advsimd new file mode 100644 index 0000000000..4ff36b0528 --- /dev/null +++ b/instructionAPI/ISA_ps/uhsub_advsimd @@ -0,0 +1,17 @@ +##uhsub_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +integer element1; +integer element2; +integer diff; + +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + diff = element1 - element2; + Elem[result, e, esize] = diff; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/umaddl b/instructionAPI/ISA_ps/umaddl new file mode 100644 index 0000000000..70f2e5e2f9 --- /dev/null +++ b/instructionAPI/ISA_ps/umaddl @@ -0,0 +1,15 @@ +##umaddl_execute +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = X[m]; +bits(destsize) operand3 = X[a]; + +integer result; + +if sub_op then + result = Int(operand3, true) - (Int(operand1, true) * Int(operand2, true)); +else + result = Int(operand3, true) + (Int(operand1, true) * Int(operand2, true)); +end + +X[d] = result<63:0>; +@@ diff --git a/instructionAPI/ISA_ps/umax_advsimd b/instructionAPI/ISA_ps/umax_advsimd new file mode 100644 index 0000000000..72a8e7b411 --- /dev/null +++ b/instructionAPI/ISA_ps/umax_advsimd @@ -0,0 +1,17 @@ +##umax_advsimd_ex/u/s/s/ssunny/dev-home/dyninst/dyninst-code/instructionAPI/ISA_ps/msubecute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +integer element1; +integer element2; +integer maxmin; + +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + maxmin = if minimum then Min(element1, element2) else Max(element1, element2); + Elem[result, e, esize] = maxmin; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/umaxp_advsimd b/instructionAPI/ISA_ps/umaxp_advsimd new file mode 100644 index 0000000000..77f41bb011 --- /dev/null +++ b/instructionAPI/ISA_ps/umaxp_advsimd @@ -0,0 +1,18 @@ +##umaxp_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +bits(2*datasize) concat = operand2:operand1; +integer element1; +integer element2; +integer maxmin; + +for e = 0 to elements-1 + element1 = Int(Elem[concat, 2*e, esize], unsigned); + element2 = Int(Elem[concat, (2*e)+1, esize], unsigned); + maxmin = if minimum then Min(element1, element2) else Max(element1, element2); + Elem[result, e, esize] = maxmin; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/umaxv_advsimd b/instructionAPI/ISA_ps/umaxv_advsimd new file mode 100644 index 0000000000..e22b4d2927 --- /dev/null +++ b/instructionAPI/ISA_ps/umaxv_advsimd @@ -0,0 +1,13 @@ +##umaxv_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +integer maxmin; +integer element; + +maxmin = Int(Elem[operand, 0, esize], unsigned); +for e = 1 to elements-1 + element = Int(Elem[operand, e, esize], unsigned); + maxmin = if min then Min(maxmin, element) else Max(maxmin, element); + +V[d] = maxmin; +@@ diff --git a/instructionAPI/ISA_ps/umin_advsimd b/instructionAPI/ISA_ps/umin_advsimd new file mode 100644 index 0000000000..b0c5e755e8 --- /dev/null +++ b/instructionAPI/ISA_ps/umin_advsimd @@ -0,0 +1,17 @@ +##umin_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +integer element1; +integer element2; +integer maxmin; + +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + maxmin = if minimum then Min(element1, element2) else Max(element1, element2); + Elem[result, e, esize] = maxmin; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/uminp_advsimd b/instructionAPI/ISA_ps/uminp_advsimd new file mode 100644 index 0000000000..bbb0489292 --- /dev/null +++ b/instructionAPI/ISA_ps/uminp_advsimd @@ -0,0 +1,18 @@ +##uminp_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +bits(2*datasize) concat = operand2:operand1; +integer element1; +integer element2; +integer maxmin; + +for e = 0 to elements-1 + element1 = Int(Elem[concat, 2*e, esize], unsigned); + element2 = Int(Elem[concat, (2*e)+1, esize], unsigned); + maxmin = if minimum then Min(element1, element2) else Max(element1, element2); + Elem[result, e, esize] = maxmin; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/uminv_advsimd b/instructionAPI/ISA_ps/uminv_advsimd new file mode 100644 index 0000000000..946cdbd863 --- /dev/null +++ b/instructionAPI/ISA_ps/uminv_advsimd @@ -0,0 +1,13 @@ +##uminv_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +integer maxmin; +integer element; + +maxmin = Int(Elem[operand, 0, esize], unsigned); +for e = 1 to elements-1 + element = Int(Elem[operand, e, esize], unsigned); + maxmin = if min then Min(maxmin, element) else Max(maxmin, element); + +V[d] = maxmin; +@@ diff --git a/instructionAPI/ISA_ps/umlal_advsimd_elt b/instructionAPI/ISA_ps/umlal_advsimd_elt new file mode 100644 index 0000000000..09c585ff33 --- /dev/null +++ b/instructionAPI/ISA_ps/umlal_advsimd_elt @@ -0,0 +1,22 @@ +##umlal_advsimd_elt_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = Vpart[n, part]; +bits(idxdsize) operand2 = V[m]; +bits(2*datasize) operand3 = V[d]; +bits(2*datasize) result; +integer element1; +integer element2; +bits(2*esize) product; + +element2 = Int(Elem[operand2, index, esize], unsigned); +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + product = (element1 * element2)<2*esize-1:0>; + if sub_op then + Elem[result, e, 2*esize] = Elem[operand3, e, 2*esize] - product; + else + Elem[result, e, 2*esize] = Elem[operand3, e, 2*esize] + product; + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/umlal_advsimd_vec b/instructionAPI/ISA_ps/umlal_advsimd_vec new file mode 100644 index 0000000000..64c445e2a2 --- /dev/null +++ b/instructionAPI/ISA_ps/umlal_advsimd_vec @@ -0,0 +1,24 @@ +##umlal_advsimd_vec_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = Vpart[n, part]; +bits(datasize) operand2 = Vpart[m, part]; +bits(2*datasize) operand3 = V[d]; +bits(2*datasize) result; +integer element1; +integer element2; +bits(2*esize) product; +bits(2*esize) accum; + +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + product = (element1 * element2)<2*esize-1:0>; + if sub_op then + accum = Elem[operand3, e, 2*esize] - product; + else + accum = Elem[operand3, e, 2*esize] + product; + end + Elem[result, e, 2*esize] = accum; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/umlsl_advsimd_elt b/instructionAPI/ISA_ps/umlsl_advsimd_elt new file mode 100644 index 0000000000..c8150c2b31 --- /dev/null +++ b/instructionAPI/ISA_ps/umlsl_advsimd_elt @@ -0,0 +1,22 @@ +##umlsl_advsimd_elt_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = Vpart[n, part]; +bits(idxdsize) operand2 = V[m]; +bits(2*datasize) operand3 = V[d]; +bits(2*datasize) result; +integer element1; +integer element2; +bits(2*esize) product; + +element2 = Int(Elem[operand2, index, esize], unsigned); +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + product = (element1 * element2)<2*esize-1:0>; + if sub_op then + Elem[result, e, 2*esize] = Elem[operand3, e, 2*esize] - product; + else + Elem[result, e, 2*esize] = Elem[operand3, e, 2*esize] + product; + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/umlsl_advsimd_vec b/instructionAPI/ISA_ps/umlsl_advsimd_vec new file mode 100644 index 0000000000..737ee4f5dc --- /dev/null +++ b/instructionAPI/ISA_ps/umlsl_advsimd_vec @@ -0,0 +1,24 @@ +##umlsl_advsimd_vec_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = Vpart[n, part]; +bits(datasize) operand2 = Vpart[m, part]; +bits(2*datasize) operand3 = V[d]; +bits(2*datasize) result; +integer element1; +integer element2; +bits(2*esize) product; +bits(2*esize) accum; + +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + product = (element1 * element2)<2*esize-1:0>; + if sub_op then + accum = Elem[operand3, e, 2*esize] - product; + else + accum = Elem[operand3, e, 2*esize] + product; + end + Elem[result, e, 2*esize] = accum; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/umnegl_umsubl b/instructionAPI/ISA_ps/umnegl_umsubl new file mode 100644 index 0000000000..91d396a2f2 --- /dev/null +++ b/instructionAPI/ISA_ps/umnegl_umsubl @@ -0,0 +1,15 @@ +##umnegl_umsubl_execute +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = X[m]; +bits(destsize) operand3 = X[a]; + +integer result; + +if sub_op then + result = Int(operand3, true) - (Int(operand1, true) * Int(operand2, true)); +else + result = Int(operand3, true) + (Int(operand1, true) * Int(operand2, true)); +end + +X[d] = result<63:0>; +@@ diff --git a/instructionAPI/ISA_ps/umov_advsimd b/instructionAPI/ISA_ps/umov_advsimd new file mode 100644 index 0000000000..b6f77ff87b --- /dev/null +++ b/instructionAPI/ISA_ps/umov_advsimd @@ -0,0 +1,6 @@ +##umov_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(idxdsize) operand = V[n]; + +X[d] = ZeroExtend(Elem[operand, index, esize], datasize); +@@ diff --git a/instructionAPI/ISA_ps/umsubl b/instructionAPI/ISA_ps/umsubl new file mode 100644 index 0000000000..b642591a54 --- /dev/null +++ b/instructionAPI/ISA_ps/umsubl @@ -0,0 +1,15 @@ +##umsubl_execute +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = X[m]; +bits(destsize) operand3 = X[a]; + +integer result; + +if sub_op then + result = Int(operand3, true) - (Int(operand1, true) * Int(operand2, true)); +else + result = Int(operand3, true) + (Int(operand1, true) * Int(operand2, true)); +end + +X[d] = result<63:0>; +@@ diff --git a/instructionAPI/ISA_ps/umulh b/instructionAPI/ISA_ps/umulh new file mode 100644 index 0000000000..abb7fac562 --- /dev/null +++ b/instructionAPI/ISA_ps/umulh @@ -0,0 +1,10 @@ +##umulh_execute +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = X[m]; + +integer result; + +result = Int(operand1, true) * Int(operand2, true); + +X[d] = result<127:64>; +@@ diff --git a/instructionAPI/ISA_ps/umull_advsimd_elt b/instructionAPI/ISA_ps/umull_advsimd_elt new file mode 100644 index 0000000000..d42dca8f0a --- /dev/null +++ b/instructionAPI/ISA_ps/umull_advsimd_elt @@ -0,0 +1,17 @@ +##umull_advsimd_elt_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = Vpart[n, part]; +bits(idxdsize) operand2 = V[m]; +bits(2*datasize) result; +integer element1; +integer element2; +bits(2*esize) product; + +element2 = Int(Elem[operand2, index, esize], unsigned); +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + product = (element1 * element2)<2*esize-1:0>; + Elem[result, e, 2*esize] = product; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/umull_advsimd_vec b/instructionAPI/ISA_ps/umull_advsimd_vec new file mode 100644 index 0000000000..db0038507b --- /dev/null +++ b/instructionAPI/ISA_ps/umull_advsimd_vec @@ -0,0 +1,15 @@ +##umull_advsimd_vec_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = Vpart[n, part]; +bits(datasize) operand2 = Vpart[m, part]; +bits(2*datasize) result; +integer element1; +integer element2; + +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + Elem[result, e, 2*esize] = (element1 * element2)<2*esize-1:0>; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/umull_umaddl b/instructionAPI/ISA_ps/umull_umaddl new file mode 100644 index 0000000000..49011d9d71 --- /dev/null +++ b/instructionAPI/ISA_ps/umull_umaddl @@ -0,0 +1,15 @@ +##umull_umaddl_execute +bits(datasize) operand1 = X[n]; +bits(datasize) operand2 = X[m]; +bits(destsize) operand3 = X[a]; + +integer result; + +if sub_op then + result = Int(operand3, true) - (Int(operand1, true) * Int(operand2, true)); +else + result = Int(operand3, true) + (Int(operand1, true) * Int(operand2, true)); +end + +X[d] = result<63:0>; +@@ diff --git a/instructionAPI/ISA_ps/uqadd_advsimd b/instructionAPI/ISA_ps/uqadd_advsimd new file mode 100644 index 0000000000..499abb8eb5 --- /dev/null +++ b/instructionAPI/ISA_ps/uqadd_advsimd @@ -0,0 +1,19 @@ +##uqadd_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +integer element1; +integer element2; +integer sum; +boolean sat; + +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + sum = element1 + element2; + (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned); + if sat then FPSR.QC = 1; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/uqrshl_advsimd b/instructionAPI/ISA_ps/uqrshl_advsimd new file mode 100644 index 0000000000..2515c6ca90 --- /dev/null +++ b/instructionAPI/ISA_ps/uqrshl_advsimd @@ -0,0 +1,26 @@ +##uqrshl_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; + +integer round_const = 0; +integer shift; +integer element; +boolean sat; + +for e = 0 to elements-1 + shift = SInt(Elem[operand2, e, esize]<7:0>); + if rounding then + round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift + element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; + if saturating then + (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); + if sat then FPSR.QC = 1; + else + end + Elem[result, e, esize] = element; + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/uqrshrn_advsimd b/instructionAPI/ISA_ps/uqrshrn_advsimd new file mode 100644 index 0000000000..34052913fc --- /dev/null +++ b/instructionAPI/ISA_ps/uqrshrn_advsimd @@ -0,0 +1,15 @@ +##uqrshrn_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize*2) operand = V[n]; +bits(datasize) result; +integer round_const = if round then (1 << (shift - 1)) else 0; +integer element; +boolean sat; + +for e = 0 to elements-1 + element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift; + (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); + if sat then FPSR.QC = 1; + +Vpart[d, part] = result; +@@ diff --git a/instructionAPI/ISA_ps/uqshl_advsimd_imm b/instructionAPI/ISA_ps/uqshl_advsimd_imm new file mode 100644 index 0000000000..a908839d2c --- /dev/null +++ b/instructionAPI/ISA_ps/uqshl_advsimd_imm @@ -0,0 +1,14 @@ +##uqshl_advsimd_imm_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +integer element; +boolean sat; + +for e = 0 to elements-1 + element = Int(Elem[operand, e, esize], src_unsigned) << shift; + (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned); + if sat then FPSR.QC = 1; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/uqshl_advsimd_reg b/instructionAPI/ISA_ps/uqshl_advsimd_reg new file mode 100644 index 0000000000..2e1c342097 --- /dev/null +++ b/instructionAPI/ISA_ps/uqshl_advsimd_reg @@ -0,0 +1,26 @@ +##uqshl_advsimd_reg_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; + +integer round_const = 0; +integer shift; +integer element; +boolean sat; + +for e = 0 to elements-1 + shift = SInt(Elem[operand2, e, esize]<7:0>); + if rounding then + round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift + element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; + if saturating then + (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); + if sat then FPSR.QC = 1; + else + end + Elem[result, e, esize] = element; + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/uqshrn_advsimd b/instructionAPI/ISA_ps/uqshrn_advsimd new file mode 100644 index 0000000000..eb4d49575b --- /dev/null +++ b/instructionAPI/ISA_ps/uqshrn_advsimd @@ -0,0 +1,15 @@ +##uqshrn_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize*2) operand = V[n]; +bits(datasize) result; +integer round_const = if round then (1 << (shift - 1)) else 0; +integer element; +boolean sat; + +for e = 0 to elements-1 + element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift; + (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); + if sat then FPSR.QC = 1; + +Vpart[d, part] = result; +@@ diff --git a/instructionAPI/ISA_ps/uqsub_advsimd b/instructionAPI/ISA_ps/uqsub_advsimd new file mode 100644 index 0000000000..38f1082b6a --- /dev/null +++ b/instructionAPI/ISA_ps/uqsub_advsimd @@ -0,0 +1,19 @@ +##uqsub_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +integer element1; +integer element2; +integer diff; +boolean sat; + +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + diff = element1 - element2; + (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned); + if sat then FPSR.QC = 1; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/uqxtn_advsimd b/instructionAPI/ISA_ps/uqxtn_advsimd new file mode 100644 index 0000000000..c5ff42a9c8 --- /dev/null +++ b/instructionAPI/ISA_ps/uqxtn_advsimd @@ -0,0 +1,14 @@ +##uqxtn_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(2*datasize) operand = V[n]; +bits(datasize) result; +bits(2*esize) element; +boolean sat; + +for e = 0 to elements-1 + element = Elem[operand, e, 2*esize]; + (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned); + if sat then FPSR.QC = 1; + +Vpart[d, part] = result; +@@ diff --git a/instructionAPI/ISA_ps/urecpe_advsimd b/instructionAPI/ISA_ps/urecpe_advsimd new file mode 100644 index 0000000000..8dbc6ddaed --- /dev/null +++ b/instructionAPI/ISA_ps/urecpe_advsimd @@ -0,0 +1,12 @@ +##urecpe_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +bits(32) element; + +for e = 0 to elements-1 + element = Elem[operand, e, 32]; + Elem[result, e, 32] = UnsignedRecipEstimate(element); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/urhadd_advsimd b/instructionAPI/ISA_ps/urhadd_advsimd new file mode 100644 index 0000000000..aa8155a5f5 --- /dev/null +++ b/instructionAPI/ISA_ps/urhadd_advsimd @@ -0,0 +1,15 @@ +##urhadd_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; +integer element1; +integer element2; + +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + Elem[result, e, esize] = (element1 + element2 + 1); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/urshl_advsimd b/instructionAPI/ISA_ps/urshl_advsimd new file mode 100644 index 0000000000..3c95e58512 --- /dev/null +++ b/instructionAPI/ISA_ps/urshl_advsimd @@ -0,0 +1,26 @@ +##urshl_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; + +integer round_const = 0; +integer shift; +integer element; +boolean sat; + +for e = 0 to elements-1 + shift = SInt(Elem[operand2, e, esize]<7:0>); + if rounding then + round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift + element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; + if saturating then + (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); + if sat then FPSR.QC = 1; + else + end + Elem[result, e, esize] = element; + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/urshr_advsimd b/instructionAPI/ISA_ps/urshr_advsimd new file mode 100644 index 0000000000..d4559fd0b6 --- /dev/null +++ b/instructionAPI/ISA_ps/urshr_advsimd @@ -0,0 +1,15 @@ +##urshr_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) operand2; +bits(datasize) result; +integer round_const = if round then (1 << (shift - 1)) else 0; +integer element; + +operand2 = if accumulate then V[d] else Zeros(64); +for e = 0 to elements-1 + element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; + Elem[result, e, esize] = Elem[operand2, e, esize] + element; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/ursqrte_advsimd b/instructionAPI/ISA_ps/ursqrte_advsimd new file mode 100644 index 0000000000..c6c7c66912 --- /dev/null +++ b/instructionAPI/ISA_ps/ursqrte_advsimd @@ -0,0 +1,12 @@ +##ursqrte_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; +bits(32) element; + +for e = 0 to elements-1 + element = Elem[operand, e, 32]; + Elem[result, e, 32] = UnsignedRSqrtEstimate(element); + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/ursra_advsimd b/instructionAPI/ISA_ps/ursra_advsimd new file mode 100644 index 0000000000..41d95cf31b --- /dev/null +++ b/instructionAPI/ISA_ps/ursra_advsimd @@ -0,0 +1,15 @@ +##ursra_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) operand2; +bits(datasize) result; +integer round_const = if round then (1 << (shift - 1)) else 0; +integer element; + +operand2 = if accumulate then V[d] else Zeros(64); +for e = 0 to elements-1 + element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; + Elem[result, e, esize] = Elem[operand2, e, esize] + element; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/ushl_advsimd b/instructionAPI/ISA_ps/ushl_advsimd new file mode 100644 index 0000000000..d7167a088b --- /dev/null +++ b/instructionAPI/ISA_ps/ushl_advsimd @@ -0,0 +1,26 @@ +##ushl_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; + +integer round_const = 0; +integer shift; +integer element; +boolean sat; + +for e = 0 to elements-1 + shift = SInt(Elem[operand2, e, esize]<7:0>); + if rounding then + round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift + element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; + if saturating then + (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); + if sat then FPSR.QC = 1; + else + end + Elem[result, e, esize] = element; + end + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/ushll_advsimd b/instructionAPI/ISA_ps/ushll_advsimd new file mode 100644 index 0000000000..6bb48a598c --- /dev/null +++ b/instructionAPI/ISA_ps/ushll_advsimd @@ -0,0 +1,12 @@ +##ushll_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = Vpart[n, part]; +bits(datasize*2) result; +integer element; + +for e = 0 to elements-1 + element = Int(Elem[operand, e, esize], unsigned) << shift; + Elem[result, e, 2*esize] = element<2*esize-1:0>; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/ushr_advsimd b/instructionAPI/ISA_ps/ushr_advsimd new file mode 100644 index 0000000000..0954697119 --- /dev/null +++ b/instructionAPI/ISA_ps/ushr_advsimd @@ -0,0 +1,15 @@ +##ushr_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) operand2; +bits(datasize) result; +integer round_const = if round then (1 << (shift - 1)) else 0; +integer element; + +operand2 = if accumulate then V[d] else Zeros(64); +for e = 0 to elements-1 + element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; + Elem[result, e, esize] = Elem[operand2, e, esize] + element; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/usqadd_advsimd b/instructionAPI/ISA_ps/usqadd_advsimd new file mode 100644 index 0000000000..6513aa043d --- /dev/null +++ b/instructionAPI/ISA_ps/usqadd_advsimd @@ -0,0 +1,17 @@ +##usqadd_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) result; + +bits(datasize) operand2 = V[d]; +integer op1; +integer op2; +boolean sat; + +for e = 0 to elements-1 + op1 = Int(Elem[operand, e, esize], !unsigned); + op2 = Int(Elem[operand2, e, esize], unsigned); + (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned); + if sat then FPSR.QC = 1; +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/usra_advsimd b/instructionAPI/ISA_ps/usra_advsimd new file mode 100644 index 0000000000..fed6a987d2 --- /dev/null +++ b/instructionAPI/ISA_ps/usra_advsimd @@ -0,0 +1,15 @@ +##usra_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = V[n]; +bits(datasize) operand2; +bits(datasize) result; +integer round_const = if round then (1 << (shift - 1)) else 0; +integer element; + +operand2 = if accumulate then V[d] else Zeros(64); +for e = 0 to elements-1 + element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; + Elem[result, e, esize] = Elem[operand2, e, esize] + element; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/usubl_advsimd b/instructionAPI/ISA_ps/usubl_advsimd new file mode 100644 index 0000000000..c65791d834 --- /dev/null +++ b/instructionAPI/ISA_ps/usubl_advsimd @@ -0,0 +1,21 @@ +##usubl_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = Vpart[n, part]; +bits(datasize) operand2 = Vpart[m, part]; +bits(2*datasize) result; +integer element1; +integer element2; +integer sum; + +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + if sub_op then + sum = element1 - element2; + else + sum = element1 + element2; + end + Elem[result, e, 2*esize] = sum<2*esize-1:0>; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/usubw_advsimd b/instructionAPI/ISA_ps/usubw_advsimd new file mode 100644 index 0000000000..e81258adbe --- /dev/null +++ b/instructionAPI/ISA_ps/usubw_advsimd @@ -0,0 +1,21 @@ +##usubw_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(2*datasize) operand1 = V[n]; +bits(datasize) operand2 = Vpart[m, part]; +bits(2*datasize) result; +integer element1; +integer element2; +integer sum; + +for e = 0 to elements-1 + element1 = Int(Elem[operand1, e, 2*esize], unsigned); + element2 = Int(Elem[operand2, e, esize], unsigned); + if sub_op then + sum = element1 - element2; + else + sum = element1 + element2; + end + Elem[result, e, 2*esize] = sum<2*esize-1:0>; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/uxtb_ubfm b/instructionAPI/ISA_ps/uxtb_ubfm new file mode 100644 index 0000000000..1b12f9464f --- /dev/null +++ b/instructionAPI/ISA_ps/uxtb_ubfm @@ -0,0 +1,13 @@ +##uxtb_ubfm_execute +bits(datasize) dst = if inzero then Zeros(64) else X[d]; +bits(datasize) src = X[n]; + +// perform bitfield move on low bits +bits(datasize) bot = (dst AND NOT(wmask)) OR (ROR(src, R) AND wmask); + +// determine extension bits (sign, zero or dest register) +bits(datasize) top = if extend then Replicate(src) else dst; + +// combine extension bits and result bits +X[d] = (top AND NOT(tmask)) OR (bot AND tmask); +@@ diff --git a/instructionAPI/ISA_ps/uxth_ubfm b/instructionAPI/ISA_ps/uxth_ubfm new file mode 100644 index 0000000000..cf705d00d8 --- /dev/null +++ b/instructionAPI/ISA_ps/uxth_ubfm @@ -0,0 +1,13 @@ +##uxth_ubfm_execute +bits(datasize) dst = if inzero then Zeros(64) else X[d]; +bits(datasize) src = X[n]; + +// perform bitfield move on low bits +bits(datasize) bot = (dst AND NOT(wmask)) OR (ROR(src, R) AND wmask); + +// determine extension bits (sign, zero or dest register) +bits(datasize) top = if extend then Replicate(src) else dst; + +// combine extension bits and result bits +X[d] = (top AND NOT(tmask)) OR (bot AND tmask); +@@ diff --git a/instructionAPI/ISA_ps/uxtl_ushll_advsimd b/instructionAPI/ISA_ps/uxtl_ushll_advsimd new file mode 100644 index 0000000000..6dcbdfd28b --- /dev/null +++ b/instructionAPI/ISA_ps/uxtl_ushll_advsimd @@ -0,0 +1,12 @@ +##uxtl_ushll_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand = Vpart[n, part]; +bits(datasize*2) result; +integer element; + +for e = 0 to elements-1 + element = Int(Elem[operand, e, esize], unsigned) << shift; + Elem[result, e, 2*esize] = element<2*esize-1:0>; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/uzp1_advsimd b/instructionAPI/ISA_ps/uzp1_advsimd new file mode 100644 index 0000000000..a4da73ecef --- /dev/null +++ b/instructionAPI/ISA_ps/uzp1_advsimd @@ -0,0 +1,13 @@ +##uzp1_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operandl = V[n]; +bits(datasize) operandh = V[m]; +bits(datasize) result; +integer e; + +bits(datasize*2) zipped = operandh:operandl; +for e = 0 to elements-1 + Elem[result, e, esize] = Elem[zipped, 2*e+part, esize]; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/uzp2_advsimd b/instructionAPI/ISA_ps/uzp2_advsimd new file mode 100644 index 0000000000..1d5da34797 --- /dev/null +++ b/instructionAPI/ISA_ps/uzp2_advsimd @@ -0,0 +1,13 @@ +##uzp2_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operandl = V[n]; +bits(datasize) operandh = V[m]; +bits(datasize) result; +integer e; + +bits(datasize*2) zipped = operandh:operandl; +for e = 0 to elements-1 + Elem[result, e, esize] = Elem[zipped, 2*e+part, esize]; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/wfe_hint b/instructionAPI/ISA_ps/wfe_hint new file mode 100644 index 0000000000..b9e663a2bc --- /dev/null +++ b/instructionAPI/ISA_ps/wfe_hint @@ -0,0 +1,48 @@ +##wfe_hint_execute +case op of + when SystemHintOp_YIELD + Hint_Yield(); + end + + when SystemHintOp_WFE + if EventRegistered() then + ClearEventRegister(); + else + if PSTATE.EL == EL0 then + AArch64.CheckForWFxTrap(EL1, TRUE); + end + if HaveEL(EL2) && !IsSecure() && PSTATE.EL IN {EL0,EL1} then + AArch64.CheckForWFxTrap(EL2, TRUE); + end + if HaveEL(EL3) && PSTATE.EL != EL3 then + AArch64.CheckForWFxTrap(EL3, TRUE); + end + WaitForEvent(); + end + + end + when SystemHintOp_WFI + if !InterruptPending() then + if PSTATE.EL == EL0 then + AArch64.CheckForWFxTrap(EL1, FALSE); + end + if HaveEL(EL2) && !IsSecure() && PSTATE.EL IN {EL0,EL1} then + AArch64.CheckForWFxTrap(EL2, FALSE); + end + if HaveEL(EL3) && PSTATE.EL != EL3 then + AArch64.CheckForWFxTrap(EL3, FALSE); + end + WaitForInterrupt(); + end + + end + when SystemHintOp_SEV + SendEvent(); + end + + when SystemHintOp_SEVL + EventRegisterSet(); + end + + otherwise // do nothing +@@ diff --git a/instructionAPI/ISA_ps/wfi_hint b/instructionAPI/ISA_ps/wfi_hint new file mode 100644 index 0000000000..b584a14e75 --- /dev/null +++ b/instructionAPI/ISA_ps/wfi_hint @@ -0,0 +1,48 @@ +##wfi_hint_execute +case op of + when SystemHintOp_YIELD + Hint_Yield(); + end + + when SystemHintOp_WFE + if EventRegistered() then + ClearEventRegister(); + else + if PSTATE.EL == EL0 then + AArch64.CheckForWFxTrap(EL1, TRUE); + end + if HaveEL(EL2) && !IsSecure() && PSTATE.EL IN {EL0,EL1} then + AArch64.CheckForWFxTrap(EL2, TRUE); + end + if HaveEL(EL3) && PSTATE.EL != EL3 then + AArch64.CheckForWFxTrap(EL3, TRUE); + end + WaitForEvent(); + end + + end + when SystemHintOp_WFI + if !InterruptPending() then + if PSTATE.EL == EL0 then + AArch64.CheckForWFxTrap(EL1, FALSE); + end + if HaveEL(EL2) && !IsSecure() && PSTATE.EL IN {EL0,EL1} then + AArch64.CheckForWFxTrap(EL2, FALSE); + end + if HaveEL(EL3) && PSTATE.EL != EL3 then + AArch64.CheckForWFxTrap(EL3, FALSE); + end + WaitForInterrupt(); + end + + end + when SystemHintOp_SEV + SendEvent(); + end + + when SystemHintOp_SEVL + EventRegisterSet(); + end + + otherwise // do nothing +@@ diff --git a/instructionAPI/ISA_ps/xtn_advsimd b/instructionAPI/ISA_ps/xtn_advsimd new file mode 100644 index 0000000000..9dfbb2d3fc --- /dev/null +++ b/instructionAPI/ISA_ps/xtn_advsimd @@ -0,0 +1,11 @@ +##xtn_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(2*datasize) operand = V[n]; +bits(datasize) result; +bits(2*esize) element; + +for e = 0 to elements-1 + element = Elem[operand, e, 2*esize]; + Elem[result, e, esize] = element; +Vpart[d, part] = result; +@@ diff --git a/instructionAPI/ISA_ps/yield_hint b/instructionAPI/ISA_ps/yield_hint new file mode 100644 index 0000000000..b2b9270720 --- /dev/null +++ b/instructionAPI/ISA_ps/yield_hint @@ -0,0 +1,48 @@ +##yield_hint_execute +case op of + when SystemHintOp_YIELD + Hint_Yield(); + end + + when SystemHintOp_WFE + if EventRegistered() then + ClearEventRegister(); + else + if PSTATE.EL == EL0 then + AArch64.CheckForWFxTrap(EL1, TRUE); + end + if HaveEL(EL2) && !IsSecure() && PSTATE.EL IN {EL0,EL1} then + AArch64.CheckForWFxTrap(EL2, TRUE); + end + if HaveEL(EL3) && PSTATE.EL != EL3 then + AArch64.CheckForWFxTrap(EL3, TRUE); + end + WaitForEvent(); + end + + end + when SystemHintOp_WFI + if !InterruptPending() then + if PSTATE.EL == EL0 then + AArch64.CheckForWFxTrap(EL1, FALSE); + end + if HaveEL(EL2) && !IsSecure() && PSTATE.EL IN {EL0,EL1} then + AArch64.CheckForWFxTrap(EL2, FALSE); + end + if HaveEL(EL3) && PSTATE.EL != EL3 then + AArch64.CheckForWFxTrap(EL3, FALSE); + end + WaitForInterrupt(); + end + + end + when SystemHintOp_SEV + SendEvent(); + end + + when SystemHintOp_SEVL + EventRegisterSet(); + end + + otherwise // do nothing +@@ diff --git a/instructionAPI/ISA_ps/zip1_advsimd b/instructionAPI/ISA_ps/zip1_advsimd new file mode 100644 index 0000000000..be4fa786fa --- /dev/null +++ b/instructionAPI/ISA_ps/zip1_advsimd @@ -0,0 +1,15 @@ +##zip1_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; + +integer base = part * pairs; +integer p; + +for p = 0 to pairs-1 + Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize]; + Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize]; + +V[d] = result; +@@ diff --git a/instructionAPI/ISA_ps/zip2_advsimd b/instructionAPI/ISA_ps/zip2_advsimd new file mode 100644 index 0000000000..d43061923c --- /dev/null +++ b/instructionAPI/ISA_ps/zip2_advsimd @@ -0,0 +1,15 @@ +##zip2_advsimd_execute +CheckFPAdvSIMDEnabled64(); +bits(datasize) operand1 = V[n]; +bits(datasize) operand2 = V[m]; +bits(datasize) result; + +integer base = part * pairs; +integer p; + +for p = 0 to pairs-1 + Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize]; + Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize]; + +V[d] = result; +@@ diff --git a/instructionAPI/aarch64_pseudocode_extractor.py b/instructionAPI/aarch64_pseudocode_extractor.py new file mode 100644 index 0000000000..c9dfb1a8c8 --- /dev/null +++ b/instructionAPI/aarch64_pseudocode_extractor.py @@ -0,0 +1,101 @@ +import os, sys +import re + +ISA_dir = '/p/paradyn/arm/arm-download-1350222/AR100-DA-70000-r0p0-00rel10/AR100-DA-70000-r0p0-00rel10/ISA_xml/ISA_xml_v2_00rel11/' +ISA_ps = '/p/paradyn/development/ssunny/dyninst/dyninst-code/instructionAPI/ISA_ps/' +files_dir = os.listdir(ISA_dir) +ifkeywords = ["else", "elsif"] +lineignorewords = ["Constrain", "CheckSPAlignment"] + +for f in files_dir: + parts = f.split('.') + if len(parts) != 2 or parts[1] != "xml" or len(parts[0]) < 1: + continue + instr = parts[0] + + curfname = ISA_dir + instr + ".xml" + fdata = "" + with open(curfname) as curfile: + fdata = curfile.read().replace('\n', '') + if fdata.find("aliasto") != -1: + refiformval = fdata.split("aliasto ")[1].split(" ")[0] + curfname = ISA_dir + refiformval.split("=")[1].replace('\"', '') + + lines = list(open(curfname)) + idx = -1 + + startPs = False + isDecode = False + isExecute = False + + blockidxstack = list() + blockcount = 0 + + decode = "" + execute = "" + for line in lines: + idx += 1 + + if line.find("") != -1: + startPs = False + # if isDecode == True: + # isDecode = False + if isExecute == True: + isExecute = False + while blockcount > 0: + top = blockidxstack.pop() + execute += (" " * top) + execute += "end\n" + blockcount -= 1 + elif startPs == True: + # if isDecode == True: + # decode += line + if isExecute == True and any(kw in line for kw in lineignorewords) == False: + curidx = len(line) - len(line.lstrip()) + + if blockcount > 0 and (blockidxstack[len(blockidxstack) - 1] >= curidx or line.strip() == "") and any(kw in line for kw in ifkeywords) == False: + top = blockidxstack.pop() + + prevline = lines[idx - 1] + if prevline.find("if") == -1 and prevline.find("then") == -1: + execute += (" " * top) + execute += "end\n" + blockcount -= 1 + + if (line.find("if") != -1 and line.find("then") != -1 and line.find("bits") != 0 and line.find("elsif") == -1) or (line.find("when") != -1): + blockcount = blockcount + 1 + blockidxstack.append(curidx) + + execute += line + else: + print("!!!Found pseudocode section that is not decode or execute!!!") + # sys.exit(0) + else: + continue + + decode = re.sub(r"<[^>]*>|^\s+|\'", "", decode) + decode = re.sub(r"&", "&", re.sub(r">", ">", re.sub(r"<", "<", decode))) + execute = re.sub(r"&", "&", re.sub(r">", ">", re.sub(r"<", "<", re.sub(r"<[^>]*>|^\s+|\'", "", execute)))) + execute = re.sub(r"Zeros\(\)", "Zeros(64)", execute) + + f = open(ISA_ps + instr, "w") + if decode != "": + f.write("##" + instr + "_" + "decode\n") + f.write(decode) + f.write("@@\n") + if execute != "": + f.write("##" + instr + "_" + "execute\n") + f.write(execute) + f.write("@@\n") + f.close()