Dyninst 9.3.2

@wrwilliams wrwilliams released this Apr 18, 2017 · 8 commits to v9.3.x since this release

Change Log

v9.3.2 (2017-04-05)

Full Changelog

Fixed bugs:

  • memcpy can fail with rewriter tests #355
  • dyninst does not build on i386 #343
  • [ARMv8 Decoding] SQ* instructions need to check bits with specific values #268
  • [ARMv8 Decoding] SMADDL and SMSUBL should have 32-bit register for operands 2 and 3 #266
  • [ARMv8 Decoding] SHL and SLI should have 0 for bit 11 #265
  • [ARMv8 Decoding] NEG instruction must have size = '11' #263
  • [ARMv8 Decoding] FMUL instruction cannot have size:q = '10' #262
  • [ARM Decoding] FMUL instructions cannot have 'size:L' == '11' #258
  • [ARM Decoding] Convert instruction immediate has reserved values (currently ignored) #257
  • [ARM Decoding] FCVTXN should be FCVTXN2 #255
  • [ARM Decoding] FCVT 'type' field cannot equal 'opc' field #254
  • [ARM Decoding] Reserved size value for some vector register instructions is ignored #249
  • [ARM Decoding] Stack pointer used where zero register should be #248
  • [ARM Decoding] Signed multiply instructions ignore size resitrictions #247
  • [ARM Decoding] Paired memory accesses must access aligned memory #245
  • [ARM Decoding] Convert instruction immediates appear incorrect at 64 #241
  • [ARM Decoding] Convert instruction immediate should not be larger than the register size #240
  • [ARM Syntax] Signed immediates should be shown as signed #239
  • [ARM Decoding] We should print the full operands of PRFUM #238
  • [ARM Decoding] Bad shift amounts. #233
  • [ARM Decoding] SIMD load instruction should be valid #223
  • [ARM Decoding] Decoding of MOVK instruction ignores restriction on combination of size and hw bits #222
  • [ARM Decoding] Decoding of ADDHN ignore reserved size bits #221
  • [ARM Syntax] Zero register should have sizing, either XZR or WZR #220
  • [ARM Decoding] Invalid CCMP and CCMN decoded as valid #219
  • [ARM Syntax] Shifted immediate for CCMP and CCMN #218
  • [ARM Syntax] Immediate out of range for LDRSB #217
  • [ARM Syntax] Repeated register number as constant #216

Merged pull requests:

  • CMake fixup #349 (wrwilliams)
  • Fix up exception handling code so that we only consider call instructions for exception sensitivity and its attendant emulation #347 (wrwilliams)
  • Refactor BPatch_type so it always has a reference to its underlying symtab type. #346 (wrwilliams)

* This Change Log was automatically generated by github_changelog_generator