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Broaden isSchedulingBoundary to check aliases of SP.

On PPC the stack pointer is X1, but ADJCALLSTACK writes R1.

Fixes PR14315: Register regmask dependency problem with misched.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168248 91177308-0d34-0410-b5e6-96231b3b80d8
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commit 9dd17210b132d6135ee4a849d307e263e60f545c 1 parent 5c7121e
Andrew Trick authored
3  lib/CodeGen/TargetInstrInfoImpl.cpp
@@ -472,7 +472,8 @@ bool TargetInstrInfoImpl::isSchedulingBoundary(const MachineInstr *MI,
472 472 // stack slot reference to depend on the instruction that does the
473 473 // modification.
474 474 const TargetLowering &TLI = *MF.getTarget().getTargetLowering();
475   - if (MI->definesRegister(TLI.getStackPointerRegisterToSaveRestore()))
  475 + const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
  476 + if (MI->modifiesRegister(TLI.getStackPointerRegisterToSaveRestore(), TRI))
476 477 return true;
477 478
478 479 return false;
33 test/CodeGen/PowerPC/2012-11-16-mischedcall.ll
... ... @@ -0,0 +1,33 @@
  1 +; RUN: llc -march=ppc64 -enable-misched < %s | FileCheck %s
  2 +;
  3 +; PR14315: misched should not move the physreg copy of %t below the calls.
  4 +
  5 +@.str89 = external unnamed_addr constant [6 x i8], align 1
  6 +
  7 +declare void @init() nounwind
  8 +
  9 +declare void @clock() nounwind
  10 +
  11 +; CHECK: %entry
  12 +; CHECK: fmr f31, f1
  13 +; CHECK: bl _init
  14 +define void @s332(double %t) nounwind {
  15 +entry:
  16 + tail call void @init()
  17 + tail call void @clock() nounwind
  18 + br label %for.cond2
  19 +
  20 +for.cond2: ; preds = %for.body4, %entry
  21 + %i.0 = phi i32 [ %inc, %for.body4 ], [ 0, %entry ]
  22 + %cmp3 = icmp slt i32 undef, 16000
  23 + br i1 %cmp3, label %for.body4, label %L20
  24 +
  25 +for.body4: ; preds = %for.cond2
  26 + %cmp5 = fcmp ogt double undef, %t
  27 + %inc = add nsw i32 %i.0, 1
  28 + br i1 %cmp5, label %L20, label %for.cond2
  29 +
  30 +L20: ; preds = %for.body4, %for.cond2
  31 + %index.0 = phi i32 [ -2, %for.cond2 ], [ %i.0, %for.body4 ]
  32 + unreachable
  33 +}

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