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Jul 11, 2014

  1. Kariddi

    Fixup PHIs in LowerSwitch when a Leaf node is not emitted.

    This commit fixes bug
    Thanks to Qwertyuiop for the report and the proposed fix.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
    Kariddi authored
  2. [X86] AVX512: Improve readability of isCDisp8

    No functional change.  As I was trying to understand this function, I found
    that variables were reused with confusing names and the broadcast case was a
    bit too implicit.  Hopefully, this is an improvement.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
    Adam Nemet authored
  3. [X86] AVX512: Simplify logic in isCDisp8

    It was computing the VL/n case as:
      MemObjSize = VectorByteSize / ElemByteSize / Divider * ElemByteSize
    ElemByteSize not only falls out but VectorByteSize/Divider now actually
    matches the definition of VL/n.
    Also some formatting fixes.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
    Adam Nemet authored
  4. Revert "Reapply "DebugInfo: Ensure that all debug location scope chai…

    …ns from instructions within a function, lead to the function itself.""
    This reverts commit r212776.
    Nope, still seems to be failing on the sanitizer bots... but hey, not
    the msan self-host anymore, it's failing in asan now. I'll start looking
    there next.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
    David Blaikie authored

Jul 10, 2014

  1. Partially fix PR20058: reduce compile time for loop unrolling with ve…

    …ry high count by reducing calls to SE->forgetLoop
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
    Mark Heffernan authored
  2. [RuntimeDyld] Replace a crufty old ARM RuntimeDyld test with a new on…

    …e that uses
    This allows us to remove one of the six remaining object files in the LLVM
    source tree.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
    Lang Hames authored
  3. [RuntimeDyld] Improve error diagnostic in RuntimeDyldChecker.

    The compiler often emits assembler-local labels (beginning with 'L') for use in
    relocation expressions, however these aren't included in the object files.
    Teach RuntimeDyldChecker to warn the user if they try to use one of these in an
    expression, since it will never work.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
    Lang Hames authored
  4. Reapply "DebugInfo: Ensure that all debug location scope chains from …

    …instructions within a function, lead to the function itself."
    Committed in r212205 and reverted in r212226 due to msan self-hosting
    failure, I believe I've got that fixed by r212761 to Clang.
    Original commit message:
    "Originally committed in r211723, reverted in r211724 due to failure
    cases found and fixed (ArgumentPromotion: r211872, Inlining: r212065),
    committed again in r212085 and reverted again in r212089 after fixing
    some other cases, such as debug info subprogram lists not keeping track
    of the function they represent (r212128) and then short-circuiting
    things like LiveDebugVariables that build LexicalScopes for functions
    that might not have full debug info.
    And again, I believe the invariant actually holds for some reasonable
    amount of code (but I'll keep an eye on the buildbots and see what
    happens... ).
    Original commit message:
    PR20038: DebugInfo: Inlined call sites where the caller has debug info
    but the call itself has no debug location.
    This situation does bad things when inlined, so I've fixed Clang not to
    produce inlinable call sites without locations when the caller has debug
    info (in the one case where I could find that this occurred). This
    updates the PR20038 test case to be what clang now produces, and readds
    the assertion that had to be removed due to this bug.
    I've also beefed up the debug info verifier to help diagnose these
    issues in the future, and I hope to add checks to the inliner to just
    assert-fail if it encounters this situation. If, in the future, we
    decide we have to cope with this situation, the right thing to do is
    probably to just remove all the DebugLocs from the inlined
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
    David Blaikie authored
  5. This test case doesn't actually need the inliner to reproduce the input.

    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
    David Blaikie authored
  6. Jan Vesely

    R600: Implement float to long/ulong

    Use alg. from LegalizeDAG.cpp
    Move Expand setting to SIISellowering
    v2: Extend existing tests instead of creating new ones
    v3: use separate LowerFPTOSINT function
    v4: use TargetLowering::expandFP_TO_SINT
        add comment about using FP_TO_SINT for uints
    Signed-off-by: Jan Vesely <>
    Reviewed-by: Tom Stellard <>
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
    jvesely authored
  7. Jan Vesely

    SelectionDAG: Factor FP_TO_SINT lower code out of DAGLegalizer

    Move the code to a helper function to allow calls from TypeLegalizer.
    No functionality change intended
    Signed-off-by: Jan Vesely <>
    Reviewed-by: Tom Stellard <>
    Reviewed-by: Owen Anderson <>
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
    jvesely authored
  8. brad0

    Use the integrated assembler by default on OpenBSD.

    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
    brad0 authored
  9. [mips] Emit two CFI offset directives per double precision SDC1/LDC1

    instead of just one for FR=1 registers
    Differential Revision:
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
    Zoran Jovanovic authored
  10. Extend the test coverage in combine-vec-shuffle-2.ll adding some nega…

    …tive tests.
    Add test cases where we don't expect to trigger the combine optimizations
    introduced at revision 212748.
    No functional change intended.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
    Andrea Di Biagio authored
  11. Matt Arsenault

    Revert "Revert r212640, "Add trunc (select c, a, b) -> select c (trun…

    …c a), (trunc b) combine.""
    Don't try to convert the select condition type.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
    arsenm authored
  12. [DAG] Further improve the logic in DAGCombiner that folds a pair of s…

    …huffles into a single shuffle if the resulting mask is legal.
    This patch teaches the DAGCombiner how to fold shuffles according to the
    following new rules:
      1. shuffle(shuffle(x, y), undef) -> x
      2. shuffle(shuffle(x, y), undef) -> y
      3. shuffle(shuffle(x, y), undef) -> shuffle(x, undef)
      4. shuffle(shuffle(x, y), undef) -> shuffle(y, undef)
    The backend avoids to combine shuffles according to rules 3. and 4. if
    the resulting shuffle does not have a legal mask. This is to avoid introducing
    illegal shuffles that are potentially expanded into a sub-optimal sequence of
    target specific dag nodes during vector legalization.
    Added test case combine-vec-shuffle-2.ll to verify that we correctly triggers
    the new rules when combining shuffles.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
    Andrea Di Biagio authored
  13. [X86] Mark pseudo instruction TEST8ri_NOEREX as hasSIdeEffects=0.

    Also, add a case clause in X86InstrInfo::shouldScheduleAdjacent to enable
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
    Akira Hatanaka authored
  14. Add the CSR company and the Kalimba DSP processor to Triple.

    Patch by Matthew Gardiner with fixes by me.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
    Eric Christopher authored
  15. Make it possible for the Subtarget to change between function

    passes in the mips back end. This, unfortunately, required a
    bit of churn in the various predicates to use a pointer rather
    than a reference.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
    Eric Christopher authored
  16. InstCombine: Fix a crash in Descale for multiply-by-zero

    Fix a crash in `InstCombiner::Descale()` when a multiply-by-zero gets
    created as an argument to a GEP partway through an iteration, causing
    -instcombine to optimize the GEP before the multiply.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
    Duncan P. N. Exon Smith authored
  17. majnemer

    IR: Aliases don't belong to an explicit comdat

    Aliases inherit their comdat from their aliasee, they don't have an
    explicit comdat.
    This fixes PR20279.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
    majnemer authored
  18. Hal Finkel

    Feeding isSafeToSpeculativelyExecute its DataLayout pointer (in Sink)

    This is the one remaining place I see where passing
    isSafeToSpeculativelyExecute a DataLayout pointer might matter (at least for
    loads) -- I think I got the others in r212720. Most of the other remaining
    callers of isSafeToSpeculativelyExecute only use it for call sites (or
    otherwise exclude loads).
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
    hfinkel authored
  19. majnemer

    Mips: Silence a -Wcovered-switch-default

    Remove a default label which covered no enumerators, replace it with a
    No functionality changed.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
    majnemer authored
  20. [mips] Added FPXX modeless calling convention.

    Differential Revision:
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
    Zoran Jovanovic authored
  21. [AArch64] Add logical alias instructions to MC AsmParser

    This patch teaches the AsmParser to accept some logical+immediate
    instructions and convert them as shown:
      bic  Rd, Rn, #imm  ->  and Rd, Rn, #~imm
      bics Rd, Rn, #imm  ->  ands Rd, Rn, #~imm
      orn  Rd, Rn, #imm  ->  orr Rd, Rn, #~imm
      eon  Rd, Rn, #imm  ->  eor Rd, Rn, #~imm
    Those instructions are an alternate syntax available to assembly coders,
    and are needed in order to support code already compiling with some other
    assemblers. For example, the bic construct is used by the linux kernel.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
    Arnaud A. de Grandmaison authored
  22. Hal Finkel

    Feeding isSafeToSpeculativelyExecute its DataLayout pointer

    isSafeToSpeculativelyExecute can optionally take a DataLayout pointer. In the
    past, this was mainly used to make better decisions regarding divisions known
    not to trap, and so was not all that important for users concerned with "cheap"
    instructions. However, now it also helps look through bitcasts for
    dereferencable loads, and will also be important if/when we add a
    dereferencable pointer attribute.
    This is some initial work to feed a DataLayout pointer through to callers of
    isSafeToSpeculativelyExecute, generally where one was already available.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
    hfinkel authored
  23. AArch64: correctly fast-isel i8 & i16 multiplies

    We were asking for a register for type i8 or i16 which caused an assert.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
    Tim Northover authored
  24. [mips] Add support for -modd-spreg/-mno-odd-spreg

    When -mno-odd-spreg is in effect, 32-bit floating point values are not
    permitted in odd FPU registers. The option also prohibits 32-bit and 64-bit
    floating point comparison results from being written to odd registers.
    This option has three purposes:
    * It allows support for certain MIPS implementations such as loongson-3a that
      do not allow the use of odd registers for single precision arithmetic.
    * When using -mfpxx, -mno-odd-spreg is the default and this allows us to
      statically check that code is compliant with the O32 FPXX ABI since mtc1/mfc1
      instructions to/from odd registers are guaranteed not to appear for any
      reason. Once this has been established, the user can then re-enable
      -modd-spreg to regain the use of all 32 single-precision registers.
    * When using -mfp64 and -mno-odd-spreg together, an O32 extension named
      O32 FP64A is used as the ABI. This is intended to provide almost all
      functionality of an FR=1 processor but can also be executed on a FR=0 core
      with the assistance of a hardware compatibility mode which emulates FR=0
      behaviour on an FR=1 processor.
    * Added '.module oddspreg' and '.module nooddspreg' each of which update
      the .MIPS.abiflags section appropriately
    * Moved setFpABI() call inside emitDirectiveModuleFP() so that the caller
      doesn't have to remember to do it.
    * MipsABIFlags now calculates the flags1 and flags2 member on demand rather
      than trying to maintain them in the same format they will be emitted in.
    There is one portion of the -mfp64 and -mno-odd-spreg combination that is not
    implemented yet. Moves to/from odd-numbered double-precision registers must not
    use mtc1. I will fix this in a follow-up.
    Differential Revision:
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
    Daniel Sanders authored
  25. [x32] Add AsmBackend for X32 which uses ELF32 with x86_64 (the author…

    … is Pavel Chupin).
    This is minimal change for backend required to have "hello world" compiled and working on x32 target (x86_64-linux-gnux32). More patches for x32 will follow.
    Differential Revision:
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
    Zinovy Nis authored
  26. Chandler Carruth

    [x86,SDAG] Introduce any- and sign-extend-vector-inreg nodes analogous

    to the zero-extend-vector-inreg node introduced previously for the same
    purpose: manage the type legalization of widened extend operations,
    especially to support the experimental widening mode for x86.
    I'm adding both because sign-extend is expanded in terms of any-extend
    with shifts to propagate the sign bit. This removes the last
    fundamental scalarization from vec_cast2.ll (a test case that hit many
    really bad edge cases for widening legalization), although the trunc
    tests in that file still appear scalarized because the the shuffle
    legalization is scalarizing. Funny thing, I've been working on that.
    Some initial experiments with this and SSE2 scenarios is showing
    moderately good behavior already for sign extension. Still some work to
    do on the shuffle combining on X86 before we're generating optimal
    sequences, but avoiding scalarization is a huge step forward.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
    chandlerc authored
  27. [SystemZ] Use to define callee-saved registers

    Just a clean-up.  No behavioral change intended.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
    Richard Sandiford authored
  28. NAKAMURA Takumi

    SpecialCaseList.h: Fix -Wdocumentation with \code.

    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
    chapuni authored
  29. NAKAMURA Takumi

    llvm/test/CodeGen/X86/shift-parts.ll: FileCheck-ize. (from r212640)

    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
    chapuni authored
  30. NAKAMURA Takumi

    Revert r212640, "Add trunc (select c, a, b) -> select c (trunc a), (t…

    …runc b) combine."
    This caused miscompilation on, at least, x86-64. SExt(i1 cond) confused other optimizations.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
    chapuni authored
  31. [SystemZ] Tweak instruction format classifications

    There's no real need to have Shift as a separate format type from Binary.
    The comments for other format types were too specific and in some cases
    no longer accurate.
    Just a clean-up, no behavioral change intended.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
    Richard Sandiford authored
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