diff --git a/ports/cortex_m3/ac5/inc/tx_port.h b/ports/cortex_m3/ac5/inc/tx_port.h
index 62783624a..62cae66d0 100644
--- a/ports/cortex_m3/ac5/inc/tx_port.h
+++ b/ports/cortex_m3/ac5/inc/tx_port.h
@@ -9,6 +9,10 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Some portions generated by Gemini (Gemini 2.0 Flash).
+// Some portions generated by Copilot (Claude Sonnet 4.6).
+// Some portions generated by Claude Code (Opus 5).
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -539,8 +543,9 @@ unsigned int posture;
 #ifdef TX_PORT_USE_BASEPRI
 __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsigned int basepri_value)
 {
-    __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value));
+    __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value) : "memory");
 }
+
 #else
 __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
 {
@@ -552,7 +557,7 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(unsign
 {
 #ifdef TX_PORT_USE_BASEPRI
     __set_basepri_value(int_posture);
-    //__asm__ volatile ("MSR  BASEPRI,%0": : "r" (int_posture): "memory");
+    __asm__ volatile ("" : : : "memory");
 #else
     __asm__ volatile ("MSR  PRIMASK,%0": : "r" (int_posture): "memory");
 #endif
@@ -578,6 +583,7 @@ unsigned int interrupt_save;
 
     /* Set PendSV to invoke ThreadX scheduler.  */
     *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
+    __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
     if (__get_ipsr_value() == 0)
     {
         interrupt_save = __get_interrupt_posture();
@@ -587,6 +593,7 @@ unsigned int interrupt_save;
         __enable_interrupts();
 #endif
         __restore_interrupt(interrupt_save);
+        __asm__ volatile ("isb 0xF " : : : "memory");
     }
 }
 
diff --git a/ports/cortex_m3/ac6/inc/tx_port.h b/ports/cortex_m3/ac6/inc/tx_port.h
index df44632b0..7265724ef 100644
--- a/ports/cortex_m3/ac6/inc/tx_port.h
+++ b/ports/cortex_m3/ac6/inc/tx_port.h
@@ -11,6 +11,7 @@
 
 // Some portions generated by Gemini (Gemini 2.0 Flash).
 // Some portions generated by Copilot (Claude Sonnet 4.6).
+// Some portions generated by Claude Code (Opus 5).
 
 
 /**************************************************************************/
@@ -544,8 +545,8 @@ __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsign
 {
     __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value) : "memory");
 }
-#else
 
+#else
 __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
 {
     __asm__ volatile ("CPSIE  i": : : "memory");
@@ -592,8 +593,10 @@ unsigned int interrupt_save;
         __enable_interrupts();
 #endif
         __restore_interrupt(interrupt_save);
+        __asm__ volatile ("isb 0xF " : : : "memory");
     }
 }
+
 #define TX_INTERRUPT_SAVE_AREA                  UINT interrupt_save;
 #define TX_DISABLE                              interrupt_save =  __disable_interrupts();
 #define TX_RESTORE                              __restore_interrupt(interrupt_save);
diff --git a/ports/cortex_m3/ac6/src/tx_thread_system_return.S b/ports/cortex_m3/ac6/src/tx_thread_system_return.S
index a8654f6ba..6d0e26afa 100644
--- a/ports/cortex_m3/ac6/src/tx_thread_system_return.S
+++ b/ports/cortex_m3/ac6/src/tx_thread_system_return.S
@@ -85,10 +85,12 @@ _tx_thread_system_return:
     MOV     r0, #0
     MSR     BASEPRI, r0                             // Enable interrupts
     MSR     BASEPRI, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #else
     MRS     r1, PRIMASK                             // Thread context returning, pickup PRIMASK
     CPSIE   i                                       // Enable interrupts
     MSR     PRIMASK, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #endif
 _isr_context:
     BX      lr                                      // Return to caller
diff --git a/ports/cortex_m3/gnu/inc/tx_port.h b/ports/cortex_m3/gnu/inc/tx_port.h
index d36b9ea38..d5299cb38 100644
--- a/ports/cortex_m3/gnu/inc/tx_port.h
+++ b/ports/cortex_m3/gnu/inc/tx_port.h
@@ -10,6 +10,8 @@
  **************************************************************************/
 
 // Some portions generated by Gemini (Gemini 2.0 Flash).
+// Some portions generated by Copilot (Claude Sonnet 4.6).
+// Some portions generated by Claude Code (Opus 5).
 
 
 /**************************************************************************/
@@ -543,6 +545,7 @@ __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsign
 {
     __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value) : "memory");
 }
+
 #else
 __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
 {
@@ -554,6 +557,7 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(unsign
 {
 #ifdef TX_PORT_USE_BASEPRI
     __set_basepri_value(int_posture);
+    __asm__ volatile ("" : : : "memory");
 #else
     __asm__ volatile ("MSR  PRIMASK,%0": : "r" (int_posture): "memory");
 #endif
diff --git a/ports/cortex_m3/iar/inc/tx_port.h b/ports/cortex_m3/iar/inc/tx_port.h
index 18c7e9f2e..5b05c277a 100644
--- a/ports/cortex_m3/iar/inc/tx_port.h
+++ b/ports/cortex_m3/iar/inc/tx_port.h
@@ -11,6 +11,7 @@
 
 // Some portions generated by Gemini (Gemini 2.0 Flash).
 // Some portions generated by Copilot (Claude Sonnet 4.6).
+// Some portions generated by Claude Code (Opus 5).
 
 
 /**************************************************************************/
@@ -544,8 +545,8 @@ __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsign
 {
     __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value) : "memory");
 }
-#else
 
+#else
 __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
 {
     __asm__ volatile ("CPSIE  i": : : "memory");
@@ -592,8 +593,10 @@ unsigned int interrupt_save;
         __enable_interrupts();
 #endif
         __restore_interrupt(interrupt_save);
+        __asm__ volatile ("isb 0xF " : : : "memory");
     }
 }
+
 #define TX_INTERRUPT_SAVE_AREA                  UINT interrupt_save;
 #define TX_DISABLE                              interrupt_save =  __disable_interrupts();
 #define TX_RESTORE                              __restore_interrupt(interrupt_save);
diff --git a/ports/cortex_m3/iar/src/tx_thread_system_return.s b/ports/cortex_m3/iar/src/tx_thread_system_return.s
index 8bd4ca820..7bc5f2ebc 100644
--- a/ports/cortex_m3/iar/src/tx_thread_system_return.s
+++ b/ports/cortex_m3/iar/src/tx_thread_system_return.s
@@ -83,10 +83,12 @@ _tx_thread_system_return:
     MOV     r0, #0
     MSR     BASEPRI, r0                             // Enable interrupts
     MSR     BASEPRI, r1                             // Restore original interrupt posture
+    ISB     SY                                      // Flush pipeline
 #else
     MRS     r1, PRIMASK                             // Thread context returning, pickup PRIMASK
     CPSIE   i                                       // Enable interrupts
     MSR     PRIMASK, r1                             // Restore original interrupt posture
+    ISB     SY                                      // Flush pipeline
 #endif
 _isr_context:
     BX      lr                                      // Return to caller
diff --git a/ports/cortex_m3/keil/inc/tx_port.h b/ports/cortex_m3/keil/inc/tx_port.h
index d7a7e9412..0fc2ea65a 100644
--- a/ports/cortex_m3/keil/inc/tx_port.h
+++ b/ports/cortex_m3/keil/inc/tx_port.h
@@ -9,6 +9,10 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Some portions generated by Gemini (Gemini 2.0 Flash).
+// Some portions generated by Copilot (Claude Sonnet 4.6).
+// Some portions generated by Claude Code (Opus 5).
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -539,8 +543,9 @@ unsigned int posture;
 #ifdef TX_PORT_USE_BASEPRI
 __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsigned int basepri_value)
 {
-    __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value));
+    __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value) : "memory");
 }
+
 #else
 __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
 {
@@ -552,7 +557,7 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(unsign
 {
 #ifdef TX_PORT_USE_BASEPRI
     __set_basepri_value(int_posture);
-    //__asm__ volatile ("MSR  BASEPRI,%0": : "r" (int_posture): "memory");
+    __asm__ volatile ("" : : : "memory");
 #else
     __asm__ volatile ("MSR  PRIMASK,%0": : "r" (int_posture): "memory");
 #endif
@@ -578,6 +583,7 @@ unsigned int interrupt_save;
 
     /* Set PendSV to invoke ThreadX scheduler.  */
     *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
+    __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
     if (__get_ipsr_value() == 0)
     {
         interrupt_save = __get_interrupt_posture();
@@ -587,6 +593,7 @@ unsigned int interrupt_save;
         __enable_interrupts();
 #endif
         __restore_interrupt(interrupt_save);
+        __asm__ volatile ("isb 0xF " : : : "memory");
     }
 }
 
diff --git a/ports/cortex_m33/ac6/inc/tx_port.h b/ports/cortex_m33/ac6/inc/tx_port.h
index bfdff366b..86411a859 100644
--- a/ports/cortex_m33/ac6/inc/tx_port.h
+++ b/ports/cortex_m33/ac6/inc/tx_port.h
@@ -10,6 +10,7 @@
  **************************************************************************/
 
 // Some portions generated by Gemini (Gemini 2.0 Flash).
+// Some portions generated by Claude Code (Opus 5).
 
 
 /**************************************************************************/
@@ -592,6 +593,7 @@ UINT interrupt_save;
         __enable_interrupts();
 #endif
         __restore_interrupt(interrupt_save);
+        __asm__ volatile ("isb 0xF " : : : "memory");
     }
 }
 
diff --git a/ports/cortex_m33/ac6/src/tx_thread_system_return.S b/ports/cortex_m33/ac6/src/tx_thread_system_return.S
index e57b28ea2..cd183702f 100644
--- a/ports/cortex_m33/ac6/src/tx_thread_system_return.S
+++ b/ports/cortex_m33/ac6/src/tx_thread_system_return.S
@@ -86,10 +86,12 @@ _tx_thread_system_return:
     MOV     r0, #0
     MSR     BASEPRI, r0                             // Enable interrupts
     MSR     BASEPRI, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #else
     MRS     r1, PRIMASK                             // Thread context returning, pickup PRIMASK
     CPSIE   i                                       // Enable interrupts
     MSR     PRIMASK, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #endif
 _isr_context:
     BX      lr                                      // Return to caller
diff --git a/ports/cortex_m33/gnu/inc/tx_port.h b/ports/cortex_m33/gnu/inc/tx_port.h
index bc6321c0b..dc67c0015 100644
--- a/ports/cortex_m33/gnu/inc/tx_port.h
+++ b/ports/cortex_m33/gnu/inc/tx_port.h
@@ -10,6 +10,7 @@
  **************************************************************************/
 
 // Some portions generated by Gemini (Gemini 2.0 Flash).
+// Some portions generated by Claude Code (Opus 5).
 
 
 /**************************************************************************/
@@ -556,6 +557,7 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(UINT i
 {
 #ifdef TX_PORT_USE_BASEPRI
     __set_basepri_value(int_posture);
+    __asm__ volatile ("" : : : "memory");
 #else
     __asm__ volatile ("MSR  PRIMASK,%0": : "r" (int_posture): "memory");
 #endif
diff --git a/ports/cortex_m33/iar/inc/tx_port.h b/ports/cortex_m33/iar/inc/tx_port.h
index a5667779c..6527b34a1 100644
--- a/ports/cortex_m33/iar/inc/tx_port.h
+++ b/ports/cortex_m33/iar/inc/tx_port.h
@@ -10,6 +10,7 @@
  **************************************************************************/
 
 // Some portions generated by Gemini (Gemini 2.0 Flash).
+// Some portions generated by Claude Code (Opus 5).
 
 
 /**************************************************************************/
@@ -592,6 +593,7 @@ UINT interrupt_save;
         __enable_interrupts();
 #endif
         __restore_interrupt(interrupt_save);
+        __asm__ volatile ("isb 0xF " : : : "memory");
     }
 }
 
diff --git a/ports/cortex_m33/iar/src/tx_thread_system_return.s b/ports/cortex_m33/iar/src/tx_thread_system_return.s
index 83eb4a66a..89f086fc5 100644
--- a/ports/cortex_m33/iar/src/tx_thread_system_return.s
+++ b/ports/cortex_m33/iar/src/tx_thread_system_return.s
@@ -82,10 +82,12 @@ _tx_thread_system_return:
     MOV     r0, #0
     MSR     BASEPRI, r0                             // Enable interrupts
     MSR     BASEPRI, r1                             // Restore original interrupt posture
+    ISB     SY                                      // Flush pipeline
 #else
     MRS     r1, PRIMASK                             // Thread context returning, pickup PRIMASK
     CPSIE   i                                       // Enable interrupts
     MSR     PRIMASK, r1                             // Restore original interrupt posture
+    ISB     SY                                      // Flush pipeline
 #endif
 _isr_context:
     BX      lr                                      // Return to caller
diff --git a/ports/cortex_m4/ac5/inc/tx_port.h b/ports/cortex_m4/ac5/inc/tx_port.h
index febc6e8fe..ea89ed1aa 100644
--- a/ports/cortex_m4/ac5/inc/tx_port.h
+++ b/ports/cortex_m4/ac5/inc/tx_port.h
@@ -9,6 +9,10 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Some portions generated by Gemini (Gemini 2.0 Flash).
+// Some portions generated by Copilot (Claude Sonnet 4.6).
+// Some portions generated by Claude Code (Opus 5).
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -539,8 +543,9 @@ unsigned int posture;
 #ifdef TX_PORT_USE_BASEPRI
 __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsigned int basepri_value)
 {
-    __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value));
+    __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value) : "memory");
 }
+
 #else
 __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
 {
@@ -552,7 +557,7 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(unsign
 {
 #ifdef TX_PORT_USE_BASEPRI
     __set_basepri_value(int_posture);
-    //__asm__ volatile ("MSR  BASEPRI,%0": : "r" (int_posture): "memory");
+    __asm__ volatile ("" : : : "memory");
 #else
     __asm__ volatile ("MSR  PRIMASK,%0": : "r" (int_posture): "memory");
 #endif
@@ -578,6 +583,7 @@ unsigned int interrupt_save;
 
     /* Set PendSV to invoke ThreadX scheduler.  */
     *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
+    __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
     if (__get_ipsr_value() == 0)
     {
         interrupt_save = __get_interrupt_posture();
@@ -587,6 +593,7 @@ unsigned int interrupt_save;
         __enable_interrupts();
 #endif
         __restore_interrupt(interrupt_save);
+        __asm__ volatile ("isb 0xF " : : : "memory");
     }
 }
 
diff --git a/ports/cortex_m4/ac6/inc/tx_port.h b/ports/cortex_m4/ac6/inc/tx_port.h
index e1d21df1a..3946fec21 100644
--- a/ports/cortex_m4/ac6/inc/tx_port.h
+++ b/ports/cortex_m4/ac6/inc/tx_port.h
@@ -545,8 +545,8 @@ __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsign
 {
     __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value) : "memory");
 }
-#else
 
+#else
 __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
 {
     __asm__ volatile ("CPSIE  i": : : "memory");
@@ -593,6 +593,7 @@ unsigned int interrupt_save;
         __enable_interrupts();
 #endif
         __restore_interrupt(interrupt_save);
+        __asm__ volatile ("isb 0xF " : : : "memory");
     }
 }
 
diff --git a/ports/cortex_m4/ac6/src/tx_thread_system_return.S b/ports/cortex_m4/ac6/src/tx_thread_system_return.S
index 4c5068ee9..59a7210d5 100644
--- a/ports/cortex_m4/ac6/src/tx_thread_system_return.S
+++ b/ports/cortex_m4/ac6/src/tx_thread_system_return.S
@@ -85,10 +85,12 @@ _tx_thread_system_return:
     MOV     r0, #0
     MSR     BASEPRI, r0                             // Enable interrupts
     MSR     BASEPRI, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #else
     MRS     r1, PRIMASK                             // Thread context returning, pickup PRIMASK
     CPSIE   i                                       // Enable interrupts
     MSR     PRIMASK, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #endif
 _isr_context:
     BX      lr                                      // Return to caller
diff --git a/ports/cortex_m4/gnu/inc/tx_port.h b/ports/cortex_m4/gnu/inc/tx_port.h
index d35a6d4ee..98d81669f 100644
--- a/ports/cortex_m4/gnu/inc/tx_port.h
+++ b/ports/cortex_m4/gnu/inc/tx_port.h
@@ -11,6 +11,7 @@
 
 // Some portions generated by Gemini (Gemini 2.0 Flash).
 // Some portions generated by Copilot (Claude Sonnet 4.6).
+// Some portions generated by Claude Code (Opus 5).
 
 
 /**************************************************************************/
@@ -544,8 +545,8 @@ __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsign
 {
     __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value) : "memory");
 }
-#else
 
+#else
 __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
 {
     __asm__ volatile ("CPSIE  i": : : "memory");
diff --git a/ports/cortex_m4/iar/inc/tx_port.h b/ports/cortex_m4/iar/inc/tx_port.h
index 84711da1e..8acba9076 100644
--- a/ports/cortex_m4/iar/inc/tx_port.h
+++ b/ports/cortex_m4/iar/inc/tx_port.h
@@ -11,6 +11,7 @@
 
 // Some portions generated by Gemini (Gemini 2.0 Flash).
 // Some portions generated by Copilot (Claude Sonnet 4.6).
+// Some portions generated by Claude Code (Opus 5).
 
 
 /**************************************************************************/
@@ -544,8 +545,8 @@ __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsign
 {
     __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value) : "memory");
 }
-#else
 
+#else
 __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
 {
     __asm__ volatile ("CPSIE  i": : : "memory");
@@ -592,8 +593,10 @@ unsigned int interrupt_save;
         __enable_interrupts();
 #endif
         __restore_interrupt(interrupt_save);
+        __asm__ volatile ("isb 0xF " : : : "memory");
     }
 }
+
 #define TX_INTERRUPT_SAVE_AREA                  UINT interrupt_save;
 #define TX_DISABLE                              interrupt_save =  __disable_interrupts();
 #define TX_RESTORE                              __restore_interrupt(interrupt_save);
diff --git a/ports/cortex_m4/iar/src/tx_thread_system_return.s b/ports/cortex_m4/iar/src/tx_thread_system_return.s
index f9a668d96..b466bacaa 100644
--- a/ports/cortex_m4/iar/src/tx_thread_system_return.s
+++ b/ports/cortex_m4/iar/src/tx_thread_system_return.s
@@ -83,10 +83,12 @@ _tx_thread_system_return:
     MOV     r0, #0
     MSR     BASEPRI, r0                             // Enable interrupts
     MSR     BASEPRI, r1                             // Restore original interrupt posture
+    ISB     SY                                      // Flush pipeline
 #else
     MRS     r1, PRIMASK                             // Thread context returning, pickup PRIMASK
     CPSIE   i                                       // Enable interrupts
     MSR     PRIMASK, r1                             // Restore original interrupt posture
+    ISB     SY                                      // Flush pipeline
 #endif
 _isr_context:
     BX      lr                                      // Return to caller
diff --git a/ports/cortex_m4/keil/inc/tx_port.h b/ports/cortex_m4/keil/inc/tx_port.h
index c502b37ea..415d5f507 100644
--- a/ports/cortex_m4/keil/inc/tx_port.h
+++ b/ports/cortex_m4/keil/inc/tx_port.h
@@ -9,6 +9,10 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Some portions generated by Gemini (Gemini 2.0 Flash).
+// Some portions generated by Copilot (Claude Sonnet 4.6).
+// Some portions generated by Claude Code (Opus 5).
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -539,8 +543,9 @@ unsigned int posture;
 #ifdef TX_PORT_USE_BASEPRI
 __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsigned int basepri_value)
 {
-    __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value));
+    __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value) : "memory");
 }
+
 #else
 __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
 {
@@ -552,7 +557,7 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(unsign
 {
 #ifdef TX_PORT_USE_BASEPRI
     __set_basepri_value(int_posture);
-    //__asm__ volatile ("MSR  BASEPRI,%0": : "r" (int_posture): "memory");
+    __asm__ volatile ("" : : : "memory");
 #else
     __asm__ volatile ("MSR  PRIMASK,%0": : "r" (int_posture): "memory");
 #endif
@@ -578,6 +583,7 @@ unsigned int interrupt_save;
 
     /* Set PendSV to invoke ThreadX scheduler.  */
     *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
+    __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
     if (__get_ipsr_value() == 0)
     {
         interrupt_save = __get_interrupt_posture();
@@ -587,6 +593,7 @@ unsigned int interrupt_save;
         __enable_interrupts();
 #endif
         __restore_interrupt(interrupt_save);
+        __asm__ volatile ("isb 0xF " : : : "memory");
     }
 }
 
diff --git a/ports/cortex_m55/ac6/inc/tx_port.h b/ports/cortex_m55/ac6/inc/tx_port.h
index 9ee2abfb8..f3cbba3a1 100644
--- a/ports/cortex_m55/ac6/inc/tx_port.h
+++ b/ports/cortex_m55/ac6/inc/tx_port.h
@@ -9,6 +9,9 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Some portions generated by Gemini (Gemini 2.0 Flash).
+// Some portions generated by Claude Code (Opus 5).
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -541,7 +544,7 @@ UINT posture;
 #ifdef TX_PORT_USE_BASEPRI
 __attribute__( ( always_inline ) ) static inline void __set_basepri_value(UINT basepri_value)
 {
-    __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value));
+    __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value) : "memory");
 }
 #else
 __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
@@ -554,6 +557,7 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(UINT i
 {
 #ifdef TX_PORT_USE_BASEPRI
     __set_basepri_value(int_posture);
+    __asm__ volatile ("" : : : "memory");
 #else
     __asm__ volatile ("MSR  PRIMASK,%0": : "r" (int_posture): "memory");
 #endif
@@ -579,6 +583,7 @@ UINT interrupt_save;
 
     /* Set PendSV to invoke ThreadX scheduler.  */
     *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
+    __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
     if (_tx_ipsr_get() == 0)
     {
         interrupt_save = __get_interrupt_posture();
@@ -588,6 +593,7 @@ UINT interrupt_save;
         __enable_interrupts();
 #endif
         __restore_interrupt(interrupt_save);
+        __asm__ volatile ("isb 0xF " : : : "memory");
     }
 }
 
diff --git a/ports/cortex_m55/ac6/src/tx_thread_system_return.S b/ports/cortex_m55/ac6/src/tx_thread_system_return.S
index a27c2756e..a72a9a418 100644
--- a/ports/cortex_m55/ac6/src/tx_thread_system_return.S
+++ b/ports/cortex_m55/ac6/src/tx_thread_system_return.S
@@ -9,6 +9,8 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Some portions generated by Gemini (Gemini 2.0 Flash).
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -74,6 +76,8 @@ _tx_thread_system_return:
     MOV     r0, #0x10000000                         // Load PENDSVSET bit
     MOV     r1, #0xE000E000                         // Load NVIC base
     STR     r0, [r1, #0xD04]                        // Set PENDSVBIT in ICSR
+    DSB     #0xF                                    // Ensure memory access is complete
+    ISB     #0xF                                    // Flush pipeline
     MRS     r0, IPSR                                // Pickup IPSR
     CMP     r0, #0                                  // Is it a thread returning?
     BNE     _isr_context                            // If ISR, skip interrupt enable
@@ -82,10 +86,12 @@ _tx_thread_system_return:
     MOV     r0, #0
     MSR     BASEPRI, r0                             // Enable interrupts
     MSR     BASEPRI, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #else
     MRS     r1, PRIMASK                             // Thread context returning, pickup PRIMASK
     CPSIE   i                                       // Enable interrupts
     MSR     PRIMASK, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #endif
 _isr_context:
     BX      lr                                      // Return to caller
diff --git a/ports/cortex_m55/gnu/inc/tx_port.h b/ports/cortex_m55/gnu/inc/tx_port.h
index 9ceac0915..3f91c12d4 100644
--- a/ports/cortex_m55/gnu/inc/tx_port.h
+++ b/ports/cortex_m55/gnu/inc/tx_port.h
@@ -10,6 +10,7 @@
  **************************************************************************/
 
 // Some portions generated by Gemini (Gemini 2.0 Flash).
+// Some portions generated by Claude Code (Opus 5).
 
 
 /**************************************************************************/
diff --git a/ports/cortex_m55/iar/inc/tx_port.h b/ports/cortex_m55/iar/inc/tx_port.h
index 786cef0a7..3ff916b30 100644
--- a/ports/cortex_m55/iar/inc/tx_port.h
+++ b/ports/cortex_m55/iar/inc/tx_port.h
@@ -9,6 +9,9 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Some portions generated by Gemini (Gemini 2.0 Flash).
+// Some portions generated by Claude Code (Opus 5).
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -541,7 +544,7 @@ UINT posture;
 #ifdef TX_PORT_USE_BASEPRI
 __attribute__( ( always_inline ) ) static inline void __set_basepri_value(UINT basepri_value)
 {
-    __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value));
+    __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value) : "memory");
 }
 #else
 __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
@@ -554,6 +557,7 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(UINT i
 {
 #ifdef TX_PORT_USE_BASEPRI
     __set_basepri_value(int_posture);
+    __asm__ volatile ("" : : : "memory");
 #else
     __asm__ volatile ("MSR  PRIMASK,%0": : "r" (int_posture): "memory");
 #endif
@@ -589,6 +593,7 @@ UINT interrupt_save;
         __enable_interrupts();
 #endif
         __restore_interrupt(interrupt_save);
+        __asm__ volatile ("isb 0xF " : : : "memory");
     }
 }
 
diff --git a/ports/cortex_m55/iar/src/tx_thread_system_return.s b/ports/cortex_m55/iar/src/tx_thread_system_return.s
index 20493afcb..cb311a479 100644
--- a/ports/cortex_m55/iar/src/tx_thread_system_return.s
+++ b/ports/cortex_m55/iar/src/tx_thread_system_return.s
@@ -82,10 +82,12 @@ _tx_thread_system_return:
     MOV     r0, #0
     MSR     BASEPRI, r0                             // Enable interrupts
     MSR     BASEPRI, r1                             // Restore original interrupt posture
+    ISB     SY                                      // Flush pipeline
 #else
     MRS     r1, PRIMASK                             // Thread context returning, pickup PRIMASK
     CPSIE   i                                       // Enable interrupts
     MSR     PRIMASK, r1                             // Restore original interrupt posture
+    ISB     SY                                      // Flush pipeline
 #endif
 _isr_context:
     BX      lr                                      // Return to caller
diff --git a/ports/cortex_m7/ac5/inc/tx_port.h b/ports/cortex_m7/ac5/inc/tx_port.h
index 1a8679569..8f84e7fe7 100644
--- a/ports/cortex_m7/ac5/inc/tx_port.h
+++ b/ports/cortex_m7/ac5/inc/tx_port.h
@@ -9,6 +9,10 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Some portions generated by Gemini (Gemini 2.0 Flash).
+// Some portions generated by Copilot (Claude Sonnet 4.6).
+// Some portions generated by Claude Code (Opus 5).
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -539,8 +543,9 @@ unsigned int posture;
 #ifdef TX_PORT_USE_BASEPRI
 __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsigned int basepri_value)
 {
-    __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value));
+    __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value) : "memory");
 }
+
 #else
 __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
 {
@@ -552,7 +557,7 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(unsign
 {
 #ifdef TX_PORT_USE_BASEPRI
     __set_basepri_value(int_posture);
-    //__asm__ volatile ("MSR  BASEPRI,%0": : "r" (int_posture): "memory");
+    __asm__ volatile ("" : : : "memory");
 #else
     __asm__ volatile ("MSR  PRIMASK,%0": : "r" (int_posture): "memory");
 #endif
@@ -578,6 +583,7 @@ unsigned int interrupt_save;
 
     /* Set PendSV to invoke ThreadX scheduler.  */
     *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
+    __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
     if (__get_ipsr_value() == 0)
     {
         interrupt_save = __get_interrupt_posture();
@@ -587,6 +593,7 @@ unsigned int interrupt_save;
         __enable_interrupts();
 #endif
         __restore_interrupt(interrupt_save);
+        __asm__ volatile ("isb 0xF " : : : "memory");
     }
 }
 
diff --git a/ports/cortex_m7/ac6/inc/tx_port.h b/ports/cortex_m7/ac6/inc/tx_port.h
index f3947f71b..bf2276eb0 100644
--- a/ports/cortex_m7/ac6/inc/tx_port.h
+++ b/ports/cortex_m7/ac6/inc/tx_port.h
@@ -11,6 +11,7 @@
 
 // Some portions generated by Gemini (Gemini 2.0 Flash).
 // Some portions generated by Copilot (Claude Sonnet 4.6).
+// Some portions generated by Claude Code (Opus 5).
 
 
 /**************************************************************************/
@@ -544,8 +545,8 @@ __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsign
 {
     __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value) : "memory");
 }
-#else
 
+#else
 __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
 {
     __asm__ volatile ("CPSIE  i": : : "memory");
@@ -592,8 +593,10 @@ unsigned int interrupt_save;
         __enable_interrupts();
 #endif
         __restore_interrupt(interrupt_save);
+        __asm__ volatile ("isb 0xF " : : : "memory");
     }
 }
+
 #define TX_INTERRUPT_SAVE_AREA                  UINT interrupt_save;
 #define TX_DISABLE                              interrupt_save =  __disable_interrupts();
 #define TX_RESTORE                              __restore_interrupt(interrupt_save);
diff --git a/ports/cortex_m7/ac6/src/tx_thread_system_return.S b/ports/cortex_m7/ac6/src/tx_thread_system_return.S
index a092e34c8..d0243dea6 100644
--- a/ports/cortex_m7/ac6/src/tx_thread_system_return.S
+++ b/ports/cortex_m7/ac6/src/tx_thread_system_return.S
@@ -85,10 +85,12 @@ _tx_thread_system_return:
     MOV     r0, #0
     MSR     BASEPRI, r0                             // Enable interrupts
     MSR     BASEPRI, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #else
     MRS     r1, PRIMASK                             // Thread context returning, pickup PRIMASK
     CPSIE   i                                       // Enable interrupts
     MSR     PRIMASK, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #endif
 _isr_context:
     BX      lr                                      // Return to caller
diff --git a/ports/cortex_m7/gnu/inc/tx_port.h b/ports/cortex_m7/gnu/inc/tx_port.h
index b6fd6e482..b01873cf1 100644
--- a/ports/cortex_m7/gnu/inc/tx_port.h
+++ b/ports/cortex_m7/gnu/inc/tx_port.h
@@ -11,6 +11,7 @@
 
 // Some portions generated by Gemini (Gemini 2.0 Flash).
 // Some portions generated by Copilot (Claude Sonnet 4.6).
+// Some portions generated by Claude Code (Opus 5).
 
 
 /**************************************************************************/
@@ -544,8 +545,8 @@ __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsign
 {
     __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value) : "memory");
 }
-#else
 
+#else
 __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
 {
     __asm__ volatile ("CPSIE  i": : : "memory");
@@ -562,7 +563,6 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(unsign
 #endif
 }
 
-
 __attribute__( ( always_inline ) ) static inline unsigned int __disable_interrupts(void)
 {
 unsigned int int_posture;
diff --git a/ports/cortex_m7/iar/inc/tx_port.h b/ports/cortex_m7/iar/inc/tx_port.h
index b6f19933f..a9ebe3c88 100644
--- a/ports/cortex_m7/iar/inc/tx_port.h
+++ b/ports/cortex_m7/iar/inc/tx_port.h
@@ -11,6 +11,7 @@
 
 // Some portions generated by Gemini (Gemini 2.0 Flash).
 // Some portions generated by Copilot (Claude Sonnet 4.6).
+// Some portions generated by Claude Code (Opus 5).
 
 
 /**************************************************************************/
@@ -544,8 +545,8 @@ __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsign
 {
     __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value) : "memory");
 }
-#else
 
+#else
 __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
 {
     __asm__ volatile ("CPSIE  i": : : "memory");
@@ -592,8 +593,10 @@ unsigned int interrupt_save;
         __enable_interrupts();
 #endif
         __restore_interrupt(interrupt_save);
+        __asm__ volatile ("isb 0xF " : : : "memory");
     }
 }
+
 #define TX_INTERRUPT_SAVE_AREA                  UINT interrupt_save;
 #define TX_DISABLE                              interrupt_save =  __disable_interrupts();
 #define TX_RESTORE                              __restore_interrupt(interrupt_save);
diff --git a/ports/cortex_m7/iar/src/tx_thread_system_return.s b/ports/cortex_m7/iar/src/tx_thread_system_return.s
index 00a07ea87..345fca808 100644
--- a/ports/cortex_m7/iar/src/tx_thread_system_return.s
+++ b/ports/cortex_m7/iar/src/tx_thread_system_return.s
@@ -83,10 +83,12 @@ _tx_thread_system_return:
     MOV     r0, #0
     MSR     BASEPRI, r0                             // Enable interrupts
     MSR     BASEPRI, r1                             // Restore original interrupt posture
+    ISB     SY                                      // Flush pipeline
 #else
     MRS     r1, PRIMASK                             // Thread context returning, pickup PRIMASK
     CPSIE   i                                       // Enable interrupts
     MSR     PRIMASK, r1                             // Restore original interrupt posture
+    ISB     SY                                      // Flush pipeline
 #endif
 _isr_context:
     BX      lr                                      // Return to caller
diff --git a/ports/cortex_m85/ac6/inc/tx_port.h b/ports/cortex_m85/ac6/inc/tx_port.h
index 90917cbf3..38def972b 100644
--- a/ports/cortex_m85/ac6/inc/tx_port.h
+++ b/ports/cortex_m85/ac6/inc/tx_port.h
@@ -9,6 +9,9 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Some portions generated by Gemini (Gemini 2.0 Flash).
+// Some portions generated by Claude Code (Opus 5).
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -541,7 +544,7 @@ UINT posture;
 #ifdef TX_PORT_USE_BASEPRI
 __attribute__( ( always_inline ) ) static inline void __set_basepri_value(UINT basepri_value)
 {
-    __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value));
+    __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value) : "memory");
 }
 #else
 __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
@@ -554,6 +557,7 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(UINT i
 {
 #ifdef TX_PORT_USE_BASEPRI
     __set_basepri_value(int_posture);
+    __asm__ volatile ("" : : : "memory");
 #else
     __asm__ volatile ("MSR  PRIMASK,%0": : "r" (int_posture): "memory");
 #endif
@@ -579,6 +583,7 @@ UINT interrupt_save;
 
     /* Set PendSV to invoke ThreadX scheduler.  */
     *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
+    __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
     if (_tx_ipsr_get() == 0)
     {
         interrupt_save = __get_interrupt_posture();
@@ -588,6 +593,7 @@ UINT interrupt_save;
         __enable_interrupts();
 #endif
         __restore_interrupt(interrupt_save);
+        __asm__ volatile ("isb 0xF " : : : "memory");
     }
 }
 
diff --git a/ports/cortex_m85/ac6/src/tx_thread_system_return.S b/ports/cortex_m85/ac6/src/tx_thread_system_return.S
index 2b335f8d3..639af9fbb 100644
--- a/ports/cortex_m85/ac6/src/tx_thread_system_return.S
+++ b/ports/cortex_m85/ac6/src/tx_thread_system_return.S
@@ -9,6 +9,8 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Some portions generated by Gemini (Gemini 2.0 Flash).
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -74,6 +76,8 @@ _tx_thread_system_return:
     MOV     r0, #0x10000000                         // Load PENDSVSET bit
     MOV     r1, #0xE000E000                         // Load NVIC base
     STR     r0, [r1, #0xD04]                        // Set PENDSVBIT in ICSR
+    DSB     #0xF                                    // Ensure memory access is complete
+    ISB     #0xF                                    // Flush pipeline
     MRS     r0, IPSR                                // Pickup IPSR
     CMP     r0, #0                                  // Is it a thread returning?
     BNE     _isr_context                            // If ISR, skip interrupt enable
@@ -82,10 +86,12 @@ _tx_thread_system_return:
     MOV     r0, #0
     MSR     BASEPRI, r0                             // Enable interrupts
     MSR     BASEPRI, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #else
     MRS     r1, PRIMASK                             // Thread context returning, pickup PRIMASK
     CPSIE   i                                       // Enable interrupts
     MSR     PRIMASK, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #endif
 _isr_context:
     BX      lr                                      // Return to caller
diff --git a/ports/cortex_m85/gnu/inc/tx_port.h b/ports/cortex_m85/gnu/inc/tx_port.h
index 0f67673b5..1f1702dfa 100644
--- a/ports/cortex_m85/gnu/inc/tx_port.h
+++ b/ports/cortex_m85/gnu/inc/tx_port.h
@@ -10,6 +10,7 @@
  **************************************************************************/
 
 // Some portions generated by Gemini (Gemini 2.0 Flash).
+// Some portions generated by Claude Code (Opus 5).
 
 
 /**************************************************************************/
diff --git a/ports/cortex_m85/iar/inc/tx_port.h b/ports/cortex_m85/iar/inc/tx_port.h
index 2d0024ab9..26ab0c756 100644
--- a/ports/cortex_m85/iar/inc/tx_port.h
+++ b/ports/cortex_m85/iar/inc/tx_port.h
@@ -9,6 +9,9 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Some portions generated by Gemini (Gemini 2.0 Flash).
+// Some portions generated by Claude Code (Opus 5).
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -580,6 +583,7 @@ UINT interrupt_save;
 
     /* Set PendSV to invoke ThreadX scheduler.  */
     *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
+    __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
     if (_tx_ipsr_get() == 0)
     {
         interrupt_save = __get_interrupt_posture();
@@ -589,6 +593,7 @@ UINT interrupt_save;
         __enable_interrupts();
 #endif
         __restore_interrupt(interrupt_save);
+        __asm__ volatile ("isb 0xF " : : : "memory");
     }
 }
 
@@ -624,5 +629,3 @@ extern  CHAR                    _tx_version_id[];
 #endif
 
 #endif
-
-#endif
diff --git a/ports/cortex_m85/iar/src/tx_thread_system_return.s b/ports/cortex_m85/iar/src/tx_thread_system_return.s
index fcc87228c..8b62acc19 100644
--- a/ports/cortex_m85/iar/src/tx_thread_system_return.s
+++ b/ports/cortex_m85/iar/src/tx_thread_system_return.s
@@ -82,10 +82,12 @@ _tx_thread_system_return:
     MOV     r0, #0
     MSR     BASEPRI, r0                             // Enable interrupts
     MSR     BASEPRI, r1                             // Restore original interrupt posture
+    ISB     SY                                      // Flush pipeline
 #else
     MRS     r1, PRIMASK                             // Thread context returning, pickup PRIMASK
     CPSIE   i                                       // Enable interrupts
     MSR     PRIMASK, r1                             // Restore original interrupt posture
+    ISB     SY                                      // Flush pipeline
 #endif
 _isr_context:
     BX      lr                                      // Return to caller
diff --git a/ports_arch/ARMv7-M/threadx/ac6/src/tx_thread_system_return.S b/ports_arch/ARMv7-M/threadx/ac6/src/tx_thread_system_return.S
index 75d518133..ad07e2aa9 100644
--- a/ports_arch/ARMv7-M/threadx/ac6/src/tx_thread_system_return.S
+++ b/ports_arch/ARMv7-M/threadx/ac6/src/tx_thread_system_return.S
@@ -9,6 +9,8 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Some portions generated by Gemini (Gemini 2.0 Flash).
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -73,6 +75,8 @@ _tx_thread_system_return:
     MOV     r0, #0x10000000                         // Load PENDSVSET bit
     MOV     r1, #0xE000E000                         // Load NVIC base
     STR     r0, [r1, #0xD04]                        // Set PENDSVBIT in ICSR
+    DSB     #0xF                                    // Ensure memory access is complete
+    ISB     #0xF                                    // Flush pipeline
     MRS     r0, IPSR                                // Pickup IPSR
     CMP     r0, #0                                  // Is it a thread returning?
     BNE     _isr_context                            // If ISR, skip interrupt enable
@@ -81,10 +85,12 @@ _tx_thread_system_return:
     MOV     r0, #0
     MSR     BASEPRI, r0                             // Enable interrupts
     MSR     BASEPRI, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #else
     MRS     r1, PRIMASK                             // Thread context returning, pickup PRIMASK
     CPSIE   i                                       // Enable interrupts
     MSR     PRIMASK, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #endif
 _isr_context:
     BX      lr                                      // Return to caller
diff --git a/ports_arch/ARMv7-M/threadx/gnu/src/tx_thread_system_return.S b/ports_arch/ARMv7-M/threadx/gnu/src/tx_thread_system_return.S
index 8b6817478..af17e9a74 100644
--- a/ports_arch/ARMv7-M/threadx/gnu/src/tx_thread_system_return.S
+++ b/ports_arch/ARMv7-M/threadx/gnu/src/tx_thread_system_return.S
@@ -9,6 +9,8 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Some portions generated by Gemini (Gemini 2.0 Flash).
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -73,6 +75,8 @@ _tx_thread_system_return:
     MOV     r0, #0x10000000                         // Load PENDSVSET bit
     MOV     r1, #0xE000E000                         // Load NVIC base
     STR     r0, [r1, #0xD04]                        // Set PENDSVBIT in ICSR
+    DSB     #0xF                                    // Ensure memory access is complete
+    ISB     #0xF                                    // Flush pipeline
     MRS     r0, IPSR                                // Pickup IPSR
     CMP     r0, #0                                  // Is it a thread returning?
     BNE     _isr_context                            // If ISR, skip interrupt enable
@@ -81,10 +85,12 @@ _tx_thread_system_return:
     MOV     r0, #0
     MSR     BASEPRI, r0                             // Enable interrupts
     MSR     BASEPRI, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #else
     MRS     r1, PRIMASK                             // Thread context returning, pickup PRIMASK
     CPSIE   i                                       // Enable interrupts
     MSR     PRIMASK, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #endif
 _isr_context:
     BX      lr                                      // Return to caller
diff --git a/ports_arch/ARMv7-M/threadx/iar/src/tx_thread_system_return.s b/ports_arch/ARMv7-M/threadx/iar/src/tx_thread_system_return.s
index 65bec5a57..18a449325 100644
--- a/ports_arch/ARMv7-M/threadx/iar/src/tx_thread_system_return.s
+++ b/ports_arch/ARMv7-M/threadx/iar/src/tx_thread_system_return.s
@@ -1,16 +1,19 @@
-/***************************************************************************
- * Copyright (c) 2024 Microsoft Corporation
- * Copyright (c) 2026-present Eclipse ThreadX contributors
- *
- * This program and the accompanying materials are made available under the
- * terms of the MIT License which is available at
- * https://opensource.org/licenses/MIT.
- *
- * SPDX-License-Identifier: MIT
- **************************************************************************/
+;***************************************************************************
+;* Copyright (c) 2024 Microsoft Corporation
+;* Copyright (c) 2026-present Eclipse ThreadX contributors
+;*
+;* This program and the accompanying materials are made available under the
+;* terms of the MIT License which is available at
+;* https://opensource.org/licenses/MIT.
+;*
+;* SPDX-License-Identifier: MIT
+;**************************************************************************
 
+; Some portions generated by Gemini (Gemini 2.0 Flash).
+
+
+;**************************************************************************
 
-/**************************************************************************/
 /**************************************************************************/
 /**                                                                       */
 /** ThreadX Component                                                     */
@@ -70,6 +73,8 @@ _tx_thread_system_return:
     MOV     r0, #0x10000000                         // Load PENDSVSET bit
     MOV     r1, #0xE000E000                         // Load NVIC base
     STR     r0, [r1, #0xD04]                        // Set PENDSVBIT in ICSR
+    DSB     SY                                      // Ensure memory access is complete
+    ISB     SY                                      // Flush pipeline
     MRS     r0, IPSR                                // Pickup IPSR
     CMP     r0, #0                                  // Is it a thread returning?
     BNE     _isr_context                            // If ISR, skip interrupt enable
@@ -78,10 +83,12 @@ _tx_thread_system_return:
     MOV     r0, #0
     MSR     BASEPRI, r0                             // Enable interrupts
     MSR     BASEPRI, r1                             // Restore original interrupt posture
+    ISB     SY                                      // Flush pipeline
 #else
     MRS     r1, PRIMASK                             // Thread context returning, pickup PRIMASK
     CPSIE   i                                       // Enable interrupts
     MSR     PRIMASK, r1                             // Restore original interrupt posture
+    ISB     SY                                      // Flush pipeline
 #endif
 _isr_context:
     BX      lr                                      // Return to caller
diff --git a/ports_arch/ARMv7-M/threadx/inc/tx_port.h b/ports_arch/ARMv7-M/threadx/inc/tx_port.h
index ac21ab556..b988675f1 100644
--- a/ports_arch/ARMv7-M/threadx/inc/tx_port.h
+++ b/ports_arch/ARMv7-M/threadx/inc/tx_port.h
@@ -9,6 +9,10 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Some portions generated by Gemini (Gemini 2.0 Flash).
+// Some portions generated by Copilot (Claude Sonnet 4.6).
+// Some portions generated by Claude Code (Opus 5).
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -539,8 +543,9 @@ unsigned int posture;
 #ifdef TX_PORT_USE_BASEPRI
 __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsigned int basepri_value)
 {
-    __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value));
+    __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value) : "memory");
 }
+
 #else
 __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
 {
@@ -552,7 +557,7 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(unsign
 {
 #ifdef TX_PORT_USE_BASEPRI
     __set_basepri_value(int_posture);
-    //__asm__ volatile ("MSR  BASEPRI,%0": : "r" (int_posture): "memory");
+    __asm__ volatile ("" : : : "memory");
 #else
     __asm__ volatile ("MSR  PRIMASK,%0": : "r" (int_posture): "memory");
 #endif
@@ -578,6 +583,7 @@ unsigned int interrupt_save;
 
     /* Set PendSV to invoke ThreadX scheduler.  */
     *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
+    __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
     if (__get_ipsr_value() == 0)
     {
         interrupt_save = __get_interrupt_posture();
@@ -587,6 +593,7 @@ unsigned int interrupt_save;
         __enable_interrupts();
 #endif
         __restore_interrupt(interrupt_save);
+        __asm__ volatile ("isb 0xF " : : : "memory");
     }
 }
 
diff --git a/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_system_return.S b/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_system_return.S
index e31c4a557..5e2164cb0 100644
--- a/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_system_return.S
+++ b/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_system_return.S
@@ -9,6 +9,8 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Some portions generated by Gemini (Gemini 2.0 Flash).
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -74,6 +76,8 @@ _tx_thread_system_return:
     MOV     r0, #0x10000000                         // Load PENDSVSET bit
     MOV     r1, #0xE000E000                         // Load NVIC base
     STR     r0, [r1, #0xD04]                        // Set PENDSVBIT in ICSR
+    DSB     #0xF                                    // Ensure memory access is complete
+    ISB     #0xF                                    // Flush pipeline
     MRS     r0, IPSR                                // Pickup IPSR
     CMP     r0, #0                                  // Is it a thread returning?
     BNE     _isr_context                            // If ISR, skip interrupt enable
@@ -82,10 +86,12 @@ _tx_thread_system_return:
     MOV     r0, #0
     MSR     BASEPRI, r0                             // Enable interrupts
     MSR     BASEPRI, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #else
     MRS     r1, PRIMASK                             // Thread context returning, pickup PRIMASK
     CPSIE   i                                       // Enable interrupts
     MSR     PRIMASK, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #endif
 _isr_context:
     BX      lr                                      // Return to caller
diff --git a/ports_arch/ARMv8-M/threadx/gnu/CMakeLists.txt b/ports_arch/ARMv8-M/threadx/gnu/CMakeLists.txt
index 5ad3b8e75..763a2696c 100644
--- a/ports_arch/ARMv8-M/threadx/gnu/CMakeLists.txt
+++ b/ports_arch/ARMv8-M/threadx/gnu/CMakeLists.txt
@@ -1,7 +1,8 @@
-target_sources(${PROJECT_NAME} PRIVATE
+target_sources(${PROJECT_NAME}
+    PRIVATE
+    # {{BEGIN_TARGET_SOURCES}}
     ${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_secure_stack_allocate.c
     ${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_secure_stack_free.c
-    ${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.S
     ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.S
     ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S
     ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S
@@ -14,8 +15,10 @@ target_sources(${PROJECT_NAME} PRIVATE
     ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S
     ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S
     ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S
+    # {{END_TARGET_SOURCES}}
 )
 
-target_include_directories(${PROJECT_NAME} PUBLIC
-    inc
+target_include_directories(${PROJECT_NAME}
+    PUBLIC
+    ${CMAKE_CURRENT_LIST_DIR}/inc
 )
diff --git a/ports_arch/ARMv8-M/threadx/gnu/src/tx_initialize_low_level.S b/ports_arch/ARMv8-M/threadx/gnu/src/tx_initialize_low_level.S
deleted file mode 100644
index f0b326a17..000000000
--- a/ports_arch/ARMv8-M/threadx/gnu/src/tx_initialize_low_level.S
+++ /dev/null
@@ -1,276 +0,0 @@
-/***************************************************************************
- * Copyright (c) 2024 Microsoft Corporation
- * Copyright (c) 2026-present Eclipse ThreadX contributors
- *
- * This program and the accompanying materials are made available under the
- * terms of the MIT License which is available at
- * https://opensource.org/licenses/MIT.
- *
- * SPDX-License-Identifier: MIT
- **************************************************************************/
-
-
-/**************************************************************************/
-/**************************************************************************/
-/**                                                                       */
-/** ThreadX Component                                                     */
-/**                                                                       */
-/**   Initialize                                                          */
-/**                                                                       */
-/**************************************************************************/
-/**************************************************************************/
-
-#ifdef TX_INCLUDE_USER_DEFINE_FILE
-#include "tx_user.h"
-#endif
-
-SYSTEM_CLOCK        =     6000000
-SYSTICK_CYCLES      =     ((SYSTEM_CLOCK / 100) -1)
-
-/* Setup the stack and heap areas.  */
-
-STACK_SIZE          =     0x00000400
-HEAP_SIZE           =     0x00000000
-
-/**************************************************************************/
-/*                                                                        */
-/*  FUNCTION                                               RELEASE        */
-/*                                                                        */
-/*    _tx_initialize_low_level                          Cortex-Mxx/GNU    */
-/*                                                           6.2.1        */
-/*  AUTHOR                                                                */
-/*                                                                        */
-/*    Scott Larson, Microsoft Corporation                                 */
-/*                                                                        */
-/*  DESCRIPTION                                                           */
-/*                                                                        */
-/*    This function is responsible for any low-level processor            */
-/*    initialization, including setting up interrupt vectors, setting     */
-/*    up a periodic timer interrupt source, saving the system stack       */
-/*    pointer for use in ISR processing later, and finding the first      */
-/*    available RAM memory address for tx_application_define.             */
-/*                                                                        */
-/*  INPUT                                                                 */
-/*                                                                        */
-/*    None                                                                */
-/*                                                                        */
-/*  OUTPUT                                                                */
-/*                                                                        */
-/*    None                                                                */
-/*                                                                        */
-/*  CALLS                                                                 */
-/*                                                                        */
-/*    None                                                                */
-/*                                                                        */
-/*  CALLED BY                                                             */
-/*                                                                        */
-/*    _tx_initialize_kernel_enter           ThreadX entry function        */
-/*                                                                        */
-/**************************************************************************/
-// VOID   _tx_initialize_low_level(VOID)
-// {
-    .section .text
-    .balign 4
-    .syntax unified
-    .eabi_attribute Tag_ABI_align_preserved, 1
-    .global  _tx_initialize_low_level
-    .thumb_func
-.type _tx_initialize_low_level, function
-_tx_initialize_low_level:
-
-    /* Disable interrupts during ThreadX initialization.  */
-    CPSID   i
-
-    /* Set base of available memory to end of non-initialised RAM area.  */
-    LDR     r0, =_tx_initialize_unused_memory       // Build address of unused memory pointer
-    LDR     r1, =__RAM_segment_used_end__           // Build first free address
-    ADD     r1, r1, #4                              //
-    STR     r1, [r0]                                // Setup first unused memory pointer
-
-    /* Setup Vector Table Offset Register.  */
-    MOV     r0, #0xE000E000                         // Build address of NVIC registers
-    LDR     r1, =_vectors                           // Pickup address of vector table
-    STR     r1, [r0, #0xD08]                        // Set vector table address
-
-    /* Enable the cycle count register.  */
-    LDR     r0, =0xE0001000                         // Build address of DWT register
-    LDR     r1, [r0]                                // Pickup the current value
-    ORR     r1, r1, #1                              // Set the CYCCNTENA bit
-    STR     r1, [r0]                                // Enable the cycle count register
-
-    /* Set system stack pointer from vector value.  */
-    LDR     r0, =_tx_thread_system_stack_ptr        // Build address of system stack pointer
-    LDR     r1, =_vectors                           // Pickup address of vector table
-    LDR     r1, [r1]                                // Pickup reset stack pointer
-    STR     r1, [r0]                                // Save system stack pointer
-
-    /* Configure SysTick.  */
-    MOV     r0, #0xE000E000                         // Build address of NVIC registers
-    MOV     r1, #0                                  // Build value for SysTick reset
-    STR     r1, [r0, #0x10]                         // Reset SysTick Control
-    STR     r1, [r0, #0x18]                         // Reset SysTick Counter Value
-    LDR     r1, =SYSTICK_CYCLES
-    STR     r1, [r0, #0x14]                         // Setup SysTick Reload Value
-    MOV     r1, #0x7                                // Build SysTick Control Enable Value
-    STR     r1, [r0, #0x10]                         // Setup SysTick Control
-
-    /* Configure handler priorities.  */
-    LDR     r1, =0x00000000                         // Rsrv, UsgF, BusF, MemM
-    STR     r1, [r0, #0xD18]                        // Setup System Handlers 4-7 Priority Registers
-    LDR     r1, =0xFF000000                         // SVCl, Rsrv, Rsrv, Rsrv
-    STR     r1, [r0, #0xD1C]                        // Setup System Handlers 8-11 Priority Registers
-                                                    // Note: SVC must be lowest priority, which is 0xFF
-    LDR     r1, =0x40FF0000                         // SysT, PnSV, Rsrv, DbgM
-    STR     r1, [r0, #0xD20]                        // Setup System Handlers 12-15 Priority Registers
-                                                    // Note: PnSV must be lowest priority, which is 0xFF
-
-    /* Return to caller.  */
-    BX      lr
-// }
-
-
-/* Define shells for each of the unused vectors.  */
-    .section .text
-    .balign 4
-    .syntax unified
-    .eabi_attribute Tag_ABI_align_preserved, 1
-    .global  __tx_BadHandler
-    .thumb_func
-.type __tx_BadHandler, function
-__tx_BadHandler:
-    B       __tx_BadHandler
-
-
-    .section .text
-    .balign 4
-    .syntax unified
-    .eabi_attribute Tag_ABI_align_preserved, 1
-    .global  __tx_IntHandler
-    .thumb_func
-.type __tx_IntHandler, function
-__tx_IntHandler:
-// VOID InterruptHandler (VOID)
-// {
-    PUSH    {r0,lr}     // Save LR (and dummy r0 to maintain stack alignment)
-#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
-    BL      _tx_execution_isr_enter             // Call the ISR enter function
-#endif
-    /* Do interrupt handler work here */
-    /* .... */
-#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
-    BL      _tx_execution_isr_exit              // Call the ISR exit function
-#endif
-    POP     {r0,lr}
-    BX      lr
-// }
-
-
-    .section .text
-    .balign 4
-    .syntax unified
-    .eabi_attribute Tag_ABI_align_preserved, 1
-    .global  SysTick_Handler
-    .thumb_func
-.type SysTick_Handler, function
-SysTick_Handler:
-// VOID TimerInterruptHandler (VOID)
-// {
-    PUSH    {r0,lr}     // Save LR (and dummy r0 to maintain stack alignment)
-#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
-    BL      _tx_execution_isr_enter             // Call the ISR enter function
-#endif
-    BL      _tx_timer_interrupt
-#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
-    BL      _tx_execution_isr_exit              // Call the ISR exit function
-#endif
-    POP     {r0,lr}
-    BX      lr
-// }
-
-
-    .section .text
-    .balign 4
-    .syntax unified
-    .eabi_attribute Tag_ABI_align_preserved, 1
-    .global  HardFault_Handler
-    .thumb_func
-.type HardFault_Handler, function
-HardFault_Handler:
-    B       HardFault_Handler
-
-
-    .section .text
-    .balign 4
-    .syntax unified
-    .eabi_attribute Tag_ABI_align_preserved, 1
-    .global  UsageFault_Handler
-    .thumb_func
-.type UsageFault_Handler, function
-UsageFault_Handler:
-    CPSID   i                                       // Disable interrupts
-    // Check for stack limit fault
-    LDR     r0, =0xE000ED28                         // CFSR address
-    LDR     r1,[r0]                                 // Pick up CFSR
-    TST     r1, #0x00100000                         // Check for Stack Overflow
-_unhandled_usage_loop:
-    BEQ     _unhandled_usage_loop                   // If not stack overflow then loop
-
-    // Handle stack overflow
-    STR     r1, [r0]                                // Clear CFSR flag(s)
-
-#ifdef __ARM_FP
-    LDR     r0, =0xE000EF34                         // Cleanup FPU context: Load FPCCR address
-    LDR     r1, [r0]                                // Load FPCCR
-    BIC     r1, r1, #1                              // Clear the lazy preservation active bit
-    STR     r1, [r0]                                // Store the value
-#endif
-
-    LDR     r0, =_tx_thread_current_ptr             // Build current thread pointer address
-    LDR     r0,[r0]                                 // Pick up current thread pointer
-    PUSH    {r0,lr}                                 // Save LR (and r0 to maintain stack alignment)
-    BL      _tx_thread_stack_error_handler          // Call ThreadX/user handler
-    POP     {r0,lr}                                 // Restore LR and dummy reg
-
-#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
-    // Call the thread exit function to indicate the thread is no longer executing.
-    PUSH    {r0, lr}                                // Save LR (and r0 just for alignment)
-    BL      _tx_execution_thread_exit               // Call the thread exit function
-    POP     {r0, lr}                                // Recover LR
-#endif
-
-    MOV     r1, #0                                  // Build NULL value
-    LDR     r0, =_tx_thread_current_ptr             // Pickup address of current thread pointer
-    STR     r1, [r0]                                // Clear current thread pointer
-
-    // Return from UsageFault_Handler exception
-    LDR     r0, =0xE000ED04                         // Load ICSR
-    LDR     r1, =0x10000000                         // Set PENDSVSET bit
-    STR     r1, [r0]                                // Store ICSR
-    DSB                                             // Wait for memory access to complete
-    CPSIE   i                                       // Enable interrupts
-    BX      lr                                      // Return from exception
-
-
-
-    .section .text
-    .balign 4
-    .syntax unified
-    .eabi_attribute Tag_ABI_align_preserved, 1
-    .global  __tx_NMIHandler
-    .thumb_func
-.type __tx_NMIHandler, function
-__tx_NMIHandler:
-    B       __tx_NMIHandler
-
-
-    .section .text
-    .balign 4
-    .syntax unified
-    .eabi_attribute Tag_ABI_align_preserved, 1
-    .global  __tx_DBGHandler
-    .thumb_func
-.type __tx_DBGHandler, function
-__tx_DBGHandler:
-    B       __tx_DBGHandler
-
-    .end
diff --git a/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_system_return.S b/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_system_return.S
index 1e84582eb..420a6ef39 100644
--- a/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_system_return.S
+++ b/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_system_return.S
@@ -9,6 +9,8 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Some portions generated by Gemini (Gemini 2.0 Flash).
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -74,6 +76,8 @@ _tx_thread_system_return:
     MOV     r0, #0x10000000                         // Load PENDSVSET bit
     MOV     r1, #0xE000E000                         // Load NVIC base
     STR     r0, [r1, #0xD04]                        // Set PENDSVBIT in ICSR
+    DSB     #0xF                                    // Ensure memory access is complete
+    ISB     #0xF                                    // Flush pipeline
     MRS     r0, IPSR                                // Pickup IPSR
     CMP     r0, #0                                  // Is it a thread returning?
     BNE     _isr_context                            // If ISR, skip interrupt enable
@@ -82,10 +86,12 @@ _tx_thread_system_return:
     MOV     r0, #0
     MSR     BASEPRI, r0                             // Enable interrupts
     MSR     BASEPRI, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #else
     MRS     r1, PRIMASK                             // Thread context returning, pickup PRIMASK
     CPSIE   i                                       // Enable interrupts
     MSR     PRIMASK, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #endif
 _isr_context:
     BX      lr                                      // Return to caller
diff --git a/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_system_return.s b/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_system_return.s
index f2a187ea0..4bc165238 100644
--- a/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_system_return.s
+++ b/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_system_return.s
@@ -1,16 +1,19 @@
-/***************************************************************************
- * Copyright (c) 2024 Microsoft Corporation
- * Copyright (c) 2026-present Eclipse ThreadX contributors
- *
- * This program and the accompanying materials are made available under the
- * terms of the MIT License which is available at
- * https://opensource.org/licenses/MIT.
- *
- * SPDX-License-Identifier: MIT
- **************************************************************************/
+;***************************************************************************
+;* Copyright (c) 2024 Microsoft Corporation
+;* Copyright (c) 2026-present Eclipse ThreadX contributors
+;*
+;* This program and the accompanying materials are made available under the
+;* terms of the MIT License which is available at
+;* https://opensource.org/licenses/MIT.
+;*
+;* SPDX-License-Identifier: MIT
+;**************************************************************************
 
+; Some portions generated by Gemini (Gemini 2.0 Flash).
+
+
+;**************************************************************************
 
-/**************************************************************************/
 /**************************************************************************/
 /**                                                                       */
 /** ThreadX Component                                                     */
@@ -69,6 +72,8 @@ _tx_thread_system_return:
     MOV     r0, #0x10000000                         // Load PENDSVSET bit
     MOV     r1, #0xE000E000                         // Load NVIC base
     STR     r0, [r1, #0xD04]                        // Set PENDSVBIT in ICSR
+    DSB     SY                                      // Ensure memory access is complete
+    ISB     SY                                      // Flush pipeline
     MRS     r0, IPSR                                // Pickup IPSR
     CMP     r0, #0                                  // Is it a thread returning?
     BNE     _isr_context                            // If ISR, skip interrupt enable
@@ -77,10 +82,12 @@ _tx_thread_system_return:
     MOV     r0, #0
     MSR     BASEPRI, r0                             // Enable interrupts
     MSR     BASEPRI, r1                             // Restore original interrupt posture
+    ISB     SY                                      // Flush pipeline
 #else
     MRS     r1, PRIMASK                             // Thread context returning, pickup PRIMASK
     CPSIE   i                                       // Enable interrupts
     MSR     PRIMASK, r1                             // Restore original interrupt posture
+    ISB     SY                                      // Flush pipeline
 #endif
 _isr_context:
     BX      lr                                      // Return to caller
diff --git a/ports_arch/ARMv8-M/threadx/inc/tx_port.h b/ports_arch/ARMv8-M/threadx/inc/tx_port.h
index 316da65b7..1f088d412 100644
--- a/ports_arch/ARMv8-M/threadx/inc/tx_port.h
+++ b/ports_arch/ARMv8-M/threadx/inc/tx_port.h
@@ -9,6 +9,9 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Some portions generated by Gemini (Gemini 2.0 Flash).
+// Some portions generated by Claude Code (Opus 5).
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -541,7 +544,7 @@ UINT posture;
 #ifdef TX_PORT_USE_BASEPRI
 __attribute__( ( always_inline ) ) static inline void __set_basepri_value(UINT basepri_value)
 {
-    __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value));
+    __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value) : "memory");
 }
 #else
 __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
@@ -554,6 +557,7 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(UINT i
 {
 #ifdef TX_PORT_USE_BASEPRI
     __set_basepri_value(int_posture);
+    __asm__ volatile ("" : : : "memory");
 #else
     __asm__ volatile ("MSR  PRIMASK,%0": : "r" (int_posture): "memory");
 #endif
@@ -579,6 +583,7 @@ UINT interrupt_save;
 
     /* Set PendSV to invoke ThreadX scheduler.  */
     *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
+    __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
     if (_tx_ipsr_get() == 0)
     {
         interrupt_save = __get_interrupt_posture();
@@ -588,6 +593,7 @@ UINT interrupt_save;
         __enable_interrupts();
 #endif
         __restore_interrupt(interrupt_save);
+        __asm__ volatile ("isb 0xF " : : : "memory");
     }
 }
 
diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_system_return.S
index e1c5c2a2c..6d0e26afa 100644
--- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_system_return.S
+++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_system_return.S
@@ -9,6 +9,8 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Some portions generated by Gemini (Gemini 2.0 Flash).
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -73,6 +75,8 @@ _tx_thread_system_return:
     MOV     r0, #0x10000000                         // Load PENDSVSET bit
     MOV     r1, #0xE000E000                         // Load NVIC base
     STR     r0, [r1, #0xD04]                        // Set PENDSVBIT in ICSR
+    DSB     #0xF                                    // Ensure memory access is complete
+    ISB     #0xF                                    // Flush pipeline
     MRS     r0, IPSR                                // Pickup IPSR
     CMP     r0, #0                                  // Is it a thread returning?
     BNE     _isr_context                            // If ISR, skip interrupt enable
@@ -81,10 +85,12 @@ _tx_thread_system_return:
     MOV     r0, #0
     MSR     BASEPRI, r0                             // Enable interrupts
     MSR     BASEPRI, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #else
     MRS     r1, PRIMASK                             // Thread context returning, pickup PRIMASK
     CPSIE   i                                       // Enable interrupts
     MSR     PRIMASK, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #endif
 _isr_context:
     BX      lr                                      // Return to caller
diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_system_return.S
index 9d9a32fc9..92ad3f628 100644
--- a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_system_return.S
+++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_system_return.S
@@ -9,6 +9,8 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Some portions generated by Gemini (Gemini 2.0 Flash).
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -73,6 +75,8 @@ _tx_thread_system_return:
     MOV     r0, #0x10000000                         // Load PENDSVSET bit
     MOV     r1, #0xE000E000                         // Load NVIC base
     STR     r0, [r1, #0xD04]                        // Set PENDSVBIT in ICSR
+    DSB     #0xF                                    // Ensure memory access is complete
+    ISB     #0xF                                    // Flush pipeline
     MRS     r0, IPSR                                // Pickup IPSR
     CMP     r0, #0                                  // Is it a thread returning?
     BNE     _isr_context                            // If ISR, skip interrupt enable
@@ -81,10 +85,12 @@ _tx_thread_system_return:
     MOV     r0, #0
     MSR     BASEPRI, r0                             // Enable interrupts
     MSR     BASEPRI, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #else
     MRS     r1, PRIMASK                             // Thread context returning, pickup PRIMASK
     CPSIE   i                                       // Enable interrupts
     MSR     PRIMASK, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #endif
 _isr_context:
     BX      lr                                      // Return to caller
diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_system_return.s
index 712a6e5ce..7bc5f2ebc 100644
--- a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_system_return.s
+++ b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_system_return.s
@@ -1,16 +1,19 @@
-/***************************************************************************
- * Copyright (c) 2024 Microsoft Corporation
- * Copyright (c) 2026-present Eclipse ThreadX contributors
- *
- * This program and the accompanying materials are made available under the
- * terms of the MIT License which is available at
- * https://opensource.org/licenses/MIT.
- *
- * SPDX-License-Identifier: MIT
- **************************************************************************/
+;***************************************************************************
+;* Copyright (c) 2024 Microsoft Corporation
+;* Copyright (c) 2026-present Eclipse ThreadX contributors
+;*
+;* This program and the accompanying materials are made available under the
+;* terms of the MIT License which is available at
+;* https://opensource.org/licenses/MIT.
+;*
+;* SPDX-License-Identifier: MIT
+;**************************************************************************
 
+; Some portions generated by Gemini (Gemini 2.0 Flash).
+
+
+;**************************************************************************
 
-/**************************************************************************/
 /**************************************************************************/
 /**                                                                       */
 /** ThreadX Component                                                     */
@@ -70,6 +73,8 @@ _tx_thread_system_return:
     MOV     r0, #0x10000000                         // Load PENDSVSET bit
     MOV     r1, #0xE000E000                         // Load NVIC base
     STR     r0, [r1, #0xD04]                        // Set PENDSVBIT in ICSR
+    DSB     SY                                      // Ensure memory access is complete
+    ISB     SY                                      // Flush pipeline
     MRS     r0, IPSR                                // Pickup IPSR
     CMP     r0, #0                                  // Is it a thread returning?
     BNE     _isr_context                            // If ISR, skip interrupt enable
@@ -78,10 +83,12 @@ _tx_thread_system_return:
     MOV     r0, #0
     MSR     BASEPRI, r0                             // Enable interrupts
     MSR     BASEPRI, r1                             // Restore original interrupt posture
+    ISB     SY                                      // Flush pipeline
 #else
     MRS     r1, PRIMASK                             // Thread context returning, pickup PRIMASK
     CPSIE   i                                       // Enable interrupts
     MSR     PRIMASK, r1                             // Restore original interrupt posture
+    ISB     SY                                      // Flush pipeline
 #endif
 _isr_context:
     BX      lr                                      // Return to caller
diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_system_return.S
index b4348f9db..59a7210d5 100644
--- a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_system_return.S
+++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_system_return.S
@@ -9,6 +9,8 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Some portions generated by Gemini (Gemini 2.0 Flash).
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -73,6 +75,8 @@ _tx_thread_system_return:
     MOV     r0, #0x10000000                         // Load PENDSVSET bit
     MOV     r1, #0xE000E000                         // Load NVIC base
     STR     r0, [r1, #0xD04]                        // Set PENDSVBIT in ICSR
+    DSB     #0xF                                    // Ensure memory access is complete
+    ISB     #0xF                                    // Flush pipeline
     MRS     r0, IPSR                                // Pickup IPSR
     CMP     r0, #0                                  // Is it a thread returning?
     BNE     _isr_context                            // If ISR, skip interrupt enable
@@ -81,10 +85,12 @@ _tx_thread_system_return:
     MOV     r0, #0
     MSR     BASEPRI, r0                             // Enable interrupts
     MSR     BASEPRI, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #else
     MRS     r1, PRIMASK                             // Thread context returning, pickup PRIMASK
     CPSIE   i                                       // Enable interrupts
     MSR     PRIMASK, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #endif
 _isr_context:
     BX      lr                                      // Return to caller
diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_system_return.S
index 8c4a09fd1..4709af37f 100644
--- a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_system_return.S
+++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_system_return.S
@@ -9,6 +9,8 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Some portions generated by Gemini (Gemini 2.0 Flash).
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -73,6 +75,8 @@ _tx_thread_system_return:
     MOV     r0, #0x10000000                         // Load PENDSVSET bit
     MOV     r1, #0xE000E000                         // Load NVIC base
     STR     r0, [r1, #0xD04]                        // Set PENDSVBIT in ICSR
+    DSB     #0xF                                    // Ensure memory access is complete
+    ISB     #0xF                                    // Flush pipeline
     MRS     r0, IPSR                                // Pickup IPSR
     CMP     r0, #0                                  // Is it a thread returning?
     BNE     _isr_context                            // If ISR, skip interrupt enable
@@ -81,10 +85,12 @@ _tx_thread_system_return:
     MOV     r0, #0
     MSR     BASEPRI, r0                             // Enable interrupts
     MSR     BASEPRI, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #else
     MRS     r1, PRIMASK                             // Thread context returning, pickup PRIMASK
     CPSIE   i                                       // Enable interrupts
     MSR     PRIMASK, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #endif
 _isr_context:
     BX      lr                                      // Return to caller
diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_system_return.s
index 4f8b9870f..b466bacaa 100644
--- a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_system_return.s
+++ b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_system_return.s
@@ -1,16 +1,19 @@
-/***************************************************************************
- * Copyright (c) 2024 Microsoft Corporation
- * Copyright (c) 2026-present Eclipse ThreadX contributors
- *
- * This program and the accompanying materials are made available under the
- * terms of the MIT License which is available at
- * https://opensource.org/licenses/MIT.
- *
- * SPDX-License-Identifier: MIT
- **************************************************************************/
+;***************************************************************************
+;* Copyright (c) 2024 Microsoft Corporation
+;* Copyright (c) 2026-present Eclipse ThreadX contributors
+;*
+;* This program and the accompanying materials are made available under the
+;* terms of the MIT License which is available at
+;* https://opensource.org/licenses/MIT.
+;*
+;* SPDX-License-Identifier: MIT
+;**************************************************************************
 
+; Some portions generated by Gemini (Gemini 2.0 Flash).
+
+
+;**************************************************************************
 
-/**************************************************************************/
 /**************************************************************************/
 /**                                                                       */
 /** ThreadX Component                                                     */
@@ -70,6 +73,8 @@ _tx_thread_system_return:
     MOV     r0, #0x10000000                         // Load PENDSVSET bit
     MOV     r1, #0xE000E000                         // Load NVIC base
     STR     r0, [r1, #0xD04]                        // Set PENDSVBIT in ICSR
+    DSB     SY                                      // Ensure memory access is complete
+    ISB     SY                                      // Flush pipeline
     MRS     r0, IPSR                                // Pickup IPSR
     CMP     r0, #0                                  // Is it a thread returning?
     BNE     _isr_context                            // If ISR, skip interrupt enable
@@ -78,10 +83,12 @@ _tx_thread_system_return:
     MOV     r0, #0
     MSR     BASEPRI, r0                             // Enable interrupts
     MSR     BASEPRI, r1                             // Restore original interrupt posture
+    ISB     SY                                      // Flush pipeline
 #else
     MRS     r1, PRIMASK                             // Thread context returning, pickup PRIMASK
     CPSIE   i                                       // Enable interrupts
     MSR     PRIMASK, r1                             // Restore original interrupt posture
+    ISB     SY                                      // Flush pipeline
 #endif
 _isr_context:
     BX      lr                                      // Return to caller
diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_system_return.S
index 831c00e4c..d0243dea6 100644
--- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_system_return.S
+++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_system_return.S
@@ -9,6 +9,8 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Some portions generated by Gemini (Gemini 2.0 Flash).
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -73,6 +75,8 @@ _tx_thread_system_return:
     MOV     r0, #0x10000000                         // Load PENDSVSET bit
     MOV     r1, #0xE000E000                         // Load NVIC base
     STR     r0, [r1, #0xD04]                        // Set PENDSVBIT in ICSR
+    DSB     #0xF                                    // Ensure memory access is complete
+    ISB     #0xF                                    // Flush pipeline
     MRS     r0, IPSR                                // Pickup IPSR
     CMP     r0, #0                                  // Is it a thread returning?
     BNE     _isr_context                            // If ISR, skip interrupt enable
@@ -81,10 +85,12 @@ _tx_thread_system_return:
     MOV     r0, #0
     MSR     BASEPRI, r0                             // Enable interrupts
     MSR     BASEPRI, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #else
     MRS     r1, PRIMASK                             // Thread context returning, pickup PRIMASK
     CPSIE   i                                       // Enable interrupts
     MSR     PRIMASK, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #endif
 _isr_context:
     BX      lr                                      // Return to caller
diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_system_return.S
index ce5a3f46f..180894b3b 100644
--- a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_system_return.S
+++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_system_return.S
@@ -9,6 +9,8 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Some portions generated by Gemini (Gemini 2.0 Flash).
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -73,6 +75,8 @@ _tx_thread_system_return:
     MOV     r0, #0x10000000                         // Load PENDSVSET bit
     MOV     r1, #0xE000E000                         // Load NVIC base
     STR     r0, [r1, #0xD04]                        // Set PENDSVBIT in ICSR
+    DSB     #0xF                                    // Ensure memory access is complete
+    ISB     #0xF                                    // Flush pipeline
     MRS     r0, IPSR                                // Pickup IPSR
     CMP     r0, #0                                  // Is it a thread returning?
     BNE     _isr_context                            // If ISR, skip interrupt enable
@@ -81,10 +85,12 @@ _tx_thread_system_return:
     MOV     r0, #0
     MSR     BASEPRI, r0                             // Enable interrupts
     MSR     BASEPRI, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #else
     MRS     r1, PRIMASK                             // Thread context returning, pickup PRIMASK
     CPSIE   i                                       // Enable interrupts
     MSR     PRIMASK, r1                             // Restore original interrupt posture
+    ISB     #0xF                                    // Flush pipeline
 #endif
 _isr_context:
     BX      lr                                      // Return to caller
diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_system_return.s
index 0cef80c6f..345fca808 100644
--- a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_system_return.s
+++ b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_system_return.s
@@ -1,16 +1,19 @@
-/***************************************************************************
- * Copyright (c) 2024 Microsoft Corporation
- * Copyright (c) 2026-present Eclipse ThreadX contributors
- *
- * This program and the accompanying materials are made available under the
- * terms of the MIT License which is available at
- * https://opensource.org/licenses/MIT.
- *
- * SPDX-License-Identifier: MIT
- **************************************************************************/
+;***************************************************************************
+;* Copyright (c) 2024 Microsoft Corporation
+;* Copyright (c) 2026-present Eclipse ThreadX contributors
+;*
+;* This program and the accompanying materials are made available under the
+;* terms of the MIT License which is available at
+;* https://opensource.org/licenses/MIT.
+;*
+;* SPDX-License-Identifier: MIT
+;**************************************************************************
 
+; Some portions generated by Gemini (Gemini 2.0 Flash).
+
+
+;**************************************************************************
 
-/**************************************************************************/
 /**************************************************************************/
 /**                                                                       */
 /** ThreadX Component                                                     */
@@ -70,6 +73,8 @@ _tx_thread_system_return:
     MOV     r0, #0x10000000                         // Load PENDSVSET bit
     MOV     r1, #0xE000E000                         // Load NVIC base
     STR     r0, [r1, #0xD04]                        // Set PENDSVBIT in ICSR
+    DSB     SY                                      // Ensure memory access is complete
+    ISB     SY                                      // Flush pipeline
     MRS     r0, IPSR                                // Pickup IPSR
     CMP     r0, #0                                  // Is it a thread returning?
     BNE     _isr_context                            // If ISR, skip interrupt enable
@@ -78,10 +83,12 @@ _tx_thread_system_return:
     MOV     r0, #0
     MSR     BASEPRI, r0                             // Enable interrupts
     MSR     BASEPRI, r1                             // Restore original interrupt posture
+    ISB     SY                                      // Flush pipeline
 #else
     MRS     r1, PRIMASK                             // Thread context returning, pickup PRIMASK
     CPSIE   i                                       // Enable interrupts
     MSR     PRIMASK, r1                             // Restore original interrupt posture
+    ISB     SY                                      // Flush pipeline
 #endif
 _isr_context:
     BX      lr                                      // Return to caller