diff --git a/compiler/aarch64/codegen/OMRInstOpCode.enum b/compiler/aarch64/codegen/OMRInstOpCode.enum
index cb04ef501c4..731add2fa99 100644
--- a/compiler/aarch64/codegen/OMRInstOpCode.enum
+++ b/compiler/aarch64/codegen/OMRInstOpCode.enum
@@ -27,8 +27,6 @@
 #include "compiler/codegen/OMRInstOpCode.enum"
 
 //		Opcode                                                          BINARY    	OPCODE    	comments
-/* UNALLOCATED */
-		bad,                                                    	/* 0x00000000	BAD       	invalid operation */
 /* Branch,exception generation and system Instruction */
 	/* Compare _ Branch (immediate) */
 		cbzw,                                                   	/* 0x34000000	CBZ       	 */
diff --git a/compiler/codegen/OMRInstOpCode.enum b/compiler/codegen/OMRInstOpCode.enum
index e2ec7163b9e..efc356d06de 100644
--- a/compiler/codegen/OMRInstOpCode.enum
+++ b/compiler/codegen/OMRInstOpCode.enum
@@ -24,4 +24,5 @@
  * definitions are permitted.
  */
 
-   assocreg,           // Register Association
\ No newline at end of file
+   assocreg,           // Register Association
+   bad,                // Bad Opcode
\ No newline at end of file
diff --git a/compiler/p/codegen/OMRInstOpCode.enum b/compiler/p/codegen/OMRInstOpCode.enum
index 1eba832ff30..4338ce97804 100644
--- a/compiler/p/codegen/OMRInstOpCode.enum
+++ b/compiler/p/codegen/OMRInstOpCode.enum
@@ -26,7 +26,6 @@
 
 #include "compiler/codegen/OMRInstOpCode.enum"
 
-   bad,              // Illegal Opcode
    add,              // Add
    add_r,            // Add Rc=1
    addc,             // Add carrying
diff --git a/compiler/riscv/codegen/OMRInstOpCode.enum b/compiler/riscv/codegen/OMRInstOpCode.enum
index 7bdd06253e6..7f3ddac6574 100644
--- a/compiler/riscv/codegen/OMRInstOpCode.enum
+++ b/compiler/riscv/codegen/OMRInstOpCode.enum
@@ -26,8 +26,6 @@
 
 #include "compiler/codegen/OMRInstOpCode.enum"
 
-/* UNALLOCATED */
-		bad,
 /*
  * RISC-V instructions
  */
diff --git a/compiler/z/codegen/BinaryCommutativeAnalyser.cpp b/compiler/z/codegen/BinaryCommutativeAnalyser.cpp
index 9dfbf73c115..119c2afe097 100644
--- a/compiler/z/codegen/BinaryCommutativeAnalyser.cpp
+++ b/compiler/z/codegen/BinaryCommutativeAnalyser.cpp
@@ -350,7 +350,7 @@ TR_S390BinaryCommutativeAnalyser::genericAnalyser(TR::Node * root, TR::InstOpCod
          if (cg()->comp()->target().cpu.supportsFeature(OMR_FEATURE_S390_MISCELLANEOUS_INSTRUCTION_EXTENSION_2))
             {
             // Check for multiplications on z14
-            TR::InstOpCode::Mnemonic z14OpCode = TR::InstOpCode::BAD;
+            TR::InstOpCode::Mnemonic z14OpCode = TR::InstOpCode::bad;
 
             if(root->getOpCodeValue() == TR::lmul &&
                     firstRegister != NULL &&
@@ -367,7 +367,7 @@ TR_S390BinaryCommutativeAnalyser::genericAnalyser(TR::Node * root, TR::InstOpCod
                z14OpCode = TR::InstOpCode::MSRKC;
                }
 
-            if(z14OpCode != TR::InstOpCode::BAD)
+            if(z14OpCode != TR::InstOpCode::bad)
                {
                bool isCanClobberFirstReg = cg()->canClobberNodesRegister(firstChild);
                nodeReg = isCanClobberFirstReg ? firstRegister : cg()->allocateRegister();
diff --git a/compiler/z/codegen/BinaryEvaluator.cpp b/compiler/z/codegen/BinaryEvaluator.cpp
index de83b16dee8..7b5b8cafed8 100644
--- a/compiler/z/codegen/BinaryEvaluator.cpp
+++ b/compiler/z/codegen/BinaryEvaluator.cpp
@@ -2350,7 +2350,7 @@ OMR::Z::TreeEvaluator::baddEvaluator(TR::Node* node, TR::CodeGenerator* cg)
    cg->evaluate(rhsChild);
 
    TR_S390BinaryCommutativeAnalyser temp(cg);
-   temp.genericAnalyser(node, TR::InstOpCode::AR, TR::InstOpCode::BAD, TR::InstOpCode::LR);
+   temp.genericAnalyser(node, TR::InstOpCode::AR, TR::InstOpCode::bad, TR::InstOpCode::LR);
 
    cg->decReferenceCount(lhsChild);
    cg->decReferenceCount(rhsChild);
@@ -2386,7 +2386,7 @@ OMR::Z::TreeEvaluator::bsubEvaluator(TR::Node* node, TR::CodeGenerator* cg)
    cg->evaluate(rhsChild);
 
    TR_S390BinaryAnalyser temp(cg);
-   temp.genericAnalyser(node, TR::InstOpCode::SR, TR::InstOpCode::BAD, TR::InstOpCode::LR);
+   temp.genericAnalyser(node, TR::InstOpCode::SR, TR::InstOpCode::bad, TR::InstOpCode::LR);
 
    return node->getRegister();
    }
@@ -2572,7 +2572,7 @@ OMR::Z::TreeEvaluator::bmulEvaluator(TR::Node* node, TR::CodeGenerator* cg)
    cg->evaluate(rhsChild);
 
    TR_S390BinaryCommutativeAnalyser temp(cg);
-   temp.genericAnalyser(node, TR::InstOpCode::MSR, TR::InstOpCode::BAD, TR::InstOpCode::LR);
+   temp.genericAnalyser(node, TR::InstOpCode::MSR, TR::InstOpCode::bad, TR::InstOpCode::LR);
 
    cg->decReferenceCount(lhsChild);
    cg->decReferenceCount(rhsChild);
diff --git a/compiler/z/codegen/InstOpCode.cpp b/compiler/z/codegen/InstOpCode.cpp
index 9bdd466c7f6..1ed730f9d30 100644
--- a/compiler/z/codegen/InstOpCode.cpp
+++ b/compiler/z/codegen/InstOpCode.cpp
@@ -296,7 +296,7 @@ OMR::Z::InstOpCode::getEquivalentLongDisplacementMnemonic(TR::InstOpCode::Mnemon
       case TR::InstOpCode::CDS:
          return TR::InstOpCode::CDSY;
       default:
-         return TR::InstOpCode::BAD;
+         return TR::InstOpCode::bad;
       }
    }
 
@@ -564,7 +564,7 @@ OMR::Z::InstOpCode::getLoadRegOpCodeFromNode(TR::CodeGenerator *cg, TR::Node *no
 TR::InstOpCode::Mnemonic
 OMR::Z::InstOpCode::getMoveHalfWordImmOpCodeFromStoreOpCode(TR::InstOpCode::Mnemonic storeOpCode)
    {
-   TR::InstOpCode::Mnemonic mvhiOpCode = TR::InstOpCode::BAD;
+   TR::InstOpCode::Mnemonic mvhiOpCode = TR::InstOpCode::bad;
    if (storeOpCode == TR::InstOpCode::ST)
       mvhiOpCode = TR::InstOpCode::MVHI;
    else if (storeOpCode == TR::InstOpCode::STG)
diff --git a/compiler/z/codegen/OMRInstOpCode.enum b/compiler/z/codegen/OMRInstOpCode.enum
index 1ed708ec727..9ded8365133 100644
--- a/compiler/z/codegen/OMRInstOpCode.enum
+++ b/compiler/z/codegen/OMRInstOpCode.enum
@@ -28,7 +28,6 @@
 
    /* Pseudo Instructions */
 
-   BAD,                 // Bad Opcode
    BREAK,               // Breakpoint (debugger)
    DC,                  // DC
    DC2,                 // DC2
diff --git a/compiler/z/codegen/OMRInstOpCode.hpp b/compiler/z/codegen/OMRInstOpCode.hpp
index e7f31f0bd20..91e47d43870 100644
--- a/compiler/z/codegen/OMRInstOpCode.hpp
+++ b/compiler/z/codegen/OMRInstOpCode.hpp
@@ -397,7 +397,7 @@ class InstOpCode: public OMR::InstOpCode
    {
    protected:
 
-   InstOpCode():  OMR::InstOpCode(BAD)  {}
+   InstOpCode():  OMR::InstOpCode(bad)  {}
    InstOpCode(Mnemonic m): OMR::InstOpCode(m)  {}
 
    public:
diff --git a/compiler/z/codegen/OMRInstOpCodeProperties.hpp b/compiler/z/codegen/OMRInstOpCodeProperties.hpp
index 23821980eeb..04a52c3c69f 100644
--- a/compiler/z/codegen/OMRInstOpCodeProperties.hpp
+++ b/compiler/z/codegen/OMRInstOpCodeProperties.hpp
@@ -37,8 +37,8 @@
    },
 
    {
-   /* .mnemonic    = */ OMR::InstOpCode::BAD,
-   /* .name        = */ "BAD",
+   /* .mnemonic    = */ OMR::InstOpCode::bad,
+   /* .name        = */ "bad",
    /* .description = */ "Bad Opcode",
    /* .opcode[0]   = */ 0x00,
    /* .opcode[1]   = */ 0x00,
diff --git a/compiler/z/codegen/OMRMachine.cpp b/compiler/z/codegen/OMRMachine.cpp
index 551dbd8709a..0e09f43a783 100644
--- a/compiler/z/codegen/OMRMachine.cpp
+++ b/compiler/z/codegen/OMRMachine.cpp
@@ -265,9 +265,9 @@ OMR::Z::Machine::registerExchange(TR::CodeGenerator* cg,
       {
       TR_ASSERT_FATAL(targetReg->getAssignedRegister()->is64BitReg() == sourceReg->getAssignedRegister()->is64BitReg(), "Attempting register exchange with one 64-bit register (%s) and one 32-bit register (%s)", getRegisterName(sourceReg, cg), getRegisterName(targetReg, cg));
 
-      TR::InstOpCode::Mnemonic opLoadReg = TR::InstOpCode::BAD;
-      TR::InstOpCode::Mnemonic opLoad = TR::InstOpCode::BAD;
-      TR::InstOpCode::Mnemonic opStore = TR::InstOpCode::BAD;
+      TR::InstOpCode::Mnemonic opLoadReg = TR::InstOpCode::bad;
+      TR::InstOpCode::Mnemonic opLoad = TR::InstOpCode::bad;
+      TR::InstOpCode::Mnemonic opStore = TR::InstOpCode::bad;
 
       if (targetReg->getAssignedRegister()->is64BitReg())
          {
diff --git a/compiler/z/codegen/OMRMemoryReference.cpp b/compiler/z/codegen/OMRMemoryReference.cpp
index eea3be0572c..cd7ca0e8872 100644
--- a/compiler/z/codegen/OMRMemoryReference.cpp
+++ b/compiler/z/codegen/OMRMemoryReference.cpp
@@ -1974,7 +1974,7 @@ TR::Register *OMR::Z::MemoryReference::swapBaseRegister(TR::Register *br, TR::Co
 TR::Instruction *
 OMR::Z::MemoryReference::handleLargeOffset(TR::Node * node, TR::MemoryReference *interimMemoryReference, TR::Register *tempTargetRegister, TR::CodeGenerator * cg, TR::Instruction * preced)
    {
-   TR::InstOpCode::Mnemonic op = TR::InstOpCode::BAD;
+   TR::InstOpCode::Mnemonic op = TR::InstOpCode::bad;
 
    if (_offset > MINLONGDISP && _offset < MAXLONGDISP)
       {
@@ -2951,7 +2951,7 @@ OMR::Z::MemoryReference::generateBinaryEncoding(uint8_t * cursor, TR::CodeGenera
       auto longDisplacementMnemonic = TR::InstOpCode::getEquivalentLongDisplacementMnemonic(instr->getOpCodeValue());
 
       if ((displacement < MAXLONGDISP && displacement > MINLONGDISP)
-         && (longDisplacementMnemonic != TR::InstOpCode::BAD
+         && (longDisplacementMnemonic != TR::InstOpCode::bad
             || instructionFormat == TR::Instruction::IsRXY
             || instructionFormat == TR::Instruction::IsRXYb
             || instructionFormat == TR::Instruction::IsRSY
@@ -2970,7 +2970,7 @@ OMR::Z::MemoryReference::generateBinaryEncoding(uint8_t * cursor, TR::CodeGenera
          // formats and S390*Instruction formats
          instructionFormat = TR::Instruction::IsRXY;
 
-         if (longDisplacementMnemonic != TR::InstOpCode::BAD)
+         if (longDisplacementMnemonic != TR::InstOpCode::bad)
             {
             TR::DebugCounter::incStaticDebugCounter(comp, TR::DebugCounter::debugCounterName(comp, "z/memref/long-displacement-upgrade/(%s)", comp->signature()));
             }
diff --git a/compiler/z/codegen/OMRPeephole.cpp b/compiler/z/codegen/OMRPeephole.cpp
index 6eeff617bc0..5b6c53eb827 100644
--- a/compiler/z/codegen/OMRPeephole.cpp
+++ b/compiler/z/codegen/OMRPeephole.cpp
@@ -762,7 +762,7 @@ OMR::Z::Peephole::tryToReduce64BitShiftTo32BitShift()
 
    if (performTransformation(self()->comp(), "O^O S390 PEEPHOLE: Reverting int shift at %p from SLLG/SLAG/S[LR][LA]K to SLL/SLA/SRL/SRA.\n", shiftInst))
       {
-      TR::InstOpCode::Mnemonic newOpCode = TR::InstOpCode::BAD;
+      TR::InstOpCode::Mnemonic newOpCode = TR::InstOpCode::bad;
       switch (oldOpCode)
          {
          case TR::InstOpCode::SLLG:
diff --git a/compiler/z/codegen/OMRTreeEvaluator.cpp b/compiler/z/codegen/OMRTreeEvaluator.cpp
index 4de47f8a37a..deebee24a1c 100644
--- a/compiler/z/codegen/OMRTreeEvaluator.cpp
+++ b/compiler/z/codegen/OMRTreeEvaluator.cpp
@@ -734,10 +734,10 @@ generateS390ImmOp(TR::CodeGenerator * cg,  TR::InstOpCode::Mnemonic memOp, TR::N
    {
    TR::Compilation *comp = cg->comp();
    TR::Instruction * cursor = NULL, *resultMultReduction = NULL;
-   TR::InstOpCode::Mnemonic immOp = TR::InstOpCode::BAD;
+   TR::InstOpCode::Mnemonic immOp = TR::InstOpCode::bad;
 
    // LL: Store Golden Eagle extended immediate instruction - 6 bytes long
-   TR::InstOpCode::Mnemonic ei_immOp = TR::InstOpCode::BAD;
+   TR::InstOpCode::Mnemonic ei_immOp = TR::InstOpCode::bad;
 
    switch (memOp)
       {
@@ -1029,13 +1029,13 @@ generateS390ImmOp(TR::CodeGenerator * cg,  TR::InstOpCode::Mnemonic memOp, TR::N
             // value = 0x****0000
             value = value >> 16;
             immOp = TR::InstOpCode::OILH;
-            ei_immOp = TR::InstOpCode::BAD; // Reset so we don't generate OILF.
+            ei_immOp = TR::InstOpCode::bad; // Reset so we don't generate OILF.
             }
          else if (!(value & 0xFFFF0000))
             {
             // value = 0x0000****
             immOp = TR::InstOpCode::OILL;
-            ei_immOp = TR::InstOpCode::BAD; // Reset so we don't generate OILF.
+            ei_immOp = TR::InstOpCode::bad; // Reset so we don't generate OILF.
             }
          }
          break;
@@ -1062,13 +1062,13 @@ generateS390ImmOp(TR::CodeGenerator * cg,  TR::InstOpCode::Mnemonic memOp, TR::N
             {
             value = value & 0x0000FFFF;
             immOp = TR::InstOpCode::NILL;
-            ei_immOp = TR::InstOpCode::BAD; // Reset so we don't generate NILF.
+            ei_immOp = TR::InstOpCode::bad; // Reset so we don't generate NILF.
             }
          else if ((value & 0x0000FFFF) == 0x0000FFFF)
             {
             value = value >> 16;
             immOp = TR::InstOpCode::NILH;
-            ei_immOp = TR::InstOpCode::BAD; // Reset so we don't generate NILF.
+            ei_immOp = TR::InstOpCode::bad; // Reset so we don't generate NILF.
             }
          }
          break;
@@ -1148,12 +1148,12 @@ generateS390ImmOp(TR::CodeGenerator * cg,  TR::InstOpCode::Mnemonic memOp, TR::N
       cursor = generateRRInstruction(cg, TR::InstOpCode::getLoadRegOpCodeFromNode(cg, node), node, targetRegisterNoPair, sourceRegister, (cursor != NULL) ? cursor : preced);
       }
 
-   if (ei_immOp != TR::InstOpCode::BAD)
+   if (ei_immOp != TR::InstOpCode::bad)
       {
       cursor = generateRILInstruction(cg, ei_immOp, node, targetRegisterNoPair, value, (cursor != NULL) ? cursor : preced);
       return cursor;
       }
-   else if (immOp != TR::InstOpCode::BAD)
+   else if (immOp != TR::InstOpCode::bad)
       {
       cursor = generateRIInstruction(cg, immOp, node, targetRegisterNoPair, value, (cursor != NULL) ? cursor : preced);
       return cursor;
@@ -1173,10 +1173,10 @@ generateS390ImmOp(TR::CodeGenerator * cg,
    {
    TR_ASSERT( preced == NULL, "Support has not yet been adding for preced instruction");
    TR::Instruction * cursor = NULL;
-   TR::InstOpCode::Mnemonic immOp=TR::InstOpCode::BAD;
+   TR::InstOpCode::Mnemonic immOp=TR::InstOpCode::bad;
 
    // LL: Store Golden Eagle extended immediate instruction - 6 bytes long
-   TR::InstOpCode::Mnemonic ei_immOp=TR::InstOpCode::BAD;
+   TR::InstOpCode::Mnemonic ei_immOp=TR::InstOpCode::bad;
 
    const int64_t hhMask = CONSTANT64(0x0000FFFFFFFFFFFF);
    const int64_t hlMask = CONSTANT64(0xFFFF0000FFFFFFFF);
@@ -1460,11 +1460,11 @@ generateS390ImmOp(TR::CodeGenerator * cg,
       }
 
    // LL: Golden Eagle extended immediate instructions
-   if (ei_immOp != TR::InstOpCode::BAD)
+   if (ei_immOp != TR::InstOpCode::bad)
       {
       return generateRILInstruction(cg, ei_immOp, node, targetRegister, static_cast<int32_t>(value));
       }
-   else if (immOp != TR::InstOpCode::BAD)
+   else if (immOp != TR::InstOpCode::bad)
       {
       return generateRIInstruction(cg, immOp, node, targetRegister, (int16_t)value);
       }
@@ -2084,7 +2084,7 @@ tryGenerateSIComparisons(TR::Node *node, TR::Node *constNode, TR::Node *otherNod
 
       TR::MemoryReference *memRef = TR::MemoryReference::create(cg, operand);
 
-      TR::InstOpCode::Mnemonic opCode = TR::InstOpCode::BAD;
+      TR::InstOpCode::Mnemonic opCode = TR::InstOpCode::bad;
       if (operandSize == 8)
          opCode = (isUnsignedCmp ? TR::InstOpCode::CLGHSI : TR::InstOpCode::CGHSI);
       else if (operandSize == 4)
@@ -2573,14 +2573,14 @@ tryGenerateConversionRXComparison(TR::Node *node, TR::CodeGenerator *cg, bool *i
       // Signed
       // memSize                    regSize
       // 2       4       8             v
-      {{ TR::InstOpCode::CH,  TR::InstOpCode::C,   TR::InstOpCode::BAD },  // 4
-       { TR::InstOpCode::BAD, TR::InstOpCode::CGF, TR::InstOpCode::CG  }}, // 8 // FIXME: CGH missing because it doesn't exist in s390ops
+      {{ TR::InstOpCode::CH,  TR::InstOpCode::C,   TR::InstOpCode::bad },  // 4
+       { TR::InstOpCode::bad, TR::InstOpCode::CGF, TR::InstOpCode::CG  }}, // 8 // FIXME: CGH missing because it doesn't exist in s390ops
 
       // Unsigned
       // memSize                     regSize
       // 2       4        8             v
-      {{ TR::InstOpCode::BAD, TR::InstOpCode::CL,   TR::InstOpCode::BAD },  // 4
-       { TR::InstOpCode::BAD, TR::InstOpCode::CLGF, TR::InstOpCode::CLG }}, // 8
+      {{ TR::InstOpCode::bad, TR::InstOpCode::CL,   TR::InstOpCode::bad },  // 4
+       { TR::InstOpCode::bad, TR::InstOpCode::CLGF, TR::InstOpCode::CLG }}, // 8
       };
 
    // FIXME: the above table needs to be intersected with the architecture.
@@ -2589,7 +2589,7 @@ tryGenerateConversionRXComparison(TR::Node *node, TR::CodeGenerator *cg, bool *i
    // forcing a signedCmp (e.g. CH) if convertToSignExtension is true
    TR::InstOpCode::Mnemonic op = choices[convertToSignExtension ? false : isUnsignedCmp][regSize == 4 ? 0 : 1][memSizeCoord];
 
-   if (op == TR::InstOpCode::BAD)
+   if (op == TR::InstOpCode::bad)
       {
       return 0;
       }
@@ -2834,7 +2834,7 @@ generateS390CompareAndBranchOpsHelper(TR::Node * node, TR::CodeGenerator * cg, T
             isUnsignedCmp = true;
             }
 
-         TR::InstOpCode::Mnemonic compareOpCode = TR::InstOpCode::BAD;
+         TR::InstOpCode::Mnemonic compareOpCode = TR::InstOpCode::bad;
          int64_t constValue64 = 0;
          int32_t constValue32 = 0;
          bool useConstValue64 = false;
@@ -3179,7 +3179,7 @@ getOpCodeIfSuitableForCompareAndBranch(TR::CodeGenerator * cg, TR::Node * node,
    {
    // be pessimistic and signal we can't use compare and branch until we
    // determine otherwise.
-   TR::InstOpCode::Mnemonic opCodeToUse = TR::InstOpCode::BAD;
+   TR::InstOpCode::Mnemonic opCodeToUse = TR::InstOpCode::bad;
 
    bool isUnsignedCmp = node->getOpCode().isUnsignedCompare();
    if (dataType == TR::Address)
@@ -3239,7 +3239,7 @@ genCompareAndBranchInstructionIfPossible(TR::CodeGenerator * cg, TR::Node * node
 
    // be pessimistic and signal we can't use compare and branch until we
    // determine otherwise.
-   TR::InstOpCode::Mnemonic opCodeToUse = TR::InstOpCode::BAD;
+   TR::InstOpCode::Mnemonic opCodeToUse = TR::InstOpCode::bad;
 
    TR::Node * firstChild = node->getFirstChild();
    TR::Node * secondChild = node->getSecondChild();
@@ -3302,7 +3302,7 @@ genCompareAndBranchInstructionIfPossible(TR::CodeGenerator * cg, TR::Node * node
 
    opCodeToUse = getOpCodeIfSuitableForCompareAndBranch(cg, node, dataType, canUseImm8 );
 
-   if (opCodeToUse == TR::InstOpCode::BAD)
+   if (opCodeToUse == TR::InstOpCode::bad)
       {
       return NULL;
       }
@@ -4234,13 +4234,13 @@ static const TR::InstOpCode::Mnemonic loadInstrs[2/*Form*/][4/*numberOfBits*/][2
 /* 8*/   { { TR::InstOpCode::LLCR,  TR::InstOpCode::LLGCR }, { TR::InstOpCode::LBR,   TR::InstOpCode::LGBR } },
 /*16*/   { { TR::InstOpCode::LLHR,  TR::InstOpCode::LLGHR }, { TR::InstOpCode::LHR,   TR::InstOpCode::LGHR } },
 /*32*/   { { TR::InstOpCode::LR,    TR::InstOpCode::LLGFR }, { TR::InstOpCode::LR,    TR::InstOpCode::LGFR } },
-/*64*/   { { TR::InstOpCode::BAD,   TR::InstOpCode::LGR   }, { TR::InstOpCode::BAD,   TR::InstOpCode::LGR  } }
+/*64*/   { { TR::InstOpCode::bad,   TR::InstOpCode::LGR   }, { TR::InstOpCode::bad,   TR::InstOpCode::LGR  } }
       },
 /*MemReg*/{
 /* 8*/   { { TR::InstOpCode::LLC,   TR::InstOpCode::LLGC  }, { TR::InstOpCode::LB,    TR::InstOpCode::LGB } },
 /*16*/   { { TR::InstOpCode::LLH,   TR::InstOpCode::LLGH  }, { TR::InstOpCode::LH,    TR::InstOpCode::LGH } },
 /*32*/   { { TR::InstOpCode::L,     TR::InstOpCode::LLGF  }, { TR::InstOpCode::L,     TR::InstOpCode::LGF } },
-/*64*/   { { TR::InstOpCode::BAD,   TR::InstOpCode::LG    }, { TR::InstOpCode::BAD,   TR::InstOpCode::LG  } }
+/*64*/   { { TR::InstOpCode::bad,   TR::InstOpCode::LG    }, { TR::InstOpCode::bad,   TR::InstOpCode::LG  } }
       }
    };
 
@@ -4632,7 +4632,7 @@ bool relativeLongLoadHelper(TR::CodeGenerator * cg, TR::Node * node, TR::Registe
        !cg->getConditionalMovesEvaluationMode()
       )
       {
-      TR::InstOpCode::Mnemonic op = TR::InstOpCode::BAD;
+      TR::InstOpCode::Mnemonic op = TR::InstOpCode::bad;
       if (node->getType().isInt32() || (!(cg->comp()->target().is64Bit()) && node->getType().isAddress() ))
          {
          op = TR::InstOpCode::LRL;
@@ -4652,7 +4652,7 @@ bool relativeLongLoadHelper(TR::CodeGenerator * cg, TR::Node * node, TR::Registe
          op = TR::InstOpCode::LGRL;
          }
 
-      TR_ASSERT(op != TR::InstOpCode::BAD, "Bad opcode selection in relative load helper!\n");
+      TR_ASSERT(op != TR::InstOpCode::bad, "Bad opcode selection in relative load helper!\n");
 
       if ((!disableFORCELRL || cg->canUseRelativeLongInstructions(staticAddress)) &&
            ((cg->comp()->target().is32Bit() && (staticAddress&0x3) == 0)  ||
@@ -5539,7 +5539,7 @@ astoreHelper(TR::Node * node, TR::CodeGenerator * cg)
       TR::Register* sourceRegister = NULL;
 
       // Try Move HalfWord Immediate instructions first
-      if (mvhiOp != TR::InstOpCode::BAD &&
+      if (mvhiOp != TR::InstOpCode::bad &&
           valueChild->getOpCode().isLoadConst() &&
           !cg->getConditionalMovesEvaluationMode())
          {
@@ -5555,9 +5555,9 @@ astoreHelper(TR::Node * node, TR::CodeGenerator * cg)
          else
             {
             // Successfully generated Move Halfword Immediate instruction
-            // Set storeOp to TR::InstOpCode::BAD, so we do not explicitly generate a
+            // Set storeOp to TR::InstOpCode::bad, so we do not explicitly generate a
             // store instruction later.
-            storeOp = TR::InstOpCode::BAD;
+            storeOp = TR::InstOpCode::bad;
             }
          }
       // aload is the child, then don't evaluate the child, generate MVC to move directly among memory
@@ -5596,11 +5596,11 @@ astoreHelper(TR::Node * node, TR::CodeGenerator * cg)
          tempMR = TR::MemoryReference::create(cg, node);
          }
 
-      // Generate the Store instruction unless storeOp is TR::InstOpCode::BAD (i.e. Move
+      // Generate the Store instruction unless storeOp is TR::InstOpCode::bad (i.e. Move
       // Halfword Immediate instruction was generated).
       if (storeOp == TR::InstOpCode::STCM)
          generateRSInstruction(cg, TR::InstOpCode::STCM, node, sourceRegister, (uint32_t) 0x7, tempMR);
-      else if (storeOp != TR::InstOpCode::BAD)
+      else if (storeOp != TR::InstOpCode::bad)
          {
          if (cg->getConditionalMovesEvaluationMode())
             generateRSInstruction(cg, (storeOp == TR::InstOpCode::STG)? TR::InstOpCode::STOCG : TR::InstOpCode::STOC, node, sourceRegister, cg->getRCondMoveBranchOpCond(), tempMR);
@@ -12073,7 +12073,7 @@ TR::Register *OMR::Z::TreeEvaluator::bitOpMemEvaluator(TR::Node * node, TR::Code
    // see if we can generate immediate instructions
    TR::InstOpCode::Mnemonic SI_opcode = isXor ? TR::InstOpCode::XI :
                               isAnd ? TR::InstOpCode::NI :
-                              isOr  ? TR::InstOpCode::OI : TR::InstOpCode::BAD;
+                              isOr  ? TR::InstOpCode::OI : TR::InstOpCode::bad;
    bool useSIFormat = false;
    char *value = NULL;
 
@@ -12176,7 +12176,7 @@ TR::Register *OMR::Z::TreeEvaluator::bitOpMemEvaluator(TR::Node * node, TR::Code
             byteSrc1Reg = cg->gprClobberEvaluate(byteSrc1Node);
          TR::InstOpCode::Mnemonic opcode = isXor ? TR::InstOpCode::XC :
                                  isAnd ? TR::InstOpCode::NC :
-                                 isOr  ? TR::InstOpCode::OC : TR::InstOpCode::BAD;
+                                 isOr  ? TR::InstOpCode::OC : TR::InstOpCode::bad;
 
          if (byteLenReg == NULL)
             {
@@ -12833,7 +12833,7 @@ OMR::Z::TreeEvaluator::inlineVectorBitSelectOp(TR::Node * node, TR::CodeGenerato
 TR::Register *
 OMR::Z::TreeEvaluator::vloadEvaluator(TR::Node *node, TR::CodeGenerator *cg)
    {
-   TR::InstOpCode::Mnemonic opcode = TR::InstOpCode::BAD;
+   TR::InstOpCode::Mnemonic opcode = TR::InstOpCode::bad;
 
    if (node->getOpCodeValue() == TR::vload ||
        node->getOpCodeValue() == TR::vloadi)
@@ -12892,7 +12892,7 @@ OMR::Z::TreeEvaluator::vRegStoreEvaluator(TR::Node *node, TR::CodeGenerator *cg)
 TR::Register *
 OMR::Z::TreeEvaluator::vstoreEvaluator(TR::Node *node, TR::CodeGenerator *cg)
    {
-   TR::InstOpCode::Mnemonic opcode = TR::InstOpCode::BAD;
+   TR::InstOpCode::Mnemonic opcode = TR::InstOpCode::bad;
 
    if (node->getOpCodeValue() == TR::vstore ||
        node->getOpCodeValue() == TR::vstorei)
@@ -12921,7 +12921,7 @@ OMR::Z::TreeEvaluator::vstoreEvaluator(TR::Node *node, TR::CodeGenerator *cg)
 TR::Register *
 OMR::Z::TreeEvaluator::vdremEvaluator(TR::Node *node, TR::CodeGenerator *cg)
    {
-   return TR::TreeEvaluator::inlineVectorBinaryOp(node, cg, TR::InstOpCode::BAD);
+   return TR::TreeEvaluator::inlineVectorBinaryOp(node, cg, TR::InstOpCode::bad);
    }
 
 TR::Register *
@@ -14375,7 +14375,7 @@ OMR::Z::TreeEvaluator::vdecEvaluator(TR::Node *node, TR::CodeGenerator *cg)
 TR::Register *
 OMR::Z::TreeEvaluator::vnegEvaluator(TR::Node *node, TR::CodeGenerator *cg)
    {
-   TR::InstOpCode::Mnemonic opCode = TR::InstOpCode::BAD;
+   TR::InstOpCode::Mnemonic opCode = TR::InstOpCode::bad;
    switch (node->getDataType())
       {
       case TR::VectorInt8:
@@ -14472,7 +14472,7 @@ generateFusedMultiplyAddIfPossible(TR::CodeGenerator *cg, TR::Node *addNode, TR:
       case TR::InstOpCode::MSEBR:
       case TR::InstOpCode::MSDR:
       case TR::InstOpCode::MSDBR:
-         if (negateOp != TR::InstOpCode::BAD)
+         if (negateOp != TR::InstOpCode::bad)
             {
             TR::Register *tempReg = cg->allocateRegister(TR_FPR);
             generateRRInstruction(cg, negateOp, addNode, tempReg, mulLeftReg); // negate one operand of the multiply
@@ -14514,7 +14514,7 @@ OMR::Z::TreeEvaluator::vaddEvaluator(TR::Node *node, TR::CodeGenerator *cg)
       }
    else
       {
-      TR::InstOpCode::Mnemonic opCode = TR::InstOpCode::BAD;
+      TR::InstOpCode::Mnemonic opCode = TR::InstOpCode::bad;
       switch (node->getDataType())
          {
          case TR::VectorInt8:
@@ -14549,7 +14549,7 @@ OMR::Z::TreeEvaluator::vsubEvaluator(TR::Node *node, TR::CodeGenerator *cg)
       }
    else
       {
-      TR::InstOpCode::Mnemonic opCode = TR::InstOpCode::BAD;
+      TR::InstOpCode::Mnemonic opCode = TR::InstOpCode::bad;
       switch (node->getDataType())
          {
          case TR::VectorInt8:
@@ -14672,7 +14672,7 @@ OMR::Z::TreeEvaluator::vDivOrRemHelper(TR::Node *node, TR::CodeGenerator *cg, bo
 
       bool isUnsigned = divisor->isUnsigned();
       bool is64Bit = (node->getDataType() == TR::VectorInt64);
-      TR::InstOpCode::Mnemonic divOp = TR::InstOpCode::BAD;
+      TR::InstOpCode::Mnemonic divOp = TR::InstOpCode::bad;
       if (is64Bit)
          divOp = isUnsigned ? TR::InstOpCode::DLGR : TR::InstOpCode::DSGR;
       else
@@ -15212,7 +15212,7 @@ OMR::Z::TreeEvaluator::vsetelemEvaluator(TR::Node *node, TR::CodeGenerator *cg)
       (valueNode->getOpCode().isMemoryReference() || valueNode->getOpCode().isLoadConst()))
       {
       uint8_t m3 = elementNode->getLongInt() % (16/size);
-      TR::InstOpCode::Mnemonic op = TR::InstOpCode::BAD;
+      TR::InstOpCode::Mnemonic op = TR::InstOpCode::bad;
 
       if (valueNode->getOpCode().isLoadConst() && valueNode->getOpCode().isInteger() &&
           valueNode->getLongInt() >= MIN_IMMEDIATE_VAL && valueNode->getLongInt() <= MAX_IMMEDIATE_VAL)
diff --git a/compiler/z/codegen/OpMemToMem.cpp b/compiler/z/codegen/OpMemToMem.cpp
index 11f00087a2b..66b96967269 100644
--- a/compiler/z/codegen/OpMemToMem.cpp
+++ b/compiler/z/codegen/OpMemToMem.cpp
@@ -1294,7 +1294,7 @@ TR::Instruction *
 MemToMemConstLenMacroOp::generateInstruction(int32_t offset, int64_t length, TR::Instruction * cursor1)
    {
    TR::Compilation *comp = _cg->comp();
-   TR_ASSERT(_opcode != TR::InstOpCode::BAD,"no opcode set for MemToMemConstLenMacroOp node %p\n",_rootNode);
+   TR_ASSERT(_opcode != TR::InstOpCode::bad,"no opcode set for MemToMemConstLenMacroOp node %p\n",_rootNode);
    TR::Instruction * cursor=NULL;
    TR::MemoryReference * srcMR = _srcMR;
    TR::MemoryReference * dstMR = _dstMR;
diff --git a/compiler/z/codegen/OpMemToMem.hpp b/compiler/z/codegen/OpMemToMem.hpp
index 22997d9408f..384185b3b0f 100644
--- a/compiler/z/codegen/OpMemToMem.hpp
+++ b/compiler/z/codegen/OpMemToMem.hpp
@@ -259,7 +259,7 @@ class MemToMemConstLenMacroOp : public MemToMemMacroOp
          }
    protected:
       MemToMemConstLenMacroOp(TR::Node* rootNode, TR::Node* dstNode, TR::Node* srcNode, TR::CodeGenerator * cg, int64_t length,
-                              TR::Register * itersReg=0, TR::InstOpCode::Mnemonic op=TR::InstOpCode::BAD, bool inNestedICF=false)
+                              TR::Register * itersReg=0, TR::InstOpCode::Mnemonic op=TR::InstOpCode::bad, bool inNestedICF=false)
         : MemToMemMacroOp(rootNode, dstNode, srcNode, cg,NULL, itersReg), _length(length), _maxCopies(16), _opcode(op), _needDep(true), _inNestedICF(inNestedICF), _nestedICFDeps(NULL)
          {
          uint64_t len = (uint64_t)length;
diff --git a/compiler/z/codegen/S390Evaluator.hpp b/compiler/z/codegen/S390Evaluator.hpp
index f678e56993e..3bc801cb217 100644
--- a/compiler/z/codegen/S390Evaluator.hpp
+++ b/compiler/z/codegen/S390Evaluator.hpp
@@ -233,6 +233,6 @@ TR::InstOpCode::S390BranchCondition getStandardIfBranchCondition(TR::ILOpCodes o
 TR::InstOpCode::S390BranchCondition getButestBranchCondition(TR::ILOpCodes opCode, int32_t compareVal);
 
 bool canUseNodeForFusedMultiply(TR::Node *node);
-bool generateFusedMultiplyAddIfPossible(TR::CodeGenerator *cg, TR::Node *addNode, TR::InstOpCode::Mnemonic op, TR::InstOpCode::Mnemonic negateOp = TR::InstOpCode::BAD);
+bool generateFusedMultiplyAddIfPossible(TR::CodeGenerator *cg, TR::Node *addNode, TR::InstOpCode::Mnemonic op, TR::InstOpCode::Mnemonic negateOp = TR::InstOpCode::bad);
 
 #endif
diff --git a/compiler/z/codegen/S390GenerateInstructions.cpp b/compiler/z/codegen/S390GenerateInstructions.cpp
index 2045cd915ca..ae1d8a44690 100644
--- a/compiler/z/codegen/S390GenerateInstructions.cpp
+++ b/compiler/z/codegen/S390GenerateInstructions.cpp
@@ -234,7 +234,7 @@ TR::InstOpCode::Mnemonic getReplacementCompareAndBranchOpCode(TR::CodeGenerator
    static char * disableS390CompareAndBranch = feGetEnv("TR_DISABLES390CompareAndBranch");
 
    if (disableS390CompareAndBranch)
-      return TR::InstOpCode::BAD ;
+      return TR::InstOpCode::bad ;
 
    switch(compareOpCode)
       {
@@ -263,7 +263,7 @@ TR::InstOpCode::Mnemonic getReplacementCompareAndBranchOpCode(TR::CodeGenerator
          return TR::InstOpCode::CLGIJ;
          break;
       default:
-         return TR::InstOpCode::BAD;
+         return TR::InstOpCode::bad;
          break;
       }
    }
@@ -275,7 +275,7 @@ getReplacementLongDisplacementOpCode(TR::CodeGenerator* cg, TR::InstOpCode::Mnem
       {
       auto longDisplacementMnemonic = TR::InstOpCode::getEquivalentLongDisplacementMnemonic(op);
 
-      if (longDisplacementMnemonic != TR::InstOpCode::BAD)
+      if (longDisplacementMnemonic != TR::InstOpCode::bad)
          {
          op = longDisplacementMnemonic;
 
@@ -314,7 +314,7 @@ generateS390CompareAndBranchInstruction(TR::CodeGenerator * cg,
    TR::Instruction * returnInstruction = NULL;
 
    // test to see if this node is suitable for compare and branch, and which
-   // compare and branch op code to use if so.  if we get TR::InstOpCode::BAD, it isn't
+   // compare and branch op code to use if so.  if we get TR::InstOpCode::bad, it isn't
    // suitable for compare and branch, and we'll generate the old fashioned way.
    TR::InstOpCode::Mnemonic replacementOpCode = getReplacementCompareAndBranchOpCode(cg, compareOpCode);
 
@@ -322,7 +322,7 @@ generateS390CompareAndBranchInstruction(TR::CodeGenerator * cg,
    // compare-and-branch instructions are zEC12 and above
    if( !cg->comp()->getOption(TR_DisableCompareAndBranchInstruction) &&
            !needsCC &&
-           replacementOpCode != TR::InstOpCode::BAD &&
+           replacementOpCode != TR::InstOpCode::bad &&
            cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_S390_ZEC12))
       {
       // generate a compare and branch.
@@ -393,10 +393,10 @@ generateS390CompareAndBranchInstruction(TR::CodeGenerator * cg,
    // declare a space for the instruction we'll return (the compare and branch
    // instruction, or the branch instruction if z6 support is off).
    TR::Instruction * cursor = NULL;
-   TR::InstOpCode::Mnemonic replacementOpCode = TR::InstOpCode::BAD;
+   TR::InstOpCode::Mnemonic replacementOpCode = TR::InstOpCode::bad;
 
    // test to see if this node is suitable for compare and branch, and which
-   // compare and branch op code to use if so.  if we get TR::InstOpCode::BAD, it isn't
+   // compare and branch op code to use if so.  if we get TR::InstOpCode::bad, it isn't
    // suitable for compare and branch, and we'll generate the old fashioned way.
    bool canUseReplacementOpCode = false;
    switch(compareOpCode)
@@ -418,7 +418,7 @@ generateS390CompareAndBranchInstruction(TR::CodeGenerator * cg,
    // compare-and-branch instructions are zEC12 and above
    if( !cg->comp()->getOption(TR_DisableCompareAndBranchInstruction) &&
            !needsCC &&
-           replacementOpCode != TR::InstOpCode::BAD &&
+           replacementOpCode != TR::InstOpCode::bad &&
            cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_S390_ZEC12))
       {
       cursor = (TR::S390RIEInstruction *)generateRIEInstruction(cg, replacementOpCode, node, first, (int8_t) second, branchDestination, bc, preced);
diff --git a/compiler/z/codegen/S390Instruction.cpp b/compiler/z/codegen/S390Instruction.cpp
index ada65767499..911b89081be 100644
--- a/compiler/z/codegen/S390Instruction.cpp
+++ b/compiler/z/codegen/S390Instruction.cpp
@@ -2385,7 +2385,7 @@ TR::S390RSInstruction::generateBinaryEncoding()
          {
          auto longDisplacementMnemonic = TR::InstOpCode::getEquivalentLongDisplacementMnemonic(getOpCodeValue());
 
-         if (longDisplacementMnemonic != TR::InstOpCode::BAD)
+         if (longDisplacementMnemonic != TR::InstOpCode::bad)
             {
             opCode = TR::InstOpCode(longDisplacementMnemonic);
             }
@@ -3140,7 +3140,7 @@ TR::S390RXInstruction::generateBinaryEncoding()
       {
       auto longDisplacementMnemonic = TR::InstOpCode::getEquivalentLongDisplacementMnemonic(getOpCodeValue());
 
-      if (longDisplacementMnemonic != TR::InstOpCode::BAD)
+      if (longDisplacementMnemonic != TR::InstOpCode::bad)
          {
          opCode = TR::InstOpCode(longDisplacementMnemonic);
          }
@@ -4844,7 +4844,7 @@ TR::S390SIInstruction::generateBinaryEncoding()
       {
       auto longDisplacementMnemonic = TR::InstOpCode::getEquivalentLongDisplacementMnemonic(getOpCodeValue());
 
-      if (longDisplacementMnemonic != TR::InstOpCode::BAD)
+      if (longDisplacementMnemonic != TR::InstOpCode::bad)
          {
          opCode = TR::InstOpCode(longDisplacementMnemonic);
          }
diff --git a/compiler/z/codegen/S390Instruction.hpp b/compiler/z/codegen/S390Instruction.hpp
index 5c99385a885..194968a8590 100644
--- a/compiler/z/codegen/S390Instruction.hpp
+++ b/compiler/z/codegen/S390Instruction.hpp
@@ -4830,7 +4830,7 @@ class S390VRIInstruction : public S390VInstruction
    protected:
    S390VRIInstruction(
                        TR::CodeGenerator      * cg               = NULL,
-                       TR::InstOpCode::Mnemonic          op      = TR::InstOpCode::BAD,
+                       TR::InstOpCode::Mnemonic          op      = TR::InstOpCode::bad,
                        TR::Node               * n                = NULL,
                        TR::Register           * targetReg        = NULL,
                        uint16_t                constantImm16      = 0,
@@ -4891,7 +4891,7 @@ class S390VRIaInstruction : public S390VRIInstruction
    public:
    S390VRIaInstruction(
                           TR::CodeGenerator      * cg            = NULL,
-                          TR::InstOpCode::Mnemonic  op           = TR::InstOpCode::BAD,
+                          TR::InstOpCode::Mnemonic  op           = TR::InstOpCode::bad,
                           TR::Node               * n             = NULL,
                           TR::Register           * targetReg     = NULL,
                           uint16_t                constantImm2   = 0,  /* 16 bits */
@@ -4920,7 +4920,7 @@ class S390VRIbInstruction : public S390VRIInstruction
    public:
    S390VRIbInstruction(
                           TR::CodeGenerator      * cg             = NULL,
-                          TR::InstOpCode::Mnemonic          op    = TR::InstOpCode::BAD,
+                          TR::InstOpCode::Mnemonic          op    = TR::InstOpCode::bad,
                           TR::Node               * n              = NULL,
                           TR::Register           * targetReg      = NULL,
                           uint8_t                 constantImm2    = 0,    /*  8 bits */
@@ -4950,7 +4950,7 @@ class S390VRIcInstruction : public S390VRIInstruction
    public:
    S390VRIcInstruction(
                           TR::CodeGenerator      * cg               = NULL,
-                          TR::InstOpCode::Mnemonic          op               = TR::InstOpCode::BAD,
+                          TR::InstOpCode::Mnemonic          op               = TR::InstOpCode::bad,
                           TR::Node               * n                = NULL,
                           TR::Register           * targetReg        = NULL,
                           TR::Register           * sourceReg3       = NULL,
@@ -4983,7 +4983,7 @@ class S390VRIdInstruction : public S390VRIInstruction
    public:
    S390VRIdInstruction(
                           TR::CodeGenerator      * cg               = NULL,
-                          TR::InstOpCode::Mnemonic          op      = TR::InstOpCode::BAD,
+                          TR::InstOpCode::Mnemonic          op      = TR::InstOpCode::bad,
                           TR::Node               * n                = NULL,
                           TR::Register           * targetReg        = NULL,
                           TR::Register           * sourceReg2       = NULL,
@@ -5021,7 +5021,7 @@ class S390VRIeInstruction : public S390VRIInstruction
    public:
    S390VRIeInstruction(
                           TR::CodeGenerator      * cg               = NULL,
-                          TR::InstOpCode::Mnemonic          op               = TR::InstOpCode::BAD,
+                          TR::InstOpCode::Mnemonic          op               = TR::InstOpCode::bad,
                           TR::Node               * n                = NULL,
                           TR::Register           * targetReg        = NULL,
                           TR::Register           * sourceReg2       = NULL,
@@ -5059,7 +5059,7 @@ class S390VRIfInstruction : public S390VRIInstruction
    public:
    S390VRIfInstruction(
                           TR::CodeGenerator      * cg               = NULL,
-                          TR::InstOpCode::Mnemonic          op               = TR::InstOpCode::BAD,
+                          TR::InstOpCode::Mnemonic          op               = TR::InstOpCode::bad,
                           TR::Node               * n                = NULL,
                           TR::Register           * targetReg        = NULL,
                           TR::Register           * sourceReg2       = NULL,
@@ -5098,7 +5098,7 @@ class S390VRIgInstruction : public S390VRIInstruction
    public:
    S390VRIgInstruction(
                           TR::CodeGenerator      * cg               = NULL,
-                          TR::InstOpCode::Mnemonic          op      = TR::InstOpCode::BAD,
+                          TR::InstOpCode::Mnemonic          op      = TR::InstOpCode::bad,
                           TR::Node               * n                = NULL,
                           TR::Register           * targetReg        = NULL,
                           TR::Register           * sourceReg2       = NULL,
@@ -5133,7 +5133,7 @@ class S390VRIhInstruction : public S390VRIInstruction
    public:
    S390VRIhInstruction(
                           TR::CodeGenerator      * cg               = NULL,
-                          TR::InstOpCode::Mnemonic     op           = TR::InstOpCode::BAD,
+                          TR::InstOpCode::Mnemonic     op           = TR::InstOpCode::bad,
                           TR::Node               * n                = NULL,
                           TR::Register           * targetReg        = NULL,
                           uint16_t                constantImm2      = 0,    /*  16 bits */
@@ -5166,7 +5166,7 @@ class S390VRIiInstruction : public S390VRIInstruction
    public:
    S390VRIiInstruction(
                           TR::CodeGenerator      * cg               = NULL,
-                          TR::InstOpCode::Mnemonic          op      = TR::InstOpCode::BAD,
+                          TR::InstOpCode::Mnemonic          op      = TR::InstOpCode::bad,
                           TR::Node               * n                = NULL,
                           TR::Register           * targetReg        = NULL,
                           TR::Register           * sourceReg2       = NULL,
@@ -5230,7 +5230,7 @@ class S390VRRInstruction : public S390VInstruction
    protected:
    S390VRRInstruction(
                          TR::CodeGenerator       * cg  = NULL,
-                         TR::InstOpCode::Mnemonic           op  = TR::InstOpCode::BAD,
+                         TR::InstOpCode::Mnemonic           op  = TR::InstOpCode::bad,
                          TR::Node                * n   = NULL,
                          TR::Register            * targetReg  = NULL,
                          TR::Register            * sourceReg2 = NULL,
@@ -5301,7 +5301,7 @@ class S390VRRaInstruction: public S390VRRInstruction
    public:
    S390VRRaInstruction(
                           TR::CodeGenerator       * cg         = NULL,
-                          TR::InstOpCode::Mnemonic           op         = TR::InstOpCode::BAD,
+                          TR::InstOpCode::Mnemonic           op         = TR::InstOpCode::bad,
                           TR::Node                * n          = NULL,
                           TR::Register            * targetReg  = NULL,
                           TR::Register            * sourceReg2 = NULL,
@@ -5375,7 +5375,7 @@ class S390VRRcInstruction: public S390VRRInstruction
    public:
    S390VRRcInstruction(
                           TR::CodeGenerator       * cg  = NULL,
-                          TR::InstOpCode::Mnemonic           op  = TR::InstOpCode::BAD,
+                          TR::InstOpCode::Mnemonic           op  = TR::InstOpCode::bad,
                           TR::Node                * n   = NULL,
                           TR::Register            * targetReg  = NULL,
                           TR::Register            * sourceReg2 = NULL,
@@ -5408,7 +5408,7 @@ class S390VRRdInstruction: public S390VRRInstruction
    public:
    S390VRRdInstruction(
                           TR::CodeGenerator       * cg  = NULL,
-                          TR::InstOpCode::Mnemonic           op  = TR::InstOpCode::BAD,
+                          TR::InstOpCode::Mnemonic           op  = TR::InstOpCode::bad,
                           TR::Node                * n   = NULL,
                           TR::Register            * targetReg  = NULL,
                           TR::Register            * sourceReg2 = NULL,
@@ -5446,7 +5446,7 @@ class S390VRReInstruction: public S390VRRInstruction
    public:
    S390VRReInstruction(
                           TR::CodeGenerator       * cg  = NULL,
-                          TR::InstOpCode::Mnemonic           op  = TR::InstOpCode::BAD,
+                          TR::InstOpCode::Mnemonic           op  = TR::InstOpCode::bad,
                           TR::Node                * n   = NULL,
                           TR::Register            * targetReg  = NULL,
                           TR::Register            * sourceReg2 = NULL,
@@ -5484,7 +5484,7 @@ class S390VRRfInstruction: public S390VRRInstruction
    public:
    S390VRRfInstruction(
                           TR::CodeGenerator       * cg  = NULL,
-                          TR::InstOpCode::Mnemonic           op  = TR::InstOpCode::BAD,
+                          TR::InstOpCode::Mnemonic           op  = TR::InstOpCode::bad,
                           TR::Node                * n   = NULL,
                           TR::Register            * targetReg  = NULL,
                           TR::Register            * sourceReg2 = NULL, /* GPR */
@@ -5515,7 +5515,7 @@ class S390VRRgInstruction: public S390VRRInstruction
    public:
    S390VRRgInstruction(
                           TR::CodeGenerator       * cg         = NULL,
-                          TR::InstOpCode::Mnemonic  op         = TR::InstOpCode::BAD,
+                          TR::InstOpCode::Mnemonic  op         = TR::InstOpCode::bad,
                           TR::Node                * n          = NULL,
                           TR::Register            * v1Reg  = NULL)
    : S390VRRInstruction(cg, op, n, v1Reg, NULL, 0, 0, 0, 0)
@@ -5539,7 +5539,7 @@ class S390VRRhInstruction: public S390VRRInstruction
    public:
    S390VRRhInstruction(
                           TR::CodeGenerator       * cg         = NULL,
-                          TR::InstOpCode::Mnemonic         op  = TR::InstOpCode::BAD,
+                          TR::InstOpCode::Mnemonic         op  = TR::InstOpCode::bad,
                           TR::Node                * n          = NULL,
                           TR::Register            * v1Reg      = NULL,
                           TR::Register            * v2Reg      = NULL,
@@ -5568,7 +5568,7 @@ class S390VRRiInstruction: public S390VRRInstruction
    public:
    S390VRRiInstruction(
                           TR::CodeGenerator       * cg         = NULL,
-                          TR::InstOpCode::Mnemonic   op        = TR::InstOpCode::BAD,
+                          TR::InstOpCode::Mnemonic   op        = TR::InstOpCode::bad,
                           TR::Node                * n          = NULL,
                           TR::Register            * r1Reg      = NULL, /* GPR */
                           TR::Register            * v2Reg      = NULL,
@@ -5689,7 +5689,7 @@ class S390VRSInstruction : public S390VInstruction
    protected:
    S390VRSInstruction(
                          TR::CodeGenerator       * cg           = NULL,
-                         TR::InstOpCode::Mnemonic           op           = TR::InstOpCode::BAD,
+                         TR::InstOpCode::Mnemonic           op           = TR::InstOpCode::bad,
                          TR::Node                * n            = NULL,
                          TR::Register            * targetReg    = NULL,   /* VRF        */
                          TR::Register            * sourceReg    = NULL,   /* VRF or GPR */
@@ -5713,7 +5713,7 @@ class S390VRSaInstruction : public S390VStorageInstruction
    public:
    S390VRSaInstruction(
                          TR::CodeGenerator       * cg           = NULL,
-                         TR::InstOpCode::Mnemonic   op          = TR::InstOpCode::BAD,
+                         TR::InstOpCode::Mnemonic   op          = TR::InstOpCode::bad,
                          TR::Node                * n            = NULL,
                          TR::Register            * targetReg    = NULL,   /* VRF */
                          TR::Register            * sourceReg    = NULL,   /* VRF */
@@ -5754,7 +5754,7 @@ class S390VRSbInstruction : public S390VStorageInstruction
    public:
    S390VRSbInstruction(
                          TR::CodeGenerator       * cg           = NULL,
-                         TR::InstOpCode::Mnemonic           op  = TR::InstOpCode::BAD,
+                         TR::InstOpCode::Mnemonic           op  = TR::InstOpCode::bad,
                          TR::Node                * n            = NULL,
                          TR::Register            * targetReg    = NULL,   /* VRF */
                          TR::Register            * sourceReg    = NULL,   /* GPR */
@@ -5795,7 +5795,7 @@ class S390VRScInstruction : public S390VStorageInstruction
    public:
    S390VRScInstruction(
                          TR::CodeGenerator       * cg           = NULL,
-                         TR::InstOpCode::Mnemonic           op           = TR::InstOpCode::BAD,
+                         TR::InstOpCode::Mnemonic           op           = TR::InstOpCode::bad,
                          TR::Node                * n            = NULL,
                          TR::Register            * targetReg    = NULL,   /* GPR */
                          TR::Register            * sourceReg    = NULL,   /* VRF */
@@ -5843,7 +5843,7 @@ class S390VRSdInstruction : public S390VStorageInstruction
    public:
    S390VRSdInstruction(
                          TR::CodeGenerator       * cg           = NULL,
-                         TR::InstOpCode::Mnemonic     op        = TR::InstOpCode::BAD,
+                         TR::InstOpCode::Mnemonic     op        = TR::InstOpCode::bad,
                          TR::Node                * n            = NULL,
                          TR::Register            * r3Reg        = NULL,   /* GPR */
                          TR::Register            * v1Reg        = NULL,   /* VRF */
@@ -5905,7 +5905,7 @@ class S390VRVInstruction : public S390VStorageInstruction
    public:
    S390VRVInstruction(
                          TR::CodeGenerator       * cg           = NULL,
-                         TR::InstOpCode::Mnemonic           op           = TR::InstOpCode::BAD,
+                         TR::InstOpCode::Mnemonic           op           = TR::InstOpCode::bad,
                          TR::Node                * n            = NULL,
                          TR::Register            * sourceReg    = NULL,   /* VRF */
                          TR::MemoryReference * mr           = NULL,
@@ -5946,7 +5946,7 @@ class S390VRXInstruction : public S390VStorageInstruction
    public:
    S390VRXInstruction(
                          TR::CodeGenerator       * cg           = NULL,
-                         TR::InstOpCode::Mnemonic           op           = TR::InstOpCode::BAD,
+                         TR::InstOpCode::Mnemonic           op           = TR::InstOpCode::bad,
                          TR::Node              * n            = NULL,
                          TR::Register            * reg          = NULL,   /* GPR */
                          TR::MemoryReference * mr           = NULL,
@@ -5987,7 +5987,7 @@ class S390VSIInstruction : public S390VStorageInstruction
    {
    public:
    S390VSIInstruction(TR::CodeGenerator       * cg           = NULL,
-                      TR::InstOpCode::Mnemonic  op           = TR::InstOpCode::BAD,
+                      TR::InstOpCode::Mnemonic  op           = TR::InstOpCode::bad,
                       TR::Node                * n            = NULL,
                       TR::Register            * v1Reg        = NULL,
                       TR::MemoryReference     * memRef       = NULL,
diff --git a/compiler/z/codegen/UnaryEvaluator.cpp b/compiler/z/codegen/UnaryEvaluator.cpp
index d62ef7f5550..fe812f1fe89 100644
--- a/compiler/z/codegen/UnaryEvaluator.cpp
+++ b/compiler/z/codegen/UnaryEvaluator.cpp
@@ -159,7 +159,7 @@ OMR::Z::TreeEvaluator::iabsEvaluator(TR::Node * node, TR::CodeGenerator * cg)
 
    TR::Register * sourceRegister = cg->evaluate(firstChild);
    TR::Register * targetRegister;
-   TR::InstOpCode::Mnemonic opCode  = TR::InstOpCode::BAD;
+   TR::InstOpCode::Mnemonic opCode  = TR::InstOpCode::bad;
    if (node->getOpCodeValue() == TR::fabs)
       opCode = TR::InstOpCode::LPEBR;
    else if (node->getOpCodeValue() == TR::dabs)