From 5a46f00fc81ce0b65e092ea719453474e8c84af5 Mon Sep 17 00:00:00 2001 From: BradleyWood Date: Mon, 12 Jun 2023 16:14:56 -0600 Subject: [PATCH] x86: Support AVX512-CD Signed-off-by: BradleyWood --- compiler/env/ProcessorInfo.hpp | 5 ++-- compiler/x/codegen/OMRCodeGenerator.hpp | 1 + compiler/x/codegen/OMRInstOpCode.hpp | 32 ++++++++++++++++--------- compiler/x/env/OMRCPU.cpp | 7 +++++- 4 files changed, 31 insertions(+), 14 deletions(-) diff --git a/compiler/env/ProcessorInfo.hpp b/compiler/env/ProcessorInfo.hpp index 419f454dfee..fb4e78dce6b 100644 --- a/compiler/env/ProcessorInfo.hpp +++ b/compiler/env/ProcessorInfo.hpp @@ -177,7 +177,7 @@ enum TR_X86ProcessorFeatures8 TR_IntelProcessorTrace = 0x02000000, // Reserved by Intel = 0x04000000, // Reserved by Intel = 0x08000000, - // Reserved by Intel = 0x10000000, + TR_AVX512CD = 0x10000000, TR_SHA = 0x20000000, TR_AVX512BW = 0x40000000, TR_AVX512VL = 0x80000000, @@ -191,7 +191,8 @@ inline uint32_t getFeatureFlags8Mask() | TR_AVX512F | TR_AVX512VL | TR_AVX512BW - | TR_AVX512DQ; + | TR_AVX512DQ + | TR_AVX512CD; } enum TR_ProcessorDescription diff --git a/compiler/x/codegen/OMRCodeGenerator.hpp b/compiler/x/codegen/OMRCodeGenerator.hpp index 853d66e19fd..9d3bce84ef1 100644 --- a/compiler/x/codegen/OMRCodeGenerator.hpp +++ b/compiler/x/codegen/OMRCodeGenerator.hpp @@ -165,6 +165,7 @@ struct TR_X86ProcessorInfo bool supportsAVX512F() {return testFeatureFlags8(TR_AVX512F) && enabledXSAVE();} bool supportsAVX512BW() {return testFeatureFlags8(TR_AVX512BW) && enabledXSAVE();} bool supportsAVX512DQ() {return testFeatureFlags8(TR_AVX512DQ) && enabledXSAVE();} + bool supportsAVX512CD() {return testFeatureFlags8(TR_AVX512CD) && enabledXSAVE();} bool supportsAVX512VL() {return testFeatureFlags8(TR_AVX512VL) && enabledXSAVE();} bool supportsBMI1() {return testFeatureFlags8(TR_BMI1) && enabledXSAVE();} bool supportsBMI2() {return testFeatureFlags8(TR_BMI2) && enabledXSAVE();} diff --git a/compiler/x/codegen/OMRInstOpCode.hpp b/compiler/x/codegen/OMRInstOpCode.hpp index e8e19f827cf..d77b8ad18fc 100644 --- a/compiler/x/codegen/OMRInstOpCode.hpp +++ b/compiler/x/codegen/OMRInstOpCode.hpp @@ -169,17 +169,20 @@ namespace TR { class Register; } #define X86FeatureProp_EVEX128RequiresAVX512VL 0x00001000 // EVEX-128 encoded version requires AVX-512VL #define X86FeatureProp_EVEX128RequiresAVX512BW 0x00002000 // EVEX-128 encoded version requires AVX-512BW #define X86FeatureProp_EVEX128RequiresAVX512DQ 0x00004000 // EVEX-128 encoded version requires AVX-512DQ -#define X86FeatureProp_EVEX256Supported 0x00008000 // ISA supports EVEX-256 encoded version -#define X86FeatureProp_EVEX256RequiresAVX512F 0x00010000 // EVEX-256 encoded version requires AVX-512F -#define X86FeatureProp_EVEX256RequiresAVX512VL 0x00020000 // EVEX-256 encoded version requires AVX-512VL -#define X86FeatureProp_EVEX256RequiresAVX512BW 0x00040000 // EVEX-256 encoded version requires AVX-512BW -#define X86FeatureProp_EVEX256RequiresAVX512DQ 0x00080000 // EVEX-256 encoded version requires AVX-512DQ -#define X86FeatureProp_EVEX512Supported 0x00100000 // ISA supports EVEX-512 encoded version -#define X86FeatureProp_EVEX512RequiresAVX512F 0x00200000 // EVEX-512 encoded version requires AVX-512F -#define X86FeatureProp_EVEX512RequiresAVX512BW 0x00400000 // EVEX-512 encoded version requires AVX-512BW -#define X86FeatureProp_EVEX512RequiresAVX512DQ 0x00800000 // EVEX-512 encoded version requires AVX-512DQ -#define X86FeatureProp_VEX128RequiresFMA 0x01000000 // VEX-128 encoded version requires AVX -#define X86FeatureProp_VEX256RequiresFMA 0x02000000 // VEX-128 encoded version requires AVX +#define X86FeatureProp_EVEX128RequiresAVX512CD 0x00008000 // EVEX-128 encoded version requires AVX-512CD +#define X86FeatureProp_EVEX256Supported 0x00010000 // ISA supports EVEX-256 encoded version +#define X86FeatureProp_EVEX256RequiresAVX512F 0x00020000 // EVEX-256 encoded version requires AVX-512F +#define X86FeatureProp_EVEX256RequiresAVX512VL 0x00040000 // EVEX-256 encoded version requires AVX-512VL +#define X86FeatureProp_EVEX256RequiresAVX512BW 0x00080000 // EVEX-256 encoded version requires AVX-512BW +#define X86FeatureProp_EVEX256RequiresAVX512DQ 0x00100000 // EVEX-256 encoded version requires AVX-512DQ +#define X86FeatureProp_EVEX256RequiresAVX512CD 0x00200000 // EVEX-256 encoded version requires AVX-512CD +#define X86FeatureProp_EVEX512Supported 0x00400000 // ISA supports EVEX-512 encoded version +#define X86FeatureProp_EVEX512RequiresAVX512F 0x00800000 // EVEX-512 encoded version requires AVX-512F +#define X86FeatureProp_EVEX512RequiresAVX512BW 0x01000000 // EVEX-512 encoded version requires AVX-512BW +#define X86FeatureProp_EVEX512RequiresAVX512DQ 0x02000000 // EVEX-512 encoded version requires AVX-512DQ +#define X86FeatureProp_EVEX512RequiresAVX512CD 0x04000000 // EVEX-512 encoded version requires AVX-512CD +#define X86FeatureProp_VEX128RequiresFMA 0x08000000 // VEX-128 encoded version requires AVX +#define X86FeatureProp_VEX256RequiresFMA 0x10000000 // VEX-128 encoded version requires AVX typedef enum { @@ -493,6 +496,8 @@ class InstOpCode: public OMR::InstOpCode supported = target->supportsFeature(OMR_FEATURE_X86_AVX512BW); if (supported && flags & X86FeatureProp_EVEX128RequiresAVX512DQ) supported = target->supportsFeature(OMR_FEATURE_X86_AVX512DQ); + if (supported && flags & X86FeatureProp_EVEX128RequiresAVX512CD) + supported = target->supportsFeature(OMR_FEATURE_X86_AVX512CD); if (supported) return OMR::X86::EVEX_L128; @@ -531,6 +536,8 @@ class InstOpCode: public OMR::InstOpCode supported = target->supportsFeature(OMR_FEATURE_X86_AVX512BW); if (supported && flags & X86FeatureProp_EVEX256RequiresAVX512DQ) supported = target->supportsFeature(OMR_FEATURE_X86_AVX512DQ); + if (supported && flags & X86FeatureProp_EVEX128RequiresAVX512CD) + supported = target->supportsFeature(OMR_FEATURE_X86_AVX512CD); if (supported) return OMR::X86::EVEX_L256; @@ -560,6 +567,9 @@ class InstOpCode: public OMR::InstOpCode if (supported && flags & X86FeatureProp_EVEX512RequiresAVX512DQ) supported = target->supportsFeature(OMR_FEATURE_X86_AVX512DQ); + if (supported && flags & X86FeatureProp_EVEX128RequiresAVX512CD) + supported = target->supportsFeature(OMR_FEATURE_X86_AVX512CD); + if (supported) return OMR::X86::EVEX_L512; diff --git a/compiler/x/env/OMRCPU.cpp b/compiler/x/env/OMRCPU.cpp index 6ce7cd49ef3..16d45acd80b 100644 --- a/compiler/x/env/OMRCPU.cpp +++ b/compiler/x/env/OMRCPU.cpp @@ -42,7 +42,7 @@ OMR::X86::CPU::detect(OMRPortLibrary * const omrPortLib) OMR_FEATURE_X86_POPCNT, OMR_FEATURE_X86_AESNI, OMR_FEATURE_X86_OSXSAVE, OMR_FEATURE_X86_AVX, OMR_FEATURE_X86_AVX2, OMR_FEATURE_X86_FMA, OMR_FEATURE_X86_HLE, OMR_FEATURE_X86_RTM, OMR_FEATURE_X86_AVX512F, OMR_FEATURE_X86_AVX512VL, - OMR_FEATURE_X86_AVX512BW, OMR_FEATURE_X86_AVX512DQ + OMR_FEATURE_X86_AVX512BW, OMR_FEATURE_X86_AVX512DQ, OMR_FEATURE_X86_AVX512CD }; OMRPORT_ACCESS_FROM_OMRPORT(omrPortLib); @@ -386,6 +386,8 @@ OMR::X86::CPU::supports_feature_test(uint32_t feature) return TR::CodeGenerator::getX86ProcessorInfo().supportsAVX512BW(); case OMR_FEATURE_X86_AVX512DQ: return TR::CodeGenerator::getX86ProcessorInfo().supportsAVX512DQ(); + case OMR_FEATURE_X86_AVX512CD: + return TR::CodeGenerator::getX86ProcessorInfo().supportsAVX512CD(); default: return false; } @@ -588,6 +590,9 @@ OMR::X86::CPU::supports_feature_old_api(uint32_t feature) case OMR_FEATURE_X86_AVX512DQ: supported = TR::CodeGenerator::getX86ProcessorInfo().supportsAVX512DQ(); break; + case OMR_FEATURE_X86_AVX512CD: + supported = TR::CodeGenerator::getX86ProcessorInfo().supportsAVX512CD(); + break; case OMR_FEATURE_X86_FMA: supported = TR::CodeGenerator::getX86ProcessorInfo().supportsFMA(); break;