From 694185f4ea8357d18fd51804d6c16165fa228125 Mon Sep 17 00:00:00 2001 From: Daryl Maier Date: Thu, 30 May 2024 12:39:30 -0400 Subject: [PATCH] Eliminate targetSupportsSoftwarePrefetches flag This flag was always set to true and all supported target x86 processors support prefetch instructions. This flag is unnecessary. Signed-off-by: Daryl Maier --- compiler/x/codegen/OMRCodeGenerator.cpp | 4 +--- compiler/x/codegen/OMRCodeGenerator.hpp | 8 +------- 2 files changed, 2 insertions(+), 10 deletions(-) diff --git a/compiler/x/codegen/OMRCodeGenerator.cpp b/compiler/x/codegen/OMRCodeGenerator.cpp index c41133ffe12..980c5f796c7 100644 --- a/compiler/x/codegen/OMRCodeGenerator.cpp +++ b/compiler/x/codegen/OMRCodeGenerator.cpp @@ -323,15 +323,13 @@ OMR::X86::CodeGenerator::initializeX86(TR::Compilation *comp) self()->setXMMDoubleLoadOpCode(TR::InstOpCode::MOVSDRegMem); } - self()->setTargetSupportsSoftwarePrefetches(); - // Enable software prefetch of the TLH and configure the TLH prefetching // geometry. // TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->compilePortableCode() || comp->target().cpu.is(OMR_PROCESSOR_X86_INTEL_CORE2) == comp->cg()->getX86ProcessorInfo().isIntelCore2(), "isIntelCore2() failed\n"); TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->compilePortableCode() || comp->target().cpu.is(OMR_PROCESSOR_X86_INTEL_NEHALEM) == comp->cg()->getX86ProcessorInfo().isIntelNehalem(), "isIntelNehalem() failed\n"); if (((!comp->getOption(TR_DisableTLHPrefetch) && (comp->target().cpu.is(OMR_PROCESSOR_X86_INTEL_CORE2) || comp->target().cpu.is(OMR_PROCESSOR_X86_INTEL_NEHALEM))) || - (comp->getOption(TR_TLHPrefetch) && self()->targetSupportsSoftwarePrefetches()))) + (comp->getOption(TR_TLHPrefetch)))) { self()->setEnableTLHPrefetching(); } diff --git a/compiler/x/codegen/OMRCodeGenerator.hpp b/compiler/x/codegen/OMRCodeGenerator.hpp index b9dd5f32d55..4a2cc7353a9 100644 --- a/compiler/x/codegen/OMRCodeGenerator.hpp +++ b/compiler/x/codegen/OMRCodeGenerator.hpp @@ -800,7 +800,7 @@ class OMR_EXTENSIBLE CodeGenerator : public OMR::CodeGenerator EnableTLHPrefetching = 0x00000800, ///< enable software prefetches on TLH allocates // Available = 0x00001000, // Available = 0x00002000, - TargetSupportsSoftwarePrefetches = 0x00004000, ///< target processor and OS both support software prefetch instructions + // Available = 0x00004000, MethodEnterExitTracingEnabled = 0x00008000, ///< trace method enter/exits // Available = 0x00010000, PushPreservedRegisters = 0x00020000 ///< we've chosen to save/restore preserved regs using push/pop instructions instead of movs @@ -848,12 +848,6 @@ class OMR_EXTENSIBLE CodeGenerator : public OMR::CodeGenerator } void setEnableRegisterAssociations() {_flags.set(EnableRegisterAssociations);} - bool targetSupportsSoftwarePrefetches() - { - return _flags.testAny(TargetSupportsSoftwarePrefetches); - } - void setTargetSupportsSoftwarePrefetches() {_flags.set(TargetSupportsSoftwarePrefetches);} - bool enableTLHPrefetching() { return _flags.testAny(EnableTLHPrefetching);