diff --git a/compiler/aarch64/codegen/ARM64Debug.cpp b/compiler/aarch64/codegen/ARM64Debug.cpp index 010fd5ca8aa..b9e8c83e7b6 100644 --- a/compiler/aarch64/codegen/ARM64Debug.cpp +++ b/compiler/aarch64/codegen/ARM64Debug.cpp @@ -93,6 +93,7 @@ static const char *ARM64ExtendCodeNames[] = static const char *opCodeToNameMap[] = { + "assocreg", "bad", "cbzw", "cbnzw", @@ -751,7 +752,6 @@ static const char *opCodeToNameMap[] = "dd", "label", "vgdnop", - "assocreg" }; const char * diff --git a/compiler/aarch64/codegen/OMRInstOpCode.enum b/compiler/aarch64/codegen/OMRInstOpCode.enum index 0eda5a8a955..cb04ef501c4 100644 --- a/compiler/aarch64/codegen/OMRInstOpCode.enum +++ b/compiler/aarch64/codegen/OMRInstOpCode.enum @@ -741,6 +741,5 @@ dd, // Define word label, // Destination of a jump vgdnop, // Virtual Guard NOP instruction - assocreg, // Associate real registers with Virtual registers. - ARM64LastOp = assocreg, + ARM64LastOp = vgdnop, ARM64NumOpCodes = ARM64LastOp+1, diff --git a/compiler/codegen/OMRInstOpCode.enum b/compiler/codegen/OMRInstOpCode.enum index 7364aab88f1..e2ec7163b9e 100644 --- a/compiler/codegen/OMRInstOpCode.enum +++ b/compiler/codegen/OMRInstOpCode.enum @@ -24,3 +24,4 @@ * definitions are permitted. */ + assocreg, // Register Association \ No newline at end of file diff --git a/compiler/p/codegen/OMRInstOpCode.enum b/compiler/p/codegen/OMRInstOpCode.enum index 8a621af6529..1eba832ff30 100644 --- a/compiler/p/codegen/OMRInstOpCode.enum +++ b/compiler/p/codegen/OMRInstOpCode.enum @@ -546,7 +546,6 @@ wrtbar, // Write barrier directive proc, // Entry to the method dd, // define word - assocreg, // Associate real registers with Virtual registers. vgdnop, // Virtual Guard NOP instruction probenop, // Probe NOP (for RI) iflong, // compare and branch long diff --git a/compiler/p/codegen/OMRInstOpCodeProperties.hpp b/compiler/p/codegen/OMRInstOpCodeProperties.hpp index ec55657503a..a260062dd19 100644 --- a/compiler/p/codegen/OMRInstOpCodeProperties.hpp +++ b/compiler/p/codegen/OMRInstOpCodeProperties.hpp @@ -25,6 +25,17 @@ */ + { + /* .mnemonic = */ OMR::InstOpCode::assocreg, + /* .name = */ "assocreg", + /* .description = "Associate real registers with Virtual registers.", */ + /* .prefix = */ 0x00000000, + /* .opcode = */ 0x00000000, + /* .format = */ FORMAT_NONE, + /* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN, + /* .properties = */ PPCOpProp_SyncSideEffectFree, + }, + { /* .mnemonic = */ OMR::InstOpCode::bad, /* .name = */ "bad", @@ -6257,17 +6268,6 @@ /* .properties = */ PPCOpProp_None, }, - { - /* .mnemonic = */ OMR::InstOpCode::assocreg, - /* .name = */ "assocreg", - /* .description = "Associate real registers with Virtual registers.", */ - /* .prefix = */ 0x00000000, - /* .opcode = */ 0x00000000, - /* .format = */ FORMAT_NONE, - /* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN, - /* .properties = */ PPCOpProp_SyncSideEffectFree, - }, - { /* .mnemonic = */ OMR::InstOpCode::vgdnop, /* .name = */ "vgdnop", diff --git a/compiler/p/codegen/OMRRegisterDependency.cpp b/compiler/p/codegen/OMRRegisterDependency.cpp index fc6d20d4546..b9fe4e21eff 100644 --- a/compiler/p/codegen/OMRRegisterDependency.cpp +++ b/compiler/p/codegen/OMRRegisterDependency.cpp @@ -531,7 +531,7 @@ void OMR::Power::RegisterDependencyConditions::bookKeepingRegisterUses(TR::Instr if (instr->getOpCodeValue() == TR::InstOpCode::assocreg) return; - // Don't track associations or emit assocregs in outlined code + // Don't track associations or emit assocreg in outlined code // Register assigner can save/restore associations across outlined sections properly, however no such mechanism exists for instruction selection // so we don't want these associations to clobber the associations that were set in main line code, which are more important // TODO: Fix this by saving/restoring the associations in swapInstructionListsWithCompilation() @@ -570,7 +570,7 @@ void OMR::Power::RegisterDependencyConditions::bookKeepingRegisterUses(TR::Instr if (numAssoc > 0) { - // Emit an AssocRegs instruction to track the previous association + // Emit an assocreg instruction to track the previous association assoc->setNumPostConditions(numAssoc, cg->trMemory()); generateDepInstruction(cg, TR::InstOpCode::assocreg, instr->getNode(), assoc, instr->getPrev()); } diff --git a/compiler/p/codegen/OMRTreeEvaluator.cpp b/compiler/p/codegen/OMRTreeEvaluator.cpp index a817afe7ecd..7ad5565c659 100644 --- a/compiler/p/codegen/OMRTreeEvaluator.cpp +++ b/compiler/p/codegen/OMRTreeEvaluator.cpp @@ -4767,7 +4767,7 @@ TR::Register *OMR::Power::TreeEvaluator::BBEndEvaluator(TR::Node *node, TR::Code numAssoc++; } } - // Emit an AssocRegs instruction to track the previous association + // Emit an assocreg instruction to track the previous association if( numAssoc > 0 ) { assoc->setNumPostConditions(numAssoc, cg->trMemory()); diff --git a/compiler/p/codegen/PPCInstruction.cpp b/compiler/p/codegen/PPCInstruction.cpp index 711995120e6..5b4dd0695ce 100644 --- a/compiler/p/codegen/PPCInstruction.cpp +++ b/compiler/p/codegen/PPCInstruction.cpp @@ -134,7 +134,7 @@ void TR::PPCDepInstruction::assignRegisters(TR_RegisterKinds kindToBeAssigned) } else { - // Restore the register association using the ASSOCREGS instruction info + // Restore the register association using the assocreg instruction info int i; TR::RegisterDependencyConditions *assocreg = getDependencyConditions(); TR::RegisterDependency *assoc; diff --git a/compiler/riscv/codegen/RVDebug.cpp b/compiler/riscv/codegen/RVDebug.cpp index 1dbd2e35dad..6bf90088ccd 100644 --- a/compiler/riscv/codegen/RVDebug.cpp +++ b/compiler/riscv/codegen/RVDebug.cpp @@ -39,6 +39,7 @@ static const char *opCodeToNameMap[] = { + "assocreg", "bad", /* * RISC-V instructions diff --git a/compiler/z/codegen/InstOpCode.cpp b/compiler/z/codegen/InstOpCode.cpp index 15221d554f4..9bdd466c7f6 100644 --- a/compiler/z/codegen/InstOpCode.cpp +++ b/compiler/z/codegen/InstOpCode.cpp @@ -60,7 +60,7 @@ uint32_t OMR::Z::InstOpCode::isAdmin() { return (_mnemonic == RET || - _mnemonic == ASSOCREGS || + _mnemonic == assocreg || _mnemonic == DEPEND || _mnemonic == FENCE || _mnemonic == PROC || diff --git a/compiler/z/codegen/OMRInstOpCode.enum b/compiler/z/codegen/OMRInstOpCode.enum index e6c27ec79cb..1ed708ec727 100644 --- a/compiler/z/codegen/OMRInstOpCode.enum +++ b/compiler/z/codegen/OMRInstOpCode.enum @@ -28,7 +28,6 @@ /* Pseudo Instructions */ - ASSOCREGS, // Register Association BAD, // Bad Opcode BREAK, // Breakpoint (debugger) DC, // DC diff --git a/compiler/z/codegen/OMRInstOpCodeProperties.hpp b/compiler/z/codegen/OMRInstOpCodeProperties.hpp index 090066ee9d8..23821980eeb 100644 --- a/compiler/z/codegen/OMRInstOpCodeProperties.hpp +++ b/compiler/z/codegen/OMRInstOpCodeProperties.hpp @@ -26,8 +26,8 @@ { - /* .mnemonic = */ OMR::InstOpCode::ASSOCREGS, - /* .name = */ "ASSOCREGS", + /* .mnemonic = */ OMR::InstOpCode::assocreg, + /* .name = */ "assocreg", /* .description = */ "Register Association", /* .opcode[0] = */ 0x00, /* .opcode[1] = */ 0x00, diff --git a/compiler/z/codegen/OMRInstruction.cpp b/compiler/z/codegen/OMRInstruction.cpp index e41ce4ec62f..3f0999ce3ca 100644 --- a/compiler/z/codegen/OMRInstruction.cpp +++ b/compiler/z/codegen/OMRInstruction.cpp @@ -169,10 +169,10 @@ OMR::Z::Instruction::initialize(TR::Instruction * precedingInstruction, bool ins if (cond) { - // Don't want to increment total use counts for ASSOCREGS instructions + // Don't want to increment total use counts for assocreg instructions // because their register references will confuse the code that tries // to determine when the first use of a register takes place - if (condFlag || self()->getOpCodeValue() != TR::InstOpCode::ASSOCREGS) + if (condFlag || self()->getOpCodeValue() != TR::InstOpCode::assocreg) { cond->bookKeepingRegisterUses(self(), cg); if(cond->getPreConditions()) cond->getPreConditions()->incNumUses(); @@ -767,7 +767,7 @@ OMR::Z::Instruction::assignRegisters(TR_RegisterKinds kindToBeAssigned) { TR::Compilation *comp = self()->cg()->comp(); - if (self()->getOpCodeValue() != TR::InstOpCode::ASSOCREGS) + if (self()->getOpCodeValue() != TR::InstOpCode::assocreg) { self()->assignRegistersAndDependencies(kindToBeAssigned); } diff --git a/compiler/z/codegen/OMRMachine.cpp b/compiler/z/codegen/OMRMachine.cpp index 68ccfeb5506..551dbd8709a 100644 --- a/compiler/z/codegen/OMRMachine.cpp +++ b/compiler/z/codegen/OMRMachine.cpp @@ -4061,7 +4061,7 @@ OMR::Z::Machine::createRegisterAssociationDirective(TR::Instruction * cursor) associations->addPostCondition(self()->getVirtualAssociatedWithReal(regNum), regNum); } - TR::Instruction *cursor1 = new (self()->cg()->trHeapMemory(), TR_MemoryBase::S390Instruction) TR::Instruction(cursor, TR::InstOpCode::ASSOCREGS, associations, self()->cg()); + TR::Instruction *cursor1 = new (self()->cg()->trHeapMemory(), TR_MemoryBase::S390Instruction) TR::Instruction(cursor, TR::InstOpCode::assocreg, associations, self()->cg()); if (cursor == self()->cg()->getAppendInstruction()) { diff --git a/compiler/z/codegen/OMRRegisterDependency.cpp b/compiler/z/codegen/OMRRegisterDependency.cpp index 5afdf13e10f..d40312ce5a9 100644 --- a/compiler/z/codegen/OMRRegisterDependency.cpp +++ b/compiler/z/codegen/OMRRegisterDependency.cpp @@ -692,7 +692,7 @@ OMR::Z::RegisterDependencyConditions::usesRegister(TR::Register * r) void OMR::Z::RegisterDependencyConditions::bookKeepingRegisterUses(TR::Instruction * instr, TR::CodeGenerator * cg, int32_t oldPreCursor, int32_t oldPostCursor) { - if (instr->getOpCodeValue() != TR::InstOpCode::ASSOCREGS) + if (instr->getOpCodeValue() != TR::InstOpCode::assocreg) { // We create a register association directive for each dependency diff --git a/compiler/z/codegen/OMRTreeEvaluator.cpp b/compiler/z/codegen/OMRTreeEvaluator.cpp index 9b84ef033e6..4de47f8a37a 100644 --- a/compiler/z/codegen/OMRTreeEvaluator.cpp +++ b/compiler/z/codegen/OMRTreeEvaluator.cpp @@ -2267,7 +2267,7 @@ tryGenerateCLCForComparison(TR::Node *node, TR::CodeGenerator *cg) // ------------------------------ // // [0x000003ff9e44be48] CLC Auto[] ?+0(3,GPR5), Shadow[] 0(&GPR_6161) - // [0x000003ff9e44c190] ASSOCREGS + // [0x000003ff9e44c190] assocreg // [0x000003ff9e44bf88] BRC MASK3(0x6), Label L0175 // // \\ gnu/testlet/java/text/DateFormat/Test.test(Lgnu/testlet/TestHarness;)V @@ -2279,7 +2279,7 @@ tryGenerateCLCForComparison(TR::Node *node, TR::CodeGenerator *cg) // \\ 354 JBinvokevirtual 52 gnu/testlet/java/text/DateFormat/Test.equals(Ljava/lang/Object;)Z // \\ 19 JBifacmpeq 24 // 0x000003ffdf6cb13a 0000333e [0x000003ff9e44be48] d5 02 50 78 70 00 CLC Auto[] 120(3,GPR5), Shadow[] 0(GPR7) - // 0x000003ffdf6cb140 00003344 [0x000003ff9e44c190] ASSOCREGS + // 0x000003ffdf6cb140 00003344 [0x000003ff9e44c190] assocreg // 0x000003ffdf6cb140 00003344 [0x000003ff9e44bf88] a7 64 12 fc BRC MASK3(0x6), Label L0175, labelTargetAddr=0x000003FFDF6CD738 bool operand1IsVFTSymbol = operand1->getOpCode().hasSymbolReference() && (operand1->getSymbolReference() == comp->getSymRefTab()->findVftSymbolRef()); @@ -9523,7 +9523,7 @@ OMR::Z::TreeEvaluator::BBEndEvaluator(TR::Node * node, TR::CodeGenerator * cg) if (!nextTT || !nextTT->getNode()->getBlock()->isExtensionOfPreviousBlock()) { if (cg->enableRegisterAssociations() && - cg->getAppendInstruction()->getOpCodeValue() != TR::InstOpCode::ASSOCREGS) + cg->getAppendInstruction()->getOpCodeValue() != TR::InstOpCode::assocreg) { cg->machine()->createRegisterAssociationDirective(cg->getAppendInstruction()); } diff --git a/compiler/z/codegen/OpMemToMem.cpp b/compiler/z/codegen/OpMemToMem.cpp index 3b600532874..11f00087a2b 100644 --- a/compiler/z/codegen/OpMemToMem.cpp +++ b/compiler/z/codegen/OpMemToMem.cpp @@ -1527,7 +1527,7 @@ MemCmpVarLenMacroOp::generate(TR::Register* dstReg, TR::Register* srcReg, TR::Re if(_startControlFlow==NULL) { _startControlFlow=cursorBefore->getNext(); - if(_startControlFlow->getOpCodeValue() == TR::InstOpCode::ASSOCREGS) _startControlFlow=_startControlFlow->getNext(); + if(_startControlFlow->getOpCodeValue() == TR::InstOpCode::assocreg) _startControlFlow=_startControlFlow->getNext(); } if(_startControlFlow != _cursor) { @@ -1569,7 +1569,7 @@ MemCmpConstLenMacroOp::generate(TR::Register* dstReg, TR::Register* srcReg, TR:: if(_startControlFlow==NULL) { _startControlFlow=cursorBefore->getNext(); - if(_startControlFlow->getOpCodeValue() == TR::InstOpCode::ASSOCREGS) _startControlFlow=_startControlFlow->getNext(); + if(_startControlFlow->getOpCodeValue() == TR::InstOpCode::assocreg) _startControlFlow=_startControlFlow->getNext(); } if(_startControlFlow != _cursor) { @@ -1663,7 +1663,7 @@ MemCmpVarLenSignMacroOp::generate(TR::Register* dstReg, TR::Register* srcReg, TR if(_startControlFlow==NULL) { _startControlFlow=cursorBefore->getNext(); - if(_startControlFlow->getOpCodeValue() == TR::InstOpCode::ASSOCREGS) _startControlFlow=_startControlFlow->getNext(); + if(_startControlFlow->getOpCodeValue() == TR::InstOpCode::assocreg) _startControlFlow=_startControlFlow->getNext(); } if(_startControlFlow != _cursor) { @@ -1712,7 +1712,7 @@ MemCmpConstLenSignMacroOp::generate(TR::Register* dstReg, TR::Register* srcReg, if(_startControlFlow==NULL) { _startControlFlow=cursorBefore->getNext(); - if(_startControlFlow->getOpCodeValue() == TR::InstOpCode::ASSOCREGS) _startControlFlow=_startControlFlow->getNext(); + if(_startControlFlow->getOpCodeValue() == TR::InstOpCode::assocreg) _startControlFlow=_startControlFlow->getNext(); } if(_startControlFlow != _cursor) { diff --git a/compiler/z/codegen/OpMemToMem.hpp b/compiler/z/codegen/OpMemToMem.hpp index 6bb5f9a5c44..22997d9408f 100644 --- a/compiler/z/codegen/OpMemToMem.hpp +++ b/compiler/z/codegen/OpMemToMem.hpp @@ -86,7 +86,7 @@ class MemToMemMacroOp if(_startControlFlow==NULL) { _startControlFlow=cursorBefore->getNext(); - if(_startControlFlow->getOpCodeValue() == TR::InstOpCode::ASSOCREGS) _startControlFlow=_startControlFlow->getNext(); + if(_startControlFlow->getOpCodeValue() == TR::InstOpCode::assocreg) _startControlFlow=_startControlFlow->getNext(); } if(_startControlFlow != _cursor) { diff --git a/compiler/z/codegen/S390Debug.cpp b/compiler/z/codegen/S390Debug.cpp index a1bd8a22ba2..279f22fa204 100644 --- a/compiler/z/codegen/S390Debug.cpp +++ b/compiler/z/codegen/S390Debug.cpp @@ -158,7 +158,7 @@ TR_Debug::printz(TR::FILE *pOutFile, TR::Instruction * instr) } // dump the inst's pre deps - if (instr->getOpCodeValue() != TR::InstOpCode::ASSOCREGS && _comp->cg()->getCodeGeneratorPhase() <= TR::CodeGenPhase::BinaryEncodingPhase) + if (instr->getOpCodeValue() != TR::InstOpCode::assocreg && _comp->cg()->getCodeGeneratorPhase() <= TR::CodeGenPhase::BinaryEncodingPhase) dumpDependencies(pOutFile, instr, true, false); switch (instr->getKind()) @@ -352,10 +352,10 @@ TR_Debug::printz(TR::FILE *pOutFile, TR::Instruction * instr) case TR::Instruction::IsNotExtended: case TR::Instruction::IsE: { - // ASSOCREGS piggy backs on a vanilla TR::Instruction - // if (instr->getOpCodeValue() == TR::InstOpCode::ASSOCREGS) break; + // assocreg piggy backs on a vanilla TR::Instruction + // if (instr->getOpCodeValue() == TR::InstOpCode::assocreg) break; - if ((instr->getOpCodeValue() == TR::InstOpCode::ASSOCREGS) && /*(debug("traceMsg90RA"))*/ + if ((instr->getOpCodeValue() == TR::InstOpCode::assocreg) && /*(debug("traceMsg90RA"))*/ (_comp->getOption(TR_TraceRA))) { if (_comp->cg()->getCodeGeneratorPhase() < TR::CodeGenPhase::BinaryEncodingPhase) @@ -371,7 +371,7 @@ TR_Debug::printz(TR::FILE *pOutFile, TR::Instruction * instr) } // dump the inst's post deps - if (instr->getOpCodeValue() != TR::InstOpCode::ASSOCREGS && _comp->cg()->getCodeGeneratorPhase() <= TR::CodeGenPhase::BinaryEncodingPhase) + if (instr->getOpCodeValue() != TR::InstOpCode::assocreg && _comp->cg()->getCodeGeneratorPhase() <= TR::CodeGenPhase::BinaryEncodingPhase) dumpDependencies(pOutFile, instr, false, true); }