From ecd2dddc69f34d813cab064491b788b0451b77b3 Mon Sep 17 00:00:00 2001 From: KONNO Kazuhiro Date: Wed, 5 Jun 2024 15:45:12 +0900 Subject: [PATCH] AArch64: Improve *cmpeq-*select instruction sequence This commit improves the instruction sequence for *select nodes with a *cmpeq node as the first child. Signed-off-by: KONNO Kazuhiro --- .../aarch64/codegen/ControlFlowEvaluator.cpp | 32 ++++++++++++++++--- 1 file changed, 28 insertions(+), 4 deletions(-) diff --git a/compiler/aarch64/codegen/ControlFlowEvaluator.cpp b/compiler/aarch64/codegen/ControlFlowEvaluator.cpp index 24e5f3dcf31..978c77defa4 100644 --- a/compiler/aarch64/codegen/ControlFlowEvaluator.cpp +++ b/compiler/aarch64/codegen/ControlFlowEvaluator.cpp @@ -816,7 +816,6 @@ OMR::ARM64::TreeEvaluator::iselectEvaluator(TR::Node *node, TR::CodeGenerator *c TR::Node *trueNode = node->getChild(1); TR::Node *falseNode = node->getChild(2); - TR::Register *condReg = cg->evaluate(condNode); TR::Register *trueReg = cg->evaluate(trueNode); TR::Register *falseReg = cg->evaluate(falseNode); TR::Register *resultReg = trueReg; @@ -844,11 +843,36 @@ OMR::ARM64::TreeEvaluator::iselectEvaluator(TR::Node *node, TR::CodeGenerator *c resultReg = (node->getOpCodeValue() == TR::aselect) ? cg->allocateCollectedReferenceRegister() : cg->allocateRegister(); } - generateCompareImmInstruction(cg, node, condReg, 0, true); // 64-bit compare - generateCondTrg1Src2Instruction(cg, TR::InstOpCode::cselx, node, resultReg, trueReg, falseReg, TR::CC_NE); + if ((condNode->getOpCodeValue() == TR::acmpeq + || condNode->getOpCodeValue() == TR::lcmpeq + || condNode->getOpCodeValue() == TR::icmpeq + || condNode->getOpCodeValue() == TR::scmpeq + || condNode->getOpCodeValue() == TR::bcmpeq) + && condNode->getReferenceCount() == 1 + && condNode->getRegister() == NULL) + { + TR::Node *cmp1Node = condNode->getChild(0); + TR::Node *cmp2Node = condNode->getChild(1); + TR::Register *cmp1Reg = cg->evaluate(cmp1Node); + TR::Register *cmp2Reg = cg->evaluate(cmp2Node); + bool is64bit = (condNode->getOpCodeValue() == TR::acmpeq || condNode->getOpCodeValue() == TR::lcmpeq); + + generateCompareInstruction(cg, node, cmp1Reg, cmp2Reg, is64bit); + generateCondTrg1Src2Instruction(cg, TR::InstOpCode::cselx, node, resultReg, trueReg, falseReg, TR::CC_EQ); + + cg->recursivelyDecReferenceCount(condNode); + } + else + { + TR::Register *condReg = cg->evaluate(condNode); + + generateCompareImmInstruction(cg, node, condReg, 0, true); // 64-bit compare + generateCondTrg1Src2Instruction(cg, TR::InstOpCode::cselx, node, resultReg, trueReg, falseReg, TR::CC_NE); + + cg->decReferenceCount(condNode); + } node->setRegister(resultReg); - cg->decReferenceCount(condNode); cg->decReferenceCount(trueNode); cg->decReferenceCount(falseNode);