MarcheProcessor

A wide-word pipelined processor with 128-bit data path.

• Verilog RTL design of the 4-stage pipelined Troy Wideword Processor, with 128-bit datapath.
• Verilog testbenches have been developed for each Verilog module to support unit testing and regression testing. A Makefile is provided for "build automation" (or the automation of analyzing and elaborating the RTL designs, and simulating them).
• See TROY_AJM_ZO.pdf for the project report.
• See processor.pdf for an addendum to the project report.