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Make simple io mem handler endian aware

As an alternative to the 3 individual handlers, there is also a simplified
io mem hook function. To be consistent, let's add an endianness parameter
there too.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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1 parent 2507c12 commit 6bef04365589b1b82be1a1c3aa223f4bddb3dabb @agraf agraf committed with blueswirl Dec 8, 2010
Showing with 17 additions and 10 deletions.
  1. +2 −1 hw/apb_pci.c
  2. +8 −4 hw/pci_host.c
  3. +4 −2 hw/unin_pci.c
  4. +2 −2 rwhandler.c
  5. +1 −1 rwhandler.h
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3 hw/apb_pci.c
@@ -418,7 +418,8 @@ static int pci_pbm_init_device(SysBusDevice *dev)
/* PCI configuration space */
s->pci_config_handler.read = apb_pci_config_read;
s->pci_config_handler.write = apb_pci_config_write;
- pci_config = cpu_register_io_memory_simple(&s->pci_config_handler);
+ pci_config = cpu_register_io_memory_simple(&s->pci_config_handler,
+ DEVICE_NATIVE_ENDIAN);
assert(pci_config >= 0);
/* at region 1 */
sysbus_init_mmio(dev, 0x1000000ULL, pci_config);
View
12 hw/pci_host.c
@@ -187,9 +187,11 @@ int pci_host_conf_register_mmio(PCIHostState *s, int swap)
{
pci_host_init(s);
if (swap) {
- return cpu_register_io_memory_simple(&s->conf_handler);
+ return cpu_register_io_memory_simple(&s->conf_handler,
+ DEVICE_NATIVE_ENDIAN);
} else {
- return cpu_register_io_memory_simple(&s->conf_noswap_handler);
+ return cpu_register_io_memory_simple(&s->conf_noswap_handler,
+ DEVICE_NATIVE_ENDIAN);
}
}
@@ -203,9 +205,11 @@ int pci_host_data_register_mmio(PCIHostState *s, int swap)
{
pci_host_init(s);
if (swap) {
- return cpu_register_io_memory_simple(&s->data_handler);
+ return cpu_register_io_memory_simple(&s->data_handler,
+ DEVICE_NATIVE_ENDIAN);
} else {
- return cpu_register_io_memory_simple(&s->data_noswap_handler);
+ return cpu_register_io_memory_simple(&s->data_noswap_handler,
+ DEVICE_NATIVE_ENDIAN);
}
}
View
6 hw/unin_pci.c
@@ -154,7 +154,8 @@ static int pci_unin_main_init_device(SysBusDevice *dev)
pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1);
s->data_handler.read = unin_data_read;
s->data_handler.write = unin_data_write;
- pci_mem_data = cpu_register_io_memory_simple(&s->data_handler);
+ pci_mem_data = cpu_register_io_memory_simple(&s->data_handler,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
@@ -175,7 +176,8 @@ static int pci_u3_agp_init_device(SysBusDevice *dev)
pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1);
s->data_handler.read = unin_data_read;
s->data_handler.write = unin_data_write;
- pci_mem_data = cpu_register_io_memory_simple(&s->data_handler);
+ pci_mem_data = cpu_register_io_memory_simple(&s->data_handler,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
View
4 rwhandler.c
@@ -35,14 +35,14 @@ static CPUReadMemoryFunc * const cpu_io_memory_simple_read[] = {
&cpu_io_memory_simple_readl,
};
-int cpu_register_io_memory_simple(struct ReadWriteHandler *handler)
+int cpu_register_io_memory_simple(struct ReadWriteHandler *handler, int endian)
{
if (!handler->read || !handler->write) {
return -1;
}
return cpu_register_io_memory(cpu_io_memory_simple_read,
cpu_io_memory_simple_write,
- handler, DEVICE_NATIVE_ENDIAN);
+ handler, endian);
}
RWHANDLER_WRITE(ioport_simple_writeb, 1, uint32_t);
View
2 rwhandler.h
@@ -19,7 +19,7 @@ struct ReadWriteHandler {
/* Helpers for when we want to use a single routine with length. */
/* CPU memory handler: both read and write must be present. */
-int cpu_register_io_memory_simple(ReadWriteHandler *);
+int cpu_register_io_memory_simple(ReadWriteHandler *, int endian);
/* io port handler: can supply only read or write handlers. */
int register_ioport_simple(ReadWriteHandler *,
pio_addr_t start, int length, int size);

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