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FPGA88_SC_HD_Verilog
Merge branch 'RTL-dev' into erc-fixes
April 5, 2023 06:33
def
reharden user_project_wrapper
April 28, 2023 20:12
doc
add remaining design files
March 20, 2022 11:43
dv
updating ccff_test
March 30, 2022 09:29
env
tapeout
July 5, 2022 02:26
firmware
add firmware files
April 10, 2022 12:15
gds
reharden user_project_wrapper
April 28, 2023 20:12
lef
reharden user_project_wrapper
April 28, 2023 20:12
lib
reharden all tiles
April 27, 2023 02:31
mag
reharden user_project_wrapper
April 28, 2023 20:12
maglef
reharden user_project_wrapper
April 28, 2023 20:12
openfpga/input
add remaining design files
March 20, 2022 11:43
openlane
reharden fpga_core
April 28, 2023 20:11
scripts
tapeout
July 5, 2022 02:26
sdc
reharden user_project_wrapper
April 28, 2023 20:12
sdf
reharden user_project_wrapper
April 28, 2023 20:12
signoff
+ add cvc results log (missing from commit 271f73e)
May 8, 2023 02:46
spef
reharden user_project_wrapper
April 28, 2023 20:12
spi/lvs
reharden user_project_wrapper
April 28, 2023 20:12
verilog
reharden user_project_wrapper
April 28, 2023 20:12
.gitignore
~ update .gitignore to add generated libs and sdf files for caravel…
April 18, 2023 15:48
LICENSE
initial commit
March 20, 2022 11:29
Makefile
~ update Makefile to the latest caravel_user_project one
April 30, 2023 06:49
README.md
initial commit
March 20, 2022 11:29
repreducability.md
updates
June 29, 2022 08:25
timing.mk
add timing files
July 1, 2022 15:24