A Complete Mixed-Signal ASIC implementation of the PicoSoc/PicoRV32
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LICENSE Initial Commit - Raven FOSS Oct 25, 2018
README Update README Oct 25, 2018

README

Raven:  An ASIC hardware implementation of the PicoSoc PicoRV32
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Designed by efabless engineering
San Jose, CA
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The purpose of this repository is to provide a completely free
and open-source simulation environment for the Raven chip.  The
Raven chip itself can be found in the efabless IP catalog.  See
https://efabless.com (registration is required to view the IP
catalog.  Regitration is free and validation is not required to
view the catalog contents.  However, validation is required to
use the efabless design environments; e.g., to view the layout
of the raven chip on the Open Galaxy design platform).

The simulation environment matches the reference design in the
efabless IP catalog functionally, and can be used to write
software/firmware that will run on the Raven test board.

The requirements for simulating the Raven chip are:  iverilog
(iverilog.icarus.com), and the RISC-V gcc configured for the
RISC-V options used by the picoRV32 processor design.  The best
way to obtain the correct gcc cross-compiler is to install the
picoRV32 source from github
(https://github.com/cliffordwolf/picorv32).  The Makefile in
the picoRV32 repository automatically downloads and locally
installs the correct gcc cross-compiler.  In this repository,
it is necessary to change the path to gcc in verilog/Makefile
and verilog/*/Makefile to match the local installation.  Once
that is done, cd to the "verilog/" directory and run "make" to
run the simulation test suite.

Documentation on the memory mapping and the SPI slave interface
can be found in the "doc/" directory.