{"payload":{"header_redesign_enabled":false,"results":[{"id":"330422935","archived":false,"color":"#adb2cb","followers":1,"has_funding_file":false,"hl_name":"eimon96/VHDL","hl_trunc_description":null,"language":"VHDL","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":330422935,"name":"VHDL","owner_id":18515231,"owner_login":"eimon96","updated_at":"2021-02-22T21:04:57.551Z","has_issues":true}},"sponsorable":false,"topics":["vhdl","logic-gates","vhdl-code","vhdl-coursework","vhdl-testbench"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":73,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Aeimon96%252FVHDL%2B%2Blanguage%253AVHDL","metadata":null,"csrf_tokens":{"/eimon96/VHDL/star":{"post":"WY_FHVfYAIvEqBWYUkl8TlQkNjIE6-qze9vDfHLKXx3jXmJrn4cBPL0oFDk4VGF7p7cJAhp0Jm7WU8YsJglNSA"},"/eimon96/VHDL/unstar":{"post":"cFhcbMyeciN8v1zXHXq0NRmV2e0qkW5DSTJr_-f5q6SMOJRxCfnOelKSstTupLCYNWTMP_8wLt2ecq0M_1eKaw"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"6LOVeNXYABmj6sDiV-joYxeueliYjki0lM6BJXl7-1iwOVXIiJSsUz5YupAUcu-RI2bbiHmM3b9rR8_Il0sGVg"}}},"title":"Repository search results"}