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  1. MIT 6.004x Beta RISC processor Implemented and synthesized on an FPGA. This is the Verilog version of the Beta with all the testbenches required.

    C 2

  2. custom shift scheduling utility

    Python 1

  3. This is where all the projects i did for Online courses, Student activites, self projects are posted

    C#

  4. All the projects required in this year Operating systems class exist here

    C

  5. A simple low power I2c slave, this is just a prototype

    Verilog

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Contribution activity

March 2021

Opened 1 issue in 1 repository
pytest-dev/pytest
1 open

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