The RISC-V Microcontroller Profile
A proposal for a friendlier microcontroller architecture using the beautiful RISC-V instruction set.
- Liviu Ionescu
Warning: This draft specification is in a preliminary phase and may change at any time. For the moment it is more like a wish list than a real specs document.
"People are more expensive than transistors".
Table of Contents
- Memory Map
- The Startup Process
- Exceptions and Interrupts
- Control and Status Registers (CSRs)
- Hart Control Block (
- Hart Interrupt Controller (
- Device Control Block (
- Device Real-Time Clock (
- Device System Clock (
- Device Watchdog Timer (
- Embedded ABI (EABI)
- RTOS Support Features
- Appendix A: Improvements upon RISC-V privileged <--- Read Me First!
- Appendix B: Interrupts use cases
- Appendix C: History
- Appendix D: Contributing
- add MPU definitions
- add more details about the restrictions in user mode.
This document is released under a Creative Commons Attribution 4.0 International license.