Generally the RISC-V microcontroller memory map is implementation specific; the only reserved area in the RISC-V microcontroller profile is a slice at the end of the memory space, called the system control area.
Typical RISC-V microcontroller devices have:
- a read-only code area, usually at 0x00000000, but the actual address may be implementation specific (typically flash)
- a read-write data area (typically RAM)
- an implementation specific peripheral area.
Multi-hart devices can share certain memory areas (code or data), but can also have hart-specific memory areas, or both shared and specific areas.
The system control area
The system control area is a slice of 256 MiB at the end of the memory space. This area must have the execute permissions removed, and attempts to execute code from it must trigger an exceptions (instruction access fault).
For 32-bits devices, the system control area is 0xF0000000-0xFFFFFFFF.
For 64-bits devices, the system control area is 0xFFFFFFFF'F0000000-0xFFFFFFFF'FFFFFFFF.
The system control area is implemented as a set of memory-mapped address spaces, some providing control and status registers common for the entire device, and some providing control and status registers for the current hart:
||The Device Control Block.|
||The Device System Clock.|
||The Device Real-Time Clock.|
||The Device Watchdog Timer.|
||The Hart Control Block.|
||The Hart Interrupt Controller.|
Each hart has its own separate control block; all HCBs map to the same address, the internal logic being able to distinguish between them based on the ID of the hart requesting access; thus each hart can access only its own hart control block.
Same for the Hart Interrupt Controller.
(the addresses are preliminary, need more work to find a solution easy to decode)
TODO [PA]: reserving space in the system control area for debug program buffer, in case an implementation chooses to make the buffer memory mapped.