Fix -bit adjective (singular)

csrs.md

@@ -11,7 +11,7 @@ Unless otherwise mentioned, write access to the CSRs is limited to machine/privi
 
 ## Hart ID Register (`hartid`)
 
-The `hartid` CSR is an xlen-bits read-only register containing the integer ID of the
+The `hartid` CSR is an xlen-bit read-only register containing the integer ID of the
 hart running the code. This register must be readable in any implementation.
 In single-hart devices, it always reads 0. In multi-hart devices, the hart IDs might
 not necessarily be numbered contiguously
@@ -28,7 +28,7 @@ This CSR is identical to `mhartid` in the RISC-V privileged profile.
 
 ## Configuration and control (`ctrl`)
 
-The `ctrl` CSR is an xlen-bits read/write register that controls several aspects of the hart
+The `ctrl` CSR is an xlen-bit read/write register that controls several aspects of the hart
 functionality.
 
 | Bits | Name | Type | Reset | Description |
@@ -52,7 +52,7 @@ TODO: allocate a number for it.
 
 ## Mode and status (`status`)
 
-The `status` CSR is an xlen-bits read/write register that identifies the
+The `status` CSR is an xlen-bit read/write register that identifies the
 current hart mode and status.
 
 | Bits | Name | Type | Reset | Description |
@@ -73,7 +73,7 @@ TODO: allocate a number for it.
 
 ## Interrupt Enable (`iena`)
 
-The `iena` CSR is an xlen-bits read/write register that controls whether the interrupt
+The `iena` CSR is an xlen-bit read/write register that controls whether the interrupt
 are enabled or not.
 
 This register has a single bit on purpose. Access to the interrupt enable bit must be quite
@@ -90,7 +90,7 @@ TODO: allocate a number for it.
 
 ## Interrupt Priority Threshold (`iprioth`)
 
-The `iprioth` CSR is an xlen-bits read/write register that holds the interrupts threshold.
+The `iprioth` CSR is an xlen-bit read/write register that holds the interrupts threshold.
 Only interrupts requests that have a priority strictly greater than the threshold will cause
 an interrupt to become active. The threshold register must always be able to hold the value zero,
 in which case, no interrupts are masked. The threshold register must also be able to hold
@@ -126,7 +126,7 @@ TODO: allocate a number for it.
 
 ## Interrupt Priority Threshold Increase (`ipriothinc`)
 
-The `ipriothinc` CSR behaves like an xlen-bits read/write register, but in fact uses the
+The `ipriothinc` CSR behaves like an xlen-bit read/write register, but in fact uses the
 same register as `iprioth`. The difference is that writes to this CSR are effective only
 if the new value is higher than the current value, in other words it guarantees that the
 interrupt threshold is not decreased.
@@ -150,7 +150,7 @@ TODO: allocate a number for it.
 
 ## Main Stack Pointer (`spm`)
 
-The `spm` CSR is an xlen-bits read-write register that holds the main stack pointer.
+The `spm` CSR is an xlen-bit read-write register that holds the main stack pointer.
 It is always the default stack pointer after reset. Interrupts and exceptions always
 use this stack to store the exception frame.
 
@@ -167,7 +167,7 @@ TODO: allocate a number for it.
 
 ## Main Stack Pointer Limit (`spmlimit`)
 
-The `msplimit` CSR is an xlen-bits read-write register that holds the lowest address
+The `msplimit` CSR is an xlen-bit read-write register that holds the lowest address
 the main stack can descend.
 
 | Bits | Name | Type | Reset | Description |
@@ -187,7 +187,7 @@ TODO: allocate a number for it.
 
 ## Thread Stack Pointer (`spt`)
 
-The `spt` CSR is an xlen-bits read-write register that holds the stack pointer used
+The `spt` CSR is an xlen-bit read-write register that holds the stack pointer used
 by the application current thread. It is intended to multi-threaded applications.
 
 This register is a CSR because access to the stack pointer may occur in context switching
@@ -204,7 +204,7 @@ TODO: allocate a number for it.
 
 ## Thread Stack Pointer Limit (`sptlimit`)
 
-The `tsplimit` CSR is an xlen-bits read-write register that holds the lowest address
+The `tsplimit` CSR is an xlen-bit read-write register that holds the lowest address
 the thread stack can descend.
 
 This register is a CSR because access to the stack pointer limit may occur in context switching

hart-control-block.md

@@ -40,7 +40,7 @@ same address in the memory space.
 
 ## Exceptions vector table address (`excvta`)
 
-An xlen-bits register that holds the address of the exceptions dispatch table.
+An xlen-bit register that holds the address of the exceptions dispatch table.
 The table is an array of addresses
 (xlen size elements) pointing to exception handlers (C/C++ functions).
 
@@ -50,7 +50,7 @@ If not set (i.e. 0x0) and an exception occurs, the behaviour is undefined.
 
 ## Interrupts vector table address (`intvta`)
 
-An xlen-bits register that holds the address of the interrupts dispatch table.
+An xlen-bit register that holds the address of the interrupts dispatch table.
 The table is an array of addresses
 (xlen size elements) pointing to interrupt handlers (C/C++ functions).
 
@@ -63,7 +63,7 @@ to determine at runtime if the hart implements an interrupt controller.
 
 ## The highest interrupt number (`intmax`)
 
-The `intmax` read-only register is 32-bits and reads the highest interrupt number; it is
+The `intmax` read-only register is 32-bit and reads the highest interrupt number; it is
 useful when iterating the Hart Interrupt Controller array.
 
 ## The system clock comparator
@@ -76,22 +76,22 @@ See the Device Real-Time Clock page.
 
 ## Cycle count
 
-The `cyclecnt` register is 64-bits wide and holds a count of the number of clock cycles
+The `cyclecnt` register is 64-bit wide and holds a count of the number of clock cycles
 executed by the core on which the hart is running (not the hart itself!) from an
 arbitrary start time in the past. In practice, the underlying 64-bit counter should never
 overflow between two samples. The rate at which the cycle counter advances will depend
 on the implementation and operating environment. The execution environment
 should provide a means to determine the current rate (cycles/second) at which
 the cycle counter is incrementing.
 
-RV64 devices expose a single 64-bits register, accessible with 64-bits instructions.
-RV32 devices exposes separate high/low 32-bits registers.
+RV64 devices expose a single 64-bit register, accessible with 64-bit instructions.
+RV32 devices exposes separate high/low 32-bit registers.
 
 ## Instructions count
 
-The `instcnt` register is 64-bits wide and counts the number of instructions executed
+The `instcnt` register is 64-bit wide and counts the number of instructions executed
 by this hart from some arbitrary start point in the past.
 
-RV64 devices expose a single 64-bits register, accessible with 64-bits instructions.
-RV32 devices exposes separate high/low 32-bits registers.
+RV64 devices expose a single 64-bit register, accessible with 64-bit instructions.
+RV32 devices exposes separate high/low 32-bit registers.
 

improvements-upon-privileged.md

@@ -470,7 +470,7 @@ C application programmers to fully take control of their applications.
 > "RISC-V microcontrollers should compare to PIC or AVR devices"
 
 This was probably true 10-15 years ago, but today it is no longer the case.
-Not only the industry migrated to 32-bits cores, but the ecosystems around
+Not only the industry migrated to 32-bit cores, but the ecosystems around
 Cortex-M and the ease of use made most of the other cores irrelevant.
 
 There is also another fact to be noted: according to several studies, the
@@ -494,7 +494,7 @@ but with nested, pre-emptive high priority interrupts, even a single hart device
 can handle multiple tasks very well, and if the real-time tasks are driven by ISRs,
 then the network stack can run at a lower priority.
 
-### 64-bits microcontrollers will never be needed
+### 64-bit microcontrollers will never be needed
 
 > "Why 64-bit? Any system big enough to need more
 than 32-bit addressing is probably already running an operating system
@@ -504,20 +504,20 @@ That's a good question. By the time 8051 was king, many questioned
 why would someone think of 16-bit microcontrollers. While some were
 debating this, vendors gradually offered devices with 12 address
 bits, then 16 bits, even 24 bits. Cortex-M came boldly and provided
-32-bits registers and a large (32-bits) linear address space.
+32-bit registers and a large (32-bit) linear address space.
 
 Although a 4 GiB memory space may be enough for most current devices,
-it should be noted that 64-bits devices bring not only a wider memory
-space, but also 64-bits registers, and native atomic 64-bits accesses.
+it should be noted that 64-bit devices bring not only a wider memory
+space, but also 64-bit registers, and native atomic 64-bit accesses.
 
-Applications with lots of integer arithmetic may benefit from 64-bits
+Applications with lots of integer arithmetic may benefit from 64-bit
 cores, and, indirectly, applications manupulating double floating point
 numbers may also benefit.
 
-Also applications with large and fast timers benefit from atomic 64-bits
-accesses, which otherwise require a lot of juggling on a 32-bits platform
+Also applications with large and fast timers benefit from atomic 64-bit
+accesses, which otherwise require a lot of juggling on a 32-bit platform
 (see the recommended RISC-V mechanism to access the timer registers on
-a 32-bits device).
+a 32-bit device).
 
 ## Proposed steps to change the current RISC-V specs
 

interrupt-controller.md

@@ -59,7 +59,7 @@ pending
 * `active`: interrupts can either be in an active (being served) or inactive state
 * `prio`: interrupt priority
 
-To store and control these attributes, each interrupt has two 32-bits registers:
+To store and control these attributes, each interrupt has two 32-bit registers:
 
 | Offset | Name | Width | Type | Reset | Description |
 |:-------|:-----|:------|:-----|:------|-------------|

introduction.md

@@ -31,14 +31,14 @@ Since there are many microcontroller configurations, 3 classes were identified:
 
 - **ES** (embedded small) **ES-RV32E** if possible, otherwise **ES-RV32I[M][C]**:
 **low end**, single hart,
-32-bits, no floating point, no unprivileged mode (intended to support legacy PIC & AVR class
+32-bit, no floating point, no unprivileged mode (intended to support legacy PIC & AVR class
 applications; comparable with Cortex-M0)
 - **EM** (embedded medium) **EM-RV32IM[F[D]]C** / **EM-RV64IM[F[D]]C**:
-**regular**, single hart, 32/64-bits, possibly with floating point
+**regular**, single hart, 32/64-bit, possibly with floating point
 (intended to support common multi-threaded applications; comparable with
 Cortex-M3/M4)
 - **EL** (embedded large) **EL-RV32IMA[F[D]]C** / **EL-RV64IMA[F[D]]C**:
-**high end**, multi-hart/multi-core, 32/64-bits, atomics, possibly with floating point
+**high end**, multi-hart/multi-core, 32/64-bit, atomics, possibly with floating point
 (intended to support hard real-time, high performance applications)
 
 ## Benefits

memory-map.md

@@ -20,9 +20,9 @@ The system control area is a slice of 256 MiB at the end of the memory space. Th
 must have the execute permissions removed, and attempts to execute code from it must trigger
 an exceptions (instruction access fault).
 
-For 32-bits devices, the system control area is **0xF0000000-0xFFFFFFFF**.
+For 32-bit devices, the system control area is **0xF0000000-0xFFFFFFFF**.
 
-For 64-bits devices, the system control area is **0xFFFFFFFF'F0000000-0xFFFFFFFF'FFFFFFFF**.
+For 64-bit devices, the system control area is **0xFFFFFFFF'F0000000-0xFFFFFFFF'FFFFFFFF**.
 
 The system control area is implemented as a set of memory-mapped address spaces, some providing control and status registers common for the entire
 device, and some providing control and status registers for the current hart:

real-time-clock.md

@@ -81,8 +81,8 @@ The real-time clock time point register is a 64-bit counter, common on all RV32
 
 To guarantee the steadiness characteristic of the clock, the register is read-only.
 
-RV64 devices expose a single 64-bits register, accessible with 64-bits instructions.
-RV32 devices exposes separate high/low 32-bits registers.
+RV64 devices expose a single 64-bit register, accessible with 64-bit instructions.
+RV32 devices exposes separate high/low 32-bit registers.
 
 ## The clock comparator register
 
@@ -96,8 +96,8 @@ counter register
 contains a value greater than or equal to the value in the comparator register.
 The interrupt remains posted until it is cleared by writing to the comparator register.
 
-RV64 devices expose a single 64-bits register, accessible with 64-bits instructions.
-RV32 devices exposes separate high/low 32-bits registers.
+RV64 devices expose a single 64-bit register, accessible with 64-bit instructions.
+RV32 devices exposes separate high/low 32-bit registers.
 
 ## Usage
 

system-clock.md

@@ -91,12 +91,12 @@ By default, the system clock starts disabled; software must enable it during sta
 
 ## The clock counter register
 
-The system clock time point register is a 64-bits counter, common on all RV32 and RV64 devices.
+The system clock time point register is a 64-bit counter, common on all RV32 and RV64 devices.
 
 To guarantee the steadiness characteristic of the clock, the register is read-only. At reset, the register is cleared to 0.
 
-RV64 devices expose a single 64-bits register, accessible with 64-bits instructions.
-RV32 devices exposes separate high/low 32-bits registers.
+RV64 devices expose a single 64-bit register, accessible with 64-bit instructions.
+RV32 devices exposes separate high/low 32-bit registers.
 
 ## The clock comparator register
 
@@ -115,8 +115,8 @@ Only hart 0 is required to have a comparator. If any other harts also have compa
 the `sysclock_cmp` interrupt is posted only to the local hart. For harts that do not have
 a comparator, this register always reads as 0 and writes are ignored.
 
-RV64 devices expose a single 64-bits register, accessible with 64-bits instructions.
-RV32 devices exposes separate high/low 32-bits registers.
+RV64 devices expose a single 64-bit register, accessible with 64-bit instructions.
+RV32 devices exposes separate high/low 32-bit registers.
 
 ## Usage