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Preliminary RISCV support#804

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MabezDev:feature/riscv
Jun 19, 2022
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Preliminary RISCV support#804
bors[bot] merged 1 commit into
embassy-rs:masterfrom
MabezDev:feature/riscv

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@MabezDev MabezDev commented Jun 10, 2022 •
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  • Moves the default Interrupt implementation into a cortex_m specific module
  • Adds a RISCV32 executor based on osobiehl's work in esp32c3 mess work

(FYI esp implementation of embassy traits etc, is being developed here)

bonus ascii cinema

This was referenced Jun 10, 2022
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jessebraham
jessebraham reviewed Jun 14, 2022
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Comment thread embassy/src/executor/arch/riscv32.rs Outdated
@MabezDev MabezDev force-pushed the feature/riscv branch 3 times, most recently from 69d7bc4 to 540ffc6 Compare June 19, 2022 21:21
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Dirbaio commented Jun 19, 2022

@MabezDev LGTM, could you squash?

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arch:riscv32
31e8006 
- Add basic riscv32 executor
- Add 16MHZ timer support
Dirbaio
Dirbaio approved these changes Jun 19, 2022
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🚀!!! Thank you! :)

bors r+

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bors Bot commented Jun 19, 2022

Build succeeded:

@bors bors Bot merged commit e4fbfaf into embassy-rs:master Jun 19, 2022
huntc
huntc reviewed Jun 19, 2022
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Comment thread embassy/src/executor/arch/riscv32.rs
bors Bot added a commit that referenced this pull request Jun 22, 2022
@bors @MabezDev
Merge #805
4a6f69e 
805: Preliminary Xtensa support r=Dirbaio a=MabezDev

Based on the work in #804.

I hope non-upstream target support is acceptable :).

Co-authored-by: Scott Mabin <scott@mabez.dev>
kaspar030 pushed a commit to kaspar030/embassy that referenced this pull request Aug 18, 2025
@thvdveld
Merge pull request embassy-rs#804 from thvdveld/rpl-parents-use-linea…
6831e86 
…r-map

rpl: use LinearMap for the ParentSet
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@huntc huntc huntc left review comments

@Dirbaio Dirbaio Dirbaio approved these changes

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@jessebraham jessebraham jessebraham left review comments

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@MabezDev @Dirbaio @huntc @jessebraham