bindings/python/llvm/disassembler.py

@@ -36,7 +36,7 @@
 
 
 _initialized = False
-_targets = ['AArch64', 'ARM', 'Hexagon', 'MSP430', 'Mips', 'NVPTX', 'PowerPC', 'R600', 'Sparc', 'SystemZ', 'X86', 'XCore']
+_targets = ['AArch64', 'ARM', 'Hexagon', 'MSP430', 'Mips', 'NVPTX', 'PowerPC', 'R600', 'Sparc', 'SystemZ', 'AAP', 'X86', 'XCore']
 def _ensure_initialized():
     global _initialized
     if not _initialized:

cmake/config-ix.cmake

@@ -393,6 +393,8 @@ elseif (LLVM_NATIVE_ARCH MATCHES "wasm32")
   set(LLVM_NATIVE_ARCH WebAssembly)
 elseif (LLVM_NATIVE_ARCH MATCHES "wasm64")
   set(LLVM_NATIVE_ARCH WebAssembly)
+elseif (LLVM_NATIVE_ARCH MATCHES "aap")
+  set(LLVM_NATIVE_ARCH AAP)
 else ()
   message(FATAL_ERROR "Unknown architecture ${LLVM_NATIVE_ARCH}")
 endif ()

include/llvm/ADT/Triple.h

@@ -91,7 +91,8 @@ class Triple {
     wasm64,         // WebAssembly with 64-bit pointers
     renderscript32, // 32-bit RenderScript
     renderscript64, // 64-bit RenderScript
-    LastArchType = renderscript64
+    aap,            // AAP architecture
+    LastArchType = aap
   };
   enum SubArchType {
     NoSubArch,

include/llvm/CodeGen/AsmPrinter.h

@@ -169,7 +169,7 @@ class AsmPrinter : public MachineFunctionPass {
   const DataLayout &getDataLayout() const;
 
   /// Return the pointer size from the TargetMachine
-  unsigned getPointerSize() const;
+  virtual unsigned getPointerSize() const;
 
   /// Return information about subtarget.
   const MCSubtargetInfo &getSubtargetInfo() const;

include/llvm/CodeGen/MachineRegisterInfo.h

@@ -122,6 +122,10 @@ class MachineRegisterInfo {
   /// second element.
   std::vector<std::pair<unsigned, unsigned> > LiveIns;
 
+  /// Keep track of the physical registers that are live out of the function.
+  /// Live out values are return values in registers.
+  std::vector<unsigned> LiveOuts;
+
   MachineRegisterInfo(const MachineRegisterInfo&) = delete;
   void operator=(const MachineRegisterInfo&) = delete;
 public:
@@ -797,6 +801,12 @@ class MachineRegisterInfo {
     LiveIns.push_back(std::make_pair(Reg, vreg));
   }
 
+  /// addLiveOut - Add the specified register as a live-out.  Note that it
+  /// is an error to add the same register to the same set more than once.
+  void addLiveOut(unsigned Reg) {
+    LiveOuts.push_back(Reg);
+  }
+
   // Iteration support for the live-ins set.  It's kept in sorted order
   // by register number.
   typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator
@@ -807,6 +817,14 @@ class MachineRegisterInfo {
 
   bool isLiveIn(unsigned Reg) const;
 
+  // Iteration support for the live-outs set. Not necessarily in sorted order.
+  typedef std::vector<unsigned>::const_iterator liveout_iterator;
+  liveout_iterator liveout_begin() const { return LiveOuts.begin(); }
+  liveout_iterator liveout_end()   const { return LiveOuts.end(); }
+  bool             liveout_empty() const { return LiveOuts.empty(); }
+
+  bool isLiveOut(unsigned Reg) const;
+
   /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
   /// corresponding live-in physical register.
   unsigned getLiveInPhysReg(unsigned VReg) const;

include/llvm/Object/ELFObjectFile.h

@@ -861,6 +861,8 @@ StringRef ELFObjectFile<ELFT>::getFileFormatName() const {
       return "ELF32-wasm";
     case ELF::EM_AMDGPU:
       return "ELF32-amdgpu";
+    case ELF::EM_AAP:
+      return "ELF32-aap";
     default:
       return "ELF32-unknown";
     }

include/llvm/Support/ELF.h

@@ -317,6 +317,8 @@ enum {
   // such numbers for an official value for WebAssembly. As soon as one is
   // allocated, this enum will be updated to use it.
   EM_WEBASSEMBLY   = 0x4157, // WebAssembly architecture
+
+  EM_AAP           = 0x5343 // AAP
 };
 
 // Object file classes.
@@ -622,6 +624,11 @@ enum {
 #include "ELFRelocs/BPF.def"
 };
 
+// ELF Relocation type for AAP.
+enum {
+#include "ELFRelocs/AAP.def"
+};
+
 #undef ELF_RELOC
 
 // Section header.

include/llvm/Support/ELFRelocs/AAP.def

@@ -0,0 +1,23 @@
+
+#ifndef ELF_RELOC
+#error "ELF_RELOC must be defined"
+#endif
+
+ELF_RELOC(R_AAP_NONE,       0x00)
+ELF_RELOC(R_AAP_8,          0x01)
+ELF_RELOC(R_AAP_16,         0x02)
+ELF_RELOC(R_AAP_32,         0x03)
+ELF_RELOC(R_AAP_64,         0x04)
+ELF_RELOC(R_AAP_BR16,       0x05)
+ELF_RELOC(R_AAP_BR32,       0x06)
+ELF_RELOC(R_AAP_BRCC16,     0x07)
+ELF_RELOC(R_AAP_BRCC32,     0x08)
+ELF_RELOC(R_AAP_BAL16,      0x09)
+ELF_RELOC(R_AAP_BAL32,      0x0a)
+ELF_RELOC(R_AAP_ABS6,       0x0b)
+ELF_RELOC(R_AAP_ABS9,       0x0c)
+ELF_RELOC(R_AAP_ABS10,      0x0d)
+ELF_RELOC(R_AAP_ABS12,      0x0e)
+ELF_RELOC(R_AAP_ABS16,      0x0f)
+ELF_RELOC(R_AAP_OFF10,      0x10)
+ELF_RELOC(R_AAP_SHIFT6,     0x11)

include/llvm/module.modulemap

@@ -260,6 +260,7 @@ module LLVM_Utils {
     textual header "Support/AArch64TargetParser.def"
     textual header "Support/Dwarf.def"
     textual header "Support/MachO.def"
+    textual header "Support/ELFRelocs/AAP.def"
     textual header "Support/ELFRelocs/AArch64.def"
     textual header "Support/ELFRelocs/AMDGPU.def"
     textual header "Support/ELFRelocs/ARM.def"

lib/CodeGen/AsmPrinter/AsmPrinter.cpp

@@ -144,7 +144,12 @@ const DataLayout &AsmPrinter::getDataLayout() const {
 
 // Do not use the cached DataLayout because some client use it without a Module
 // (llmv-dsymutil, llvm-dwarfdump).
-unsigned AsmPrinter::getPointerSize() const { return TM.getPointerSize(); }
+// By default, use the pointer size defined by the target machine
+unsigned AsmPrinter::getPointerSize() const {
+  if (MAI)
+    return MAI->getPointerSize();
+  return TM.getPointerSize();
+}
 
 const MCSubtargetInfo &AsmPrinter::getSubtargetInfo() const {
   assert(MF && "getSubtargetInfo requires a valid MachineFunction!");

lib/CodeGen/MachineRegisterInfo.cpp

@@ -391,6 +391,13 @@ bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
   return false;
 }
 
+bool MachineRegisterInfo::isLiveOut(unsigned Reg) const {
+  for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I)
+    if (*I == Reg)
+      return true;
+  return false;
+}
+
 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
 /// corresponding live-in physical register.
 unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {

lib/CodeGen/TargetFrameLoweringImpl.cpp

@@ -91,6 +91,14 @@ void TargetFrameLowering::determineCalleeSaves(MachineFunction &MF,
     if (CallsUnwindInit || MRI.isPhysRegModified(Reg))
       SavedRegs.set(Reg);
   }
+
+  // Don't save any register which is live out of the function
+  for (unsigned i = 0; CSRegs[i]; ++i) {
+    unsigned Reg = CSRegs[i];
+    if (MRI.isLiveOut(Reg)) {
+      SavedRegs.reset(Reg);
+    }
+  }
 }
 
 unsigned TargetFrameLowering::getStackAlignmentSkew(

lib/Object/ELF.cpp

@@ -40,6 +40,13 @@ StringRef getELFRelocationTypeName(uint32_t Machine, uint32_t Type) {
       break;
     }
     break;
+  case ELF::EM_AAP:
+    switch (Type) {
+#include "llvm/Support/ELFRelocs/AAP.def"
+    default:
+      break;
+    }
+    break;
   case ELF::EM_AARCH64:
     switch (Type) {
 #include "llvm/Support/ELFRelocs/AArch64.def"

lib/ObjectYAML/ELFYAML.cpp

@@ -531,6 +531,9 @@ void ScalarEnumerationTraits<ELFYAML::ELF_REL>::enumeration(
     break;
   case ELF::EM_LANAI:
 #include "llvm/Support/ELFRelocs/Lanai.def"
+  break;
+  case ELF::EM_AAP:
+#include "llvm/Support/ELFRelocs/AAP.def"
     break;
   case ELF::EM_AMDGPU:
 #include "llvm/Support/ELFRelocs/AMDGPU.def"

lib/Support/Triple.cpp

@@ -66,6 +66,7 @@ const char *Triple::getArchTypeName(ArchType Kind) {
   case wasm64:         return "wasm64";
   case renderscript32: return "renderscript32";
   case renderscript64: return "renderscript64";
+  case aap:            return "aap";
   }
 
   llvm_unreachable("Invalid ArchType!");
@@ -134,6 +135,7 @@ const char *Triple::getArchTypePrefix(ArchType Kind) {
   case shave:       return "shave";
   case wasm32:
   case wasm64:      return "wasm";
+  case aap:         return "aap";
   }
 }
 
@@ -286,6 +288,7 @@ Triple::ArchType Triple::getArchTypeForLLVMName(StringRef Name) {
     .Case("wasm64", wasm64)
     .Case("renderscript32", renderscript32)
     .Case("renderscript64", renderscript64)
+    .Case("aap", aap)
     .Default(UnknownArch);
 }
 
@@ -397,6 +400,7 @@ static Triple::ArchType parseArch(StringRef ArchName) {
     .Case("wasm64", Triple::wasm64)
     .Case("renderscript32", Triple::renderscript32)
     .Case("renderscript64", Triple::renderscript64)
+    .Case("aap", Triple::aap)
     .Default(Triple::UnknownArch);
 
   // Some architectures require special parsing logic just to compute the
@@ -579,6 +583,7 @@ static Triple::ObjectFormatType getDefaultFormat(const Triple &T) {
       return Triple::COFF;
     return Triple::ELF;
 
+  case Triple::aap:
   case Triple::aarch64_be:
   case Triple::amdgcn:
   case Triple::amdil:
@@ -1121,6 +1126,7 @@ static unsigned getArchPointerBitWidth(llvm::Triple::ArchType Arch) {
 
   case llvm::Triple::avr:
   case llvm::Triple::msp430:
+  case llvm::Triple::aap:
     return 16;
 
   case llvm::Triple::arm:
@@ -1196,6 +1202,7 @@ Triple Triple::get32BitArchVariant() const {
   case Triple::msp430:
   case Triple::systemz:
   case Triple::ppc64le:
+  case Triple::aap:
     T.setArch(UnknownArch);
     break;
 
@@ -1258,6 +1265,7 @@ Triple Triple::get64BitArchVariant() const {
   case Triple::xcore:
   case Triple::sparcel:
   case Triple::shave:
+  case Triple::aap:
     T.setArch(UnknownArch);
     break;
 
@@ -1334,6 +1342,7 @@ Triple Triple::getBigEndianArchVariant() const {
   case Triple::xcore:
   case Triple::renderscript32:
   case Triple::renderscript64:
+  case Triple::aap:
 
   // ARM is intentionally unsupported here, changing the architecture would
   // drop any arch suffixes.
@@ -1420,6 +1429,7 @@ bool Triple::isLittleEndian() const {
   case Triple::xcore:
   case Triple::renderscript32:
   case Triple::renderscript64:
+  case Triple::aap:
     return true;
   default:
     return false;

lib/Target/AAP/AAP.h

@@ -0,0 +1,67 @@
+//===-- AAP.h - Top-level interface for AAP representation ------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the entry points for global functions defined in the LLVM
+// AAP back-end.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef TARGET_AAP_H
+#define TARGET_AAP_H
+
+#include "MCTargetDesc/AAPMCTargetDesc.h"
+#include "llvm/Support/MathExtras.h"
+#include "llvm/Target/TargetMachine.h"
+
+namespace AAPCC {
+// AAP specific condition codes
+enum CondCode {
+  COND_EQ = 0,
+  COND_NE = 1,
+  COND_LTS = 2,
+  COND_LES = 3,
+  COND_LTU = 4,
+  COND_LEU = 5,
+  COND_INVALID = -1
+};
+} // end namespace AAP
+
+namespace llvm {
+extern Target TheAAPTarget;
+class AAPTargetMachine;
+
+FunctionPass *createAAPISelDag(AAPTargetMachine &TM,
+                               CodeGenOpt::Level OptLevel);
+
+FunctionPass *createAAPShortInstrPeepholePass(AAPTargetMachine &TM);
+
+namespace AAP {
+// Various helper methods to define operand ranges used throughout the backend
+static bool inline isImm3(int64_t I) { return isUInt<3>(I); }
+static bool inline isImm6(int64_t I) { return isUInt<6>(I); }
+static bool inline isImm9(int64_t I) { return isUInt<9>(I); }
+static bool inline isImm10(int64_t I) { return isUInt<10>(I); }
+static bool inline isImm12(int64_t I) { return isUInt<12>(I); }
+
+static bool inline isOff3(int64_t I) { return isInt<3>(I); }
+static bool inline isOff6(int64_t I) { return isInt<6>(I); }
+static bool inline isOff9(int64_t I) { return isInt<9>(I); }
+static bool inline isOff10(int64_t I) { return isInt<10>(I); }
+
+static bool inline isField16(int64_t I) {
+  return isInt<16>(I) || isUInt<16>(I);
+}
+
+static bool inline isShiftImm3(int64_t I) { return (I >= 1) && (I <= 8); }
+static bool inline isShiftImm6(int64_t I) { return (I >= 1) && (I <= 64); }
+
+} // end of namespace AAP
+} // end namespace llvm
+
+#endif