The PULP RI5CY core modified for Verilator modeling and as a GDB server.
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Ian Bolton
Ian Bolton Fix up dp_ram.sv to work also for misaligned accesses.
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.gitignore Tidy up .gitignore Jun 7, 2017
LICENSE.GPL3 Clarify licensing. Jun 7, 2017
LICENSE.solderpad Clarify licensing. Jun 7, 2017
README.md Note need for very new Verilator Jun 7, 2017
alu.sv Implemented beqimm and bneimm Jul 6, 2016
alu_div.sv Bit of beautify Apr 12, 2016
compressed_decoder.sv beautify banners Jun 13, 2016
controller.sv Built a Verilator model. Jun 7, 2017
cs_registers.sv beautify banners Jun 13, 2016
debug_unit.sv Built a Verilator model. Jun 7, 2017
decoder.sv Fix a typo. Jul 12, 2017
ex_stage.sv moved to package based riscv core Jun 3, 2016
exc_controller.sv moved to package based riscv core Jun 3, 2016
hwloop_controller.sv moved to package based riscv core Jun 3, 2016
hwloop_regs.sv Built a Verilator model. Jun 7, 2017
id_stage.sv Built a Verilator model. Jun 7, 2017
if_stage.sv Built a Verilator model. Jun 7, 2017
load_store_unit.sv Built a Verilator model. Jun 7, 2017
mult.sv Built a Verilator model. Jun 7, 2017
prefetch_L0_buffer.sv Built a Verilator model. Jun 7, 2017
prefetch_buffer.sv Built a Verilator model. Jun 7, 2017
register_file.sv Clean headers Dec 14, 2015
register_file_ff.sv Built a Verilator model. Jun 7, 2017
riscv_core.sv fixed issue with include file Jun 23, 2016
riscv_simchecker.sv fixed issue with include file Jun 23, 2016
riscv_tracer.sv moved to package based riscv core Jun 3, 2016
src_files.yml Revert "fixes for new ipstools" Jun 24, 2016

README.md

RI5CY: RISC-V Core

This is a fork of the PULP Platform RI5CY core for Verilator and GDB server development.

RI5CY is a small 4-stage RISC-V core. It starte its life as a fork of the OR10N cpu core that is based on the OpenRISC ISA.

RI5CY fully implements the RV32I instruction set, the multiply instruction from RV32M and many custom instruction set extensions that improve its performance for signal processing applications.

The core was developed as part of the PULP platform for energy-efficient computing and is currently used as the processing core for PULP and PULPino.

Documentation

A datasheet that explains the most important features of the core can be found in docs/datasheet/.

It is written using LaTeX and can be generated as follows

make all

Verilator model

The Verilator model can be built at the top level using

make all

The RI5CY code uses some quite advanced System Verilog, so you will need a very up to date Verilator. We succeeded with development version 3.905, but found version 3.900 crashed.

Licensing

The upstream design is all licensed under the SolderPad License v 0.51, see the file LICENSE.solderpad.

The modifications by Embecosm to support Verilator modeling and implement a GDB server are licensed under the GNU General Public License 3.0, see the file LICENSE.GPL3.

The headers for source files should indicate which license applies. If no license is specified, then the solderPad license should be assumed.