diff --git a/CHANGES b/CHANGES index 3ec1341b9e..f6572c018f 100644 --- a/CHANGES +++ b/CHANGES @@ -27,6 +27,7 @@ -------------------------- - BIOS: commands have been renamed/reorganized. - LiteDRAM: rdcmdphase/wrcmdphase no longer exposed. + - CSR: change default csr_data_width from 8 to 32. [> 2020.08, planned for July 2020 --------------------------------- diff --git a/litex/soc/doc/csr.py b/litex/soc/doc/csr.py index 74193dcc81..417109f127 100644 --- a/litex/soc/doc/csr.py +++ b/litex/soc/doc/csr.py @@ -63,7 +63,7 @@ def __init__(self, name, address, f.description = self.trim(f.description) class DocumentedCSRRegion: - def __init__(self, name, region, module=None, submodules=[], csr_data_width=8): + def __init__(self, name, region, module=None, submodules=[], csr_data_width=32): self.name = name self.origin = region.origin self.busword = region.busword diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 344d84f406..95d268720f 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -80,7 +80,7 @@ def __init__(self, platform, clk_freq, integrated_main_ram_size = 0, integrated_main_ram_init = [], # CSR parameters - csr_data_width = 8, + csr_data_width = 32, csr_address_width = 14, csr_paging = 0x800, csr_ordering = "big", @@ -282,7 +282,7 @@ def soc_core_args(parser): help="size/enable the integrated main RAM") # CSR parameters parser.add_argument("--csr-data-width", default=None, type=auto_int, - help="CSR bus data-width (8 or 32, default=8)") + help="CSR bus data-width (8 or 32, default=32)") parser.add_argument("--csr-address-width", default=14, type=auto_int, help="CSR bus address-width") parser.add_argument("--csr-paging", default=0x800, type=auto_int,