Digilent's Nexys Video SoC based on LiteX
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doc
firmware
gateware
test
Makefile
README
load.py
nexys_base.py
nexys_ddr3.py
nexys_etherbone.py
nexys_video.py

README

         _  __                    ____     _____
        / |/ /____ ____ _________/ __/__  / ___/
       /    / -_) \ / // (_-<___/\ \/ _ \/ /__
      /_/|_/\__/_\_\\_, /___/  /___/\___/\___/
                   /___/

         Copyright 2015-2017 / EnjoyDigital

      Digilent's Nexys Video SoC based on LiteX

[> Getting started
------------------
1. Install Python3 and your vendor's software

2. Obtain LiteX and install it:
  git clone https://github.com/enjoy-digital/litex --recursive
  cd litex
  python3 setup.py develop
  cd ..

3. Obtain LiteDRAM and install it:
  git clone https://github.com/enjoy-digital/litedram
  cd litedram
  python3 setup.py develop
  cd ..

4. Obtain LiteEth and install it:
  git clone https://github.com/enjoy-digital/liteeth
  cd liteeth
  python3 setup.py develop
  cd ..

5. Obtain LiteScope and install it:
  git clone https://github.com/enjoy-digital/litescope
  cd litescope
  python3 setup.py develop
  cd ..

6. Build the gateware and software:
  make minisoc (or ddr3, etherbone, video)
  make load

[> Status
---------
BaseSoC / MiniSoC validated with 16 bits DDR3 @ 800Mbps/pin.
EtherboneSoC validated.
VideoSoC validated with hdmi in/hdmi out @ 720p60.

[> Contact
----------
E-mail: florent@enjoy-digital.fr