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executable file 206 lines (165 sloc) 7.32 KB
#!/usr/bin/env python3
import argparse
import os
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.boards.platforms import nexys_video
from litex.soc.integration.soc_core import mem_decoder
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litex.soc.cores.uart import *
from litedram.modules import MT41K256M16
from litedram.phy import a7ddrphy
from litedram.core import ControllerSettings
from liteeth.phy.s7rgmii import LiteEthPHYRGMII
from liteeth.core.mac import LiteEthMAC
from litex.soc.cores import dna, xadc
from gateware import oled
def csr_map_update(csr_map, csr_peripherals):
csr_map.update(dict((n, v)
for v, n in enumerate(csr_peripherals, start=max(csr_map.values()) + 1)))
def period_ns(freq):
return 1e9/freq
class CRG(Module):
def __init__(self, platform):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
self.clock_domains.cd_clk200 = ClockDomain()
self.clock_domains.cd_clk100 = ClockDomain()
clk100 = platform.request("clk100")
rst = ~platform.request("cpu_reset")
pll_locked = Signal()
pll_fb = Signal()
self.pll_sys = Signal()
pll_sys4x = Signal()
pll_sys4x_dqs = Signal()
pll_clk200 = Signal()
self.specials += [
Instance("PLLE2_BASE",
p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
# VCO @ 1600 MHz
p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=10.0,
p_CLKFBOUT_MULT=16, p_DIVCLK_DIVIDE=1,
i_CLKIN1=clk100, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
# 100 MHz
p_CLKOUT0_DIVIDE=16, p_CLKOUT0_PHASE=0.0,
o_CLKOUT0=self.pll_sys,
# 400 MHz
p_CLKOUT1_DIVIDE=4, p_CLKOUT1_PHASE=0.0,
o_CLKOUT1=pll_sys4x,
# 400 MHz dqs
p_CLKOUT2_DIVIDE=4, p_CLKOUT2_PHASE=90.0,
o_CLKOUT2=pll_sys4x_dqs,
# 200 MHz
p_CLKOUT3_DIVIDE=8, p_CLKOUT3_PHASE=0.0,
o_CLKOUT3=pll_clk200
),
Instance("BUFG", i_I=self.pll_sys, o_O=self.cd_sys.clk),
Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk),
Instance("BUFG", i_I=pll_sys4x_dqs, o_O=self.cd_sys4x_dqs.clk),
Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),
Instance("BUFG", i_I=clk100, o_O=self.cd_clk100.clk),
AsyncResetSynchronizer(self.cd_sys, ~pll_locked | rst),
AsyncResetSynchronizer(self.cd_clk200, ~pll_locked | rst),
AsyncResetSynchronizer(self.cd_clk100, ~pll_locked | rst),
]
reset_counter = Signal(4, reset=15)
ic_reset = Signal(reset=1)
self.sync.clk200 += \
If(reset_counter != 0,
reset_counter.eq(reset_counter - 1)
).Else(
ic_reset.eq(0)
)
self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset)
class BaseSoC(SoCSDRAM):
csr_peripherals = [
"ddrphy",
"dna",
"xadc",
"oled",
]
csr_map_update(SoCSDRAM.csr_map, csr_peripherals)
def __init__(self, platform, **kwargs):
clk_freq = int(100e6)
SoCSDRAM.__init__(self, platform, clk_freq,
cpu_type="vexriscv",
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
with_uart=False,
reserve_nmi_interrupt=False,
**kwargs)
self.submodules.crg = CRG(platform)
self.submodules.dna = dna.DNA()
self.submodules.xadc = xadc.XADC()
self.submodules.oled = oled.OLED(platform.request("oled"))
uart_interfaces = [RS232PHYInterface() for i in range(2)]
self.submodules.uart = UART(uart_interfaces[0])
self.submodules.bridge = WishboneStreamingBridge(uart_interfaces[1], self.clk_freq)
self.add_wb_master(self.bridge.wishbone)
self.submodules.uart_phy = RS232PHY(platform.request("serial"), self.clk_freq, 115200)
self.submodules.uart_multiplexer = RS232PHYMultiplexer(uart_interfaces, self.uart_phy)
self.comb += self.uart_multiplexer.sel.eq(platform.request("user_sw", 0))
self.crg.cd_sys.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk, period_ns(100e6))
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
sdram_module = MT41K256M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(with_bandwidth=True,
cmd_buffer_depth=8,
with_refresh=True))
class MiniSoC(BaseSoC):
csr_peripherals = [
"ethphy",
"ethmac",
]
csr_map_update(BaseSoC.csr_map, csr_peripherals)
interrupt_map = {
"ethmac": 3,
}
interrupt_map.update(BaseSoC.interrupt_map)
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
}
mem_map.update(BaseSoC.mem_map)
def __init__(self, *args, **kwargs):
BaseSoC.__init__(self, *args, **kwargs)
self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"),
self.platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, period_ns(125e6))
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, period_ns(125e6))
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
def configure_ip(self, ip_type, ip):
for i, e in enumerate(ip):
s = ip_type + str(i + 1)
s = s.upper()
self.add_constant(s, e)
def main():
parser = argparse.ArgumentParser(description="Nexys LiteX SoC")
builder_args(parser)
soc_sdram_args(parser)
parser.add_argument("--with-ethernet", action="store_true",
help="enable Ethernet support")
parser.add_argument("--nocompile-gateware", action="store_true")
args = parser.parse_args()
platform = nexys_video.Platform()
cls = MiniSoC if args.with_ethernet else BaseSoC
soc = cls(platform, **soc_sdram_argdict(args))
builder = Builder(soc, output_dir="build",
compile_gateware=not args.nocompile_gateware,
csr_csv="test/csr.csv")
vns = builder.build()
if __name__ == "__main__":
main()