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hwdocs: Convert all remaining toplevel ranges to new directives.

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1 parent 0a9eea1 commit 07af5067dfd9dcda2737b5c6bc5e94dee624da58 @koriakin koriakin committed Feb 5, 2014
Showing with 453 additions and 322 deletions.
  1. +3 −1 hwdocs/bus/hwsq.rst
  2. +1 −1 hwdocs/bus/index.rst
  3. +2 −2 hwdocs/bus/pbus.rst
  4. +4 −0 hwdocs/bus/pci.rst
  5. +28 −14 hwdocs/bus/pfuse.rst
  6. +4 −4 hwdocs/bus/pmc.rst
  7. +7 −7 hwdocs/bus/{pibus.rst → pring.rst}
  8. +3 −3 hwdocs/bus/punits.rst
  9. +3 −3 hwdocs/display/nv50/pcodec.rst
  10. +7 −4 hwdocs/display/nv50/pdisplay.rst
  11. +3 −3 hwdocs/display/nv50/pkfuse.rst
  12. +4 −0 hwdocs/display/nv50/punk1c3.rst
  13. +5 −1 hwdocs/envy.py
  14. +1 −1 hwdocs/fifo/index.rst
  15. +0 −1 hwdocs/fifo/nv04-pfifo.rst
  16. +21 −14 hwdocs/fifo/nv50-pfifo.rst
  17. +17 −14 hwdocs/fifo/nvc0-pfifo.rst
  18. +30 −0 hwdocs/fifo/nvc0-pspoon.rst
  19. +0 −30 hwdocs/fifo/nvc0-psubfifo.rst
  20. +4 −0 hwdocs/fifo/pcopy.rst
  21. +3 −3 hwdocs/graph/fermi/pgraph.rst
  22. +3 −3 hwdocs/graph/tesla/pgraph.rst
  23. +7 −4 hwdocs/io/pnvio.rst
  24. +6 −3 hwdocs/memory/nv50-host-mem.rst
  25. +3 −3 hwdocs/memory/nv50-pfb.rst
  26. +4 −1 hwdocs/memory/nvc0-host-mem.rst
  27. +3 −3 hwdocs/memory/nvc0-p2p.rst
  28. +7 −3 hwdocs/memory/pbfb.rst
  29. +10 −5 hwdocs/memory/peephole.rst
  30. +3 −3 hwdocs/memory/pffb.rst
  31. +13 −3 hwdocs/memory/pmfb.rst
  32. +3 −3 hwdocs/memory/pxbar.rst
  33. +169 −151 hwdocs/mmio.rst
  34. +3 −5 hwdocs/pcounter/intro.rst
  35. +11 −5 hwdocs/pm/nv50-clock.rst
  36. +11 −5 hwdocs/pm/nva3-clock.rst
  37. +7 −4 hwdocs/pm/nvc0-clock.rst
  38. +4 −0 hwdocs/pm/pdaemon/io.rst
  39. +3 −3 hwdocs/pm/ptherm.rst
  40. +4 −0 hwdocs/vdec/pvcomp.rst
  41. +4 −0 hwdocs/vdec/pvenc.rst
  42. +3 −3 hwdocs/vdec/vp2/pbsp.rst
  43. +3 −3 hwdocs/vdec/vp2/pcrypt2.rst
  44. +3 −3 hwdocs/vdec/vp2/pvp2.rst
  45. +4 −0 hwdocs/vdec/vp3/pcrypt3.rst
  46. +4 −0 hwdocs/vdec/vp3/pppp.rst
  47. +4 −0 hwdocs/vdec/vp3/pvdec.rst
  48. +4 −0 hwdocs/vdec/vp3/pvld.rst
View
@@ -55,8 +55,10 @@ Address Variants Name
.. todo:: cleanup, crossref
+.. space:: 8 phwsq-large-code 0x1000 extended HWSQ code space
+
+ .. todo:: writ me
-.. _pbus-hwsq-new-code-mmio:
Code space
==========
View
@@ -14,6 +14,6 @@ Contents:
prma
nv01-prm
pfuse
- pibus
+ pring
punits
pci
View
@@ -117,8 +117,8 @@ MMIO 0x001100: INTR [NV03-]
- bit 0: BUS_ERROR - ??? [NV03:NV50]
- bit 1: MMIO_DISABLED_ENG - MMIO access from host failed due to accessing
an area disabled via PMC.ENABLE [NVC0-] [XXX: document]
- - bit 2: MMIO_IBUS_ERR - :ref:`MMIO access from host failed due to some error in
- IBUS <pbus-intr-mmio-ibus-err>` [NVC0-]
+ - bit 2: MMIO_RING_ERR - :ref:`MMIO access from host failed due to some error in
+ PRING <pbus-intr-mmio-ring-err>` [NVC0-]
- bit 3: MMIO_FAULT - MMIO access from host failed due to other reasons
[NV41-] [XXX: document]
- bit 4: GPIO_0_RISE - :ref:`GPIO #0 went from 0 to 1 [NV10:NV31] <nv10-gpio-intr>`
View
@@ -26,6 +26,10 @@ MMIO registers
.. todo:: write me
+.. space:: 8 pbridge-pci 0x1000 access to PCI config registers of the GPU's upstream PCIE bridge
+
+ .. todo:: write me
+
.. _ppci-intr:
View
@@ -6,6 +6,7 @@ PFUSE: Configuration fuses
.. contents::
+
Introduction
============
@@ -14,26 +15,39 @@ software later on. The name comes from the fact that once the Configuration
has been set, it is possible to avoid further writes by blowing the power supply
or the data lines of the the write circuitry.
-.. _pfuse-mmio:
+.. todo:: more info
+
MMIO registers
==============
-PFUSE's MMIO range is 0x021000-0x022000.
+.. space:: 8 pfuse 0x1000 efuses storing chipset options
+ 0x144 TPC_DISABLE_MASK pfuse-tpc-disable-mask NV50:NVC0
+ 0x148 PART_DISABLE_MASK pfuse-part-disable-mask NV50:NVC0
+ 0x1a0 TEMP_CAL_SLOPE_MUL_OFFSET pfuse-temp-cal-slope-mul-offset
+ 0x1a4 TEMP_CAL_OFFSET_MUL_OFFSET pfuse-temp-cal-offset-mul-offset
+ 0x1a8 TEMP_CAL_OK pfuse-temp-cal-ok
+
+ .. todo:: fill me
+
+.. reg:: 32 pfuse-tpc-disable-mask TPC disable mask
+
+ The TPC disable mask.
+
+.. reg:: 32 pfuse-part-disable-mask PART disable mask
+
+ The PART disable mask.
+
+.. reg:: 32 pfuse-temp-cal-slope-mul-offset slope calibration
-MMIO 0x21144: TPC_DISABLE_MASK
- The TPC disable mask.
+ An offset added to the slope calibration value of the internal temperature
+ sensor (int8_t). :ref:`See PTHERM for more information <ptherm>`
-MMIO 0x21148: PART_DISABLE_MASK
- The PART disable mask.
+.. reg:: 32 pfuse-temp-cal-offset-mul-offset slope calibration
-MMIO 0x211a0: TEMP_CAL_SLOPE_MUL_OFFSET
- An offset added to the slope calibration value of the internal temperature
- sensor (int8_t). :ref:`See PTHERM for more information <ptherm>`
+ An offset added to the offset calibration value of the internal temperature
+ sensor (int16_t). :ref:`See PTHERM for more information <ptherm>`
-MMIO 0x211a4: TEMP_CAL_OFFSET_MUL_OFFSET
- An offset added to the offset calibration value of the internal temperature
- sensor (int16_t). :ref:`See PTHERM for more information <ptherm>`
+.. reg:: 32 pfuse-temp-cal-ok internal thermal sensor enable
-MMIO 0x211a8: TEMP_CAL_OK
- Should the internal temperature sensor be used? Set to 1 if so, 0 otherwise.
+ Should the internal temperature sensor be used? Set to 1 if so, 0 otherwise.
View
@@ -246,7 +246,7 @@ On NVC0+, the bits are:
- 2: :ref:`PXBAR <pxbar>`
- 3: :ref:`PMFB <pmfb>`
- 4: :ref:`PMEDIA <pmedia>`
-- 5: :ref:`PIBUS <pibus>`
+- 5: :ref:`PRING <pring>`
- 6: :ref:`PCOPY[0] <pcopy>`
- 7: :ref:`PCOPY[1] <pcopy>`
- 8: :ref:`PFIFO <nvc0-pfifo>`
@@ -269,8 +269,8 @@ NVC0 also introduced SUBFIFO_ENABLE register:
.. reg:: 32 pmc-spoon-enable PSPOON enables
- Enables PFIFO's PSUBFIFOs. Bit i corresponds to PSUBFIFO[i]. See
- :ref:`NVC0+ PFIFO <nvc0-psubfifo>` for details.
+ Enables PFIFO's PSPOONs. Bit i corresponds to PSPOON[i]. See
+ :ref:`NVC0+ PFIFO <nvc0-pspoon>` for details.
There are also two other registers looking like ENABLE, but with seemingly
no effect and currently unknown purpose:
@@ -491,7 +491,7 @@ For NVC0+:
- 27: :ref:`PFFB <pffb-intr>`
- 28: :ref:`PBUS <pbus-intr>` - has separate NRHOST line
- 29: :ref:`PPCI <ppci-intr>`
-- 30: :ref:`PIBUS <pibus-intr>`
+- 30: :ref:`PRING <pring-intr>`
- 31: software
.. todo:: unknowns
@@ -1,7 +1,7 @@
-.. _pibus:
+.. _pring:
========================
-PIBUS: Card internal bus
+PRING: Card internal bus
========================
.. contents::
@@ -15,23 +15,23 @@ Introduction
.. todo:: write me
-.. _pibus-mmio:
-
MMIO registers
==============
-.. todo:: write me
+.. space:: 8 pring 0x10000 card internal bus
+
+ .. todo:: write me
-.. _pibus-intr:
+.. _pring-intr:
Interrupts
==========
.. todo:: write me
-.. _pbus-intr-mmio-ibus-err:
+.. _pbus-intr-mmio-ring-err:
PBUS interrupts
===============
View
@@ -15,9 +15,9 @@ Introduction
.. todo:: write me
-.. _punits-mmio:
-
MMIO registers
==============
-.. todo:: write me
+.. space:: 8 punits 0x400 control over enabled card units
+
+ .. todo:: write me
@@ -15,9 +15,9 @@ Introduction
.. todo:: write me
-.. _pcodec-mmio:
-
MMIO registers
==============
-.. todo:: write me
+.. space:: 8 pcodec 0x1000 HDA codec for HDMI audio
+
+ .. todo:: write me
@@ -15,13 +15,16 @@ Introduction
.. todo:: write me
-.. _pdisplay-mmio:
-.. _display-user-mmio:
-
MMIO registers
==============
-.. todo:: write me
+.. space:: 8 nv50-pdisplay 0xb0000 unified display engine
+
+ .. todo:: write me
+
+.. space:: 8 nvd9-pdisplay 0xb0000 unified display engine
+
+ .. todo:: write me
.. _pdisplay-intr:
@@ -15,9 +15,9 @@ Introduction
.. todo:: write me
-.. _pkfuse-mmio:
-
MMIO registers
==============
-.. todo:: write me
+.. space:: 8 pkfuse 0x1000 efuses storing secret key stuff
+
+ .. todo:: write me
@@ -83,6 +83,10 @@ IO registers:
IO registers
============
+.. space:: 8 punk1c3 0x1000 ???
+
+ .. todo:: write me
+
The IO registers:
=========== ===== ============
View
@@ -132,9 +132,13 @@ def make_obj(self):
for sub in subs:
pos, name, ref, *rest = sub.split()
if rest:
- variants, = rest
+ variants, *rest = rest
else:
variants = None
+ if rest:
+ tags, = rest
+ else:
+ tags = None
obj.presubs.append((pos, name, ref, variants))
self.locs = []
return obj
View
@@ -15,5 +15,5 @@ Contents:
nv04-pfifo
nv50-pfifo
nvc0-pfifo
- nvc0-psubfifo
+ nvc0-pspoon
pcopy
@@ -42,7 +42,6 @@ FIFO submission area
.. todo:: document me
-
.. space:: 8 nv40-dma-user 0x1000 PFIFO DMA submission area
.. todo:: document me
View
@@ -6,30 +6,23 @@ NV50:NVC0 PFIFO engine
.. contents::
-.. todo:: write me
-
-.. note::
-
- This file deals only with NV50:NVC0 PFIFO. For other GPUs, read:
-
- * NV01:NV04 - :ref:`nv01-pfifo`
- * NV04:NV50 - :ref:`nv04-pfifo`
- * NVC0+ - :ref:`nvc0-pfifo`
-
Introduction
============
.. todo:: write me
-.. _nv50-pfifo-mmio:
-.. _nv50-pfifo-mmio-cache:
-
MMIO registers
==============
-.. todo:: write me
+.. space:: 8 nv50-pfifo 0x2000 DMA FIFO submission to engines
+
+ .. todo:: write me
+
+.. space:: 8 nv50-pfifo-cache 0x1000 PFIFO cache data
+
+ .. todo:: write me
.. _nv50-pfifo-intr:
@@ -55,3 +48,17 @@ Channel switching
=================
.. todo:: write me
+
+
+FIFO submission area
+====================
+
+.. todo:: write me
+
+.. space:: 8 nv50-pio-user 0x2000 PFIFO MMIO submission area
+
+ .. todo:: document me
+
+.. space:: 8 nv50-dma-user 0x2000 PFIFO DMA submission area
+
+ .. todo:: document me
View
@@ -6,30 +6,33 @@ NVC0+ PFIFO engine
.. contents::
-.. todo:: write me
-
-.. note::
-
- This file deals only with NVC0+ PFIFO. For other GPUs, read:
-
- * NV01:NV04 - :ref:`nv01-pfifo`
- * NV04:NV50 - :ref:`nv04-pfifo`
- * NV50:NVC0 - :ref:`nv50-pfifo`
Introduction
============
.. todo:: write me
-.. _nvc0-pfifo-mmio:
-.. _nvc0-pfifo-mmio-bypass:
-.. _nvc0-pfifo-mmio-chan:
-
MMIO registers
==============
-.. todo:: write me
+.. space:: 8 nvc0-pfifo 0x2000 DMA FIFO submission to engines
+
+ .. todo:: write me
+
+.. space:: 8 nvc0-pfifo-pio 0x1000 PFIFO PIO submission
+
+ .. todo:: write me
+
+.. space:: 8 nvc0-pfifo-unk1c0000 0x1000 PFIFO ???
+
+ .. todo:: write me
+
+.. space:: 8 nvc0-pfifo-chan 0x10000 PFIFO channel table
+
+ Related to PFIFO and playlist?
+
+ .. todo:: write me
.. _nvc0-pfifo-intr:
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