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hwdocs: Misc FIFO-related fixups.

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1 parent d043611 commit 53d63c05bb14a24531f7f4ca4f543c8127932259 @koriakin koriakin committed Oct 5, 2013
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@@ -217,16 +217,16 @@ On NV50:NVC0, the bits are:
- 17: :ref:`PVP2 <pvp2>` [NV84:NV98 NVA0:NVAA]
- 17: :ref:`PVDEC <pvdec>` [NV98:NVA0 NVAA-]
- 20: :ref:`PFB <nv50-pfb>`
-- 21: :ref:`PGRAPH CHSW <nv50-pfifo>` [NV84-]
-- 22: :ref:`PMPEG CHSW <nv50-pfifo>` [NV84-]
-- 23: :ref:`PCOPY CHSW <nv50-pfifo>` [NVA3-]
-- 24: :ref:`PVP2 CHSW <nv50-pfifo>` [NV84:NV98 NVA0:NVAA]
-- 24: :ref:`PVDEC CHSW <nv50-pfifo>` [NV98:NVA0 NVAA-]
-- 25: :ref:`PCRYPT2 CHSW <nv50-pfifo>` [NV84:NV98 NVA0:NVAA]
-- 25: :ref:`PCRYPT3 CHSW <nv50-pfifo>` [NV98:NVA0 NVAA:NVA3]
-- 25: :ref:`PVCOMP CHSW <nv50-pfifo>` [NVAF]
-- 26: :ref:`PBSP CHSW <nv50-pfifo>` [NV84:NV98 NVA0:NVAA]
-- 26: :ref:`PVLD CHSW <nv50-pfifo>` [NV98:NVA0 NVAA-]
+- 21: :ref:`PGRAPH CHSW <nv50-pfifo-chsw>` [NV84-]
+- 22: :ref:`PMPEG CHSW <nv50-pfifo-chsw>` [NV84-]
+- 23: :ref:`PCOPY CHSW <nv50-pfifo-chsw>` [NVA3-]
+- 24: :ref:`PVP2 CHSW <nv50-pfifo-chsw>` [NV84:NV98 NVA0:NVAA]
+- 24: :ref:`PVDEC CHSW <nv50-pfifo-chsw>` [NV98:NVA0 NVAA-]
+- 25: :ref:`PCRYPT2 CHSW <nv50-pfifo-chsw>` [NV84:NV98 NVA0:NVAA]
+- 25: :ref:`PCRYPT3 CHSW <nv50-pfifo-chsw>` [NV98:NVA0 NVAA:NVA3]
+- 25: :ref:`PVCOMP CHSW <nv50-pfifo-chsw>` [NVAF]
+- 26: :ref:`PBSP CHSW <nv50-pfifo-chsw>` [NV84:NV98 NVA0:NVAA]
+- 26: :ref:`PVLD CHSW <nv50-pfifo-chsw>` [NV98:NVA0 NVAA-]
- 27: ??? [NV84-]
- 28: ??? [NV84-]
- 30: :ref:`PDISPLAY <pdisplay>`
@@ -264,7 +264,7 @@ NVC0 also introduced SUBFIFO_ENABLE register:
MMIO 0x000204: SUBFIFO_ENABLE
Enables PFIFO's PSUBFIFOs. Bit i corresponds to PSUBFIFO[i]. See
- :ref:`NVC0+ PFIFO <nvc0-pfifo>` for details.
+ :ref:`NVC0+ PFIFO <nvc0-psubfifo>` for details.
There are also two other registers looking like ENABLE, but with seemingly
no effect and currently unknown purpose:
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@@ -1,4 +1,4 @@
-.. _dma-pusher:
+.. _fifo-dma-pusher:
===============================
DMA submission to FIFOs on NV04
@@ -108,6 +108,9 @@ troubleshooting:
.. todo:: determine what happens on NVC0 on all imaginable error conditions
+
+.. _fifo-user-mmio-dma:
+
Channel control area
====================
@@ -239,24 +242,26 @@ cause DMA_PUSHER error of type MEM_FAULT.
The IB entry is made of two 32-bit words in PFIFO endianness. Their format is:
Word 0:
- - bits 0-1: unused, should be 0
- - bits 2-31: ADDRESS_LOW, bits 2-31 of pushbuffer start address
+
+- bits 0-1: unused, should be 0
+- bits 2-31: ADDRESS_LOW, bits 2-31 of pushbuffer start address
Word 1:
- - bits 0-7: ADDRESS_HIGH, bits 32-39 of pushbuffer start address
- - bit 8: ???
- - bit 9: NOT_MAIN, "not main pushbuffer" flag
- - bits 10-30: SIZE, pushbuffer size in 32-bit words
- - bit 31: NO_PREFETCH (probably; use for pushbuffer data generated by the GPU)
+
+- bits 0-7: ADDRESS_HIGH, bits 32-39 of pushbuffer start address
+- bit 8: ???
+- bit 9: NOT_MAIN, "not main pushbuffer" flag
+- bits 10-30: SIZE, pushbuffer size in 32-bit words
+- bit 31: NO_PREFETCH (probably; use for pushbuffer data generated by the GPU)
.. todo:: figure out bit 8 some day
-When an IB entry is read, the pushbuffer is prepared for reading:
+When an IB entry is read, the pushbuffer is prepared for reading::
- - dma_get[2:39] = ADDRESS
- - dma_put = dma_get + SIZE * 4
- - nonmain = NOT_MAIN
- - if (!nonmain) dma_mget = dma_get
+ dma_get[2:39] = ADDRESS
+ dma_put = dma_get + SIZE * 4
+ nonmain = NOT_MAIN
+ if (!nonmain) dma_mget = dma_get
Subsequently, just like in NV04-style mode, words from dma_get are read until
it reaches dma_put. When that happens, processing can move on to the next IB
@@ -277,20 +282,21 @@ role in NV04-style mode.
The commands - pre-NVC0 format
+==============================
The command stream, as assembled by NV04-style or IB mode pushbuffer read, is
then split into individual commands. The command type is determined by its
first word. The word has to match one of the following forms:
================================ ====================================
-000CCCCCCCCCCC00SSSMMMMMMMMMMM00 increasing methods [NV04+]
-0000000000000001MMMMMMMMMMMMXX00 SLI conditional [NV40+, if enabled]
-00000000000000100000000000000000 return [NV11+, NV04-style only]
-0000000000000011SSSMMMMMMMMMMM00 long non-increasing methods [IB only]
-001JJJJJJJJJJJJJJJJJJJJJJJJJJJ00 old jump [NV04+, NV04-style only]
-010CCCCCCCCCCC00SSSMMMMMMMMMMM00 non-increasing methods [NV10+]
-JJJJJJJJJJJJJJJJJJJJJJJJJJJJJJ01 jump [NV11+, NV04-style only]
-JJJJJJJJJJJJJJJJJJJJJJJJJJJJJJ10 call [NV11+, NV04-style only]
+000CCCCCCCCCCC00SSSMMMMMMMMMMM00 increasing methods [NV04+]
+0000000000000001MMMMMMMMMMMMXX00 SLI conditional [NV40+, if enabled]
+00000000000000100000000000000000 return [NV11+, NV04-style only]
+0000000000000011SSSMMMMMMMMMMM00 long non-increasing methods [IB only]
+001JJJJJJJJJJJJJJJJJJJJJJJJJJJ00 old jump [NV04+, NV04-style only]
+010CCCCCCCCCCC00SSSMMMMMMMMMMM00 non-increasing methods [NV10+]
+JJJJJJJJJJJJJJJJJJJJJJJJJJJJJJ01 jump [NV11+, NV04-style only]
+JJJJJJJJJJJJJJJJJJJJJJJJJJJJJJ10 call [NV11+, NV04-style only]
================================ ====================================
.. todo:: do an exhaustive scan of commands
@@ -311,9 +317,9 @@ NV04 method submission commands
-------------------------------
================================ ====================================
-000CCCCCCCCCCC00SSSMMMMMMMMMMM00 increasing methods [NV04+]
-010CCCCCCCCCCC00SSSMMMMMMMMMMM00 non-increasing methods [NV10+]
-0000000000000011SSSMMMMMMMMMMM00 long non-increasing methods [IB only]
+000CCCCCCCCCCC00SSSMMMMMMMMMMM00 increasing methods [NV04+]
+010CCCCCCCCCCC00SSSMMMMMMMMMMM00 non-increasing methods [NV10+]
+0000000000000011SSSMMMMMMMMMMM00 long non-increasing methods [IB only]
================================ ====================================
These three commands are used to submit methods. the MM..M field selects the
@@ -345,10 +351,10 @@ NV04 control flow commands
--------------------------
================================ ====================================
-001JJJJJJJJJJJJJJJJJJJJJJJJJJJ00 old jump [NV04+]
-JJJJJJJJJJJJJJJJJJJJJJJJJJJJJJ01 jump [NV11+]
-JJJJJJJJJJJJJJJJJJJJJJJJJJJJJJ10 call [NV11+]
-00000000000000100000000000000000 return [NV11+]
+001JJJJJJJJJJJJJJJJJJJJJJJJJJJ00 old jump [NV04+]
+JJJJJJJJJJJJJJJJJJJJJJJJJJJJJJ01 jump [NV11+]
+JJJJJJJJJJJJJJJJJJJJJJJJJJJJJJ10 call [NV11+]
+00000000000000100000000000000000 return [NV11+]
================================ ====================================
For jumps and calls, J..JJ is bits 2-28 or 2-31 of the target address. The
@@ -373,7 +379,7 @@ NV04 SLI conditional command
----------------------------
================================ ====================================
-0000000000000001MMMMMMMMMMMMXX00 SLI conditional [NV40+]
+0000000000000001MMMMMMMMMMMMXX00 SLI conditional [NV40+]
================================ ====================================
NV40 introduced SLI functionality. One of the associated features is the SLI
@@ -399,7 +405,7 @@ The XX bits in the command are ignored.
NVC0 commands
--------------
+=============
NVC0 format follows the same idea, but uses all-new command encoding.
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@@ -23,6 +23,7 @@ Contents:
nv04-pfifo
nv50-pfifo
nvc0-pfifo
+ nvc0-psubfifo
.. rubric:: Other FIFO engines
View
@@ -28,54 +28,50 @@ possible to effectively hang the whole GPU by launching a long-running shader.
.. todo:: check if it still holds on NVC0
-The engines that PFIFO controls are:
-
-+-----+----------+-----------+---------------------------------------------------+
-|idx | name | cards | description |
-+=====+==========+===========+===================================================+
-|0/1f | | | Not really an engine, causes interrupt for each |
-| | SOFTWARE | all | command, can be used to execute driver functions |
-| | | | in sync with other commands. |
-+-----+----------+-----------+---------------------------------------------------+
-|1/0 | PGRAPH | all | Main engine of the card: 2d, 3d, compute. |
-| | | | [see :ref:`graph-intro`] |
-+-----+----------+-----------+---------------------------------------------------+
-|2/- | PMPEG | NV31:NV98 | The PFIFO interface to VPE MPEG2 decoding engine. |
-| | | | [see :ref:`pmpeg`] |
-+-----+----------+-----------+---------------------------------------------------+
-|3/- | PME | NV40:NV84 | VPE motion estimation engine [see :ref:`pme`] |
-+-----+----------+-----------+---------------------------------------------------+
-|4/- | PVP1 | NV41:NV84 | VP1 microcoded video processor. [see :ref:`pvp1`] |
-+-----+----------+-----------+---------------------------------------------------+
-|4/- | PVP2 | | VP2 video decoding engines: video processor and |
-+-----+----------+ | bitstream processor. Microcoded through embedded |
-|6/- | PBSP | NV84:NV98 | xtensa cores. [see :ref:`pvp2`, :ref:`pbsp`] |
-+-----+----------+ +---------------------------------------------------+
-|5/- | PCRYPT2 | | AES cryptography and copy engine. [:ref:`pcrypt2`]|
-+-----+----------+-----------+---------------------------------------------------+
-|2/2 | PPPP | | VP3 falcon-microcoded video decoding engines: |
-+-----+----------+ | picture, post-processor, video processor, |
-|4/1 | PVDEC | NV98:.... | bitstream processor. [see :ref:`pvld`, |
-+-----+----------+ | :ref:`pvdec`, :ref:`pppp`] |
-|6/3 | PVLD | | |
-+-----+----------+-----------+---------------------------------------------------+
-| | | | falcon-microcoded engine with AES crypto |
-|5/- | PCRYPT3 | NV98:NVA3 | coprocessor. On NVA3+, the crypto powers were |
-| | | | instead merged into PVLD. [see :ref:`pcrypt3`] |
-+-----+----------+-----------+---------------------------------------------------+
-|5/- | PVCOMP | NVAF:NVC0 | falcon-microcoded video compositing engine |
-| | | | [see :ref:`pvcomp`] |
-+-----+----------+-----------+---------------------------------------------------+
-|3/4,5| | | falcon-microcoded engine, meant to copy stuff from|
-| | PCOPY | NVA3:.... | point A to point B. Comes in two copies on NVC0+, |
-| | | | three copies on NVE4+ [see :ref:`pcopy`] |
-+-----+----------+-----------+---------------------------------------------------+
-|-/6 | PVENC | NVE4:.... | falcon-microcoded H.264 encoding engine |
-| | | | [see :ref:`pvenc`] |
-+-----+----------+-----------+---------------------------------------------------+
-
-idx is the FIFO engine id. The first number is the id for pre-nvc0 cards, the
-second is for nvc0+ cards.
+On NV01:NV04, the only engine that PFIFO controls is PGRAPH, the main 2d/3d
+engine of the card. In addition, PFIFO can submit commands to the SOFTWARE
+pseudo-engine, which will trigger an interrupt for every submitted method.
+
+The engines that PFIFO controls on NV04:NVC0 are:
+
+== ========== =========================== ===================================================
+Id Present on Name Description
+== ========== =========================== ===================================================
+0 all SOFTWARE Not really an engine, causes interrupt for each
+ command, can be used to execute driver functions
+ in sync with other commands.
+1 all :ref:`PGRAPH <graph-intro>` Main engine of the card: 2d, 3d, compute.
+2 NV31:NV98 :ref:`PMPEG <pmpeg>` The PFIFO interface to VPE MPEG2 decoding engine.
+ NVA0:NVAA
+3 NV40:NV84 :ref:`PME <pme>` VPE motion estimation engine.
+4 NV41:NV84 :ref:`PVP1 <pvp1>` VPE microcoded vector processor.
+4 VP2 :ref:`PVP2 <pvp2>` xtensa-microcoded vector processor.
+5 VP2 :ref:`PCRYPT2 <pcrypt2>` AES cryptography and copy engine.
+6 VP2 :ref:`PBSP <pbsp>` xtensa-microcoded bitstream processor.
+2 VP3- :ref:`PPPP <pppp>` falcon-based video post-processor.
+4 VP3- :ref:`PVDEC <pvdec>` falcon-based microcoded video decoder.
+5 VP3 :ref:`PCRYPT3 <pcrypt3>` falcon-based AES crypto engine. On VP4, merged into PVLD.
+6 VP3- :ref:`PVLD <pvld>` falcon-based variable length decoder.
+3 NVA3- :ref:`PCOPY <pcopy>` falcon-based memory copy engine.
+5 NVAF:NVC0 :ref:`PVCOMP <pvcomp>` falcon-based video compositing engine.
+== ========== =========================== ===================================================
+
+The engines that PFIFO controls on NVC0- are:
+
+===== ========== =========================== ===================================================
+Id Present on Name Description
+===== ========== =========================== ===================================================
+1f all SOFTWARE Not really an engine, causes interrupt for each
+ command, can be used to execute driver functions
+ in sync with other commands.
+0 all :ref:`PGRAPH <graph-intro>` Main engine of the card: 2d, 3d, compute.
+1 all :ref:`PVDEC <pvdec>` falcon-based microcoded video decoder.
+2 all :ref:`PPPP <pppp>` falcon-based video post-processor.
+3 all :ref:`PVLD <pvld>` falcon-based variable length decoder.
+4,5 NVC0:NVE4 :ref:`PCOPY <pcopy>` falcon-based memory copy engines.
+6 NVE4- :ref:`PVENC <pvenc>` falcon-based H.264 encoding engine.
+4,5.7 NVE4- :ref:`PCOPY <pcopy>` Memory copy engines.
+===== ========== =========================== ===================================================
This file deals only with the user-visible side of the PFIFO. For kernel-side
programming, see :ref:`nv01-pfifo`, :ref:`nv04-pfifo`, :ref:`nv50-pfifo`,
@@ -93,22 +89,22 @@ The PFIFO can be split into roughly 4 pieces:
- PFIFO CACHE: a big queue of commands waiting for execution by
- PFIFO puller: executes the commands, passes them to the proper engine,
or to the driver.
-- PFIFO switcher: ticks out the time slices for the channels and saves/
+- PFIFO switcher: ticks out the time slices for the channels and saves /
restores the state of the channel between PFIFO registers and RAMFC
memory.
A channel consists of the following:
-- channel mode: PIO [NV01:NVC0], DMA [NV04:NVC0], or IB [NV50:NVC0]
-- PFIFO DMA pusher state [DMA and IB channels only] [see :ref:`DMA pusher <dma-pusher>`]
+- channel mode: PIO [NV01:NVC0], DMA [NV04:NVC0], or IB [NV50-]
+- PFIFO :ref:`DMA pusher <fifo-dma-pusher>` state [DMA and IB channels only]
- PFIFO CACHE state: the commands already accepted but not yet executed
-- PFIFO puller state [see :ref:`DMA puller <puller>`]
+- PFIFO :ref:`puller <fifo-puller>` state
- RAMFC: area of VRAM storing the above when channel is not currently active
on PFIFO [not user-visible]
- RAMHT [pre-NVC0 only]: a table of "objects" that the channel can use. The
objects are identified by arbitrary 32-bit handles, and can be DMA objects
- [see :ref:`nv03-dmaobj`, :ref:`nv04-dmaobj`, :ref:`nv50-vm`] or
- engine objects [see :ref:`DMA puller <puller>` and engine documentation]. On pre-NV50
+ [see :ref:`nv03-dmaobj`, :ref:`nv04-dmaobj`, :ref:`nv50-dmaobj`] or
+ engine objects [see :ref:`fifo-puller` and engine documentation]. On pre-NV50
cards, individual objects can be shared between channels.
- vspace [NV50+ only]: A hierarchy of page tables that describes the virtual
memory space visible to engines while executing commands for the channel.
@@ -120,32 +116,29 @@ Channel mode determines the way of submitting commands to the channel. PIO
mode is available on pre-NVC0 cards, and involves poking the methods directly
to the channel control area. It's slow and fragile - everything breaks down
easily when more than one channel is used simultanously. Not recommended. See
-:ref:`pio` for details. On NV01:NV40, all channels support PIO mode. On
-NV40:NV50, only first 32
-channels support PIO mode. On NV50:NVC0
-only channel 0 supports PIO mode.
+:ref:`fifo-pio` for details. On NV01:NV40, all channels support PIO mode. On
+NV40:NV50, only first 32 channels support PIO mode. On NV50:NVC0 only
+channel 0 supports PIO mode.
.. todo:: check PIO channels support on NV40:NV50
-NV01 PFIFO doesn't support any DMA mode. There's apparently a PDMA engine that
-could be DMA command submission, but nobody bothers enough to figure out how
-it works.
+NV01 PFIFO doesn't support any DMA mode.
NV03 PFIFO introduced a hacky DMA mode that requires kernel assistance for
every submitted batch of commands and prevents channel switching while stuff
-is being submitted. See :ref:`nv01-pfifo` for details.
+is being submitted. See :ref:`nv03-pfifo-dma` for details.
NV04 PFIFO greatly enhanced the DMA mode and made it controllable directly
through the channel control area. Thus, commands can now be submitted by
multiple applications simultanously, without coordination with each other
-and without kernel's help. DMA mode is described in :ref:`dma-pusher`.
+and without kernel's help. DMA mode is described in :ref:`fifo-dma-pusher`.
NV50 introduced IB mode. IB mode is a modified version of DMA mode that,
instead of following a single stream of commands from memory, has the ability
to stitch together parts of multiple memory areas into a single command stream
- allowing constructs that submit commands with parameters pulled directly from
memory written by earlier commands. IB mode is described along with DMA mode in
-:ref:`dma-pusher`.
+:ref:`fifo-dma-pusher`.
NVC0 rearchitected the whole PFIFO, made it possible to have up to 3 channels
executing simultanously, and introduced a new DMA packet format.
@@ -179,8 +172,8 @@ packet, or NI if the command was submitted through non-increasing packet. This
information isn't actually used for anything by the card, but it's stored in
the CACHE for certain optimisation when submitting PGRAPH commands.
-Method execution is described in detail in :ref:`DMA puller <puller>` and engine-specific
-documentation.
+Method execution is described in detail in :ref:`DMA puller <fifo-puller>`
+and engine-specific documentation.
Pre-NV11, PFIFO treats everything as little-endian. NV11 introduced big-endian
mode, which affects pushbuffer/IB reads and semaphores. On NV11:NV50 cards,
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