Merge pull request #103 from Echelon9/doc/improve-slcg-registers

rnndb/graph/slcg: Document missing SLCG (Second Level Clock Gating) registers

Author: Echelon9

rnndb/graph/gf100_pgraph/gpc.xml

@@ -145,6 +145,7 @@
 	<array offset="0x880" name="FFB" stride="0x080" length="1">
 		<reg32 offset="0x04" name="PM_MUX_A"/> <!-- or is it? -->
 		<reg32 offset="0x18" name="BLCG"/>
+		<reg32 offset="0x1c" name="SLCG" variants="GK104-"/>
 		<reg32 offset="0x20" name="ELPG0"/>
 		<reg32 offset="0x2c" name="PART_CONFIG">
 			<bitfield low="0" high="3" name="PART_COUNT"/>

rnndb/graph/gf100_pgraph/tpc.xml

@@ -349,6 +349,7 @@
 		</reg32>
 		<reg32 offset="0x20" name="CTX_UNK20" variants="GF100:GK104"/>
 		<reg32 offset="0x24" name="CTX_UNK24" variants="GF100:GK104"/>
+		<reg32 offset="0x24" name="SLCG" variants="GK104-"/>
 		<reg32 offset="0x2c" name="PM_MUX">
 			<bitfield low="0" high="3" name="SEL"/>
 			<bitfield pos="31" name="ENABLE"/>