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Merge pull request #103 from Echelon9/doc/improve-slcg-registers

rnndb/graph/slcg: Document missing SLCG (Second Level Clock Gating) registers
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Echelon9 committed Oct 17, 2017
2 parents 6a23a12 + 9c9ad96 commit 5d96aa18f5e66d77082a389d63ccf77fa5936665
Showing with 2 additions and 0 deletions.
  1. +1 −0 rnndb/graph/gf100_pgraph/gpc.xml
  2. +1 −0 rnndb/graph/gf100_pgraph/tpc.xml
@@ -145,6 +145,7 @@
<array offset="0x880" name="FFB" stride="0x080" length="1">
<reg32 offset="0x04" name="PM_MUX_A"/> <!-- or is it? -->
<reg32 offset="0x18" name="BLCG"/>
<reg32 offset="0x1c" name="SLCG" variants="GK104-"/>
<reg32 offset="0x20" name="ELPG0"/>
<reg32 offset="0x2c" name="PART_CONFIG">
<bitfield low="0" high="3" name="PART_COUNT"/>
@@ -349,6 +349,7 @@
</reg32>
<reg32 offset="0x20" name="CTX_UNK20" variants="GF100:GK104"/>
<reg32 offset="0x24" name="CTX_UNK24" variants="GF100:GK104"/>
<reg32 offset="0x24" name="SLCG" variants="GK104-"/>
<reg32 offset="0x2c" name="PM_MUX">
<bitfield low="0" high="3" name="SEL"/>
<bitfield pos="31" name="ENABLE"/>

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