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demmt: disassemble shaders and macros for nve4:nvf0 cards
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TSCs and TICs are encoded differently, so no support for now.
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@mslusarz
mslusarz committed Jul 15, 2014
1 parent 805e695 commit cc45954
Showing 1 changed file with 101 additions and 45 deletions.
146 changes: 101 additions & 45 deletions rnn/demmt_objects.c
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Expand Up @@ -296,6 +296,58 @@ static struct
struct buffer *tic_buffer;
} nvc0_3d = { 0, NULL };

static int decode_nvc0_3d_tsc_tic(struct pushbuf_decode_state *pstate, int mthd, uint32_t data)
{
if (mthd == 0x155c) // TSC_ADDRESS_HIGH
nvc0_3d.tsc_address = ((uint64_t)data) << 32;
else if (mthd == 0x1560) // TSC_ADDRESS_LOW
{
nvc0_3d.tsc_address |= data;
nvc0_3d.tsc_buffer = find_buffer_by_gpu_address(nvc0_3d.tsc_address);
mmt_debug("tsc address: 0x%08lx, buffer found: %d\n", nvc0_3d.tsc_address, nvc0_3d.tsc_buffer ? 1 : 0);
}
else if (mthd == 0x1574) // TIC_ADDRESS_HIGH
nvc0_3d.tic_address = ((uint64_t)data) << 32;
else if (mthd == 0x1578) // TIC_ADDRESS_LOW
{
nvc0_3d.tic_address |= data;
nvc0_3d.tic_buffer = find_buffer_by_gpu_address(nvc0_3d.tic_address);
mmt_debug("tic address: 0x%08lx, buffer found: %d\n", nvc0_3d.tic_address, nvc0_3d.tic_buffer ? 1 : 0);
}
else if (mthd >= 0x2400 && mthd < 0x2404 + 0x20 * 5)
{
int i;
for (i = 0; i < 5; ++i)
{
if (nvc0_3d.tsc_buffer && mthd == 0x2400 + i * 0x20) // BIND_TSC[i]
{
int j, tsc = (data >> 12) & 0xfff;
mmt_debug("bind tsc[%d]: 0x%08x\n", i, tsc);
uint32_t *tsc_data = (uint32_t *)&nvc0_3d.tsc_buffer->data[32 * tsc];

for (j = 0; j < 8; ++j)
decode_tsc(tsc, j, tsc_data);

break;
}
if (nvc0_3d.tic_buffer && mthd == 0x2404 + i * 0x20) // BIND_TIC[i]
{
int j, tic = (data >> 9) & 0x1ffff;
mmt_debug("bind tic[%d]: 0x%08x\n", i, tic);
uint32_t *tic_data = (uint32_t *)&nvc0_3d.tic_buffer->data[32 * tic];

for (j = 0; j < 8; ++j)
decode_tic(tic, j, tic_data);

break;
}
}
}
else
return 0;
return 1;
}

static void decode_nvc0_3d(struct pushbuf_decode_state *pstate, int mthd, uint32_t data)
{
if (mthd == 0x1608) // CODE_ADDRESS_HIGH
Expand Down Expand Up @@ -339,6 +391,9 @@ static void decode_nvc0_3d(struct pushbuf_decode_state *pstate, int mthd, uint32
isa_nvc0 = ed_getisa("nvc0");
struct varinfo *var = varinfo_new(isa_nvc0->vardata);

if (chipset >= 0xe4)
varinfo_set_variant(var, "nve4");

envydis(isa_nvc0, stdout, nvc0_3d.code_buffer->data + reg->start + 20 * 4, 0,
reg->end - reg->start - 20 * 4, var, 0, NULL, 0, colors);
varinfo_del(var);
Expand Down Expand Up @@ -382,51 +437,8 @@ static void decode_nvc0_3d(struct pushbuf_decode_state *pstate, int mthd, uint32
}
}
}
else if (mthd == 0x155c) // TSC_ADDRESS_HIGH
nvc0_3d.tsc_address = ((uint64_t)data) << 32;
else if (mthd == 0x1560) // TSC_ADDRESS_LOW
{
nvc0_3d.tsc_address |= data;
nvc0_3d.tsc_buffer = find_buffer_by_gpu_address(nvc0_3d.tsc_address);
mmt_debug("tsc address: 0x%08lx, buffer found: %d\n", nvc0_3d.tsc_address, nvc0_3d.tsc_buffer ? 1 : 0);
}
else if (mthd == 0x1574) // TIC_ADDRESS_HIGH
nvc0_3d.tic_address = ((uint64_t)data) << 32;
else if (mthd == 0x1578) // TIC_ADDRESS_LOW
{
nvc0_3d.tic_address |= data;
nvc0_3d.tic_buffer = find_buffer_by_gpu_address(nvc0_3d.tic_address);
mmt_debug("tic address: 0x%08lx, buffer found: %d\n", nvc0_3d.tic_address, nvc0_3d.tic_buffer ? 1 : 0);
}
else if (mthd >= 0x2400 && mthd < 0x2404 + 0x20 * 5)
{
int i;
for (i = 0; i < 5; ++i)
{
if (nvc0_3d.tsc_buffer && mthd == 0x2400 + i * 0x20) // BIND_TSC[i]
{
int j, tsc = (data >> 12) & 0xfff;
mmt_debug("bind tsc[%d]: 0x%08x\n", i, tsc);
uint32_t *tsc_data = (uint32_t *)&nvc0_3d.tsc_buffer->data[32 * tsc];

for (j = 0; j < 8; ++j)
decode_tsc(tsc, j, tsc_data);

break;
}
if (nvc0_3d.tic_buffer && mthd == 0x2404 + i * 0x20) // BIND_TIC[i]
{
int j, tic = (data >> 9) & 0x1ffff;
mmt_debug("bind tic[%d]: 0x%08x\n", i, tic);
uint32_t *tic_data = (uint32_t *)&nvc0_3d.tic_buffer->data[32 * tic];

for (j = 0; j < 8; ++j)
decode_tic(tic, j, tic_data);

break;
}
}
}
else if (chipset < 0xe0 && decode_nvc0_3d_tsc_tic(pstate, mthd, data))
{ }
}

static struct
Expand Down Expand Up @@ -471,6 +483,48 @@ static void decode_nvc0_m2mf(struct pushbuf_decode_state *pstate, int mthd, uint
}
}

static struct
{
uint64_t offset_out;
struct buffer *offset_out_buffer;
int data_offset;
} nve0_p2mf = { 0, NULL, 0 };

static void decode_nve0_p2mf(struct pushbuf_decode_state *pstate, int mthd, uint32_t data)
{
if (mthd == 0x0188) // UPLOAD.DST_ADDRESS_HIGH
{
nve0_p2mf.offset_out = ((uint64_t)data) << 32;
nve0_p2mf.offset_out_buffer = NULL;
}
else if (mthd == 0x018c) // UPLOAD.DST_ADDRESS_LOW
nve0_p2mf.offset_out |= data;
else if (mthd == 0x01b0) // UPLOAD.EXEC
{
int flags_ok = (data & 0x1) == 0x1 ? 1 : 0;
mmt_debug("p2mf exec: 0x%08x linear: %d\n", data, flags_ok);
if (flags_ok)
nve0_p2mf.offset_out_buffer = find_buffer_by_gpu_address(nve0_p2mf.offset_out);

if (!flags_ok || nve0_p2mf.offset_out_buffer == NULL)
{
nve0_p2mf.offset_out = 0;
nve0_p2mf.offset_out_buffer = NULL;
}
if (nve0_p2mf.offset_out_buffer)
nve0_p2mf.data_offset = nve0_p2mf.offset_out - nve0_p2mf.offset_out_buffer->gpu_start;
}
else if (mthd == 0x01b4) // UPLOAD.DATA
{
mmt_debug("p2mf data: 0x%08x\n", data);
if (nve0_p2mf.offset_out_buffer)
{
buffer_register_write(nve0_p2mf.offset_out_buffer, nve0_p2mf.data_offset, 4, &data);
nve0_p2mf.data_offset += 4;
}
}
}

static const struct gpu_object
{
uint32_t class_;
Expand All @@ -488,6 +542,8 @@ objs[] =
{ 0x9097, decode_nvc0_3d },
{ 0x9197, decode_nvc0_3d },
{ 0x9297, decode_nvc0_3d },
{ 0xa040, decode_nve0_p2mf },
{ 0xa097, decode_nvc0_3d },
{ 0, NULL}
};

Expand Down

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