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nva: Add support for non-GPU device types.

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1 parent 3095201 commit d43460646ea1666243637a73737fac4c4073358b @koriakin koriakin committed Feb 16, 2014
Showing with 149 additions and 134 deletions.
  1. +3 −3 hwtest/hwtest.c
  2. +6 −6 hwtest/nv10_tile.c
  3. +8 −8 hwtest/vram.c
  4. +8 −5 include/nva.h
  5. +3 −3 nva/evotiming.c
  6. +58 −59 nva/nva.c
  7. +5 −5 nva/nvacounter.c
  8. +3 −3 nva/nvaevo.c
  9. +4 −4 nva/nvafakebios.c
  10. +11 −11 nva/nvagetbios.c
  11. +17 −4 nva/nvalist.c
  12. +1 −1 nva/nvapeek.c
  13. +1 −1 nva/nvapms.c
  14. +1 −1 nva/nvapoke.c
  15. +2 −2 nva/nvapy.pyx
  16. +1 −1 nva/nvascan.c
  17. +2 −2 nva/nvaspyi2c.c
  18. +7 −7 nva/nvatiming.c
  19. +3 −3 nva/set_timings.c
  20. +4 −4 nva/vbios_mgmt.c
  21. +1 −1 vdpow/vdpow.c
View
6 hwtest/hwtest.c
@@ -79,9 +79,9 @@ int main(int argc, char **argv) {
fprintf (stderr, "No cards found.\n");
return 1;
}
- ctx->chipset = nva_cards[ctx->cnum].chipset.chipset;
- ctx->card_type = nva_cards[ctx->cnum].chipset.card_type;
- if (pci_device_has_kernel_driver(nva_cards[ctx->cnum].pci)) {
+ ctx->chipset = nva_cards[ctx->cnum]->chipset.chipset;
+ ctx->card_type = nva_cards[ctx->cnum]->chipset.card_type;
+ if (pci_device_has_kernel_driver(nva_cards[ctx->cnum]->pci)) {
if (force) {
fprintf(stderr, "WARNING: Kernel driver in use.\n");
} else {
View
12 hwtest/nv10_tile.c
@@ -351,24 +351,24 @@ static int test_comp_size(struct hwtest_ctx *ctx) {
}
static uint32_t comp_seek(int cnum, int part, int addr) {
- if (nva_cards[cnum].chipset.chipset == 0x20) {
+ if (nva_cards[cnum]->chipset.chipset == 0x20) {
nva_wr32(cnum, 0x1000f0, 0x1300000 |
(part << 16) | (addr & 0x1fc0));
return 0x100100 + (addr & 0x3c);
- } else if (nva_cards[cnum].chipset.chipset < 0x30) {
+ } else if (nva_cards[cnum]->chipset.chipset < 0x30) {
nva_wr32(cnum, 0x1000f0, 0x2380000 |
((addr << 6) & 0x40000) |
(part << 16) | (addr & 0xfc0));
return 0x100100 + (addr & 0x3c);
- } else if (nva_cards[cnum].chipset.chipset < 0x35) {
+ } else if (nva_cards[cnum]->chipset.chipset < 0x35) {
nva_wr32(cnum, 0x1000f0, 0x2380000 |
(part << 16) | (addr & 0x7fc0));
return 0x100100 + (addr & 0x3c);
- } else if (nva_cards[cnum].chipset.chipset < 0x36) {
+ } else if (nva_cards[cnum]->chipset.chipset < 0x36) {
nva_wr32(cnum, 0x1000f0, 0x2380000 | (addr & 4) << 16 |
(part << 16) | (addr >> 1 & 0x7fc0));
return 0x100100 + (addr >> 1 & 0x3c);
- } else if (nva_cards[cnum].chipset.chipset < 0x40) {
+ } else if (nva_cards[cnum]->chipset.chipset < 0x40) {
nva_wr32(cnum, 0x1000f0, 0x2380000 | (addr & 0xc) << 15 |
(part << 16) | (addr >> 2 & 0x7fc0));
return 0x100100 + (addr >> 2 & 0x3c);
@@ -396,7 +396,7 @@ void comp_wr32(int cnum, int part, int addr, uint32_t v) {
void clear_comp(int cnum) {
uint32_t size = (nva_rd32(cnum, 0x100320) + 1) / 8;
int i, j;
- for (i = 0; i < get_maxparts(nva_cards[cnum].chipset.chipset); i++) {
+ for (i = 0; i < get_maxparts(nva_cards[cnum]->chipset.chipset); i++) {
for (j = 0; j < size; j += 0x4)
comp_wr32(cnum, i, j, 0);
}
View
16 hwtest/vram.c
@@ -26,11 +26,11 @@
#include "nva.h"
uint32_t vram_rd32(int card, uint64_t addr) {
- if (nva_cards[card].chipset.card_type < 3) {
+ if (nva_cards[card]->chipset.card_type < 3) {
return nva_rd32(card, 0x1000000 + addr);
- } else if (nva_cards[card].chipset.card_type < 0x30) {
- return nva_grd32(nva_cards[card].bar1, addr);
- } else if (nva_cards[card].chipset.card_type < 0x50) {
+ } else if (nva_cards[card]->chipset.card_type < 0x30) {
+ return nva_grd32(nva_cards[card]->bar1, addr);
+ } else if (nva_cards[card]->chipset.card_type < 0x50) {
nva_wr32(card, 0x1570, addr);
return nva_rd32(card, 0x1574);
} else {
@@ -43,11 +43,11 @@ uint32_t vram_rd32(int card, uint64_t addr) {
}
void vram_wr32(int card, uint64_t addr, uint32_t val) {
- if (nva_cards[card].chipset.card_type < 3) {
+ if (nva_cards[card]->chipset.card_type < 3) {
nva_wr32(card, 0x1000000 + addr, val);
- } else if (nva_cards[card].chipset.card_type < 0x30) {
- nva_gwr32(nva_cards[card].bar1, addr, val);
- } else if (nva_cards[card].chipset.card_type < 0x50) {
+ } else if (nva_cards[card]->chipset.card_type < 0x30) {
+ nva_gwr32(nva_cards[card]->bar1, addr, val);
+ } else if (nva_cards[card]->chipset.card_type < 0x50) {
nva_wr32(card, 0x1570, addr);
nva_wr32(card, 0x1574, val);
} else {
View
13 include/nva.h
@@ -29,6 +29,9 @@
#include "nvhw.h"
struct nva_card {
+ enum {
+ NVA_DEVICE_GPU,
+ } type;
struct pci_device *pci;
struct chipset_info chipset;
void *bar0;
@@ -46,7 +49,7 @@ struct nva_card {
};
int nva_init();
-extern struct nva_card *nva_cards;
+extern struct nva_card **nva_cards;
extern int nva_cardsnum;
static inline uint32_t nva_grd32(void *base, uint32_t addr) {
@@ -66,19 +69,19 @@ static inline void nva_gwr8(void *base, uint32_t addr, uint32_t val) {
}
static inline uint32_t nva_rd32(int card, uint32_t addr) {
- return nva_grd32(nva_cards[card].bar0, addr);
+ return nva_grd32(nva_cards[card]->bar0, addr);
}
static inline void nva_wr32(int card, uint32_t addr, uint32_t val) {
- nva_gwr32(nva_cards[card].bar0, addr, val);
+ nva_gwr32(nva_cards[card]->bar0, addr, val);
}
static inline uint32_t nva_rd8(int card, uint32_t addr) {
- return nva_grd8(nva_cards[card].bar0, addr);
+ return nva_grd8(nva_cards[card]->bar0, addr);
}
static inline void nva_wr8(int card, uint32_t addr, uint32_t val) {
- nva_gwr8(nva_cards[card].bar0, addr, val);
+ nva_gwr8(nva_cards[card]->bar0, addr, val);
}
static inline uint32_t nva_mask(int cnum, uint32_t reg, uint32_t mask, uint32_t val)
View
6 nva/evotiming.c
@@ -45,16 +45,16 @@ int evosend (int cnum, int c, int m, int d)
{
uint32_t ctrl;
- if (nva_cards[cnum].chipset.chipset >= 0xd0) {
+ if (nva_cards[cnum]->chipset.chipset >= 0xd0) {
ctrl = nva_rd32(cnum, 0x610700 + (c * 8));
nva_wr32(cnum, 0x610700 + (c * 8), ctrl | 1);
nva_wr32(cnum, 0x610704 + (c * 8), d);
nva_wr32(cnum, 0x610700 + (c * 8), 0x80000001 | m);
while (nva_rd32(cnum, 0x610700 + (c * 8)) & 0x80000000);
nva_wr32(cnum, 0x610700 + (c * 8), ctrl);
} else
- if (nva_cards[cnum].chipset.chipset == 0x50 ||
- nva_cards[cnum].chipset.chipset >= 0x84) {
+ if (nva_cards[cnum]->chipset.chipset == 0x50 ||
+ nva_cards[cnum]->chipset.chipset >= 0x84) {
ctrl = nva_rd32(cnum, 0x610300 + (c * 8));
nva_wr32(cnum, 0x610300 + (c * 8), ctrl | 1);
nva_wr32(cnum, 0x610304 + (c * 8), d);
View
117 nva/nva.c
@@ -29,18 +29,71 @@
#include "nva.h"
#include "util.h"
-struct nva_card *nva_cards = 0;
+struct nva_card **nva_cards = 0;
int nva_cardsnum = 0;
int nva_cardsmax = 0;
int nva_vgaarberr = 0;
-struct pci_id_match nv_match[4] = {
+struct pci_id_match nv_match[] = {
{0x104a, 0x0009, PCI_MATCH_ANY, PCI_MATCH_ANY, 0, 0},
{0x12d2, PCI_MATCH_ANY, PCI_MATCH_ANY, PCI_MATCH_ANY, 0x30000, 0xffff0000},
{0x10de, PCI_MATCH_ANY, PCI_MATCH_ANY, PCI_MATCH_ANY, 0x30000, 0xffff0000},
{0x10de, PCI_MATCH_ANY, PCI_MATCH_ANY, PCI_MATCH_ANY, 0x48000, 0xffffff00},
};
+struct nva_card *nva_init_gpu(struct pci_device *dev) {
+ struct nva_card *card = calloc(sizeof *card, 1);
+ if (!card)
+ return 0;
+ card->type = NVA_DEVICE_GPU;
+ card->pci = dev;
+ int ret = pci_device_map_range(dev, dev->regions[0].base_addr, dev->regions[0].size, PCI_DEV_MAP_FLAG_WRITABLE, &card->bar0);
+ if (ret) {
+ fprintf (stderr, "WARN: Can't probe %04x:%02x:%02x.%x\n", dev->domain, dev->bus, dev->dev, dev->func);
+ free(card);
+ return 0;
+ }
+ card->bar0len = dev->regions[0].size;
+ if (dev->regions[1].size) {
+ card->hasbar1 = 1;
+ card->bar1len = dev->regions[1].size;
+ ret = pci_device_map_range(dev, dev->regions[1].base_addr, dev->regions[1].size, PCI_DEV_MAP_FLAG_WRITABLE, &card->bar1);
+ if (ret) {
+ card->bar1 = 0;
+ }
+ }
+ if (dev->regions[2].size && !dev->regions[2].is_IO) {
+ card->hasbar2 = 1;
+ card->bar2len = dev->regions[2].size;
+ ret = pci_device_map_range(dev, dev->regions[2].base_addr, dev->regions[2].size, PCI_DEV_MAP_FLAG_WRITABLE, &card->bar2);
+ if (ret) {
+ card->bar2 = 0;
+ }
+ } else if (dev->regions[3].size) {
+ card->hasbar2 = 1;
+ card->bar2len = dev->regions[3].size;
+ ret = pci_device_map_range(dev, dev->regions[3].base_addr, dev->regions[3].size, PCI_DEV_MAP_FLAG_WRITABLE, &card->bar2);
+ if (ret) {
+ card->bar2 = 0;
+ }
+ }
+ /* ignore errors */
+ pci_device_map_legacy(dev, 0, 0x100000, PCI_DEV_MAP_FLAG_WRITABLE, &card->rawmem);
+ card->rawio = pci_legacy_open_io(dev, 0, 0x10000);
+ int iobar = -1;
+ if (dev->regions[2].size && dev->regions[2].is_IO)
+ iobar = 2;
+ if (dev->regions[5].size && dev->regions[5].is_IO)
+ iobar = 5;
+ if (iobar != -1) {
+ card->iobar = pci_device_open_io(dev, dev->regions[iobar].base_addr, dev->regions[iobar].size);
+ card->iobarlen = dev->regions[iobar].size;
+ }
+ uint32_t pmc_id = nva_grd32(card->bar0, 0);
+ parse_pmc_id(pmc_id, &card->chipset);
+ return card;
+}
+
int nva_init() {
int ret;
ret = pci_system_init();
@@ -58,71 +111,17 @@ int nva_init() {
struct pci_device *dev;
while ((dev = pci_device_next(it))) {
- struct nva_card c = { 0 };
ret = pci_device_probe(dev);
if (ret) {
fprintf (stderr, "WARN: Can't probe %04x:%02x:%02x.%x\n", dev->domain, dev->bus, dev->dev, dev->func);
continue;
}
pci_device_enable(dev);
- c.pci = dev;
- ADDARRAY(nva_cards, c);
+ struct nva_card *card = nva_init_gpu(dev);
+ if (card)
+ ADDARRAY(nva_cards, card);
}
pci_iterator_destroy(it);
}
-
- for (i = 0; i < nva_cardsnum; i++) {
- struct pci_device *dev;
- dev = nva_cards[i].pci;
- ret = pci_device_map_range(dev, dev->regions[0].base_addr, dev->regions[0].size, PCI_DEV_MAP_FLAG_WRITABLE, &nva_cards[i].bar0);
- if (ret) {
- fprintf (stderr, "WARN: Can't probe %04x:%02x:%02x.%x\n", dev->domain, dev->bus, dev->dev, dev->func);
- int j;
- for (j = i + 1; j < nva_cardsnum; j++) {
- nva_cards[j-1] = nva_cards[j];
- }
- nva_cardsnum--;
- i--;
- continue;
- }
- nva_cards[i].bar0len = dev->regions[0].size;
- if (dev->regions[1].size) {
- nva_cards[i].hasbar1 = 1;
- nva_cards[i].bar1len = dev->regions[1].size;
- ret = pci_device_map_range(dev, dev->regions[1].base_addr, dev->regions[1].size, PCI_DEV_MAP_FLAG_WRITABLE, &nva_cards[i].bar1);
- if (ret) {
- nva_cards[i].bar1 = 0;
- }
- }
- if (dev->regions[2].size && !dev->regions[2].is_IO) {
- nva_cards[i].hasbar2 = 1;
- nva_cards[i].bar2len = dev->regions[2].size;
- ret = pci_device_map_range(dev, dev->regions[2].base_addr, dev->regions[2].size, PCI_DEV_MAP_FLAG_WRITABLE, &nva_cards[i].bar2);
- if (ret) {
- nva_cards[i].bar2 = 0;
- }
- } else if (dev->regions[3].size) {
- nva_cards[i].hasbar2 = 1;
- nva_cards[i].bar2len = dev->regions[3].size;
- ret = pci_device_map_range(dev, dev->regions[3].base_addr, dev->regions[3].size, PCI_DEV_MAP_FLAG_WRITABLE, &nva_cards[i].bar2);
- if (ret) {
- nva_cards[i].bar2 = 0;
- }
- }
- /* ignore errors */
- pci_device_map_legacy(dev, 0, 0x100000, PCI_DEV_MAP_FLAG_WRITABLE, &nva_cards[i].rawmem);
- nva_cards[i].rawio = pci_legacy_open_io(dev, 0, 0x10000);
- int iobar = -1;
- if (dev->regions[2].size && dev->regions[2].is_IO)
- iobar = 2;
- if (dev->regions[5].size && dev->regions[5].is_IO)
- iobar = 5;
- if (iobar != -1) {
- nva_cards[i].iobar = pci_device_open_io(dev, dev->regions[iobar].base_addr, dev->regions[iobar].size);
- nva_cards[i].iobarlen = dev->regions[iobar].size;
- }
- uint32_t pmc_id = nva_rd32(i, 0);
- parse_pmc_id(pmc_id, &nva_cards[i].chipset);
- }
return (nva_cardsnum == 0);
}
View
10 nva/nvacounter.c
@@ -385,7 +385,7 @@ void find_host_mem_read_write(int cnum)
{
uint32_t signals_real[0x100 * 8] = { 0 };
uint32_t signals_real_cycles[0x100 * 8] = { 0 };
- struct pci_device *dev = nva_cards[cnum].pci;
+ struct pci_device *dev = nva_cards[cnum]->pci;
volatile uint8_t *bar1, val;
int ret, i, e;
@@ -566,18 +566,18 @@ int main(int argc, char **argv)
return 1;
}
- if (nva_cards[cnum].chipset.chipset < 0x10 ||
- nva_cards[cnum].chipset.chipset >= 0xc0)
+ if (nva_cards[cnum]->chipset.chipset < 0x10 ||
+ nva_cards[cnum]->chipset.chipset >= 0xc0)
{
fprintf(stderr, "The chipset nv%x isn't currently supported\n",
- nva_cards[cnum].chipset.chipset);
+ nva_cards[cnum]->chipset.chipset);
return 1;
}
/* Init */
nva_wr32(cnum, 0x200, 0xffffffff);
- printf("Chipset nv%x:\n\n", nva_cards[cnum].chipset.chipset);
+ printf("Chipset nv%x:\n\n", nva_cards[cnum]->chipset.chipset);
poll_signals(cnum, signals_ref);
find_counter_noise(cnum);
View
6 nva/nvaevo.c
@@ -58,16 +58,16 @@ int main(int argc, char **argv) {
sscanf (argv[optind + 1], "%x", &m);
sscanf (argv[optind + 2], "%x", &d);
- if (nva_cards[cnum].chipset.chipset >= 0xd0) {
+ if (nva_cards[cnum]->chipset.chipset >= 0xd0) {
ctrl = nva_rd32(cnum, 0x610700 + (c * 8));
nva_wr32(cnum, 0x610700 + (c * 8), ctrl | 1);
nva_wr32(cnum, 0x610704 + (c * 8), d);
nva_wr32(cnum, 0x610700 + (c * 8), 0x80000001 | m);
while (nva_rd32(cnum, 0x610700 + (c * 8)) & 0x80000000);
nva_wr32(cnum, 0x610700 + (c * 8), ctrl);
} else
- if (nva_cards[cnum].chipset.chipset == 0x50 ||
- nva_cards[cnum].chipset.chipset >= 0x84) {
+ if (nva_cards[cnum]->chipset.chipset == 0x50 ||
+ nva_cards[cnum]->chipset.chipset >= 0x84) {
ctrl = nva_rd32(cnum, 0x610300 + (c * 8));
nva_wr32(cnum, 0x610300 + (c * 8), ctrl | 1);
nva_wr32(cnum, 0x610304 + (c * 8), d);
View
8 nva/nvafakebios.c
@@ -66,17 +66,17 @@ int vbios_upload_pramin(int cnum, uint8_t *vbios, int length)
uint32_t ret = EUNK;
int i = 0;
- if (nva_cards[cnum].chipset.chipset < 0x04) {
+ if (nva_cards[cnum]->chipset.chipset < 0x04) {
return ECARD;
}
/* Update the checksum */
chksum(vbios, length);
fprintf(stderr, "Attempt to upload the vbios to card %i (nv%02x) using PRAMIN\n",
- cnum, nva_cards[cnum].chipset.chipset);
+ cnum, nva_cards[cnum]->chipset.chipset);
- if (nva_cards[cnum].chipset.card_type >= 0x50) {
+ if (nva_cards[cnum]->chipset.card_type >= 0x50) {
uint64_t vbios_vram = (uint64_t)(nva_rd32(cnum, 0x619f04) & ~0xff) << 8;
if (!vbios_vram)
@@ -93,7 +93,7 @@ int vbios_upload_pramin(int cnum, uint8_t *vbios, int length)
ret = EOK;
- if (nva_cards[cnum].chipset.card_type >= 0x50)
+ if (nva_cards[cnum]->chipset.card_type >= 0x50)
nva_wr32(cnum, 0x1700, old_bar0_pramin);
return ret;
View
22 nva/nvagetbios.c
@@ -124,20 +124,20 @@ int vbios_extract_prom(int cnum, uint8_t *vbios, int *length)
int i;
fprintf(stderr, "Attempt to extract the vbios from card %i (nv%02x) using PROM\n",
- cnum, nva_cards[cnum].chipset.chipset);
+ cnum, nva_cards[cnum]->chipset.chipset);
int32_t prom_offset;
int32_t prom_size;
int32_t pbus_offset = 0;
- if (nva_cards[cnum].chipset.chipset < 0x03) {
+ if (nva_cards[cnum]->chipset.chipset < 0x03) {
prom_offset = 0x610000;
prom_size = NV01_PROM_SIZE;
- } else if (nva_cards[cnum].chipset.chipset < 0x04) {
+ } else if (nva_cards[cnum]->chipset.chipset < 0x04) {
prom_offset = 0x110000;
prom_size = NV03_PROM_SIZE;
} else {
- if (nva_cards[cnum].chipset.chipset < 0x40)
+ if (nva_cards[cnum]->chipset.chipset < 0x40)
pbus_offset = 0x1800;
else
pbus_offset = 0x88000;
@@ -156,7 +156,7 @@ int vbios_extract_prom(int cnum, uint8_t *vbios, int *length)
vbios[i] = nva_rd32(cnum, prom_offset + (i & ~3)) >> (i & 3) * 8;
ret = nv_ckbios(vbios);
- if (nva_cards[cnum].chipset.chipset >= 0x04) {
+ if (nva_cards[cnum]->chipset.chipset >= 0x04) {
nva_wr32(cnum, pbus_offset + 0x50, pci_cfg_50);
}
*length = prom_size;
@@ -170,16 +170,16 @@ int vbios_extract_pramin(int cnum, uint8_t *vbios, int *length)
uint32_t ret = EUNK;
int i;
- if (nva_cards[cnum].chipset.chipset < 0x04) {
+ if (nva_cards[cnum]->chipset.chipset < 0x04) {
fprintf(stderr, "Card %i (nv%02x) does not support PRAMIN!\n",
- cnum, nva_cards[cnum].chipset.chipset);
+ cnum, nva_cards[cnum]->chipset.chipset);
return ECARD;
}
fprintf(stderr, "Attempt to extract the vbios from card %i (nv%02x) using PRAMIN\n",
- cnum, nva_cards[cnum].chipset.chipset);
+ cnum, nva_cards[cnum]->chipset.chipset);
- if (nva_cards[cnum].chipset.card_type >= 0x50) {
+ if (nva_cards[cnum]->chipset.card_type >= 0x50) {
uint64_t vbios_vram = (uint64_t)(nva_rd32(cnum, 0x619f04) & ~0xff) << 8;
if (!vbios_vram)
@@ -196,7 +196,7 @@ int vbios_extract_pramin(int cnum, uint8_t *vbios, int *length)
vbios[i] = nva_rd8(cnum, NV_PRAMIN_OFFSET + i);
ret = nv_ckbios(vbios);
- if (nva_cards[cnum].chipset.card_type >= 0x50)
+ if (nva_cards[cnum]->chipset.card_type >= 0x50)
nva_wr32(cnum, 0x1700, old_bar0_pramin);
return ret;
@@ -245,7 +245,7 @@ int main(int argc, char **argv) {
}
if (source == NULL) {
- if (nva_cards[cnum].chipset.chipset < 4)
+ if (nva_cards[cnum]->chipset.chipset < 4)
source = "PROM";
else
source = "PRAMIN";
View
21 nva/nvalist.c
@@ -24,17 +24,30 @@
#include "nva.h"
#include <stdio.h>
+#include <stdlib.h>
#include <pciaccess.h>
+void list_gpu(struct nva_card *card) {
+ printf (" %s %08x\n", card->chipset.name, card->chipset.pmc_id);
+}
+
int main() {
if (nva_init()) {
fprintf (stderr, "PCI init failure!\n");
return 1;
}
int i;
- for (i = 0; i < nva_cardsnum; i++)
- printf ("%d: %04x:%02x:%02x.%x %s %08x\n", i,
- nva_cards[i].pci->domain, nva_cards[i].pci->bus, nva_cards[i].pci->dev, nva_cards[i].pci->func,
- nva_cards[i].chipset.name, nva_cards[i].chipset.pmc_id);
+ for (i = 0; i < nva_cardsnum; i++) {
+ struct nva_card *card = nva_cards[i];
+ printf ("%d: %04x:%02x:%02x.%x", i,
+ card->pci->domain, card->pci->bus, card->pci->dev, card->pci->func);
+ switch (card->type) {
+ case NVA_DEVICE_GPU:
+ list_gpu(card);
+ break;
+ default:
+ abort();
+ }
+ }
return 0;
}
View
2 nva/nvapeek.c
@@ -63,7 +63,7 @@ int main(int argc, char **argv) {
fprintf (stderr, "No cards found.\n");
return 1;
}
- rs.card = &nva_cards[rs.cnum];
+ rs.card = nva_cards[rs.cnum];
if (rs.regsz == 0)
rs.regsz = nva_rsdefsz(&rs);
int32_t a, b = rs.regsz, i, j;
View
2 nva/nvapms.c
@@ -78,7 +78,7 @@ pms_launch(int cnum, struct pms_ucode* pms, ptime_t *wall_time)
struct timeval wall_start, wall_end;
int i;
- if (nva_cards[cnum].chipset.chipset < 0x90) {
+ if (nva_cards[cnum]->chipset.chipset < 0x90) {
pms_data = 0x001400;
pms_kick = 0x00000003;
} else {
View
2 nva/nvapoke.c
@@ -64,7 +64,7 @@ int main(int argc, char **argv) {
fprintf (stderr, "No cards found.\n");
return 1;
}
- rs.card = &nva_cards[rs.cnum];
+ rs.card = nva_cards[rs.cnum];
if (rs.regsz == 0)
rs.regsz = nva_rsdefsz(&rs);
uint32_t a, b = rs.regsz;
View
4 nva/nvapy.pyx
@@ -16,7 +16,7 @@ cdef extern from "nva.h":
unsigned bar2len
int hasbar1
int hasbar2
- nva_card *nva_cards
+ nva_card **nva_cards
int nva_cardsnum
int nva_init()
unsigned nva_grd32(void *base, unsigned addr)
@@ -78,4 +78,4 @@ if nva_init():
cards = []
for i in range(nva_cardsnum):
- cards.append(nva_wrapcard(&nva_cards[i]))
+ cards.append(nva_wrapcard(nva_cards[i]))
View
2 nva/nvascan.c
@@ -73,7 +73,7 @@ int main(int argc, char **argv) {
fprintf (stderr, "No cards found.\n");
return 1;
}
- rs.card = &nva_cards[rs.cnum];
+ rs.card = nva_cards[rs.cnum];
if (rs.regsz == 0)
rs.regsz = nva_rsdefsz(&rs);
int32_t a, b = rs.regsz, i;
View
4 nva/nvaspyi2c.c
@@ -254,10 +254,10 @@ int main(int argc, char **argv)
}
sscanf (argv[optind], "%i", &port);
- if (nva_cards[cnum].chipset.chipset < 0xd9 && port >= 4) {
+ if (nva_cards[cnum]->chipset.chipset < 0xd9 && port >= 4) {
printf("Invalid port number: This chipset has 4 ports\n");
return 1;
- } else if (nva_cards[cnum].chipset.chipset >= 0xd9 && port >= 10) {
+ } else if (nva_cards[cnum]->chipset.chipset >= 0xd9 && port >= 10) {
printf("Invalid port number: NVD9+ chipsets have 10 ports\n");
return 1;
}
View
14 nva/nvatiming.c
@@ -112,7 +112,7 @@ void time_pcounter_nv10(unsigned int cnum)
nva_wr32(cnum, 0xa624, 0);
nva_wr32(cnum, 0xa628, 0);
nva_wr32(cnum, 0xa62c, 0);
- if (nva_cards[cnum].chipset.card_type >= 0x20) {
+ if (nva_cards[cnum]->chipset.card_type >= 0x20) {
nva_wr32(cnum, 0xa504, 0);
nva_wr32(cnum, 0xa50c, 0xffff);
nva_wr32(cnum, 0xa514, 0xffff);
@@ -126,7 +126,7 @@ void time_pcounter_nv10(unsigned int cnum)
nva_wr32(cnum, 0xa404, 0xffff);
sleep(1);
printf ("Set 0: %d Hz\n", nva_rd32(cnum, 0xa608));
- if (nva_cards[cnum].chipset.card_type >= 0x20) {
+ if (nva_cards[cnum]->chipset.card_type >= 0x20) {
printf ("Set 1: %u Hz\n", nva_rd32(cnum, 0xa708));
}
}
@@ -240,9 +240,9 @@ void time_pgraph_dispatch_clock(unsigned int card)
ptime_t t_start, t_end;
u32 reg;
- if (nva_cards[card].chipset.card_type == 0x50)
+ if (nva_cards[card]->chipset.card_type == 0x50)
reg = 0x4008f8;
- else if (nva_cards[card].chipset.card_type == 0xc0)
+ else if (nva_cards[card]->chipset.card_type == 0xc0)
reg = 0x4040f4;
else {
printf("pgraph_dispatch_clock is only available on nv50+ chipsets\n");
@@ -288,7 +288,7 @@ u64 crystal_type(unsigned int card)
{
unsigned int crystal, chipset;
- chipset = nva_cards[card].chipset.chipset;
+ chipset = nva_cards[card]->chipset.chipset;
crystal = (nva_rd32(card, 0x101000) & 0x40) >> 6;
@@ -333,7 +333,7 @@ void time_ptimer(unsigned int card)
printf("PTIMER's clock source: 1s = %llu cycles --> frequency = %f MHz\n",
ptimer_default, ptimer_default/1000000.0);
- if (nva_cards[card].chipset.card_type >= 0x40) {
+ if (nva_cards[card]->chipset.card_type >= 0x40) {
/* Calibrate to max frequency */
nva_wr32(card, 0x9200, 0x1);
nva_wr32(card, 0x9210, 0x1);
@@ -516,7 +516,7 @@ int main(int argc, char **argv)
fprintf (stderr, "No cards found.\n");
return 1;
} else
- card = &nva_cards[cnum];
+ card = nva_cards[cnum];
/* activate all the engines */
pmc_enable = nva_rd32(cnum, 0x200);
View
6 nva/set_timings.c
@@ -318,7 +318,7 @@ dump_timings(struct nvamemtiming_conf *conf, FILE* outf,
}
fprintf(outf, "\n");
- if (nva_cards[conf->cnum].chipset.card_type >= 0xc0) {
+ if (nva_cards[conf->cnum]->chipset.card_type >= 0xc0) {
dump_regs(conf->cnum, outf, ref_val3, ref_exist, 0x10f240, 0x20, color && progression > 0);
dump_regs(conf->cnum, outf, ref_val1, ref_exist, 0x10f290, 0xa0, color && progression > 0);
dump_regs(conf->cnum, outf, ref_val4, ref_exist, 0x10f610, 0x10, color && progression > 0);
@@ -440,7 +440,7 @@ deep_dump(struct nvamemtiming_conf *conf)
return 1;
}
- if (nva_cards[conf->cnum].chipset.card_type >= 0xc0)
+ if (nva_cards[conf->cnum]->chipset.card_type >= 0xc0)
timing_value_types = nvc0_timing_value_types;
else
timing_value_types = nv40_timing_value_types;
@@ -498,7 +498,7 @@ shallow_dump(struct nvamemtiming_conf *conf)
return 1;
}
- if (nva_cards[conf->cnum].chipset.card_type >= 0xc0)
+ if (nva_cards[conf->cnum]->chipset.card_type >= 0xc0)
timing_value_types = nvc0_timing_value_types;
else
timing_value_types = nv40_timing_value_types;
View
8 nva/vbios_mgmt.c
@@ -63,17 +63,17 @@ int vbios_upload_pramin(int cnum, uint8_t *vbios, int length)
uint32_t old_bar0_pramin = 0;
int i = 0;
- if (nva_cards[cnum].chipset.chipset < 0x04) {
+ if (nva_cards[cnum]->chipset.chipset < 0x04) {
return ECARD;
}
fprintf(stderr, "Attempt to upload the vbios to card %i (nv%02x) using PRAMIN\n",
- cnum, nva_cards[cnum].chipset.chipset);
+ cnum, nva_cards[cnum]->chipset.chipset);
/* Update the checksum */
chksum(vbios, length);
- if (nva_cards[cnum].chipset.card_type >= 0x50) {
+ if (nva_cards[cnum]->chipset.card_type >= 0x50) {
uint32_t vbios_vram = (nva_rd32(cnum, 0x619f04) & ~0xff) << 8;
if (!vbios_vram)
@@ -88,7 +88,7 @@ int vbios_upload_pramin(int cnum, uint8_t *vbios, int length)
for (i = 0; i < length; i++)
nva_wr8(cnum, NV_PRAMIN_OFFSET + i, vbios[i]);
- if (nva_cards[cnum].chipset.card_type >= 0x50)
+ if (nva_cards[cnum]->chipset.card_type >= 0x50)
nva_wr32(cnum, 0x1700, old_bar0_pramin);
return EOK;
View
2 vdpow/vdpow.c
@@ -223,7 +223,7 @@ static uint32_t mask_pvp(enum vs_type codec, uint32_t idx) {
case 0x688 ... 0x69c:
return 0U;
case 0x440 ... 0x444:
- return nva_cards[cnum].chipset.chipset < 0xd0 ? 0U : ~0U;
+ return nva_cards[cnum]->chipset.chipset < 0xd0 ? 0U : ~0U;
default:
return ~0U;
}

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