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GM117.

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commit deed543e3abf4291829eec8dd73e80414e1448b3 1 parent 83cbf48
@koriakin koriakin authored
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3  hwdocs/chipsets.rst
@@ -692,6 +692,7 @@ pciid pciid /GPC /GPC /GPC /PART
100X+ 0e1a NVF0 GK110 5 3 6 6 4 3 4 2 4 3
100X+ 0e1a NVF1 GK110B 5 3 6 6 4 3 4 2 4 3
128X+ 0e0f NV108 GK208 1 2 1 1 4 3 4 1 2 2
+138X+ 0fbc NV117 GM107 1 5 2 2 4 3 4 2 4 2
===== ===== ===== ====== ==== ==== ===== === ====== ====== ===== ==== ===== ======
.. todo:: it is said that one of the GPCs [0th one] has only one TPC on NVE6
@@ -699,3 +700,5 @@ pciid pciid /GPC /GPC /GPC /PART
.. todo:: what the fuck is NVF1?
.. todo:: GK20A
+
+.. todo:: another design counter available on GM107
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3  nvhw/chipset.c
@@ -145,6 +145,9 @@ int parse_pmc_id(uint32_t pmc_id, struct chipset_info *info) {
case 0xf1: info->name = "GK110B"; break;
case 0x108: info->name = "GK208"; break;
+ /* maxwell */
+ case 0x117: info->name = "GM107"; break;
+
/* wtf */
default: info->name = "???";
}
View
41 rnndb/bus/punits.xml
@@ -41,7 +41,8 @@
<reg32 offset="0x040" name="DESIGN_UNK_ZCULL_PER_GPC_COUNT" variants="NVC1:NVC8 NVD9-"/>
<reg32 offset="0x044" name="DESIGN_PCOPY_COUNT" variants="NVD9-"/>
<reg32 offset="0x048" name="DESIGN_CRTC_COUNT" variants="NVD9-"/>
- <reg32 offset="0x100" name="HW_MISC_DISABLE">
+ <reg32 offset="0x048" name="DESIGN_UNK7_COUNT" variants="NV117-"/>
+ <reg32 offset="0x100" name="HW_MISC_DISABLE" variants="NVC0:NV117">
<bitfield pos="0" name="PDISPLAY_PUNK1C3"/>
<bitfield pos="1" name="PVDEC_PPPP"/>
<bitfield pos="2" name="PVLD"/>
@@ -50,16 +51,16 @@
<bitfield low="8" high="11" name="PCOPY_MASK"/> <!-- 2 bits on NVC0:NVC1, 4 bits on NVC1:NVE4, 3 bits on NVE4- -->
<bitfield low="12" high="17" name="UNK12" variants="NVE4-"/>
</reg32>
- <reg32 offset="0x104" name="HW_GPC_DISABLE_MASK"/>
- <reg32 offset="0x108" name="HW_TPC_DISABLE_MASK" length="8"/>
- <reg32 offset="0x128" name="HW_UNK_ZCULL_DISABLE_MASK" length="8"/>
- <reg32 offset="0x148" name="HW_PART_DISABLE_MASK"/>
- <reg32 offset="0x14c" name="HW_UNK0_DISABLE_MASK"/>
- <reg32 offset="0x150" name="HW_UNK1_DISABLE_MASK" variants="NVC1-"/>
- <reg32 offset="0x154" name="HW_MC_DISABLE_MASK"/>
- <reg32 offset="0x158" name="HW_UNK3_DISABLE_MASK" variants="NVC1-"/>
- <reg32 offset="0x15c" name="HW_CRTC_DISABLE_MASK" variants="NVD9-"/>
- <reg32 offset="0x180" name="SW_MISC_DISABLE">
+ <reg32 offset="0x104" name="HW_GPC_DISABLE_MASK" variants="NVC0:NV117"/>
+ <reg32 offset="0x108" name="HW_TPC_DISABLE_MASK" length="8" variants="NVC0:NV117"/>
+ <reg32 offset="0x128" name="HW_UNK_ZCULL_DISABLE_MASK" length="8" variants="NVC0:NV117"/>
+ <reg32 offset="0x148" name="HW_PART_DISABLE_MASK" variants="NVC0:NV117"/>
+ <reg32 offset="0x14c" name="HW_UNK0_DISABLE_MASK" variants="NVC0:NV117"/>
+ <reg32 offset="0x150" name="HW_UNK1_DISABLE_MASK" variants="NVC1:NV117"/>
+ <reg32 offset="0x154" name="HW_MC_DISABLE_MASK" variants="NVC0:NV117"/>
+ <reg32 offset="0x158" name="HW_UNK3_DISABLE_MASK" variants="NVC1:NV117"/>
+ <reg32 offset="0x15c" name="HW_CRTC_DISABLE_MASK" variants="NVD9:NV117"/>
+ <reg32 offset="0x180" name="SW_MISC_DISABLE" variants="NVC0:NV117">
<bitfield pos="0" name="PDISPLAY_PUNK1C3"/>
<bitfield pos="1" name="PVDEC_PPPP"/>
<bitfield pos="2" name="PVLD"/>
@@ -68,16 +69,16 @@
<bitfield low="8" high="11" name="PCOPY_MASK"/>
<bitfield low="12" high="17" name="UNK12" variants="NVE4-"/>
</reg32>
- <reg32 offset="0x184" name="SW_GPC_DISABLE_MASK"/>
- <reg32 offset="0x188" name="SW_TPC_DISABLE_MASK" length="8"/>
- <reg32 offset="0x1a8" name="SW_UNK_ZCULL_DISABLE_MASK" length="8"/>
- <reg32 offset="0x1c8" name="SW_PART_DISABLE_MASK"/>
+ <reg32 offset="0x184" name="SW_GPC_DISABLE_MASK" variants="NVC0:NV117"/>
+ <reg32 offset="0x188" name="SW_TPC_DISABLE_MASK" length="8" variants="NVC0:NV117"/>
+ <reg32 offset="0x1a8" name="SW_UNK_ZCULL_DISABLE_MASK" length="8" variants="NVC0:NV117"/>
+ <reg32 offset="0x1c8" name="SW_PART_DISABLE_MASK" variants="NVC0:NV117"/>
<!-- the following two are tied to partitions -->
- <reg32 offset="0x1cc" name="SW_UNK0_DISABLE_MASK"/> <!-- needs MISC_DISABLE.UNK4 set to be noticed --> <!-- 1 on NVD9, 0 on NVC1 and NVE4? -->
- <reg32 offset="0x1d0" name="SW_UNK1_DISABLE_MASK" variants="NVC1-"/> <!-- 1 on NVD9, 4 on NVE4, 2 on NVC1 -->
- <reg32 offset="0x1d4" name="SW_MC_DISABLE_MASK"/> <!-- 6 on NVC1??? -->
- <reg32 offset="0x1d8" name="SW_UNK3_DISABLE_MASK" variants="NVC1-"/> <!-- 8 on NVC1, NVD9 and NVE4 -->
- <reg32 offset="0x1dc" name="SW_CRTC_DISABLE_MASK" variants="NVD9-"/>
+ <reg32 offset="0x1cc" name="SW_UNK0_DISABLE_MASK" variants="NVC0:NV117"/> <!-- needs MISC_DISABLE.UNK4 set to be noticed --> <!-- 1 on NVD9, 0 on NVC1 and NVE4? -->
+ <reg32 offset="0x1d0" name="SW_UNK1_DISABLE_MASK" variants="NVC1:NV117"/> <!-- 1 on NVD9, 4 on NVE4, 2 on NVC1 -->
+ <reg32 offset="0x1d4" name="SW_MC_DISABLE_MASK" variants="NVC0:NV117"/> <!-- 6 on NVC1??? -->
+ <reg32 offset="0x1d8" name="SW_UNK3_DISABLE_MASK" variants="NVC1:NV117"/> <!-- 8 on NVC1, NVD9 and NVE4 -->
+ <reg32 offset="0x1dc" name="SW_CRTC_DISABLE_MASK" variants="NVD9:NV117"/>
</array>
</domain>
View
3  rnndb/nvchipsets.xml
@@ -154,6 +154,9 @@
<value value="0x108" name="NV108">
<brief>GK208</brief>
</value>
+ <value value="0x117" name="NV117">
+ <brief>GM107</brief>
+ </value>
</enum>
</database>
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