Computer Architecture Course – University of Tehran (Spring 2025)

This repository contains the projects for the Computer Architecture course at the University of Tehran. The course involved designing and implementing various computer architectures based on the RISC-V instruction set through four main assignments.

Assignments

CA1 – Rat in a Maze

Implemented a basic computer to solve the Rat in a Maze problem through hardware-level design.

CA2 – Single-Cycle RISC-V Processor

Implemented a single-cycle processor based on the RISC-V instruction set supporting key instruction types (R, I, S, B, U, J) and ran a program to find the largest 32-bit number in a 20-element array.

CA3 – Multi-Cycle Stack CPU

Designed an 8-bit multi-cycle CPU using a stack for all operations, with simple 8-bit instructions and a 5-bit address space.

CA4 – Pipelined RISC-V CPU

Implemented a pipelined processor based on the RISC-V instruction set with hazard handling, supporting major instruction types. Ran a program to find the largest 32-bit number in a 20-element array.

Contributors

• Sajjad Hassanpour (sajadhp)
• Erfan Falahati (erfan-f)