esp-hal-common: uart/ESP32: fix get_rx_fifo_count() (#804)

Currently the `get_rx_fifo_count()` is using `fifo_cnt`, which is unreliable
for ESP32, according to the errata:
https://www.espressif.com/sites/default/files/documentation/esp32_errata_en.pdf
section 3.17

This commit is fixing the code for the ESP32 according to the
workaround example.

Main discussion and my debugging results:
https://github.com/esp-rs/esp-hal/discussions/765

Author: manio

CHANGELOG.md

@@ -17,6 +17,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - Add new_no_miso to Spi FullDuplexMode (#794)
 - Add UART support for splitting into TX and RX (#754)
 - Async support for I2S (#801)
+- UART/ESP32: fix calculating FIFO counter with `get_rx_fifo_count()` (#804)
 
 ### Changed
 

esp-hal-common/src/uart.rs

@@ -891,12 +891,46 @@ pub trait Instance {
     }
 
     fn get_rx_fifo_count() -> u16 {
-        Self::register_block()
+        let fifo_cnt: u16 = Self::register_block()
             .status
             .read()
             .rxfifo_cnt()
             .bits()
-            .into()
+            .into();
+
+        // Calculate the real count based on the FIFO read and write offset address:
+        // https://www.espressif.com/sites/default/files/documentation/esp32_errata_en.pdf
+        // section 3.17
+        #[cfg(esp32)]
+        {
+            let rd_addr: u16 = Self::register_block()
+                .mem_rx_status
+                .read()
+                .mem_rx_rd_addr()
+                .bits()
+                .into();
+            let wr_addr: u16 = Self::register_block()
+                .mem_rx_status
+                .read()
+                .mem_rx_wr_addr()
+                .bits()
+                .into();
+
+            if wr_addr > rd_addr {
+                wr_addr - rd_addr
+            } else if wr_addr < rd_addr {
+                (wr_addr + UART_FIFO_SIZE) - rd_addr
+            } else {
+                if fifo_cnt > 0 {
+                    UART_FIFO_SIZE
+                } else {
+                    0
+                }
+            }
+        }
+
+        #[cfg(not(esp32))]
+        fifo_cnt
     }
 
     fn is_tx_idle() -> bool {