diff --git a/svd/esp8266.base.svd b/svd/esp8266.base.svd index 607095d..859c620 100644 --- a/svd/esp8266.base.svd +++ b/svd/esp8266.base.svd @@ -1,7 +1,7 @@ - Espressif + esp8266 1.0 32 @@ -131,7 +131,7 @@ 0x60000300 0 - 0x000003a0 + 0x00000380 registers @@ -265,14 +265,14 @@ The values of the strapping pins. 16 16 - read-write + write-only GPIO_IN_DATA The values of the GPIO pins when the GPIO pin is set as input. 0 16 - read-write + write-only @@ -1038,38 +1038,6 @@ - - GPIO_RTC_CALIB_VALUE - 0x70 - 0: during RTC-clock-calibration; 1: RTC-clock-calibration is done - 32 - 0x00000000 - - - RTC_CALIB_RDY - 0: during RTC-clock-calibration; 1: RTC-clock-calibration is done - 31 - 1 - read-write - - - RTC_CALIB_RDY_REAL - 0: during RTC-clock-calibration; 1: RTC-clock-calibration is done - 30 - 1 - read-write - - - RTC_CALIB_VALUE - The cycle number of clk_xtal (crystal clock) for the RTC_PERIOD_NUM cycles of - RTC-clock - - 0 - 20 - read-write - - - @@ -3089,7 +3057,7 @@ 0x60000200 0 - 0x00000400 + 0x000003e0 registers @@ -3827,25 +3795,6 @@ - - SPI_EXT3 - 0xfc - This register is for two SPI masters to share the same cs, clock and data signals. - - 32 - 0x00000000 - - - reg_int_hold_ena - This register is for two SPI masters to share the same cs, clock and data - signals. - - 0 - 2 - read-write - - - SPI_W0 0x40 @@ -4109,7 +4058,7 @@ 0x60000600 0 - 0x00000120 + 0x00000100 registers @@ -4264,22 +4213,6 @@ - - FRC2_ALARM - 0x30 - the alarm value for the counter - 32 - 0x00000000 - - - frc2_alarm - the alarm value for the counter - 0 - 32 - read-write - - - @@ -4287,7 +4220,7 @@ 0x60000000 0 - 0x000001e0 + 0x000001c0 registers @@ -4947,21 +4880,6 @@ - - UART_ID - 0x7c - UART_ID - 32 - 0x00000000 - - - uart_id - 0 - 32 - read-write - - - @@ -4969,7 +4887,7 @@ 0x60000f00 0 - 0x000001e0 + 0x000001c0 registers @@ -5629,21 +5547,6 @@ - - UART_ID - 0x7c - UART_ID - 32 - 0x00000000 - - - uart_id - 0 - 32 - read-write - - -