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xbox: initial skeleton!

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espes committed Oct 20, 2012
1 parent 8b4a3df commit d823f5802e7c4c84163aea8b4d924044951c705e
Showing with 2,181 additions and 6 deletions.
  1. +132 −0 hw/acpi_mcpx.c
  2. +36 −0 hw/acpi_mcpx.h
  3. +206 −0 hw/amd_smbus.c
  4. +21 −0 hw/amd_smbus.h
  5. +2 −0 hw/i386/Makefile.objs
  6. +569 −0 hw/nv2a.c
  7. +27 −0 hw/nv2a.h
  8. +11 −0 hw/pci_ids.h
  9. +7 −0 hw/smbus.h
  10. +86 −0 hw/smbus_adm1032.c
  11. +127 −0 hw/smbus_cx25871.c
  12. +13 −6 hw/smbus_eeprom.c
  13. +183 −0 hw/smbus_pic16lc.c
  14. +276 −0 hw/xbox.c
  15. +404 −0 hw/xbox_pci.c
  16. +81 −0 hw/xbox_pci.h
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/*
* ACPI implementation
*
* Copyright (c) 2006 Fabrice Bellard
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License version 2 as published by the Free Software Foundation.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>
*
* Contributions after 2012-01-13 are licensed under the terms of the
* GNU GPL, version 2 or (at your option) any later version.
*/
/*
* Copyright (C) 2012 espes
*
* Based on acpi.c, acpi_ich9.c, acpi_piix4.c
*/
#include "hw.h"
#include "pc.h"
#include "pci.h"
#include "qemu-timer.h"
#include "sysemu.h"
#include "acpi.h"
#include "acpi_mcpx.h"
#define DEBUG
#ifdef DEBUG
# define MCPX_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
#else
# define MCPX_DPRINTF(format, ...) do { } while (0)
#endif
static void mcpx_pm_update_sci_gn(ACPIREGS *regs)
{
MCPX_PMRegs *pm = container_of(regs, MCPX_PMRegs, acpi_regs);
//pm_update_sci(pm);
}
#define MCPX_PMIO_PM1_STS 0x0
#define MCPX_PMIO_PM1_EN 0x2
#define MCPX_PMIO_PM1_CNT 0x4
#define MCPX_PMIO_PM_TMR 0x8
static void mcpx_pm_ioport_write(IORange *ioport, uint64_t addr, unsigned width,
uint64_t val)
{
MCPX_PMRegs *pm = container_of(ioport, MCPX_PMRegs, ioport);
switch (addr) {
case MCPX_PMIO_PM1_STS:
acpi_pm1_evt_write_sts(&pm->acpi_regs, val);
//pm_update_sci(pm);
break;
case MCPX_PMIO_PM1_EN:
pm->acpi_regs.pm1.evt.en = val;
//pm_update_sci(pm);
break;
case MCPX_PMIO_PM1_CNT:
acpi_pm1_cnt_write(&pm->acpi_regs, val, 0);
break;
default:
break;
}
MCPX_DPRINTF("PM: write port=0x%04x val=0x%04x\n",
(unsigned int)addr, (unsigned int)val);
}
static void mcpx_pm_ioport_read(IORange *ioport, uint64_t addr, unsigned width,
uint64_t *data)
{
MCPX_PMRegs *pm = container_of(ioport, MCPX_PMRegs, ioport);
uint32_t val;
switch (addr) {
case MCPX_PMIO_PM1_STS:
val = acpi_pm1_evt_get_sts(&pm->acpi_regs);
break;
case MCPX_PMIO_PM1_EN:
val = pm->acpi_regs.pm1.evt.en;
break;
case MCPX_PMIO_PM1_CNT:
val = pm->acpi_regs.pm1.cnt.cnt;
break;
case MCPX_PMIO_PM_TMR:
val = acpi_pm_tmr_get(&pm->acpi_regs);
break;
default:
val = 0;
break;
}
MCPX_DPRINTF("PM: read port=0x%04x val=0x%04x\n",
(unsigned int)addr, (unsigned int)val);
*data = val;
}
static const IORangeOps mcpx_iorange_ops = {
.read = mcpx_pm_ioport_read,
.write = mcpx_pm_ioport_write,
};
void mcpx_pm_iospace_update(MCPX_PMRegs *pm, uint32_t pm_io_base) {
MCPX_DPRINTF("PM: iospace update to 0x%x\n", pm_io_base);
//Disabled when 0
if (pm_io_base != 0) {
iorange_init(&pm->ioport, &mcpx_iorange_ops, pm_io_base, 256);
ioport_register(&pm->ioport);
}
}
void mcpx_pm_init(MCPX_PMRegs *pm/*, qemu_irq sci_irq*/) {
acpi_pm_tmr_init(&pm->acpi_regs, mcpx_pm_update_sci_gn);
acpi_pm1_cnt_init(&pm->acpi_regs);
//acpi_gpe_init(&pm->acpi_regs, ICH9_PMIO_GPE0_LEN);
//pm->irq = sci_irq;
}
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@@ -0,0 +1,36 @@
/*
* QEMU MCPX PM Emulation
*
* Copyright (c) 2012 espes
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>
*/
#ifndef HW_ACPI_MCPX_H
#define HW_ACPI_MCPX_H
#include "acpi.h"
typedef struct MCPX_PMRegs {
IORange ioport;
ACPIREGS acpi_regs;
qemu_irq irq;
} MCPX_PMRegs;
void mcpx_pm_init(MCPX_PMRegs *pm /*, qemu_irq sci_irq*/);
void mcpx_pm_iospace_update(MCPX_PMRegs *pm, uint32_t pm_io_base);
#endif
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@@ -0,0 +1,206 @@
#include "hw.h"
#include "pc.h"
#include "amd_smbus.h"
#include "smbus.h"
/* AMD756 SMBus address offsets */
#define SMB_ADDR_OFFSET 0xE0
#define SMB_IOSIZE 16
#define SMB_GLOBAL_STATUS 0x0
#define SMB_GLOBAL_ENABLE 0x2
#define SMB_HOST_ADDRESS 0x4
#define SMB_HOST_DATA 0x6
#define SMB_HOST_COMMAND 0x8
#define SMB_HOST_BLOCK_DATA 0x9
#define SMB_HAS_DATA 0xA
#define SMB_HAS_DEVICE_ADDRESS 0xC
#define SMB_HAS_HOST_ADDRESS 0xE
#define SMB_SNOOP_ADDRESS 0xF
/* AMD756 constants */
#define AMD756_QUICK 0x00
#define AMD756_BYTE 0x01
#define AMD756_BYTE_DATA 0x02
#define AMD756_WORD_DATA 0x03
#define AMD756_PROCESS_CALL 0x04
#define AMD756_BLOCK_DATA 0x05
/*
SMBUS event = I/O 28-29 bit 11
see E0 for the status bits and enabled in E2
*/
#define GS_ABRT_STS (1 << 0)
#define GS_COL_STS (1 << 1)
#define GS_PRERR_STS (1 << 2)
#define GS_HST_STS (1 << 3)
#define GS_HCYC_STS (1 << 4)
#define GS_TO_STS (1 << 5)
#define GS_SMB_STS (1 << 11)
#define GS_CLEAR_STS (GS_ABRT_STS | GS_COL_STS | GS_PRERR_STS | \
GS_HCYC_STS | GS_TO_STS )
#define GE_CYC_TYPE_MASK (7)
#define GE_HOST_STC (1 << 3)
#define GE_ABORT (1 << 5)
#define DEBUG
#ifdef DEBUG
# define SMBUS_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
#else
# define SMBUS_DPRINTF(format, ...) do { } while (0)
#endif
static void amd756_smb_transaction(AMD756SMBus *s)
{
uint8_t prot = s->smb_ctl & GE_CYC_TYPE_MASK;
uint8_t read = s->smb_addr & 0x01;
uint8_t cmd = s->smb_cmd;
uint8_t addr = (s->smb_addr >> 1) & 0x7f;
i2c_bus *bus = s->smbus;
SMBUS_DPRINTF("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
switch(prot) {
case AMD756_QUICK:
smbus_quick_command(bus, addr, read);
break;
case AMD756_BYTE:
if (read) {
s->smb_data0 = smbus_receive_byte(bus, addr);
} else {
smbus_send_byte(bus, addr, cmd);
}
break;
case AMD756_BYTE_DATA:
if (read) {
s->smb_data0 = smbus_read_byte(bus, addr, cmd);
} else {
smbus_write_byte(bus, addr, cmd, s->smb_data0);
}
break;
case AMD756_WORD_DATA:
if (read) {
uint16_t val;
val = smbus_read_word(bus, addr, cmd);
s->smb_data0 = val;
//s->smb_data1 = val >> 8;
} else {
smbus_write_word(bus, addr, cmd, s->smb_data0);
}
break;
case AMD756_BLOCK_DATA:
if (read) {
s->smb_data0 = smbus_read_block(bus, addr, cmd, s->smb_data);
} else {
smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0);
}
break;
default:
goto error;
}
s->smb_stat |= GS_HCYC_STS;
return;
error:
s->smb_stat |= GS_PRERR_STS;
}
void amd756_smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
{
AMD756SMBus *s = opaque;
addr &= 0x3f;
SMBUS_DPRINTF("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
switch(addr) {
case SMB_GLOBAL_STATUS:
//s->smb_stat = 0;
if (val & GS_CLEAR_STS) {
s->smb_stat = 0;
s->smb_index = 0;
} else if (val & GS_HCYC_STS) {
s->smb_stat = GS_HCYC_STS;
s->smb_index = 0;
} else {
s->smb_stat = GS_HCYC_STS;
s->smb_index = 0;
}
break;
case SMB_GLOBAL_ENABLE:
s->smb_ctl = val;
if (val & GE_ABORT)
s->smb_stat |= GS_ABRT_STS;
if (val & GE_HOST_STC)
amd756_smb_transaction(s);
break;
case SMB_HOST_COMMAND:
s->smb_cmd = val;
break;
case SMB_HOST_ADDRESS:
s->smb_addr = val;
break;
case SMB_HOST_DATA:
s->smb_data0 = val;
break;
/*case SMBHSTDAT1:
s->smb_data1 = val;
break;*/
case SMB_HOST_BLOCK_DATA:
s->smb_data[s->smb_index++] = val;
if (s->smb_index > 31)
s->smb_index = 0;
break;
default:
break;
}
}
uint32_t amd756_smb_ioport_readb(void *opaque, uint32_t addr)
{
AMD756SMBus *s = opaque;
uint32_t val;
addr &= 0x3f;
switch(addr) {
case SMB_GLOBAL_STATUS:
val = s->smb_stat;
break;
case SMB_GLOBAL_ENABLE:
//s->smb_index = 0;
val = s->smb_ctl & 0x1f;
break;
case SMB_HOST_COMMAND:
val = s->smb_cmd;
break;
case SMB_HOST_ADDRESS:
val = s->smb_addr;
break;
case SMB_HOST_DATA:
val = s->smb_data0;
break;
/*case SMBHSTDAT1:
val = s->smb_data1;
break;*/
case SMB_HOST_BLOCK_DATA:
val = s->smb_data[s->smb_index++];
if (s->smb_index > 31)
s->smb_index = 0;
break;
default:
val = 0;
break;
}
SMBUS_DPRINTF("SMB readb port=0x%04x val=0x%02x\n", addr, val);
return val;
}
void amd756_smbus_init(DeviceState *parent, AMD756SMBus *smb)
{
smb->smbus = i2c_init_bus(parent, "i2c");
smb->smb_stat = 0;
}
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